LTC3810IUH-5-TR [Linear]
60V Current Mode Synchronous Switching Regulator Controller; 60V电流模式同步开关稳压控制器型号: | LTC3810IUH-5-TR |
厂家: | Linear |
描述: | 60V Current Mode Synchronous Switching Regulator Controller |
文件: | 总36页 (文件大小:1400K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3810-5
60V Current Mode
Synchronous Switching
Regulator Controller
FEATURES
DESCRIPTION
n
High Voltage Operation: Up to 60V
The LTC®3810-5 is a synchronous step-down switching
regulator controller that can directly step-down voltages
from up to 60V, making it ideal for telecom and automo-
tive applications. The LTC3810-5 uses a constant on-time
valley current control architecture to deliver very low duty
cycles with accurate cycle-by-cycle current limit, without
requiring a sense resistor.
n
Large 1Ω Gate Drivers
n
No Current Sense Resistor Required
n
Dual N-Channel MOSFET Synchronous Drive
n
Extremely Fast Transient Response
0.5% 0.8V Voltage Reference
n
n
Programmable Output Voltage Tracking/Soft-Start
n
Generates 5.5V Driver Supply from Input Supply
A precise internal reference provides 0.5% DC accuracy. A
highbandwidth(25MHz)erroramplifierprovidesveryfast
line and load transient response. Large 1Ω gate drivers
allow the LTC3810-5 to drive multiple MOSFETs for higher
current applications. The operating frequency is selected
by an external resistor and is compensated for variations
n
Synchronizable to External Clock
n
Selectable Pulse Skip Mode Operation
n
Power Good Output Voltage Monitor
n
Adjustable On-Time/Frequency: t
< 100ns
ON(MIN)
n
n
n
n
Adjustable Cycle-by-Cycle Current Limit
Programmable Undervoltage Lockout
Output Overvoltage Protection
in V and can also be synchronized to an external clock
IN
for switching-noise sensitive applications. A shutdown
pin allows the LTC3810-5 to be turned off, reducing the
supply current to 240μA.
Thermally Enhanced 32-Pin QFN Package
APPLICATIONS
Integrated bias control generates gate drive power from
the input supply during start-up or when an output short-
circuit occurs, with the addition of a small external SOT23
MOSFET. When in regulation, power is derived from the
output for higher efficiency.
n
48V Telecom and Base Station Power Supplies
n
Networking Equipment, Servers
n
Automotive and Industrial Control Systems
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 5481178, 5847554, 6304066, 6476589, 6580258, 6677210, 6774611.
TYPICAL APPLICATION
High Efficiency High Voltage Step-Down Converter
Efficiency vs Load Current
V
100
IN
13V TO 60V
+
274k
100k
22μF
V
V
= 24V
= 42V
IN
IN
I
ON
NDRV
ZXMN10A07F
95
90
85
PGOOD
BOOST
LTC3810-5
V
RNG
Si7450DP
TG
10μH
0.1μF
V
MODE/SYNC
SS/TRACK
SHDN
OUT
SW
1000pF
12V/6A
EXTV
DRV
INTV
CC
CC
14k
CC
+
+
MBR1100
270μF
0
2
3
4
5
6
1
SENSE
I
TH
5pF
LOAD CURRENT (A)
200k
Si7450DP
BG
38105 TA01b
V
FB
–
SENSE
BGRTN
47pF
SGND
1μF
1k
38105 TA01
38105fc
1
LTC3810-5
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Supply Voltages
INTV , DRV ....................................... –0.3V to 14V
CC
CC
(DRV – BGRTN), (BOOST – SW) ........ –0.3V to 14V
CC
32 31 30 29 28 27 26 25
BOOST (Continuous) ............................. –0.3V to 85V
BOOST (≤400ms) .................................. –0.3V to 95V
BGRTN........................................................ –5V to 0V
+
–
NC
1
2
3
4
5
6
7
8
24 SENSE
23 NC
V
ON
V
NC
NC
22
21
RNG
EXTV .................................................. –0.3V to 15V
CC
PGOOD
33
(EXTV – INTV ).................................. –12V to 12V
MODE/SYNC
20 SENSE
BGRTN
CC
CC
I
TH
19
(NDRV – INTV ) Voltage........................... –0.3V to 10V
CC
+
V
18 BG
FB
SW, SENSE Voltage (Continuous)................ –1V to 70V
PLL/LPF
17 DRV
+
CC
SW, SENSE Voltage (400ms)....................... –1V to 80V
9
10 11 12 13 14 15 16
I
I
Voltage (Continuous) ........................... –0.3V to 70V
Voltage (400ms) .................................. –0.3V to 80V
ON
ON
SS/TRACK Voltage ....................................... –0.3V to 5V
PGOOD Voltage............................................ –0.3V to 7V
RNG ON
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
V
, V , MODE/SYNC, SHDN,
T
= 125°C, θ = 34°C/W
JA
JMAX
EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB
UVIN Voltages............................................ –0.3V to 14V
PLL/LPF, FB Voltages................................. –0.3V to 2.7V
TG, BG, INTV , EXTV RMS Currents.................50mA
CC
CC
Operating Temperature Range (Note 2)
LTC3810E-5 ......................................... –40°C to 85°C
LTC3810I-5 ........................................ –40°C to 125°C
Junction Temperature (Notes 3, 7)........................ 125°C
Storage Temperature Range................... –65°C to 125°C
ORDER INFORMATION
LEAD FREE FINISH
LTC3810EUH-5#PBF
LTC3810IUH-5#PBF
LEAD BASED FINISH
LTC3810EUH-5
TAPE AND REEL
PART MARKING*
38105
38105
PART MARKING
38105
38105
PACKAGE DESCRIPTION
32-Lead (5mm × 5mm) Plastic QFN
32-Lead (5mm × 5mm) Plastic QFN
PACKAGE DESCRIPTION
32-Lead (5mm × 5mm) Plastic QFN
32-Lead (5mm × 5mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 85°C
–40°C to 125°C
TEMPERATURE RANGE
–40°C to 85°C
–40°C to 125°C
LTC3810EUH-5#TRPBF
LTC3810IUH-5#TRPBF
TAPE AND REEL
LTC3810EUH-5#TR
LTC3810IUH-5#TR
LTC3810IUH-5
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
38105fc
2
LTC3810-5
ELECTRICAL CHARACTERISTICS
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, INTVCC = DRVCC = VBOOST = VON = VRNG = SHDN = UVIN = VEXTVCC = VNDRV
–
+
= 5V, VMODE/SYNC = VSENSE = VSENSE = VBGRTN = VSW = 0V, unless otherwise specified.
SYMBOL
PARAMETER
INTV Supply Voltage
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
l
INTV
4.35
14
V
CC
CC
I
Q
INTV Supply Current
SHDN > 1.5V (Notes 4, 5)
SHDN = 0V
3
240
6
600
mA
μA
CC
INTV Shutdown Current
CC
I
BOOST Supply Current
SHDN > 1.5V (Note 5)
SHDN = 0V
270
0
400
5
μA
μA
BOOST
V
Feedback Voltage
(Note 4)
0.796
0.794
0.792
0.792
0.800
0.800
0.800
0.800
0.804
0.806
0.806
0.808
V
V
V
V
FB
l
l
l
0°C to 85°C
–40°C to 85°C
–40°C to 125°C (I-Grade)
l
ΔV
Feedback Voltage Line Regulation
Maximum Current Sense Threshold
5V < INTV < 14V (Note 4)
0.002
0.02
%/V
FB,LINE
CC
V
V
RNG
V
RNG
V
RNG
= 2V, V = 0.76V
256
70
170
320
95
215
384
120
260
mV
mV
mV
SENSE(MAX)
FB
= 0V, V = 0.76V
FB
= INTV , V = 0.76V
CC FB
V
Minimum Current Sense Threshold
V
RNG
V
RNG
V
RNG
= 2V, V = 0.84V
–300
–85
–200
mV
mV
mV
SENSE(MIN)
FB
= 0V, V = 0.84V
FB
= INTV , V = 0.84V
CC FB
I
Feedback Current
V
= 0.8V
20
100
25
150
nA
dB
VFB
FB
A
(EA)
Error Amplifier DC Open Loop Gain
65
VOL
f
Error Amp Unity-Gain Crossover
Frequency
(Note 6)
MHz
U
V
MODE/SYNC Threshold
MODE/SYNC Current
V
Rising
0.75
1.2
0.8
0
0.85
V
μA
V
MODE/SYNC
MODE/SYNC
I
MODE/SYNC = 5V
1
2
1
MODE/SYNC
V
Shutdown Threshold
1.5
0
SHDN
SHDN
I
SHDN Pin Input Current
UVIN Undervoltage Lockout
μA
l
l
V
UVIN Rising
UVIN Falling
Hysteresis
0.86
0.78
0.07
0.89
0.80
0.10
0.92
0.82
0.12
V
V
V
UVIN
V
INTV Undervoltage Lockout
VCCUV
CC
l
l
l
Linear Regulator Mode
External Supply Mode
Trickle-Charge Mode
INTV Rising, I
= 100μA
4.05
4.05
8.70
4.2
4.2
9
4.35
4.35
9.30
V
V
V
V
CC
NDRV
INTV Rising, NDRV = INTV = EXTV
CC
CC
CC
CC
INTV Rising, NDRV = INTV , EXTV = 0
CC
CC
INTV Falling
3.7
CC
Oscillator and Phase-Locked Loop
t
ON
On-Time
I
I
= 100μA
= 300μA
1.55
515
1.85
605
2.15
695
μs
ns
ON
ON
t
t
t
Minimum On-Time
Minimum Off-Time
I
= 2000μA
100
350
ns
ns
ON(MIN)
OFF(MIN)
ON(PLL)
ON
250
t
Modulation Range by PLL
ON
Down Modulation
Up Modulation
I
ON
I
ON
= 100μA, V
= 100μA, V
= 0.6V
= 1.8V
2.2
0.6
3.6
1.2
5
1.8
μs
μs
PLL/LPF
PLL/LPF
I
Phase Detector Output Current
Sinking Capability
Sourcing Capability
PLL/LPF
f
f
< f
> f
15
–25
μA
μA
PLLIN
PLLIN
SW
SW
Driver
I
BG Driver Peak Source Current
V
= 0V
0.7
0.7
1
1
1
1
A
ꢀ
A
BG,PEAK
BG
R
BG Driver Pull-Down R
1.5
1.5
BG,SINK
TG,PEAK
DS(ON)
I
TG Driver Peak Source Current
TG Driver Pull-Down R
V
– V = 0
TG SW
R
ꢀ
TG,SINK
DS(ON)
38105fc
3
LTC3810-5
ELECTRICAL CHARACTERISTICS
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, INTVCC = DRVCC = VBOOST = VON = VRNG = SHDN = UVIN = VEXTVCC = VNDRV
–
+
= 5V, VMODE/SYNC = VSENSE = VSENSE = VBGRTN = VSW = 0V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PGOOD Output
ΔV
PGOOD Upper Threshold
PGOOD Lower Threshold
V
V
Rising
Falling
7.5
–7.5
10
–10
12.5
–12.5
%
%
FBOV
FB
FB
ΔV
PGOOD Hysterisis
PGOOD Low Voltage
PGOOD Leakage Current
PGOOD Delay
V
Returning
1.5
0.3
0
3
0.6
2
%
V
FB,HYST
FB
V
I
= 5mA
= 5V
PGOOD
PGOOD
I
V
V
μA
μs
PGOOD
PGOOD
PG Delay
Falling
120
FB
Tracking
I
SS/TRACK Source Current
Feedback Voltage at Tracking
V
> 0.5V
SS/TRACK
0.7
1.4
2.5
μA
SS/TRACK
V
V
= 0V, I = 1.2V (Note 4)
–0.018
0.5
V
V
FB,TRACK
TRACK
TH
V
= 0.5V, I = 1.2V (Note 4)
0.48
0.52
TRACK
TH
V
CC
Regulators
V
EXTV Switchover Voltage
CC
EXTVCC
l
EXTV Rising
4.45
0.1
4.7
V
V
CC
EXTV Hysterisis
0.25
0.4
5.8
CC
V
INTV Voltage from EXTV
6V < V < 15V
EXTVCC
5.2
5.5
75
V
mV
%
INTVCC,1
CC
CC
ΔV
ΔV
V
- V
at Dropout
I
I
= 20mA, V = 5V
EXTVCC
150
EXTVCC,1
LOADREG,1
INTVCC,2
EXTVCC
INTVCC
CC
CC
INTV Load Regulation from EXTV
= 0mA to 20mA, V = 10V
EXTVCC
0.01
5.5
CC
CC
V
INTV Voltage from NDRV Regulator
Linear Regulator in Operation
= 0mA to 20mA, V = 0
5.2
5.8
V
CC
ΔV
INTV Load Regulation from NDRV
I
CC
0.01
40
%
LOADREG,2
CC
EXTVCC
I
I
Current into NDRV Pin
V
NDRV
– V = 3V
INTVCC
20
60
μA
μA
NDRV
NDRVTO
Linear Regulator Timeout Enable
Threshold
210
270
350
V
Maximum Supply Voltage
Trickle Charger Shunt Regulator
Trickle Charger Shunt Regulator,
15
V
CCSR
I
Maximum Current into NDRV/INTV
10
mA
CCSR
CC
INTV ≤ 16.7V (Note 8)
CC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The LTC3810-5 is tested in a feedback loop that servos V to the
FB
reference voltage with the I pin forced to a voltage between 1V and 2V.
TH
Note 5: The dynamic input supply current is higher due to the power
MOSFET gate charging being delivered at the switching frequency
Note 2: The LTC3810E-5 is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3810I-5 is guaranteed to meet
performance specifications over the full –40°C to 125°C operating
temperature range.
(Q • f ).
G OSC
Note 6: Guaranteed by design. Not subject to test.
Note 7: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
D
Note 8: I is the sum of current into NDRV and INTV
.
CC
CC
LTC3810-5: T = T + (P • 34°C/W)
J
A
D
PARAMETER
Maximum V
LTC3810
100V
LTC3810-5
60V
LTC3812-5
60V
IN
MOSFET Gate Drive
6.35V to 14V
6.2V
4.5V to 14V
4.2V
4.5V to 14V
4.2V
+
INTV UV
CC
–
INTV UV
6V
4V
4V
CC
38105fc
4
LTC3810-5
TYPICAL PERFORMANCE CHARACTERISTICS
Short-Circuit/
Fault Timeout Operation
Load Transient Response
Start-Up
INTV
V
CC
OUT
V
5V/DIV
OUT
10V/DIV
INTV
100mV/DIV
CC
V
OUT
SS/TRACK
4V/DIV
5V/DIV
V
IN
50V/DIV
I
I
OUT
L
I
5A/DIV
L
5A/DIV
5A/DIV
38105 G03
38105 G01
38105 G02
10ms/DIV
50μs/DIV
500μs/DIV
V
= 48V
SHORT
V
= 48V
V
I
= 48V
= 1A
IN
IN
IN
LOAD
MODE/SYNC = 0V
R
= 0.1Ω
0A TO 5A LOADSTEP
FRONT PAGE CIRCUIT
FRONT PAGE CIRCUIT
FRONT PAGE CIRCUIT
Short-Circuit/
Foldback Operation
Tracking
Pulse Skip Mode Operation
V
OUT
5V/DIV
V
V
OUT
OUT
SS/TRACK
100mV/DIV
5V/DIV
V
I
FB
SS/TRACK
0.5V/DIV
TH
V
FB
0.5V/DIV
0.5V/DIV
V
FB
0.5V/DIV
I
L
I
L
I
2A/DIV
5A/DIV
L
5A/DIV
38105 G04
38105 G05
38105 G06
V
I
= 48V
OUT
20μs/DIV
200μs/DIV
FRONT PAGE CIRCUIT
V
I
= 48V
= 1A
500μs/DIV
V
= 48V
IN
IN
LOAD
MODE/SYNC = 0V
IN
= 100mA
MODE/SYNC = INTV
CC
FRONT PAGE CIRCUIT
FRONT PAGE CIRCUIT
Efficiency vs Input Voltage
Efficiency vs Load Current
Frequency vs Input Voltage
280
270
260
250
240
230
100
90
100
95
90
85
80
75
70
I
= 5A
OUT
V
= 36V
IN
V
= 12V
IN
V
= 60V
IN
I
I
= 0A
= 5A
OUT
OUT
I
= 0.5A
OUT
80
V
= 5V
OUT
Si7850 MOSFETs
V
= 12V
OUT
MODE/SYNC = INTV
f = 250kHz
MODE/SYNC = 0V
FRONT PAGE CIRCUIT
Si7852 MOSFETs
f = 250kHz
CC
70
0
2
3
4
5
6
7
50
60
80
10
20
30
40
50
60
70
80
1
10 20 30 40
70
LOAD CURRENT (A)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
38105 G08
38105 G09
38105 G07
38105fc
5
LTC3810-5
TYPICAL PERFORMANCE CHARACTERISTICS
Current Sense Threshold
vs ITH Voltage
Frequency vs Load Current
On-Time vs ION Current
350
300
400
300
200
100
10000
1000
100
V
= INTV
V
= 2V
ON
CC
RNG
FORCED
CONTINUOUS
1.4V
1V
0.7V
0.5V
250
200
150
100
50
0
–100
PULSE SKIP
–200
–300
–400
0
10
1
2
3
5
0
4
0.5
1.0
2.0
1.5
VOLTAGE (V)
0
2.5
3.0
10
100
1000
CURRENT (μA)
10000
LOAD CURRENT (A)
I
TH
I
ON
38105 G12
38105 G10
38105 G11
On-Time vs VON Voltage
On-Time vs Temperature
Current Limit Foldback
680
660
640
620
700
600
250
200
150
100
50
500
400
300
200
100
600
580
560
I
= 300μA
I
= 300μA
2.5
V
= INTV
CC
ON
ON
RNG
0.6
0
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
2
3
0.4
(V)
0
0.5
1
1.5
0
0.2
0.8
V
VOLTAGE (V)
V
ON
FB
38105 G14
38105 G13
38105 G15
Maximum Current Sense
Threshold vs VRNG Voltage
Maximum Current Sense
Threshold vs Temperature
Reference Voltage vs
Temperature
230
220
210
200
190
180
0.803
0.802
0.801
0.800
400
300
200
100
0
0.799
0.798
0.797
V
= INTV
CC
RNG
–50 –25
0
25
50
75 100 125
50
TEMPERATURE (°C)
100 125
1
1.5
–50 –25
0
25
75
0.5
2
TEMPERATURE (°C)
V
VOLTAGE (V)
RNG
38105 G17
38105 G18
38105 G16
38105fc
6
LTC3810-5
TYPICAL PERFORMANCE CHARACTERISTICS
Driver Peak Source Current
vs Temperature
Driver Pull-Down RDS(ON)
vs Temperature
Driver Peak Source Current
vs Supply Voltage
1.75
1.50
1.25
1.00
1.5
1.0
0.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= V
INTVCC
= 5V
V
= V
= 5V
INTVCC
BOOST
BOOST
0.75
0.50
0.25
–50 –25
0
25
50
75 100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
4
5
6
7
8
9
10 11 12 13 14
TEMPERATURE (°C)
DRV /BOOST VOLTAGE (V)
CC
38105 G19
38105 G20
38105 G21
Driver Pull-Down RDS(ON)
vs Supply Voltage
EXTVCC LDO Resistance at
Dropout vs Temperature
INTVCC Current vs Temperature
4
3
2
1
0
1.1
7
6
1.0
0.9
5
4
3
2
1
0.8
0.7
0.6
0
–50 –25
0
25
50
75 100 125
50
TEMPERATURE (°C)
100 125
4
5
6
7
8
9
10 11 12 13 14
–50 –25
0
25
75
TEMPERATURE (°C)
DRV /BOOST VOLTAGE (V)
CC
38105 G24
38105 G22
38105 G23
INTVCC Shutdown Current
vs Temperature
INTVCC Current vs INTVCC Voltage
3.5
3.0
400
300
INTV = 5V
CC
2.5
2.0
1.5
1.0
0.5
200
100
0
0
8
12
14
–25
0
50
75 100 125
0
2
4
6
10
–50
25
INTV VOLTAGE (V)
TEMPERATURE (°C)
CC
38105 G26
38105 G25
38105fc
7
LTC3810-5
TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC Shutdown Current
vs INTVCC Voltage
SS/TRACK Pull-Up Current
vs Temperature
3
2
300
250
200
150
100
50
1
0
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
8
12
14
0
2
4
6
10
INTV VOLTAGE (V)
CC
38105 G28
38105 G27
ITH Voltage
vs Load Current
Shutdown Threshold
vs Temperature
3.0
2.5
2.0
1.5
1.0
0.5
0
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
V
= 1V
RNG
FRONT PAGE CIRCUIT
0.6
4
6
7
–50 –25
0
25
50
75 100 125
0
1
2
3
5
LOAD CURRENT (A)
TEMPERATURE (°C)
38105 G29
38105 G30
38105fc
8
LTC3810-5
PIN FUNCTIONS
V
(Pin 2): On-Time Voltage Input. Voltage trip point for
PLL/LPF (Pin 8): The phase-locked loop’s lowpass filter
is tied to this pin. The voltage at this pin defaults to 1.2V
when the IC is not synchronized with an external clock at
the MODE/SYNC pin.
ON
theon-timecomparator.Tyingthispintotheoutputvoltage
ortoanexternalresistivedividerfromtheoutputmakesthe
on-time proportional to V . The comparator defaults to
OUT
0.7V when the pin is grounded and defaults to 2.4V when
SS/TRACK(Pin9):Soft-Start/TrackingInput.Forsoft-start,
a capacitor to ground at this pin sets the ramp rate of the
output voltage (approximately 0.6s/μF). For coincident or
ratiometric tracking, connect this pin to a resistive divider
between the voltage to be tracked and ground.
the pin is connected to INTV . Tie this pin to INTV in
CC
CC
high V
applications to use a lower R value.
OUT
ON
V
(Pin 3): Sense Voltage Limit Set. The voltage at this
RNG
pin sets the nominal sense voltage at maximum output
current and can be set from 0.5V to 2V by a resistive
SHDN (Pin 12): Shutdown Pin. Pulling this pin below
1.5V will shut down the LTC3810-5, turn off both of the
external MOSFET switches and reduce the quiescent sup-
ply current to 240μA.
divider from INTV . The nominal sense voltage defaults
CC
to 95mV when this pin is tied to ground, and 215mV when
tied to INTV .
CC
PGOOD (Pin 4): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage
is not between 10% of the regulation point. The output
voltage must be out of regulation for at least 120μs before
the power good output is pulled to ground.
UVIN (Pin 13): UVLO Input. This pin is input to the inter-
nal UVLO and is compared to an internal 0.8V reference.
An external resistor divider is connected to this pin and
the input supply to program the undervoltage lockout
voltage. When UVIN is less than 0.8V, the LTC3810-5 is
shut down.
MODE/SYNC (Pin 5): Pulse Skip Mode Enable/Sync Pin.
This multifunction pin provides pulse skip mode enable/
disable control and an external clock input to the phase
detector. Pulling this pin below 0.8V or to an external
logic-levelsynchronizationsignaldisablespulseskipmode
operation and forces continuous operation. Pulling this
pin above 0.8V enables pulse skip mode operation. For a
clock input, the phase-locked loop will force the rising top
gate signal to be synchronized with the rising edge of the
clock signal.This pin can also be connected to a feedback
resistor divider from a secondary winding on the inductor
to regulate a second output voltage.
NDRV (Pin 14): Drive Output for External Pass Device of
the Linear Regulator for INTV . Connect to the gate of
CC
an external NMOS pass device and a pull-up resistor to
the input voltage V .
IN
EXTV (Pin 15): External Driver Supply Voltage. When
CC
this voltage exceeds 4.7V, an internal switch connects this
pin to INTV through an LDO and turns off the exter nal
CC
MOSFET connected to NDRV, so that controller and gate
drive are drawn from EXTV .
CC
INTV (Pin 16): Main Supply Pin. All internal circuits ex-
CC
cept the output drivers are powered from this pin. INTV
I
TH
(Pin 6): Error Amplifier Compensation Point and Cur-
CC
shouldbebypassedtoground(Pin10)withatleasta0.1μF
rent Control Threshold. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.6V with 1.2V corresponding to zero sense
voltage (zero current).
capacitor in close proximity to the LTC3810-5.
DRV (Pin 17): Driver Supply Pin. DRV supplies power
CC
CC
to the BG output driver. This pin is normally connected to
INTV . DRV should be bypassed to BGRTN (Pin 20)
V (Pin7):FeedbackInput.ConnectV througharesistor
CC
CC
FB
FB
withalowESR(X5Rorbetter)1μF-10μFcapacitorinclose
divider network to V
to set the output voltage.
OUT
proximity to the LTC3810-5.
38105fc
9
LTC3810-5
PIN FUNCTIONS
BG (Pin 18): Bottom Gate Drive. The BG pin drives the
TG (Pin 26): Top Gate Drive. The TG pin drives the gate of
the top N-channel synchronous switch MOSFET. The TG
driver draws power from the BOOST pin and returns to the
SW pin, providing true floating drive to the top MOSFET.
gateofthebottomN-channelsynchronousswitchMOSFET.
This pin swings from BGRTN to DRV .
CC
BGRTN(Pin19):BottomGateReturn.Thispinconnectsto
the source of the pulldown MOSFET in the BG driver and
is normally connected to ground. Connecting a negative
supply to this pin allows the synchronous MOSFET’s gate
to be pulled below ground to help prevent false turn-on
during high dV/dt transitions on the SW node. See the
Applications Information section for more details.
BOOST (Pin 27): Top Gate Driver Supply. The BOOST pin
supplies power to the floating TG driver. BOOST should
be bypassed to SW with a low ESR (X5R or better) 0.1μF
capacitor. An additional fast recovery Schottky diode from
DRV to the BOOST pin will create a complete floating
CC
charge-pumped supply at BOOST.
+
–
SENSE , SENSE (Pin 24, Pin 20): Current Sense Com-
parator Input. The (+) input to the current comparator is
normally connected to SW unless using a sense resistor.
The (–) input is used to accurately kelvin sense the bottom
side of the sense resistor or MOSFET.
I
(Pin31):On-TimeCurrentInput.TiearesistorfromV
ON IN
to this pin to set the one-shot timer current and thereby
set the switching frequency.
SGND (Pin 33): Signal Ground. All small-signal compo-
nentsshouldconnecttothisgroundandeventuallyconnect
to PGND at one point.
SW (Pin 25): Switch Node Connection to Inductor and
Bootstrap Capacitor. The voltage swing at this pin is –0.7V
(a Schottky diode (external) voltage drop) to V .
IN
38105fc
10
LTC3810-5
FUNCTIONAL DIAGRAM
INTV
EXTV
N
INTV
CC
CC
CC DRV
V
IN
5V
REG
0.8V
REF
INTV
MODE
LOGIC
CC
5.5V
+
–
NDRV
14
M3
V
IN
9V
4.2V
R
R
UVIN
13
UV1
UV2
OFF
+
–
INTV
–
+
CC
INTV
CC
UV
V
IN
UV
16
EXTV
15
CC
+
–
0.8V
+
–
F
MODE/SYNC
5
270μA
5.5V
4.7V
PLL/LPF
8
ON
+
+
PLL-SYNC
1.4μA
+
–
V
ON
V
IN
D
B
2
BOOST
27
TIMEOUT
LOGIC
100nA
C
IN
I
R
ON
ON
C
TG
26
V
I
B
DRV OFF
VON
ION
V
IN
t
=
(76pF)
20k
31
ON
FCNT
M1
R
S
ON
Q
SW
25
+
SENSE
24
+
–
+
–
L1
SWITCH
LOGIC
V
OUT
I
I
REV
CMP
DRV
CC
17
SHDN
OV
C
VCC
BG
18
M2
+
BGRTN
19
C
OUT
×
–
SENSE
20
1.4V
0.7V
OVERTEMP
SENSE
V
RNG
PGOOD
4
I
’
TH
3
R
FB1
FOLDBACK
FB
0.72V
+
–
I
TH
UV
OV
6
V
FB
2.6V 4V
7
C
R
C
C2
R
+
–
FB2
RUN
SHDN
SGND
12
C
EA
C1
FAULT
–
+
–
+
+
0.88V
1.5V
SS/TRACK
0.8V
SHDN
12
9
38105 FD
38105fc
11
LTC3810-5
OPERATION
Main Control Loop
behaves as a constant frequency part against the load and
supply variations.
The LTC3810-5 is a current mode controller for DC/DC
step-down converters. In normal operation, the top
MOSFET is turned on for a fixed interval determined by
a one-shot timer (OST). When the top MOSFET is turned
off, the bottom MOSFET is turned on until the current
Pulling the SHDN pin low forces the controller into its
shutdown state, turning off both M1 and M2. Forcing a
voltage above 1.5V will turn on the device.
Pulse Skip Mode
comparator I
trips, restarting the one-shot timer and
CMP
initiating the next cycle. Inductor current is determined
TheLTC3810-5canoperateinoneoftwomodesselectable
withtheMODE/SYNCpin—pulseskipmodeorforcedcon-
tinuous mode (see Figure 1). Pulse skip mode is selected
when increased efficiency at light loads is desired (see
Figure 2). In this mode, the bottom MOSFET is turned off
wheninductorcurrentreversestominimizeefficiencyloss
due to reverse current flow and gate charge switching.
–
+
by sensing the voltage between the SENSE and SENSE
pins using a sense resistor or the bottom MOSFET on-
resistance. The voltage on the I pin sets the comparator
TH
threshold corresponding to the inductor valley current.
The fast 25MHz error amplifier EA adjusts this voltage by
comparing the feedback signal V to the internal 0.8V
FB
reference voltage. If the load current increases, it causes a
At low load currents, I will drop below the zero current
TH
drop in the feedback voltage relative to the reference. The
level (1.2V) shutting off both switches. Both switches will
I
voltage then rises until the average inductor current
TH
remain off with the output capacitor supplying the load
again matches the load current.
current until the I voltage rises above the zero current
TH
level to initiate another cycle. In this mode, frequency is
Theoperatingfrequencyisdeterminedimplicitlybythetop
MOSFET on-time and the duty cycle required to maintain
regulation. Theone-shottimergeneratesanontimethatis
proportionaltotheidealdutycycle,thusholdingfrequency
approximately constant with changes in V . The nominal
frequency can be adjusted with an external resistor R .
proportional to load current at light loads.
Pulse skip mode operation is disabled by comparator F
when the MODE/SYNC pin is brought below 0.8V, forcing
continuous synchronous operation. Forced continuous
mode is less efficient due to resistive losses, but has the
advantage of better transient response at low currents,
approximatelyconstantfrequencyoperation,andtheability
to maintain regulation when sinking current.
IN
ON
For applications with stringent constant frequency re-
quirements, the LTC3810-5 can be synchronized with an
external clock. By programming the nominal frequency
the same as the external clock frequency, the LTC3810-5
PULSE SKIP MODE
FORCED CONTINUOUS
100
PULSE
SKIP
90
80
70
0A
0A
0A
0A
0A
0A
FORCED
60
CONTINUOUS
DECREASING
LOAD
CURRENT
50
40
30
20
V
V
= 12V
= 42V
10
IN
IN
0
0.01
0.1
1
10
LOAD (A)
38105 F01
38105 F02
Figure 1. Comparison of Inductor Current Waveforms for Pulse Skip Mode
and Forced Continuous Operation
Figure 2. Efficiency in Pulse Skip/
Forced Continuous Modes
38105fc
12
LTC3810-5
OPERATION
Fault Monitoring/Protection
skip mode operation, where it is possible that the bottom
MOSFET will be off for an extended period of time, an
internal timeout guarantees that the bottom MOSFET is
turned on at least once every 25μs for one on-time period
to refresh the bootstrap capacitor.
Constant on-time current mode architecture provides ac-
curate cycle-by-cycle current limit protection—a feature
thatisveryimportantforprotectingthehighvoltagepower
supply from output short circuits. The cycle-by-cycle cur-
rentmonitorguaranteesthattheinductorcurrentwillnever
The bottom driver has an additional feature that helps
minimizethepossibilityofexternalMOSFETshoot-through.
When the top MOSFET turns on, the switch node dV/dt
pulls up the bottom MOSFET’s internal gate through the
Millercapacitance, evenwhenthebottomdriverisholding
the gate terminal at ground. If the gate is pulled up high
enough, shoot-through between the top side and bottom
side MOSFETs can occur. To prevent this from occurring,
the bottom driver return is brought out as a separate pin
(BGRTN) so that a negative supply can be used to reduce
the effect of the Miller pull-up. For example, if a –2V sup-
ply is used on BGRTN, the switch node dV/dt could pull
exceed the value programmed on the V
pin.
RNG
Foldback current limiting provides further protection if the
output is shorted to ground. As V drops, the buffered
FB
currentthresholdvoltageI ispulleddownandclamped
THB
to 1V. This reduces the inductor valley current level to
one-sixth of its maximum value as V approaches 0V.
FB
Foldback current limiting is disabled at start-up.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a 10% window around the regulation point after the
internal120μspowerbadmasktimerexpires.Furthermore,
in an overvoltage condition, M1 is turned off and M2 is
turned on immediately and held on until the overvoltage
condition clears.
the gate up 2V before the V of the bottom MOSFET has
GS
more than 0V across it.
V
DRV
IN
CC
The LTC3810-5 provides two undervoltage lockout com-
parators—one for the INTV /DRV supply and one for
D
+
B
LTC3810-5
DRV
CC
BOOST
TG
C
IN
CC
CC
the input supply V . The INTV UV threshold is 4.2V to
C
IN
CC
B
M1
guarantee that the MOSFETs have sufficient gate drive
L
SW
voltagebeforeturningon.TheV UVthreshold(UVINpin)
V
OUT
IN
BG
is 0.8V with 10% hysteresis which allows programming
+
M2
C
OUT
the V threshold with the appropriate resistor divider
IN
BGRTN
0V TO –5V
38105 F03
connected to V . If either comparator inputs are under
IN
the UV threshold, the LTC3810-5 is shut down and the
drivers are turned off.
Figure 3. Floating TG Driver Supply and Negative BG Return
Strong Gate Drivers
IC/Driver Supply Power
The LTC3810-5 contains very low impedance drivers ca-
pable of supplying amps of current to slew large MOSFET
gates quickly. This minimizes transition losses and allows
paralleling MOSFETs for higher current applications. A
60V floating high side driver drives the top side MOSFET
and a low side driver drives the bottom side MOSFET
(see Figure 3). The bottom side driver is supplied directly
The LTC3810-5’s internal control circuitry and top and
bottom MOSFET drivers operate from a supply voltage
(INTV , DRV pins) in the range of 4.5V to 14V. The
CC
CC
LTC3810-5 has two integrated linear regulator controllers
toeasilygeneratethisIC/driversupplyfromeitherthehigh
voltageinputorfromtheoutputvoltage.Forbestefficiency
thesupplyisderivedfromtheinputvoltageduringstart-up
and then derived from the lower voltage output as soon
as the output is higher than 4.7V. Alternatively, the supply
from the DRV pin. The top MOSFET drivers are biased
CC
from floating bootstrap capacitor, C , which normally is
B
recharged during each off cycle through an external diode
can be derived from the input continuously if the output is
from DRV when the top MOSFET turns off. In pulse
CC
38105fc
13
LTC3810-5
OPERATION
<4.7V or an external supply in the appropriate range can
be used. The LTC3810-5 will automatically detect which
mode is being used and operate properly.
start-up.TheMOSFETissizedforproperdissipationand
thedrivershutdown/restartforV <4.7Visdisabled.
OUT
This scheme is less efficient but may be necessary if
V
< 4.7V and a boost network is not desired.
OUT
The four possible operating modes for generating this
supply are summarized as follows (see Figure 4):
3. Tricklechargemodeprovidesanevensimplerapproach
by eliminating the external MOSFET. The IC/driver sup-
plycapacitorsarechargedthroughasinglehigh-valued
1.LTC3810-5generatesa5.5Vstart-upsupplyfromasmall
external SOT23 N-channel MOSFET acting as linear
resistorconnectedtotheinputsupply.WhentheINTV
CC
regulatorwithdrainconnectedtoV andgatecontrolled
IN
voltage reaches the turn-on threshold of 9V (automati-
cally raised from 4.7V to provide extra headroom for
start-up), the drivers turn on and begin charging up the
outputcapacitor.Whentheoutputreaches4.7V,IC/driver
powerisderivedfromtheoutput.Intrickle-chargemode,
the supply capacitors must have sufficient capacitance
by the LTC3810-5’s internal linear regulator controller
through the NDRV pin. As soon as the output voltage
reaches 4.7V, the 5.5V IC/driver supply is derived from
the output through an internal low-dropout regulator to
optimize efficiency. If the output is lost due to a short,
the LTC3810-5 goes through repeated low duty cycle
soft-start cycles (with the drivers shut off in between)
to attempt to bring up the output without burning up
the SOT23 MOSFET. This scheme eliminates the long
start-up times associated with a conventional trickle
charger by using an external MOSFET to quickly charge
such that they are not discharged below the 4V INTV
CC
UV threshold before the output is high enough to take
over or else the power supply will not start.
4.Lowvoltagesupplyavailable.Thesimplestapproachisif
alowvoltagesupply(between4.5Vand14V)isavailable
and connected directly to the IC/driver supply pins.
the IC/driver supply capacitors (C
, C
).
INTVCC DRVCC
2.Similar to (1) except that the external MOSFET is used
for continuous IC/driver power instead of just for
Mode 1: MOSFET for Start-Up Only
Mode 2: MOSFET for Continuous Use
V
V
IN
IN
I > 270μA
NDRV
I < 270μA
NDRV
INTV
5.5V
INTV
5.5V
CC
CC
+
+
LTC3810-5
LTC3810-5
V
(> 4.7V)
EXTV
EXTV
OUT
CC
CC
V
IN
Mode 3: Trickle Charge Mode
Mode 4: External Supply
NDRV
NDRV
INTV
CC
INTV
CC
5.5V
+
+
LTC3810-5
LTC3810-5
+
–
4.5V to
14V
EXTV
CC
EXTV
CC
V
OUT
38105 F04
Figure 4. Operating Modes for IC/Driver Supply
38105fc
14
LTC3810-5
APPLICATIONS INFORMATION
The basic LTC3810-5 application circuit is shown on the
first page of this data sheet. External component selection
isprimarilydeterminedbythemaximuminputvoltageand
load current and begins with the selection of the sense
resistance and power MOSFET switches. The LTC3810-5
uses either a sense resistor or the on-resistance of the
synchronouspowerMOSFETfordeterminingtheinductor
current.Thedesiredamountofripplecurrentandoperating
the sense resistor. Using a sense resistor provides a well
definedcurrentlimit, butaddscostandreducesefficiency.
Alternatively, one can eliminate the sense resistor and use
thebottomMOSFETasthecurrentsenseelementbysimply
+
connecting the SENSE pin to the lower MOSFET drain
–
and SENSE pin to the MOSFET source. This improves
efficiency, but one must carefully choose the MOSFET
on-resistance, as discussed below.
frequency largely determines the inductor value. Next, C
IN
Power MOSFET Selection
is selected for its ability to handle the large RMS current
into the converter and C is chosen with low enough
OUT
The LTC3810-5 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
ESR to meet the output voltage ripple and transient
specification. Finally, loop compensation components
are selected to meet the required transient/phase margin
specifications.
the power MOSFETs are the breakdown voltage BV
,
DSS
threshold voltage V(GS)TH, on-resistance RDS(ON), input
capacitance and maximum current IDS(MAX)
.
Maximum Sense Voltage and V
Pin
RNG
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its on-resis-
tance. MOSFET on-resistance is typically specified with
Inductor current is determined by measuring the volt-
age across a sense resistance that appears between the
–
+
SENSE and SENSE pins. The maximum sense voltage
a maximum value R
at 25°C. In this case,
DS(ON)(MAX)
is set by the voltage applied to the V
to approximately:
pin and is equal
RNG
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
V
= 0.173V
– 0.026
SENSE(MAX)
RNG
RSENSE
RDS(ON)(MAX)
=
The current mode control loop will not allow the inductor
current valleys to exceed V /R . In prac-
ρT
SENSE(MAX) SENSE
tice, one should allow some margin for variations in the
LTC3810-5 and external component values and a good
guide for selecting the sense resistance is:
The ρ term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature (see Figure 5) and typically varies
from 0.4%/°C to 1.0%/°C depending on the particular
MOSFET used.
T
VSENSE(MAX)
RSENSE
=
1.3•IOUT(MAX)
2.0
An external resistive divider from INTV can be used
CC
to set the voltage of the V
pin between 0.5V and 2V
RNG
1.5
1.0
0.5
resulting in nominal sense voltages of 60mV to 320mV.
Additionally, the V pin can be tied to SGND or INTV
RNG
CC
in which case the nominal sense voltage defaults to 95mV
or 215mV, respectively.
+
–
Connecting the SENSE and SENSE Pins
The LTC3810-5 can be used with or without a sense re-
sistor. When using a sense resistor, place it between the
source of the bottom MOSFET, M2 and PGND. Connect
0
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
38105 F05
+
–
Figure 5. RDS(ON) vs Temperature
the SENSE and SENSE pins to the top and bottom of
38105fc
15
LTC3810-5
APPLICATIONS INFORMATION
Themostimportantparameterinhighvoltageapplications
data sheets. C
and C are specified sometimes but
RSS OS
definitions of these parameters are not included.
is breakdown voltage BV . Both the top and bottom
DSS
MOSFETs will see full input voltage plus any additional
ringing on the switch node across its drain-to-source dur-
ing its off-time and must be chosen with the appropriate
breakdown specification. The LTC3810-5 is designed to
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
VOUT
Main Switch Duty Cycle =
be used with a 4.5V to 14V gate drive supply (DRV pin)
V
CC
≥ 4.5V).
IN
for driving logic-level MOSFETs (V
GS(MIN)
V – VOUT
IN
Synchronous Switch Duty Cycle=
For maximum efficiency, on-resistance R
and input
V
DS(ON)
IN
capacitanceshouldbeminimized. LowR
minimizes
DS(ON)
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combi-
nation of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 6).
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
VOUT
PTOP
=
I
(
2(ꢀT)RDS(ON)
+
MAX
)
V
IN
V
IN
2 I
V
MAX (RDR)(CMILLER)•
2
IN
MILLER EFFECT
V
V
GS
ꢁ
ꢃ
ꢂ
ꢄ
a
b
1
1
+
–
+
(f)
ꢆ
V
DS
+
V – VTH(IL) VTH(IL) ꢆ
ꢃ CC
Q
V
ꢅ
IN
GS
–
C
= (Q – Q )/V
B A DS
MILLER
V – V
38105 F06
IN
PBOT
=
OUT (IMAX )2(ꢀT)RDS(0N)
V
IN
Figure 6. Gate Charge Characteristic
where ρ is the temperature dependency of R
, R
The curve is generated by forcing a constant input cur-
rent into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
T
DS(ON) DR
is the effective top driver resistance (approximately 2Ω at
= V ), V is the drain potential and the change
V
GS
MILLER
IN
in drain potential in the particular application. V
is
TH(IL)
the data sheet specified typical gate threshold voltage
specified in the power MOSFET data sheet at the specified
drain current. C
is the calculated capacitance using
MILLER
the gate charge curve from the MOSFET data sheet and
the technique described above.
2
Both MOSFETs have I R losses while the topside N-chan-
nel equation incudes an additional term for transition
losses, which peak at the highest input voltage. For high
input voltage low duty cycle applications that are typical
for the LTC3810-5, transition losses are the dominate
while the curve is flat) is specified for a given V drain
DS
voltage, but can be adjusted for different V voltages by
DS
multiplying by the ratio of the application V to the curve
DS
specified V values. A way to estimate the C
term
DS
MILLER
loss term and therefore using higher R
device with
DS(ON)
is to take the change in gate charge from points a and b
lower C
usually provides the highest efficiency. The
MILLER
on a manufacturers data sheet and divide by the stated
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
V
voltage specified. C
is the most important se-
MILLER
DS
lection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
to 100% of the period. Since there is no transition loss
38105fc
16
LTC3810-5
APPLICATIONS INFORMATION
term in the synchronous MOSFET, optimal efficiency is
Tying a resistor R from V to the I pin yields an
ON IN ON
obtainedbyminimizingR
—byusinglargerMOSFETs
on-time inversely proportional to V . For a step-down
DS(ON)
IN
or paralleling multiple MOSFETs.
converter,thisresultsinapproximatelyconstantfrequency
operation as the input supply varies:
Multiple MOSFETs can be used in parallel to lower
VOUT
VVON • RON(76pF)
R
and meet the current and thermal requirements
DS(ON)
f =
[HZ ]
if desired. The LTC3810-5 contains large low impedance
drivers capable of driving large gate capacitances without
significantly slowing transition times. In fact, when driv-
ing MOSFETs with very low gate charge, it is sometimes
helpful to slow down the drivers by adding small gate
resistors (10Ω or less) to reduce noise and EMI caused
by the fast transitions.
Toholdfrequencyconstantduringoutputvoltagechanges,
tie the V pin to V or to a resistive divider from V
ON
OUT
OUT
when V
> 2.4V. The V pin has internal clamps that
OUT
ON
limit its input to the one-shot timer. If the pin is tied below
0.7V,theinputtotheone-shotisclampedat0.7V.Similarly,
if the pin is tied above 2.4V, the input is clamped at 2.4V.
Operating Frequency
In high V
applications, tie V to INTV . Figures 7a
OUT
ON CC
and 7b show how R relates to switching frequency for
ON
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improvesefficiencybyreducingMOSFETswitchinglosses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
several common output voltages.
Changes in the load current magnitude will cause fre-
quency shift. Parasitic resistance in the MOSFET switches
and inductor reduce the effective voltage across the
inductance, resulting in increased duty cycle as the load
current increases. By lengthening the on-time slightly as
current increases, constant frequency operation can be
maintained. This is accomplished with a resistive divider
The operating frequency of LTC3810-5 applications is
determined implicitly by the one-shot timer that controls
the on-time, t , of the top MOSFET switch. The on-time
ON
is set by the current out of the I pin and the voltage at
ON
from the I pin to the V pin and V . The values
TH
ON
OUT
the V pin according to:
ON
required will depend on the parasitic resistances in the
specific application. A good starting point is to feed about
25% of the voltage change at the I pin to the V pin
V
tON
=
VON (76pF)
IION
TH
ON
as shown in Figure 8. Place capacitance on the V pin
ON
to filter out the I variations at the switching frequency.
TH
1000
1000
V
= 5V
OUT
V
= 12V
V
OUT
V
= 3.3V
OUT
V
= 2.5V
OUT
= 5V
OUT
V
= 1.5V
V
= 3.3V
OUT
OUT
100
100
10
100
(kΩ)
1000
38105 F07a
10
100
R (kΩ)
ON
1000
38105 F07b
R
ON
Figure 7a. Switching Frequency vs RON (VON = 0V)
Figure 7b. Switching Frequency vs RON (VON = INTVCC)
38105fc
17
LTC3810-5
APPLICATIONS INFORMATION
Inductor Selection
R
VON1
100k
Given the desired input and output voltages, the induc-
tor value and operating frequency determine the ripple
current:
INTV
CC
V
ON
5.5V
C
R
VON
VON2
30k
100k
LTC3810-5
0.01μF
I
TH
ꢁ
OUT ꢄ ꢁ
OUT ꢄ
V
V
ꢀIL =
1ꢇ
38105 F08
ꢃ
ꢆ ꢃ
ꢆ
f L
V
ꢂ
ꢅ ꢂ
ꢅ
IN
Figure 8. Correcting Frequency Shift with Load Current Changes
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
Minimum Off-Time and Dropout Operation
The minimum off-time t
is the smallest amount of
OFF(MIN)
time that the LTC3810-5 is capable of turning on the bot-
tom MOSFET, tripping the current comparator and turning
the MOSFET back off. This time is generally about 250ns.
The minimum off-time limit imposes a maximum duty
A reasonable starting point is to choose a ripple current
that is about 40% of I
. The largest ripple current
cycle of t /(t + t
). If the maximum duty cycle
OFF(MIN)
OUT(MAX)
ON ON
occurs at the highest V . To guarantee that ripple current
is reached, due to a dropping input voltage for example,
then the output will drop out of regulation. The minimum
input voltage to avoid dropout is:
IN
does not exceed a specified maximum, the inductance
should be chosen according to:
ꢁ
ꢃ
ꢂ
ꢄ
ꢆ
ꢅ
ꢁ
ꢄ
VOUT
fꢀIL(MAX)
VOUT
t
ON + tOFF(MIN)
L =
1ꢇ
ꢃ
ꢆ
VIN(MIN) = VOUT
V
ꢂ
ꢅ
IN(MAX)
tON
A plot of maximum duty cycle vs frequency is shown in
Figure 9.
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
affordthecorelossfoundinlowcostpowderedironcores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mμ® cores. A variety of inductors designed for
high current, low voltage applications are available from
manufacturers such as Sumida, Panasonic, Coiltronics,
Coilcraft and Toko.
2.0
1.5
DROPOUT
REGION
1.0
0.5
0
Schottky Diode D1 Selection
The Schottky diode D1 shown in the front page schematic
conducts during the dead time between the conduction of
the power MOSFET switches. It is intended to prevent the
body diode of the bottom MOSFET from turning on and
storing charge during the dead time, which can cause a
modest (about 1%) efficiency loss. The diode can be rated
for about one-half to one-fifth of the full load current since
it is on for only a fraction of the duty cycle. In order for the
diode to be effective, the inductance between it and the
0
0.25
0.50
0.75
1.0
DUTY CYCLE (V /V
)
OUT IN
38105 F09
Figure 9. Maximum Switching Frequency vs Duty Cycle
38105fc
18
LTC3810-5
APPLICATIONS INFORMATION
bottom MOSFET must be as small as possible, mandating
thatthesecomponentsbeplacedadjacently.Thediodecan
be omitted if the efficiency loss is tolerable.
by the aluminum capacitors alone, when used together,
the percentage of RMS current that will be supplied by the
aluminum capacitor is reduced to approximately:
1
Input Capacitor Selection
%IRMS,ALUM
≈
•100%
2
1+(8fCRESR
)
In continuous mode, the drain current of the top MOSFET
is approximately a square wave of duty cycle V /V
which must be supplied by the input capacitor. To prevent
large input transients, a low ESR input capacitor sized for
the maximum RMS current is given by:
OUT IN
where R
is the ESR of the aluminum capacitor and C
ESR
is the overall capacitance of the ceramic capacitors. Using
an aluminum electrolytic with a ceramic also helps damp
the high Q of the ceramic, minimizing ringing.
OUT ꢁ
ꢄ1/2
–1
V
V
V
OUT
IN
Output Capacitor Selection
ICIN(RMS) ꢀIO(MAX)
ꢃ
ꢆ
V
ꢂ
ꢅ
IN
The selection of C
is primarily determined by the ESR
OUT
required to minimize voltage ripple. The output ripple
(ΔV ) is approximately equal to:
This formula has a maximum at V = 2V , where I =
RMS
O(MAX)
IN
OUT
OUT
I
/2. This simple worst-case condition is commonly
usedfordesignbecauseevensignificantdeviationsdonot
offer much relief. Note that the ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life. This makes it advisable to further derate
the capacitor or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also
be placed in parallel to meet size or height requirements
in the design.
ꢂ
ꢅ
ꢇ
1
ꢀVOUT ꢁ ꢀIL ESR+
ꢄ
8fC
ꢃ
OUT ꢆ
Since ΔI increases with input voltage, the output ripple
L
is highest at maximum input voltage. ESR also has a
significant effect on the load transient response. Fast load
transitions at the output will appear as voltage across the
ESR of C
until the feedback loop in the LTC3810-5 can
OUT
BecausetantalumandOS-CONcapacitorsarenotavailable
in voltages above 30V, ceramics or aluminum electrolytics
mustbeusedforregulatorswithinputsuppliesabove30V.
Ceramic capacitors have the advantage of very low ESR
and can handle high RMS current, but ceramics with high
voltage ratings (> 50V) are not available with more than
a few microfarads of capacitance. Furthermore, ceram-
ics have high voltage coefficients which means that the
capacitance values decrease even more when used at the
rated voltage. X5R and X7R type ceramics are recom-
mended for their lower voltage and temperature coef-
ficients. Another consideration when using ceramics is
their high Q which, if not properly damped, may result in
excessive voltage stress on the power MOSFETs. Alumi-
num electrolytics have much higher bulk capacitance, but
they have higher ESR and lower RMS current ratings.
change the inductor current to match the new load current
value. Typically, once the ESR requirement is satisfied the
capacitance is adequate for filtering and has the required
RMS current rating.
Manufacturers such as Nichicon, Nippon Chemi-Con
and Sanyo should be considered for high performance
throughhole capacitors. The OS-CON (organic semicon-
ductor dielectric) capacitor available from Sanyo has the
lowestproductofESRandsizeofanyaluminumelectroly-
tic at a somewhat higher price. An additional ceramic
capacitor in parallel with OS-CON capacitors is recom-
mended to reduce the effect of their lead inductance.
In surface mount applications, multiple capacitors placed
in parallel may be required to meet the ESR, RMS current
handlingandloadsteprequirements.Drytantalum,special
polymerandaluminumelectrolyticcapacitorsareavailable
in surface mount packages. Special polymer capacitors
offer very low ESR but have lower capacitance density
A good approach is to use a combination of aluminum
electrolyticsforbulkcapacitanceandceramicsforlowESR
and RMS current. If the RMS current cannot be handled
38105fc
19
LTC3810-5
APPLICATIONS INFORMATION
than other types. Tantalum capacitors have the highest
capacitance density but it is important to only use types
that have been surge tested for use in switching power
supplies. Several excellent surge-tested choices are the
AVX, TPS and TPSV or the KEMET T510 series. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-driven applications providing that
consideration is given to ripple current ratings and long
term reliability. Other capacitor types include Panasonic
SP and Sanyo POSCAPs.
Top MOSFET Driver Supply (C , D )
B B
An external bootstrap capacitor, C , connected to the
B
BOOST pin supplies the gate drive voltage for the topside
MOSFET. This capacitor is charged through diode D from
B
DRV whentheswitchnodeislow.WhenthetopMOSFET
CC
turns on, the switch node rises to V and the BOOST pin
IN
rises to approximately V + INTV . The boost capacitor
IN
CC
needs to store about 100 times the gate charge required
by the top MOSFET. In most applications 0.1μF to 0.47μF,
X5R or X7R dielectric capacitor is adequate.
Output Voltage
The reverse breakdown of the external diode, D , must
B
begreaterthanV
. Anotherimportantconsideration
IN(MAX)
The LTC3810-5 output voltage is set by a resistor divider
according to the following formula:
for the external diode is the reverse recovery and reverse
leakage, either of which may cause excessive reverse
current to flow at full reverse voltage. If the reverse cur-
rent times reverse voltage exceeds the maximum allow-
able power dissipation, the diode may be damaged. For
best results, use an ultrafast recovery diode such as the
MMDL770T1.
ꢀ
FB1 ꢃ
FB2 ꢄ
R
R
VOUT = 0.8V 1+
ꢂ
ꢅ
ꢁ
The external resistor divider is connected to the output as
shownintheFunctionalDiagram, allowingremotevoltage
sensing. The resultant feedback signal is compared with
the internal precision 800mV voltage reference by the
error amplifier. The internal reference has a guaranteed
tolerance of less than 1%. Tolerance of the feedback
resistors will add additional error to the output voltage.
0.1% to 1% resistors are recommended.
Bottom MOSFET Driver Return Supply (BGRTN)
The bottom gate driver, BG, switches from DRV to
CC
BGRTN where BGRTN can be a voltage between ground
and –5V. Why not just keep it simple and always connect
BGRTN to ground? In high voltage switching converters,
the switch node dV/dt can be many volts/ns, which will
pull up on the gate of the bottom MOSFET through its
Miller capacitance. If this Miller current, times the internal
gate resistance of the MOSFET plus the driver resistance,
exceeds the threshold of the FET, shoot-through will oc-
cur. By using a negative supply on BGRTN, the BG can be
pulledbelowgroundwhenturningthebottomMOSFEToff.
This provides a few extra volts of margin before the gate
reaches the turn-on threshold of the MOSFET. Be aware
Input Voltage Undervoltage Lockout
A resistor divider connected from the input supply to the
UVIN pin (see Functional Diagram) is used to program the
input supply undervoltage lockout thresholds. When the
rising voltage at UVIN reaches 0.88V the LTC3810 turns
on, and when the falling voltage at UVIN drops below 0.8V,
the LTC3810 is shut down—providing 10% hysterisis.
The input voltage UVLO thresholds are set by the resistor
divider according to the following formulas:
that the maximum voltage difference between DRV and
CC
BGRTNis14V. If, forexample, V
=–2V, themaximum
BGRTN
V
= 0.8V (1 + R /R
)
IN,FALLING
UV1 UV2
voltage on DRV pin is now 12V instead of 14V.
CC
and
IC/MOSFET Driver Supplies (INTV and DRV )
CC
CC
V
= 0.88V (1 + R /R
)
IN,RISING
UV1 UV2
The LTC3810-5 drivers are supplied from the DRV
CC
If input supply undervoltage lockout is not needed, it can
be disabled by connecting UVIN to INTV .
and BOOST pins (see Figure 2), which have an absolute
CC
maximum voltage of 14V. Since the main supply voltage,
38105fc
20
LTC3810-5
APPLICATIONS INFORMATION
V is typically much higher than 14V a separate supply
current I
is greater than 270μA by using the follow-
IN
NDRV
ing formulas:
for the IC power (INTV ) and driver power (DRV ) must
CC
CC
be used. The LTC3810-5 has integrated bias supply con-
PMOSFET(MAX) /ICC − VTH
270μA
trol circuitry that allows the IC/driver supply to be easily
RNDRV
≤
generated from V and/or V
with minimal external
IN
OUT
components. There are four ways to do this as shown in
the simplified schematics of Figure 3 and explained in the
following sections.
where
I =(f) QG(TOP) +QG(BOTTOM) + 3mA
(
)
CC
and V is the threshold voltage of the MOSFET.
Using the Linear Regulator for INTV /DRV Supply
TH
CC
CC
The value of R
also affects the V
as follows:
In Mode 1, a small external SOT23 MOSFET, controlled
by the NDRV pin, is used to generate a 5.5V start-up
NDRV
IN(MIN)
NDRV
V
= V
+ (40μA) R
+V
(1)
IN(MIN)
INTVCC(MIN)
T
supply from V . The small SOT23 package can be used
IN
where V
is normally 4.5V for driving logic-level
becausetheNMOSisoncontinuouslyonlyduringthebrief
start-up period. As soon as the output voltage reaches
4.7V, the LTC3810-5 turns off the external NMOS and the
INTVCC(MIN)
MOSFETs. If minimum V is not low enough, consider
IN
reducing R
and/or using a Darlington NPN instead
NDRV
of an NMOS to reduce V to ~1.4V.
LTC3810-5 regulates the 5.5V supply from the EXTV
T
CC
pin (connected to V
or a V
derived boost network)
OUT
OUT
When using R
LTC3810-5 will enable the low duty cycle soft-start re-
tries only when the desired maximum power dissipation,
equal to the computed value, the
NDRV
throughaninternallowdropoutregulator.Forthismodeto
workproperly,EXTV mustbeintherange4.7V<EXTV
CC
CC
< 15V. If V
< 4.7V, a charge pump or extra winding can
OUT
P
, in the MOSFET is exceeded and leave the
MOSFET(MAX)
be used to raise EXTV to the proper voltage, or alter-
CC
drivers on continuously otherwise. The shutoff/restart
times are a function of the TRACK/SS capacitor value.
natively, Mode 2 should be used as explained later in this
section. If V
is shorted or otherwise goes below the
OUT
minimum 4.5V threshold, the MOSFET connected to V
The external NMOS for the linear regulator should be a
standard3Vthresholdtype(i.e.,notalogic-levelthreshold).
IN
is turned back on to maintain the 5.5V supply. However if
the output cannot be brought up within a timeout period,
the drivers are turned off to prevent the SOT23 MOSFET
from overheating. Soft-start cycles are then attempted at
low duty cycle intervals to try to bring the output back up
(see Figure 10). This fault timeout operation is enabled
The rate of charge of INTV from 0V to 5.5V is controlled
CC
by the LTC3810-5 to be approximately 75μs regardless of
the size of the capacitor connected to the INTV pin. The
CC
charging current for this capacitor is approximately:
ꢀ
ꢂ
ꢃ
ꢅ
5.5V
ꢁ 75μsꢄ
by choosing the choosing R
such that the resistor
NDRV
IC =
CINTVCC
FAULT TIMEOUT
DRIVER OFF THRESHOLD
ENABLED
DRIVER POWER
FROM V
OUT
I
= 1.4μA (SOURCE)
I
SS/TRACK
SS/TRACK
DRIVER POWER
DRIVER POWER
FROM V
FROM V
= 0.1μA (SINK)
IN
IN
SS/TRACK
START-UP
EXTV UV THRESHOLD
CC
V
OUT
SHORT-CIRCUIT EVENT
START-UP INTO SHORT-CIRCUIT
TG/BG
38105 F10
Figure 10. Fault Timeout Operation
38105fc
21
LTC3810-5
APPLICATIONS INFORMATION
The safe operating area (SOA) for the external NMOS
should be chosen so that capacitor charging does not
damage the NMOS. Excessive values of capacitor are
unnecessary and should be avoided. Typically values in
the 1μF to 10μF work well.
by the driver current I . In order to ensure proper start-
G
up, C
/C
must be chosen large enough so that
INTVCC DRVCC
the EXTV voltage reaches the switchover threshold of
CC
4.7V before C
UV threshold of 4V. This is ensured if:
/C
discharges below the falling
INTVCC DRVCC
Onemoredesignrequirementforthismodeistheminimum
soft-start capacitor value. The fault timeout is enabled
when SS/TRACK voltage is greater than 4V. This gives the
power supply time to bring the output up before it starts
the timeout sequence. To prevent timeout sequence from
C
INTVCC +CDRVCC
>
COUT
IMAX
5.5•105 •CSS
VOUT(REG)
ꢀ
ꢂ
ꢁ
ꢃ
ꢅ
ꢄ
I • larger of
or
G
Where I is the gate drive current = (f)(Q
G(BOTTOM)
selected by V
+
G(TOP)
startingprematurelyduringstart-up,aminimumC value
G
SS
Q
) and I
RNG
is the maximum inductor current
is necessary to ensure that V
< 4V until V
MAX
SS/TRACK
> 4.7V. To ensure this, choose:
EXTVCC
.
–6
For R
, the value should fall in the following range
C
> C
• (2.3 • 10 )/I
PULLUP
to ensure proper start-up:
SS
OUT
OUT(MAX)
Mode 2 should be used if V
is outside of the 4.7V <
OUT
Min R > (V
– 14V)/I
EXTV < 15V operating range and the extra complexity
PULLUP
IN(MAX)
CCSR
CC
of a charge pump or extra inductor winding is not wanted
Max R
< (V
– 9V)/I
IN(MIN) Q,SHUTDOWN
PULLUP
to boost this voltage above 4.7V. In this mode, EXTV is
CC
grounded and the NMOS is chosen to handle the worst-
Using an External Supply Connected to the INTV /
CC
case power dissipation:
DRV Pins
CC
ꢀ
ꢂ
If an external supply is available between 4.5V and 14V,
PMOSFET = V
f QG(TOP) +QG(BOTTOM) + 3mA
( )
(
)
(
)
IN(MAX)
ꢁ
ꢃ
the supply can be connected directly to the INTV /DRV
CC
CC
pins. In this mode, INTV , EXTV and NDRV must be
CC
CC
To operate properly, the fault timeout operation must be
disabled by choosing
shorted together.
R
> (V
– 5.5V – V )/270μA
NDRV
IN(MAX)
TH
INTV /DRV Supply and the EXTV Connection
CC
CC
CC
IftherequiredR
valueresultsinanunacceptablevalue
NDRV
The LTC3810-5 contains an internal low dropout regulator
toproducethe5.5VINTV /DRV supplyfromtheEXTV
for V
(see Equation 1), fault timeout operation can
IN(MIN)
CC
CC
CC
also be disabled by connecting a 500k to 1Meg resistor
from SS/TRACK pin to INTV .
pin voltage. This regulator turns on when the EXTV pin
CC
CC
is above 4.7V and remains on until EXTV drops below
CC
4.45V. This allows the IC/MOSFET power to be derived
Using Trickle Charge Mode
fromtheoutputoranoutputderivedboostnetworkduring
normal operation and from the external NMOS from V
Trickle charge mode is selected by shorting NDRV and
INTV and connecting EXTV to V . Trickle charge
IN
during start-up or short-circuit. Using the EXTV pin in
CC
CC
CC
OUT
this way results in significant efficiency gains compared
mode has the advantage of not requiring an external
MOSFET but takes longer to start up due to slow charge
to what would be possible when deriving this power
continuously from the typically much higher V voltage.
up of C
• R
and C
DRVCC
through R
(t
= 0.77
IN
INTVCC
DRVCC
PULLUP DELAY
The EXTV connection also allows the power supply to
• C
) and usually requires larger INTV /
CC
PULLUP
CC
be configured in trickle charge mode in which it starts up
DRV capacitor values to hold up the supply voltage dur-
CC
with a high valued “bleed” resistor connected from V
ing start-up. Once the INTV /DRV voltage reaches the
IN
CC
CC
to INTV to charge up the INTV capacitor. As soon as
trickle charge UV threshold of 9V, the drivers will turn on
CC
CC
the output rises above 4.7V the internal EXTV regulator
and start discharging C
/C
at a rate determined
CC
INTVCC DRVCC
38105fc
22
LTC3810-5
APPLICATIONS INFORMATION
takes over before the INTV capacitor discharges below
FEEDBACK LOOP/COMPENSATION
Feedback Loop Types
CC
the UV threshold. When the EXTV regulator is active,
CC
the EXTV pin can supply up to 50mA RMS. Do not ap-
CC
ply more than 15V to the EXTV pin. The following list
CC
In a typical LTC3810-5 circuit, the feedback loop con-
sists of the modulator, the output filter and load, and the
feedback amplifier with its compensation network. All of
these components affect loop behavior and must be ac-
counted for in the loop compensation. The modulator and
output filter consists of the internal current comparator,
the output MOSFET drivers and the external MOSFETs,
inductor and output capacitor. Current mode control
eliminates the effect of the inductor by moving it to the
inner loop, reducing it to a first order system. From a
feedback loop point of view, it looks like a linear voltage
summarizes the possible connections for EXTV :
CC
1. EXTV grounded. This connection will require INTV
CC
CC
to be powered continuously from an external NMOS
from V resulting in an efficiency penalty as high as
IN
10% at high input voltages.
2. EXTV connected directly to V . This is the normal
CC
OUT
connection for 4.7V < V
< 15V and provides the
OUT
highest efficiency. The power supply will start up using
an external NMOS or a bleed resistor until the output
supply is available.
controlled current source from I to V
and has a gain
TH
OUT
3. EXTV connected to an output-derived boost network.
equal to (I
R
)/1.2V. It has fairly benign AC behavior
CC
OUT
MAX OUT
If V
< 4.7V. The low voltage output can be boosted
at typical loop compensation frequencies with significant
phase shift appearing at half the switching frequency. The
external output capacitor and load cause a first order roll
using a charge pump or flyback winding to greater
than 4.7V.
off at the output at the R
C
pole frequency, with
OUT OUT
4. EXTV connected to INTV . This is the required
CC
CC
the attendant 90° phase shift. This roll off is what filters
the PWM waveform, resulting in the desired DC output
voltage. The output capacitor also contributes a zero at
connection for EXTV if INTV is connected to an
CC
CC
external supply where the external supply is 4.5V <
< 15V.
V
EXT
the C
R
frequency which adds back the 90° phase
OUT ESR
Applications using large MOSFETs with a high input
voltage and high frequency of operation may result in a
and cancels the first order roll off.
So far, the AC response of the loop is pretty well out of the
user’s control. The modulator is a fundamental piece of
the LTC3810-5 design and the external output capacitor is
usually chosen based on the regulation and load current
requirements without considering the AC loop response.
The feedback amplifier, on the other hand, gives us a
handle with which to adjust the AC response. The goal is
to have 180° phase shift at DC (so the loop regulates), and
something less than 360° phase shift (preferably about
300°) at the point that the loop gain falls to 0dB, i.e., the
crossover frequency, with as much gain as possible at
frequencies below the crossover frequency. Since the
modulator/output filter is a first order system with maxi-
large EXTV pin current. Due to the LTC3810-5 thermally
CC
enhanced package, maximum junction temperature will
rarely be exceeded, however, it is good design practice
to verify that the maximum junction temperature rating
and RMS current rating are within the maximum limits.
Typically, most of the EXTV current consists of the
CC
MOSFET gates current. In continuous mode operation,
this EXTV current is:
CC
IEXTVCC = f QG(TOP) +QG(BOTTOM) + 3mA <50mA
(
)
The junction temperature can be estimated from the
equations given in Note 2 of the Electrical Characteristics
as follows:
mum of 90° phase shift (at frequencies below f /4) and
SW
the feedback amplifier adds another 90° of phase shift,
some phase boost is required at the crossover frequency
to achieve good phase margin. If the ESR zero is below the
crossover frequency, this zero may provide enough phase
T = T + I
• (V
– V )(34°C/W)
INTVCC
J
A
EXTVCC
EXTVCC
< 125°C
Ifabsolutemaximumratingsareexceeded,considerusing
an external supply connected directly to the INTV pin.
boost to achieve the desired phase margin and the only
CC
38105fc
23
LTC3810-5
APPLICATIONS INFORMATION
requirement of the compensation will be to guarantee that
Feedback Component Selection
the gain is below zero at frequencies above f /4. If the
SW
Selecting the R and C values for a typical Type 2 or Type 3
loop is a nontrivial task. The applications shown in this
data sheet show typical values, optimized for the power
components shown. They should give acceptable perfor-
mancewithsimilarpowercomponents,butcanbewayoffif
evenonemajorpowercomponentischangedsignificantly.
Applicationsthatrequireoptimizedtransientresponsewill
requirerecalculationofthecompensationvaluesspecifically
for the circuit in question. The underlying mathematics are
complex, but the component values can be calculated in
a straightforward manner if we know the gain and phase
of the modulator at the crossover frequency.
ESR zero is above the crossover frequency, the feedback
amplifierwillprobablyberequiredtoprovidephaseboost.
FormostLTC3810-5applications,Type2compensationwill
provide enough phase boost; however some applications
where high bandwidth is required with low ESR ceramics
and lots of bulk capacitance, Type 3 compensation may
be necessary to provide additional phase boost.
The two types of compensation networks, “Type 2” and
“Type 3” are shown in Figures 11 and 12. When compo-
nent values are chosen properly, these networks provide
a “phase bump” at the crossover frequency. Type 2 uses
a single pole-zero pair to provide up to about 60° of phase
boostwhileType3usestwopolesandtwozerostoprovide
up to 150° of phase boost.
Modulator gain and phase can be obtained in one of
three ways: measured directly from a breadboard, or if
the appropriate parasitic values are known, simulated or
generated from the modulator transfer function. Mea-
surement will give more accurate results, but simulation
or transfer function can often get close enough to give
a working system. To measure the modulator gain and
phase directly, wire up a breadboard with an LTC3810-5
and the actual MOSFETs, inductor and input and output
capacitors that the final design will use. This breadboard
should use appropriate construction techniques for high
speed analog circuitry: bypass capacitors located close
to the LTC3810-5, no long wires connecting components,
appropriately sized ground returns, etc. Wire the feedback
C2
C1
IN
R2
–6dB/OCT
GAIN
R
R
FB1
FB
–6dB/OCT
–
OUT
0
FREQ
–90
FB2
V
+
REF
–180
–270
–360
PHASE
38105 F11
Figure 11. Type 2 Schematic and Transfer Function
amplifier with a 0.1μF feedback capacitor from I to FB
TH
and a 10k to 100k resistor from V
to FB. Choose the
OUT
IN
C2
bias resistor (R ) as required to set the desired output
FB2
C1
C3
R3
R2
voltage. Disconnect R from ground and connect it to
FB2
R
FB1
–6dB/OCT
GAIN
a signal generator or to the source output of a network
FB
–
+6dB/OCT
–6dB/OCT
analyzer to inject a test signal into the loop. Measure the
OUT
0
FREQ
R
FB2
gain and phase from the I pin to the output node at the
TH
–90
V
+
REF
positive terminal of the output capacitor. Make sure the
–180
–270
–360
PHASE
analyzer’s input is AC coupled so that the DC voltages
present at both the I and V
nodes don’t corrupt the
TH
OUT
38105 F12
measurements or damage the analyzer.
Figure 12. Type 3 Schematic and Transfer Function
If breadboard measurement is not practical, a SPICE
simulationcanbeusedtogenerateapproximategain/phase
curves.Plugtheexpectedcapacitor,inductorandMOSFET
values into the following SPICE deck and generate an AC
plot of V /V with gain in dB and phase in degrees.
OUT ITH
38105fc
24
LTC3810-5
APPLICATIONS INFORMATION
Refer to your SPICE manual for details of how to generate
this plot.
*3810-5 modulator gain/phase
*2006 Linear Technology
*this file simulates a simplified model of
*the LTC3810-5 for generating a v(out)/
v(ith)
GAIN
0
0
–90
PHASE
*bode plot
.param rdson=.0135 ;MOSFET rdson
–180
FREQUENCY (Hz)
38105 F13
.param Vrng=2
;use 1.4 for INTVCC and
0.7 for ground
Figure 13. Transfer Function of Buck Modulator
.param vsnsmax={0.173*Vrng-0.026}
.param Imax={vsnsmax/rdson}
(PHASE, in degrees) at this point. The desired feedback
amplifier gain will be –GAIN to make the loop gain at 0dB
at this frequency. Now calculate the needed phase boost,
assuming 60° as a target phase margin:
.param DL=4
;inductor ripple current
*inductor current
gl out 0 value={(v(ith)-1.2)*Imax/1.2+DL/2}
BOOST = – (PHASE + 30°)
*output cap
cout out out2 270u ;capacitor value
resr out2 0 0.018 ;capacitor ESR
If the required BOOST is less than 60°, a Type 2 loop can
be used successfully, saving two external components.
BOOST values greater than 60° usually require Type 3
loops for satisfactory performance.
*load
Rout out 0 2 ; load resistor
Finally, choose a convenient resistor value for R (10k is
FB1
vstim ith 0 0 ac 1 ;ac stimulus
usually a good value). Now calculate the remaining values:
.ac dec 100 100 10meg
.probe
.end
(K is a constant used in the calculations)
f = chosen crossover frequency
Mathematical software such as MATHCAD or MATLAB
can also be used to generate plots using the following
transfer function of the modulator:
(GAIN/20)
G = 10
(this converts GAIN in dB to G in
absolute gain)
TYPE 2 Loop:
ꢀ
SENSE(MAX) ꢃ
V
ꢀ
OUT ꢃ
1+ s •RESR •C
1+ s •RL •COUT
ꢄ
(2)
•RL
ꢅ
H(s) =
•
ꢅ
BOOST
ꢀ
ꢁ
ꢃ
ꢄ
ꢂ
ꢂ
1.2•R
K = tan
+ 45°
ꢁ
ꢁ
ꢄ
DS(ON)
ꢂ
ꢅ
2
1
s= j2ꢆf
C2=
2ꢆ • f •G•K •RFB1
Withthegain/phaseplotinhand,aloopcrossoverfrequency
can be chosen. Usually the curves look something like
Figure 13. Choose the crossover frequency about 25%
of the switching frequency for maximum bandwidth. Al-
C1=C2 K2 ꢇ1
(
)
K
R2=
2ꢆ • f •C1
though it may be tempting to go beyond f /4, remember
SW
that significant phase shift occurs at half the switching
frequency that isn’t modeled in the above H(s) equation
and PSPICE code. Note the gain (GAIN, in dB) and phase
VREF(RFB1)
RFB2
=
VOUT ꢇ VREF
38105fc
25
LTC3810-5
APPLICATIONS INFORMATION
TYPE 3 Loop:
For SPICE, replace VSTIM line in the previous PSPICE
code with following code and generate a gain/phase plot
of V(out)/V(outin):
BOOST
4
1
ꢀ
ꢁ
ꢃ
ꢄ
K = tan2
+ 45°
ꢂ
ꢅ
rfb1 outin vfb 52.5k
rfb2 vfb 0 10k
C2=
2ꢆ • f •G•RFB1
C1=C2 K ꢇ1
eithx ithx 0 laplace {0.8-v(vfb)} =
{1/(1+s/1000)}
(
)
eith ith 0 value={limit(1e6*v(ithx),0,2.4)}
cc1 ith vfb 4p
K
R2=
R3=
C3=
2ꢆ • f •C1
cc2 ith x1 8p
RFB1
rc x1 vfb 210k
K ꢇ1
rf outin x2 11k ;delete this line for Type 2
cf x2 vfb 120p ;delete this line for Type 2
vstim out outin dc=0 ac=1m
1
2ꢆf K • R3
VREF(RFB1)
Pulse Skip Mode Operation and MODE/SYNC Pin
RB =
VOUT ꢇ VREF
The MODE/SYNC pin determines whether the bottom
MOSFETremainsonwhencurrentreversesintheinductor.
Tying this pin above its 0.8V threshold enables pulse skip
modeoperationwherethebottomMOSFETturnsoffwhen
inductorcurrentreverses.Theloadcurrentatwhichcurrent
reverses and discontinuous operation begins depends on
the amplitude of the inductor ripple current and will vary
SPICE or mathematical software can be used to generate
the gain/phase plots for the compensated power supply to
do a sanity check on the component values before trying
them out on the actual hardware. For software, use the
following transfer function:
T(s) = A(s)H(s)
with changes in V . Tying the MODE/SYNC pin below the
IN
0.8Vthresholdforcescontinuoussynchronousoperation,
allowing current to reverse at light loads and maintain-
ing high frequency operation. To prevent forcing current
back into the main power supply, potentially boosting the
input supply to a dangerous voltage level, forced continu-
ous mode of operation is disabled when the TRACK/SS
voltage is below the reference voltage during soft-start
or tracking. During these two periods, the PGOOD signal
is forced low.
where H(s) was given in Equation 2 and A(s) depends on
compensation circuit used:
Type 2:
1+ s •R3•C2
A (s)=
C2 •C3
C2+C3
ꢀ
ꢃ
ꢄ
s •RFB1 • C2+C3 • 1+ s •R3•
(
)
ꢂ
ꢅ
ꢁ
Type 3:
A (s)=
Table 1
1
•
MODE/SYNC PIN
CONDITION
s •RFB1 • C2+C3
(
)
DC Voltage: 0V to 0.75V
Forced Continuous
Current Reversal Enabled
1+ s • R +R3 •C3 • 1+ s •R2•C1
(
)
(
)
(
)
FB1
DC Voltage: ≥ 0.85V
Pulse Skip Mode Operation
No Current Reversal
C1• C2
ꢀ
ꢃ
ꢅ
1+ s •R3•C3 • 1+ s •R2•
(
)
ꢂ
ꢁ
ꢄ
C1+C2
Feedback Resistors
Ext. Clock 0V to ≥ 2V
Regulating a Secondary Winding
Forced Continuous
Current Reversal Enabled
38105fc
26
LTC3810-5
APPLICATIONS INFORMATION
ent temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
V
C
IN
+
IN
V
IN
1N4148
temperature and the resulting value of I
which heats
LIMIT
V
TG
OUT2
OUT1
•
the MOSFET switches.
+
+
C
OUT2
LTC3810-5
1μF
Caution should be used when setting the current limit
based upon the R of the MOSFETs. The maximum
V
SW
R4
R3
•
T1
1:N
DS(ON)
C
FCB
OUT
current limit is determined by the minimum MOSFET
on-resistance. Data sheets typically specify nominal
BG
SGND
PGND
38105 F14
and maximum values for R
, but not a minimum.
DS(ON)
A reasonable assumption is that the minimum R
DS(ON)
lies the same percentage below the typical value as the
maximumliesaboveit.ConsulttheMOSFETmanufacturer
for further guidelines.
Figure 14. Secondary Output Loop
In addition to providing a logic input to force continu-
ous operation, the MODE/SYNC pin provides a mean to
maintain a flyback winding output when the primary is
To further limit current in the event of a short-circuit to
ground, the LTC3810-5 includes foldback current limiting.
If the output falls by more than 50%, then the maximum
sense voltage is progressively lowered to about one-tenth
of its full value.
operatinginpulseskipmode.ThesecondaryoutputV
OUT2
is normally set as shown in Figure 14 by the turns ratio
N of the transformer. However, if the controller goes into
pulse skip mode and halts switching due to a light primary
Be aware also that when the fault timeout is enabled for
the external NMOS regulator, an over current limit may
cause the output to fall below the minimum 4.5V UV
threshold. This condition will cause a linear regulator
timeout/restartsequenceasdescribedintheLinearRegula-
tor Timeout section if this condition persists.
load current, then V
will droop. An external resistor
OUT2
dividerfromV
totheMODE/SYNCpinsetsaminimum
below which continuous operation is
has risen above its minimum.
OUT2
OUT2(MIN)
voltage V
forced until V
OUT2
R4
R3
ꢀ
ꢁ
ꢃ
ꢄ
VOUT2(MIN) = 0.8V 1+
ꢂ
ꢅ
Soft-Start and Tracking
The LTC3810-5 has the ability to either soft-start by itself
with a capacitor or track the output of another supply.
When the device is configured to soft-start by itself, a
capacitor should be connected to the TRACK/SS pin. The
LTC3810-5 is put in a low quiescent current shutdown
Fault Conditions: Current Limit and Foldback
The maximum inductor current is inherently limited in a
currentmodecontrollerbythemaximumsensevoltage.In
the LTC3810-5, the maximum sense voltage is controlled
state (I ~240μA) if the SHDN pin voltage is below 1.5V.
bythevoltageontheV
pin. Withvalleycurrentcontrol,
Q
RNG
The TRACK/SS pin is actively pulled to ground in this
shutdown state. Once the SHDN pin voltage is above
1.5V, the LTC3810-5 is powered up. A soft-start current
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
of 1.4μA then starts to charge the soft-start capacitor C .
SS
VSNS(MAX)
1
Note that soft-start is achieved not by limiting the maxi-
mum output current of the controller but by controlling
the ramp rate of the output voltage. Current foldback is
disabled during this soft-start phase. During the soft-start
phase, the LTC3810-5 is ramping the reference voltage
ILIMIT
=
+ ΔIL
2
RDS(ON) ρT
The current limit value should be checked to ensure that
>I .Theminimumvalueofcurrentlimit
I
LIMIT(MIN) OUT(MAX)
generally occurs with the largest V at the highest ambi-
until it reaches 0.8V. The force continuous mode is also
IN
38105fc
27
LTC3810-5
APPLICATIONS INFORMATION
disabledandPGOODsignalisforcedlowduringthisphase.
The total soft-start time can be calculated as:
To implement the coincident tracking in Figure 15a, con-
nectanadditionalresistivedividertoV andconnectits
OUT1
midpoint to the TRACK/SS pin of the slave IC. The ratio of
thisdividershouldbeselectedthesameasthatoftheslave
IC’s feedback divider shown in Figure 16. In this tracking
t
= 0.8 • C /1.4μA
SS
SOFTSTART
When the device is configured to track another supply,
the feedback voltage of the other supply is duplicated
by a resistor divider and applied to the TRACK/SS pin.
Therefore, the voltage ramp rate on this pin is determined
by the ramp rate of the other supply output voltage.
mode, V
mustbesethigherthanV
. Toimplement
OUT1
OUT2
the ratiometric tracking, the ratio of the divider should be
exactly the same as the master IC’s feedback divider. Note
that the internal soft-start current will introduce a small
error on the tracking voltage depending on the absolute
values of the tracking resistive divider.
Output Voltage Tracking
The LTC3810-5 allows the user to program how its out-
put ramps up by means of the TRACK/SS pin. Through
this pin, the output can be set up to either coincidentally
or ratiometrically track with another supply’s output, as
Byselectingdifferentresistors,theLTC3810-5canachieve
different modes of tracking including the two in Figure 15.
So which mode should be programmed? While either
mode in Figure 15 satisfies most practical applications,
theredoexistsometradeoffs. Theratiometricmodesaves
a pair of resistors, but the coincident mode offers better
output regulation. This can be better understood with the
shown in Figure 15. In the following discussions, V
OUT1
refers to the master LTC3810-5’s output and V
to the slave LTC3810-5’s output.
refers
OUT2
V
V
V
V
OUT1
OUT1
OUT2
OUT2
38105 F15
TIME
TIME
(15a) Coincident Tracking
(15b) Ratiometric Tracking
Figure 15. Two Different Modes of Output Voltage Tracking
V
OUT1
V
OUT1
V
V
OUT2
OUT2
R3
R4
R1
R2
R3
R4
R1
R2
R3
R4
TO
TO
FB1
PIN
TO
FB2
PIN
TO
FB2
PIN
TO
TO
FB1
PIN
TRACK/SS2
PIN
V
V
V
TRACK/SS2
PIN
V
38105 F16
(16a) Coincident Tracking Setup
(16b) Ratiometric Tracking Setup
Figure 16. Setup for Coincident and Ratiometric Tracking
38105fc
28
LTC3810-5
APPLICATIONS INFORMATION
The internal oscillator locks to the external clock after
the second clock transition is received. When external
synchronization is detected, LTC3810-5 will operate in
forced continuous mode. If an external clock transition
is not detected for three successive periods, the internal
oscillator will revert to the frequency programmed by the
I
I
+
–
D1
D2
EA2
TRACK/SS2
0.8V
D3
R
resistor.
ON
38105 F17
V
FB2
During the start-up phase, phase-locked loop function is
disabled.WhenLTC3810-5isnotinsynchronizationmode,
PLL/LPF pin voltage is set to around 1.215V. Frequency
synchronization is accomplished by changing the internal
on-time current according to the voltage on the PLL/LPF
pin.
Figure 17. Equivalent Input Circuit of Error Amplifier
help of Figure 17. At the input stage of the slave IC’s error
amplifier, two common anode diodes are used to clamp
the equivalent reference voltage and an additional diode
is used to match the shifted common mode voltage. The
top two current sources are of the same amplitude. In the
coincident mode, the TRACK/SS voltage is substantially
higher than 0.8V at steady state and effectively turns off
D1. D2 and D3 will therefore conduct the same current
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the ex-
ternal and internal pulses. This type of phase detector will
not lock up on input frequencies close to the harmonics
of the V center frequency. The PLL hold-in range, Δf ,
CO
H
and offer tight matching between V
and the internal
FB2
is equal to the capture range, Δf
C:
precision0.8Vreference.Intheratiometricmode,however,
TRACK/SS equals 0.8V at steady state. D1 will divert part
Δf = Δf = 0.3 f
O
H
C
of the bias current to make V slightly lower than 0.8V.
FB2
Theoutputofthephasedetectorisacomplementarypairof
current sources charging or discharging the external filter
network on the PLL/LPF pin. A simplified block diagram
is shown in Figure 18.
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a finite amount
ofoutputvoltagedeviation.Furthermore,whenthemaster
IC’s output experiences dynamic excursion (under load
transient, for example), the slave IC output will be affected
as well. For better output regulation, use the coincident
tracking mode instead of ratiometric.
R
LP
2.4V
C
LP
PLL/LPF
VCO
Phase-Locked Loop and Frequency Synchronization
DIGITAL
MODE/SYNC
The LTC3810-5 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range
of the voltage controlled oscillator is 30% around the
PHASE/
FREQUENCY
DETECTOR
center frequency f . The center frequency is the operating
38105 F18
O
frequency discussed in the Operating Frequency section.
The LTC3810-5 incorporates a pulse detection circuit that
will detect a clock on the MODE/SYNC pin. In turn, it will
turn on the phase-locked loop function. The pulse width of
the clock has to be greater than 400ns and the amplitude
of the clock should be greater than 2V.
Figure 18. Phase-Locked Loop Block Diagram
38105fc
29
LTC3810-5
APPLICATIONS INFORMATION
If the external frequency (f
) is greater than the
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the
inputvoltage,loadcurrent,driverstrengthandMOSFET
capacitance,amongotherfactors.Thelossissignificant
at input voltages above 20V and can be estimated from
MODE
oscillator frequency f , current is sourced continuously,
O
pulling up the PLL/LPF pin. When the external frequency
is less than f , current is sunk continuously, pulling down
O
the PLL/LPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus the voltage on the PLL/LPF
pin is adjusted until the phase and frequency of the ex-
ternal and internal oscillators are identical. At this stable
operating point the phase comparator output is open and
thesecondtermoftheP
equationfoundinthePower
MAIN
MOSFET Selection section. When transition losses are
significant, efficiency can be improved by lowering the
frequency and/or using a top MOSFET(s) with lower
C
RSS
at the expense of higher R
.
DS(ON)
the filter capacitor C holds the voltage. The LTC3810-5
LP
3. INTV /DRV current. This is the sum of the MOSFET
CC
CC
MODE/SYNC pin must be driven from a low impedance
driver and control currents. Control current is typically
source such as a logic gate located close to the pin.
about3mAanddrivercurrentcanbecalculatedby:I
GATE
are
The loop filter components (C , R ) smooth out the
= f(Q
+ Q
), where Q
and Q
LP LP
G(TOP)
G(BOT)
G(TOP)
G(BOT)
current pulses from the phase detector and provide a
the gate charges of the top and bottom MOSFETs. This
loss is proportional to the supply voltage that INTV /
stable input to the voltage controlled oscillator. The filter
CC
components C and R determine how fast the loop
DRV is derived from, i.e., V for the external NMOS
LP
LP
CC
IN
acquires lock. Typically R = 10kΩ and C is 0.01μF
linear regulator, V
for the internal EXTV regula-
LP
LP
OUT CC
to 0.1μF.
tor, or V
when an external supply is connected to
EXT
INTV /DRV .
CC
CC
Efficiency Considerations
4. C loss. The input capacitor has the difficult job of fil-
IN
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3810-5 circuits:
tering the large RMS input current to the regulator. It
2
must have a very low ESR to minimize the AC I R loss
and sufficient capacitance to prevent the RMS current
from causing additional upstream losses in fuses or
batteries.
Other losses, including C
ESR loss, Schottky diode D1
OUT
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss. When
making adjustments to improve efficiency, the input cur-
rent is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
2
1. DC I R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiencytodropathighoutputcurrents. Incontinuous
modetheaverageoutputcurrentflowsthroughL, butis
choppedbetweenthetopandbottomMOSFETs.Ifthetwo
MOSFETs have approximately the same R
, then
DS(ON)
the resistance of one MOSFET can simply be summed
with the resistances of L and the board traces to obtain
Checking Transient Response
2
the DC I R loss. For example, if R
L
= 0.01Ω and
DS(ON)
The regulator loop response can be checked by look-
ing at the load transient response. Switching regulators
take several cycles to respond to a step in load current.
R = 0.005Ω, the loss will range from 15mW to 1.5W
as the output current varies from 1A to 10A.
38105fc
30
LTC3810-5
APPLICATIONS INFORMATION
When load step occurs, V
immediately shifts by an
V
= 320mV, assume a junction temperature of about
OUT
SNS
amount equal to ΔI
(ESR), where ESR is the effective
55°C above a 70°C ambient (ρ
= 1.7):
125°C
LOAD
series resistance of C . ΔI
also begins to charge or
OUT LOAD
generatingafeedbackerrorsignalusedby
320mV
1.7 •0.031Ω 2
1
dischargeC
ILIMIT
≥
+ •2.4A = 7.3A
OUT
theregulatortoreturnV toitssteady-statevalue.During
OUT
this recovery time, V
can be monitored for overshoot
OUT
and double-check the assumed T in the MOSFET:
J
or ringing that would indicate a stability problem.
60V − 5V
P
=
•7.3A2 •1.7 •0.031Ω= 2.6W
Design Example
BOT
60V
As a design example, take a supply with the following
T = 70°C + 2.6W • 22°C/W = 127°C
J
specifications:V =12Vto60V, V
=5V 5%, I
IN
OUT
OUT(MAX)
= 6A, f = 250kHz. First, calculate the timing resistor:
Verify that the Si7850DP is also a good choice for the top
MOSFET by checking its power dissipation at current limit
andmaximuminputvoltage,assumingajunctiontempera-
5V
RON
=
=110k
2.4V •250kHz •76pF
ture of 30°C above a 70°C ambient (ρ
= 1.5):
100°C
and choose the inductor for about 40% ripple current at
5V
60V
7.3A
the maximum V :
PMAIN
=
•7.3A2 1.5•0.031ꢀ
(
)
IN
1
1
ꢂ
ꢃ
ꢅ
ꢆ
5V
5V
60V
+60V2 •
•2ꢀ •183pF •
+
•250kHz
ꢁ
ꢂ
ꢄ
ꢅ
L =
1ꢀ
= 7.6μH
ꢄ
ꢇ
ꢃ
ꢆ
2
5V ꢁ 3.8V 3.8V
250kHz •0.4•6A
= 0.206W +1.32W =1.53W
With a 7.7μH inductor, ripple current will vary from 1.5A
to 2.4A (25% to 40%) over the input supply range.
T = 70°C + 1.53W • 22°C/W = 104°C
J
The junction temperature will be significantly less at
nominal current, but this analysis shows that careful at-
tention to heat sinking on the board will be necessary in
this circuit.
Next, choose the bottom MOSFET switch. Since the
drain of the MOSFET will see the full supply voltage 60V
(max) plus any ringing, choose an 60V MOSFET. The
Si7850DP has:
Since V
> 4.7V, the INTV voltage can be generated
CC
OUT
OUT
BV
DS(ON)
δ = 0.007/°C,
= 60V
DSS
from V
with the internal LDO by connecting V
to
OUT
R
= 31mΩ (max)/25mΩ (nom),
the EXTV pin. A small SOT23 MOSFET such as the
CC
ZXMN10A07F can be used for the pass device if fault
C
V
JA
= (8.3nC – 2.8nC)/30V = 183pF,
MILLER
GS(MILLER)
θ = 22°C/W.
timeout is enabled. Choose R
to guarantee that fault
NDRV
= 3.8V,
timeout is enabled when power dissipation of M3 exceeds
0.4W (max for 70°C ambient):
This yields a nominal sense voltage of:
I
= 250kHz • 2 • 18nC + 3mA = 12mA
CC
V
= 6A • 1.3 • 0.025Ω = 195mV
SNS(NOM)
0.4W / 0.012A – 3V
Toguaranteepropercurrentlimitatworst-caseconditions,
increase nominal V by at least 50% to 320mV (by tying
RNG
RNDRV
≤
=112k
270µA
SNS
V
to 2V). To check if the current limit is acceptable at
So, choose R
= 100k.
NDRV
38105fc
31
LTC3810-5
APPLICATIONS INFORMATION
C
is chosen for an RMS current rating of about 3A at
PC Board Layout Checklist
IN
85°C. The output capacitors are chosen for a low ESR
of 0.018Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
When laying out a PC board follow one of two suggested
approaches. The simple PC board layout requires a dedi-
cated ground plane layer. Also, for higher currents, it is
recommended to use a multilayer board to help with heat
sinking power components.
ΔV
= ΔI
• ESR = 2.4A • 0.018Ω
L(MAX)
OUT(RIPPLE)
= 43mV
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
However, a 0A to 6A load step will cause an output change
of up to:
ΔV
= ΔI
• ESR = 6A • 0.018Ω
LOAD
• Place C , C , MOSFETs, D1 and inductor all in one
OUT(STEP)
= 108mV
IN OUT
compact area. It may help to have some components
on the bottom side of the board.
An optional 10μF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 19.
•
Use an immediate via to connect the components to
groundplaneincludingSGNDandPGNDofLTC3810-5.
Use several bigger vias for power components.
V
IN
12V TO 60V
C
68μF
100V
R
NDRV
100k
IN1
R
ON
C
IN2
M3
110k
1μF
ZXMN10A07F
100V
C
ON
100pF
DB
BAS19
PGND
LTC3810
31
2
27
26
I
BOOST
ON
40.2k
60.4k
C
0.1μF
B
M1
TG
Si7852DP
V
V
ON
25
24
SW
3
4
5
6
7
8
RNG
+
SENSE
PGOOD
PGOOD
MODE_SYNC
L1
250kHz
CLOCK
10μH
V
5V
6A
OUT
20
19
–
SENSE
I
TH
0.01μF
V
BGRTN
10k
FB
C
0.1μF
C
OUT1
270μF
6.3V
PLL/LPF
DRVCC
C
SS
1000pF
R
UV1
18
17
M2
Si7852DP
BG
200k
C
9
OUT2
10μF
6.3V
DRV
CC
SS/TRACK
16
15
14
33
12
13
INTV
CC
EXTV
CC
NDRV
D1
SGND
SHDN
UVIN
B1100
SHDN
C5
1μF
C
VCC
R
14.3k
1μF
C
C2
47pF
UV2
SGND
PGND
C
C1
5pF
R
C
R
FB2
1.91k
R
200k
FB1
10k
38105 F19
Figure 19. 12V to 60V Input Voltage to 5V/6A Synchronized at 250kHz
38105fc
32
LTC3810-5
APPLICATIONS INFORMATION
• Use compact plane for switch node (SW) to improve
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
cooling of the MOSFETs and to keep EMI down.
•
Connect the input capacitor(s) C close to the pow-
er MOSFETs. This capacitor carries the MOSFET AC
current.
• Use planes for V and V
to maintain good voltage
OUT
IN
IN
filtering and to keep power losses low.
• Floodallunusedareasonalllayerswithcopper.Flooding
with copper will reduce the temperature rise of power
component. You can connect the copper areas to any
• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
DC net (V , V , GND or to any other DC rail in your
IN OUT
• Connect the INTV decoupling capacitor C
closely
CC
VCC
system).
to the INTV and SGND pins.
CC
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera-
tion of the controller.
• Connect the top driver boost capacitor C closely to
B
the BOOST and SW pins.
• ConnectthebottomdriverdecouplingcapacitorC
DRVCC
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to
the source of M2.
closely to the DRV and BGRTN pins.
CC
TYPICAL APPLICATIONS
7V to 60V Input Voltage to 5V/5A with IC Power from 12V Supply
and All Ceramic Output Capacitors
V
IN
7V TO 60V
C
68μF
100V
12V
IN1
R
ON
110k
C
IN2
1μF
C
DB
BAS19
ON
100V
100pF
LTC3810-5
31
27
PGND
I
BOOST
ON
C
B
0.1μF
26
M1
Si7850DP
TG
2
3
4
5
6
25
24
V
V
ON
SW
+
RNG
SENSE
PGOOD
PGOOD
MODE_SYNC
L1
4.7μH
V
5V
5A
OUT
20
19
–
I
SENSE
TH
R
UV1
470k
7
8
V
BGRTN
FB
C
OUT
C
PLL/LPF
DRVCC
C
47μF
6.3V
s3
SS
1000pF
0.1μF
18
17
M2
Si7850DP
BG
9
SS/TRACK
DRV
CC
16
15
14
33
12
13
SGND
SHDN
UVIN
INTV
EXTV
NDRV
D1
CC
CC
B1100
SHDN
C5
22μF
C
VCC
1μF
R
UV2
61.9k
SGND
PGND
C
C2
47pF
C
C1
R
5pF
C
R
FB2
1.91k
R
FB1
10k
100k
38105 TA03
38105fc
33
LTC3810-5
TYPICAL APPLICATIONS
15V to 60V Input Voltage to 3.3V/5A with Fault Timeout,
Pulse Skip and VIN UV Disabled
V
IN
15V TO 60V
C
68μF
100V
R
NDRV
274k
IN1
R
ON
C
IN2
M3
ZVN4210G
71.5k
1μF
100V
C
ON
DB
100pF
PGND
BAS19
LTC3810-5
31
27
26
I
BOOST
ON
C
B
0.1μF
M1
TG
Si7850DP
2
3
4
5
6
7
8
25
24
V
V
ON
SW
+
RNG
SENSE
PGOOD
PGOOD
L1
MODE_SYNC
4.7μH
V
3.3V
5A
OUT
20
19
–
I
V
SENSE
BGRTN
TH
FB
C
0.1μF
C
PLL/LPF
DRVCC
OUT1
C
270μF
6.3V
SS
M2
Si7850DP
18
17
1000pF
BG
C
9
OUT2
10μF
6.3V
SS/TRACK
DRV
CC
16
15
14
33
12
13
INTV
EXTV
D1
SGND
SHDN
UVIN
CC
CC
NDRV
B1100
SHDN
C5
1μF
C
1μF
VCC
C
SGND
PGND
C2
47pF
C
C1
R
C
200k
5pF
R
FB1
10.2k
R
FB2
3.24k
38105 TA04
38105fc
34
LTC3810-5
PACKAGE DESCRIPTION
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 p0.05
5.50 p0.05
4.10 p0.05
3.45 p 0.05
3.50 REF
(4 SIDES)
3.45 p 0.05
PACKAGE OUTLINE
0.25 p 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 s 45° CHAMFER
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
0.75 p 0.05
5.00 p 0.10
(4 SIDES)
31 32
0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.45 p 0.10
3.50 REF
(4-SIDES)
3.45 p 0.10
(UH32) QFN 0406 REV D
0.200 REF
0.25 p 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
38105fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC3810-5
TYPICAL APPLICATION
13V to 60V Input Voltage to 12V/10A with Trickle Charger Start-Up
V
IN
13V TO 60V
C
68μF
100V
R
IN1
NDRV
100k
R
ON
263k
C
IN2
1μF
C
DB
ON
100pF
100V
BAS19
LTC3810-5
27
26
31
BOOST
PGND
I
ON
C
B
0.1μF
M1
Si7850DP
TG
2
3
4
25
24
V
V
ON
SW
+
RNG
SENSE
PGOOD
PGOOD
L1
10μH
5
6
7
8
MODE_SYNC
V
12V
10A
OUT
–
20
19
I
TH
SENSE
R
UV1
V
FB
BGRTN
200k
C
DRVCC
0.1μF
C
OUT1
PLL/LPF
C
SS
1000pF
270μF
16V
M2
Si7850DP
s2
18
17
BG
DRV
CC
C
9
OUT2
10μF
16V
SS/TRACK
16
33
12
13
INTV
CC
D1
B1100
SGND
SHDN
UVIN
15
14
EXTV
SHDN
CC
C5
22μF
NDRV
C
VCC
1μF
R
UV2
C
C2
SGND
PGND
13.3k
47pF
C
C1
5pF
R
C
R
FB2
1k
R
FB1
14k
200k
38105 TA05
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
up to 60V, TO-220 and DD Packages
LT®1074HV/LT1076HV Monolithic 5A/2A Step-Down DC/DC Converters
V
IN
LTC1735
LTC1778
LT1956
Synchronous Step-Down DC/DC Controller
No R ™ Synchronous DC/DC Controller
3.5V ≤ V ≤ 36V, 0.8V ≤ V
≤ 6V, Current Mode, I
≤ 20A
IN
OUT
OUT
4V ≤ V ≤ 36V, Fast Transient Response, Current Mode, I ≤ 20A
OUT
SENSE
IN
Monolithic 1.5A, 500kHz Step-Down Regulator
50mA, 3V to 80V Linear Regulator
5.5V ≤ V ≤ 60V, 2.5mA Supply Current, 16-Pin SSOP
IN
LT3010
1.275V ≤ V
≤ 60V, No Protection Diode Required, 8-Lead MSOP
OUT
LT3430/LT3431
LT3433
Monolithic 3A, 200kHz/500kHz Step-Down Regulator
Monolithic Step-Up/Step-Down DC/DC Converter
100V Synchronous DC/DC Controller
5.5V ≤ V ≤ 60V, 0.1Ω Saturation Switch, 16-Pin SSOP
IN
4V ≤ V ≤ 60V, 500mA Switch, Automatic Step-Up/Step-Down,
IN
LTC3703
LT3800
V
IN
up to 100V, 9.3V to 15V Gate Drive Supply
High Voltage Synchronous Fixed
Frequency Step-Down Regulator Controller
V
up to 60V, I
≤ 20A, Current Mode, Onboard Bias Regulator,
OUT
IN
Low I , TSSOP-16
Q
LTC3810
LTC3812-5
LTC3824
LT3844
100V Current Mode Synchronous Step-Down Regulator
Controller
V
up to 100V, I
SENSE
≤ 20A, Constant On-Time, Synchronizable, No
OUT
IN
R
Required
No R
High Voltage Synchronous Step-Down
V
up to 60V, I
≤ 20A, Current Mode, Low I , External Bias
OUT Q
SENSE
IN
Controller
Regulator Control
up to 60V, I ≤ 7A, Current Mode, Low I , 200kHz to 600kHz
OUT Q
High Voltage Step-Down Controller with 100% Duty Cycle
V
IN
Fixed Frequency or Synchronizable, MSOP-10
V up to 60V, I ≤ 10A, Current Mode, Onboard Bias Regulator,
IN
Low I , TSSOP-16, Synchronizable
High Voltage Non-Synchronous Programmable Frequency
Step-Down Regulator Controller
OUT
Q
LT3845
High Voltage Synchronous Programmable Frequency
Step-Down Regulator Controller
V
up to 60V, I
Q
≤ 20A, Current Mode, Onboard Bias Regulator,
OUT
IN
Low I , TSSOP-16, Synchronizable
No R
is a registered trademark of Linear Technology Corporation.
SENSE
38105fc
LT 0608 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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