LTC3811EUHF-TRPBF_技术文档

LTC3811

High Speed Dual,

Multiphase Step-Down DC/DC

Controller

FEATURES

DESCRIPTION

The LTC^®3811 is a dual, PolyPhase^®synchronous step-

down switching regulator controller optimized for output

■

Fixed Frequency, Peak Current Mode Control

■

±±0.5 Output ꢀccuracy Oꢁer Temperature

■

Optimized for Low V

ꢀpplications (Up to 303V)

voltages up to 3.3V. The LTC3811 includes high bandwidth

error ampliﬁers as well as a high speed differential remote

sense ampliﬁer. The sense voltage range is programmable

from24mVto85mV,allowingtheuseofeithertheinductor

DCR or a discrete sense resistor. Multiphase operation is

made possible using the MODE/SYNC input, the CLKOUT

output and the PHASEMODE control pin, allowing 1-, 2-,

3-, 4-, 6- or 12-phase operation.

OUT

■

Dual or Single Output, Multiphase Operation

Wide V Range: 40.V to 3±V Operation

IN

High Speed Differential Remote Sense ꢀmpliﬁer

Inductor DCR or Sense Resistor Capable

ꢀdjustable Peak Current Sense Voltage:

24mV to 8.mV

■

Very Low Duty Cycle Operation: t

Powerful Internal Gate Drivers

Output Voltage Soft-Start, Tracking and Sequencing

Programmable Load Line for Reduced C

= 6.ns (Typ)

ON(MIN)

Large internal gate drivers minimize switching losses and

allow the use of multiple power MOSFETs connected in

parallel for high current applications.

OUT

Clock Input and Output for Up to 12-Phase Operation

Fixed Frequency Operation from 250kHz to 750kHz

PLL Synchronization from 150kHz Up to 900kHz

Selectable CCM or DCM Operation

TheoperatingfrequencyoftheLTC3811canbeprogrammed

from 250kHz to 750kHz and can also be synchronized to

an external clock using the internal PLL.

Available in 5mm × 7mm QFN and G36 Packages

Tracking and sequencing are possible with the LTC3811,

and soft-start is programmed with an external capacitor.

Shutdown reduces supply current to 20μA.

, LT, LTC, LTM and PolyPhase are registered trademarks of Linear Technology

Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 5481178, 6304066, 5929620, 6177787, 6144194,

6580258, 5705919.

APPLICATIONS

■

Network Servers

■

High Current ASIC Supplies

■

Low Voltage Power Distribution

TYPICAL APPLICATION

Dual Output, 2-Phase Tracking Core and I/O Supply

V

IN

Load Step

4.5V TO 14V

V

INTV

DRV

IN

CC

TG2

TG1

V

OUT

100mV/DIV

BOOST1

SW1

BOOST2

SW2

BG1

BG2

RUN1

RUN2

PGND

LTC3811

+

SENSE1

SENSE2

I

L

–

5A/DIV

SENSE1

RNG1

SENSE2

+

DIFF/IN

–

DIFF/IN

RNG2

FB1

DIFF/OUT

FB2

V

OUT1

2V

15A

3811 TA01b

V

1.5V

15A

OUT2

V

= 12V

20μs/DIV

IN

COMP1

COMP2

= 2V

OUT

SS/TRACK1 SGND SS/TRACK2

I

= 0A to 12.5A

3811 TA01a

3811f

1

LTC3811

ABSOLUTE MAXIMUM RATINGS ^{(Note 1)}

Input Supply Voltage (V )......................... –0.3V to 30V

FB1, FB2, RNG1, RNG2, SS/TRACK1, SS/TRACK2,

IN

+

–

+

Topside Driver Voltages

PLL/LPF, SENSE1 , SENSE1 , SENSE2 ,

–

(BOOST1, BOOST2)............................... –0.3V to 37V

Switch Voltage (SW1, SW2) ......................... –5V to 30V

SENSE2 Voltages................................. –0.3V to INTV

DRV LDO RMS Output Current.........................100mA

OperatingTemperature Range (Note 2)..... –40°C to 85°C

Junction Temperature (Note 3) ............................. 125°C

Storage Temperature Range................... –65°C to 125°C

Lead Temperature (Soldering, 10 sec)

CC

BOOST1 – SW1, BOOST2 – SW2................. –0.3V to 7V

+

DRV , INTV , EXTV , RUN1, RUN2, DIFF/IN ,

CC

–

DIFF/IN , PHASEMODE, PGOOD1, PGOOD2,

MODE/SYNC Voltages.................................. –0.3V to 7V

SSOP Package.................................................. 300°C

PIN CONFIGURATION

TOP VIEW

1

2

PGOOD2

PLL/LPF

MODE/SYNC

BOOST1

TG1

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

PGOOD1

RUN1

38 37 36 35 34 33 32

+

3

RUN2

+

SENSE1

1

2

3

4

5

6

7

8

9

31 BOOST1

30 TG1

4

SENSE1

–

SENSE1

SS/TRACK1

COMP1

FB1

5

SENSE1

SW1

BG1

29

28

6

SW1

SS/TRACK1

COMP1

FB1

7

BG1

27 EXTV

CC

8

EXTV

CC

SGND

PGND

26

9

PGND

SGND

39

INTV

CC

25 DRV

CC

10

11

12

13

14

15

16

17

18

DRV

CC

INTV

CC

FB2

24

V

IN

V

FB2

COMP2

IN

COMP2

23 BG2

BG2

SS/TRACK2 10

22 SW2

21 TG2

SW2

SS/TRACK2

–

SENSE2 11

–

TG2

+

SENSE2

20

SENSE2 12

BOOST2

+

BOOST2

CLKOUT

RNG2

RNG1

SENSE2

13 14 15 16 17 18 19

DIFF/OUT

–

DIFF/IN

+

DIFF/IN

UHF PACKAGE

38-LEAD (5mm × 7mm) PLASTIC QFN

G PACKAGE

36-LEAD PLASTIC SSOP WIDE

= 125°C, θ = 100°C/W

T

JMAX

= 125°C, θ = 34°C/W

JA

T

JMAX

JA

EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEꢀD FREE FINISH

LTC3811EUHF#PBF

LTC3811EG#PBF

TꢀPE ꢀND REEL

PꢀRT MꢀRKING

3811

PꢀCKꢀGE DESCRIPTION

TEMPERꢀTURE RꢀNGE

–40°C to 85°C

LTC3811EUHF#TRPBF

LTC3811EG#TRPBF

38-Lead (5mm × 7mm) Plastic QFN

36-Lead Plastic SSOP Wide

LTC3811EG

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

3811f

2

LTC3811

ELECTRICAL CHARACTERISTICS ^The● denotes the speciﬁcations which apply oꢁer the full operating

junction temperature range, otherwise speciﬁcations are at T_J= 2.°C0 V_IN= 12V, MODE/SYNC = ±V, unless otherwise speciﬁed0

SYMBOL

PꢀRꢀMETER

CONDITIONS

MIN

TYP

MꢀX

UNITS

Input Supply

V

IN

Operating Input Voltage Range

4.5

30

V

I

Q

Total Quiescent Supply Current

Continuous Mode (Note 4)

Shutdown Mode

●

V

= 0.7V

RUN1,2

10.5

20

40

mA

μA

FB1,2

= 0V

RUN Pin ON/OFF Control

I

RUN Pin Input Leakage

V

= 3.3V

–1

1

μA

V

RUN

RUN1,2

V

Low Level RUN Input Threshold

High Level RUN Input Threshold

0.3

IL(RUN)

1.8

V

IH(RUN)

Error ꢀmpliﬁer Characteristics (Both Channels)

V

, V

Feedback Voltage Accuracy

(Note 5)

= 1.25V (Note 5)

598

597

600

602

603

mV

FB1 FB2

●

I

, I

Feedback Pin Input Current

Line Regulation

V

COMP

–100

100

nA

%/V

%

FB1 FB2

●

ΔV /ΔV

4.5V ≤ V ≤ 30V (Note 5)

0.002

–0.01

8

0.02

FB

IN

ΔV /ΔV

Load Regulation

ΔV

= 1.25V to 1.5V (Note 5)

COMP

–0.1

FB

COMP

f

Error Ampliﬁer Unity Gain Crossover

Frequency

(Note 6)

MHz

0dB(EA)

V

Error Ampliﬁer Maximum Output

Voltage (Internally Clamped)

V

= 0.54V, No Load

2.6

V

OH(EA)

FB

V

Error Ampliﬁer Minimum Output Voltage

V

= 0.66V, No Load

10

mV

V

OL(EA)

FB

FB Voltage Threshold to Disable Error

Ampliﬁer Output

– V

0.3

FB(OFF)

INTVCC

FB

Soft-Start/Tracking

, I

I

SS/TRACK1, SS/TRACK2 Charging

Currents

V

= V

= 0.3V

–2.5

1

μA

SS1 SS2

SS/TRACK1

SS/TRACK2

R , R

SS1 SS2

SS/TRACK1, SS/TRACK2 Pull-Down

Resistance in Shutdown

= V

= 0V

kΩ

RUN1

RUN2

Differential ꢀmpliﬁer

A

Differential Mode Gain,

DIFF/OUT

ΔV

= 1V to 3.5V, I

= –100μA

0.995

–6

1.000

1.005

6

V/V

mV

V

DIFF/IN

DIFF/OUT

ΔV

/ΔV

DIFF/IN

V

Output Offset Voltage,

– V

V

+ = 1.25V, V

– = 0V,

DIFF/IN

OS(DIFF)

DIFF/IN

V

+

I

= –100μA

DIFF/OUT

DIFF/IN

DIFF/OUT

R

Input Resistance

Measured at V

+

160

100

kΩ

dB

V

IN

DIFF/IN

PSRR

Power Supply Rejection Ratio

7V ≤ V ≤ 30V

IN

DIFF

V

Maximum Differential Mode Input

Voltage

V

+ – V

DIFF/OUT DIFF/OUT

–, Measured at

= –100μA

5.5

–2

DM(DIFF)

DIFF/IN

, I

I

f

+

–

Maximum Sink Current

Maximum Source Current

Unity Gain Bandwidth

2

mA

MAX

(Note 6)

8

MHz

0dB(DIFF)

Current Comparators

V

Maximum Current Sense Threshold

V

= 0.575V, V = 1.25V

SENSE(MAX)

FB CM

(V

+ – V

–)

V

= 0V

14

32.5

60

24

50

85

34

67.5

110

mV

SENSE

RNG

= INTV

= 2V

CC

V

Minimum Current Sense Threshold

(V + – V –)

V

= 0.625V, V = 1.25V

SENSE(MIN)

FB CM

V

= 0V

–21

–41

–67

mV

SENSE

RNG

= INTV

= 2V

CC

3811f

3

LTC3811

ELECTRICAL CHARACTERISTICS ^The● denotes the speciﬁcations which apply oꢁer the full operating

junction temperature range, otherwise speciﬁcations are at T_J= 2.°C0 V_IN= 12V, MODE/SYNC = ±V, unless otherwise speciﬁed0

SYMBOL

PꢀRꢀMETER

CONDITIONS

MIN

TYP

MꢀX

UNITS

I

Total Sense Pin Current

SENSE

V

= 1.25V

–1.5

μA

SENSE

CM

(V

+ + V

–)

SENSE

V

+, V – Pin Common Mode

SENSE

0

3.5

V

CM(CS)

SENSE

Input Voltage Range

Voltage Position ꢀmpliﬁer (QFN Package Only)

g

Voltage Position Transconductance,

ΔI /ΔV (Note 8)

V

+ – V

SENSE2

– = V +

SENSE2

5.0

mS

μA

m

SENSE1

– V

– = 50mV, V = 1.25V,

CM

CSOUT

SENSE

V

= 1.25V

CSOUT

I

Output Offset Current, Measured at

CSOUT

V

+ – V

SENSE2

– = V +

SENSE2

= 1.25V

CSOUT

–40

450

40

OS(VP)

SENSE1

– V

– = 1.25V, V

Multiphase Oscillator and Phase-Lock Loop (Note 9)

f

Nominal Frequency

V

Pin Floating, MODE/SYNC = DC

= 0V, MODE/SYNC = DC Voltage

500

550

kHz

NOM

PLL/LPF

Voltage

f

Lowest Frequency

Highest Frequency

V

200

650

250

750

300

850

kHz

LOW

HIGH

PLL/LPF

= INTV , MODE/SYNC = DC

PLL/LPF

Voltage

CC

f

I

Minimum Synchronizable Frequency

Maximum Synchronizable Frequency

MODE/SYNC = External Clock

125

175

kHz

SYNC(MIN)

SYNC(MAX)

PLL/LPF

900

1000

Phase Detector Output Current

Sinking

Sourcing

f

< f

> f

–4.3

5.1

μA

MODE/SYNC

OSC

θ1 – θ2

Channel 1 to Channel 2 Phase

Relationship (Note 9)

V

= 0V

180

120

deg

PHASMODE

= 50% INTV

CC

= INTV

CC

θ1 – θ

Channel 1 to CLKOUT Phase

Relationship (Note 9)

V

= 0V

90

60

240

deg

CLKOUT

PHASMODE

= 50% INTV

= INTV

CC

V

Low Level CLKOUT Output Voltage

High Level CLKOUT Output Voltage

MODE/SYNC Input Resistance

R

CLK

R

CLK

= 50k to Ground

0.2

0.3

V

OL(CLKOUT)

4.0

1.8

5.8

75

OH(CLKOUT)

R

kΩ

V

MODE/SYNC

V

Low Level MODE/SYNC Input Threshold

High Level MODE/SYNC Input Threshold

IL(MODE/SYNC)

IH(MODE/SYNC)

V

Power Good Indicators

V

PGOOD Voltage Low

I

= 2mA

= 6V

0.12

0.30

1.0

13

V

μA

%

OL(PGOOD)

PGOOD(OFF)

PGOOD

I

PGOOD Leakage Current

V

PGOOD

FB(OV)

FB(UV)

ΔV

ΔV , PGOOD Overvoltage Threshold

FB

– V

in Percent

7

10

–10

12

FB(OV)

FB(UV)

FB(NOM)

ΔV , PGOOD Undervoltage Threshold

FB

–13

–7

%

ΔV , PGOOD Comparator Hysteresis

FB

UV or OV Comparator

mV

μs

FB(HYST)

PG(FAULT)

t

Delay from UV/OV Condition to PGOOD

Falling

145

Delay from UV/OV Fault Recovery to

PGOOD Rising

38

μs

PG(OK)

Thermal Protection

T

Thermal Shutdown Junction

Temperature

(Note 6)

165

25

°C

JSD

T

Thermal Shutdown Junction

Temperature Hysteresis

JSD(HYST)

3811f

4

LTC3811

ELECTRICAL CHARACTERISTICS ^The● denotes the speciﬁcations which apply oꢁer the full operating

junction temperature range, otherwise speciﬁcations are at T_J= 2.°C0 V_IN= 12V, MODE/SYNC = ±V, unless otherwise speciﬁed0

SYMBOL

PꢀRꢀMETER

CONDITIONS

MIN

TYP

MꢀX

UNITS

DRV Linear Regulator

CC

DRVCC

●

V

LDO Regulator Output Voltage

DRV Load Regulation

V

= 0V

5.6

6.0

–0.5

0.01

3.7

6.4

V

%

EXTVCC

ΔV

I = 0mA to 50mA

LOAD

–2.0

DRVCC(LOAD)

DRVCC(LINE)

DRVCC(UVLO)

DRVCC(HYST)

EXTVCC

CC

DRV Line Regulation

ΔV = 8.5V to 30V

0.2

%/V

V

CC

IN

V

LDO Regulator Undervoltage Threshold DRV Rising

CC

LDO Regulator Undervoltage Hysteresis

0.56

4.5

V

EXTV Switchover Voltage

I

= 20mA, EXTV Rising

V

CC

DRVCC

CC

EXTV Switchover Hysteresis

= 20mA

400

100

mV

EXTVCC(HYST)

EXTVCC(DROP)

CC

EXTV Voltage Drop

= 20mA, V

= 5V

CC

EXTVCC

Gate Driꢁers

t (TG1, TG2)

Top Gate Rise Time

Top Gate Fall Time

C = 3300pF (Note 6)

20

10

20

10

0.9

ns

Ω

r

L

t (TG1, TG2)

f

C = 3300pF (Note 6)

L

t (BG1, BG2)

r

Bottom Gate Rise Time

Bottom Gate Fall Time

C = 3300pF (Note 6)

L

t (BG1, BG2)

f

C = 3300pF (Note 6)

L

R

Top Gate Pull-Down NMOS

On-Resistance

TG to SW

DS(ON)(TG)

TG1, TG2

Ω

R

Bottom Gate Pull-Down NMOS

On-Resistance

BG to PGND

0.9

DS(ON)(BG)

BG1, BG2

I

t

TG1, TG2

BG1, BG2

Top Gate (TG) Peak Source Current

1.0

30

A

PK(TG)

PK(BG)

DEAD1

Bottom Gate (BG) Peak Source Current

Bottom Gate Off to Top Gate On

Deadtime

(Note 6)

ns

t

Top Gate Off to Bottom Gate On

Deadtime

30

65

ns

DEAD2

Minimum On-Time

V

COMP

= 1.25V (Note 6, 7)

ON(MIN)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime. Unless otherwise speciﬁed, all voltages are relative

to SGND and all currents are positive into a pin.

Note 2: The LTC3811E is guaranteed to meet performance speciﬁcations

from 0°C to 85°C temperature. Speciﬁcations over the –40°C to

85°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls.

Note 6: Guaranteed by design, not subject to test.

Note 7: The minimum on-time condition corresponds to an inductor peak-

to-peak ripple current of 50% of I . See Applications Information for

MAX

more details.

Note 8: The voltage positioning ampliﬁer operates as a transconductance

+

–

ampliﬁer, where the input voltages are the SENSE to SENSE potentials

for both channels. The ampliﬁer output current ﬂows through an external

resistor in order to program the amount of voltage droop at full load.

Note 9: The PHASEMODE function is only available in the QFN package.

The 36-lead GW package has a ﬁxed channel 1-to-channel 2 phase

relationship of 180°C and a channel 1-to-CLKOUT phase relationship of

90°C. The version in the 36-lead GW package is therefore optimized for

2- and 4-phase operation.

Note 3: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formula:

D

T = T + (P • TBD°C/W)

J

A

D

Note 4: The dynamic input supply current is higher due to power

MOSFET gate charging (Q • f ). See Applications Information for more

Note 10: Rise and fall times are measured at 10% and 90% levels.

G

OSC

information.

Note 5: The error ampliﬁers are measured in a feedback loop using an

external servo operational ampliﬁer that drives the V pin and regulates

FB

V

COMP

to be equal to the external control voltage.

3811f

5

LTC3811

TYPICAL PERFORMANCE CHARACTERISTICS

Load Step (Forced Continuous

with Voltage Positioning)

Load Step (Pulse Skip Mode)

Load Step (Forced Continuous)

V

OUT

50mV/DIV

V

OUT

AC COUPLED

50mV/DIV

AC COUPLED

I

L1

L

5A/DIV

I

L2

5A/DIV

3811 G03

3811 G02

3811 G01

V

I

= 12V

50μs/DIV

V

I

= 12V

20μs/DIV

V

I

= 12V

20μs/DIV

IN

OUT

IN

OUT

IN

OUT

= 1.5V (2-PHASE)

= 1.5V

= 0A TO 15A

= 0.5A TO 8A

LOAD

Light Load Waꢁeforms

(Forced Continuous Mode)

Light Load Waꢁeforms

(Pulse Skip Mode)

Low Duty Cycle Waꢁeforms

SW

5V/DIV

SW

5V/DIV

SW

10V/DIV

V

OUT

20mV/DIV

AC COUPLED

I

L

2A/DIV

I

L

I

L

5A/DIV

3811 G06

3811 G05

3811 G04

V

I

= 12V

1μs/DIV

V

I

= 12V

1μs/DIV

V

I

= 20V

250ns/DIV

IN

OUT

IN

OUT

IN

OUT

= 1.5V

= 1.2V

= 1.5A

= 300mA

LOAD

Efﬁciency ꢁs Load Current with

R_SENSE= 10.mΩ

Efﬁciency ꢁs Load Current with

DCR Sensing

Short-Circut Waꢁeforms

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

V

= 12V

OUT

V

= 12V

OUT

IN

= 2V

I

L

5A/DIV

PGOOD

5V/DIV

V

OUT

1V/DIV

3811 G09

V

= 12V

200μs/DIV

IN

OUT

DISCONTINUOUS

FORCED CONTINUOUS

DISCONTINUOUS

FORCED CONTINUOUS

= 1.5V

1

10

100

1

10 100

LOAD CURRENT (A)

3811 G07

3811 G08

3811f

6

LTC3811

TYPICAL PERFORMANCE CHARACTERISTICS

Differential ꢀmpliﬁer Gain ꢁs

Temperature

FB Voltage ꢁs Temperature

FB Voltage Line Regulation

0.6030

0.6025

0.6020

0.6015

0.6010

0.6005

0.6000

0.5995

0.5990

0.5985

0.5980

0.5975

0.5970

600.5

600.4

600.3

600.2

600.1

600.0

599.9

599.8

599.7

599.6

599.5

1.010

1.008

1.006

1.004

1.002

1.000

0.998

0.996

0.994

0.992

0.990

–50 –30 –10 10 30 50 70 90 110 130

0

4

8

12 16 20 24 28 32 36

SUPPLY VOLTAGE (V)

–50 –30 –10 10 30 50 70 90 110 130

TEMPERATURE (°C)

3811 G10

3811 G11

3811 G12

Oscillator Frequency ꢁs

Temperature

Oscillator Frequency ꢁs

Supply Voltage

Shutdown Mode Supply Current

ꢁs Supply Voltage

40

35

30

25

20

15

10

5

800

700

600

500

400

300

200

100

0

800

700

600

500

400

300

200

100

0

85°C

25°C

V

= INTV

CC

PLL/LPF

V

= INTV

CC

PLL/LPF

V

= FLOATING

V

= FLOATING

PLL/LPF

–40°C

V

= 0V

V

= 0V

PLL/LPF

0

16 20

SUPPLY VOLTAGE (V)

0

4

8

12

24 28 32 36

20 25

10 15

SUPPLY VOLTAGE (V)

0

5

30 35 40

–50 –30 –10 10 30 50 70 90 110 130 150

TEMPERATURE (°C)

3811 G15

3811 G14

3811 G13

SS/TRꢀCK Pin Current ꢁs

Common Mode Voltage

SS/TRꢀCK Pin Current ꢁs

Temperature

Supply Current ꢁs Supply Voltage

3.0

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.0

15

3.0

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.0

14

13

12

11

10

9

–40°C

25°C

85°C

8

7

6

5

0

200 300 400 500 600 700

100

COMMON MODE VOLTAGE (mV)

0

4

8

12 16 20 24 28 32 36

SUPPLY VOLTAGE (V)

–50 –30 –10 10 30 50 70 90 110 130

TEMPERATURE (°C)

3811 G17

3811 G16

3811 G18

3811f

7

LTC3811

TYPICAL PERFORMANCE CHARACTERISTICS

DRV_CCLine Regulation

DRV_CCLoad Regulation

DRV_CCꢁs Temperature

6.010

6.008

6.006

6.004

6.002

6.000

5.998

5.996

5.994

5.992

5.990

6.5

6.4

6.3

6.2

6.1

6.0

5.9

5.8

5.7

5.6

5.5

6.1

6.0

5.9

5.8

5.7

5.6

5.5

5.4

0

4

8

12 16 20 24 28 32 36

SUPPLY VOLTAGE (V)

–50 –30 –10 10 30 50 70 90 110 130

TEMPERATURE (°C)

200

300 350

0

50

100 150

250

DRV LOAD CURRENT (mA)

CC

3811 G19

3811 G21

3811 G20

DRV_CCUnderꢁoltage Lockout

Thresholds ꢁs Temperature

EXTV_CCThresholds ꢁs

Temperature

LDO Dropout Voltage ꢁs Current

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

700

600

5.0

4.5

4.0

3.5

T

A

= 25°C

EXTV RISING

CC

DRV RISING

CC

500

400

300

200

100

DRV FALLING

CC

EXTV FALLING

CC

0

3.0

–50 –30 –10 10 30 50 70 90 110 130

TEMPERATURE (°C)

0

30

70

100

80 90

10 20

40 50 60

–50 –30 –10 10 30 50 70 90 110 130

TEMPERATURE (°C)

CURRENT (mA)

3811 G22

3811 G23

3811 G24

RUN Pin Threshold ꢁs

Supply Voltage

Current Sense ꢀmpliﬁer g_m

ꢁs Temperature

EXTV_CCSwitch IR Drop ꢁs Current

500

450

400

350

300

250

200

150

100

50

2.5

2.0

7.0

T

= 25°C

A

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

1.5

25°C

–40°C

85°C

1.0

0.5

0

10 20 30 40 50 60 70 80 90 100

0

4

8

12 16 20 24 28 32 36

SUPPLY VOLTAGE (V)

–50 –30

30 50

TEMPERATURE (°C)

–10 10

70 90

110 130

EXTV CURRENT (mA)

CC

3811 G25

3811 G26

3811 G27

3811f

8

LTC3811

TYPICAL PERFORMANCE CHARACTERISTICS

Current Sense Threshold ꢁs

COMP Pin Voltage

Maximum SENSE Pin Voltage ꢁs

Temperature

Maximum Current Sense

Threshold ꢁs V_RNGVoltage

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

100

80

RNG = 2V

60

RNG = INTV

CC

40

RNG = 0V

20

RNG = INTV

CC

0

–20

–40

–60

RNG = 0V

–80

0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9

VOLTAGE (V)

–50 –30 –10 10 30 50 70 90 110 130

TEMPERATURE (°C)

0

0.5

1

1.5

3

2

2.5

V

RNG

COMP PIN VOLTAGE (V)

3811 G30

3811 G29

3811 G28

Maximum SENSE Pin Threshold

ꢁs Duty Cycle

SENSE Pin Current ꢁs

Common Mode Voltage

Foldback Current Limit

60

55

50

45

40

35

30

25

20

15

10

5

60

50

2.5

2.0

1.5

40

30

1.0

0.5

0

20

10

0

RNG = INTV

CC

0

200 300 400 500 600 700

FB VOLTAGE (mV)

100

0

10 20 30 40 50 60 70 80 90 100

DUTY CYCLE (%)

2.0

0

0.5 1.0 1.5

2.5 3.0 3.5 4.0

COMMON MODE VOLTAGE (V)

3811 G31

3811 G32

3811 G33

Maximum SENSE Pin Threshold

ꢁs Common Mode Voltage

Frequency ꢁs PLL/LPF Pin

Voltage

SENSE Pin Current ꢁs

Temperature

55

54

53

52

51

50

49

48

47

46

45

1200

1100

1000

900

800

700

600

500

400

300

200

100

0

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

RNG = INTV

CC

30

TEMPERATURE (°C)

0

3.5

0

0.5

1

1.5

2

2.5

–50 –30 –10 10

50 70 90 110 130

2

3

0.5

1

1.5

2.5

4

COMMON MODE VOLTAGE (V)

PLL/LPF PIN VOLTAGE (V)

3811 G34

3811 G35

3811 G36

3811f

9

LTC3811

TYPICAL PERFORMANCE CHARACTERISTICS

Top Gate Turn-On Waꢁeform

Driꢁing Renesas RJK±3±.DPB

Top Gate Turn-Off Waꢁeform

Driꢁing Renesas RJK±3±.DPB

Bottom Gate Turn-On Waꢁeform

Driꢁing Renesas RJK±3±1DPB

TG – SW

2V/DIV

3811 G38

3811 G37

3811 G39

V

I

= 12V

10ns/DIV

V

I

= 12V

10ns/DIV

V

I

= 12V

IN

OUT

25ns/DIV

IN

= 1.5V

= 5A

= 1.5V

= 5A

= 1.5V

= 5A

OUT

Bottom Gate Turn-Off Waꢁeform

Driꢁing Renesas RJK±3±1DPB

Single Output, 2-Phase Current

Sharing Waꢁeforms

Start-Up Into a Pre-Biased

Output Capacitor

I

L

5A/DIV

1V/DIV

1V

PRE BIAS

2V/DIV

SW1

10V/DIV

OV

SW2

10V/DIV

3811 G40

3811 G41

3811 G42

V

= 12V

25ns/DIV

V

= 12V

1μs/DIV

V = 3.3V

OUT

500μs/DIV

IN

= 1.5V

OUT

= 5A

OUT

= 1.5V

OUT

= 16A

OUT

I

Ratiometric Tracking Start-Up

Coincident Tracking Start-Up

Sequenced Start-Up

RUN1

2V/DIV

V

OUT1

= 2V

V

OUT2

= 1.5V

RUN2

5V/DIV

500mV/DIV

V

= 2V

OUT1

V

= 1.5V

OUT2

500mV/DIV

3811 G44

3811 G43

3811 G45

V

= 12V

LOAD1

5ms/DIV

= 1.5Ω

V

= 12V

LOAD1

10ms/DIV

= 1.5Ω

5ms/DIV

IN

R

= R

R

= R

LOAD2

RUN2 CONNECTED TO PGOOD1

3811f

10

LTC3811

PIN FUNCTIONS

BG1, BG2: High Current Gate Driver Outputs for the

N-Channel Lower Power MOSFETs.

+

DIFF/IN : Remote Sense Differential Ampliﬁer Positive

Input. A low offset, high bandwidth operational ampliﬁer

is conﬁgured with four precision 80k resistors for a non-

invertinggainofone. Thispinisnormallyconnectedtothe

positive terminal of the decoupling capacitor at the load.

BOOST1, BOOST2: Bootstrapped Supply Inputs to the

TopsideFloatingDrivers.AlowESR(X5Rorbetter)ceramic

bypasscapacitorshouldbeconnectedbetweentheBOOST

pin and the SW pin as close as possible to the IC.

–

DIFF/IN : Remote Sense Differential Ampliﬁer Negative

Input. This pin is normally connected to the negative

terminal of the decoupling capacitor at the remote load.

The DIFF/IN and DIFF/IN PCB traces should be routed

as close as possible and parallel to each other from the

IC to the output capacitor.

CLKOUT:ADigitalOutputUsedforDaisy-ChainingMultiple

LTC3811 ICs in Multiphase Systems. The PHASEMODE

pin voltage controls the phase relationship between the

channel 1 TG signal and CLKOUT.

+

–

COMP1, COMP2: Error Ampliﬁer Output Voltages. The

error ampliﬁers in the LTC3811 are high bandwidth, low

offset true operational ampliﬁers that have low output

impedance. As a result, the outputs of two active error

ampliﬁers cannot be directly connected together! For

multiphase operation, connecting the FB pin of a slave

DIFF/OUT: Remote Sense Differential Ampliﬁer Output

Voltage, Conﬁgured for a Noninverting Gain of One. The

voltageattheDIFF/OUTpinisnormallyconnectedthrough

an external resistor divider to the FB pin of one channel.

The bottom of the divider should be connected to the

SGND pin of the IC.

error ampliﬁer to INTV will disable the output of that

CC

ampliﬁer. Multiphase operation can then be achieved by

connecting all of the COMP pins together and using one

channel as the master and all of the others as slaves. The

FB and COMP pins are also used for compensating the

control loop of the converter.

DRV : Output of the Internal 6V Low Dropout Regulator

CC

(LDO), Supply Pin for the Bottom Gate Drivers and Output

of the PMOS EXTV Switch. A low ESR (X5R or better)

CC

4.7ꢀF ceramic bypass capacitor should be connected

between the DRV pin and the PGND pin, as close as

CC

possible to the IC.

CSOUT (QFN Only): Output of the Voltage Positioning

g

Ampliﬁer. This pin allows the user to program the

Exposed Pad (QFN Only): The Exposed Pad of the QFN

Leadframe is PGND.

m

amount of voltage droop in the output voltage at high

load current. The output of the voltage positioning g

m

EXTV :ExternalPowerSupplyInputtoanInternalPMOS

CC

ampliﬁer is a bi-directional current proportional to the

(SENSE – SENSE ) voltages for both channels. The

g is internally ﬁxed to 5mS. Forcing the g ampliﬁer

Power Switch Connected Between EXTV (Drain) and

CC

+

–

DRV (Source). This pin allows an external supply to be

CC

m

used for the high current gate drivers, thereby reducing

output current through a low value external resistor will

program the amount of voltage droop seen at the output.

See Applications Information for more details regarding

voltage positioning.

power dissipation in the LDO and increasing efﬁciency.

When EXTV exceeds 4.5V (rising), the high current

CC

PMOS switch turns on and shorts EXTV to DRV ,

CC

bypassing the internal LDO. See Applications Information

for more details.

3811f

11

LTC3811

PIN FUNCTIONS

PGOOD1, PGOOD2: An Open-Drain NMOS Power Good

Output. This output turns on, pulling down the PGOOD

pin, when the FB voltage falls out of a 10% regulation

window. The PGOOD monitor circuit contains a 130ꢀs

nuisance ﬁlter to prevent short duration UV and OV tran-

sients from triggering the PGOOD output on, and a 30ꢀs

ﬁlter for the recovery from a fault condition.

FB1, FB2: Error Ampliﬁer Feedback Input Pins. The error

ampliﬁers in the LTC3811 are high bandwidth, low offset

true operational ampliﬁers. If differential remote sensing

is not used, the FB pin should be connected to a resistor

divider from the output of the power supply to SGND with

theresistorsplacedclosetotheIC.Innormalregulationthe

voltage at the FB pin is 0.6V. If remote sensing is used the

FB pin should be connected to a resistor divider from the

outputofthedifferentialampliﬁertoSGND.Formultiphase

operation, connecting the FB pin of a slave error ampliﬁer

PHꢀSEMODE (QFN Only): The PHASEMODE pin voltage

programsthephaserelationshipbetweenthechannel1and

channel 2 rising TG signals, as well as the phase relation-

ship between the channel 1 TG signal and CLKOUT.

to INTV will disable the output of that ampliﬁer, allowing

CC

ampliﬁer outputs to be connected in parallel.

PLL/LPF: Frequency Set and PLL Lowpass Filter Input.

When not synchronized, this pin can be used to program

the operating frequency. Connecting this pin to SGND

INTV : Supply Pin for All of the Internal Low Voltage

CC

Analog and Digital Control Circuitry, Electrically Isolated

fromtheDRV Pin.TheINTV supplyisnormallyderived

CC

forces 250kHz operation and connecting it to INTV

CC

by connecting a low value resistor (1Ω) from the output

forces 750kHz operation. Connecting the PLL/LPF pin to

a voltage between 0.4V and 2V forces 500kHz operation.

When synchronizing to an external clock, this pin serves

asthelowpassﬁlterinputforthePLL. Aseriesresistorand

capacitor connected from PLL/PLF to SGND compensate

the PLL feedback loop.

of the LDO (DRV ) to INTV and connecting a 0.1ꢀF low

CC

ESR (X5R or better) ceramic bypass capacitor connected

from INTV to SGND. This RC decoupling conﬁguration

CC

preventsgatedriverswitchingnoisefromcouplingintothe

analog control circuitry. The INTV decoupling capacitor

CC

should be connected as close as possible to the IC pins.

RNG1, RNG2: The voltage at this pin programs the sense

voltage range for peak current mode control. Connecting

this pin to SGND programs a peak sense voltage of 24mV

MODE/SYNC: Mode Control and PLL Synchronization

Input. This pin programs the operating mode and serves

as the sync input to the internal phase-lock loop (PLL).

and connecting it to INTV programs a peak sense volt-

CC

ConnectingthispintoINTV forcescontinuousoperation

CC

age of 50mV. Alternatively, the sense voltage range can be

(regardless of the load current) and connecting it to SGND

allowsdiscontinuousmodeoperationatlightload.Applying

an external clock between 175kHz and 900kHz will cause

the operating frequency to synchronize to the clock.

linearly programmed by programming the RNG pin from

0.6V to 2V with a divider from INTV to SGND.

CC

RUN1, RUN2: On/Off Input Pin for Each Controller.

+

SENSE1 , SENSE2 : Positive Inputs to the Current Com-

PGND: Power Supply Return Path for the Bottom Side

Gate Drivers, Connected to the Sources of the Lower

Power MOSFETs. PGND should also be connected to the

parators and Voltage Positioning g Ampliﬁer. The COMP

m

pin voltage programs the current comparator offset in

order to set the peak current trip threshold. The LTC3811

is capable of sensing current using a discrete resistor in

series with the inductor, or by indirectly sensing the volt-

age drop across the DCR of the inductor. See Applications

Information for more details.

negative terminal of the DRV decoupling capacitor as

CC

close as possible to the IC. PGND is electrically isolated

from the SGND pin. The Exposed Pad on the bottom of

the QFN package is PGND.

3811f

12

LTC3811

PIN FUNCTIONS

–

SENSE1 , SENSE2 : Negative Inputs to the Current

the output of the power supply. An internal 2.5ꢀA current

source will charge the capacitor and thereby control an

extra input on the reference side of the error ampliﬁer. For

tracking operation, this input allows the start-up of a sec-

ondaryoutputtotrackaprimaryoutputaccordingtoaratio

established by a resistor divider from the primary output

to the secondary error ampliﬁer track pin. For coincident

tracking of both outputs at start-up, a resistor divider with

values equal to those connected to the secondary FB pin

from the secondary output should be used to connect the

secondary track input from the primary output.

Comparators and Voltage Positioning g Ampliﬁer. The

m

common mode input voltage range for the current com-

parators is 0V to 3.5V.

SW1, SW2: Bootstrapped Supply Return Paths for the

Topside Gate Drivers, Connected to the Sources of the

Upper Power MOSFETs.

SGND: Signal Ground Pin for the IC. Common to both

controllers, this pin should be connected to the negative

terminals of the V

and INTV decoupling capacitors

OUT

CC

and should be routed separately from any high current

TG1, TG2: High Current Gate Driver Outputs for the

N-Channel Upper Power MOSFETs.

paths on the PC board.

SS/TRꢀCK1,SS/TRꢀCK2:CombinedSoft-StartandTrack-

ingInputs.Forsoft-startoperation,connectingacapacitor

from this pin to ground will control the voltage ramp at

V :MainSupplyInput.AlowESRceramicbypasscapacitor

IN

should be connected between this pin and SGND.

3811f

13

LTC3811

FUNCTIONAL DIAGRAM

3811f

14

LTC3811

OPERATION ^{(Refer to the Functional Diagram)}

Main Control Loop

In addition to differences in pinout, another difference

between the two package options is their thermal resis-

tance. The QFN package, by virtue of its exposed lead

frame, has a junction-to-ambient thermal resistance of

only 34°C/W, whereas the SSOP package has a thermal

resistance of 100°C/W. The power dissipation of the IC

is a function of the input voltage, the gate charge of the

external power MOSFETs and the operating frequency.

The gate charge losses can be partially mitigated by us-

ing the EXTV_CCinput to supply power to the IC, but users

should beware that high input voltage applications using

very high gate charge power MOSFETs, that also need to

operateathighfrequency,shouldonlybeattemptedusing

the QFN package option. More details covering thermal

management are given later in this data sheet.

The LTC3811 uses a constant frequency peak current

mode control architecture. During normal operation, the

top MOSFET is turned on each cycle when the oscillator

sets the PWM latch and turned off when the main current

comparator (ICMP) resets the latch. The peak current at

which comparator ICMP resets the latch is controlled by

the voltage on the COMP pin, which is the output of the

error ampliﬁer. The remote sense ampliﬁer (DIFFAMP)

produces a signal equal to the differential voltage sensed

across the output capacitor and re-references it to the

local IC ground reference (SGND). The FB pin receives

a portion of this voltage feedback signal and compares

it to the internal 0.6V reference. When the load current

increases it causes a slight decrease in the FB pin voltage

relative to the 0.6V reference, which in turn causes the

COMPpinvoltagetoriseuntiltheaverageinductorcurrent

is equal to the load current.

Supplying Power to the LTC3811

The LTC3811 features several power supply input pins

and multiple ways of supplying power to the gate drivers

and low voltage analog control circuitry.

The top MOSFET drivers are biased from a ﬂoating boot-

strap capacitor, C , which is normally recharged during

B

The ﬁrst method of supplying power to the IC uses the

internal low dropout linear regulator (LDO) that draws

power from V and regulates DRV to 6V, as shown in

the off-time through an external Schottky diode. When V

IN

decreases to a voltage close to V , however, the loop

OUT

may enter dropout and attempt to turn on the top MOSFET

continuously.Adropoutdetectorsensesthisconditionand

forces the top MOSFET to turn off every 10th cycle for one

third of a cycle to recharge the bootstrap capacitor.

IN

CC

Figure 1. The DRV input supplies power to the internal

CC

gate drivers, which are capable of very high peak transient

charge(1A)anddischarge(5A)currents.TheDRV supply

CC

should be decoupled to PGND with a minimum of 4.7μF

low ESR ceramic (X5R or better) capacitance. If multiple

power MOSFETs are being driven in parallel for high cur-

rent applications it is recommended that this capacitance

Differences Between the QFN and G36 Package

Options

The LTC3811 is offered in two package options, a 38-pin

QFN and a 36-pin SSOP. The full featured QFN package

option has no leads and an exposed lead frame that needs

to be soldered to the PCB, whereas the 36-pin SSOP has

leads and is therefore slightly easier to solder to a PCB

and to debug in the lab.

V

IN

V

IN

4.5V

+

–

EXTV

CC

6V

LDO

DRV

CC

The primary electrical difference between the QFN and

SSOP options is the SSOP version lacks the CSOUT

and PHASEMODE pins. With no CSOUT pin, the SSOP

version has no provision for output voltage positioning.

With no PHASEMODE input (it is internally connected

to SGND), the SSOP version is limited to 2-phase and

4-phase applications.

GATE DRIVER SUPPLY

ANALOG SUPPLY

INTV

CC

–

V

FB

BIAS

EA

SS/TRACK

0.600V

+

SGND

3811 F01

Figure 10 Supplying Power to the LTC3811 from V_IN

3811f

15

LTC3811

OPERATION ^{(Refer to the Functional Diagram)}

be increased to 10μF. Because of the high peak current

Using an External .V Supply to Measure Dynamic

Quiescent Current

capabilityofthegatedriver,itisessentialthatthiscapacitor

be placed as close as possible to DRV and PGND pins,

CC

Whenavoltageabove4.5VisappliedtotheEXTV pin,the

CC

and on the same PCB layer as the IC.

internal LDO in the LTC3811 is switched off and the power

is supplied by the external 5V power supply as shown in

Figure 2. Under these conditions, the quiescent current

The INTV pin supplies power to all of the low voltage

CC

analogcircuitryandiselectricallyisolatedfromDRV .The

CC

INTV supply is normally derived from DRV through

at the V pin of the IC is very low (less than 1mA), and

CC

IN

an RC ﬁlter, in order to prevent gate driver supply noise

from coupling into sensitive analog control circuitry. Typi-

cal values for this RC ﬁlter consist of a 1Ω resistor from

DRV to INTV and a 0.1μF low ESR ceramic capacitor

most of the current required to power the analog control

circuitry and the gate drivers ﬂows into the EXTV pin. As

CC

a result, this auxiliary supply can be used as a diagnostic

tool in order to measure the total current for thermal

calculations. In order to match the actual condition when

CC

from INTV to SGND. The INTV capacitor should be

CC

placed as close as possible to the INTV and SGND pins

the internal LDO is on, the voltage applied to EXTV when

CC

and on the same PCB layer as the IC.

the measurements are taken should be 6V (the same as

the regulated LDO output voltage).

A third power supply pin, EXTV , serves as an auxiliary

CC

input for applications where the power dissipation in the

internal LDO is excessive, or where maximum efﬁciency

is essential. This conﬁguration is shown in Figure 2. When

Once the total quiescent current for the application is

known, the power dissipation, P , on the IC will be ap-

D

proximately I

times V , since the gate drive current

EXTVCC

IN

the EXTV pin is left open or is connected to a voltage

and control circuitry quiescent current would be required

CC

less than 4.5V, the internal 6V LDO supplies DRV power

to ﬂow through the V pin. The junction temperature of

CC

IN

from V . If EXTV is tied to an external power supply

the IC can then be estimated using the following well-

IN

CC

greater than 4.5V, however, the 6V LDO is turned off and

known formula:

power is supplied to DRV through a 5Ω PMOS switch

CC

T = T + (P • R )

θJA

J

A

D

from EXTV . For 4.5V < EXTV < 7V this PMOS switch

CC

If the maximum junction temperature is close to the Abso-

lute Maximum Rating for the particular device being used,

is on and DRV is approximately equal to EXTV . Using

CC

the EXTV pin allows the gate driver and control power to

CC

the use of an auxiliary supply and the EXTV pin may be

bederivedfromahighefﬁciencyexternalsource, dramati-

CC

required.Alternatively,lowergatechargeMOSFETsshould

cally reducing power dissipation on the IC.

be used or the switching frequency should be reduced.

V

IN

Operation at Low Supply Voltage

V

IN

4.5V

+

–

EXTV

CC

The LTC3811 control circuit has a minimum input volt-

age of 4.5V, making it a good choice for applications that

experience low supply conditions. However, care should

be taken to determine the minimum gate drive supply

voltage in order to choose the optimum power MOSFETs.

Important parameters that can affect the minimum gate

6V

AUX 5V

SUPPLY

LDO

DRV

CC

GATE DRIVER SUPPLY

ANALOG SUPPLY

INTV

CC

drive voltage are the minimum input voltage (V ), the

–

EA

+

IN

V

FB

BIAS

SS/TRACK

0.600V

LDO dropout voltage, and the EXTV supply voltage, if

CC

SGND

an external gate drive supply is being used.

3811 F02

Figure 20 Supplying Power to the LTC3811 from EXTV_CC

3811f

16

LTC3811

OPERATION ^{(Refer to the Functional Diagram)}

If the internal LDO is supplying power to the gate driver

and the input voltage is low enough for the LDO to be in

dropout, then the minimum gate drive supply voltage is:

The RUN pins may be externally pulled up or driven di-

rectly by logic. Be careful not to exceed the 7V absolute

maximum rating on this pin.

V

= V

– V

DRVCC

IN(MIN) DROPOUT

Soft-Start and Tracking Using the SS/TRꢀCK Pin

The LDO dropout voltage is a function of the total gate

drive current and the quiescent current of the IC (typically

10mA).Acurveofdropoutvoltagevsoutputcurrentforthe

LDO is shown in the Typical Performance Characteristics.

The temperature coefﬁcient of the LDO dropout voltage is

approximately +4000ppm/ºC.

The start-up of each controller’s output voltage V

OUT

is normally controlled by the voltage on the SS/TRACK

pin for that channel. The SS/TRACK pin represents a

2nd noninverting input to the error ampliﬁer, as shown

in Figure 3. The error ampliﬁer is conﬁgured so that the

lower of the two noninverting inputs (the SS/TRACK pin

or the 0.6V reference) controls the feedback loop. That

is, when the voltage on the SS/TRACK pin is less than the

0.6V internal reference, the LTC3811 regulates the FB pin

voltage to be approximately equal to the SS/TRACK pin

voltage instead of the internal 0.6V reference. This allows

the user to connect a capacitor from the SS/TRACK pin to

SGNDtoprogramthesoft-startofthepowersupplyoutput.

An internal 2.5μA current source charges this capacitor,

creating a voltage ramp on the SS/TRACK pin. As the SS/

TRACK pin voltage rises from 0V to 0.6V, the output volt-

The total Q-current (I

) ﬂowing in the LDO is the sum

Q(TOT)

of the controller quiescent current (typically 10mA) and

the total gate charge drive current.

I

= I + Q

• f

Q(TOT)

Q

G(TOT)

If an external supply is being used to supply power to the

gate driver through the EXTV pin, then the minimum

CC

gate drive supply voltage is:

V

= V

– I

• R

DRVCC

EXTVCC

Q(TOT) EXTVCC

The resistance of the internal EXTV PMOS switch is

CC

age, V , rises smoothly from 0V to its ﬁnal value. Once

OUT

typically 5Ω at 25°C and has a temperature coefﬁcient of

the soft-start interval is over, the internal 2.5μA current

approximately 3400ppm/°C.

source will continue to charge the SS/TRACK capacitor

up to a maximum voltage equal to INTV .

After the calculations have been completed, it is important

to measure the gate drive waveforms (BG-to-PGND and

CC

Alternately, the SS/TRACK pin can be used to force the

TG-to-SW) and the gate driver supply voltage (DRV -to-

CC

start-up of V

to track the voltage of another supply.

OUT

PGND) over all operating conditions (low V , mid V ,

IN

Typically, this requires connecting the SS/TRACK pin to

an external divider from the other supply to ground (see

Applications Information).

and high V , as well as from light load-to-full load) to

IN

ensure adequate power MOSFET enhancement. Consult

the power MOSFET data sheet to determine the actual

R

for the measured V , and verify your thermal

GS

INTV

DS(ON)

CC

calculations by measuring the component temperatures

using an infrared camera.

Q2 Q4

V

FB

Q3

On/Off Control Using the RUN Pin

The two channels of the LTC3811 can be independently

turned on and off using the RUN1 and RUN2 pins. Pull-

ing either of these pins low shuts down the main control

loop for that channel. Pulling both pins low disables both

controllers and most of the internal circuitry, including the

INTV

CC

2.5μA

SS/TRACK

0.6V

Q1 Q5

SHDN

M1

DRV low dropout regulator (LDO). In shutdown mode

CC

3811 F03

(both RUN pins low) the LTC3811 typically draws only

20μA of current.

Figure 30 Simpliﬁed LTC3811 Error ꢀmpliﬁer Input Stage

3811f

17

LTC3811

OPERATION ^{(Refer to the Functional Diagram)}

The SS/TRACK pin has an internal open-drain NMOS pull-

downtransistorthatturnsonwhenthecorrespondingRUN

pinispulledlowtodisablethatcontroller,whenthevoltage

operating mode will always be forced continuous. Forcing

continuous mode operation results in constant frequency

operation and a more predictable noise spectrum from

the converter.

on the DRV pin is below 3.7V (the rising undervoltage

CC

lockoutthreshold),orduringanovertemperaturecondition.

During an undervoltage lockout, UVLO, or overtempera-

ture, OT, condition, both controllers are disabled and the

external MOSFETs are held off.

Table 1

MODE/SYNC

OPERꢀTING MODE DESCRIPTION

SGND

Pulse-Skip

DCM Operation at Light Load

INTV

Forced Continuous CCM from No Load to Full Load

CC

In multiphase applications, one master error ampliﬁer is

used to control all of the phase current comparators. The

FB pins for the unused error ampliﬁers are connected to

External Clock Forced Continuous Operating Frequency Synchronized

Using Internal PLL (CCM)

Frequency Selection and the Phase-Lock Loop

INTV inordertothree-statetheseampliﬁeroutputs.Asa

CC

result, the SS/TRACK pins for the unused error ampliﬁers

should be left open.

The selection of the switching frequency is a tradeoff be-

tween efﬁciency, transient response and component size.

Low frequency operation increases efﬁciency by reducing

MOSEFT switching losses, but requires a larger inductor

and output capacitor to maintain low output ripple.

Programming the Operating Mode

The MODE/SYNC pin serves to either program the oper-

ating mode or to synchronize the operating frequency to

an external clock using the internal PLL. Connecting the

MODE/SYNC pin to ground programs pulse-skip mode

The switching frequency of the LTC3811’s controllers can

beselectedusingthePLL/LPFpin.IftheMODE/SYNCpinis

notbeingdrivenbyanexternalclock,thePLL/LPFpincanbe

operation and connecting the pin to INTV programs

CC

tied to SGND, left open or tied to INTV to select 250kHz,

CC

forcedcontinuousoperation,asshowninTable1.Inpulse-

skip mode the inductor current is not allowed to reverse,

resulting in discontinuous mode, DCM, operation at light

load. Pulse-skip mode is ideal for applications where light

load efﬁciency is a higher priority than transient response.

Inforcedcontinuousmode, thesynchronousswitchturns

onaftertheprimaryswitchturnsoffandremainsonforthe

duration of the clock cycle, regardless of the load current.

Forced continuous mode is ideal for applications need-

ing optimized transient response, or for systems where

constant frequency operation is important.

500kHz or 750kHz, respectively, as shown in Table 2.

Table 2

PLL/LPF

SGND

MODE/SYNC

FREQUENCY

250kHz

0V or INTV (DC)

CC

Floating

0V or INTV (DC)

500kHz

CC

INTV

0V or INTV (DC)

750kHz

CC

RC Filter to SGND

Connected to External Phase Locked to

Clock External Clock

A phase-lock loop is available on the LTC3811 to syn-

chronize the internal oscillator to an external clock source

connected to the MODE/SYNC pin. In this case, a series

RC network connected from the PLL/LPF pin to SGND

serves as the PLL’s loop ﬁlter. The PLL/LPF pin is both the

output of the phase detector and the input to the voltage

controlled oscillator, VCO. The LTC3811 phase detector

adjusts the voltage on the PLL/LPF pin to align the ris-

ing edge of TG1 to the leading edge of the external clock

signal. The turn-on of the second channel TG2 will depend

upon the voltage on the PHASEMODE pin as shown in the

Electrical Characteristics.

Certain applications can result in the startup of the con-

verter into a non-zero load voltage, where residual charge

is stored on the output capacitor at the onset of converter

switching. In order to prevent a reversal of current in the

inductor under these conditions, pulse-skip operation

is asserted at startup until the FB pin reaches the lower

PGOODthresholdof0.54V.OncetheFBpinvoltageexceeds

0.54V, the operating mode is determined by the voltage

on the MODE/SYNC pin.

Whentheoperatingfrequencyoftheconverterissynchro-

nized to an external clock using the MODE/SYNC pin, the

3811f

18

LTC3811

OPERATION ^{(Refer to the Functional Diagram)}

The typical capture range of the LTC3811’s PLL is ap-

proximately 125kHz to 1.1MHz, with a guarantee over

all manufacturing variations to be between 175kHz and

900kHz. The amplitude of the sync pulse to the LTC3811

should be greater than 1.8V and the minimum pulse width

should be greater than 200ns.

Remote Sensing Using the Differential ꢀmpliﬁer

The LTC3811 has a differential ampliﬁer for true remote

sensing of the output voltage. The sensing connections

should be returned from the load back to the differential

ampliﬁer’s inputs through a common, tightly coupled pair

of PCB traces. The differential ampliﬁer rejects common

mode signals capacitively or inductively radiated into the

feedbackPCBtraces, aswellasgroundloopdisturbances.

The differential ampliﬁer output signal is typically divided

down and compared with the internal precision 0.6V volt-

age reference by the error ampliﬁer.

Using the CLKOUT and PHꢀSEMODE Pins in

Multiphase ꢀpplications

TheLTC3811featurestwopins(CLKOUTandPHASEMODE)

that allow multiple LTC3811 ICs to be daisy-chained to-

gether in multiphase applications. The clock output signal

on the CLKOUT pin can be used to synchronize additional

powerstagesinamultiphasepowersupplysolutionfeeding

a single high current output or even separate outputs. The

PHASEMODE pin is used to adjust the phase relationship

between channel 1 and channel 2, as well as the phase

relationship between channel 1 and CLKOUT, as summa-

rized in Table 3. The phases are calculated relative to the

zero degrees, deﬁned as the rising edge of the top gate

driver output of channel 1, TG1.

The differential ampliﬁer utilizes four precision internal

resistors to enable instrumentation-type measurement

of the output voltage. The ampliﬁer has a gain of 1.000,

containsaCMOSrail-to-railoutputstage,andisoptimized

for low input offset and high bandwidth.

The output voltage is set by an external resistive divider

according to the following formula:

R2

R1

⎡

⎤

⎥

V_OUT= 0.6 • 1+

⎢

⎣

⎦

The PHASEMODE input comparators are referenced to an

whereR2andR1aretheupperandlowerdividerresistors,

respectively. The differential ampliﬁer was optimized for

divider currents in the range of 100μA to 600μA, meaning

that R1 in the equation above should be 1k to 6k.

internaldividerfromINTV thathas33%and67%INTV

CC

thresholds. For 6-phase operation, connect PHASEMODE

to an external divider from INTV with equal value resis-

CC

tors (e.g., 100k), so that PHASEMODE is always 50% of

INTV .

CC

Using the LTC3811 Operational Error ꢀmpliﬁers in

Multiphase ꢀpplications

Table 3

# PHꢀSES

IC #

PHꢀSEMODE CLKOUT CONNECTS TO

The LTC3811 error ampliﬁers are true operational ampli-

ﬁers, meaning that they have high DC gain and low output

impedance.Inpreviousgenerationsofmultiphasecontrol-

lers, such as the LTC1628 family, the error ampliﬁers were

transconductance ampliﬁers, meaning that they could be

connected in parallel for multiphase applications.

2

3

1

0V

N/A

1

2

INTV

0V

MODE/SYNC of IC # 2

N/A

CC

4

6

1

2

0V

MODE/SYNC of IC # 2

N/A

1

2

3

50% INTV

MODE/SYNC of IC # 2

N/A

CC

Multiphase applications using the LTC3811 will use one

operational error ampliﬁer as the master and will disable

all of the slave phase error ampliﬁers. Typically, the chan-

nel 1 ampliﬁer for phase = 0º will be used as the master

and phases 2 through n (up to 12 phases) will serve as

slaves. To disable the slave error ampliﬁers but still use

their current comparators and power stages, connect the

12

1

2

3

4

5

6

50% INTV

0V

50% INTV

MODE/SYNC of IC # 2

MODE/SYNC of IC # 3

MODE/SYNC of IC # 4

MODE/SYNC of IC # 5

MODE/SYNC of IC # 6

N/A

CC

3811f

19

LTC3811

OPERATION ^{(Refer to the Functional Diagram)}

ONLY PGOOD PIN FOR

the amplitude of those for one regulator to be drawn from

the input capacitor. These large amplitude current pulses

increased the total RMS current ﬂowing from the input

capacitor, requiring the use of more expensive input ca-

pacitors and increasing both EMI and losses in the input

capacitor.

INDIVIDUAL INTV AND DRV

CC CC

MASTER CHANNEL

IS USED (FLOAT SLAVE

CHANNEL PGOOD PINS)

PINS LOCALLY DECOUPLED

(DRV NOT SHOWN)

CC

MASTER

LTC3811

INTV

FB2

DIFF/IN

PGOOD1

PGOOD2

CC

+

–

V

OUT

+

–

ON/OFF

CONTROL

OUT

DIFF/OUT

FB1

RUN1

RUN2

With multiphase operation, the two channels of the dual-

switchingregulatorareoperated180degreesoutofphase.

Thiseffectivelyinterleavesthecurrentpulsesdrawnbythe

switches,greatlyreducingtheoverlaptimewheretheyadd

together. The result is a signiﬁcant reduction in total RMS

input current, which in turn allows less expensive input

capacitors to be used, reduces shielding requirements for

EMI and improves real world operating efﬁciency.

MASTER

DIFFERENTIAL

AMPLIFIER

COMP1 SS/TRACK1

COMP2 SS/TRACK2

ALL

USED TO DRIVE

CHANNEL 1

ERROR

SS/TRACK

CLK

OUT

SGND

PINS

CONNECTED

TOGETHER

AMPLIFIER

SLAVE

CHANNEL

SYNC

LTC3811

INTV

FB2

FB1

PGOOD1

PGOOD2

RUN1

RUN2

SS/TRACK1

CC

FB PINS ALL

CONNECTED

TO LOCAL

INTV PINS

CC

COMP1

COMP2

TO DISABLE

ERROR

Figure 5 illustrates the beneﬁts of multiphase operation.

Current ripple at the input is reduced by a factor of 1.41

(square root of 2), reducing the size and cost of the input

ALL RUN

PINS

SS/TRACK2

AMPLIFIERS

CLK

OUT

SGND

CONNECTED

TOGETHER

SLAVE

capacitor. In addition, since power losses are proportional

LTC3811

SYNC

2

to I

, signiﬁcant efﬁciency improvements in the input

RMS

INTV

FB2

FB1

PGOOD1

PGOOD2

RUN1

CC

SLAVE

CHANNEL

COMP

PINS ALL

CONNECTED

TO MASTER

CHANNEL

COMP PIN

power path components (batteries, switches, protection

circuitry and PCB traces) can be achieved. Improvements

in both conducted and radiated EMI also directly accrue

as a result of the reduced RMS input current.

COMP1

RUN2

COMP2 SS/TRACK1

SS/TRACK2

SGND

3811 F04

SGND BUS ISOLATED FROM

PGND AND INDEPENDENTLY

ROUTED TO NEGATIVE

I

L

5A/DIV

TERMINAL OF OUTPUT CAPACITOR

SW1

10V/DIV

Figure 40 LTC3811 Error ꢀmpliﬁer Conﬁguration

for Multiphase Operation

SW2

10V/DIV

FB pin of a slave phase to INTV . As shown in the Func-

CC

3811 G41

V

= 12V

1μs/DIV

IN

tional Diagram, a comparator detects when the FB pin is

= 1.5V

OUT

= 16A

OUT

I

shorted to INTV and three-states this ampliﬁer’s output

CC

and input. The COMP pins for all of the phases can then

be shorted together in order to provide compensation for

the feedback loop, as shown in Figure 4.

Figure .0 2-Phase, Single Output Current Sharing Waꢁeforms

Of course, the improvement afforded by 2-phase opera-

tion is a function of the dual switching regulator’s relative

duty cycles which, in turn, are dependent upon the input

Theory and Beneﬁts of Multiphase Operation

voltage V (Duty Cycle = V /V ).

IN

OUT IN

Why the need for multiphase operation? Up until the

multiphase family, constant frequency dual switching

regulators operated both channels in phase (i.e., single-

phase operation). This means that both switches turned

on at the same time, causing current pulses of up to twice

Figure 6 shows the net ripple current seen by the output

capacitors for the different phase conﬁgurations. The

output ripple current is plotted for a ﬁxed output voltage

as the duty factor is varied between 10% and 90% on the

3811f

20

LTC3811

OPERATION ^{(Refer to the Functional Diagram)}

lockout or overtemperature condition. When the FB pin

voltage is within the 10% window, the internal PGOOD

MOSFET is turned off and the pin is normally pulled up by

an external resistor. The absolute maximum voltage rating

of the PGOOD pins is 7V.

x-axis. The output ripple current is normalized against

the inductor ripple current at zero duty factor. The graph

can be used in place of tedious calculations. As shown in

Figure 6, the zero output ripple current is obtained

when:

The PGOOD logic contains separate ﬁlters depending on

whether the controller is entering or exiting a fault condi-

tion. When the FB pin is exiting a fault condition (such as

duringnormaloutputvoltagestart-up,priortoregulation),

thePGOODpinwillremainlowforanadditional30μs. This

allows the output voltage to reach steady-state regulation

andpreventstheenablingofaheavyloadfromre-triggering

a UVLO condition. When the FB pin is entering either an

undervoltage, UV, or overvoltage, OV, fault condition, the

PGOOD pin will remain high 130μs after the onset of the

fault. This non-integrating ﬁlter prevents noise or short

duration overload conditions from triggering the PGOOD

outputsandcausingafalsesystemreset.Figure7illustrates

the timing diagram for a hypothetical undervoltage event

on the FB pin, and the resulting PGOOD waveform.

V_OUT

k

N

=

where k = 1, 2, ..., N – 1

V

IN

Sothenumberofphasesusedcanbeselectedtominimize

the output ripple current and therefore the output ripple

voltage at the given input and output voltages. In appli-

cations having a highly varying input voltage, additional

phases will produce the best results.

Accepting larger values of ΔI allows the use of low in-

L

ductances, but can result in higher output voltage ripple.

A reasonable starting point for setting ripple current is

ΔI = 0.4(I )/N, where N is the number of channels and

L

OUT

I

is the total load current. Remember, the maximum

OUT

ΔI occurs at the maximum input voltage. The individual

L

inductor ripple currents are constant determined by the

inductor, input and output voltages.

In multiphase applications, one error ampliﬁer is used to

control all of the phase current comparators. In addition,

since the FB pins for the unused error ampliﬁers are con-

1.0

1-PHASE

2-PHASE

3-PHASE

4-PHASE

6-PHASE

0.9

nectedtoINTV (inordertothree-statetheseampliﬁers),

CC

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

the PGOOD outputs for these ampliﬁers will be asserted.

In order to prevent falsely reporting a fault condition, the

0.66V = OV

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

THRESHOLD

0.54V = UV

THRESHOLD

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

3811 F06

Figure 60 Normalized Peak Output Current ꢁs

Duty factor [I_RMS≈ ±03(ΔI_O(P-P))]

Power Good Pins (PGOOD1, PGOOD2)

TIME

30μs

5

Each PGOOD pin is connected to the open drain of an

internal N-channel pull-down MOSFET. The MOSEFT turns

on and pulls the PGOOD pin low when the corresponding

FB pin is outside a 10% window around the 0.6V refer-

ence voltage. The PGOOD pin is also pulled low when the

corresponding RUN pin is low, or during an undervoltage

t < 30μs

130μs

0

TIME ^{3811 F07}

Figure 70 PGOOD Filter Timing Diagram

3811f

21

LTC3811

OPERATION ^{(Refer to the Functional Diagram)}

PGOOD outputs for the unused error ampliﬁers should be

left open. Only the PGOOD output for the master control

error ampliﬁer should be connected to the fault monitor.

Under short-circuit conditions with very low duty cycles,

the LTC3811 may begin to skip pulses in order to limit the

maximum current. In this situation the bottom MOSFET

will be dissipating most of the power; however this will

be less than in normal operation at maximum load. In this

case the short circuit ripple current is determined by the

Fault Conditions: Current Limit and Foldback

One of the main advantages of the LTC3811 is the fact that

the maximum inductor current is inherently limited due

to the use of peak current mode control. The maximum

sense voltage is controlled by the voltage on the RNG pins

and the maximum DC output current is:

minimum on-time, t

, of the LTC3811 (about 65ns),

ON(MIN)

the input voltage, and the inductor value, according to the

following equation:

V

L

IN

ΔI_L(SC)= t_ON(MIN)

•

V_SENSE(MAX)

1

– • ΔI_L

I_LIMIT

=

R_SENSE

2

The resulting short-circuit current is

0.3 • V_SENSE(MAX)

1

2

The current limit value should be checked to ensure that

LIMIT(MIN) OUT(MAX)

I_SC

=

– • ΔI_L(SC)

R_SENSE

I

> I

. The minimum value of the current

limit generally occurs with the largest V at the highest

IN

Depending upon the ratio of the DC value of the current

limit to the maximum load current and the percentage

ripple current in the inductor, it is possible that the con-

ambient temperature, conditions that cause the largest

power losses in the converter.

Tofurtherlimitcurrentintheeventofanoutputshort-circuit

toground,theLTC3811includesfoldbackcurrentlimiting.

When the FB pin falls below 0.3V (50% of its nominally

regulatedvalue), thefoldbackcircuitisactivated, progres-

sively lowering the peak current limit in proportion to the

severity of the overcurrent or short circuit condition. If the

FB pin reaches 0V, the peak current sense threshold will

be reduced to 30% of its maximum value. The foldback

current limit transfer function is shown in Figure 8.

verter will operate in discontinuous mode when V = 0V

FB

(a so-called “dead short”). In this case, the short-circuit

current of the converter will be:

ΔI_L(SC)

V

2 •L

IN

I_SC

=

= t_ON(MIN)•

2

In order for the converter to start up properly with a non-

linear load, the foldback current limiting circuit in the

LTC3811 is disabled during the initial soft-start interval.

When the FB pin voltage reaches 0.54V, the soft-start in-

terval is terminated and the foldback circuit is enabled.

60

55

50

45

40

35

30

25

20

15

In the event the converter is turned on into a shorted load,

the foldback circuit will be disabled until the SS/TRACK

pin reaches 0.54V. This ensures that the converter will still

limit the maximum current to a safe level and reduce the

peak power dissipated with a shorted load.

RNG = INTV

10

5

CC

0

200 300 400 500 600 700

FB VOLTAGE (mV)

100

3811 G31

Figure 80 Current Foldback Charactistic

3811f

22

LTC3811

APPLICATIONS INFORMATION

Duty Cycle Considerations

COMP

The duty cycle for a buck converter is well known:

LTC3811

V_OUT

V

OUT

D =

= t_ON• f

FB

V

IN

R2

R1

C

OUT

Rearranging, theminimumon-timeforagivenapplication

can be calculated:

SGND

3811 F09

DIVIDER AND COMPENSATION

COMPONENTS PLACED NEAR

FB, SGND AND COMP PINS

V_OUT

_IN(MAX)• f

t_ON(MIN)

=

V

Figure 90 Output Diꢁider and Compensation

Component Placement

Foragiveninputandoutputvoltage,itisimportanttoknow

how close the minimum on-time of the application comes

to the minimum on-time of the control IC. The LTC3811

hasatypicalminimumon-timeof65ns,allowingbothhigh

input to output ratios and high frequency operation.

Sensing the Output Voltage with a Differential

ꢀmpliﬁer

The LTC3811 includes a low offset, unity gain, high band-

widthdifferentialampliﬁerforapplicationsthatrequiretrue

remotesensing.SensingbothSENSE andSENSE greatly

beneﬁtsregulationinhighcurrent,lowvoltageapplications,

where board interconnection losses can be a signiﬁcant

portion of the total error budget.

In an application circuit, if the IC’s minimum on-time

exceeds the value required in the duty cycle equations,

the converter will begin to skip pulses and operate at a

fractionoftheintendedfrequency. Thisfrequencydivision

will result in higher current and voltage ripple and is of

particular concern in forced continuous applications with

low ripple currents at light loads.

+

–

TheLTC3811differentialampliﬁerhasatypicaloutputslew

rate of 8V/μs and has rail-to-rail output drive capability.

The ampliﬁer is conﬁgured for unit gain, meaning that the

difference between SENSE and SENSE is translated to

DIFFOUT, relative to SGND.

Setting the Output Voltage

+

–

The LTC3811 output voltages are each set by external

feedback resistor dividers, according to the following

equation:

+

–

CareshouldbetakentoroutetheSENSE andSENSE PCB

traces parallel to each other all the way to the terminals

of the output capacitor or remote sensing points on the

board.Inaddition,avoidroutingthesesensitivetracesnear

any high speed switching nodes in the circuit. Ideally, the

SENSE and SENSE traces should be shielded by a low

impedance ground plane to maintain signal integrity.

R2

R1

⎡

⎤

⎥

V_OUT= 0.6V • 1+

⎢

⎣

⎦

+

–

Care should be taken to place the output divider resistors

and the compensation components as close as possible

to the IC FB and SGND pins, in order to prevent switching

noisefromcouplingintothesignalpath.Thisconﬁguration

is shown in Figure 9. The top of R2 is normally routed to

the top of the output capacitor, or to the output of the dif-

ferential ampliﬁer, if remote sensing is being employed.

Choosing the Inductor Value and Saturation Current

Rating

Theoperatingfrequencyandinductorvalueareinterrelated

inthathigheroperatingfrequenciesallowtheuseofsmaller

inductorsandcapacitors.Higherfrequencyoperationalso

resultsinhigherswitchingandgatedrivelosses,soabasic

tradeoff exists between size and efﬁciency.

Becausethecommonmoderangeofthecurrentcompara-

tor input stages is 0V to 3.5V, the output voltage range is

limited from 0.6V to 3.3V.

3811f

23

LTC3811

APPLICATIONS INFORMATION

ForCCMoperation,theinductorvaluecanbechosenusing

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core materials exhibit “hard” saturation, meaning that

the inductance collapses abruptly when the peak current

capability is exceeded. This results in an abrupt increase

in inductor ripple current and output voltage ripple. Do

not allow the core to saturate!

the following equation:

⎡

⎤

⎥

⎦

V_OUT

L =

1–

⎢

f • ΔI_{L ⎢}

V

IN(MAX) ⎥

⎣

Choosing a larger value of ΔI allows the use of a lower

L

value inductor, but results in higher output voltage ripple

and greater core losses. A reasonable starting point for

setting the ripple current is 40% to 50% of the maximum

output current, or:

Programming the Maximum Sense Voltage Using the

RNG Pin

ΔI = 0.4 • I

L

OUT(MAX)

The RNG pin can be used in two different ways in order to

program the maximum peak current sense voltage. The

easiest way to program the peak sense voltage is to tie

The inductor saturation current rating needs to be higher

than the peak inductor current during an overload condi-

the RNG pin to either ground or INTV . Connecting the

CC

tion. If I

is the maximum rated load current, then

OUT(MAX)

RNG pin to ground results in a 24mV peak sense voltage

the maximum overload current, I

, would normally

MAX

and connecting it to INTV programs in a 50mV peak

CC

be chosen to be some factor (e.g., 30%) greater than

sense voltage. Alternately, an external resistor divider

I

:

OUT(MAX)

from INTV to ground can be used to set the RNG pin

CC

I_MAX= 1.3 •I_OUT(MAX)

between 0.6V and 2V, resulting in a nominal peak sense

voltage range of 24mV to 85mV. Figure 10 illustrates the

transfer function from the RNG pin to the peak sense

voltage, which closely follows the following equation for

1

2

I_L(PK)= I_MAX+ • ΔI_L

0.6V < V

< 2V:

RNG

For a 40% ripple application, the minimum saturation

current rating of the inductor would therefore be:

V

= 0.0436 • V

– 0.0022

SENSE(MAX)

RNG

I

= 1.5 • I

O(MAX)

In general, the accuracy of the SENSE pin threshold will

scale with the peak sense voltage deﬁned by the RNG

L(PK)

Inotherwords, foranapplicationwith40%inductorripple

current and a maximum output current 30% greater than

the full load current, the inductor’s saturation current rat-

ing needs to be at least 1.5 times the maximum output

current.

90

80

70

60

50

40

30

20

10

Inductor Core Selection

Once the value of L is known, the type of inductor must be

selected.Highefﬁciencyconvertersgenerallycannotafford

the core losses found in low cost powdered iron cores,

forcingtheuseofmoreexpensiveferriteormolypermalloy

cores.Actualcorelossisindependentofcoresizeforaﬁxed

inductor value, but is very dependent on the inductance

selected. As inductance increases, core losses go down.

Unfortunately, increased inductance requires more turns

of wire and therefore copper losses will increase.

0

0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9

V

RNG

VOLTAGE (V)

3811 G30

Figure 1±0 Maximum Current Sense Threshold

ꢁs RNG Pin Voltage

3811f

24

LTC3811

APPLICATIONS INFORMATION

with operation up to 1MHz are becoming more common.

Under these conditions the voltage drop across the sense

resistor’s parasitic inductance is no longer negligible.

pin. For applications requiring maximum current limit ac-

curacy, a higher peak sense voltage (e.g., 85mV) should

be chosen. An additional beneﬁt of a higher peak SENSE

pin threshold is a slight reduction in the minimum on-

time of the controller. That is, for a given ripple current

in the inductor, a higher peak sense voltage results in

higher SENSE pin dV/dt, speeding up the input stage of

the current comparator slightly. For applications where

high efﬁciency and tight current limit accuracy are both

important, the peak current sense voltage can be reduced

to as low as 24mV.

A typical sensing circuit using a discrete resistor is shown

inFigure12.Inpreviousgenerationsofcontrollers,asmall

RC ﬁlter placed near the IC was commonly used to reduce

the effects of capacitive and inductive noise coupled in

the sense traces on the PCB. A typical ﬁlter consists of

two series 10Ω resistors connected to a parallel 1000pF

capacitor, resulting in a time constant of 20ns.

2.5

Inmultiphaseapplications,onlyoneerrorampliﬁerisused

tocontrolallofthephasecurrentcomparators.Asaresult,

inmultiphaseapplicationsalloftheRNGpinsshouldallbe

tied to the same potential, in order to program the same

2.0

1.5

power stage g for each phase.

m

1.0

0.5

0

+

–

SENSE and SENSE Pins

The common mode input voltage range of the current

comparators is 0V to 3.5V. Continuous linear operation is

provided throughout this range, allowing output voltages

between 0.6V (the reference input to the error ampliﬁers)

and3.3V. TheSENSE andSENSE pinsarealsotheinputs

to the voltage positioning current sense g ampliﬁer.

Under normal operation, a small current of about 1.5μA

ﬂows out of the SENSE inputs and represents the total

base current of the two vertical PNP input stages (one in

the current comparator and one in the voltage positioning

currentsenseampliﬁer).Whenthecommonmodevoltage

is lower than about 0.4V, the current ﬂowing out of the

SENSE pins increases, up to about 2.2μA at V

Figure 11 illustrates the change in the SENSE pin current

as a function of common mode voltage.

2.0

COMMON MODE VOLTAGE (V)

0

0.5 1.0 1.5

2.5 3.0 3.5 4.0

+

–

3811 G33

m

Figure 110 SENSE Pin Input Bias Current ꢁs

Common Mode (Output) Voltage

V

IN

V

IN

DRV

CC

LTC3811

BOOST

SENSE RESISTOR

PLUS PARASITIC

INDUCTANCE

= 0V.

SENSE

TG

R

ESL

S

SW

V

OUT

BG

C

F

• 2R = ESL/R

F

S

PGND

POLE-ZERO

CANCELLATION

Sensing Techniques Using Low Value Resistors

R

F

+

SENSE

For previous generation current mode controllers, the

maximum sense voltage was high enough (e.g., 75mV

for the LTC1628 family) that the voltage drop across the

parasitic inductance of the sense resistor represented a

relatively small error. For today’s highest current density

solutions, however, the value of the sense resistor can be

lessthan1mΩandthepeaksensevoltagecanbeaslowas

24mV.Inaddition,inductorripplecurrentsgreaterthan50%

C

F

–

SENSE

F

SGND

3811 F12

FILTER COMPONENTS

PLACED NEAR SENSE PINS

Figure 120 Using a Resistor to Sense Current with the LTC3811

3811f

25

LTC3811

APPLICATIONS INFORMATION

This same RC ﬁlter, with minor modiﬁcations, can be used

to extract the resistive component of the current sense

signalinthepresenceofparasiticinductance.Forexample,

Figure13illustratesthevoltagewaveformacrossa1.5mΩ

Panasonic metal strip resistor (ERJ-M1WTJ1M5U). The

waveformisthesuperpositionofapurelyresistivecompo-

nentandapurelyinductivecomponentandwasmeasured

with a single low impedance scope probe through a BNC

connected directly across the sense resistor terminals.

Based on additional measurements of the inductor ripple

current and the on- and off-times of the primary switch,

the value of the parasitic inductance was determined to

be 0.5nH using the equation:

sense voltages, check the sense resistor manufacturer’s

data sheet for information about parasitic inductance. In

the absence of data, measure the voltage drop directly

across the sense resistor using a low impedance con-

nection to extract the magnitude of the ESL step and

use the equation above to determine the proper ﬁlter

time constant, keeping the two ﬁlter resistor values equal

and less than about 200Ω each. Finally, place these ﬁlter

components close to the IC and run the positive and

negative sense traces parallel to each other all the way

to the sense resistor.

Inductor DCR Sensing

For applications requiring the highest possible efﬁciency,

the LTC3811 is capable of sensing the voltage drop across

the inductor DCR, as shown in Figure 15. The DCR of

the inductor represents the small amount of DC winding

resistance of the copper, which can be less than 1mΩ for

today’s low value, high current inductors. If the external

RC time constant is chosen to be exactly equal to the

L/DCR time constant, the voltage drop across the external

capacitor is equal to the voltage drop across the inductor

DCR.Checkthemanufacturer’sdatasheetforspeciﬁcations

regardingtheinductorDCRinordertoproperlydimension

the external ﬁlter components. The DCR of the inductor

can also be measured using a good RLC meter.

⎡

⎢

⎣

⎤

⎥

⎦

ΔI_LΔI_L

+

V_ESL(STEP)= ESL •

t_ONt_OFF

If the R∙C time constant is chosen to be exactly the same

as the parasitic inductance divided by the sense resistor

(L/R), the resulting waveform looks resistive again, as

shown in Figure 14. For applications using low maximum

10mV/DIV

V

IN

3811 F13

250ns/DIV

V

IN

DRV

CC

LTC3811

BOOST

Figure 130 Current Sense Waꢁeform for the Circuit in Figure 33

INDUCTOR

L

TG

V

OUT

DCR

SW

BG

R1

PGND

R1 = R2

R2

+

SENSE

10mV/DIV

C1

R1 • C1 = L/DCR

–

SENSE

SGND

3811 F15

PLACE R1 NEAR

INDUCTOR TO

MINIMIZE SW NODE

NOISE COUPLING

3811 F14

FILTER COMPONENTS

250ns/DIV

SHOULD BE PLACED NEAR

+

–

SENSE , SENSE PINS

Figure 140 Waꢁeform at the SENSE⁺and SENSE^–Pins

Using RC – L/R Time Constant Cancellation

Figure1.: Current Mode Control Using the Inductor DCR

3811f

26

LTC3811

APPLICATIONS INFORMATION

The value of the resistors in the RC ﬁlter is a tradeoff

between power dissipation and DC accuracy. The power

loss on R1 is:

In general, there are three potential sources of power

dissipation in the LTC3811:

1. The quiescent current consumed by all of the analog

control circuitry connected to INTV

V – V • V

CC

(

)

IN

O

P_R1=

2. Gate drive losses

R1

for a buck converter.

3. Losses in the LDO when power is being supplied from

V

IN

If the value of the ﬁlter resistor is too low, its power dis-

sipation will rise, resulting in a larger package size and

decreased efﬁciency at light load. If the value of the ﬁlter

resistor is too high, the input bias current ﬂowing out of

The steady-state quiescent current of the IC is typically

10mA and ﬂows into the INTV pin, either through the

CC

LDO from V or through an auxiliary power supply con-

IN

+

the SENSE pin (approximately 1.5μA) could cause the

nected to the EXTV pin.

CC

voltage drop across the resistor to be the same order

of magnitude of the peak sense voltage, which is also

undesirable. A good balance is to use a resistor value of

The second source of power dissipation is the gate drivers

connected to DRV . The lower MOSFET gate drivers are

CC

directly connected to DRV and the upper ones are con-

–

+

CC

about1k.Anadditional1kresistor(R2)intheSENSE path

is used to compensate for the drop in the SENSE path,

and ideally these two resistors (R1 and R2) should match

one another.

nected to DRV through the bootstrap diode and ﬂoating

CC

supplycapacitorC (refertoFunctionalDiagram).Thegate

B

driver current requirement depends upon the number of

MOSFETs being driven, their total gate charge, Q

,

G(TOT)

Ingeneral,thelargerthesensevoltagerangeis,thesmaller

the percentage error due to a mismatch in the ﬁlter resis-

tor IR drops. The current comparators were designed for

low offset and high speed, speciﬁcally for applications

requiring a small peak sense voltage.

and the operating frequency, f, of the converter. The total

current required by the low voltage circuitry is the sum of

the DC quiescent current and the gate drive current.

I

= 10mA + Q

• f

G(TOT)

VCC

If the internal LDO in the LTC3811 is used to supply power

to DRV and INTV , care should be taken to ensure that

Gate Driꢁe Power Supply Considerations

CC

the total low voltage current doesn’t exceed the 100mA

limit for the LDO.

The LTC3811 user has a choice of how to supply power to

the gate drivers and low voltage analog control circuitry.

The ﬁrst of these is to use the internal low dropout linear

Assuming that DRV = EXTV = INTV = 6V, power

CC

regulator,LDO,todrawpowerfromV andregulateDRV

IN

CC

dissipation due to the quiescent current and gate drive

to 6V. The second way of supplying power to the gate

losses is:

drivers and analog control circuitry is through the EXTV

CC

PV = 6V • (10mA + Q

• f)

CC

G(TOT)

pin. The choice of which supply path to use depends upon

system ﬂexibility, power dissipation and the maximum

junction temperature in the application.

The third source of power dissipation occurs in the LDO,

which supplies power to the DRV pin when EXTV is

CC

less than 4.7V. When power is being drawn from V the

IN

The internal DRV LDO is capable of sourcing up to

CC

power dissipated in the LDO is:

100mA, allowing the user to connect multiple power

MOSFETs in parallel on both channels for the high power

density applications. High input voltage applications in

which multiple large MOSFETs are being driven at high

frequencies, however, may cause the maximum junction

temperature rating for the LTC3811 to be exceeded.

P

= (V – V

) • (10mA + Q

• f)

LDO

IN

DRVCC

G(TOT)

3811f

27

LTC3811

APPLICATIONS INFORMATION

The total power dissipation is the sum of these two and

the junction temperature can then be estimated using the

following equation:

connecting the EXTV pin to the DRV pin and thereby

CC CC

supplying the internal analog and digital circuitry and

MOSFET gate drive power. Do not apply greater than 7V

to the EXTV pin (its absolute maximum rating) and en-

CC

T = T + (P

+ P ) • R

LDO θJA

J

A

VCC

sure that EXTV < V + 0.3V when using the application

CC

IN

As an example, consider a 2-phase, single-output applica-

tion with a 12V input voltage and a 1.2V output at up to

30A (15A/phase), using the QFN version of the LTC3811.

The upper power MOSFETs are the Renesas RJK0305DPB

(one per phase) and the lower power MOSFETs are the

RJK0301DPB (one per phase). The upper MOSFETs have

circuits shown. If an external voltage source is applied to

the EXTV pin when the V supply is not present, a diode

CC

IN

can be placed in series with the LTC3811’s V pin and a

IN

Schottky diode between the EXTV pin and the V pin,

CC

IN

to prevent current from backfeeding into V through the

IN

PMOS body diodes.

a typical R

= 10mΩ at V = 4.5V and a typical Q =

DS(ON)

GS

G

Signiﬁcant energy gains can be realized by power-

8nC. The lower MOSFETs have a typical R

= 3mΩ at

DS(ON)

ing DRV and INTV from an auxiliary supply, since

CC

V

GS

= 4.5V and a typical Q = 32nC. The total gate charge

G

the V current resulting from the driver and analog

IN

is therefore 80nC and the operating frequency is 500kHz.

With a maximum ambient temperature of 70°C and a

thermal resistance of 34°C/W for the QFN package,

control circuitry currents will be scaled by the ratio:

Duty Cycle/Efﬁciency

The following list summarizes the three possible connec-

I

= 10mA + 500kHz • 80nC = 50mA

DRVCC

tions for EXTV :

CC

P

= 6V • (10mA + 500kHz • 80nC) = 300mW

DRVCC

1. EXTV left open (or grounded). This will cause DRV

CC

= (12V – 6V) • (10mA + 500kHz • 80nC)

= 300mW

and INTV to be powered from the internal 6V LDO,

LDO

CC

resulting in a signiﬁcant efﬁciency penalty and excess

power dissipation at high input voltages.

T = 70°C + (0.3 + 0.3) • 34°C/W = 90°C

J

2. EXTV connected to an external supply. If an external

CC

A20°CriseinthejunctiontemperatureandamaximumLDO

current of 50mA are acceptable numbers but could be im-

supply is available in the 5V to 7V range it may be used

to power EXTV , provided it is capable of satisfying

CC

proveduponbyusingtheEXTV pintosupplypowertothe

CC

the gate drive and control IC current requirements. V

IN

gatedrivers.Theuseofanauxiliarysupplyconnectedtothe

must be greater than or equal to the voltage applied to

the EXTV pin.

EXTV pin would reduce the junction temperature rise by

CC

a factor of 2, resulting in a max junction temperature of:

3. EXTV connectedtoanoutput-derivedboostnetwork.

CC

T = 70°C + 0.3 • 34°C/W = 80°C

J

For 3.3V and other low voltage regulators, efﬁciency

For applications where the internal LDO is being used to

supply power to the IC, to prevent the maximum junction

temperature from being exceeded the input supply cur-

gains can still be realized by connecting EXTV to

CC

an output-derived voltage which has been boosted to

greater than 4.5V but less than 7V. This can be done

with a capacitive charge pump shown in Figure 16.

rent should be monitored at maximum V in continuous

IN

conduction mode (i.e., with MODE/SYNC connected to

INTV ).

Power MOSFET and Schottky Diode (Optional)

Selection

CC

Using the EXTV Pin to Supply Power to the LTC3811

CC

Two external power MOSFETs must be selected for each

controller in the LTC3811: one N-channel MOSFET for the

top (main) switch, and one N-channel MOSFET for the

bottom (synchronous) switch.

The LTC3811 contains an internal P-channel MOSFET

switch connected between the EXTV and DRV pins.

CC

When the voltage applied to EXTV exceeds 4.5V, the

CC

internal LDO is turned off and the PMOS switch turns on,

3811f

28

LTC3811

APPLICATIONS INFORMATION

+

V_OUT

V

+

IN

P_MAIN

=

(

I

²R_DS(ON)1+ δ +

C

(

)

(

)

IN

MAX

V

IN

V

IN

0.22μF

BAT85

I

⎡

⎤

2

TG1

MAX

V

R C

_DR)(

•

)

(

)

IN

MILLER

⎢

⎥

LTC3811

2

⎣

⎦

VN2222LL

EXTV

CC

R

SENSE

⎡

⎤

⎥

⎦

V

1

SW1

BG1

OUT

L1

D1

+

f

( )

⎢

+

V

– V_THMINV_THMIN

INTVCC

⎣

C

OUT

3811 F16

V – V_OUT

2

IN

PGND

P_SYNC

=

I

(

1+ δ R

DS(ON)

(

)

MAX

V

IN

where δ is the temperature dependency of R_DS(ON)and

R_DR(approximately 2Ω) is the effective top gate driver

resistanceattheMOSFET’sMillerthresholdvoltage.V_THMIN

is the typical MOSFET minimum threshold voltage.

Figure 160 Capacitiꢁe Charge Pump for EXTV_CC

The peak-to-peak drive levels are set by the INTV_CC

voltage. This voltage is typically 6V during start-up

(see EXTV_CCPin Connection). Consequently, logic-level

threshold MOSFETs should be used in most applications.

The only exception is if low input voltage is expected

(V_IN< 5V); then, sub-logic level threshold MOSFETs

(V_GS(TH)< 3V) should be used. Pay close attention to the

BV_DSSspeciﬁcation for the MOSFETs as well; most of the

logic-level MOSFETs are limited to 30V or less.

BothMOSFETshaveI²RlosseswhilethetopsideN-channel

equation includes an additional term for transition losses,

which are highest at high input voltages. For V_IN< 20V

the high current efﬁciency generally improves with larger

MOSFETs, while for V_IN> 20V the transition losses rapidly

increasetothepointthattheuseofahigherR_DS(ON)device

withlowerC_MILLERactuallyprovideshigherefﬁciency. The

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

a short-circuit when the synchronous switch is on close

to 100% of the period.

SelectioncriteriaforthepowerMOSFETsincludethe“ON”

resistance R

, Miller capacitance C

, input

DS(ON)

MILLER

voltage and maximum output current. Miller capacitance,

, can be approximated from the gate charge curve

C

MILLER

The term (1+δ) is generally given for a MOSFET in the

form of a normalized R_DS(ON)vs Temperature curve, but

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

usually provided on the MOSFET manufacturers’ data

sheet. C is equal to the increase in gate charge

MILLER

along the horizontal axis while the curve is approximately

ﬂat divided by the speciﬁed change in V . This result is

DS

then multiplied by the ratio of the application applied V

DS

The optional Schottky diode, D1, shown in Figure 16 con-

ducts during the dead-time between the conduction of the

two power MOSFETs. This prevents the body diode of the

bottom MOSFET from turning on, storing charge during

the dead-time and requiring a reverse recovery period that

to the Gate charge curve speciﬁed V . When the IC is

DS

operating in continuous mode the duty cycles for the top

and bottom MOSFETs are given by:

V_OUT

Main Switch Duty Cycle =

could cost as much as 1% in efﬁciency at high V . A 1A

IN

V

IN

to 3A Schottky is generally a good compromise for both

regions of operation due to the relatively small average

current.Largerdiodesresultinadditionaltransitionlosses

due to their larger junction capacitance.

V – V_OUT

IN

Synchronous Switch Duty Cycle =

V

IN

The MOSFET power dissipations at maximum output

current are given by:

3811f

29

LTC3811

APPLICATIONS INFORMATION

C_INand C_OUTSelection

0.6

0.5

0.4

0.3

0.2

0.1

0

Incontinuousmode,thedraincurrentofeachtopN-channel

MOSFETisasquarewaveofdutycycleV_OUT/V_IN.AlowESR

input capacitor sized for the maximum RMS current must

be used. The details of a close form equation can be found

inApplicationNote77.Figure17showstheinputcapacitor

ripple current for different phase conﬁgurations with the

output voltage ﬁxed and input voltage varied. The input

ripplecurrentisnormalizedagainsttheDCoutputcurrent.

Thegraphcanbeusedinplaceoftediouscalculations.The

minimum input ripple current can be achieved when the

product of phase number and output voltage, N(V_OUT), is

approximately equal to the input voltage V_INor:

1-PHASE

2-PHASE

3-PHASE

4-PHASE

6-PHASE

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

3811 F17

Figure 170 Normilized Input RMS Ripple Current ꢁs

Duty Factor for 1 to 6 Output Stages

V_OUT

k

N

=

where k = 1, 2, ..., N – 1

system.Therequiredamountofinputcapacitanceisfurther

reduced by the factor, N, due to the effective increase in

the frequency of the current pulses.

V

IN

So the phase number can be chosen to minimize the input

capacitor size for the given input and output voltages.

The selection of C_OUTis driven by the required effective

series resistance (ESR). Typically once the ESR require-

ment has been met, the RMS current rating generally far

exceeds the I_RIPPLE(P-P)requirements. The steady-state

output ripple (ΔV_OUT) is determined by:

In the graph of Figure 17, the local maximum input RMS

capacitor currents are reached when:

V_OUT

2k − 1

=

where k = 1, 2, ..., N

V

2N

IN

⎡

⎤

⎥

⎦

1

Theseworst-caseconditionsarecommonlyusedfordesign

becauseevensigniﬁcantdeviationsdonotoffermuchrelief.

Note that capacitor manufacturer’s ripple current ratings

are often based on only 2000 hours of life. This makes

it advisable to further derate the capacitor, or to choose

a capacitor rated at a higher temperature than required.

Several capacitors may also be paralleled to meet size or

height requirements in the design. Always consult the

capacitor manufacturer if there is any question.

ΔV_OUT≈ ΔI_RIPPLEESR+

⎢

8NfC_OUT

⎣

where f = operating frequency of each stage, N is the

number of phases, C_OUT= output capacitance and

ΔI_RIPPLE= combined inductor ripple currents.

The output ripple varies with input voltage since ΔI_Lis a

functionofinputvoltage.Theoutputripplewillbelessthan

50mV at max V_INwith ΔI_L= 0.4I_OUT(MAX)/N assuming:

The graph shows that the peak RMS input current is

reduced linearly, inversely proportional to the number, N

of stages used. It is important to note that the efﬁciency

loss is proportional to the input RMS current squared and

therefore a 2-stage implementation results in 75% less

power loss when compared to a single phase design. Bat-

tery/input protection fuse resistance (if used), PC board

trace and connector resistance losses are also reduced

by the reduction of the input ripple current in a PolyPhase

C_OUTrequired ESR < 2N(R_SENSE) and

C_OUT> 1/(8Nf)(R_SENSE

)

The emergence of very low ESR ceramic capacitors in

small, surface mount packages makes very physically

small implementations possible. The ability to externally

compensate the switching regulator loop using the

LTC3811’s true operational error ampliﬁer allows a much

wider selection of output capacitor types. The ability to

3811f

30

LTC3811

APPLICATIONS INFORMATION

use type III compensation effectively removes constraints

on output capacitor ESR. The impedance characteristics

of each capacitor type are signiﬁcantly different than an

ideal capacitor and therefore require accurate modeling

and bench evaluation during design.

providing a linear ramping voltage at the SS/TRACK pin.

The LTC3811 will regulate the V_FBpin (and hence V_OUT

)

according to the voltage on the SS/TRACK pin, allowing

V_OUTto rise smoothly from 0V to its ﬁnal regulated value.

The total soft-start time will be approximately:

Manufacturers such as Nichicon, United Chemicon and

Sanyoshouldbeconsideredforhighperformancethrough-

hole capacitors. The OS-CON semiconductor dielectric

capacitor available from Sanyo and the Panasonic SP

surface mount types have the lowest (ESR)(size) product

of any aluminum electrolytic at a somewhat higher price.

An additional ceramic capacitor in parallel with OS-CON

type capacitors is recommended to reduce inductance

effects.

0.6V

2.5μA

t_SS= C_SS

•

Alternatively, the SS/TRACK pin can be used to track two

(or more) supplies during start-up, as shown qualitatively

in Figures 19a and 19b. To do this, a resistor divider

should be connected from the master supply (V_X) to the

SS/TRACK pin of the slave supply (V_OUT), as shown in

Figure 20. During start-up V_OUTwill track V_Xaccording

to the ratio set by the resistor divider:

In surface mount applications, multiple capacitors may

have to be paralleled to meet the ESR or RMS current

handling requirements of the application. Aluminum

electrolytic and dry tantalum capacitors are both available

in surface mount conﬁgurations. New special polymer

surface mount capacitors offer very low ESR also but

have much lower capacitive density per unit volume. In

the case of tantalum, it is critical that the capacitors are

surge tested for use in switching power supplies. Several

excellentchoicesaretheAVXTPS,AVXTPSVortheKEMET

T510 series of surface mount tantalums, available in case

heights ranging from 2mm to 4mm. Other capacitor types

include Sanyo OS-CON, Nichicon PL series and Sprague

595D series. Consult the manufacturer for other speciﬁc

recommendations. A combination of capacitors will often

result in maximizing performance and minimizing overall

cost and size.

V_OUTR_TRACKA

R_A+R_B

_TRACKA+R_TRACKB

=

•

V_X

R_A

R

For coincident tracking (V_OUT= V_Xduring start-up),

R_A= R_TRACKA

R_B= R_TRACKB

Note that the small SS/TRACK charging current is always

ﬂowing, producing a small offset error. To minimize this

error, select the tracking resistor divider values to be small

enough to make this error negligible.

Topside MOSFET Driꢁer Supply (C_B, D_B)

External bootstrap capacitors C_Bconnected to the BOOST

and SW pins supply the gate drive voltages for the topside

MOSFETs. Capacitor C_Bin the Functional Diagram is

charged though external diode D_Bfrom DRV_CCwhen the

SW pin is low. When one of the topside MOSFETs is to

be turned on, the driver places the C_Bvoltage across the

gate-source of the desired MOSFET. This enhances the

MOSFET and turns on the topside switch. The switch

Tracking and Soft-Start (SS/TRꢀCK Pins)

The start-up of each V_OUTis controlled by the voltage on

the respective SS/TRACK pin. When the voltage on the

SS/TRACK pin is less than the internal 0.6V reference,

the LTC3811 regulates the V_FBpin voltage to the voltage

on the SS/TRACK pin instead of 0.6V. The SS/TRACK pin

can be used to program an external soft-start function or

to allow V_OUTto “track” another supply during start-up.

LTC3811

SS/TRACK

C

SS

SGND

Soft-startisenabledbysimplyconnectingacapacitorfrom

the SS/TRACK pin to ground, as shown in Figure 18. An

internal 2.5μA current source charges up the capacitor,

3811 F18

Figure 180 Using the SS/TRꢀCK pin to Program Soft-Start

3811f

31

LTC3811

APPLICATIONS INFORMATION

node voltage, SW, rises to V_INand the BOOST pin follows.

With the topside MOSFET on, the boost voltage is above

the input supply: V_BOOST= V_IN+ V_DRVCC. The value of the

boost capacitor C_Bneeds to be 100 times that of the total

input capacitance of the topside MOSFET(s). The reverse

breakdown of the external Schottky diode must be greater

than V_IN(MAX). When adjusting the gate drive level, the

ﬁnal arbiter is the total input current for the regulator. If

a change is made and the input current decreases, then

the efﬁciency has improved. If there is no change in input

current, then there is no change in efﬁciency.

Oꢁerꢁoltage Protection

The LTC3811 contains a comparator that monitors the

FB pin voltage for potential overvoltage conditions. This

comparator (OV in the Functional Diagram) detects when

theFBpinvoltageexceeds0.66V, oris10%abovenominal

regulation.Whenthisconditionissensed,thetopMOSFET

is turned off and the bottom MOSFET is turned on. For an

overvoltageconditionthatpersists,theinductorcurrentwill

reverse until the negative current limit of the converter is

V (MASTER)

X

reached. If the OV condition terminates V

will return to

OUT

V

OUT

(SLAVE)

regulation and normal operation automatically resumes.

The OV signal that controls the top and bottom MOSFET

switching does not propagate through the PGOOD ﬁlter

before action is taken. The OV comparator is capable of

sensing a fault condition within 100ns to 200ns, after

which the top MOSFET is turned off. The PGOOD ﬁlter

will delay the signal to the open-drain NMOS transistor

connectedtothePGOODpin,however,preventingOV(and

UV) transients of less than about 130μs from forcing a

system reset.

TIME

3811 F19a

(19a) Coincident Tracking

V (MASTER)

X

V

OUT

(SLAVE)

Phase-Locked Loop and Frequency Synchronization

The LTC3811 has a phase-locked loop (PLL) comprised of

aninternalvoltage-controlledoscillator(VCO)andaphase

detector. This allows the turn-on of the top MOSFET of

controller 1 to be locked to the rising edge of an external

clock signal applied to the MODE/SYNC pin. The turn-on

phase of controller 2’s top MOSFET is controlled by the

voltage on the PHASEMODE pin. The phase detector is

an edge sensitive digital type that provides zero degrees

phase shift between the external and internal oscillators.

This type of phase detector does not exhibit false lock to

harmonics of the external clock.

3811 F19b

TIME

(19b) Ratiometric Tracking

Figure 190 Two different Modes of Output Votlage Tracking

V

OUT

x

LTC3811

R

B

A

V

FB

R

TRACKB

TRACKA

The output of the phase detector is a pair of comple-

mentary current sources that charge or discharge the

external ﬁlter network connected to the PLL/LPF pin. The

relationship between the voltage on the PLL/LPF pin and

operating frequency, when there is a clock signal applied

SS/TRACK

2.5μA

3811 F20

Figure 2±0 Using the SS/TRꢀCK Pin for Tracking

3811f

32

LTC3811

APPLICATIONS INFORMATION

2.4V

to MODE/SYNC, is shown in Figure 21 and speciﬁed in the

Electrical Characteristics table. Note that the LTC3811 can

onlybesynchronizedtoanexternalclockwhosefrequency

is within range of the LTC3811’s internal VCO, which is

nominally 125kHz to 1.1MHz. This is guaranteed to be

between 175kHz and 900kHz. A simpliﬁed block diagram

is shown in Figure 22.

R

LP

C

LP

PLL/LPF

MODE/

SYNC

DIGITAL

PHASE/

FREQUENCY

DETECTOR

EXTERNAL

OSCILLATOR

If the external clock frequency is greater than the internal

oscillator’s frequency, f_OSC, then current is sourced con-

tinuously from the phase detector output, pulling up the

PLL/LPF pin. When the external clock frequency is less

than f_OSC, current is sunk continuously, pulling down

the PLL/LPF pin. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

the phase difference. The voltage on the PLL/LPF pin is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

the ﬁlter capacitor C_LPholds the voltage.

3811 F22

Figure 220 Phase-Locked Loop Block Diagram

Typically, the external clock (on MODE/SYNC pin) input

high threshold is 1.1V, while the input low threshold

is 1.0V.

Efﬁciency Considerations

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Percent efﬁciency can

be expressed as:

The loop ﬁlter components, C_LPand R_LP, smooth out

the current pulses from the phase detector and provide a

stable input to the voltage-controlled oscillator. The ﬁlter

components C_LPand R_LPdetermine how fast the loop

acquires lock. Typically R_LP= 10k and C_LPis 2200pF

to 0.01μF.

%Efﬁciency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

1200

1100

1000

900

800

700

600

500

400

300

200

100

0

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3811 circuits: 1) IC V_INcurrent, 2) DRV_CC

regulator current, 3) I²R losses, 4) Topside MOSFET

transition losses.

1. The V_INcurrent has two components: the ﬁrst is the

DCsupplycurrentgivenintheElectricalCharacteristics

table, and the second is the MOSFET driver and control

currents.

0

0.5

1

1.5

2

2.5

2. DRV_CCcurrent is the sum of the MOSFET driver and

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched

from low to high to low again, a packet of charge dQ

PLL/LPF PIN VOLTAGE (V)

3811 G36

Figure 210 Relationship Between Oscillator Frequency

and Voltage at the PLL/LPF Pin When Synchronizing to

an External Clock

3811f

33

LTC3811

APPLICATIONS INFORMATION

moves from DRV_CCto ground. The resulting dQ/dt is

a current out of DRV_CCthat is typically much larger

than the control circuit current. In continuous mode,

I_GATECHG= f(Q_T+ Q_B), where Q_Tand Q_Bare the gate

charges of the topside and bottom side MOSFETs.

10% efﬁciency degradation in portable systems. It is very

important to include these “system” level losses during

the design phase. The internal battery and fuse resistance

losses can be minimized by making sure that C_INhas ad-

equate charge storage and very low ESR at the switching

frequency.A25Wsupplywilltypicallyrequire aminimumof

20μFto40μFofcapacitancehavinga maximumof20mΩto

50mΩofESR. TheLTC38112-phasearchitecturetypically

halvesthisinputcapacitancerequirementovercompeting

solutions. Other losses including Schottky conduction

lossesduringdead-timeandinductorcorelossesgenerally

account for less than 1% total additional loss.

Supplying DRV and INTV_CCpower through the

CC

EXTV_CCswitch input from an output-derived source

will scale the V_INcurrent required for the driver and

control circuits by a factor of (Duty Cycle)/(Efﬁciency).

For example, in a 20V input to 2.5V output application,

40mA of DRV_CCcurrent results in approximately 5mA

of V_INcurrent. This reduces the mid-current efﬁciency

loss from 10% or more (if the driver was powered

directly from V_IN) to only a few percent.

Feedback Loop Compensation

The LTC3811 incorporates a peak current mode control

topology. Peak current mode control provides excellent

line and load transient response, and inherently provides

the best possible phase-to-phase current sharing in

multiphase applications.

3. I²R losses are predicted from the DC resistances of

the fuse (if used), MOSFET, inductor, current sense

resistor, and input and output capacitor ESR. In

continuous mode the average output current ﬂows

through L and R_SENSE, but is “chopped” between the

topside MOSFET and the synchronous MOSFET. If the

The LTC3811 incorporates a true operational error ampli-

ﬁer in the feedback loop, enabling the user the ﬂexibility

to place poles and zeros at well deﬁned frequencies in

the transfer function, thereby optimizing the loop’s AC

response.

two MOSFETs have approximately the same R_DS(ON)

,

then the resistance of one MOSFET can simply be

summed with the resistances of L, R_SENSEand ESR to

obtainI²Rlosses.Forexample,ifeachR_DS(ON)=5mΩ,

R_L= 1mΩ, R_SENSE= 1.5mΩ and R_ESR= 4mΩ (sum

of both input and output capacitance losses), then the

totalresistanceis16mΩ.Thisresultsinlossesranging

from 5.6% to 8.4% as the output current increases

from 10A to 15A for a 2.5V output. Efﬁciency varies

as the inverse square of V_OUTfor the same external

components and output power level. The combined

effectsofincreasinglyloweroutputvoltagesandhigher

currentsrequiredbyhighperformancedigitalsystems

isnotdoublingbutquadruplingtheimportanceofloss

terms in the switching regulator system!

The control-to-output transfer function has a pole at the

origin in order to provide DC regulation, and a pole due

to the load resistance and capacitance at:

1

f_P(LOAD)

=

2π •R_L• C_L

The output decoupling capacitor ESR contributes a zero

to the transfer function at:

1

f_Z(ESR)

=

2π •ESR • C_L

4. Transition losses apply only to the topside MOSFET(s),

and become signiﬁcant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

Thetransferfunctionalsohasamathematicaldoublepoleat

half the switching frequency due to the sampling nature of

currentmodecontrol,althoughthepole-splittingbehavior

of the LTC3811’s internal slope compensation reduces the

₂I_MAX

Translation Loss = V

•R_DR•C_MILLER

phase shift for frequencies below f /2.

(

)

SW

IN

2

Formostsystems,thesimple2-pole,single-zeroresponse

of a Type-II compensation network (shown in Figure 23)

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

3811f

34

LTC3811

APPLICATIONS INFORMATION

to achieve a good combination of bulk capacitance and

low ESR. In general, the output capacitor is not normally

chosen to optimize the bode response.

will provide adequate phase margin at the unity-gain

frequency of the loop.

In a Type-II compensation scheme, the zero is typically

placed below the target unity-gain frequency, depending

uponthedesiredsettlingtimeoftheconverter,andthepole

is placed no higher than half the switching frequency in

order to attenuate the switching frequency from the loop.

The gain between the zero and pole is typically adjusted

until the desired phase margin is achieved.

Due to their small case size and low ESR, ceramic output

capacitors are well suited to very low voltage, high current

applications.TheirlowESRandrelativelyhighRMScurrent

capability make them a good choice for today’s demand-

ing processor-based loads. A fully ceramic output stage,

however, will result in very low ESR, pushing the ESR zero

frequencyrelativelyclosetotheunity-gainfrequencyofthe

loop. In this case a Type-III compensation network using

3 poles and 2 zeros may be necessary (see Figure 24). For

particularly demanding applications requirements, please

consult Linear Technology’s Applications department.

In general, the output capacitor is chosen based on cost

and size considerations, given a certain error budget

due to output ripple voltage and load transient response.

Oftentimes, multiple capacitor types (such as ceramic

and special polymer) are connected in parallel in order

C1

V

OUT

C1

V

C2

OUT

R3

C2

R4

C3

R3

R2

–

+

–

+

R1

0.6V

EA

R1

0.6V

1

f

=

P1

P2

f

=

f

=

2π • R2 C1+ C2

(

)

P1

P2

Z1

2π• R3 • C2

2π • R2 C1+ C2

(

)

1

=

f

=

⎛ C1• C2 ⎞

⎝ C1+ C2⎠

Z2

⎛ C1• C2 ⎞

⎝ C1+ C2⎠

2π• R2 + R4 • C3

(

)

2π • R3

⎜

⎟

2π • R3

⎜

⎟

1

f

=

Z

f

=

2π • R3 • C2

P3

2π• R4 • C3

f

P2

30

20

10

Z

f

Z1

f

Z2

f

P2

f

P3

30

20

10

R3

R1

A

= 20 log •

V

–20dB

DECADE

–20dB/DECADE

f

–20dB/DECADE

f

–20dB

DECADE

f

90

45

–45

–90

f

0

–45

–90

3811 F23

3811 F24

Figure 230 Type-II Compensation Network and

Frequency Response

Figure 240 Type-III Compensation Network and

Frequency Response

3811f

35

LTC3811

APPLICATIONS INFORMATION

ity without having to break the feedback loop. Placing a

power MOSFET directly across the output capacitor and

driving the gate with an appropriate signal generator or

gate driver is a practical way to produce a realistic load

step condition.

Measuring the Loop’s Transient Response

Oncethecompensationcomponentshavebeenchosen,the

AC performance of the power supply should be veriﬁed in

the lab. The two most common ways of checking the AC

response of the circuit are with load and line steps, and

by measuring the loop gain using a network analyzer or

Venablemeasurementsystem.Bothofthesemeasurement

techniques should be performed on the ﬁnal design to en-

sure adequate correlation between the two, and to identify

and correct potential regions of marginal stability. These

measurements should be performed over all of the load,

line,temperatureandcomponentstolerancevariationsthe

system will experience in a practical application.

Voltage Positioning for Single Output,

Multiphase ꢀpplications

The output voltage load line can be programmed with the

LTC3811 using one external resistor, allowing the user to

reduce the total output capacitance required for a given

error budget. The inductor current information is sensed

+

–

using the SENSE and SENSE inputs for both channels

and fed into a transconductance ampliﬁer with two input

stages, as shown in Figure 26. The output current of the

transconductance ampliﬁer, along with one external resis-

Figure 25 illustrates a typical load step response for the

LTC3811. When a positive load step occurs, the output

voltage immediately drops by ΔI

• ESR, where ESR

LOAD

tor (R ), allows the user to inject a load-current-related

AVP

is the equivalent series resistance of the output capacitor.

The increased load current then begins to discharge the

output capacitor, generating a feedback error signal that

forces the regulator to adapt to the current change and

errorsignalintothevoltagefeedbackloop.Pleasenotethat

becausetheg ampliﬁermixesthesignalsfrombothchan-

m

nels, voltage positioning is only possible for multiphase,

single output applications; dual output applications with

voltage positioning are not possible.

return V

to its steady-state regulated value. During

OUT

this recovery time V

can be monitored for excessive

OUT

The internal mixing of the current sense signals within

the voltage positioning ampliﬁer, combined with the fact

overshoot or ringing which would indicate a stability

problem. Assuming a second order system, the phase

margin and/or damping factor can be estimated using the

percentage overshoot seen at the output.

that the g ampliﬁer output signal is a current, allows the

m

user to connect the CSOUT pins of several LTC3811 chips

togetherinmultiphaseapplications.Thetransconductance

Anoutputcurrentpulseof20%to100%offullloadhaving

a rise time of 0.1μs to 1ꢀs will produce an output voltage

waveform that will give an indication of the loop stabil-

(g ) of the voltage positioning ampliﬁer is 2.5mS/phase,

m

and the load slope is:

R_SENSE

R2

R1

⎡

⎤

⎡

⎤

⎥

V_OUT= 0.6 • 1+

– I_OUT

•

• 5m •R_AVP

⎢

⎥

⎢

n

⎣

⎦

⎣

⎦

V

OUT

50mV/DIV

where n is the number of phases.

AC COUPLED

The input common mode range of the voltage position

m

g ampliﬁer is 0.6V to 3.5V, comfortably allowing output

I

L

5A/DIV

voltages up to 3.3V. In addition, the output voltage range

of the g ampliﬁer for linear operation is limited to volt-

m

ages above 0.6V, due to the headroom requirements of

the NMOS sink transistors in the output stage. And ﬁnally,

themaximumdifferentialinputvoltageforlinearoperation

is 100mV.

3811 G02

V

LOAD

= 12V

20μs/DIV

IN

= 1.5V

OUT

I

= 0.5A TO 8A

Figure 2.0 Load Step Response for the

LTC3811 Circuit in Figure 33

3811f

36

LTC3811

APPLICATIONS INFORMATION

V

OUT

50mV/DIV

L1

L2

+

–

AC COUPLED

SENSE1

SENSE2

SENSE1

SENSE2

CSOUT

I

L1

+

5A/DIV

g

R

S1

R

m

S2

–

I

CSAMP

L2

5A/DIV

3811 G03

V

LOAD

= 12V

50μs/DIV

IN

= 1.5V (2-PHASE)

OUT

I

= 0A TO 15A

SGND

+

80k

DIFFIN

Figure 270 Load Step Response for the Circuit in Figure 3±

R

80k

AVP

+

–

C

OUT

To program 500kHz operation, ﬂoat the PLL/LPF pin.

The inductor value in this design is chosen assuming

50% ripple current. The highest ripple current occurs at

maximum input voltage.

–

DIFFAMP

DIFFIN

DIFFOUT

COMP

C2

R3

⎡

⎤

⎥

⎦

V_OUT

f • ΔI_L

V_OUT

C1

FB

EA

L =

• 1–

⎢

0.6V

+

–

R2

R1

V

⎢

⎣

IN(MAX) ⎥

3811 F26

1.5V

500kHz • 0.5 • 15A

A 0.4ꢀH inductor will result in 6.7A of ripple current, or

45%. Assuming a value for the current limit value 30%

greater than the maximum load current, then I

1.5V

14V

⎡

⎤

SGND

=

• 1–

= 0.36μH

⎢

⎥

⎣

⎦

Figure 260 Simpliﬁed LTC3811 Voltage Positionig Block Diagram

Figure 27 illustrates the load step response for the circuit

in Figure 30, with voltage positioning.

= 1.3 •

MAX

15A = 19.5A. The peak inductor current will be the maxi-

mum DC value plus one half the ripple current, or:

ꢀ Design Example

As a design example consider one channel of a 2-phase

1

2

I

_L(PK)= 19.5A + • 6.7A = 22.9A

single output supply. Assume V = 4.5V to 14V, V

=

IN

OUT

1.5V, I

= 30A(15A per phase) and f = 500kHz.

MAX

This represents the minimum saturation current rating for

theinductor.Forthisapplication,aVitec59P9875inductor

was chosen. This inductor has a room temp saturation

current rating of 23A and a DCR of 0.32mΩ.

In order to achieve the best output accuracy, 1% resistors

(or better) should be used in the divider that programs the

output voltage. Choosing 600ꢀA for the divider current,

R2 = 1.5k and R1 = 1k. The nominal output voltage will

therefore be 1.50V.

To maintain good cycle-by-cycle control of the inductor

current and still have good efﬁciency, a 1.5mΩ, 1W sense

resistor from Panasonic (ERJ-M1WTJ1M5U) connected

in series with the inductor is used for current sensing.

With a maximum peak inductor current of 22.9A, the peak

sense voltage will be:

Fortheinputandoutputconditionsgivenabove,thesteady

state minimum on-time for this application at V = 14V

IN

will be approximately:

V_OUT

_IN(MAX)• f 14V • 500kHz

1.5V

t_ON(MIN)

=

= 214ns

V

= 22.9A • 0.0015Ω = 34.4mV

SENSE(PK)

3811f

37

LTC3811

APPLICATIONS INFORMATION

The maximum power dissipation in the sense resistor

The power MOSFETs chosen for this application are the

Renesas RJK0305DPB (top) and RJK0301DPB (bottom).

The upper MOSFET, which is optimized for low switching

will be:

2

P

= 22.9A • 0.0015Ω = 0.79W

R(SENSE)

losses, has a typical R

of 10mΩ at V = 4.5V, a

DS(ON)

GS

DSS

To ensure that the maximum current can be delivered

over all of the power component and IC tolerances, the

maximum sense voltage for the LTC3811 is chosen to be

50mV. This is programmed by connecting the RNG pin

total gate charge of 8nC, and a minimum BV

of 30V.

The bottom MOSFET, which is zero-voltage switched and

is optimized for low on-resistance, has a typical R

DS(ON)

of 3mΩ at V = 4.5V, a total gate charge of 32nC, and a

GS

to INTV .

minimum BV

of 20V.

CC

DSS

Due to the use of a 400nH inductor and 500kHz opera-

tion, the magnitude of the inductive voltage drop across

the sense resistor should be calculated and compared to

the maximum sense voltage (50mV). First calculate the

nominal switch on-time:

From the datasheet of the RJK0305DPB upper MOSFET,

the Miller capacitance is calculated to be:

ΔQ_G

2nC

C_MILLER

=

= 167pF

ΔV_DS12V

V_OUT

Assuming a top MOSFET junction temperature of 75°C,

δ = 0.25 and the power dissipated in this MOSFET is:

1.5V

t_ON

=

= 250ns

V • f 12V • 500kHz

IN

V_OUT

I_MAX

2

The inductor ΔI /dt is therefore:

2

L

P_MAIN

=

•I_MAX•R_DS(ON)• 1+ δ + V

•

T

(

)

IN

V

IN

ΔI_L

dt 250ns

6.7A 26.8A

=

⎡

⎢

⎣

⎤

⎥

⎦

μs

1

• R_DR• C_MILLER

•

+

• f

V

– V_TH(MIN)V_{TH(MIN) ⎥}

⎢ INTVCC

The Panasonic sense resistor has a typical parasitic series

inductance (ESL) of 0.5nH, meaning that the inductive

voltage drop across the resistor is:

1.5V

12V

15A

2

P_MAIN

• 15A²• 0.01• 1+ 0.25 + 12V²•

(

)

ΔI_L

dt

26.8A

μs

1

⎤

⎡

V_L(SENSE)= ESL •

= 0.5nH •

= 13.4mV

• 2Ω • 167pF •

+

• 500kHz

⎥

⎢

6V – 1V 1V

⎣

⎦

The ESL/R time constant for the sense resistor is

therefore:

P_MAIN= 0.351W + 0.216W = 0.567W

For the synchronous MOSFET the power dissipation is:

ESL

R_SENSE

τ =

= 333ns

V – V_OUT

2

IN

P_SYNC

=

•I_MAX•R_DS(ON)• 1+ δ

(

)

V

IN

ThesensepinsneedanRCﬁlterwiththesametimeconstant

+

–

in order for the waveform at the SENSE and SENSE pin

to accurately represent the inductor current. Choosing a

value of 1000pF for the ﬁlter capacitor, the total resistance

12V – 1.5V

12V

P_MAIN

• 15A²• 0.003 • 1+ 0.25

(

)

+

should therefore be 333Ω. Split between the SENSE

= 0.738W

–

and SENSE pins, each resistor should be 165Ω. These

TodeterminetheRMScurrentratingoftheinputcapacitor,

we need to ﬁrst determine the minimum and maximum

dutycycle.Foranoutputvoltageof1.5Vandaninputrange

of 4.5V to 14V, the duty cycle range is 12.5% to 33.3%.

We then use Figure 17 to determine the percentage of

+

components should be placed adjacent to the SENSE and

–

SENSE pins on the LTC3811, and the PCB traces from

the 165Ω ﬁlter resistors should be minimum width and

run parallel to each other all the way to the sense resistor

location on the board.

3811f

38

LTC3811

APPLICATIONS INFORMATION

the maximum load current that represents the minimum

RMS current rating of the input capacitor. The worst-case

condition occurs when only one output is operational. The

3. Thebottomterminalsoftheinputandoutputcapacitors

should be placed as close as possible to one another,

with the small-signal ground connection in between

them. This component arrangement will reduce dif-

ferential mode noise due to the two high di/dt loops

in the power circuit.

output with the highest (V )(I ) product should be

OUT OUT

used to determine the minimum RMS current rating of the

input capacitor. From Figure 17 we can see that the worst

caseconditionforthisoutputoccursatthemaximumduty

cycle of 33.3%, and that the minimum RMS current rating

of the input capacitor needs to exceed 7A (47% of 15A).

4. If the output capacitor is located far away from the

IC and the remote sense differential ampliﬁer is being

used to level-shift the output voltage back to the local

ICground,thesmall-signalgroundaroundtheLTC3811

should be Kelvin-connected to the main ground node

near the bottom terminal of the input capacitor.

The ceramic output capacitors chosen have an effective

ESR of 5mΩ and a bulk capacitance of 660ꢀF. The peak-

to-peak output ripple for this conﬁguration is:

5. The PGND pin should be connected to the sources

of the bottom MOSFETs using a wide, short trace on

the top layer of the board. The MOSFETs should also

be placed on the top layer of the board. The exposed

area on the bottom of the QFN package is internally

connected to the PGND node of the IC.

⎡

⎤

⎥

⎦

1

ΔV_OUT= ΔI • ESR +

⎢

L

8 • n • f • C_OUT

⎣

1

⎡

⎤

= 6.7A • 0.005Ω +

⎢

⎥

8 • 2 • 500kHz • 660μF

⎣

⎦

ΔV_OUT= 33.5mV + 1.3mV = 34.8mV

6. Place the INTV analog supply decoupling capacitor

CC

and resistor right next to the INTV and SGND pins

CC

This represents a ripple voltage of 2.3%. As can be seen

fromthecalculation,thebiggestportionoftheoutputripple

comes from the ESR of the capacitor. This is why low ESR

ceramic capacitors are so important in low voltage, high

current applications.

on the same layer as the IC. A low ESR 0.1ꢀF to 1ꢀF

ceramic capacitor should be used.

7. PlacetheDRV gatedriversupplydecouplingcapaci-

CC

tor right next the DRV and PGND pins, on the same

CC

layerastheIC.Thiscapacitorcarrieshighdi/dtMOSFET

gate drive currents. A low ESR (X5R or better) 4.7ꢀF

to 10ꢀF ceramic capacitor should be used.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the converter:

8. The ﬂoating gate driver supply decoupling capacitor

should be located right next the BOOST and SW pins,

onthesamelayerastheIC. Thiscapacitorcarrieshigh

di/dt currents to drive the upper power MOSFETs. A

lowESR(X5Rorbetter)ceramiccapacitoratleast100

times the total input capacitance of the upper power

MOSFETs for that channel should be used.

1. TheconnectionbetweentheSGNDpinontheLTC3811

and all of the small-signal components surrounding

the IC should be isolated from the power ground and

PGNDpin,andshouldbeKelvin-connectedtothemain

ground node near the bottom terminal of the output

capacitors.

9. TheresistordividerconnectedtotheFBpintoprogram

the output voltage should be located as near as pos-

sible to the IC, with the bottom resistor connecting to

the isolated signal ground node near the SGND pin.

The PCB trace connecting the top resistor to the upper

terminal of the output capacitor should avoid any high

2. Place the small-signal components away from high

frequencyswitchingnodesontheboard.Thepinoutof

the LTC3811 was carefully designed in order to make

component placement as easy and noise free as pos-

sible. All of the power components can be placed on

one side of the IC, away from all of the small-signal

components.

3811f

39

LTC3811

APPLICATIONS INFORMATION

frequency switching nodes in the circuit and should

ideally be shielded (both laterally and vertically) by

ground planes.

especially from the opposite channel’s voltage- and

current-sensing feedback signals. The SW, TG and

BOOST nodes can have slew rates in excess of 1V/ns

relative to ground and should therefore be kept on

the “output side” of the LTC3811.

10. Ifthedifferentialremotesenseampliﬁerisbeingused,

+

–

the PCB traces connecting DIFF/IN and DIFF/IN to

theoutputcapacitorshouldavoidanyhighfrequency

switching nodes in the circuit and should ideally be

shielded (both laterally and vertically) by ground

16. Check the stress on the power MOSFETs by indepen-

dentlymeasuringthedrain-to-sourcevoltagesdirectly

across the devices terminals. Beware of inductive

ringing that could exceed the maximum voltage rating

of the MOSFET. If this ringing cannot be avoided and

exceeds the maximum rating of the device, choose a

higher voltage rated MOSFET.

+

–

planes. In addition, the DIFF/IN and DIFF/IN PCB

traces should be routed parallel to one another with

minimum spacing in between. Due to the 160kΩ

input impedance of these pins, it is critical that these

traces avoid any high frequency switching nodes in

the circuit.

17. WhensynchronizingtheLTC3811toanexternalclock,

use a low impedance source such as a logic gate to

drive the MODE/SYNC pin and keep the lead as short

as possible.

11. The high di/dt loops formed by the input capacitor

and the power MOSFETs should be kept as small as

possible to avoid EMI and differential mode switching

noise. The upper power MOSFETs should be located

close to one another and as close as possible to the

positive terminal of the input decoupling capacitor. Do

not attempt to split the input decoupling for the two

channels as it can cause a large resonant loop.

18. Minimize the capacitive load on the CLKOUT pin to

minimizeexcessphaseshift.BuffertheCLKOUTsignal

with an emitter follower if necessary.

ThediagraminFigure28illustratesallthebranchcurrentsin

a2-phasesingleoutputswitchingregulator.Afterstudying

thewaveformsitisclearwhyitiscriticaltoreducethearea

of the high dV/dt nodes as much as possible. High electric

and magnetic ﬁelds will radiate from these “loops,” just as

a radio station broadcasts a signal. The output capacitor

ground should return to the negative terminal of the input

capacitor and not share a common ground path with any

switched current paths. The left half of the circuit gives

rise to the “noise” generated by the switching regulator.

ThegroundterminationsofthesynchronousMOSFETsand

Schottkyoptionaldiodesshouldreturntothebottomplate

of the input capacitor with a short, isolated PC trace since

very high di/dt currents are present. A separate, isolated

path from the negative terminals of the input and output

capacitors should be used to connect the IC signal ground

pin (SGND). This technique keeps inherent signals gener-

ated by the high di/dt current pulses from taking alternate

current paths that have ﬁnite impedances during the total

period of the switching regulator.

12. The bottom MOSFETs sources should also be located

close to one another and as close as possible to the

negative terminal of the input capacitor. Since the

inductor can be modeled as a current source, its

placement on the board is less critical than the high

di/dt components.

13. The switch node area should be kept small, with

the upper power MOSFET sources and lower power

MOSFET drains in close proximity.

+

–

14. The ﬁlter capacitor between the SENSE and SENSE

pins, as well as the ﬁlter resistors, should be located

as close as possible to the IC. In addition, the connec-

+

–

tions between the SENSE and SENSE ﬁlter resistors

and the sense resistor should be routed parallel to one

another with minimum spacing in between. These

traces should avoid any high frequency switching

nodes in the circuit.

15. Keep the switch nodes (SW1, SW2), the top gate

nodes (TG1, TG2) and the boost nodes (BOOST1,

BOOST2) away from sensitive small-signal nodes,

3811f

40

LTC3811

APPLICATIONS INFORMATION

PC Board Layout Debugging

Variation in the duty cycle at a subharmonic rate can sug-

gest noise pickup at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regula-

tor bandwidth optimization is not required. Only after

each controller is checked for its individual performance

should both controllers be turned on at the same time.

A particularly difﬁcult region of operation is when one

controller channel is nearing its current comparator trip

pointwhentheotherchannelisturningonitstopMOSFET.

This occurs around 50% duty cycle on either channel due

to the phasing of the internal clocks and may cause minor

duty cycle jitter.

Start with one controller on at a time. It is helpful to use

a DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switching node (SW pin) to synchronize the oscilloscope

totheinternaloscillatorandprobetheactualoutputvoltage

as well. Check for proper performance over the operating

voltage and current range expected in the application. The

frequency of operation should be maintained over the

input voltage range.

Thedutycyclepercentageshouldbemaintainedfromcycle

tocycleinawell-designed,lownoisePCBimplementation.

SW1

D1

L1

R

SENSE1

V

IN

V

OUT

R

IN

C

OUT

+

C

IN

R

L

SW2

L2

R

SENSE2

D2

BOLD LINES INDICATE

HIGH, SWITCHING

CURRENT LINES.

KEEP LINES TO A

MINIMUM LENGTH.

3811 F28

Figure 280 Instantaneous Current Path Flow in a Multiple Phase Switching Regulator

3811f

41

LTC3811

APPLICATIONS INFORMATION

Reduce V_INfrom its nominal level to verify operation of

for inductive coupling between C_IN, Schottky and the top

MOSFET components to the sensitive current and voltage

sensing traces. In addition, investigate common ground

path voltage pickup between these components and the

SGND pin of the IC.

the regulator at low V . Check the operation of the un-

IN

der-voltage lockout circuit by further lowering V_INwhile

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

An embarrassing problem, which can be missed in an

otherwise properly working switching regulator, results

when the current sensing leads are hooked up backwards.

The output voltage under this improper hookup will still

be maintained but the advantages of current mode control

will not be realized. Compensation of the voltage loop will

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

3811f

42

LTC3811

TYPICAL APPLICATIONS

V

IN

4.5V TO 14.5

1Ω

47μF

X5R

330μF

16V

0.1μF

10μF

X5R

BAT54

EXTV

V

INTV

DRV

CC

IN

CC

RJK0305DPB

0.1μF

RJK0305DPB

RJK0301DPB

TG1

TG2

0.1μF

BOOST1

SW1

BOOST2

SW2

RJK0301DPB

1.21k

BG1

BG2

CLKOUT

PLL/LPF

PGND

100k

PGOOD1

PGOOD2

CS/OUT

INTV

CC

1.21k

MODE/SYNC

PHASMODE

100k

LTC3811

0.4μH

0.5mΩ

680nF

0.4μH

0.5mΩ

+

SENSE1

SENSE2

1.21k

–

SENSE1

SENSE2

+

DIFF/IN

RNG2

RNG1

RUN2

RUN1

–

DIFF/IN

7.5k

1%

V

OUT1

11.8k

1%

2V

V

1.5V

15A

OUT2

DIFF/OUT

FB2

15A

FB1

33pF

100pF

33pF

100pF

330μF

×2

47μF

X5R

COMP2

COMP1

47μF

X5R

330μF

×2

56k

4.99k

1%

4.99k

1%

SS/TRACK1 SGND SS/TRACK2

5nF

3811 F29

2.43k

1.21k

Figure 290 High Efﬁciency Core-I/O Power Supply with Differential Remote Sensing and Tracking

3811f

43

LTC3811

TYPICAL APPLICATIONS

AUX 5V GATE

V

IN

1μF

DRIVE SUPPLY

12V

1.0Ω

100μF

X5R

×4

BAT54

0.33μF

BAT54

100k

10μF

X5R

EXTV

V

IN

INTV

DRV

CC CC

CC

TO SUPPLY

MONITOR

PGOOD1

PGOOD2

BOOST1

TG1

RJK0305DPB

5nF

0.4μH

0.0015Ω

SS/TRACK1

SW1

RJK0301DPB

SS/TRACK2

RNG1

BG1

PGND

50Ω

2200pF

+

RNG2

SENSE1

–

MODE/SYNC

CLKOUT

SENSE1

0.33μF

50Ω

BOOST2

TG2

LTC3811

RJK0305DPB

PLL/LPF

0.4μH

0.0015Ω

PHASEMODE

SW2

V

OUT

1V

30A

SGND

RUN1

BG2

RJK0301DPB

100μF

X5R

330μF

×6

50Ω

+

RUN2

SENSE2

2200pF

–

SENSE2

3.32kΩ

1%

50Ω

500Ω

INTV

FB2

CSOUT

CC

+

FB1

DIFF/IN

33pF

100pF

–

COMP1

COMP2

DIFF/IN

4.99k

1%

DIFF/OUT

285k

3811 F30

100pF

Figure 3±0 2-Phase, 12V Input, 1V/3±ꢀ Output ꢀSIC Supply with Voltage Positioning

3811f

44

LTC3811

TYPICAL APPLICATIONS

AUX 5V GATE

V

IN

12V

1μF

DRIVE SUPPLY

1.0Ω

47μF

X5R

470μF

BAT54

0.33μF

BAT54

100k

10μF

X5R

EXTV

V

INTV

DRV

CC CC

CC

IN

TO SUPPLY

MONITOR

PGOOD1

BOOST1

TG1

RJK0305DPB

0.4μH

5nF

PGOOD2

0.0015Ω

SS/TRACK1

SW1

RJK0301DPB

SS/TRACK2

RNG1

BG1

PGND

LTC3811

50Ω

2200pF

+

RNG2

SENSE1

–

MODE/SYNC

SENSE1

0.33μF

50Ω

PHASEMODE

FB2

BOOST2

TG2

OUTPUT 1

ON/OFF

RJK0305DPB

CONTROL

0.4μH

0.0015Ω

PLL/LPF

SW2

V

1.5V

45A

OUT1

RJK0301DPB

CLKOUT

RUN1

BG2

200μF

X5R

CSOUT

2000μF

50Ω

+

SENSE2

RUN2

2200pF

50Ω

–

SENSE2

7.5k

1%

+

FB1

DIFF/IN

33pF

–

COMP1

COMP2

DIFF/IN

100pF

4.99k

1%

DIFF/OUT

SGND

285k

100pF

AUX 5V GATE

DRIVE SUPPLY

1μF

1.0Ω

22μF

X5R

BAT54

0.33μF

BAT54

100k

10μF

X5R

EXTV

V

INTV

DRV

CC CC

CC

IN

TO SUPPLY

MONITOR

PGOOD2

PGOOD1

RNG1

BOOST1

TG1

RJK0305DPB

0.4μH

0.0015Ω

SW1

RJK0301DPB

RNG2

FB1

BG1

LTC3811

PGND

50Ω

2200pF

50Ω

+

5nF

PHASEMODE

SENSE1

–

SS/TRACK2

SS/TRACK1

SENSE1

0.1μF

BOOST2

TG2

RJK0305DPB

10nF

10k

CLKOUT

PLL/LPF

0.4μH

0.0015Ω

V

3.3V

5A

OUT2

SW2

RJK0301DPB

MODE/SYNC

RUN1

BG2

22μF

X5R

100μF

CSOUT

50Ω

2200pF

50Ω

+

SENSE2

COMP1

RUN2

–

SENSE2

22.6k

1%

FB2

DIFF/OUT

33pF

100pF

+

COMP2

DIFF/IN

–

DIFF/IN

SGND

28.5k

4.99k

Figure 310 3-Phase, 12V Input, 10.V/4.ꢀ Output with a 303V/.ꢀ ꢀuxiliary Output

3811f

45

LTC3811

PACKAGE DESCRIPTION

UHF Package

38-Lead Plastic QFN (.mm × 7mm)

(Reference LTC DWG # 05-08-1701)

0.70 ± 0.05

5.50 ± 0.05

(2 SIDES)

4.10 ± 0.05

(2 SIDES)

3.15 ± 0.05

(2 SIDES)

PACKAGE

OUTLINE

0.25 ± 0.05

0.50 BSC

5.15 ± 0.05 (2 SIDES)

6.10 ± 0.05 (2 SIDES)

7.50 ± 0.05 (2 SIDES)

RECOMMENDED SOLDER PAD LAYOUT

PIN 1 NOTCH

R = 0.30 TYP OR

0.35 × 45° CHAMFER

3.15 ± 0.10

(2 SIDES)

0.75 ± 0.05

5.00 ± 0.10

(2 SIDES)

37 38

0.00 – 0.05

0.40 ±0.10

PIN 1

TOP MARK

(SEE NOTE 6)

1

2

5.15 ± 0.10

(2 SIDES)

7.00 ± 0.10

(2 SIDES)

0.40 ± 0.10

0.200 REF 0.25 ± 0.05

R = 0.115

TYP

(UH) QFN 0205

0.50 BSC

0.200 REF

BOTTOM VIEW—EXPOSED PAD

0.75 ± 0.05

0.00 – 0.05

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE

OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3. ALL DIMENSIONS ARE IN MILLIMETERS

3811f

46

LTC3811

PACKAGE DESCRIPTION

G Package

36-Lead Plastic SSOP (.03mm)

(Reference LTC DWG # 05-08-1640)

12.50 – 13.10*

(.492 – .516)

1.25 ±0.12

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19

7.8 – 8.2

5.3 – 5.7

7.40 – 8

(.291 – .

0.42 ±0.03

0.65 BSC

5

7

8

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

6

9 10 11 12 13 14 15 16 17 18

2.0

(.079)

MAX

5.00 – 5.60**

(.197 – .221)

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.25

(.0035 – .010)

0.55 – 0.95

(.022 – .037)

0.05

0.22 – 0.38

(.009 – .015)

TYP

(.002)

NOTE:

MIN

1. CONTROLLING DIMENSION: MILLIMETERS

G36 SSOP 0204

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .152mm (.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

3811f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

47

LTC3811

RELATED PARTS

PꢀRT NUMBER

DESCRIPTION

COMMENTS

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Ultralow I , Dual Output Synchronous Step-Down

50μA I , 0.8V ≤ V

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Q

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Low I , V from 4V to 36V, V

from 0.8V to 10V, 5mm × 5mm

Q

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QFN32

Dual, 2-Phase Synchronous Step-Down Controller with Up to Six Phases, 0.8V ≤ V

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IN

OUT

LTC3835/LTC3835-1

LT3845

Low I Synchronous Step-Down Controller

Single Channel LTC3827/LTC3827-1

1.23V ≤ V ≤ 36V, 4V ≤ V ≤ 60V, 120μA I

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Low I , High Voltage Single Output Synchronous

Q

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No R

is a trademark of Linear Technology Corporation.

SENSE

3811f

LT 0807 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

48

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3811EUHF-TRPBF
厂家：	Linear
描述：	High Speed Dual, Multiphase Step-Down DC/DC Controller 高速双通道，多相降压型DC / DC控制器控制器
文件：	总48页 (文件大小：537K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3811EUHF-TRPBF [Linear]

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