LTC3812EFE-5#PBF_技术文档

LTC3812-5

60V Current Mode

Synchronous Switching

Regulator Controller

FEATURES

DESCRIPTION

The LTC3812-5 is a synchronous step-down switching

regulator controller that can directly step down voltages

from up to 60V input, making it ideal for telecom and

automotive applications. The LTC3812-5 uses a constant

on-time valley current control architecture to deliver very

low duty cycles with accurate cycle-by-cycle current limit

without requiring a sense resistor.

n

High Voltage Operation: Up to 60V

n

Large 1Ω Gate Drivers

n

No Current Sense Resistor Required

n

Dual N-Channel MOSFET Synchronous Drive

n

Extremely Fast Transient Response

n

0.5% 0.8V Voltage Reference

n

Programmable Soft-Start

n

Generates 5.5V Driver Supply

A precise internal reference provides 0.5% DC accuracy.

A high bandwidth (25MHz) error ampliﬁer provides very

fast line and load transient response. Large 1Ω gate driv-

ers allow the LTC3812-5 to drive large power MOSFETs

for higher current applications. The operating frequency

is selected by an external resistor and is compensated for

n

Selectable Pulse Skip Mode Operation

n

Power Good Output Voltage Monitor

n

Adjustable On-Time/Frequency: t

< 100ns

ON(MIN)

n

Adjustable Cycle-by-Cycle Current Limit

Undervoltage Lockout On Driver Supply

Output Overvoltage Protection

variations in V . A shutdown pin allows the LTC3812-5 to

IN

Thermally Enhanced 16-Pin TSSOP Package

be turned off reducing the supply current to <230μA.

Integrated bias control generates gate drive power from

theinputsupplyduringstart-upandwhenanoutputshort-

circuit occurs, with the addition of a small external SOT23

MOSFET. When in regulation, power is derived from the

outputforhigherefﬁciency.

APPLICATIONS

n

48V Telecom and Base Station Power Supplies

n

Networking Equipment, Servers

n

Automotive and Industrial Control Systems

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents,

including 5481178, 5847554, 6304066, 6476589, 6580258, 6677210, 6774611.

TYPICAL APPLICATION

High Efﬁciency High Voltage Step-Down Converter

V

IN

6V TO 60V

R

ON

+

Efﬁciency vs Load Current

100k

C

IN

22μF

110k

100

M3

ZXMN-

10A07F

I

NDRV

ON

V

= 12V

IN

100k

95

90

85

BOOST

PGOOD

LTC3812-5

PGOOD

M1

L1

V

TG

V

IN

= 42V

RNG

Si7850DP

4.7μH

0.1μF

V

5V

5A

OUT

V

= 24V

IN

FCB

SW

EXTV

INTV

CC

RUN/SS

M2

Si7850DP

1000pF

I

BG

TH

10k

47pF

+

D1

MBR1100

C

OUT

270μF

200k

5pF

1μF

V

FB

PGND

SGND

80

0

1

2

3

4

5

6

LOAD CURRENT (A)

1.89k

38125 TA01b

38125 TA01

38125fb

1

LTC3812-5

ABSOLUTE MAXIMUM RATINGS

(Note 1)

I

Voltage (400ms) .................................. –0.3V to 80V

ON

Supply Voltages

RUN/SS Voltage........................................... –0.3V to 5V

PGOOD Voltage............................................ –0.3V to 7V

INTV ................................................... –0.3V to 14V

CC

(INTV – PGND), (BOOST – SW) ......... –0.3V to 14V

CC

V

, FCB Voltages.................................... –0.3V to 14V

RNG

BOOST (Continuous) ............................. –0.3V to 85V

FB Voltage................................................. –0.3V to 2.7V

BOOST (≤400ms) .................................. –0.3V to 95V

TG, BG, INTV , EXTV RMS Currents.................50mA

CC

EXTV .................................................. –0.3V to 15V

CC

Operating Temperature Range (Note 2)

(EXTV – INTV ).................................. –12V to 12V

CC

LTC3812E-5 ......................................... –40°C to 85°C

LTC3812I-5 ........................................ –40°C to 125°C

Junction Temperature (Notes 3, 7)........................ 125°C

Storage Temperature Range................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

(NDRV – INTV ) Voltage........................... –0.3V to 10V

CC

SW Voltage (Continuous).............................. –1V to 70V

SW Voltage (400ms)..................................... –1V to 80V

I

ON

Voltage (Continuous) ........................... –0.3V to 70V

PIN CONFIGURATION

TOP VIEW

I

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

BOOST

TG

ON

V

RNG

PGOOD

FCB

SW

PGND

BG

17

I

TH

V

INTV

CC

FB

RUN/SS

SGND

EXTV

CC

NDRV

FE PACKAGE

16-LEAD PLASTIC TSSOP

T

= 125°C, θ = 38°C/W

JMAX

JA

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC3812EFE-5#PBF

LTC3812IFE-5#PBF

LEAD BASED FINISH

LTC3812EFE-5

TAPE AND REEL

PART MARKING*

3812EFE-5

PACKAGE DESCRIPTION

16-Lead Plastic TSSOP

PACKAGE DESCRIPTION

16-Lead Plastic TSSOP

TEMPERATURE RANGE

–40°C to 85°C

LTC3812EFE-5#TRPBF

LTC3812IFE-5#TRPBF

TAPE AND REEL

3812IFE-5

–40°C to 125°C

PART MARKING*

3812EFE-5

TEMPERATURE RANGE

–40°C to 85°C

LTC3812EFE-5#TR

LTC3812IFE-5#TR

LTC3812IFE-5

3812IFE-5

–40°C to 125°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

38125fb

2

LTC3812-5

ELECTRICAL CHARACTERISTICS ^Thel denotes speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C, INTV_CC= V_BOOST= V_RNG= V_EXTVCC= V_NDRV= 5V, V_FCB= V_SW= 0V,

unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

l

INTV

INTV Supply Voltage

4.35

14

V

CC

I

INTV Supply Current

RUN/SS > 1.5V (Notes 4, 5)

RUN/SS = 0V

3

224

6

600

mA

μA

Q

CC

INTV Shutdown Current

CC

I

BOOST Supply Current

Feedback Voltage

RUN/SS > 1.5V (Note 5)

RUN/SS = 0V

240

0

400

5

μA

BOOST

V

(Note 4)

0°C to 85°C

–40°C to 85°C

–40°C to 125°C (I-grade)

0.796

0.794

0.792

0.800

0.804

0.806

0.808

V

FB

l

ΔV

Feedback Voltage Line Regulation

Maximum Current Sense Threshold

5V < INTV < 14V (Note 4)

0.002

0.02

%/V

FB,LINE

CC

V

RNG

V

RNG

V

RNG

= 2V, V = 0.76V

256

70

170

320

95

215

384

120

260

mV

SENSE(MAX)

FB

= 0V, V = 0.76V

FB

= INTV , V = 0.76V

CC FB

V

Minimum Current Sense Threshold

V

= 2V, V = 0.84V

–300

–85

mV

SENSE(MIN)

VFB

RNG

FB

= 0V, V = 0.84V

FB

= INTV , V = 0.84V

–200

CC FB

I

Feedback Current

V

FB

= 0.8V

20

100

25

150

nA

dB

A

VOL

(EA)

Error Ampliﬁer DC Open-Loop Gain

65

f

Error Amp Unity Gain Crossover

Frequency

(Note 6)

Rising

MHz

U

V

FCB

FCB Threshold

V

FCB

0.75

0.8

0

0.85

1

V

μA

V

I

FCB Current

FCB = 5V

FCB

V

Shutdown Threshold

RUN/SS Source Current

1.2

0.7

1.5

1.4

2

RUN/SS

I

RUN/SS = 0V

2.5

μA

RUN/SS

V

INTV Undervoltage Lockout

VCCUV

CC

l

Linear Regulator Mode

External Supply Mode

Trickle-Charge Mode

INTV Rising, I

= 100μA

NDRV

4.05

8.70

4.2

9.0

3.7

4.35

9.30

V

CC

INTV Rising, NDRV = INTV = EXTV

CC

INTV Rising, NDRV = INTV , EXTV = 0

CC

INTV Falling

CC

Oscillator

t

On-Time

I

= 100μA

= 300μA

1.55

515

1.85

605

2.15

695

μs

ns

ON

t

Minimum On-Time

Minimum Off-Time

I

ON

= 2500μA

100

350

ns

ON(MIN)

250

OFF(MIN)

Driver

I

BG Driver Peak Source Current

V

= 0V

0.7

1

A

Ω

A

BG,PEAK

BG

R

BG Driver Pull-Down R

1.5

BG,SINK

DS(ON)

I

TG Driver Peak Source Current

TG Driver Pull-Down R

V

TG

– V = 0V

TG,PEAK

SW

R

Ω

TG,SINK

DS(ON)

PGOOD Output

ΔV

PGOOD Upper Threshold

PGOOD Lower Threshold

V

Rising

Falling

7.5

–7.5

10

–10

12.5

–12.5

%

FBOV

FB

ΔV

PGOOD Hysterisis

V

Returning

1.5

0.3

3

%

FB,HYST

FB

V

PGOOD Low Voltage

I

= 5mA

0.6

V

PGOOD

38125fb

3

LTC3812-5

ELECTRICAL CHARACTERISTICS ^Thel denotes speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C, INTV_CC= V_BOOST= V_RNG= V_EXTVCC= V_NDRV= 5V, V_FCB= V_SW= 0V,

unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

0

MAX

UNITS

μA

I

PGOOD Leakage Current

PGOOD Delay

V = 5V

PGOOD

2

PGOOD

PG Delay

V

Falling

120

μs

FB

V

CC

Regulators

V

EXTV Switchover Voltage

CC

EXTVCC

l

EXTV Rising

4.5

0.1

4.7

V

CC

EXTV Hysterisis

0.25

0.4

5.8

CC

V

INTV Voltage from EXTV

6V < V

< 15V

5.2

5.5

75

V

mV

%

INTVCC,1

CC

EXTVCC

ΔV

V

- V

at Dropout

I

= 20mA, V = 5V

EXTVCC

150

EXTVCC,1

LOADREG,1

INTVCC,2

EXTVCC

INTVCC

CC

INTV Load Regulation from EXTV

= 0mA to 20mA, V = 10V

EXTVCC

0.01

5.5

CC

V

INTV Voltage from NDRV Regulator Linear Regulator in Operation

5.2

5.8

V

CC

ΔV

INTV Load Regulation from NDRV

I

= 0mA to 20mA, V = 0

EXTVCC

0.01

40

%

LOADREG,2

CC

I

Current into NDRV Pin

V

– V = 3V

INTVCC

20

60

μA

NDRV

NDRVTO

NDRV

I

Linear Regulator Timeout Enable

Threshold

210

270

350

V

Maximum Supply Voltage

Trickle Charger Shunt Regulator

Trickle Charger Shunt Regulator,

15

V

CCSR

I

Maximum Current into NDRV/INTV

10

mA

CCSR

CC

INTV ≤ 16.7V (Note 8)

CC

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: The LTC3812-5 is tested in a feedback loop that servos V to the

FB

reference voltage with the I pin forced to a voltage between 1V and 2V.

TH

Note 5: The dynamic input supply current is higher due to the power

MOSFET gate charging being delivered at the switching frequency

Note 2: The LTC3812E-5 is guaranteed to meet performance speciﬁcations

from 0°C to 85°C. Speciﬁcations over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls. The LTC3812I-5 is guaranteed to meet

performance speciﬁcations over the full –40°C to 125°C operating

temperature range.

(Q • f ).

G

OSC

Note 6: Guaranteed by design. Not subject to test.

Note 7: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the speciﬁed maximum operating junction

temperature may impair device reliability.

Note 3: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formula:

D

Note 8: I is the sum of current into NDRV and INTV

.

CC

LTC3812-5: T = T + (P • 38°C/W)

J

A

D

PARAMETER

Maximum V

LTC3810

100V

LTC3810-5

60V

LTC3812-5

60V

IN

MOSFET Gate Drive

6.35V to 14V

6.2V

4.5V to 14V

4.2V

4.5V to 14V

4.2V

+

INTV UV

CC

–

INTV UV

6V

4V

CC

38125fb

4

LTC3812-5

TYPICAL PERFORMANCE CHARACTERISTICS

Short-Circuit/Fault Timeout

Operation

Load Transient Response

Start-Up

V

IN

V

OUT

20V/DIV

5V/DIV

V

OUT

INTV

CC

INTV

V

,

SS/TRACK

2V/DIV

CC

50mV/DIV

V

OUT

2V/DIV

OUT

I

OUT

I

L

5A/DIV

I

5A/DIV

L

2A/DIV

38125 G02

38125 G03

38125 G01

2ms/DIV

FRONT PAGE CIRCUIT

5ms/DIV

FRONT PAGE CIRCUIT

= 25V

10μs/DIV

FRONT PAGE CIRCUIT

V

I

= 30V

V

IN

V

= 25V

IN

= 0.5A

R

= 0.1Ω

LOAD

0A TO 5A LOAD STEP

SHORT

FCB = 0V

Short-Circuit/Foldback Operation

Pulse Skip Mode Operation

Efﬁciency vs Input Voltage

100

95

FRONT PAGE CIRCUIT

f = 250kHz

V

OUT

5V/DIV

100mV/DIV

I

= 5A

LOAD

I

TH

FORCED

CONTINUOUS

0.5A/DIV

I

L

5A/DIV

I

L

I

= 0.5A

LOAD

90

2A/DIV

FORCED

CONTINUOUS

38125 G04

38125 G05

I

= 0.5A

LOAD

200μs/DIV

FRONT PAGE CIRCUIT

= 25V

20μs/DIV

FRONT PAGE CIRCUIT

PULSE SKIP

85

V

OUT

FCB = INTV

= 25V

IN

I

= 100mA

CC

80

0

10

20

30

40

50

60

INPUT VOLTAGE (V)

38125 G06

Frequency vs Load Current

Efﬁciency vs Load Current

Frequency vs Input Voltage

100

95

350

300

290

280

270

260

250

240

230

220

210

200

FRONT PAGE CIRCUIT

FCB = 0V

V

= 24V

= 42V

FORCED

CONTINUOUS

IN

LOAD = 5A

LOAD = 0A

250

200

150

100

50

PULSE SKIP

90

V

= 12V

OUT

FCB = INTV

f = 250kHz

CC

0

85

0

2

3

4

5

6

1

2

3

5

0

4

0

10

30

40

50

60

20

LOAD CURRENT (A)

INPUT VOLTAGE (V)

38125 G07

38125 G09

LT1108 • TPC12

38125fb

5

LTC3812-5

TYPICAL PERFORMANCE CHARACTERISTICS

Current Sense Threshold

vs I_THVoltage

I_THVoltage vs Load Current

On-Time vs I_ONCurrent

3.0

400

300

10000

1000

100

V

= INTV

V

= 1V

V

= 2V

ON

CC

RNG

FRONT PAGE CIRCUIT

2.5

2.0

1.5

1.0

0.5

0

1.4V

1V

0.7V

0.5V

200

100

0

–100

–200

–300

–400

10

0

1

2

3

4

5

6

7

0

1

I

1.5

2

2.5

3

0.5

10

100

1000

CURRENT (μA)

10000

LOAD CURRENT (A)

VOLTAGE (V)

I

ON

TH

38125 G12

38125 G10

38125 G11

Maximum Current Sense

Threshold vs V_RNGVoltage

On-Time vs Temperature

Current Limit Foldback

680

660

640

620

400

300

200

100

0

250

200

150

100

50

V

= INTV

CC

I

= 300μA

RNG

ON

600

580

560

0

1

1.5

0.5

2

50

TEMPERATURE (°C)

100 125

0.2

0.4

(V)

0.6

–50 –25

0

25

75

0

0.8

V

VOLTAGE (V)

V

RNG

FB

38125 G15

38125 G13

38125 G14

Maximum Current Sense

Threshold vs Temperature

Reference Voltage

vs Temperature

Driver Peak Source Current

vs Temperature

230

220

210

200

190

180

0.803

0.802

0.801

0.800

0.799

0.798

0.797

1.5

1.0

0.5

V

= V

= 5V

INTVCC

V

= INTV

CC

BOOST

RNG

–50 –25

0

25

50

75 100 125

50

TEMPERATURE (°C)

125

–50 –25

0

25

50

75 100 125

–50 –25

0

25

75 100

TEMPERATURE (°C)

38125 G16

38125 G18

38125 G17

38125fb

6

LTC3812-5

TYPICAL PERFORMANCE CHARACTERISTICS

Driver Pull-Down R_DS(ON)

vs Temperature

Driver Peak Source Current

vs Supply Voltage

Driver Pull-Down R_DS(ON)

vs Supply Voltage

1.75

1.50

1.25

1.00

1.1

3.0

2.5

2.0

1.5

1.0

0.5

0

V

= V

= 5V

INTVCC

BOOST

1.0

0.9

0.8

0.75

0.50

0.25

0.7

0.6

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

4

5

6

7

8

9

10 11 12 13 14

4

5

6

7

9

11 12 13 14

8

10

DRV /BOOST VOLTAGE (V)

CC

38125 G19

38125 G20

38125 G21

INTV_CCShutdown Current

vs Temperature

EXTV_CCSwitch Resistance

vs Temperature

INTV_CCCurrent vs Temperature

400

300

5

4

3

2

1

0

7

6

INTV = 5V

CC

INTV = 5V

CC

5

4

3

2

1

200

100

0

–25

0

50

75 100 125

–50

25

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

38125 G24

38125 G22

38125 G23

INTV_CCShutdown Current

vs INTV_CCVoltage

INTV_CCCurrent vs INTV_CCVoltage

3.5

3.0

350

300

2.5

2.0

1.5

1.0

0.5

250

200

150

100

50

0

8

12

14

0

2

4

6

10

8

12

14

0

2

4

6

10

INTV VOLTAGE (V)

CC

38125 G25

38125 G26

38125fb

7

LTC3812-5

TYPICAL PERFORMANCE CHARACTERISTICS

Shutdown Threshold

vs Temperature

RUN/SS Pull-Up Current

vs Temperature

2.2

3

2

RUN/SS = 0V

2.0

1.8

1.6

1.4

1.2

1.0

0.8

1

0

0.6

–25

0

50

75 100 125

–50

25

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

TEMPERATURE (°C)

38125 G28

38125 G27

PIN FUNCTIONS

I

(Pin 1): On-Time Current Input. Tie a resistor from V

I

(Pin 5): Error Ampliﬁer Compensation Point and Cur-

TH

ON

IN

to this pin to set the one-shot timer current and thereby

rent Control Threshold. The current comparator threshold

increases with control voltage. The voltage ranges from

0V to 2.6V with 1.2V corresponding to zero sense voltage

(zero current).

set the switching frequency.

V

(Pin 2): Sense Voltage Limit Set. The voltage at this

RNG

pin sets the nominal sense voltage at maximum output

current and can be set from 0.5V to 2V by a resistive

V (Pin6):FeedbackInput.ConnectV througharesistor

divider network to V

FB

divider from INTV . The nominal sense voltage defaults

to set the output voltage.

CC

OUT

to 95mV when this pin is tied to ground, and 215mV when

RUN/SS (Pin 7): RUN/Soft-Start Input. For soft-start, a

capacitor to ground at this pin sets the ramp rate of the

output voltage (approximately 0.6s/μF). Pulling this pin

below 1.5V will shut down the LTC3812-5, turn off both of

the external MOSFET switches and reduce the quiescent

supply current to 224μA.

tied to INTV .

CC

PGOOD (Pin 3): Power Good Output. Open-drain logic

output that is pulled to ground when the output voltage

is not between 10% of the regulation point. The output

voltage must be out of regulation for at least 120μs before

the power good output is pulled to ground.

SGND(Pin8):SignalGround.Allsmall-signalcomponents

should connect to this ground and eventually connect to

PGND at one point.

FCB(Pin4):PulseSkipModeEnablePin.Thispinprovides

pulse skip mode enable/disable control. Pulling this pin

below0.8Vdisablespulseskipmodeoperationandforces

continuous operation. Pulling this pin above 0.8V enables

pulseskipmodeoperation. Thispincanalsobeconnected

to a feedback resistor divider from a secondary winding

on the inductor to regulate a second output voltage.

NDRV (Pin 9): Drive Output for External Pass Device of

the Linear Regulator for INTV . Connect to the gate of

CC

an external NMOS pass device and a pull-up resistor to

the input voltage V .

IN

38125fb

8

LTC3812-5

PIN FUNCTIONS

EXTV (Pin 10): External Driver Supply Voltage. When

SW (Pin 14): Switch Node Connection to Inductor and

Bootstrap Capacitor. Voltage swing at this pin is from a

Schottky diode (external) voltage drop below ground

CC

this voltage exceeds 4.2V, an internal switch connects

this pin to INTV through an LDO and turns off the exter-

CC

nal MOSFET connected to NDRV, so that controller and

to V .

IN

gate drive are drawn from EXTV .

CC

TG (Pin 15): Top Gate Drive. The TG pin drives the gate of

the top N-channel synchronous switch MOSFET. The TG

driver draws power from the BOOST pin and returns to the

SW pin, providing true ﬂoating drive to the top MOSFET.

INTV (Pin 11): Main Supply and Driver Supply Pin. All

CC

internalcircuitsandbottomgateoutputdriverarepowered

from this pin. INTV should be bypassed to SGND and

CC

PGND with a low ESR (X5R or better) 1μF capacitor in

BOOST (Pin 16): Top Gate Driver Supply. The BOOST pin

supplies power to the ﬂoating TG driver. BOOST should

be bypassed to SW with a low ESR (X5R or better) 0.1μF

capacitor. An additional fast recovery Schottky diode from

close proximity to the LTC3812-5.

BG (Pin 12): Bottom Gate Drive. The BG pin drives the

gateofthebottomN-channelsynchronousswitchMOSFET.

This pin swings from PGND to INTV .

INTV to the BOOST pin will create a complete ﬂoating

CC

charge-pumped supply at BOOST.

PGND (Pin 13): Bottom Gate Return. This pin connects

to the source of the pull-down MOSFET in the BG driver

and is normally connected to ground.

Exposed Pad (Pin 17): Ground. The Exposed Pad must

be soldered to PCB ground.

38125fb

9

LTC3812-5

FUNCTIONAL DIAGRAM

INTV

CC

EXTV

N

INTV

CC

CC DRV

V

IN

5V

REG

0.8V

REF

INTV

CC

MODE LOGIC

5.5V

NDRV

9

+

–

M3

9V

OFF

INTV

11

CC

4.2V

+

–

+

0.8V

INTV

UV

CC

F

FCB

4

EXTV

10

CC

–

+

–

270μA

5.5V

+

–

+

ON

1.4μA

+

–

V

IN

D

B

4.7V

BOOST

TIMEOUT

LOGIC

100nA

C

IN

16

I

ON

R

ON

C

TG

15

2.4V

B

DRV OFF

V

1

t

=

(76pF)

20k

IN

ON

FCNT

I

ION

M1

R

S

ON

Q

SW

14

+

–

SWITCH

LOGIC

L1

I

REV

CMP

V

OUT

–

INTV

CC

SHDN

OV

C

VCC

BG

12

M2

+

PGND

13

C

OUT

×

OVERTEMP

SENSE

1.4V

0.7V

V

RNG

2

PGOOD

3

5V

I

TH

R

FB1

FOLDBACK

FB

RUN

SHDN

I

TH

–

+

5

0.72V

+

–

UV

OV

R

C

C2

2.6V

1.5V

FAULT

C

V

FB

C1

6

EA

–

+

R

FB2

+

–

+

SGND

8

0.88V

0.8V

–

+

1.5V

RUN/SS

7

38125 FD

38125fb

10

LTC3812-5

OPERATION

Main Control Loop

Pulse Skip Mode

The LTC3812-5 is a current mode controller for DC/DC

step-down converters. In normal operation, the top

MOSFET is turned on for a ﬁxed interval determined by

a one-shot timer (OST). When the top MOSFET is turned

off, the bottom MOSFET is turned on until the current

TheLTC3812-5canoperateinoneoftwomodesselectable

with the FCB pin—pulse skip mode or forced continuous

mode (see Figure 1). Pulse skip mode is selected when

increasedefﬁciencyatlightloadsisdesired(seeFigure 2).

In this mode, the bottom MOSFET is turned off when

inductor current reverses to minimize efﬁciency loss due

to reverse current ﬂow and gate charge switching. At low

comparator I

trips, restarting the one-shot timer and

CMP

initiating the next cycle. Inductor current is determined by

sensing the voltage between the PGND and SW pins using

load currents, I will drop below the zero current level

TH

the bottom MOSFET on-resistance. The voltage on the I

(1.2V) shutting off both switches. Both switches will

TH

pin sets the comparator threshold corresponding to the

remain off with the output capacitor supplying the load

inductor valley current. The fast 25MHz error ampliﬁer EA

current until the I voltage rises above the zero current

TH

adjusts this voltage by comparing the feedback signal V

FB

100

to the internal 0.8V reference voltage. If the load current

PULSE

SKIP

90

increases, it causes a drop in the feedback voltage relative

80

70

tothereference.TheI voltagethenrisesuntiltheaverage

TH

inductor current again matches the load current.

FORCED

CONTINUOUS

60

Theoperatingfrequencyisdeterminedimplicitlybythetop

MOSFET on-time and the duty cycle required to maintain

regulation. Theone-shottimergeneratesanontimethatis

proportionaltotheidealdutycycle,thusholdingfrequency

50

40

30

20

V

= 12V

= 42V

10

IN

approximately constant with changes in V . The nominal

IN

0

0.01

frequency can be adjusted with an external resistor R .

ON

0.1

1

10

LOAD (A)

Pulling the RUN/SS pin low forces the controller into its

shutdown state, turning off both M1 and M2. Forcing a

voltage above 1.5V will turn on the device.

38125 F02

Figure 2. Efﬁciency in Pulse Skip/Forced Continuous Modes

PULSE SKIP MODE

FORCED CONTINUOUS

0A

DECREASING

LOAD

CURRENT

0A

38125 F01

Figure 1. Comparison of Inductor Current Waveforms for Pulse Skip Mode

and Forced Continuous Operation

38125fb

11

LTC3812-5

OPERATION

level to initiate another cycle. In this mode, frequency is

proportional to load current at light loads.

gates quickly. This minimizes transition losses and allows

paralleling MOSFETs for higher current applications. A

60V ﬂoating high side driver drives the topside MOSFET

and a low side driver drives the bottom side MOSFET

(see Figure 3). The bottom side driver is supplied directly

Pulse skip mode operation is disabled by comparator F

whentheFCBpinisbroughtbelow0.8V,forcingcontinuous

synchronous operation. Forced continuous mode is less

efﬁcient due to resistive losses, but has the advantage of

better transient response at low currents, approximately

constant frequency operation, and the ability to maintain

regulation when sinking current.

from the INTV pin. The top MOSFET drivers are biased

CC

from ﬂoating bootstrap capacitor C , which normally is

B

recharged during each off cycle through an external diode

from INTV when the top MOSFET turns off. In pulse

CC

skip mode operation, where it is possible that the bottom

MOSFET will be off for an extended period of time, an

internal timeout guarantees that the bottom MOSFET is

turned on at least once every 25μs for one on-time period

to refresh the bootstrap capacitor.

Fault Monitoring/Protection

Constant on-time current mode architecture provides ac-

curate cycle-by-cycle current limit protection—a feature

thatisveryimportantforprotectingthehighvoltagepower

supply from output short-circuits. The cycle-by-cycle cur-

rentmonitorguaranteesthattheinductorcurrentwillnever

V

INTV

IN

CC

+

exceed the value programmed on the V

pin.

D

B

RNG

LTC3812-5 INTV

C

IN

CC

BOOST

TG

Foldback current limiting provides further protection if the

C

B

M1

output is shorted to ground. As V drops, the buffered

FB

L

SW

currentthresholdvoltageI ispulleddownandclamped

THB

V

OUT

to 1V. This reduces the inductor valley current level to

+

BG

one-sixth of its maximum value as V approaches 0V.

M2

FB

C

OUT

Foldback current limiting is disabled at start-up.

PGND

38125 F03

Overvoltage and undervoltage comparators OV and UV

pull the PGOOD output low if the output feedback voltage

exits a 10% window around the regulation point after the

internal120μspowerbadmasktimerexpires.Furthermore,

in an overvoltage condition, M1 is turned off and M2 is

turned on immediately and held on until the overvoltage

condition clears.

Figure 3. Floating TG Driver Supply and Negative BG Return

IC/Driver Supply Power

The LTC3812-5’s internal control circuitry and top and

bottom MOSFET drivers operate from a supply voltage

(INTV pin) in the range of 4.2V to 14V. The LTC3812-5

CC

The LTC3812-5 provides an undervoltage lockout com-

has two integrated linear regulator controllers to easily

generate this IC/driver supply from either the high voltage

input or from the output voltage. For best efﬁciency the

supply is derived from the input voltage during start-up

and then derived from the lower voltage output as soon

as the output is higher than 4.7V. Alternatively, the supply

can be derived from the input continuously if the output is

<4.7V or an external supply in the appropriate range can

be used. The LTC3812-5 will automatically detect which

mode is being used and operate properly.

parator for the INTV supply. The INTV UV threshold

CC

is 4.2V to guarantee that the MOSFETs have sufﬁcient

gate drive voltage before turning on. If INTV is under

CC

the UV threshold, the LTC3812-5 is shut down and the

drivers are turned off.

Strong Gate Drivers

The LTC3812-5 contains very low impedance drivers ca-

pable of supplying amps of current to slew large MOSFET

38125fb

12

LTC3812-5

OPERATION

The four possible operating modes for generating this

supply are summarized as follows (see Figure 4):

driver shutdown/restart for V

< 4.7V is disabled.

OUT

This scheme is less efﬁcient but may be necessary if

< 4.7V and a boost network is not desired.

V

OUT

1. LTC3812-5generatesa5.5Vstart-upsupplyfromasmall

external SOT-23 NMOS acting as linear regulator with

3. Tricklechargemodeprovidesanevensimplerapproach

by eliminating the external NMOS. The IC/driver supply

capacitors are charged through a single high valued

drain connected to V and gate controlled by the

IN

LTC3812-5’sinternallinearregulatorcontrollerthrough

the NDRV pin. As soon as the output voltage reaches

4.7V, the 5.5V IC/driver supply is derived from the

output through an internal low dropout regulator to

optimize efﬁciency. If the output is lost due to a short,

the LTC3812-5 goes through repeated low duty cycle

soft-start cycles (with the drivers shut off in between)

to attempt to bring up the output without burning up

the SOT-23 NMOS. This scheme eliminates the long

start-up times associated with a conventional trickle

charger by using an external NMOS to quickly charge

resistorconnectedtotheinputsupply.WhentheINTV

CC

voltage reaches the turn-on threshold of 9V (automati-

cally raised from 4.2V to provide extra headroom for

start-up), the drivers turn on and begin charging up the

outputcapacitor.Whentheoutputreaches4.7V,IC/driver

powerisderivedfromtheoutput.Intrickle-chargemode,

the supply capacitors must have sufﬁcient capacitance

such that they are not discharged below the 4V INTV

CC

UV threshold before the output is high enough to take

over or else the power supply will not start.

the IC/driver supply capacitor (C

).

INTVCC

4. Lowvoltagesupplyavailable.Thesimplestapproachisif

alowvoltagesupply(between4.2Vand14V)isavailable

and connected directly to the IC/driver supply pins.

2. Similar to (1) except that the external NMOS is used

for continuous IC/driver power instead of just for start-

up. The NMOS is sized for proper dissipation and the

Mode 1: MOSFET for Start-Up Only

Mode 2: MOSFET for Continuous Use

V

IN

I > 270μA

NDRV

I < 270μA

NDRV

5.5V

INTV

CC

+

LTC3812-5

V

(> 4.7V)

EXTV

OUT

CC

V

IN

Mode 3: Trickle Charge Mode

Mode 4: External Supply

NDRV

INTV

5.5V

INTV

CC

+

4.2V TO

14V

+

–

LTC3812-5

38125 F04

EXTV

V

CC

OUT

Figure 4. Operating Modes for IC/Driver Supply

38125fb

13

LTC3812-5

APPLICATIONS INFORMATION

The basic LTC3812-5 application circuit is shown on the

ﬁrst page of this data sheet. External component selection

isprimarilydeterminedbythemaximuminputvoltageand

load current and begins with the selection of the power

MOSFET switches. The LTC3812-5 uses the on-resistance

of the synchronous power MOSFET for determining the

inductor current. The desired amount of ripple current

and operating frequency largely determines the inductor

POWER MOSFET SELECTION

The LTC3812-5 requires two external N-channel power

MOSFETs, one for the top (main) switch and one for the

bottom (synchronous) switch. Important parameters for

the power MOSFETs are the breakdown voltage BV

threshold voltage V_(GS)TH, on-resistance R_DS(ON), input

capacitance and maximum current I_DS(MAX)

,

DSS

.

Since the bottom MOSFET is used as the current sense

element, particular attention must be paid to its on-resis-

tance. MOSFET on-resistance is typically speciﬁed with

value. Next, C is selected for its ability to handle the

IN

large RMS current into the converter and C

is chosen

OUT

with low enough ESR to meet the output voltage ripple

and transient speciﬁcation. Finally, loop compensation

components are selected to meet the required transient/

phase margin speciﬁcations.

a maximum value R

at 25°C. In this case,

DS(ON)(MAX)

additional margin is required to accommodate the rise in

MOSFET on-resistance with temperature:

R_SENSE

R_DS(ON)(MAX)

=

MAXIMUM SENSE VOLTAGE AND V

RNG

ꢀ_T

Inductor current is determined by measuring the voltage

acrossasenseresistance(theon-resistanceofthebottom

MOSFET) that appears between the PGND and SW pins.

The maximum sense voltage is set by the voltage applied

The ρ term is a normalization factor (unity at 25°C)

accounting for the signiﬁcant variation in on-resistance

with temperature (see Figure 5) and typically varies

from 0.4%/°C to 1.0%/°C depending on the particular

MOSFET used.

T

to the V

pin and is equal to approximately:

RNG

V

= 0.173V

– 0.026

SENSE(MAX)

RNG

The current mode control loop will not allow the inductor

current valleys to exceed V /R . In prac-

tice, one should allow some margin for variations in the

LTC3812-5 and external component values and a good

guide for selecting the sense resistance is:

SENSE(MAX) SENSE

2.0

1.5

1.0

0.5

0

V_SENSE(MAX)

R_SENSE

=

1.3•I_OUT(MAX)

An external resistive divider from INTV can be used

CC

to set the voltage of the V

pin between 0.5V and 2V

RNG

resulting in nominal sense voltages of 60mV to 320mV.

Additionally, the V pin can be tied to SGND or INTV

50

100

–50

150

0

RNG

CC

JUNCTION TEMPERATURE (°C)

in which case the nominal sense voltage defaults to 95mV

or 215mV, respectively.

38125 F05

Figure 5. R_DS(ON)vs Temperature

38125fb

14

LTC3812-5

APPLICATIONS INFORMATION

Themostimportantparameterinhighvoltageapplications

voltage, but can be adjusted for different V voltages by

DS

is breakdown voltage BV . Both the top and bottom

multiplying by the ratio of the application V to the curve

DSS

DS

MOSFETs will see full input voltage plus any additional

ringing on the switch node across its drain-to-source dur-

ing its off-time and must be chosen with the appropriate

breakdown speciﬁcation. The LTC3812-5 is designed to

speciﬁed V values. A way to estimate the C

term

DS

MILLER

is to take the change in gate charge from points a and b

on a manufacturers data sheet and divide by the stated

V

voltage speciﬁed. C

is the most important se-

MILLER

DS

be used with a 4.5V to 14V gate drive supply (INTV pin)

lection criteria for determining the transition loss term in

the top MOSFET but is not directly speciﬁed on MOSFET

CC

≥ 4.5V).

for driving logic-level MOSFETs (V

GS(MIN)

data sheets. C

and C are speciﬁed sometimes but

RSS

OS

For maximum efﬁciency, on-resistance R

and input

DS(ON)

deﬁnitions of these parameters are not included.

capacitanceshouldbeminimized. LowR

minimizes

DS(ON)

conduction losses and low input capacitance minimizes

transition losses. MOSFET input capacitance is a combi-

nation of several components but can be taken from the

typical “gate charge” curve included on most data sheets

(Figure 6).

When the controller is operating in continuous mode the

duty cycles for the top and bottom MOSFETs are given by:

V_OUT

Main Switch Duty Cycle =

V

IN

V – V_OUT

IN

V

Synchronous Switch Duty Cycle=

IN

V

IN

MILLER EFFECT

V

GS

The power dissipation for the main and synchronous

MOSFETs at maximum output current are given by:

a

b

+

–

V

DS

+

Q

V

IN

GS

V_OUT

P_TOP

=

I

(

²(ꢀ_T)R_DS(ON)

+

MAX

–

C

= (Q – Q )/V

B A DS

MILLER

)

38125 F06

V

IN

₂I

^MAX(R_DR)(C_MILLER)•

2

Figure 6. Gate Charge Characteristic

V

IN

The curve is generated by forcing a constant input cur-

rent into the gate of a common source, current source

loaded stage and then plotting the gate voltage versus

time. The initial slope is the effect of the gate-to-source

and the gate-to-drain capacitance. The ﬂat portion of the

curve is the result of the Miller multiplication effect of the

drain-to-gate capacitance as the drain drops the voltage

across the current source load. The upper sloping line is

due to the drain-to-gate accumulation capacitance and

the gate-to-source capacitance. The Miller charge (the

increase in coulombs on the horizontal axis from a to b

ꢁ

ꢃ

ꢂ

ꢄ

ꢆ

ꢅ

1

+

(f)

V – V_TH(IL)V_{TH(IL) ꢆ}

ꢃ CC

V – V

IN

P_BOT

=

^OUT(I_MAX)²(ꢀ_T)R_DS(0N)

V

IN

where ρ is the temperature dependency of R

, R

T

DS(ON) DR

is the effective top driver resistance (approximately 2Ω at

= V ), V is the drain potential and the change

V

GS

MILLER

IN

in drain potential in the particular application. V

the data sheet speciﬁed typical gate threshold voltage

speciﬁed in the power MOSFET data sheet at the speciﬁed

is

TH(IL)

while the curve is ﬂat) is speciﬁed for a given V drain

DS

38125fb

15

LTC3812-5

APPLICATIONS INFORMATION

drain current. C

is the calculated capacitance using

OPERATING FREQUENCY

MILLER

the gate charge curve from the MOSFET data sheet and

the technique described above.

The choice of operating frequency is a tradeoff between

efﬁciency and component size. Low frequency operation

improvesefﬁciencybyreducingMOSFETswitchinglosses

but requires larger inductance and/or capacitance in order

to maintain low output ripple voltage.

2

Both MOSFETs have I R losses while the topside N-chan-

nel equation incudes an additional term for transition

losses, which peak at the highest input voltage. For high

input voltage low duty cycle applications that are typical

for the LTC3812-5, transition losses are the dominate

The operating frequency of LTC3812-5 applications is

determined implicitly by the one-shot timer that controls

loss term and therefore using higher R

device with

DS(ON)

the on-time t of the top MOSFET switch. The on-time

ON

lower C

usually provides the highest efﬁciency. The

MILLER

is set by the current out of the I pin and the voltage at

ON

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during a

short-circuit when the synchronous switch is on close to

100% of the period. Since there is no transition loss term

inthesynchronousMOSFET,optimalefﬁciencyisobtained

the V pin according to:

ON

2.4V

I_ION

t_ON

=

(76pF)

by minimizing R

—by using larger MOSFETs or

DS(ON)

T

ying a resistor R from V to the I pin yields an

paralleling multiple MOSFETS.

ON IN ON

on-time inversely proportional to V . For a step-down

IN

Multiple MOSFETs can be used in parallel to lower

converter,thisresultsinapproximatelyconstantfrequency

operation as the input supply varies:

R

and meet the current and thermal requirements

DS(ON)

if desired. The LTC3812-5 contains large low impedance

drivers capable of driving large gate capacitances without

signiﬁcantly slowing transition times. In fact, when driv-

ing MOSFETs with very low gate charge, it is sometimes

helpful to slow down the drivers by adding small gate

resistors (10Ω or less) to reduce noise and EMI caused

by the fast transitions.

V_OUT

2.4V • R_ON(76pF)

f =

[Hz]

Figure 7 shows how R relates to switching frequency

ON

for several common output voltages.

1000

V

= 12V

V

OUT

= 5V

OUT

V

= 3.3V

OUT

100

10

100

(kΩ)

1000

38112 F07

R

ON

Figure 7. Switching Frequency vs R_ON

38125fb

16

LTC3812-5

APPLICATIONS INFORMATION

MINIMUM OFF-TIME AND DROPOUT OPERATION

this requires a large inductor. There is a tradeoff between

component size, efﬁciency and operating frequency.

The minimum off-time t

is the smallest amount of

OFF(MIN)

time that the LTC3812-5 is capable of turning on the bot-

tom MOSFET, tripping the current comparator and turning

the MOSFET back off. This time is generally about 250ns.

The minimum off-time limit imposes a maximum duty

A reasonable starting point is to choose a ripple current

that is about 40% of I

. The largest ripple current

OUT(MAX)

occurs at the highest V . To guarantee that ripple current

IN

does not exceed a speciﬁed maximum, the inductance

should be chosen according to:

cycle of t /(t + t

). If the maximum duty cycle

OFF(MIN)

ON ON

is reached, due to a dropping input voltage for example,

then the output will drop out of regulation. The minimum

input voltage to avoid dropout is:

ꢁ

ꢃ

ꢂ

ꢄ

ꢆ

ꢅ

ꢁ

ꢄ

V_OUT

fꢀI_L(MAX)

V_OUT

L =

1ꢇ

ꢃ

ꢆ

V

ꢂ

ꢅ

IN(MAX)

t

_ON+ t_OFF(MIN)

Once the value for L is known, the type of inductor must

be selected. High efﬁciency converters generally cannot

affordthecorelossfoundinlowcostpowderedironcores,

forcing the use of more expensive ferrite, molypermalloy

or Kool Mμ^®cores. A variety of inductors designed for

high current, low voltage applications are available from

manufacturers such as Sumida, Panasonic, Coiltronics,

Coilcraft and Toko.

V_IN(MIN)= V_OUT

t_ON

A plot of maximum duty cycle vs frequency is shown in

Figure 8.

INDUCTOR SELECTION

Given the desired input and output voltages, the induc-

tor value and operating frequency determine the ripple

current:

SCHOTTKY DIODE D1 SELECTION

The Schottky diode D1 shown in the front page schematic

conducts during the dead time between the conduction of

the power MOSFET switches. It is intended to prevent the

body diode of the bottom MOSFET from turning on and

storing charge during the dead time, which can cause a

modest (about 1%) efﬁciency loss. The diode can be rated

for about one half to one ﬁfth of the full load current since

ꢁ

_OUTꢄ ꢁ

_OUTꢄ

V

ꢀI_L=

1ꢇ

ꢃ

ꢆ ꢃ

ꢆ

f L

V

ꢂ

ꢅ ꢂ

ꢅ

IN

Lower ripple current reduces core losses in the inductor,

ESR losses in the output capacitors and output voltage

ripple. Highest efﬁciency operation is obtained at low

frequency with small ripple current. However, achieving

2.0

1.5

1.0

0.5

0

DROPOUT

REGION

0

0.25

0.50

0.75

1.0

DUTY CYCLE (V /V

)

OUT IN

38125 F08

Figure 8. Maximum Switching Frequency vs Duty Cycle

38125fb

17

LTC3812-5

APPLICATIONS INFORMATION

it is on for only a fraction of the duty cycle. In order for the

diode to be effective, the inductance between it and the

bottom MOSFET must be as small as possible, mandating

thatthesecomponentsbeplacedadjacently.Thediodecan

be omitted if the efﬁciency loss is tolerable.

A good approach is to use a combination of aluminum

electrolyticsforbulkcapacitanceandceramicsforlowESR

and RMS current. If the RMS current cannot be handled

by the aluminum capacitors alone, when used together,

the percentage of RMS current that will be supplied by the

aluminum capacitor is reduced to approximately:

INPUT CAPACITOR SELECTION

1

%I_RMS,ALUMꢀ

•100%

2

In continuous mode, the drain current of the top MOSFET

is approximately a square wave of duty cycle V /V

which must be supplied by the input capacitor. To prevent

large input transients, a low ESR input capacitor sized for

the maximum RMS current is given by:

1+(8fCR_ESR

)

OUT IN

where R

ESR

is the ESR of the aluminum capacitor and C

is the overall capacitance of the ceramic capacitors. Using

an aluminum electrolytic with a ceramic also helps damp

the high Q of the ceramic, minimizing ringing.

_OUTꢁ

ꢄ^1/2

V

OUT

IN

I_CIN(RMS)ꢀI_O(MAX)

–1

ꢃ

ꢆ

V

ꢂ

ꢅ

IN

OUTPUT CAPACITOR SELECTION

This formula has a maximum at V = 2V , where I

O(MAX)

=

The selection of C

is primarily determined by the ESR

IN

OUT

RMS

OUT

I

/2. This simple worst-case condition is commonly

required to minimize voltage ripple. The output ripple

(ΔV ) is approximately equal to:

usedfordesignbecauseevensigniﬁcantdeviationsdonot

offer much relief. Note that the ripple current ratings from

capacitor manufacturers are often based on only 2000

hours of life. This makes it advisable to further derate

the capacitor or to choose a capacitor rated at a higher

temperature than required. Several capacitors may also

be placed in parallel to meet size or height requirements

in the design.

OUT

ꢂ

ꢅ

ꢇ

1

8fC

ꢀV_OUTꢁ ꢀI_LESR+

ꢄ

ꢃ

_OUTꢆ

Since ΔI increases with input voltage, the output ripple

L

is highest at maximum input voltage. ESR also has a

signiﬁcant effect on the load transient response. Fast load

transitions at the output will appear as voltage across the

BecausetantalumandOS-CONcapacitorsarenotavailable

in voltages above 30V, ceramics or aluminum electrolytics

mustbeusedforregulatorswithinputsuppliesabove30V.

Ceramic capacitors have the advantage of very low ESR

and can handle high RMS current, but ceramics with high

voltage ratings (> 50V) are not available with more than

a few microfarads of capacitance. Furthermore, ceram-

ics have high voltage coefﬁcients which means that the

capacitance values decrease even more when used at the

rated voltage. X5R and X7R type ceramics are recom-

mended for their lower voltage and temperature coef-

ﬁcients. Another consideration when using ceramics is

their high Q which, if not properly damped, may result in

excessive voltage stress on the power MOSFETs. Alumi-

num electrolytics have much higher bulk capacitance, but

they have higher ESR and lower RMS current ratings.

ESR of C

until the feedback loop in the LTC3812-5 can

OUT

change the inductor current to match the new load current

value. Typically, once the ESR requirement is satisﬁed the

capacitance is adequate for ﬁltering and has the required

RMS current rating.

Manufacturers such as Nichicon, Nippon Chemi-Con

and Sanyo should be considered for high performance

throughhole capacitors. The OS-CON (organic semicon-

ductor dielectric) capacitor available from Sanyo has the

lowestproductofESRandsizeofanyaluminumelectroly-

tic at a somewhat higher price. An additional ceramic

capacitor in parallel with OS-CON capacitors is recom-

mended to reduce the effect of their lead inductance.

In surface mount applications, multiple capacitors placed

in parallel may be required to meet the ESR, RMS current

38125fb

18

LTC3812-5

APPLICATIONS INFORMATION

handlingandloadsteprequirements.Drytantalum,special

polymerandaluminumelectrolyticcapacitorsareavailable

in surface mount packages. Special polymer capacitors

offer very low ESR but have lower capacitance density

than other types. Tantalum capacitors have the highest

capacitance density but it is important to only use types

that have been surge tested for use in switching power

supplies. Several excellent surge-tested choices are the

AVX TPS and TPSV or the KEMET T510 series. Aluminum

electrolytic capacitors have signiﬁcantly higher ESR, but

can be used in cost-driven applications providing that

consideration is given to ripple current ratings and long

term reliability. Other capacitor types include Panasonic

SP and Sanyo POSCAPs.

The reverse breakdown of the external diode, D , must

B

begreaterthanV

. Anotherimportantconsideration

IN(MAX)

for the external diode is the reverse recovery and reverse

leakage, either of which may cause excessive reverse

current to ﬂow at full reverse voltage. If the reverse cur-

rent times reverse voltage exceeds the maximum allow-

able power dissipation, the diode may be damaged. For

best results, use an ultrafast recovery diode such as the

MMDL770T1.

IC/MOSFET DRIVER SUPPLY (INTV )

CC

The LTC3812-5 drivers are supplied from the INTV and

CC

BOOST pins (see Figure 3), which have an absolute maxi-

mum voltage of 14V. Since the main supply voltage, V is

IN

typicallymuchhigherthan14VaseparatesupplyfortheIC

OUTPUT VOLTAGE

and driver power (INTV ) must be used. The LTC3812-5

CC

The LTC3812-5 output voltage is set by a resistor divider

according to the following formula:

has integrated bias supply control circuitry that allows the

IC/driver supply to be easily generated from V and/or

IN

V

OUT

with minimal external components. There are four

ꢀ

_FB1ꢃ

_FB2ꢄ

R

ways to do this as shown in the simpliﬁed schematics of

V

_OUT= 0.8V 1+

ꢂ

ꢅ

ꢁ

Figure 4 and explained in the following sections.

The external resistor divider is connected to the output as

shownintheFunctionalDiagram, allowingremotevoltage

sensing. The resultant feedback signal is compared with

the internal precision 800mV voltage reference by the

error ampliﬁer. The internal reference has a guaranteed

tolerance of less than 1%. Tolerance of the feedback

resistors will add additional error to the output voltage.

0.1% to 1% resistors are recommended.

Using the Linear Regulator for INTV Supply

CC

In Mode 1, a small external SOT-23 MOSFET, controlled by

the NDRV pin, is used to generate a 5.5V start-up supply

from V . The small SOT-23 package can be used because

IN

theNMOSisoncontinuouslyonlyduringthebriefstart-up

period. As soon as the output voltage reaches 4.7V, the

LTC3812-5turnsofftheexternalNMOSandtheLTC3812-5

regulatesthe5.5VsupplyfromtheEXTV pin(connected

CC

to V

or a V

derived boost network) through an

OUT

TOP MOSFET DRIVER SUPPLY (C , D )

B

internal low dropout regulator. For this mode to work

properly, EXTV must be in the range 4.7V < EXTV

<

CC

AnexternalbootstrapcapacitorC connectedtotheBOOST

B

15V. If V

< 4.7V, a charge pump or extra winding can

OUT

pinsuppliesthegatedrivevoltageforthetopsideMOSFET.

be used to raise EXTV to the proper voltage, or alter-

CC

This capacitor is charged through diode D from INTV

B

CC

natively, Mode 2 should be used as explained later in this

when the switch node is low. When the top MOSFET turns

section. If V

is shorted or otherwise goes below the

OUT

on, the switch node rises to V and the BOOST pin rises

IN

minimum 4.5V threshold, the MOSFET connected to V

IN

to approximately V + INTV . The boost capacitor needs

IN

CC

is turned back on to maintain the 5.5V supply. However if

to store about 100 times the gate charge required by the

top MOSFET. In most applications 0.1μF to 0.47μF, X5R

or X7R dielectric capacitor is adequate.

the output cannot be brought up within a timeout period,

38125fb

19

LTC3812-5

APPLICATIONS INFORMATION

the drivers are turned off to prevent the SOT-23 MOSFET

from overheating. Soft-start cycles are then attempted at

low duty cycle intervals to try to bring the output back

up (see Figure 9). This fault timeout operation is enabled

The external NMOS for the linear regulator should be a

standard3Vthresholdtype(i.e.,notalogiclevelthreshold).

The rate of charge of V from 0V to 5.5V is controlled

CC

by the LTC3812-5 to be approximately 75μs regardless of

by choosing the choosing R

NDRV

ing formulas:

such that the resistor

the size of the capacitor connected to the INTV pin. The

NDRV

CC

current I

is greater than 270μA by using the follow-

charging current for this capacitor is approximately:

ꢀ

ꢂ

ꢃ

ꢅ

5.5V

ꢁ 75μsꢄ

I_C=

C_INTVCC

P

/I

_{MOSFET(MAX) CC}ꢁ V_T

R_NDRVꢀ

270μA

The safe operating area (SOA) for the external NMOS

should be chosen so that capacitor charging does not

damage the NMOS. Excessive values of capacitor are

unnecessary and should be avoided. Typically values in

the 1μF to 10μF work well.

where

I

= (f)(Q

+ Q

) + 3mA

G(BOTTOM)

CC

G(TOP)

and V is the threshold voltage of the MOSFET.

T

The value of R

also affects the V

as follows:

Onemoredesignrequirementforthismodeistheminimum

soft-start capacitor value. The fault timeout is enabled

when RUN/SS voltage is greater than 4V. This gives the

power supply time to bring the output up before it starts

the timeout sequence. To prevent timeout sequence from

NDRV

IN(MIN)

NDRV

V

= V

+ (40μA) R

+ V

(1)

IN(MIN)

INTVCC(MIN)

T

where V

is normally 4.5V for driving logic level

INTVCC(MIN)

MOSFETs. If minimum V is not low enough, consider

IN

reducing R

and/or using a darlington NPN instead of

NDRV

startingprematurelyduringstart-up,aminimumC value

SS

EXTVCC

an NMOS to reduce V to ~1.4V.

T

is necessary to ensure that V

4.7V. To ensure this, choose:

< 4V until V

>

RUN/SS

When using R

LTC3812-5 will enable the low duty cycle soft-start re-

tries only when the desired maximum power dissipation,

equal to the computed value, the

NDRV

-6

C

SS

> C

• (2.3 • 10 )/I

OUT

OUT(MAX)

Mode 2 should be used if V

is outside of the 4.7V <

OUT

P

, in the MOSFET is exceeded and leave the

MOSFET(MAX)

EXTV < 15V operating range and the extra complexity

CC

drivers on continuously otherwise. The shutoff/restart

times are a function of the RUN/SS capacitor value.

of a charge pump or extra inductor winding is not wanted

FAULT TIMEOUT

ENABLED

DRIVER OFF THRESHOLD

DRIVER POWER

FROM V

OUT

I

= 1.4μA (SOURCE)

I

SS/TRACK

RUN/SS

DRIVER POWER

FROM V

= 0.1μA (SINK)

IN

SS/TRACK

START-UP

EXTV UV THRESHOLD

CC

V

OUT

SHORT-CIRCUIT EVENT

START-UP INTO SHORT CIRCUIT

TG/BG

38125 F09

Figure 9. Fault Timeout Operation

38125fb

20

LTC3812-5

APPLICATIONS INFORMATION

to boost this voltage above 4.7V. In this mode, EXTV is

In this mode, INTV , EXTV and NDRV must be shorted

CC CC

CC

grounded and the NMOS is chosen to handle the worst-

together.

case power dissipation:

INTV Supply and the EXTV Connection

CC

P

=(V

)[(f)(Q

+Q

+3mA]

G(BOTTOM)

MOSFET

IN(MAX)

G(TOP)

The LTC3812-5 contains an internal low dropout regula-

To operate properly, the fault timeout operation must be

disabled by choosing

tor to produce the 5.5V INTV supply from the EXTV

CC

pin voltage. This regulator turns on when the EXTV pin

CC

is above 4.7V and remains on until EXTV drops below

R

> (V

– 5.5V – V )/270μA

IN(MAX) T

CC

NDRV

4.45V. This allows the IC/MOSFET power to be derived

fromtheoutputoranoutputderivedboostnetworkduring

If the required R

value results in an unacceptable

NDRV

valueforV

(seeEquation1), faulttimeoutoperation

IN(MIN)

normal operation and from the external NMOS from V

IN

can also be disabled by connecting a 500k to 1M resistor

from RUN/SS to INTV .

during start-up or short-circuit. Using the EXTV pin in

CC

this way results in signiﬁcant efﬁciency gains compared

to what would be possible when deriving this power

Using Trickle Charge Mode

continuously from the typically much higher V voltage.

IN

Trickle charge mode is selected by shorting NDRV and

INTV andconnectingEXTV toV .Tricklechargemode

The EXTV connection also allows the power supply to

CC

be conﬁgured in trickle charge mode in which it starts up

CC

OUT

hastheadvantageofnotrequiringanexternalMOSFETbut

with a high-valued “bleed” resistor connected from V

IN

takes longer to start up due to slow charge up of C

to INTV to charge up the INTV capacitor. As soon as

INTVCC

) and

CC

through R

(t

= 0.77 • R

• C

the output rises above 4.7V the internal EXTV regulator

PULLUP DELAY

usually requires a larger INTV capacitor value to hold

PULLUP

INTVCC

CC

takes over before the INTV capacitor discharges below

CC

up the supply voltage during start-up. Once the INTV

the UV threshold. When the EXTV regulator is active,

CC

voltage reaches the trickle charge UV threshold of 9V, the

the EXTV pin can supply up to 50mA RMS. Do not ap-

CC

drivers will turn on and start discharging C

at a rate

ply more than 15V to the EXTV pin. The following list

INTVCC

CC

determined by the driver current I . In order to ensure

summarizes the possible connections for EXTV :

G

CC

proper start-up, C

must be chosen large enough so

INTVCC

1. EXTV grounded. This connection will require INTV

CC

that the EXTV voltage reaches the switchover threshold

CC

to be powered continuously from an external NMOS

of 4.7V before C

threshold of 4V. This is ensured if:

discharges below the falling UV

INTVCC

from V resulting in an efﬁciency penalty as high as

IN

10% at high input voltages.

5.5•10⁵•C_SS

V_OUT(REG)

ꢀ

ꢂ

ꢁ

ꢃ

ꢅ

ꢄ

C

I_MAX

2. EXTV connected directly to V . This is the normal

C_INTVCC>I • Larger of ^OUTor

CC

OUT

G

connection for 4.7V < V

< 15V and provides the

OUT

highest efﬁciency. The power supply will start up using

an external NMOS or a bleed resistor until the output

supply is available.

whereI isthegatedrivecurrent=(f)(Q

+Q

)

G

G(TOP)

G(BOTTOM)

and I

is the maximum inductor current selected by

MAX

V

.

RNG

3. EXTV connectedtoanoutput-derivedboostnetwork.

CC

For R

, the value should fall in the following range

If V

< 4.7V. The low voltage output can be boosted

PULLUP

to ensure proper start-up:

OUT

using a charge pump or ﬂyback winding to greater than

4.7V.

Min R > (V

– 14V)/I

PULLUP

IN(MAX)

CCSR

4. EXTV connected to INTV . This is the required

CC

Max R

< (V

– 9V)/I

IN(MIN) Q,SHUTDOWN

PULLUP

connection for EXTV if INTV is connected to an

CC

external supply where the external supply is 4.2V <

< 14V.

Using an External Supply Connected to the INTV

CC

V

EXT

If an external supply is available between 4.2V and 14V,

the supply can be connected directly to the INTV pins.

CC

38125fb

21

LTC3812-5

APPLICATIONS INFORMATION

Applications using large MOSFETs with a high input

the C

R

frequency which adds back the 90° phase

OUT ESR

voltage and high frequency of operation may result in a

and cancels the ﬁrst order roll off.

large EXTV pin current. Due to the LTC3812-5 thermally

CC

So far, the AC response of the loop is pretty well out of the

user’s control. The modulator is a fundamental piece of

the LTC3812-5 design and the external output capacitor is

usually chosen based on the regulation and load current

requirements without considering the AC loop response.

The feedback ampliﬁer, on the other hand, gives us a

handle with which to adjust the AC response. The goal is

to have 180° phase shift at DC (so the loop regulates), and

something less than 360° phase shift (preferably about

300°) at the point that the loop gain falls to 0dB, i.e., the

crossover frequency, with as much gain as possible at

frequencies below the crossover frequency. Since the

modulator/output ﬁlter is a ﬁrst order system with maxi-

enhanced package, maximum junction temperature will

rarely be exceeded, however, it is good design practice

to verify that the maximum junction temperature rating

and RMS current rating are within the maximum limits.

Typically, most of the EXTV current consists of the

CC

MOSFET gates current. In continuous mode operation,

this EXTV current is:

CC

I

= f(Q

+ Q ) + 3mA < 50mA

G(BOTTOM)

EXTVCC

G(TOP)

The junction temperature can be estimated from the

equations given in Note 2 of the Electrical Characteristics

as follows:

T =T +I

•(V

–V

)(38°C/W)<125°C

J

A

EXTVCC

INTVCC

mum of 90° phase shift (at frequencies below f /4) and

SW

the feedback ampliﬁer adds another 90° of phase shift,

some phase boost is required at the crossover frequency

to achieve good phase margin. If the ESR zero is below the

crossover frequency, this zero may provide enough phase

boost to achieve the desired phase margin and the only

requirement of the compensation will be to guarantee that

If absolute maximum ratings are exceeded, consider

using an external supply connected directly to the

INTV pin.

CC

FEEDBACK LOOP/COMPENSATION

Feedback Loop Types

the gain is below zero at frequencies above f /4. If the

SW

ESR zero is above the crossover frequency, the feedback

ampliﬁerwillprobablyberequiredtoprovidephaseboost.

For most LTC3810 applications, Type 2 compensation will

provide enough phase boost; however some applications

where high bandwidth is required with low ESR ceramics

and lots of bulk capacitance, Type 3 compensation may

be necessary to provide additional phase boost.

In a typical LTC3812-5 circuit, the feedback loop con-

sists of the modulator, the output ﬁlter and load, and the

feedback ampliﬁer with its compensation network. All of

these components affect loop behavior and must be ac-

counted for in the loop compensation. The modulator and

output ﬁlter consists of the internal current comparator,

the output MOSFET drivers and the external MOSFETs,

inductor and output capacitor. Current mode control

eliminates the effect of the inductor by moving it to the

inner loop, reducing it to a ﬁrst order system. From a

feedback loop point of view, it looks like a linear voltage

The two types of compensation networks, “Type 2” and

“Type 3” are shown in Figures 10 and 11. When compo-

nent values are chosen properly, these networks provide

C2

controlled current source from I to V

and has a gain

C1

TH

OUT

IN

R2

–6dB/OCT

GAIN

equal to (I

R

)/1.2V. It has fairly benign AC behavior

MAX OUT

R1

FB

–6dB/OCT

at typical loop compensation frequencies with signiﬁcant

phase shift appearing at half the switching frequency. The

external output capacitor and load cause a ﬁrst order roll

–

R

OUT

0

FREQ

–90

B

V

+

REF

–180

–270

–360

off at the output at the R

C

pole frequency, with

PHASE

OUT OUT

the attendant 90° phase shift. This roll off is what ﬁlters

the PWM waveform, resulting in the desired DC output

voltage. The output capacitor also contributes a zero at

38125 F10

Figure 10. Type 2 Schematic and Transfer Function

38125fb

22

LTC3812-5

APPLICATIONS INFORMATION

appropriately sized ground returns, etc. Wire the feedback

IN

C2

ampliﬁer with a 0.1μF feedback capacitor from I to FB

TH

C1

C3

R3

R2

and a 10k to 100k resistor from V

to FB. Choose the

OUT

R1

–6dB/OCT

GAIN

bias resistor (R ) as required to set the desired output

FB

B

–

+6dB/OCT

–6dB/OCT

voltage. Disconnect R from ground and connect it to

B

R

OUT

0

FREQ

–90

B

a signal generator or to the source output of a network

V

+

REF

–180

–270

–360

PHASE

analyzer to inject a test signal into the loop. Measure the

gain and phase from the I pin to the output node at the

TH

positive terminal of the output capacitor. Make sure the

38125 F11

analyzer’s input is AC coupled so that the DC voltages

Figure 11. Type 3 Schematic and Transfer Function

present at both the I and V

nodes don’t corrupt the

TH

OUT

measurements or damage the analyzer.

a “phase bump” at the crossover frequency. Type 2 uses

a single pole-zero pair to provide up to about 60° of phase

boostwhileType3usestwopolesandtwozerostoprovide

up to 150° of phase boost.

If breadboard measurement is not practical, a SPICE

simulationcanbeusedtogenerateapproximategain/phase

curves.Plugtheexpectedcapacitor,inductorandMOSFET

values into the following SPICE deck and generate an AC

plot of V /V with gain in dB and phase in degrees.

Feedback Component Selection

OUT ITH

Refer to your SPICE manual for details of how to gener-

Selecting the R and C values for a typical Type 2 or

Type 3 loop is a nontrivial task. The applications shown

in this data sheet show typical values, optimized for the

power components shown. They should give acceptable

performance with similar power components, but can be

way off if even one major power component is changed

signiﬁcantly. Applications that require optimized transient

response will require recalculation of the compensation

values speciﬁcally for the circuit in question. The underly-

ing mathematics are complex, but the component values

can be calculated in a straightforward manner if we know

the gain and phase of the modulator at the crossover

frequency.

ate this plot.

*3810 modulator gain/phase

*2006 Linear Technology

*this ﬁle simulates a simpliﬁed model of

*the LTC3810 for generating a v(out)/v(ith)

*bode plot

.param rdson=.0135 ;MOSFET rdson

.param Vrng=2

;use 1.4 for INTVCC and

0.7 for ground

.param vsnsmax={0.173*Vrng-0.026}

.param Imax={vsnsmax/rdson}

.param DL=4

;inductor ripple current

Modulator gain and phase can be obtained in one of

three ways: measured directly from a breadboard, or if

the appropriate parasitic values are known, simulated or

generated from the modulator transfer function. Mea-

surement will give more accurate results, but simulation

or transfer function can often get close enough to give

a working system. To measure the modulator gain and

phase directly, wire up a breadboard with an LTC3812-5

and the actual MOSFETs, inductor and input and output

capacitors that the ﬁnal design will use. This breadboard

should use appropriate construction techniques for high

speed analog circuitry: bypass capacitors located close

to the LTC3812-5, no long wires connecting components,

*inductor current

gl out 0 value={(v(ith)-1.2)*Imax/1.2+DL/2}

*output cap

cout out out2 270u ;capacitor value

resr out2 0 0.018 ;capacitor ESR

*load

Rout out 0 2 ; load resistor

vstim ith 0 0 ac 1 ;ac stimulus

.ac dec 100 100 10meg

.probe

.end

38125fb

23

LTC3812-5

APPLICATIONS INFORMATION

MathematicalsoftwaresuchasMATHCADorMATLABcan

also be used to generate plots using the following transfer

function of the modulator:

(K is a constant used in the calculations)

f = chosen crossover frequency

(GAIN/20)

G = 10

(this converts GAIN in dB to G in

ꢀ

_SENSE(MAX)ꢃ

absolute gain)

V

ꢀ

_OUTꢃ

1+ s •R_ESR•C

1+ s •R_L•C_OUT

ꢄ

H(s) =

•

ꢅ

•R_L

(2)

ꢅ

ꢂ

1.2•R

TYPE 2 Loop:

ꢁ

ꢄ

DS(ON)

s= j2ꢆf

BOOST

ꢀ

ꢁ

ꢃ

ꢄ

K = tan

+ 45°

ꢂ

ꢅ

2

1

With the gain/phase plot in hand, a loop crossover fre-

quency can be chosen. Usually the curves look something

likeFigure12.Choosethecrossoverfrequencyabout25%

of the switching frequency for maximum bandwidth. Al-

C2=

2ꢆ • f •G•K •R1

C1=C2 K²ꢇ1

(

)

though it may be tempting to go beyond f /4, remember

SW

K

that signiﬁcant phase shift occurs at half the switching

frequency that isn’t modeled in the above H(s) equation

and PSPICE code. Note the gain (GAIN, in dB) and phase

(PHASE, in degrees) at this point. The desired feedback

ampliﬁer gain will be –GAIN to make the loop gain at 0dB

at this frequency. Now calculate the needed phase boost,

assuming 60° as a target phase margin:

R2=

R_B=

2ꢆ • f •C1

V_REF(R1)

_OUTꢇ V_REF

V

TYPE 3 Loop:

BOOST

4

1

ꢀ

ꢁ

ꢃ

ꢄ

K = tan²

+ 45°

BOOST = – (PHASE + 30°)

ꢂ

ꢅ

If the required BOOST is less than 60°, a Type 2 loop can

be used successfully, saving two external components.

BOOST values greater than 60° usually require Type 3

loops for satisfactory performance.

C2=

2ꢆ • f •G•R1

C1=C2 K ꢇ1

(

)

Finally, choose a convenient resistor value for R1 (10k

is usually a good value). Now calculate the remaining

values:

K

R2=

R3=

C3=

2ꢆ • f •C1

R1

K ꢇ1

1

2ꢆf K • R3

GAIN

V_REF(R1)

_OUTꢇ V_REF

R_B=

0

V

–90

–180

PHASE

SPICE or mathematical software can be used to generate

the gain/phase plots for the compensated power supply to

do a sanity check on the component values before trying

them out on the actual hardware. For software, use the

following transfer function:

FREQUENCY (Hz)

38125 F12

Figure 12. Transfer Function of Buck Modulator

T(s) = A(s)H(s)

38125fb

24

LTC3812-5

APPLICATIONS INFORMATION

where H(s) was given in equation 2 and A(s) depends on

compensation circuit used:

threshold forces continuous synchronous operation, al-

lowing current to reverse at light loads and maintaining

high frequency operation. To prevent forcing current back

into the main power supply, potentially boosting the input

supply to a dangerous voltage level, forced continuous

mode of operation is disabled when the RUN/SS voltage

is below 2.5V during soft-start or tracking. During these

two periods, the PGOOD signal is forced low.

Type 2:

1+ s •R3•C2

A (s)=

C2 •C3

C2+C3

ꢀ

ꢃ

ꢄ

s •R_FB1• C2+C3 • 1+ s •R3•

(

)

ꢂ

ꢁ

ꢅ

Type 3:

A (s)=

In addition to providing a logic input to force continuous

operation,theFCBpinprovidesameantomaintainaﬂyback

winding output when the primary is operating in pulse

1

•

s •R1• C2+C3

(

)

skip mode. The secondary output V

is normally set as

OUT2

1+ s • R1+R3 •C3 • 1+ s •R2•C1

shown in Figure 13 by the turns ratio N of the transformer.

However, if the controller goes into pulse skip mode and

halts switching due to a light primary load current, then

(

)

(

C1• C2

C1+C2

ꢀ

ꢃ

1+ s •R3•C3 • 1+ s •R2•

(

)

ꢂ

ꢅ

ꢁ

ꢄ

V

will droop. An external resistor divider from V

OUT2

below

to the FCB pin sets a minimum voltage V

whichcontinuousoperationisforceduntilV

above its minimum.

OUT2(MIN)

For SPICE, replace VSTIM line in the previous PSPICE

code with following code and generate a gain/phase plot

of V(out)/V(outin):

hasrisen

OUT2

R4

R3

ꢀ

ꢁ

ꢃ

ꢄ

V_OUT2(MIN)= 0.8V 1+

rfb1 outin vfb 52.5k

ꢂ

ꢅ

rfb2 vfb 0 10k

eithx ithx 0 laplace {0.8-v(vfb)} =

{1/(1+s/1000)}

Table 1

FCB PIN

CONDITION

eith ith 0 value={limit(1e6*v(ithx),0,2.4)}

cc1 ith vfb 4p

DC Voltage: 0V to 0.75V

Forced Continuous

Current Reversal Enabled

cc2 ith x1 8p

DC Voltage: ≥0.85V

Feedback Resistors

Pulse Skip Mode Operation

No Current Reversal

rc x1 vfb 210k

Regulating a Secondary Winding

rf outin x2 11k ;delete this line for Type 2

cf x2 vfb 120p ;delete this line for Type 2

vstim out outin dc=0 ac=1m

V

IN

+

C

IN

V

IN

PULSE SKIP MODE OPERATION AND FCB PIN

1N4148

V

TG

OUT2

OUT1

•

+

LTC3812-5

The FCB pin determines whether the bottom MOSFET

remains on when current reverses in the inductor. Tying

this pin above its 0.8V threshold enables pulse skip mode

operation where the bottom MOSFET turns off when in-

ductor current reverses. The load current at which current

reverses and discontinuous operation begins depends on

the amplitude of the inductor ripple current and will vary

C

OUT2

1μF

V

SW

R4

•

T1

1:N

C

FCB

OUT

R3

BG

SGND

PGND

38125 F13

with changes in V . Tying the FCB pin below the 0.8V

Figure 13. Secondary Output Loop

IN

38125fb

25

LTC3812-5

APPLICATIONS INFORMATION

FAULT CONDITIONS: CURRENT LIMIT AND FOLDBACK

RUN/SOFT-START FUNCTION

The maximum inductor current is inherently limited in a

currentmodecontrollerbythemaximumsensevoltage.In

the LTC3812-5, the maximum sense voltage is controlled

The RUN/SSpin isa multipurposepin that providesa soft-

start function and a means to shut down the LTC3812-5.

Soft-start reduces the input supply’s surge current by

controlling the ramp rate of the output voltage, eliminates

output overshoot and can also be used for power supply

sequencing.

bythevoltageontheV

pin. Withvalleycurrentcontrol,

RNG

the maximum sense voltage and the sense resistance

determine the maximum allowed inductor valley current.

The corresponding output current limit is:

Pulling RUN/SS below 1.5V puts the LTC3812-5 into a low

V_SNS(MAX)

quiescent current shutdown (I = 224μA). This pin can be

1

Q

I_LIMIT

=

+ ꢁI_L

2

drivendirectlyfromlogicasshowninFigure14. Releasing

R_DS(ON)ꢀ_T

the RUN/SS pin allows an internal 1.4μA current source to

chargeupthesoft-startcapacitor,C .Whenthevoltageon

SS

The current limit value should be checked to ensure that

RUN/SS reaches 1.5V, the LTC3812-5 turns on and begins

I

>I

.Theminimumvalueofcurrentlimit

LIMIT(MIN) OUT(MAX)

generally occurs with the largest V at the highest ambi-

regulating the output to V = V – 1.5V. As the RUN/SS

FB

SS

IN

voltage increases from 1.5V to 2.3V, the output voltage is

raised from 0% to 100% of its regulated value. Current

foldback, forced continuous mode and fault timeout are

disabled during this soft-start phase and PGOOD signal is

forced low. The RUN/SS voltage continues to charge until

it reaches its internally clamped value of 4V.

ent temperature, conditions that cause the largest power

loss in the converter. Note that it is important to check for

self-consistency between the assumed MOSFET junction

temperature and the resulting value of I

the MOSFET switches.

which heats

LIMIT

Caution should be used when setting the current limit

based upon the R of the MOSFETs. The maximum

If RUN/SS starts at 0V, the delay before starting is

approximately:

DS(ON)

current limit is determined by the minimum MOSFET

on-resistance. Data sheets typically specify nominal

1.5V

1.4µA

and maximum values for R

, but not a minimum.

t_DELAY,START

=

C_SS= 1.1s/µF C

SS

(

)

DS(ON)

A reasonable assumption is that the minimum R

DS(ON)

lies the same percentage below the typical value as the

maximumliesaboveit.ConsulttheMOSFETmanufacturer

for further guidelines.

plus an additional delay, before the output will reach its

regulated value of:

0.8V

1.4µA

To further limit current in the event of a short-circuit to

ground, the LTC3812-5 includes foldback current limiting.

If the output falls by more than 60%, then the maximum

sense voltage is progressively lowered to about one tenth

of its full value.

t

_DELAY,REGꢀ

C_SS= 0.6s/µF C

SS

(

)

The start delay can be reduced by using diode D1 in

Figure 14.

3.3V

OR 5V

Be aware also that when the fault timeout is enabled for

the external NMOS regulator, an over current limit may

cause the output to fall below the minimum 4.5V UV

threshold. This condition will cause a linear regulator

timeout/restartsequenceasdescribedintheLinearRegula-

tor Timeout section if this condition persists.

RUN/SS

D1

C

SS

C

SS

38125 F14

Figure 14. RUN/SS Pin Interfacing

38125fb

26

LTC3812-5

APPLICATIONS INFORMATION

EFFICIENCY CONSIDERATIONS

2

must have a very low ESR to minimize the AC I R loss

and sufﬁcient capacitance to prevent the RMS current

from causing additional upstream losses in fuses or

batteries.

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Although all dissipative

elements in the circuit produce losses, four main sources

account for most of the losses in LTC3812-5 circuits:

Other losses, including C

ESR loss, Schottky diode D1

OUT

conduction loss during dead time and inductor core loss

generally account for less than 2% additional loss. When

making adjustments to improve efﬁciency, the input cur-

rent is the best indicator of changes in efﬁciency. If you

make a change and the input current decreases, then the

efﬁciency has increased. If there is no change in input

current, then there is no change in efﬁciency.

2

1. DC I R losses. These arise from the resistances of the

MOSFETs, inductor and PC board traces and cause the

efﬁciencytodropathighoutputcurrents. Incontinuous

modetheaverageoutputcurrentﬂowsthroughL, butis

choppedbetweenthetopandbottomMOSFETs.Ifthetwo

CHECKING TRANSIENT RESPONSE

MOSFETs have approximately the same R

, then

DS(ON)

the resistance of one MOSFET can simply be summed

The regulator loop response can be checked by looking

at the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

with the resistances of L and the board traces to obtain

2

the DC I R loss. For example, if R

L

= 0.01Ω and

DS(ON)

R = 0.005Ω, the loss will range from 15mW to 1.5W

as the output current varies from 1A to 10A.

load step occurs, V

immediately shifts by an amount

OUT

equal to ΔI

(ESR), where ESR is the effective series

LOAD

resistance of C . ΔI

also begins to charge or dis-

2. Transition loss. This loss arises from the brief amount

of time the top MOSFET spends in the saturated region

during switch node transitions. It depends upon the

inputvoltage,loadcurrent,driverstrengthandMOSFET

capacitance,amongotherfactors.Thelossissigniﬁcant

at input voltages above 20V and can be estimated from

OUT

LOAD

chargeC generatingafeedbackerrorsignalusedbythe

OUT

regulator to return V

this recovery time, V

to its steady-state value. During

can be monitored for overshoot

OUT

or ringing that would indicate a stability problem.

thesecondtermoftheP

equationfoundinthePower

DESIGN EXAMPLE

MAIN

MOSFET Selection section. When transition losses are

signiﬁcant, efﬁciency can be improved by lowering the

frequency and/or using a top MOSFET(s) with lower

As a design example, take a supply with the following

speciﬁcations:V =12Vto60V, V

=5V 5%, I

IN

OUT

OUT(MAX)

= 6A, f = 250kHz. First, calculate the timing resistor:

C

at the expense of higher R

.

RSS

DS(ON)

5V

3. INTV current. This is the sum of the MOSFET

CC

R_ON

=

=110k

driver and control currents. Control current is typically

2.4V •250kHz •76pF

about 3mA and driver current can be calculated by:

and choose the inductor for about 40% ripple current at

I

=f(Q

+Q ),whereQ andQ

G(BOT) G(TOP) G(BOT)

GATE

G(TOP)

the maximum V :

are the gate charges of the top and bottom MOSFETs.

This loss is proportional to the supply voltage that

INTV is derived from, i.e., V for the external NMOS

IN

5V

ꢁ

ꢂ

ꢄ

ꢆ

L =

1ꢀ

= 7.6μH

CC

IN

ꢃ

ꢅ

250kHz •0.4•6A

60V

linear regulator, V

for the internal EXTV regula-

when an external supply is connected to

OUT

CC

tor, or V

EXT

With a 7.7μH inductor, ripple current will vary from 1.5A

to 2.4A (25% to 40%) over the input supply range.

INTV .

CC

4. C loss. The input capacitor has the difﬁcult job of ﬁl-

IN

Next, choose the bottom MOSFET switch. Since the

drain of the MOSFET will see the full supply voltage 60V

tering the large RMS input current to the regulator. It

38125fb

27

LTC3812-5

APPLICATIONS INFORMATION

(max) plus any ringing, choose an 60V MOSFET. The

Si7850DP has:

the EXTV pin. A small SOT23 MOSFET such as the

CC

ZXMN10A07F can be used for the pass device if fault

timeout is enabled. Choose R

to guarantee that fault

NDRV

BV

DS(ON)

δ = 0.007/°C,

= 60V

DSS

timeout is enabled when power dissipation of M3 exceeds

0.4W (max for 70°C ambient):

R

= 25mΩ (max)/31mΩ (nom),

C

V

JA

= (8.3nC – 2.8nC)/30V = 183pF,

I

= 250kHz • 2 • 18nC + 3mA = 12mA

MILLER

GS(MILLER)

θ = 22°C/W.

CC

= 3.8V,

0.4W / 0.012A – 3V

R_NDRVꢀ

=112k

270µA

This yields a nominal sense voltage of:

So, choose R

= 100k.

NDRV

V

= 6A • 1.3 • 0.025Ω = 195mV

SNS(NOM)

C

IN

is chosen for an RMS current rating of about 3A at

Toguaranteepropercurrentlimitatworst-caseconditions,

increase nominal V by at least 50% to 320mV (by tying

85°C. The output capacitors are chosen for a low ESR

of 0.018Ω to minimize output voltage changes due to

inductor ripple current and load steps. The ripple voltage

will be only:

SNS

V

to 2V). To check if the current limit is acceptable at

= 320mV, assume a junction temperature of about

55°C above a 70°C ambient (ρ

RNG

SNS

= 1.7):

125°C

ΔV

= ΔI

• ESR = 2.4A • 0.018Ω

L(MAX)

OUT(RIPPLE)

= 43mV

320mV

1.7 •0.031ꢁ 2

1

I_LIMITꢀ

+ •2.4A = 7.3A

However, a 0A to 6A load step will cause an output change

of up to:

and double-check the assumed T in the MOSFET:

J

ΔV

= ΔI

• ESR = 6A • 0.018Ω

LOAD

OUT(STEP)

= 108mV

60V ꢀ 5V

P_BOT

=

•7.3A²•1.7 •0.031ꢁ= 2.6W

60V

An optional 10μF ceramic output capacitor is included

to minimize the effect of ESL in the output ripple. The

complete circuit is shown in Figure 15.

T = 70°C + 2.6W • 22°C/W = 127°C

J

Verify that the Si7850DP is also a good choice for the top

MOSFET by checking its power dissipation at current limit

andmaximuminputvoltage,assumingajunctiontempera-

PC Board Layout Checklist

ture of 30°C above a 70°C ambient (ρ

= 1.5):

When laying out a PC board follow one of two suggested

approaches. The simple PC board layout requires a dedi-

cated ground plane layer. Also, for higher currents, it is

recommended to use a multilayer board to help with heat

sinking power components.

100°C

5V

60V

7.3A

P_MAIN

=

•7.3A²1.5•0.031ꢀ

(

)

1

ꢂ

ꢃ

ꢅ

ꢆ

+60V²•

•2ꢀ •183pF •

+

•250kHz

ꢄ

ꢇ

2

5V ꢁ 3.8V 3.8V

= 0.206W +1.32W =1.53W

• The ground plane layer should not have any traces and

it should be as close as possible to the layer with power

MOSFETs.

T = 70°C + 1.53W • 22°C/W = 104°C

J

The junction temperature will be signiﬁcantly less at

nominal current, but this analysis shows that careful at-

tention to heat sinking on the board will be necessary in

this circuit.

• Place C , C , MOSFETs, D1 and inductor all in one

IN OUT

compact area. It may help to have some components

on the bottom side of the board.

•

Use an immediate via to connect the components to

groundplaneincludingSGNDandPGNDofLTC3812-5.

Since V

> 4.7V, the INTV voltage can be generated

CC

OUT

from V

with the internal LDO by connecting V

to

OUT

Use several bigger vias for power components.

38125fb

28

LTC3812-5

APPLICATIONS INFORMATION

• Use compact plane for switch node (SW) to improve

cooling of the MOSFETs and to keep EMI down.

• Place M2 as close to the controller as possible, keeping

the PGND, BG and SW traces short.

• Use planes for V and V

to maintain good voltage

OUT

•

Connect the input capacitor(s) C close to the pow-

er MOSFETs. This capacitor carries the MOSFET AC

current.

IN

ﬁltering and to keep power losses low.

• Floodallunusedareasonalllayerswithcopper.Flooding

with copper will reduce the temperature rise of power

component. You can connect the copper areas to any

• Keep the high dV/dt SW, BOOST and TG nodes away

from sensitive small-signal nodes.

DC net (V , V , GND or to any other DC rail in your

IN OUT

• Connect the INTV decoupling capacitor C

closely

CC

VCC

system).

to the INTV and SGND pins.

CC

When laying out a printed circuit board, without a ground

plane, use the following checklist to ensure proper opera-

tion of the controller.

• Connect the top driver boost capacitor C closely to

B

the BOOST and SW pins.

• ConnectthebottomdriverdecouplingcapacitorC

INTVCC

• Segregate the signal and power grounds. All small

signal components should return to the SGND pin at

one point which is then tied to the PGND pin close to

the source of M2.

closely to the INTV and PGND pins.

CC

V

IN

12V TO 60V

C

68μF

100V

C

IN2

R

NDRV

100k

IN1

R

1μF

ON

M3

110k

100V

ZXMN10A07F

PGND

C

D

ON

B

150k

100pF

BAS19

16

1

BOOST

I

ON

C

B

100k

LTC3812-5

0.1μF

2

3

15

14

13

M1

L1

7.7μH

V

RNG

TG

Si7850DP

V

5V

6A

OUT

PGOOD

FCB

I

SW

4

5

6

PGND

TH

C

OUT1

C

DRVCC

C

V

270μF

6.3V

SS

1000pF

FB

0.1μF

12

11

M2

Si7850DP

BG

C

10μF

6.3V

7

8

OUT2

INTV

CC

RUN/SS

SGND

10

9

D1

EXTV

CC

B1100

NDRV

C

47pF

C

C2

VCC

1μF

SGND

PGND

C

5pF

C1

R

C

R

FB1

200k

FB2

1.89k

10k

38125 F15

Figure 15. 12V to 60V Input Voltage to 5V/6A

38125fb

29

LTC3812-5

TYPICAL APPLICATIONS

7V to 60V Input Voltage to 5V/5A with IC Power from 12V Supply

and All Ceramic Output Capacitors

V

IN

7V TO 60V

C

68μF

100V

C

IN2

12V

IN1

R

ON

1μF

110k

80V

C

D

B

BAS19

ON

PGND

100pF

16

1

BOOST

I

ON

C

B

LTC3812-5

0.1μF

2

3

15

14

13

M1

L1

4.7μH

V

RNG

TG

Si7850DP

V

5V

5A

OUT

PGOOD

FCB

I

SW

4

5

6

PGND

TH

C

DRVCC

C

V

FB

SS

1000pF

0.1μF

12

11

M2

Si7850DP

BG

C

OUT1

7

8

47μF

INTV

CC

RUN/SS

SGND

6.3V

10

9

D1

EXTV

CC

×3

B1100

NDRV

C5

22μF

C

VCC

C

C2

1μF

200pF

SGND

PGND

C

C1

R

100k

C

5pF

R

FB2

1.89k

R

FB1

10k

38125 TA02

15V to 60V Input Voltage to 3.3V/5A with Fault Timeout

and Pulse Skip Disabled

V

IN

15V TO 60V

C

68μF

100V

C

R

NDRV

250k

IN1

IN2

R

1μF

ON

M3

ZVN4210G

71.5k

100V

PGND

C

D

B

BAS19

ON

100pF

16

1

BOOST

I

ON

C

B

LTC3812-5

0.1μF

2

3

15

14

13

M1

L1

4.7μH

V

RNG

TG

Si7850DP

V

3.3V

5A

OUT

PGOOD

FCB

SW

4

5

6

I

TH

PGND

C

OUT1

C

DRVCC

C

V

270μF

6.3V

SS

1000pF

FB

0.1μF

12

11

M2

Si7850DP

BG

C

7

8

OUT2

10μF

6.3V

INTV

CC

RUN/SS

SGND

10

9

D1

EXTV

CC

B1100

NDRV

C

47pF

C

C2

VCC

1μF

SGND

PGND

C

5pF

C1

R

C

R

200k

FB2

3.2k

FB1

10k

38125 TA03

38125fb

30

LTC3812-5

PACKAGE DESCRIPTION

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation BA

4.90 – 5.10*

(.193 – .201)

2.74

(.108)

2.74

(.108)

16 1514 13 12 1110

9

6.60 ±0.10

2.74

(.108)

4.50 ±0.10

6.40

(.252)

BSC

SEE NOTE 4

2.74

(.108)

0.45 ±0.05

1.05 ±0.10

0.65 BSC

5

7

8

1

2

3

4

6

RECOMMENDED SOLDER PAD LAYOUT

1.10

(.0433)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.195 – 0.30

FE16 (BA) TSSOP 0204

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

38125fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

31

LTC3812-5

TYPICAL APPLICATION

15V to 60V Input Voltage to 12V/5A with Trickle Charger Start-Up

V

IN

15V TO 60V

C

IN2

IN1

R

NDRV

250k

R

68μF

1μF

ON

261k

100V

PGND

C

D

B

ON

100pF

BAS19

16

1

BOOST

I

ON

C

B

LTC3812-5

0.1μF

2

3

15

14

13

M1

L1

10μH

V

RNG

TG

Si7850DP

V

12V

5A

OUT

PGOOD

FCB

I

SW

4

5

6

PGND

TH

C

OUT1

C

0.1μF

DRVCC

C

V

270μF

16V

SS

1000pF

FB

12

11

M2

Si7850DP

BG

C

7

8

OUT2

INTV

CC

RUN/SS

SGND

10μF

10

9

16V

D1

EXTV

CC

B1100

NDRV

C5

22μF

C

C2

C

VCC

47pF

1μF

SGND

PGND

C

C1

R

200k

C

5pF

R

FB2

1k

R

FB1

14k

38125 TA04

RELATED PARTS

PART NUMBER

LT^®1074HV/LT1076HV

LTC1735

DESCRIPTION

COMMENTS

Monolithic 5A/2A Step-Down DC/DC Converters

Synchronous Step-Down DC/DC Controller

V Up to 60V, TO-220 and DD Packages

IN

3.5V ≤ V ≤ 36V, 0.8V ≤ V

≤ 6V, Current Mode, I

≤ 20A

OUT

IN

OUT

LTC1778

No R

™ Synchronous DC/DC Controller

SENSE

4V ≤ V ≤ 36V, Fast Transient Response, Current Mode, I ≤ 20A

OUT

IN

LT1956

Monolithic 1.5A, 500kHz Step-Down Regulator

50mA, 3V to 80V Linear Regulator

5.5V ≤ V ≤ 60V, 2.5mA Supply Current, 16-Pin SSOP

IN

LT3010

1.275V ≤ V

≤ 60V, No Protection Diode Required, 8-Lead MSOP

OUT

LT3430/LT3431

LT3433

Monolithic 3A, 200kHz/500kHz Step-Down Regulator 5.5V ≤ V ≤ 60V, 0.1Ω Saturation Switch, 16-Pin SSOP

IN

Monolithic Step-Up/Step-Down DC/DC Converter

100V Synchronous DC/DC Controller

60V Synchronous DC/DC Controller

4V ≤ V ≤ 60V, 500mA Switch, Automatic Step-Up/Step-Down,

IN

LTC3703

V Up to 100V, 9.3V to 15V Gate Drive Supply

IN

LT3800

4V ≤ V ≤ 60V, 200kHz, Low I

IN Q

LTC3810

100V Synchronous DC/DC Controller

V

Up to 100V, Current Mode, No R

Required

IN

SENSE

LTC3810-5

LTC3835

No R

Current Mode Controller

Up to 60V, I

≤ 20A, Large 1Ω Gate Drivers

OUT

SENSE

Low I Synchronous DC/DC Controller

V : 4V to 36V, V : 0.8V to 10V

IN OUT

Q

LT3844

60V Non-Synchronous DC/DC Controller

60V Synchronous DC/DC Controller

4V ≤ V ≤ 60V, 100kHz to 600kHz, Low I

IN

Q

LT3845

4V ≤ V ≤ 60V, 100kHz to 600kHz, Low I

IN

Q

No R

is a trademark of Linear Technology Corporation.

SENSE

38125fb

LT 0408 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3812EFE-5#PBF
厂家：	Linear
描述：	LTC3812-5 - 60V Current Mode Synchronous Switching Regulator Controller; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
文件：	总32页 (文件大小：420K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3812EFE-5#PBF [Linear]

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