LTC3814EFE-5-PBF_技术文档

LTC3814-5

60V Current Mode

Synchronous Step-Up Controller

FEATURES

DESCRIPTION

The LTC3814-5 is a synchronous step-up switching regu-

lator controller that can generate output voltages up to

60V. The LTC3814-5 uses a constant off-time peak current

control architecture to deliver very high duty cycles with

accurate cycle-by-cycle current limit without requiring a

sense resistor.

n

High Output Voltages: Up to 60V

n

Large 1Ω Gate Drivers

n

No Current Sense Resistor Required

n

Dual N-Channel MOSFET Synchronous Drive

n

0.5ꢀ 0.8V Voltage Reference

n

Fast Transient Response

n

Programmable Soft-Start

A precise internal reference provides 0.5ꢀ ꢁC accuracy.

A high bandwidth (25MHz) error ampliﬁer provides very

fast line and load transient response. Large 1Ω gate driv-

ers allow the LTC3814-5 to drive large power MOSFETs

for higher current applications. The operating frequency

is selected by an external resistor and is compensated for

n

Generates 5.5V ꢁriver Supply

n

Power Good Output Voltage Monitor

n

Adjustable Off-Time/Frequency: t

< 100ns

OFF(MIN)

n

Adjustable Cycle-by-Cycle Current Limit

Undervoltage Lockout On ꢁriver Supply

Output Overvoltage Protection

variations in V . A shutdown pin allows the LTC3814-5 to

IN

Thermally Enhanced 16-Pin TSSOP Package

be turned off reducing the supply current to <230μA.

PARAMETER

Maximum V

LTC3813

100V

LTC3814-5

60V

APPLICATIONS

OUT

MOSFET Gate ꢁrive

6.35V to 14V

6.2V

4.5V to 14V

4.2V

n

24V Fan Supplies

+

INTV UV

n

CC

48V Telecom and Base Station Power Supplies

Networking Equipment, Servers

–

n

INTV UV

6V

4V

CC

n

Automotive and Industrial Control Systems

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents,

including 5481178, 5847554, 6304066, 6476589, 6580258, 6677210, 6774611.

TYPICAL APPLICATION

Efﬁciency vs Load Current

High Efﬁciency High Voltage Step-Up Converter

100

263k

V

= 12V

V

IN

V

IN

4.5V TO 14V

OUT

I

NꢁRV

OFF

100k

+

95

90

85

80

22μF

BOOST

PGOOꢁ

LTC3814-5

V

4.7μH

PGOOꢁ

TG

RNG

M1

Si7848ꢁP

V

= 5V

IN

0.1μF

V

24V

4A

OUT

V

OFF

SW

EXTV

CC

RUN/SS

INTV

CC

1000pF

0.01μF

ꢁ1

I

TH

29.4k

1k

MBR1100

M2

Si7848ꢁP

+

BG

270μF

× 2

100k

V

PGNꢁ

FB

SGNꢁ

2

3

0

4

1

100pF

1μF

LOAꢁ (A)

38145 TA01b

38145 TA01

38145fb

1

LTC3814-5

ABSOLUTE MAXIMUM RATINGS

PACKAGE/ORDER INFORMATION

(Note 1)

Supply Voltages

TOP VIEW

INTV ................................................... –0.3V to 14V

CC

I

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

BOOST

TG

OFF

(INTV – PGNꢁ), (BOOST – SW) ......... –0.3V to 14V

CC

V

BOOST (Continuous) ............................. –0.3V to 85V

V

SW

RNG

BOOST (≤400ms) .................................. –0.3V to 95V

PGOOꢁ

PGNꢁ

BG

17

EXTV .................................................. –0.3V to 15V

CC

I

TH

(EXTV – INTV ).................................. –12V to 12V

CC

V

INTV

CC

FB

(NꢁRV – INTV ) Voltage........................... –0.3V to 10V

CC

RUN/SS

SGNꢁ

EXTV

CC

SW Voltage (Continuous).............................. –1V to 70V

NꢁRV

SW Voltage (400ms)..................................... –1V to 80V

FE PACKAGE

16-LEAꢁ PLASTIC TSSOP

I

Voltage (Continuous) .......................... –0.3V to 70V

Voltage (400ms) ................................. –0.3V to 80V

OFF

T

= 125°C, θ = 38°C/W

JMAX

JA

EXPOSEꢁ PAꢁ (PIN 17) IS GNꢁ, MUST BE SOLꢁEREꢁ TO PCB

RUN/SS Voltage........................................... –0.3V to 5V

PGOOꢁ Voltage............................................ –0.3V to 7V

V

, V Voltages................................... –0.3V to 14V

RNG OFF

FB Voltage................................................. –0.3V to 2.7V

TG, BG, INTV , EXTV RMS Currents.................50mA

Operating Temperature Range (Note 2)

CC

LTC3814E-5 ......................................... –40°C to 85°C

LTC3814I-5 ........................................ –40°C to 125°C

Junction Temperature (Notes 3, 7)........................ 125°C

Storage Temperature Range................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

ORDER INFORMATION

LEAD FREE FINISH

LTC3814EFE-5#PBF

LTC3814IFE-5#PBF

TAPE AND REEL

PART MARKING

3814EFE-5

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3814EFE-5#TRPBF

LTC3814IFE-5#TRPBF

16-Lead Plastic TSSOP

–40°C to 85°C

–40°C to 125°C

3814IFE-5

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

38145fb

2

LTC3814-5

ELECTRICAL CHARACTERISTICS ^Thel denotes speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C, INTV_CC= V_BOOST= V_RNG= V_EXTVCC= V_NDRV= V_OFF= 5V, unless

otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

l

INTV

INTV Supply Voltage

4.35

14

V

CC

I

INTV Supply Current

RUN/SS > 1.5V (Notes 4, 5)

RUN/SS = 0V

3

224

6

600

mA

μA

Q

CC

INTV Shutdown Current

CC

I

BOOST Supply Current

Feedback Voltage

RUN/SS > 1.5V (Note 5)

RUN/SS = 0V

240

0

400

5

μA

BOOST

V

(Note 4)

0°C to 85°C

–40°C to 85°C

–40°C to 125°C (I-grade)

0.796

0.794

0.792

0.800

0.804

0.806

0.808

V

FB

l

ΔV

Feedback Voltage Line Regulation

Maximum Current Sense Threshold

5V < INTV < 14V (Note 4)

0.002

0.02

ꢀ/V

FB,LINE

CC

V

RNG

V

RNG

V

RNG

= 2V, V = 0.76V

256

70

170

320

95

215

384

120

260

mV

SENSE(MAX)

FB

= 0V, V = 0.76V

FB

= INTV , V = 0.76V

CC FB

V

Minimum Current Sense Threshold

V

RNG

V

RNG

V

RNG

= 2V, V = 0.84V

–300

–85

–200

mV

SENSE(MIN)

FB

= 0V, V = 0.84V

FB

= INTV , V = 0.84V

CC FB

I

Feedback Current

V

= 0.8V

20

100

25

150

nA

dB

VFB

FB

A

(EA)

Error Ampliﬁer ꢁC Open-Loop Gain

65

VOL

f

Error Amp Unity Gain Crossover

Frequency

(Note 6)

MHz

U

V

Shutdown Threshold

0.6

0.7

0.9

1.4

1.2

2.5

V

RUN/SS

I

RUN/SS Source Current

RUN/SS = 0V

μA

RUN/SS

l

V

INTV Undervoltage Lockout

INTV Rising

4.05

4.2

0.5

4.35

V

VCCUV

CC

Hysteresis

Oscillator

t

Off-Time

I

= 100μA

= 300μA

1.55

515

1.85

605

2.15

695

μs

ns

OFF

t

Minimum Off-Time

Minimum On-Time

I

= 2000μA

100

ns

OFF(MIN)

ON(MIN)

OFF

350

Driver

I

BG ꢁriver Peak Source Current

V

= 0V

0.7

1

A

Ω

A

BG,PEAK

BG

R

BG ꢁriver Pulldown R

1.5

BG,SINK

TG,PEAK

ꢁS(ON)

I

TG ꢁriver Peak Source Current

TG ꢁriver Pulldown R

V

TG

– V = 0V

SW

Ω

R

TG,SINK

ꢁS(ON)

PGOOD Output

ΔV

PGOOꢁ Upper Threshold

PGOOꢁ Lower Threshold

V

Rising

Falling

7.5

–7.5

10

–10

12.5

–12.5

ꢀ

FBOV

FB

V

ΔV

PGOOꢁ Hysteresis

V

Returning

1.5

0.3

0

3

0.6

2

ꢀ

V

FB,HYST

FB

V

PGOOꢁ Low Voltage

PGOOꢁ Leakage Current

I

= 5mA

= 5V

PGOOꢁ

I

V

μA

PGOOꢁ

38145fb

3

LTC3814-5

ELECTRICAL CHARACTERISTICS ^Thel denotes speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C, INTV_CC= V_BOOST= V_RNG= V_EXTVCC= V_NDRV= V_OFF= 5V, unless

otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

Falling

MIN

TYP

MAX

UNITS

PG ꢁelay

PGOOꢁ ꢁelay

V

125

μs

FB

V

Regulators

CC

V

EXTV Switchover Voltage

CC

EXTVCC

l

EXTV Rising

4.5

0.1

4.7

V

CC

EXTV Hysteresis

0.25

0.4

5.8

CC

V

INTV Voltage from EXTV

6V < V < 15V

EXTVCC

5.2

5.5

75

V

mV

ꢀ

INTVCC,1

CC

ΔV

V

- V

at ꢁropout

I

= 20mA, V = 5V

EXTVCC

150

EXTVCC,1

LOAꢁREG,1

INTVCC,2

EXTVCC

INTVCC

CC

INTV Load Regulation from EXTV

= 0mA to 20mA, V = 10V

EXTVCC

0.01

5.5

0.01

40

CC

V

INTV Voltage from NꢁRV Regulator Linear Regulator in Operation

5.2

20

10

5.8

60

V

CC

ΔV

INTV Load Regulation from NꢁRV

I

CC

= 0mA to 20mA, V = 0

EXTVCC

ꢀ

LOAꢁREG,2

CC

I

Current into NꢁRV Pin

V

NꢁRV

– V = 3V

INTVCC

μA

V

NꢁRV

V

Maximum Supply Voltage

Trickle Charger Shunt Regulator

Trickle Charger Shunt Regulator,

15

CCSR

I

Maximum Current into NꢁRV/INTV

mA

CCSR

CC

INTV ≤ 16.7V (Note 8)

CC

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: The LTC3814-5 is tested in a feedback loop that servos V to the

FB

reference voltage with the I pin forced to a voltage between 1V and 2V.

TH

Note 5: The dynamic input supply current is higher due to the power

MOSFET gate charging being delivered at the switching frequency

Note 2: The LTC3814E-5 is guaranteed to meet performance speciﬁcations

from 0°C to 85°C. Speciﬁcations over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls. The LTC3814I-5 is guaranteed to meet

performance speciﬁcations over the full –40°C to 125°C operating

temperature range.

(Q • f ).

G

SW

Note 6: Guaranteed by design. Not subject to test.

Note 7: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the speciﬁed maximum operating junction

temperature may impair device reliability.

Note 3: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formula:

ꢁ

Note 8: I is the sum of current into NꢁRV and INTV

.

CC

LTC3814-5: T = T + (P • 38°C/W)

J

A

ꢁ

TYPICAL PERFORMANCE CHARACTERISTICS

Start-Up

Overcurrent Operation

Load Transient Response

V

OUT

10V/ꢁIV

200mV/ꢁIV

V

OUT

10V/ꢁIV

RUN/SS

4V/ꢁIV

I

L

I

5A/ꢁIV

OUT

2A/ꢁIV

I

L

5A/ꢁIV

38145 G03

38145 G01

38145 G02

200μs/ꢁIV

100μs/ꢁIV

FRONT PAGE CIRCUIT

1ms/ꢁIV

FRONT PAGE CIRCUIT

= 12V

V

= 1V

= 1Ω

RNG

SHORT

V

IN

I

= 12V

= 1A

V

R

V

= 12V

IN

0A TO 4A LOAꢁ STEP

LOAꢁ

38145fb

4

LTC3814-5

TYPICAL PERFORMANCE CHARACTERISTICS

Frequency vs Input Voltage

Frequency vs Load Current

Efﬁciency vs Load Current

100

95

90

300

280

260

240

220

200

300

280

260

240

220

200

V

= 50V

FRONT PAGE CIRCUIT

OUT

V

= 36V

= 24V

IN

V

= 12V

IN

I

= 0A

= 1A

LOAꢁ

V

= 12V

IN

V

= 5V

IN

85

80

1

2

3

5

0

4

5

7

9

11

13

15

0

1

2

3

4

LOAꢁ (A)

INPUT VOLTAGE (V)

LOAꢁ CURRENT (A)

38145 G04

38145 G05

38145 G06

Current Sense Threshold

vs I_THVoltage

I_THVoltage vs Load Current

Off-Time vs I_OFFCurrent

3

2

1

0

400

300

10000

1000

100

V

= INTV

FRONT PAGE CIRCUIT

OFF

CC

V

= 2V

RNG

V

= 12V

RNG

IN

= 1V

1.4V

1V

0.7V

0.5V

200

100

0

–100

–200

–300

–400

10

1

2

3

5

0

4

0

1

I

1.5

2

2.5

3

10

100

1000

10000

0.5

I

CURRENT (μA)

VOLTAGE (V)

LOAꢁ CURRENT (A)

OFF

TH

38145 G09

38145 G07

38145 G08

Maximum Current Sense

Threshold vs Temperature

Maximum Current Sense

Threshold vs V_RNGVoltage

Off-Time vs Temperature

240

230

220

210

200

190

680

660

640

620

400

300

200

100

0

I

= 300μA

V

= INTV

RNG CC

OFF

600

580

560

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

–50 –25

0

25

50

75

125

100

1

1.5

0.5

2

TEMPERATURE (°C)

V

VOLTAGE (V)

RNG

38145 G12

38145 G10

38145 G11

38145fb

5

LTC3814-5

TYPICAL PERFORMANCE CHARACTERISTICS

Reference Voltage

vs Temperature

Driver Peak Source Current

vs Temperature

Driver Pulldown R_DS(ON)

vs Temperature

0.803

0.802

0.801

0.800

0.799

0.798

0.797

1.75

1.50

1.25

1.00

1.5

1.0

0.5

V

= V

= 5V

V

= V

= 5V

INTVCC

BOOST

INTVCC

BOOST

0.75

0.50

0.25

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

50

75 100 125

–50 –25

0

25

75

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

38145 G15

38145 G16

38145 G14

Driver Peak Source Current

vs Supply Voltage

Driver Pulldown R_DS(ON)

vs Supply Voltage

EXTV_CCSwitch Resistance

vs Temperature

7

6

1.1

3.0

2.5

2.0

1.5

1.0

0.5

0

1.0

0.9

5

4

3

2

1

0.8

0.7

0.6

0

50

100 125

–50 –25

0

25

75

4

5

6

7

8

9

10 11 12 13 14

4

5

6

7

9

11 12 13 14

10

8

ꢁRV /BOOST VOLTAGE (V)

TEMPERATURE (°C)

ꢁRV /BOOST VOLTAGE (V)

CC

38145 G19

38145 G17

38145 G21

INTV_CCShutdown Current

vs Temperature

INTV_CCCurrent vs Temperature

5

4

3

2

1

0

400

300

INTV = 5V

CC

INTV = 5V

CC

200

100

0

–25

0

50

75 100 125

–50

25

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

38145 G21

38145 G20

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6

LTC3814-5

TYPICAL PERFORMANCE CHARACTERISTICS

INTV_CCShutdown Current

vs INTV_CCVoltage

INTV_CCCurrent vs INTV_CCVoltage

3.5

3.0

350

300

2.5

2.0

1.5

1.0

0.5

250

200

150

100

50

0

8

12

14

0

2

4

6

10

8

12

14

0

2

4

6

10

INTV VOLTAGE (V)

CC

38145 G22

38145 G23

RUN/SS Pull-Up Current

vs Temperature

Shutdown Threshold

vs Temperature

2.2

3

2

RUN/SS = 0V

2.0

1.8

1.6

1.4

1.2

1.0

0.8

1

0

0.6

–25

0

50

75 100 125

–50

25

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

TEMPERATURE (°C)

38145 G25

38145 G24

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7

LTC3814-5

PIN FUNCTIONS

I

(Pin 1): Off-Time Current Input. Tie a resistor from

OUT

NDRV (Pin 9): ꢁrive Output for External Pass ꢁevice of

OFF

V

to this pin to set the one-shot timer current and

the Linear Regulator for INTV . Connect to the gate of an

CC

thereby set the switching frequency.

external NMOS pass device and a pull-up resistor to the

input voltage V or the output voltage V

.

IN

OUT

V

(Pin 2): Off-Time Voltage Input. Voltage trip point

OFF

for the on-time comparator. Tying this pin to an external

EXTV (Pin 10): External ꢁriver Supply Voltage. When

CC

resistive divider from the input makes the off-time pro-

this voltage exceeds 4.7V, an internal switch connects

portional to V . The comparator defaults to 0.7V when

this pin to INTV through an LꢁO and turns off the exter-

IN

CC

the pin is grounded and defaults to 2.4V when the pin is

nal MOSFET connected to NꢁRV, so that controller and

connected to INTV .

gate drive are drawn from EXTV .

CC

V

(Pin 3): Sense Voltage Limit Set. The voltage at this

INTV (Pin 11): Main Supply and ꢁriver Supply Pin. All

RNG

CC

pin sets the nominal sense voltage at maximum output

internalcircuitsandbottomgateoutputdriverarepowered

current and can be set from 0.5V to 2V by a resistive

from this pin. INTV should be bypassed to SGNꢁ and

CC

divider from INTV . The nominal sense voltage defaults

PGNꢁ with a low ESR (X5R or better) 1μF capacitor in

CC

to 95mV when this pin is tied to ground, and 215mV when

close proximity to the LTC3814-5.

tied to INTV .

CC

BG (Pin 12): Bottom Gate ꢁrive. The BG pin drives the

PGOOD (Pin 4): Power Good Output. Open-drain logic

output that is pulled to ground when the output voltage

is not between 10ꢀ of the regulation point. The output

voltage must be out of regulation for at least 125μs before

the power good output is pulled to ground.

gate of the bottom N-channel main switch MOSFET. This

pin swings from PGNꢁ to INTV .

CC

PGND (Pin 13): Bottom Gate Return. This pin connects

to the source of the pull-down MOSFET in the BG driver

and is normally connected to ground.

I

(Pin 5): Error Ampliﬁer Compensation Point and Cur-

TH

SW (Pin 14): Switch Node Connection to Inductor and

Bootstrap Capacitor. Voltage swing at this pin is from a

Schottky diode (external) voltage drop below ground

rent Control Threshold. The current comparator threshold

increases with control voltage. The voltage ranges from

0V to 2.6V with 1.2V corresponding to zero sense voltage

(zero current).

to V

.

OUT

TG (Pin 15): Top Gate ꢁrive. The TG pin drives the gate of

the top N-channel synchronous switch MOSFET. The TG

driver draws power from the BOOST pin and returns to the

SW pin, providing true ﬂoating drive to the top MOSFET.

V (Pin6):FeedbackInput.ConnectV througharesistor

FB

divider network to V

to set the output voltage.

OUT

RUN/SS (Pin 7): RUN/Soft-Start Input. For soft-start, a

capacitor to ground at this pin sets the ramp rate of the

maximum current sense threshold. Pulling this pin below

0.9V will shut down the LTC3814-5, turn off both of the

external MOSFET switches and reduce the quiescent sup-

ply current to 224μA.

BOOST (Pin 16): Top Gate ꢁriver Supply. The BOOST pin

supplies power to the ﬂoating TG driver. BOOST should

be bypassed to SW with a low ESR (X5R or better) 0.1μF

capacitor. An additional fast recovery diode from INTV

CC

to the BOOST pin will create a complete ﬂoating charge-

SGND(Pin8):SignalGround.Allsmall-signalcomponents

should connect to this ground and eventually connect to

PGNꢁ at one point.

pumped supply at BOOST.

Exposed Pad (Pin 17): Ground. The Exposed Pad must

be soldered to PCB ground.

38145fb

8

LTC3814-5

FUNCTIONAL DIAGRAM

V

IN

5.5V

NꢁRV

9

+

–

M3

OFF

INTV

11

CC

INTV

CC

EXTV

10

CC

5V

REG

0.8V

REF

+

–

5.5V

4.7V

+

–

+

V

IN

ON

INTV

UV

CC

V

OFF

4.2V

+

–

2

ꢁ

B

V

IN

+

BOOST

16

C

IN

L

I

OFF

1

R

OFF

C

TG

15

V

I

B

VOFF

V

t

=

(76pF)

20k

OUT

OFF

IOFF

R

S

ON

Q

SW

14

+

–

SWITCH

LOGIC

SHꢁN

OV

OVERTEMP

SENSE

I

CMP

V

OUT

M1

INTV

CC

C

VCC

BG

12

M2

PGNꢁ

13

×

PGOOꢁ

4

1.4V

0.7V

+

C

OUT

V

RNG

3

R

FB1

FAULT

0.72V

+

–

1.4μA

RUN

I

TH

5

UV

OV

SHꢁN

–

+

V

–

FB

R

C

C2

2.6V

0.9V

4V

Σ

6

+

C

C1

+

–

FB2

SGNꢁ

8

EA

0.88V

–

+

0.8V

RUN/SS

7

38145 Fꢁ

38145fb

9

LTC3814-5

OPERATION

Main Control Loop

in an overvoltage condition, M1 is turned off and M2 is

turned on immediately and held on until the overvoltage

condition clears.

The LTC3814-5 is a current mode controller for ꢁC/ꢁC

step-up converters. In normal operation, the top MOSFET

is turned on for a ﬁxed interval determined by a one-shot

timer (OST). When the top MOSFET is turned off, the bot-

tom MOSFET is turned on until the current comparator

The LTC3814-5 provides an undervoltage lockout com-

parator for the INTV supply. The INTV UV threshold

CC

is 4.2V to guarantee that the MOSFETs have sufﬁcient

gate drive voltage before turning on. If INTV is under

I

trips, restarting the one-shot timer and initiating the

CC

CMP

the UV threshold, the LTC3814-5 is shut down and the

next cycle. Inductor current is determined by sensing the

voltage between the PGNꢁ and SW pins using the bottom

drivers are turned off.

MOSFET on-resistance. The voltage on the I pin sets

TH

Strong Gate Drivers

the comparator threshold corresponding to the inductor

peak current. The fast 25MHz error ampliﬁer EA adjusts

The LTC3814-5 contains very low impedance drivers ca-

pable of supplying amps of current to slew large MOSFET

gates quickly. This minimizes transition losses and allows

paralleling MOSFETs for higher current applications. A

60V ﬂoating high side driver drives the topside MOSFET

and a low side driver drives the bottom side MOSFET

(see Figure 1). The bottom side driver is supplied directly

this voltage by comparing the feedback signal V to the

FB

internal0.8Vreferencevoltage.Iftheloadcurrentincreases,

it causes a drop in the feedback voltage relative to the

reference. The I voltage then rises until the average

TH

inductor current again matches the load current.

The operating frequency is determined implicitly by the

from the INTV pin. The top MOSFET drivers are biased

CC

top MOSFET on-time (t ) and the duty cycle required to

OFF

from ﬂoating bootstrap capacitor C , which normally is

B

maintain regulation. The one-shot timer generates a top

recharged during each off cycle through an external diode

MOSFET on-time that is inversely proportional to the I

OFF

from INTV when the top MOSFET turns off. In an output

CC

current and proportional to the V voltage. Connecting

OFF

overvoltage condition, where it is possible that the bot-

tom MOSFET will be off for an extended period of time,

an internal timeout guarantees that the bottom MOSFET

is turned on at least once every 25μs for one top MOSFET

on-time period to refresh the bootstrap capacitor.

V

to I and V to V with a resistive divider keeps

OUT

OFF IN OFF

thefrequencyapproximatelyconstantwithchangesinV .

IN

The nominal frequency can be adjusted with an external

resistor R

.

OFF

Pulling the RUN/SS pin low forces the controller into its

shutdown state, turning off both M1 and M2. Forcing a

voltage above 0.9V will turn on the device.

V

IN

INTV

CC

+

C

IN

Fault Monitoring/Protection

ꢁ

B

LTC3814-5 INTV

CC

BOOST

TG

L

Constant off-time current mode architecture provides ac-

curate cycle-by-cycle current limit protection—a feature

that is very important for protecting the high voltage

power supply from output overcurrent conditions. The

cycle-by-cycle current monitor guarantees that the induc-

tor current will never exceed the value programmed on

C

B

SW

V

OUT

M1

+

BG

M2

C

OUT

PGNꢁ

38145 F01

the V

pin.

RNG

Overvoltage and undervoltage comparators OV and UV

pull the PGOOꢁ output low if the output feedback voltage

exits a 10ꢀ window around the regulation point after the

internal125μspowerbadmasktimerexpires.Furthermore,

Figure 1. Floating TG Driver Supply and Negative BG Return

38145fb

10

LTC3814-5

OPERATION

IC/Driver Supply Power

to generate a 5.5V supply from the input or output. An

internal low dropout regulator is good for voltages up to

15V, and the second, a linear regulator controller, controls

the gate of an external NMOS to generate the 5.5V supply.

Since the NMOS is external, the user has the ﬂexibility to

The LTC3814-5’s internal control circuitry and top and bot-

tomMOSFETdriversoperatefromasupplyvoltage(INTV

pin) in the range of 4.5V to 14V. If the input supply voltage

or another available supply is within this voltage range it

can be used to supply IC/driver power. If a supply in this

range is not available, two internal regulators are available

CC

choose a BV

as high as necessary.

ꢁSS

APPLICATIONS INFORMATION

input in order to dimension the power MOSFET properly

and to choose the maximum sense voltage. Based on the

fact that, ideally, the output power is equal to the input

power, the maximum average input current and average

inductor current is:

The basic LTC3814-5 application circuit is shown on the

ﬁrst page of this data sheet. External component selection

isprimarilydeterminedbythemaximuminputvoltageand

load current and begins with the selection of the power

MOSFET switches. The LTC3814-5 uses the on-resistance

of the synchronous power MOSFET for determining the

inductorcurrent. Thedesiredamountofripplecurrentand

operatingfrequencylargelydeterminestheinductorvalue.

I_O(MAX)

I_IN(MAX)=I_L,AVG(MAX)=

1−D_MAX

Next,C

isselectedforitsabilitytohandlethelargeRMS

OUT

The current mode control loop will not allow the induc-

current and is chosen with low enough ESR to meet the

output voltage ripple and transient speciﬁcation. Finally,

loop compensation components are selected to meet the

required transient/phase margin speciﬁcations.

tor peak to exceed V /R . In practice, one

SENSE(MAX) SENSE

should allow some margin for variations in the LTC3814-

5 and external component values, and a good guide for

selecting the maximum sense voltage when V sensing

ꢁS

is used is:

Duty Cycle Considerations

1.7 •R_DS(ON)•I_O(MAX)

V_SENSE(MAX)

=

For a boost converter, the duty cycle of the main switch

is:

1−D_MAX

V

is set by the voltage applied to the V

pin. Once

RNG

V

V_OUT

IN(MIN)

IN

SENSE

to be:

D=1−

;D_MAX=1−

is chosen, the required V

voltage is calculated

RNG

V_OUT

ThemaximumV capabilityoftheLTC3814-5isinversely

OUT

V

= 5.78 • (V

+ 0.026)

RNG

SENSE(MAX)

proportional to the minimum desired operating frequency

An external resistive divider from INTV can be used

to set the voltage of the V

resulting in nominal sense voltages of 60mV to 320mV.

Additionally, the V pin can be tied to SGNꢁ or INTV

in which case the nominal sense voltage defaults to 95mV

or 215mV, respectively.

CC

and minimum off-time:

pin between 0.5V and 2V

RNG

V

IN(MIN)

V_OUT(MAX)

=

≤60V

f _MIN• t_OFF(MIN)

RNG

CC

Maximum Sense Voltage and the V

RNG

The control circuit in the LTC3814-5 measures the input

current by using the R of the bottom MOSFET or

ꢁS(ON)

by using a sense resistor in the bottom MOSFET source,

so the output current needs to be reﬂected back to the

38145fb

11

LTC3814-5

OPERATION

Power MOSFET Selection

ing its off-time and must be chosen with the appropriate

breakdown speciﬁcation. The LTC3814-5 is designed to

The LTC3814-5 requires two external N-channel power

MOSFETs, one for the bottom (main) switch and one for

the top (synchronous) switch. Important parameters for

the power MOSFETs are the breakdown voltage BV

threshold voltage V_(GS)TH, on-resistance R_ꢁS(ON), Miller

capacitance and maximum current I_ꢁS(MAX)

be used with a 4.5V to 14V gate drive supply (INTV pin)

CC

≥ 4.5V).

for driving logic-level MOSFETs (V

GS(MIN)

,

For maximum efﬁciency, on-resistance R

and input

ꢁSS

ꢁS(ON)

capacitanceshouldbeminimized. LowR

minimizes

ꢁS(ON)

.

conduction losses and low input capacitance minimizes

transition losses. MOSFET input capacitance is a combi-

nation of several components but can be taken from the

typical “gate charge” curve included on most data sheets

(Figure 3).

Since the bottom MOSFET is used as the current sense

element, particular attention must be paid to its on-resis-

tance. MOSFET on-resistance is typically speciﬁed with

a maximum value R

at 25°C. In this case,

ꢁS(ON)(MAX)

additional margin is required to accommodate the rise in

MOSFET on-resistance with temperature:

V

OUT

MILLER EFFECT

V

GS

R_SENSE

R_DS(ON)(MAX)

=

a

b

ρ_T

+

–

V

ꢁS

+

Q

V

IN

GS

The ρ term is a normalization factor (unity at 25°C)

–

C

= (Q – Q )/V

B A ꢁS

T

MILLER

38145 F03

accounting for the signiﬁcant variation in on-resistance

with temperature (see Figure 2) and typically varies

Figure 3. Gate Charge Characteristic

from 0.4ꢀ/°C to 1.0ꢀ/°C depending on the particular

MOSFET used.

The curve is generated by forcing a constant input cur-

rent into the gate of a common source, current source

loaded stage and then plotting the gate voltage versus

time. The initial slope is the effect of the gate-to-source

and the gate-to-drain capacitance. The ﬂat portion of the

curve is the result of the Miller multiplication effect of the

drain-to-gate capacitance as the drain drops the voltage

across the current source load. The upper sloping line is

due to the drain-to-gate accumulation capacitance and

the gate-to-source capacitance. The Miller charge (the

increase in coulombs on the horizontal axis from a to b

2.0

1.5

1.0

0.5

while the curve is ﬂat) is speciﬁed for a given V drain

ꢁS

voltage, but can be adjusted for different V voltages by

ꢁS

0

50

100

–50

150

0

multiplying by the ratio of the application V to the curve

ꢁS

JUNCTION TEMPERATURE (°C)

speciﬁed V values. A way to estimate the C

term

ꢁS

MILLER

38145 F02

is to take the change in gate charge from points a and b

Figure 2. R_DS(ON)vs Temperature

on a manufacturers data sheet and divide by the stated

V

voltage speciﬁed. C

is the most important se-

MILLER

ꢁS

Themostimportantparameterinhighvoltageapplications

lection criteria for determining the transition loss term in

the top MOSFET but is not directly speciﬁed on MOSFET

is breakdown voltage BV . Both the top and bottom

ꢁSS

MOSFETs will see full output voltage plus any additional

data sheets. C

and C are speciﬁed sometimes but

RSS

OS

ringing on the switch node across its drain-to-source dur-

deﬁnitions of these parameters are not included.

38145fb

12

LTC3814-5

APPLICATIONS INFORMATION

When the controller is operating in continuous mode the

duty cycles for the top and bottom MOSFETs are given by:

Multiple MOSFETs can be used in parallel to lower

ꢁS(ON)

R

and meet the current and thermal requirements

if desired. The LTC3814-5 contains large low impedance

drivers capable of driving large gate capacitances without

signiﬁcantly slowing transition times. In fact, when driv-

ing MOSFETs with very low gate charge, it is sometimes

helpful to slow down the drivers by adding small gate

resistors (10Ω or less) to reduce noise and EMI caused

by the fast transitions.

V

_OUT− V

V_OUT

IN

Main Switch Duty Cycle =

Synchronous SwitchDuty Cycle=

V

IN

V_OUT

The power dissipation for the main and synchronous

MOSFETs at maximum output current are given by:

Operating Frequency

The choice of operating frequency is a tradeoff between

efﬁciency and component size. Low frequency operation

improvesefﬁciencybyreducingMOSFETswitchinglosses

but requires larger inductance and/or capacitance in order

to maintain low output ripple voltage.

I_O(MAX)

ꢁ

ꢄ²

ꢆ

P

_MAIN=D_MAX

(ꢇ_T)R_DS(ON)

ꢃ

1ꢀD

ꢂ

_MAXꢅ

I_O(MAX)

₂ꢁ

ꢄ

1

2

+ V_OUT

(R_DR)(C_MILLER)

ꢃ

ꢆ

1ꢀD

ꢂ

_MAXꢅ

The operating frequency of LTC3814-5 applications is

determined implicitly by the one-shot timer that controls

ꢈ

ꢋ

1

•

+

(f)

ꢊ

ꢍ

INTV_CC– V_TH(IL)V_{TH(IL) ꢍ}

the on-time t

of the synchronous MOSFET switch.

ꢊ

ꢉ

OFF

ꢌ

The on-time is set by the current into the I pin and the

OFF

ꢁ

ꢄ

1

voltage at the V pin according to:

P_SYNC

=

(I_O(MAX))²(ꢇ_T)R_DS(0N)

OFF

ꢃ

ꢆ

1ꢀD

ꢂ

_MAXꢅ

V_VOFF

I

IOFF

t_OFF

=

76pF

(

)

where ρ is the temperature dependency of R

, R

T

ꢁS(ON) ꢁR

is the effective top driver resistance (approximately 2Ω at

= V ). V is the data sheet speciﬁed typical

Tying a resistor R from V

to the I pin yields a syn-

OFF

OUT

V

GS

MILLER

TH(IL)

chronous MOSFET on-time inversely proportional to V

.

OUT

gatethresholdvoltagespeciﬁedinthepowerMOSFETdata

sheetatthespeciﬁeddraincurrent.C isthecalculated

This results in the following operating frequency and also

keeps frequency constant as V

MILLER

ramps up at start-up:

OUT

capacitanceusingthegatechargecurvefromtheMOSFET

data sheet and the technique described above.

V

IN

f =

(Hz)

2

V_VOFF•R_OFF(76pF)

BothMOSFETshaveI RlosseswhilethebottomN-channel

equation includes an additional term for transition losses.

The V

pin can be connected to INTV or ground or

2

OFF

CC

Both top and bottom MOSFET I R losses are greatest at

can be connected to a resistive divider from V . The V

2

IN

OFF

lowest V , and the top MOSFET I R losses also peak

IN

pin has internal clamps that limit its input to the one-shot

timer. If the pin is tied below 0.7V, the input to the one-

shot is clamped at 0.7V. Similarly, if the pin is tied above

2.4V, the input is clamped at 2.4V. Note, however, that

during an overcurrent condition when it is on close to

100ꢀ of the period. For most LTC3814-5 applications,

2

the transition loss and I R loss terms in the bottom

MOSFET are comparable, so best efﬁciency is obtained

if the V

pin is connected to a constant voltage, the

OFF

by choosing a MOSFET that optimizes both R

and

ꢁS(ON)

operating frequency will be proportional to the input

voltage V . Figures 4a and 4b illustrate how R relates

C

. Since there is no transition loss term in the syn-

MILLER

IN

OFF

chronousMOSFET,however,optimalefﬁciencyisobtained

by minimizing R —by using larger MOSFETs or

to switching frequency as a function of the input voltage

ꢁS(ON)

and V

voltage. To hold frequency constant for input

OFF

paralleling multiple MOSFETs.

38145fb

13

LTC3814-5

APPLICATIONS INFORMATION

voltage changes, tie the V pin to a resistive divider from

Changes in the load current magnitude will also cause

a frequency shift. Parasitic resistance in the MOSFET

switches and inductor reduce the effective voltage across

the inductance, resulting in increased duty cycle as the

load current increases. By shortening the off-time slightly

ascurrentincreases,constant-frequencyoperationcanbe

maintained.Thisisaccomplishedwitharesistorconnected

OFF

V , as shown in Figure 5. Choose the resistor values so

IN

that the V

of V as follows:

voltage equals about 1.55V at the mid-point

RNG

IN

V

_IN(MAX)+ V

R1

R2

^IN(MIN)=1.55V • 1+

ꢀ

ꢁ

ꢃ

V

=

ꢂ

ꢅ

IN,MID

ꢄ

2

from the I pin to the I pin to increase the I current

TH

OFF

With these resistor values, the frequency will remain

relatively constant at:

slightly as V increases. The values required will depend

ITH

on the parasitic resistances in the speciﬁc application. A

1+R1/ R2

R_OFF(76pF)

good starting point is to feed about 10ꢀ of the R cur-

f =

(Hz)

OFF

rent with R as shown in Figure 6.

ITH

for the range of 0.45V to 1.55 • V , and will be propor-

IN

tional to V outside of this range.

IN

1000

1+R1/R2 = 3.2

(V

,

= 5V)

IN MIꢁ

V

= 5V

V = 24V

IN

1+R1/R2 = 7.7

(V =12V)

,

IN MIꢁ

1+R1/R2 = 15.5

(V = 24V)

V

= 12V

IN

,

IN MIꢁ

100

10

100

(kΩ)

1000

10

100

(kΩ)

1000

38145 F04a

R

OFF

38145 F04b

Figure 4a. Switching Frequency vs R_OFF(V_OFF= INTV_CC

)

Figure 4b. Switching Frequency vs R_OFF

(V_OFFConnected to a Resistor Divider from V_IN)

V

IN

R1

R2

R

OFF

V

I

OUT

V

OFF

1000pF

R

ITH

LTC3814-5

I

TH

38145 F06

38145 F05

10R

OFF

R

=

ITH

V

OUT

Figure 5. V_OFFConnection to Keep the Operating

Frequency Constant as the Input Supply Varies

Figure 6. Correcting Frequency Shift with Load Current Changes

38145fb

14

LTC3814-5

APPLICATIONS INFORMATION

Minimum On-Time and Dropout Operation

The required saturation of the inductor should be chosen

to be greater than the peak inductor current:

The minimum on-time t

is the smallest amount of

ON(MIN)

I_O(MAX)

ΔI_L

2

timethattheLTC3814-5iscapableofturningonthebottom

MOSFET, tripping the current comparator and turning the

MOSFET back off. This time is generally about 350ns. The

minimum on-time limit imposes a minimum duty cycle

I_L(SAT)

≥

+

1−D_MAX

Once the value for L is known, the type of inductor must

be selected. High efﬁciency converters generally cannot

affordthecorelossfoundinlowcostpowderedironcores,

forcing the use of more expensive ferrite, molypermalloy

or Kool Mμ^®cores. A variety of inductors designed for

high current, low voltage applications are available from

manufacturers such as Sumida, Panasonic, Coiltronics,

Coilcraft and Toko.

of t

/(t

+ t ). If the minimum duty cycle is

ON(MIN) ON(MIN) OFF

reached, due to a rising input voltage for example, then

the output will rise out of regulation. The maximum input

voltage to avoid dropout is:

t_OFF

_ON(MIN)+ t_OFF

V_IN(MAX)= V_OUT

t

A plot of maximum duty cycle vs switching frequency is

shown in Figure 7.

Schottky Diode D1 Selection

The Schottky diode ꢁ1 shown in the front page schematic

conducts during the dead time between the conduction of

the power MOSFET switches. It is intended to prevent the

body diode of the synchronous MOSFET from turning on

and storing charge during the dead time, which can cause

a modest (about 1ꢀ) efﬁciency loss. The diode can be

rated for about one half to one ﬁfth of the full load current

since it is on for only a fraction of the duty cycle. The peak

reverse voltage that the diode must withstand is equal to

the regulator output voltage. In order for the diode to be

effective, the inductance between it and the synchronous

MOSFET must be as small as possible, mandating that

these components be placed adjacently. The diode can

be omitted if the efﬁciency loss is tolerable.

2.0

1.5

ꢁROPOUT

REGION

1.0

0.5

0

0.25

0.50

0.75

1.0

V

/V

IN OUT

38145 F07

Figure 7. Maximum Switching Frequency vs Duty Cycle

Output Capacitor Selection

In a boost converter, the output capacitor requirements

are demanding due to the fact that the current waveform

is pulsed. The choice of component(s) is driven by the

acceptable ripple voltage which is affected by the ESR,

ESL and bulk capacitance as shown in Figure 8e. The total

output ripple voltage is:

Inductor Selection

Aninductorshouldbechosenthatcancarrythemaximum

input ꢁC current which occurs at the minimum input volt-

age.Thepeak-to-peakripplecurrentissetbytheinductance

and a good starting point is to choose a ripple current of

at least 40ꢀ of its maximum value:

ꢁ

ꢄ

1

ESR

1–D

ꢀV_OUT=I_O(MAX)

+

I_O(MAX)

ꢃ

ꢆ

f •C

ꢂ

_MAXꢅ

OUT

ΔI_L= 40%•

1−D_MAX

where the ﬁrst term is due to the bulk capacitance and

second term due to the ESR.

The required inductance can then be calculated to be:

V

_IN(MIN)•D_MAX

L =

f • ΔI_L

38145fb

15

LTC3814-5

APPLICATIONS INFORMATION

Formanydesignsitispossibletochooseasinglecapacitor

type that satisﬁes both the ESR and bulk C requirements

forthedesign.Incertaindemandingapplications,however,

the ripple voltage can be improved signiﬁcantly by con-

necting two or more types of capacitors in parallel. For

example, using a low ESR ceramic capacitor can minimize

the ESR step, while an electrolytic capacitor can be used

to supply the required bulk C.

than other types. Tantalum capacitors have the highest

capacitance density but it is important to only use types

that have been surge tested for use in switching power

supplies. Several excellent surge-tested choices are the

AVX TPS and TPSV or the KEMET T510 series. Aluminum

electrolytic capacitors have signiﬁcantly higher ESR, but

can be used in cost-driven applications providing that

consideration is given to ripple current ratings and long

term reliability. Other capacitor types include Panasonic

Once the output capacitor ESR and bulk capacitance

have been determined, the overall ripple voltage wave-

form should be veriﬁed on a dedicated PC board (see PC

Board Layout Checklist section for more information on

component placement). Lab breadboards generally suffer

fromexcessiveseriesinductance(duetointer-component

wiring), and these parasitics can make the switching

waveforms look signiﬁcantly worse than they would be

on a properly designed PC board.

SP and Sanyo POSCAPs. In applications with V

> 30V,

OUT

however, choices are limited to aluminum electrolytic and

ceramic capacitors.

L

ꢁ

V

OUT

V

SW

C

R

L

IN

OUT

8a. Circuit Diagram

Theoutputcapacitorinaboostregulatorexperienceshigh

RMS ripple currents, as shown in Figure 8d. The RMS

output capacitor ripple current is:

I

IN

I

L

V_O– V

IN(MIN)

I_RMS(COUT)ꢀI_O(MAX)•

V

IN(MIN)

8b. Inductor and Input Currents

Note that the ripple current ratings from capacitor manu-

facturers are often based on only 2000 hours of life. This

makes it advisable to further derate the capacitor or to

choose a capacitor rated at a higher temperature than

required. Several capacitors may also be placed in parallel

to meet size or height requirements in the design.

I

SW

t

ON

8c. Switch Current

Manufacturers such as Nichicon, Nippon Chemi-con

and Sanyo should be considered for high performance

throughhole capacitors. The OS-CON (organic semicon-

ductor dielectric) capacitor available from Sanyo has the

lowestproductofESRandsizeofanyaluminumelectrolytic

at a somewhat higher price. An additional ceramic capaci-

tor in parallel with OS-CON capacitors is recommended

to reduce the effect of their lead inductance.

I

ꢁ

t

OFF

I

O

8d. Diode and Output Currents

ΔV

COUT

V

OUT

(AC)

RINGING ꢁUE TO

TOTAL INꢁUCTANCE

(BOARꢁ + CAP)

In surface mount applications, multiple capacitors placed

in parallel may be required to meet the ESR, RMS current

handlingandloadsteprequirements.ꢁrytantalum,special

polymerandaluminumelectrolyticcapacitorsareavailable

in surface mount packages. Special polymer capacitors

offer very low ESR but have lower capacitance density

ΔV

ESR

8e. Output Voltage Ripple Waveform

38145 F08

Figure 8. Switching Waveforms for a Boost Converter

38145fb

16

LTC3814-5

APPLICATIONS INFORMATION

Input Capacitor Selection

toapproximatelyV +INTV .Theboostcapacitorneeds

OUT CC

to store about 100 times the gate charge required by the

top MOSFET. In most applications 0.1μF to 0.47μF, X5R

or X7R dielectric capacitor is adequate.

The input capacitor of a boost converter is less critical

than the output capacitor, due to the fact that the inductor

is in series with the input and the input current waveform

is continuous (see Figure 8b). The input voltage source

impedance determines the size of the input capacitor,

which is typically in the range of 10μF to 100μF. A low

ESR capacitor is recommended though not as critical as

for the output capacitor.

The reverse breakdown of the external diode, ꢁ , must

B

be greater than V . Another important consideration

OUT

for the external diode is the reverse recovery and reverse

leakage, either of which may cause excessive reverse

current to ﬂow at full reverse voltage. If the reverse

current times reverse voltage exceeds the maximum al-

lowable power dissipation, the diode may be damaged.

For best results, use an ultrafast recovery diode such as

the MMꢁL770T1.

The RMS input capacitor ripple current for a boost con-

verter is:

V

IN(MIN)

I_RMS(CIN)= 0.3•

•D_MAX

L • f

IC/MOSFET Driver Supplies (INTV )

CC

Please note that the input capacitor can see a very high

surge current when a battery is suddenly connected to

the input of the converter and solid tantalum capacitors

can fail catastrophically under these conditions. Be sure

to specify surge-tested capacitors!

TheLTC3814-5driversandtheLTC3814-5internalcircuits

are supplied from the INTV pin (see Figure 1). These

CC

pins have an operating range between 4.2V and 14V. If

the input voltage or another supply is not available in

this voltage range, two internal regulators are provided

to simplify the generation of this IC/driver supply voltage

as described in the next sections.

Output Voltage

The LTC3814-5 output voltage is set by a resistor divider

according to the following formula:

The N

Pin Regulator

DRV

ꢀ

_FB1ꢃ

_FB2ꢄ

R

The N

pin controls the gate of an external NMOS as

ꢁRV

V_OUT= 0.8V 1+

ꢂ

ꢅ

shown in Figure 9b and can be used to generate a regu-

ꢁ

lated 5.5V supply from V or V . Since the NMOS is

external, it can be chosen with a BV

IN

OUT

The external resistor divider is connected to the output as

shownintheFunctionalꢁiagram, allowingremotevoltage

sensing. The resultant feedback signal is compared with

the internal precision 800mV voltage reference by the

error ampliﬁer. The internal reference has a guaranteed

tolerance of less than 1ꢀ. Tolerance of the feedback

resistors will add additional error to the output voltage.

0.1ꢀ to 1ꢀ resistors are recommended.

or power rating

ꢁSS

as high as necessary to safely derive power from a high

voltage input or output voltage. In order to generate an

INTV supply that is always above the 4.2V UV threshold,

CC

the supply connected to the drain must be greater than

4.2V + R

• 40μA + V .

NꢁRV

T

The EXTV Pin Regulator

CC

A second low dropout regulator is available for voltages

≤ 15V. When a supply that is greater than 4.7V is con-

Top MOSFET Driver Supply (C , D )

B

nected to the EXTV pin, the internal LꢁO will regulate

AnexternalbootstrapcapacitorC connectedtotheBOOST

CC

B

5.5V on INTV from the EXTV pin voltage and will also

pinsuppliesthegatedrivevoltageforthetopsideMOSFET.

CC

disable the NꢁRV pin regulator. This regulator is disabled

This capacitor is charged through diode ꢁ from INTV

B

CC

when the IC is shut down, when INTV < 4.2V, or when

when the switch node is low. When the top MOSFET turns

CC

EXTV < 4.7V.

on, the switch node rises to V and the BOOST pin rises

CC

OUT

38145fb

17

LTC3814-5

APPLICATIONS INFORMATION

Using the INTV Regulators

to keep INTV above the UV threshold and the BV

CC ꢁSS

CC

of the external NMOS must be chosen to be greater

than V . The EXTV regulator is disabled by

One, both or neither of these regulators can be used to

generate the 5.5V IC/driver supply depending on the

circuit requirements, available supplies, and the voltage

IN(MAX)

grounding the EXTV pin.

CC

< 14.7V and V is allowed to

IN(MAX) IN

range of V or V . ꢁeriving the 5.5V supply from V

3. Figure 9c. If the V

fall below 4.2V without disrupting the boost converter

operation, use this conﬁguration. The INTV supply

IN

OUT

IN

is more efﬁcient, however deriving it from V

advantage of maintaining regulation of V

has the

OUT

when V

OUT

IN

CC

dropsbelowtheUVthreshold.Fourpossibleconﬁgurations

are shown in Figures 9a through 9d, and are described

as follows:

is derived from V until the V

> 4.7V. Once INTV

IN

OUT

CC

is derived from V , V can fall below the 4V UV

OUT IN

threshold without losing regulation of V . Note that

OUT

in this conﬁguration, V must be > ~5V at least long

IN

1. Figure 9a. If the V voltage or another low voltage

IN

enough to start up the LTC3814-5 and charge V

>

OUT

supply between 4.5V and 14V is available, the sim-

4.7V. Also, since V

is connected to the EXTV pin,

OUT

CC

plest approach is to connect this supply directly to the

this conﬁguration is limited to V

< 15V.

OUT

INTV and ꢁRV pins. The internal regulators are

CC

disabled by shorting NꢁRV and EXTV to INTV .

4. Figure 9d. Similar to conﬁguration 3 except that V

CC

OUT

is allowed to be >15V since V

is connected to an

OUT

2. Figure 9b. If V

> 14V, an external NMOS con-

IN(MAX)

external NMOS with appropriately rated BV . V has

ꢁSS IN

nected to the NꢁRV pin can be used to generate 5.5V

same start-up requirement as 3.

from V . V

must be > 4.5V + R

• 40μA + V

NꢁRV T

IN IN(MIN)

V

IN

R

NꢁRV

INTV

CC

INTV

5.5V

CC

+

LTC3814-5

+

–

LTC3814-5

4.5V to

14V

EXTV

CC

(a) 4.2V to 14V

Supply Available

(b) INTV from V ,

CC IN

V

> 14V

IN

V

OUT

V

< 14.7V

IN

V

< 14.7V

IN

R

NꢁRV

INTV

CC

5.5V

CC

+

LTC3814-5

EXTV

CC

EXTV

V

≤ 15V

CC

OUT

38145 F09

(c) INTV from V

,

(d) INTV from V

,

OUT

CC

OUT

CC

V

≤ 15V

V

> 15V

OUT

Figure 9. Four Possible Ways to Generate INTV_CCSupply

38145fb

18

LTC3814-5

APPLICATIONS INFORMATION

Power Dissipation Considerations

ꢀ

_SENSE(MAX)ꢃ

R_L• V • V

V_OUT(s)

IN

H(s)=

=

ꢂ

ꢅ

V (s)

2.4• V_OUT• R_DS(ON)

ꢄ

Applications using large MOSFETs and high frequency

ꢁ

ITH

of operation may result in a large ꢁRV /INTV supply

CC

ꢀ

_OUTꢃ

1+ s • R_ESR• C

1+ s • R_L• C_OUT

current. Therefore, when using the linear regulators, it is

necessary to verify that the resulting power dissipation

is within the maximum limits. The ꢁRV /INTV supply

•

ꢂ

ꢅ

ꢁ

ꢄ

2

CC

ꢀ

ꢃ

ꢅ

ꢄ

(1)

V_OUT

L

current consists of the MOSFET gate current plus the

LTC3814-5 quiescent current:

• 1ꢆ s •

•

ꢂ

2

R_L

V

ꢁ

IN

I

= (f)(Q

+ Q ) + 3mA

G(BOTTOM)

s= j2ꢇ f

CC

G(TOP)

This portion of the power supply is pretty well out of the

user’s control since the current sense is chosen based on

maximum output load, and the output capacitor is usually

chosen based on load regulation and ripple requirements

without considering AC loop response. The feedback am-

pliﬁer, on the other hand, gives us a handle on which to

adjust the AC response. The goal is to have an 180° phase

shift at ꢁC so the loop regulates and less than 360° phase

shift at the point where the loop gain falls below 0dB, i.e.,

the crossover frequency, with as much gain as possible

at frequencies below the crossover frequency. Since the

feedback ampliﬁer adds an additional 90° phase shift to

the phase shift already present from the modulator/output

stage, some phase boost is required at the crossover

frequency to achieve good phase margin. The design

procedure (described in more detail in the next section) is

to (1) obtain a gain/phase plot of modulator/output stage,

(2) choose a crossover frequency and the required phase

boost, and (3) calculate the compensation network.

When using the internal LꢁO regulator, the power dissipa-

tion is internal so the rise in junction temperature can be

estimatedfromtheequationgiveninNote2oftheElectrical

Characteristics as follows:

T = T + I

• (V

– V

)(38°C/W)

INTVCC

J

A

EXTVCC

and must not exceed 125°C.

Likewise, iftheexternalNMOSregulatorisused, theworst

case power dissipation is calculated to be:

P

= (V – 5.5V) • I

ꢁRAIN(MAX) CC

MOSFET

and can be used to properly size the device.

FEEDBACK LOOP/COMPENSATION

Introduction

InatypicalLTC3814-5circuit,thefeedbackloopconsistsof

twosections:themodulator/outputstageandthefeedback

ampliﬁer/compensation network. The modulator/output

stage consists of the current sense component and in-

ternal current comparator, the power MOSFET switches

and drivers, and the output ﬁlter and load. The transfer

function of the modulator/output stage for a boost con-

180

90

GAIN

verter consists of an output capacitor pole, R C , and

L OUT

0

an ESR zero, R

C

OUT

, and also a “right-half plane” zero,

). It has a gain/phase curve that is typi-

ESR OUT

(R /L)(V /V

2

L

IN

PHASE

–90

–180

cally like the curve shown in Figure 10 and is expressed

mathematically in the following equation.

FREQUENCY (Hz)

38145 F10

Figure 10. Bode Plot of Boost Modulator/Output Stage

38145fb

19

LTC3814-5

APPLICATIONS INFORMATION

Thetwotypesofcompensationnetworks, Type2andType

3areshowninFigures11and12.Whencomponentvalues

are chosen properly, these networks provide a “phase

bump” at the crossover frequency. Type 2 uses a single

pole-zero pair to provide up to about 60° of phase boost

while Type 3 uses two poles and two zeros to provide up

to 150° of phase boost.

signiﬁcantly. Applications that require optimized transient

response will require recalculation of the compensation

values speciﬁcally for the circuit in question. The underly-

ing mathematics are complex, but the component values

can be calculated in a straightforward manner if we know

the gain and phase of the modulator at the crossover

frequency.

The compensation of boost converters are complicated

by two factors: the RHP zero and the dependence of the

loop gain on the duty cycle. The RHP zero adds additional

phase lag and gain. The phase lag degrades phase margin

and the added gain keeps the gain high typically in the

frequency region where the user is trying the roll off the

gain below 0dB. This often forces the user to choose a

crossover frequency at a lower frequency than originally

desired. The duty cycle effect of gain (see above transfer

function)causesthephasemarginandcrossoverfrequency

to be dependent on the input supply voltage which may

causeproblemsiftheinputvoltagevariesoverawiderange

since the compensation network can only be optimized

for a speciﬁc crossover frequency. These two factors

usually can be overcome if the crossover frequency is

chosen low enough.

Modulator gain and phase can be obtained in one of

three ways: measured directly from a breadboard, or if

the appropriate parasitic values are known, simulated or

generated from the modulator transfer function. Mea-

surement will give more accurate results, but simulation

or transfer function can often get close enough to give

a working system. To measure the modulator gain and

phase directly, wire up a breadboard with an LTC3814-5

and the actual MOSFETs, inductor and input and output

capacitors that the ﬁnal design will use. This breadboard

should use appropriate construction techniques for high

speed analog circuitry: bypass capacitors located close

to the LTC3814-5, no long wires connecting components,

appropriately sized ground returns, etc. Wire the feedback

ampliﬁer with a 0.1μF feedback capacitor from I to FB

TH

and a 10k to 100k resistor from V

to FB. Choose the

OUT

bias resistor (R ) as required to set the desired output

B

Feedback Component Selection

voltage. ꢁisconnect R from ground and connect it to

B

a signal generator or to the source output of a network

Selecting the R and C values for a typical Type 2 or

Type 3 loop is a nontrivial task. The applications shown

in this data sheet show typical values, optimized for the

power components shown. They should give acceptable

performance with similar power components, but can be

way off if even one major power component is changed

analyzer to inject a test signal into the loop. Measure the

gain and phase from the I pin to the output node at the

TH

positive terminal of the output capacitor. Make sure the

analyzer’s input is AC coupled so that the ꢁC voltages

present at both the I and V

nodes don’t corrupt the

OUT

TH

measurements or damage the analyzer.

C2

C1

IN

C2

C1

C3

R3

IN

R2

–6dB/OCT

GAIN

R1

FB

R1

–6dB/OCT

GAIN

FB

–6dB/OCT

–

+6dB/OCT

–6dB/OCT

R

OUT

0

FREQ

–90

R

B

OUT

0

FREQ

–90

B

V

REF

+

REF

–180

–270

–360

–180

–270

–360

PHASE

38145 F11

38145 F12

Figure 11. Type 2 Schematic and Transfer Function

Figure 12. Type 3 Schematic and Transfer Function

38145fb

20

LTC3814-5

APPLICATIONS INFORMATION

* Modulator/Output Stage

If breadboard measurement is not practical, mathemat-

ical software such as MATHCAꢁ or MATLAB can be used

to generate plots from the transfer function given in

Equation 1. A SPICE simulation can also be used to gener-

ate approximate gain/phase curves. Plug the expected

capacitor, inductor and MOSFET values into the following

eout out 0 laplace {v(ith)} =

{0.5*K*Rload*vin/vout *(1+s/wz)/(1+s/wp)

*(1-s*L/Rload*vout*vout/vin/vin)}

rload out 0 {rload}

*

vstim out outin dc=0 ac=10m; ac stimulus

SPICEdeckand generateanACplotofV /V withgain

OUT ITH

.ac dec 100 10 10meg

in dB and phase in degrees. Refer to your SPICE manual

.probe

.end

for details of how to generate this plot.

*This ﬁle simulates a simpliﬁed model of

the 3814-5 for generating a v(out)/(vith) or

a v(out)/v(outin) bode plot

With the gain/phase plot in hand, a loop crossover fre-

quency can be chosen. Usually the curves look something

likeFigure10.Choosethecrossoverfrequencyabout25ꢀ

of the switching frequency for maximum bandwidth. Al-

.param vout=24

.param vin=12

though it may be tempting to go beyond f /4, remember

SW

.param L=10u

that signiﬁcant phase shift occurs at half the switching

frequency that isn’t modeled in the above H(s) equation

and PSPICE code. Note the gain (GAIN, in dB) and phase

(PHASE, in degrees) at this point. The desired feedback

ampliﬁer gain will be –GAIN to make the loop gain at 0dB

at this frequency. Now calculate the needed phase boost,

assuming 60° as a target phase margin:

.param cout=270u

.param esr=.018

.param rload=24

*

.param rdson=0.02

.param Vrng=1

.param vsnsmax={0.173*Vrng-0.026}

.param K={vsnsmax/rdson/1.2}

.param wz={1/esr/cout}

.param wp={2/rload/cout}

*

BOOST = – (PHASE + 30°)

If the required BOOST is less than 60°, a Type 2 loop can

be used successfully, saving two external components.

BOOST values greater than 60° usually require Type 3

loops for satisfactory performance.

* Feedback Ampliﬁer

rfb1 outin vfb 29k

rfb2 vfb 0 1k

Finally, choose a convenient resistor value for R1 (10k

is usually a good value). Now calculate the remaining

values:

eithx ithx 0 laplace {0.8-v(vfb)} =

{1/(1+s/1000)}

eith ith 0 value={limit(1e6*v(ithx),0,2.4)}

cc1 ith vfb 100p

cc2 ith x1 0.01p

rc x1 vfb 100k

(K is a constant used in the calculations)

f = chosen crossover frequency

(GAIN/20)

G = 10

(this converts GAIN in dB to G in

*

absolute gain)

38145fb

21

LTC3814-5

APPLICATIONS INFORMATION

TYPE 2 Loop:

Type 2:

A (s)=

1+ s •R3•C2

BOOST

ꢀ

ꢁ

ꢃ

ꢄ

K = tan

+ 45°

ꢂ

ꢅ

C2 •C3

C2+C3

ꢀ

ꢁ

ꢃ

ꢄ

2

1

s •R1• C2+C3 • 1+ s •R3•

(

)

ꢂ

ꢅ

C2=

2ꢆ • f •G•K •R1

Type 3:

A (s)=

C1=C2 K²ꢇ1

(

)

1

•

K

s •R1• C2+C3

(

)

R2=

R_B=

2ꢆ • f •C1

V_REF(R1)

1+ s • R1+R3 •C3 • 1+ s •R2•C1

(

)

(

)

(

C1• C2

ꢀ

ꢂ

ꢃ

ꢅ

1+ s •R3•C3 • 1+ s •R2•

(

)

V_OUTꢇ V_REF

ꢁ

ꢄ

C1+C2

TYPE 3 Loop:

For SPICE, simulate the previous PSPICE code with

calculated compensation values entered and generate a

BOOST

4

1

ꢀ

ꢁ

ꢃ

ꢄ

K = tan²

+ 45°

ꢂ

ꢅ

gain/phase plot of V /V

.

OUT OUTIN

Fault Conditions: Current Limit

C2=

2ꢆ • f •G•R1

C1=C2 K ꢇ1

The maximum inductor current is inherently limited in a

currentmodecontrollerbythemaximumsensevoltage.In

the LTC3814-5, the maximum sense voltage is controlled

(

)

K

R2=

R3=

C3=

by the voltage on the V

pin. With peak current control,

RNG

2ꢆ • f •C1

the maximum sense voltage and the sense resistance

determine the maximum allowed inductor valley current.

The corresponding output current limit is:

R1

K ꢇ1

1

V_SNS(MAX)

1

2ꢆf K • R3

I_LIMIT

=

− ΔI_L

2

R_DS(ON)ρ_T

V_REF(R1)

_OUTꢇ V_REF

R_B=

V

The current limit value should be checked to ensure that

I

>I

.Theminimumvalueofcurrentlimit

LIMIT(MIN) OUT(MAX)

generally occurs at the lowest V at the highest ambient

IN

SPICE or mathematical software can be used to generate

the gain/phase plots for the compensated power supply to

do a sanity check on the component values before trying

them out on the actual hardware. For software, use the

following transfer function:

temperature, conditions that cause the largest power loss

in the converter. Note that it is important to check for

self-consistency between the assumed MOSFET junction

temperature and the resulting value of I

the MOSFET switches.

which heats

LIMIT

T(s) = A(s)H(s)

Caution should be used when setting the current limit

based upon the R of the MOSFETs. The maximum

where H(s) was given in equation 2 and A(s) depends on

compensation circuit used:

ꢁS(ON)

current limit is determined by the minimum MOSFET

on-resistance. ꢁata sheets typically specify nominal

and maximum values for R

, but not a minimum.

ꢁS(ON)

38145fb

22

LTC3814-5

APPLICATIONS INFORMATION

A reasonable assumption is that the minimum R

3.3V

OR 5V

ꢁS(ON)

RUN/SS

lies the same percentage below the typical value as the

maximumliesaboveit.ConsulttheMOSFETmanufacturer

for further guidelines.

ꢁ1

C

SS

C

SS

38145 F13

Note that in a boost mode architecture, it is only possible

to provide protection for “soft” shorts where V

> V .

Figure 13. RUN/SS Pin Interfacing

OUT

IN

For hard shorts, the inductor current is limited only by the

input supply capability.

Efﬁciency Considerations

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100ꢀ.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Although all dissipative

elements in the circuit produce losses, four main sources

account for most of the losses in LTC3814-5 circuits:

Run/Soft-Start Function

TheRUN/SS pin is amultipurpose pinthatprovides a soft-

start function and a means to shut down the LTC3814-5.

Soft-start reduces the input supply’s surge current by

controlling the ramp rate of the I voltage, eliminates

TH

output overshoot and can also be used for power supply

sequencing.

2

1. ꢁC I R losses. These arise from the resistances of the

Pulling RUN/SS below 0.9V puts the LTC3814-5 into a low

MOSFETs, inductor and PC board traces and cause

the efﬁciency to drop at high input currents. The input

current is maximum at maximum output current and

minimuminputvoltage.Theaverageinputcurrentﬂows

through L, but is chopped between the top and bottom

MOSFETs. If the two MOSFETs have approximately the

quiescent current shutdown (I = 224μA). This pin can be

Q

drivendirectlyfromlogicasshowninFigure14. Releasing

the RUN/SS pin allows an internal 1.4μA current source to

charge up the soft-start capacitor, C . When the voltage

SS

on RUN/SS reaches 0.9V, the LTC3814-5 turns on and

begins ramping the I voltage at V = V – 0.9V. As the

same R

, then the resistance of one MOSFET can

TH

ITH

SS

ꢁS(ON)

RUN/SS voltage increases from 0.9V to 3.3V, the current

limit is increased from 0ꢀ to 100ꢀ of its maximum value.

The RUN/SS voltage continues to charge until it reaches

its internally clamped value of 4V.

simply be summed with the resistances of L and the

2

board traces to obtain the ꢁC I R loss. For example, if

R

= 0.01Ω and R = 0.005Ω, the loss will range

ꢁS(ON)

L

from 15mW to 1.5W as the input current varies from

1A to 10A.

If RUN/SS starts at 0V, the delay before starting is

approximately:

2. Transition loss. This loss arises from the brief amount

of time the bottom MOSFET spends in the saturated

region during switch node transitions. It depends upon

the output voltage, load current, driver strength and

MOSFET capacitance, among other factors. The loss

is signiﬁcant at output voltages above 20V and can be

0.9V

1.4µA

t_DELAY,START

=

C = 0.64s/µF C

SS SS

(

)

plus an additional delay, before the current limit reaches

its maximum value of:

estimated from the second term of the P

equa-

MAIN

2.4V

1.4µA

tion found in the Power MOSFET Selection section.

When transition losses are signiﬁcant, efﬁciency can

be improved by lowering the frequency and/or using a

t_DELAY,REG

≥

C_SS

The start delay can be reduced by using diode ꢁ1 in

Figure 13.

bottom MOSFET(s) with lower C

at the expense of

RSS

higher R

.

ꢁS(ON)

3. INTV current. This is the sum of the MOSFET

CC

driver and control currents. Control current is typically

38145fb

23

LTC3814-5

APPLICATIONS INFORMATION

about 3mA and driver current can be calculated by:

Choose R1 = 133k and R2 = 20k. Now calculate timing

resistor R

I

=f(Q

+Q

),whereQ

andQ

:

OFF

GATE

G(TOP)

G(BOT)

G(TOP)

G(BOT)

are the gate charges of the top and bottom MOSFETs.

1+133k / 20k

250kHz •76pF

R_OFF

=

= 402.6k

This loss is proportional to the supply voltage that

INTV is derived from, i.e., V , V

supply connected to INTV .

or an external

CC

IN OUT

CC

The duty cycle is:

4. C

loss. The output capacitor has the difﬁcult job

OUT

12V

24V

D=1−

= 0.5

of ﬁltering the large RMS input current out of the synchro-

nous MOSFET. It must have a very low ESR to minimize

the AC I R loss

2

.

and the maximum input current is:

Other losses, including C ESR loss, Schottky diode ꢁ1

IN

5A

1− 0.5

I

=

=10A

IN(MAX)

conduction loss during dead time and inductor core loss

generally account for less than 2ꢀ additional loss. When

making adjustments to improve efﬁciency, the input cur-

rent is the best indicator of changes in efﬁciency. If you

make a change and the input current decreases, then the

efﬁciency has increased. If there is no change in input

current, then there is no change in efﬁciency.

Choose the inductor for about 40ꢀ ripple current at the

maximum V :

IN

12V

250kHz •0.4•10A

12V

24V

ꢁ

ꢄ

ꢅ

L =

1ꢀ

= 6μH

ꢃ

ꢆ

ꢂ

The peak inductor current is:

5A

Checking Transient Response

1

The regulator loop response can be checked by looking

at the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

I_L(PEAK)

=

+ (4A)=12A

1− 0.5 2

so, choose the CꢁEP147 5.9μH inductor with I = 16.4A

at 100°C.

SAT

load step occurs, V

immediately shifts by an amount

OUT

equal to ΔI

(ESR), where ESR is the effective series

LOAꢁ

Next, choose the bottom MOSFET switch. Since the drain

of the MOSFET will see the full output voltage plus any

ringing, choose a 40V MOSFET to provide a margin of

safety. The Si7848ꢁP has:

resistance of C . ΔI

also begins to charge or dis-

OUT

LOAꢁ

chargeC generatingafeedbackerrorsignalusedbythe

OUT

regulator to return V

this recovery time, V

to its steady-state value. ꢁuring

can be monitored for overshoot

OUT

or ringing that would indicate a stability problem.

BV

ꢁS(ON)

δ = 0.006/°C,

= 40V

ꢁSS

R

= 9mΩ(max)/7.5mΩ(nom),

Design Example

C

V

JA

= (14nC – 6nC)/20V = 400pF,

MILLER

GS(MILLER)

θ = 20°C/W.

Asadesignexample,takeasupplywiththefollowingspeci-

= 3.5V,

ﬁcations: V = 12V 20ꢀ, V

= 24V 5ꢀ, I

=

IN

OUT

OUT(MAX)

5A, f=250kHz. SinceV canvaryaroundthe12Vnominal

IN

value, connect a resistive divider from V to V to keep

IN

OFF

This yields a nominal sense voltage of:

the frequency independent of V changes:

IN

1.7 •0.0075Ω •5A

V_SNS(NOM)

=

=128mV

R1 12V

R2 1.55V

1− 0.5

=

−1= 6.74

Toguaranteepropercurrentlimitatworst-caseconditions,

increase nominal V

by 50ꢀ to 190mV. To check if the

SNS

current limit is acceptable at V

= 190mV, assume a

SNS

38145fb

24

LTC3814-5

APPLICATIONS INFORMATION

junction temperature of about 30°C above a 70°C ambient

The junction temperature will be signiﬁcantly less at

nominal current, but this analysis shows that careful at-

tention to heat sinking on the board will be necessary in

this circuit.

(ρ

= 1.4):

100°C

190mV

1.4•0.009Ω

1

2

I

≥

− • 4A =13A

IN(MAX)

Since V is always between 4.5V and 14V, it can be con-

IN

I

= I

• (1-ꢁ

) = 6.5A

nected directly to the INTV and ꢁRV pins.

OUT(MAX)

IN(MAX)

MAX

CC

and double-check the assumed T in the MOSFET:

C

OUT

is chosen for an RMS current rating of about 5A at

J

85°C. The output capacitors are chosen for a low ESR

of 0.018Ω to minimize output voltage changes due to

inductor ripple current and load steps. The ripple voltage

will be only:

1

ꢁ

ꢂ

ꢄ

ꢅ

2

P_TOP

=

6.5A (1.4)(0.009ꢇ)=1.06W

(

)

ꢃ

ꢆ

1ꢀ 0.5

T = 70°C + 1.06W • 20°C/W = 91°C

J

ꢂ

ꢅ

1

0.018

Verify that the Si7848ꢁP is also a good choice for the

bottom MOSFET by checking its power dissipation at

current limit and minimum input voltage, assuming a

junction temperature of 30°C above a 70°C ambient

ꢀV_OUT(RIPPLE)=(5A)

= 0.25V (about 1%)

+

ꢄ

ꢇ

250kHz •330μF 1ꢁ 0.5

ꢃ

ꢆ

(ρ

= 1.4):

A 0A to 5A load step will cause an output change of up to:

ΔV = ΔI • ESR = 5A • 0.018Ω

100°C

ꢁ

ꢂ

ꢄ²

ꢅ

OUT(STEP)

= 90mV

LOAꢁ

6.5A

1ꢀ 0.5

P_BOT= 0.5

(1.4)(0.009ꢇ)

ꢃ

ꢆ

An optional 10μF ceramic output capacitor is included

to minimize the effect of ESL in the output ripple. The

complete circuit is shown in Figure 14.

1

2

6.5A

1ꢀ 0.5

ꢁ

ꢂ

ꢄ

ꢅ

+ (24V)²

(2)(400pF)

ꢃ

ꢆ

1

ꢁ

ꢂ

ꢄ

ꢅ

•

+

(250kHz)

ꢃ

ꢆ

12V ꢀ 3.5V 3.5V

=1.06W + 0.30W =1.36W

T = 70°C + 1.36W • 20°C/W = 97°C

J

V

OUT

R

OFF

403k

V

IN

12V

C

68μF

20V

C

ꢁ

OFF

100pF

IN1

IN2

B

1μF

BAS19

133k

16

15

20V

1

L1

BOOST

LTC3814-5

I

OFF

C

5.9μH

B

20k

PGNꢁ

2

0.1μF

V

OFF

TG

M1

Si7848ꢁP

3

4

5

6

RNG

V

24V

5A

OUT

14

13

SW

PGOOꢁ

I

PGNꢁ

TH

C

OUT1

C

0.1μF

ꢁRVCC

C

V

330μF

35V × 2

SS

1000pF

FB

12

11

M2

Si7848ꢁP

BG

ꢁ1

B1100

C

7

8

OUT2

10μF

50V

INTV

RUN/SS

SGNꢁ

CC

10

9

EXTV

CC

NꢁRV

C

C2

C

VCC

1μF

470pF

SGNꢁ

PGNꢁ

R

250k

C

C1

47pF

C

R

FB2

1k

R

, 29.4k

FB1

38145 F14

Figure 14. 12V Input Voltage to 24V/5A

38145fb

25

LTC3814-5

APPLICATIONS INFORMATION

PC Board Layout Checklist

ꢁC net (V , V , GNꢁ or to any other ꢁC rail in your

IN OUT

system).

When laying out a PC board follow one of two suggested

approaches. The simple PC board layout requires a dedi-

cated ground plane layer. Also, for higher currents, it is

recommended to use a multilayer board to help with heat

sinking power components.

When laying out a printed circuit board, without a ground

plane, use the following checklist to ensure proper opera-

tion of the controller.

• Segregate the signal and power grounds. All small

signal components should return to the SGNꢁ pin at

one point which is then tied to the PGNꢁ pin close to

the source of M2.

• The ground plane layer should not have any traces and

it should be as close as possible to the layer with power

MOSFETs.

• Place M2 as close to the controller as possible, keeping

the PGNꢁ, BG and SW traces short.

• Place C , C , MOSFETs, ꢁ1 and inductor all in one

IN OUT

compact area. It may help to have some components

on the bottom side of the board.

•

Connect the input capacitor(s) C close to the pow-

IN

er MOSFETs. This capacitor carries the MOSFET AC

current.

•

Use an immediate via to connect the components to

groundplaneincludingSGNꢁandPGNꢁofLTC3814-5.

Use several bigger vias for power components.

• Keep the high dV/dt SW, BOOST and TG nodes away

from sensitive small-signal nodes.

• Use compact plane for switch node (SW) to improve

cooling of the MOSFETs and to keep EMI down.

• Connect the INTV decoupling capacitor C

closely

CC

VCC

to the INTV and SGNꢁ pins.

CC

• Use planes for V and V

to maintain good voltage

OUT

IN

ﬁltering and to keep power losses low.

• Connect the top driver boost capacitor C closely to

B

the BOOST and SW pins.

• Floodallunusedareasonalllayerswithcopper.Flooding

with copper will reduce the temperature rise of power

component. You can connect the copper areas to any

• ConnectthebottomdriverdecouplingcapacitorC

INTVCC

closely to the INTV and PGNꢁ pins.

CC

38145fb

26

LTC3814-5

PACKAGE DESCRIPTION

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation BA

4.90 – 5.10*

(.193 – .201)

2.74

(.108)

2.74

(.108)

16 1514 13 12 1110

9

6.60 ±0.10

2.74

(.108)

4.50 ±0.10

6.40

(.252)

BSC

SEE NOTE 4

2.74

(.108)

0.45 ±0.05

1.05 ±0.10

0.65 BSC

5

7

8

1

2

3

4

6

RECOMMENꢁEꢁ SOLꢁER PAꢁ LAYOUT

1.10

(.0433)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.195 – 0.30

FE16 (BA) TSSOP 0204

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING ꢁIMENSION: MILLIMETERS 4. RECOMMENꢁEꢁ MINIMUM PCB METAL SIZE

FOR EXPOSEꢁ PAꢁ ATTACHMENT

*ꢁIMENSIONS ꢁO NOT INCLUꢁE MOLꢁ FLASH. MOLꢁ FLASH

SHALL NOT EXCEEꢁ 0.150mm (.006") PER SIꢁE

MILLIMETERS

(INCHES)

2. ꢁIMENSIONS ARE IN

3. ꢁRAWING NOT TO SCALE

38145fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LTC3814-5

TYPICAL APPLICATION

24V Input Voltage to 50V/5A

V

IN

12V* TO 40V

V

IN

V

OUT

C

68μF

50V

C

IN2

R

IN1

NꢁRV

100k

1μF

R

OFF

806k

M3

143k

C

50V

ZXMN10A07F

PGNꢁ

ꢁ

B

BAS19

OFF

150k

100pF

L1

16

1

10μH

BOOST

I

OFF

C

B

LTC3814-5

10k

2

3

4

5

0.1μF

15

14

V

TG

OFF

100k

M1

Si7850ꢁP

RNG

SW

V

50V

5A

OUT

PGOOꢁ

I

V

13

PGNꢁ

TH

C

OUT1

C

6

ꢁRVCC

0.1μF

C

220μF

63V

× 2

SS

1000pF

FB

ꢁ1

B1100

12

11

M2

BG

Si7850ꢁP

C

7

8

OUT2

10μF

INTV

CC

RUN/SS

SGNꢁ

10

9

100V

× 2

EXTV

CC

NꢁRV

C

C2

VCC

330pF

1μF

SGNꢁ

PGNꢁ

C

C1

150pF

R

C

R

499Ω

R

300k

FB2

FB1

30.9k

38145 TA02

*I

= 2A AT V = 12V

IN

OUT(MAX)

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC ꢁesign;

LTC1624

Current Mode ꢁC/ꢁC Controller

V

Up to 36V

IN

LTC1700

No R ™ Synchronous Step-Up Controller

SENSE

Up to 95ꢀ Efﬁciency, Operating as Low as 0.9V Input

LTC1871/LTC1871-7 No R

, Wide Input Range ꢁC/ꢁC Boost Controller No R , Current Mode Control, 2.5V ≤ V ≤ 36V

SENSE

IN

LTC1872/LTC1872B

LT^®1930

SOT-23 Boost Controller

ꢁelivers Up to 5A, 550kHz Fixed Frequency, Current Mode

1.2MHz, SOT-23 Boost Converter

Inverting 1.2MHz, SOT-23 Converter

1A/2A 3MHz Synchronous Boost Converters

Up to 34V Output, 2.6V V 16V, Miniature ꢁesign

IN

LT1931

Positive-to Negative ꢁC/ꢁC Conversion, Miniature ꢁesign

LTC3401/LTC3402

Up to 97ꢀ Efﬁciency, Very Small Solution, 0.5V ≤ V ≤ 5V

IN

LTC3703/LTC3703-5 100V Synchronous Controller

Step-Up or Step ꢁown, 600kHz, SSOP-16, SSOP-28

LTC3704

LT3782

Positive-to Negative ꢁC/ꢁC Controller

2-Phase Step-Up ꢁC/ꢁC Controller

No R

, Current Mode Control, 50kHz to 1MHz

SENSE

High Power Boost with Programmable Frequency, 150kHz to 500kHz,

6V ≤ V ≤ 40V

IN

LTC3803/LTC3803-5 200kHz Flyback ꢁC/ꢁC Controller

Optimized for ꢁriving 6V MOSFETs ThinSOT

LTC3813

LTC3872

LTC3873

100V Current Mode Synchronous Step-Up Controller

Large 1Ω Gate ꢁrivers, No Current Sense Resistor Required

No R

Current Mode Boost ꢁC/ꢁC Controller

Constant-Frequency Boost/Flyback/SEPIC

550kHz Fixed Frequency, 2.75V ≤ V ≤ 9.8V

IN

SENSE

V

and V

Limited Only by External Components

OUT

SENSE

IN

Controller

No R

is a trademark of Linear Technology Corporation.

SENSE

38145fb

LT 0408 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3814EFE-5-PBF
厂家：	Linear
描述：	60V Current Mode Synchronous Step-Up Controller 60V电流模式同步升压控制器控制器
文件：	总28页 (文件大小：355K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3814EFE-5-PBF [Linear]

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