LTC3816EFE#TRPBF_技术文档

LTC3816

Single-Phase Wide V

IN

Range DC/DC Controller for

Intel IMVP-6/IMVP-6.5 CPUs

DescripTion

FeaTures

The LTC^®3816 is a single-phase synchronous step-down

DC/DCswitchingregulatorcontrollerthatdrivesN-channel

power MOSFETs in a constant-frequency voltage mode

architecture. The controller’s leading edge modulation to-

pologyallowsextremelylowoutputvoltagesandsupports

a phase-lockable switching frequency up to 550kHz. The

output voltage is programmed using a 7-bit VID code.

n

Supports 7-Bit IMVP-6/IMVP-6.5 VID Code and

Features

n

Wide V Range: 4.5V to 36V Operation with

IN

Optional Line Feedforward Compensation

n

t

< 35ns, Capable of Very Low Duty Cycle

ON(MIN)

n

Temperature Compensated Inductor DCR or Sense

Resistor Output Current Monitoring

n

Differential Remote Output Voltage Sensing with

Programmable Active Voltage Positioning

Phase-Lockable Fixed Frequency: 150kHz to 550kHz

TheLTC3816featuresalloftheIMVP-6/IMVP-6.5require-

ments, including start-up to a preset boot voltage, differ-

ential remote output voltage sensing with programmable

n

Programmable UVLO, Preset V

at Boot-Up

OUT

active voltage positioning, I

output current reporting,

MON

Programmable Slow Slew Rate Sleep State Exit

Internal LDO for Single Supply Operation

Overvoltage and Overcurrent Protection

PWRGD and VRTT# Thermal Throttling Flags

Power Optimization During Sleep and Light Load

38-Pin Thermally Enhanced eTSSOP and 5mm × 7mm

QFN Packages

power optimization during sleep state, and fast or slow

slew rate sleep state exit.

Fault protection features include input undervoltage

lockout, cycle-by-cycle current limit, output overvoltage

protection, and PWRGD and overtemperature ﬂags.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and R

SENSE

is a trademark of Linear Technology Corporation. All other trademarks are the property of their

respective owners. Protected by U.S. Patents, including 5408150, 5055767, 5481178, 6580258.

applicaTions

n

Embedded Computing

n

Mobile Computers, Internet Devices

n

Navigation Displays

Typical applicaTion

High Efﬁciency, Synchronous IMVP-6/ IMVP-6.5 Step-Down Controller

V

V3

CCP

1.1V

V

IN

3.3V

Efﬁciency and Power Loss

vs Load Current

4.5V TO 36V

+

47µF s2 + 10µF s2

4.7µF

56Ω 1.9k 1.9k

V

EXTV

INTV

IN

CC

TG

100

90

80

70

60

50

40

30

20

10

0

10

9

8

7

6

5

4

3

2

1

0

V

= 12V, f

CC(CORE)

FORCED CONTINUOUS MODE

= 400kHz

= 0.75V, V

PWRGD

CLKEN#

VRTT#

PWRGD

CLKEN#

VRTT#

IN

OSC

0.33µH,

1.3mΩ

= 5V

EXTVCC

0.1µF

BOOST

SW

VR

ON

VR

ON

V

CC(CORE)

NTC

10k

+

DPRSLPVR

MODE/SYNC

RFREQ

BG

330µF s3

+ 10µF s20

MODE/SYNC

INTV

BSOURCE

CC

EFFICIENCY

2.55k

LFF

LTC3816

I

SENP

SENN

VID0-VID6

0.1µF

I

RPTC

CSLEW

SS

6.98k

8.25k

I

MAX

R

22pF

PTC

I

TCFB

V

+ V

EXTVCC

LOSS

IN

470pF

15nF

14k

I

TC

5.1k

10k

I

MON

PREI

I

SERVO

0.01

0.1

1

10

MON

21k

12k

15nF

22pF

LOAD CURRENT (A)

V

FB

V

3816 TA01b

CC(SEN)

SS(SEN)

2.2nF

10pF

COMP

3816 TA01

GND

3816f

ꢀ

LTC3816

absoluTe MaxiMuM raTings ^{(Notes 1, 8)}

Input Supply Voltage (V )......................... –0.3V to 40V

DPRSLPVR, VRTT# .................................. –0.3V to 3.3V

SS(SEN)

IN

Topside Driver Voltage (BOOST)................ –0.3V to 46V

V

, BSOURCE ................................. –0.3V to 0.3V

Switch Voltage (SW)..................................... –5V to 40V

INTV RMS Output Current .................................50mA

CC

INTV , EXTV , (BOOST-SW) .................. –0.3V to 6V

Operating Junction Temperature Range

CC

, PREI

I

, I

, RPTC, VR , V ,

(Note 3).................................................. –40°C to 125°C

Storage Temperature Range .................. –65°C to 125°C

Lead Temperature (Soldering, 10sec)

SENN TCFB

MON MON

ON CC(SEN)

V , SS, VIDn, RFREQ, MODE/SYNC,

FB

LFF, I

, I

.........................–0.3V to INTV + 0.3V

SENP MAX CC

PWRGD, CLKEN# ........................................ –0.3V to 6V

eTSSOP.............................................................300°C

pin conFiguraTion

TOP VIEW

1

2

I

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

I

MAX

SENN

TOP VIEW

I

SENP

TCFB

3

LFF

I

TC

38 37 36 35 34 33 32

4

VRTT#

CLKEN#

PWRGD

SW

PREI

I

MON

PREI

I

1

2

3

4

5

6

7

8

9

31 CLKEN#

30 PWRGD

5

MON

6

RPTC

VR

RPTC

SW

TG

29

28

7

ON

VR

ON

8

TG

V

SS(SEN)

V

27 BOOST

SS(SEN)

9

BOOST

CC(SEN)

SERVO

V

26

CC(SEN)

SERVO

IN

39

GND

10

11

12

13

14

15

16

17

18

19

V

IN

GND

25 EXTV

CC

EXTV

CC

V

FB

V

FB

24 INTV

23 BG

CC

INTV

CC

COMP

SS

COMP

BG

SS 10

22 BSOURCE

BSOURCE

MODE/SYNC

RFREQ

VID6

DPRSLPVR

CSLEW

VID0

DPRSLPVR 11

CSLEW 12

21 MODE/SYNC

20

RFREQ

13 14 15 16 17 18 19

UHF PACKAGE

VID1

VID5

VID2

VID4

VID3

38-LEAD (5mm s 7mm) PLASTIC QFN

= 125°C, θ = 34°C/W

T

JMAX

JA

FE PACKAGE

EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB

38-LEAD PLASTIC eTSSOP

T

= 125°C, θ = 29°C/W

JA

JMAX

EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB

3816f

ꢁ

LTC3816

orDer inForMaTion

LEAD FREE FINISH

LTC3816EFE#PBF

LTC3816IFE#PBF

LTC3816EUHF#PBF

LTC3816IUHF#PBF

TAPE AND REEL

PART MARKING*

LTC3816FE

3816

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

LTC3816EFE#TRPBF

LTC3816IFE#TRPBF

LTC3816EUHF#TRPBF

LTC3816IUHF#TRPBF

38-Lead Plastic eTSSOP

38-Lead (5mm × 7mm) Plastic QFN

3816

Consult LTC Marketing for parts speciﬁed with wider operating junction temperature ranges.

*The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

elecTrical characTerisTics ^Thel denotes the speciﬁcations which apply over the full operating

junction temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 12V, BSOURCE = EXTV_CC= 0V, VR_ON= 5V, unless

otherwise noted. (Notes 2, 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Input and INTV Linear Regulator

CC

l

V

Supply Voltage Range

Supply Current

V

> V

UVLO

4.5

36

V

IN

INTVCC

I

VIN

Normal Mode

Shutdown

= V

, f

= 400kHz (Note 4)

11

27

mA

µA

BOOST

ON

INTVCC OSC

VR = 0V

100

5.5

INTV

Internal V Voltage

4.9

4.25

3.7

5.2

V

%

V

CC

V

Line Regulation

Load Regulation

7.5V < V < 36V

1.0

INTVCC(LINE)

INTVCC(LOAD)

EXTVCC

IN

Load = 0mA to 20mA

–0.25

4.50

0.4

–1.0

4.75

EXTV Switchover Voltage

EXTV Ramping Positive

CC

EXTV Hysteresis

V

EXTVCC(HYS)

EXTVCC(DROP)

UVLO

CC

EXTV Voltage Drop

Load = 20mA, V

= 5V

40

100

4.1

mV

V

CC

EXTVCC

INTV Undervoltage Reset

INTV Ramping Positive

3.9

CC

Undervoltage Hystersis

0.4

V

Switcher Control Loop

l

V

= (V

– V

)

V > 0.75V (Note 5)

CC(CORE)

0.75

6

10

%

mV

CC(CORE)

CC(SEN)

SS(SEN)

0.5V ≤ V

0.3V ≤ V

≤ 0.75V (Note 5)

CC(CORE)

< 0.5V (Note 5)

V

Voltage Line Regulation

V

= 7.5V to 36V (Note 5)

0.002

80

%/V

dB

∆V

CC(CORE)

IN

CC(CORE)

A

EA

Error Ampliﬁer DC Gain

No load

(Note 6)

f

I

Error Ampliﬁer Unity-Gain Bandwidth

20

MHz

BW

Error Ampliﬁer Output Source Current

Error Ampliﬁer Output Sink Current

V

COMP

V

COMP

= 0V

= 5V

–1.5

mA

COMP

5

I

V

Input Current

V

= V

, 0V ≤ V ≤ 1.5V

CC(SEN)

30

–60

0.1

µA

VCC(SEN)

VSS(SEN)

VFB

CC(SEN)

SS(SEN)

ISENN

CC(SEN)

= 0V

SS(SEN)

Input Current

0V ≤ V ≤ 2V

FB

I

Input Current

0V ≤ V

≤ 1.5V

ITCFB

TCFB

ITCFB

3816f

ꢂ

LTC3816

elecTrical characTerisTics ^Thel denotes the speciﬁcations which apply over the full operating

junction temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 12V, BSOURCE = EXTV_CC= 0V, VR_ON= 5V, unless

otherwise noted. (Notes 2, 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Core Supply Start-Up Voltage

V

= INTV (IMVP-6 Conﬁguration)

1.2

1.1

V

BOOT

OVF

IMON

CC

< 1.1V (IMVP-6.5 Conﬁguration)

l

V

Overvoltage Fault Threshold

V

IMON

V

IMON

= INTV (IMVP-6 Conﬁguration)

1.65

1.53

1.7

1.55

V

CC

< 1.1V (IMVP-6.5 Conﬁguration)

I

SS Pull-Up Current

V

= 0V

–1

µA

SS

CSLEW Pull-Up Current

= 0V

CSLEW

IMVP-6 and V

IMVP-6.5 or V

= INTV

= 0V

–10

–40

µA

DPRSLPVR

CC

I

RPTC Source Current

RPTC = 0V

–90

–100

0.47

–110

–11

µA

V

RPTC

V

I

RPTC Thermal Shutdown Threshold

RPTC

l

I

Source Current

MAX

–9

35

–10

–20

µA

V

IMAX

V

IMAX

= 0V, 1× Current Limit Duration

= 0V, 2× Current Limit Duration

MAX

45

630

µs

t

2× Current Limit Duration

2× Current Limit Period

IMAX2×

V

Current Comparator Offset

V

= 1.0V, V

= V

– V

IMAX

3

2

mV

µA

V

ILIM

IMAX

ILIM

ISENP

Reverse-Current Comparator Offset

= 1.0V, V

= V

– V

ISENP ISENN

IREV

ISENN

IREV

I

Input Current

0V ≤ V

≤ 1.5V

1

ISENP

ISENN

SENP

SENN

ISENP

ISENN

20

V

IMVP-6/IMVP-6.5 Selection Threshold

Regulator On Source Current

2.4

–1

IMON

I

VR = 0V

µA

VRON

ON

VR

ON

Regulator On Threshold

Regulator Power-Down Threshold

Rising Edge

Falling Edge

1.18

1.2

0.65

1.22

V

Oscillator and Drivers

f

Oscillator Frequency

RFREQ Floats

375

180

530

400

210

580

425

240

640

kHz

OSC

V

= 0V

RFREQ

= 2.5V

f

Minimum Synchronization Input Frequency

Maximum Synchronization Input Frequency

150

kHz

SYNC

550

–9

V

MODE/SYNC Synchronization Threshold

RFREQ Source Current

1.6

V

SYNC

I

V

RFREQ

= 0V

–10

–11

µA

RFREQ

V

MODE

MODE/SYNC Force Continuous Threshold

V

IMON

V

IMON

= INTV (IMVP-6 Conﬁguration)

1.6

0.5

V

CC

< 1.1V (IMVP-6.5 Conﬁguration)

DC

Maximum TG Duty Cycle

MODE/SYNC = 0, RFREQ Floats

(Note 6)

90

35

%

ns

Ω

MAX

ON(MIN)

DEAD

t

TG Minimum Pulse Width

Driver Dead-Time

30

TG R

BG R

TG Driver Pull-Up On-Resistance

TG Driver Pull-Down On-Resistance

BG Driver Pull-Up On-Resistance

BG Driver Pull-Down On-Resistance

TG High, I

= –100mA (Note 7)

= 100mA (Note 7)

= –100mA (Note 7)

= 100mA (Note 7)

2.6

1.2

2.6

0.9

UP

OUT

TG Low, I

DOWN

UP

OUT

BG High, I

OUT

BG Low, I

DOWN

OUT

3816f

ꢃ

LTC3816

elecTrical characTerisTics ^Thel denotes the speciﬁcations which apply over the full operating

junction temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 12V, BSOURCE = EXTV_CC= 0V, VR_ON= 5V, unless

otherwise noted. (Notes 2, 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

0.3

1

UNITS

VID, DPRSLPVR, LFF Parameters

V

VID Input Low Threshold

VID Input High Threshold

VID Input Leakage Current

DPRSLPVR Input Threshold

LFF Pull-Up Current

V

IL(VID)

IH(VID)

VID

0.7

I

0V ≤ V ≤ 5V

µA

V

VID

V

= INTV (IMVP-6 Conﬁguration)

1.6

–1

1

DPRSLPVR

LFF

IMON

CC

I

LFF

= 0V

LFF

µA

V

LFF Input Threshold

PWRGD, CLKEN#, VRTT#

V

Positive Power Good Threshold

Negative Power Good Threshold

With Respect to VID V

150

–240

175

–270

200

–300

mV

PWRGD

CC(CORE)

I

PWRGD, CLKEN# Leakage Current

VRTT# Leakage Current

V

VRTT#

= V

= 5V

CLKEN#

10

100

µA

LEAK

PWRGD

V

= 3.3V

V

OL

PWRGD, CLKEN# Output Low Voltage

VRTT# Output Low Voltage

I

= 2mA

= 20mA

0.1

0.075

0.3

0.18

V

OUT

t

PWRGD Glitch Filter

Power Good to Power Bad

Rising V Edge to CLKEN#

750

75

µs

PWRGD

l

CLKEN# Falling Edge Delay

50

5

100

20

CLKEN#

BOOT

Falling Edge

t

CLKEN# to PWRGD Rising Edge Delay

10

ms

ns

CLK(PWRGD)

VR(PWRGD)

VR to PWRGD Falling Edge Delay

ON

VR Falling Edge

ON

100

Note 1: Stresses beyond those listed under Absolute Maximum

Ratings may cause permanent damage to the device. Exposure to any

Absolute Maximum Rating condition for extended periods may affect

device reliability and lifetime.

Note 4: The dynamic input supply current is a function of the power

MOSFET gate charging (Q_G• f_OSC). See Applications Information for

more information.

Note 5: The LTC3816 is measured in a feedback loop that adjusts

Note 2: All currents into device pins are positive; all currents out of

device pins are negative. All voltages are referenced to ground unless

otherwise speciﬁed.

V_CC(SEN)– V_SS(SEN)to achieve a speciﬁed COMP pin voltage. The AITC

ampliﬁer is conﬁgured as an inverter with gain = –1.

Note 6: Guaranteed by design, not subject to test.

Note 3: The LTC3816 is tested under pulse load conditions such that

T_J≈ T_A. The LTC3816E is guaranteed to meet performance speciﬁcations

from 0°C to 85°C. Speciﬁcations over the –40°C to 125°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls. LTC3816I speciﬁcations are

guaranteed over the full –40°C to 125°C operating junction temperature

range. Note that the maximum ambient temperature consistent with

these speciﬁcations is determined by speciﬁc operating conditions in

conjunction with board layout, the rated package thermal impedance

Note 7: On-resistance limit is guaranteed by design and correlation

with statistical process controls.

Note 8: The LTC3816 includes overtemperature protection that is

intended to protect the device during momentary overload conditions.

The maximum rated junction temperature will be exceeded when this

protection is active. Continuous operation above the speciﬁed absolute

maximum operating junction temperature may impair device reliability

or permanently damage the device.

and other environmental factors. T is calculated from the ambient

J

temperature, T , and power dissipation, P , according to the following

A

D

formula,

LTC3816EFE: T = T + (P • 29°C/W)

J

A

D

LTC3816EUHF: T = T + (P • 34°C/W)

J

A

D

3816f

ꢄ

LTC3816

Typical perForMance characTerisTics

Efﬁciency vs Load Current

Efﬁciency vs V_CC(CORE)

Efﬁciency vs V_INwith V_EXTVCC= 0V

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V

= 12V, f

CC(CORE)

LAST PAGE CIRCUIT

= 400kHz

V

= 12V, f

= 400kHz, V

= 0V

V

= 0.75V, f

= 400kHz

OSC

IN

OSC

IN

OSC

EXTVCC

CC(CORE)

= 0.75V, V

= 0V

FORCED CONTINOUS MODE

LAST PAGE CIRCUIT

= 0V

EXTVCC

FORCED CONTINOUS MODE

LAST PAGE CIRCUIT

PULSE-SKIPPING

MODE

FORCED CONTINUOUS

MODE

V

= 0.50V

CC(CORE)

V

IN

V

IN

V

IN

= 5V

= 12V

= 24V

V

= 0.75V

= 1.00V

= 1.20V

0.01

0.1

1

10

0.01

0.1

1

10

0.01

0.1

1

10

LOAD CURRENT (A)

3816 G03

3816 G01

3816 G02

Efﬁciency vs f_OSCwith

V_EXTVCC= 0V

Efﬁciency vs f_OSCwith

V_EXTVCC= 5V

Efﬁciency vs V_INwith V_EXTVCC= 5V

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V

= 12V, V

EXTVCC

= 0.75V

V

= 12V, V

EXTVCC

= 0.75V

V

= 0.75V, f

= 400kHz

IN

CC(CORE)

IN

CC(CORE)

EXTVCC

OSC

= 0V

= 5V

FORCED CONTINOUS MODE

LAST PAGE CIRCUIT

FORCED CONTINOUS MODE

LAST PAGE CIRCUIT

FORCED CONTINOUS MODE

LAST PAGE CIRCUIT

f

= 210kHz

= 400kHz

= 580kHz

f

= 210kHz

= 400kHz

= 580kHz

OSC

f

V

IN

V

IN

= 12V

= 24V

OSC

f

OSC

0.01

0.1

1

10

0.01

0.1

1

10

0.01

0.1

1

10

LOAD CURRENT (A)

3816 G05

3816 G06

3816 G04

Load Regulation with

AVP Slope = –3mV/A

V_CC(CORE)vs Temperature

0.755

0.754

0.753

0.752

0.751

0.750

0.749

0.748

0.747

0.746

0.745

10

0

V

= 12V, f

= 400kHz

IN

EXTVCC

OSC

= 0V

AVP SLOPE = –3mV/A

FORCED CONTINOUS MODE

LAST PAGE CIRCUIT

–10

–20

–30

–40

–50

–60

–70

V

= 0.5V

= 1.2V

CC(CORE)

–80

–50

0

25

50

75 100 125

–25

0

4

8

12

28

16

20

24

TEMPERATURE (°C)

LOAD CURRENT (A)

3816 G07

3816 G08

3816f

ꢅ

LTC3816

Typical perForMance characTerisTics

Load Regulation vs Temperature

Line Regulation

0.7520

0

f

= 400kHz, V

= 0V

OSC

EXTVCC

5A LOAD

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

FORCED CONTINUOUS MODE

NO LOAD

0.7515

0.7510

LAST PAGE CIRCUIT

PTC CONFIGURATION (FIGURE 12)

10A LOAD

R

= VISHAY TFPT1206L1002FV

LPTC

VDCRP

= 23.2k, C

= 10nF

0.7505

0.7500

0.7495

0.7490

0.7485

VDCRP

NTC CONFIGURATION,

LAST PAGE CIRCUIT

NO TEMPERATURE COMPENSATION

LAST PAGE CIRCUIT, REPLACE NTC

WITH 10k RESISTOR

20A LOAD

IDEAL VALUE

V

= 12V, f

EXTVCC

L = VISHAY IHLP5050CE01 0.33µH

= 400kHz

OSC

IN

= 0V, AVP = –3mV/A

0.7480

4

8

16

(V)

20

24

28

0

12

V

–50

0

25

50

75 100 125

–25

TEMPERATURE (°C)

IN

3816 G10

3816 G09

Load Step in Forced Continuous

Mode

V_IMONvs Temperature

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

V

= 12V, f

= 400kHz

OSC

IN

= 0V, AVP = –3mV/A

EXTVCC

R

= 5.1k, R

= 21k

PREIMON

IMON

20A LOAD

PTC CONFIGURATION (FIGURE 12)

R

= VISHAY TFPT1206L1002FV

LPTC

VDCRP

V

CC(CORE)

= 23.2k, C

= 10nF

VDCRP

50mV/DIV

NTC CONFIGURATION,

LAST PAGE CIRCUIT

NO TEMPERATURE COMPENSATION

LAST PAGE CIRCUIT, REPLACE NTC

WITH 10k RESISTOR

10A LOAD

5A LOAD

LOAD

CURRENT

20A/DIV

IDEAL VALUE

L = VISHAY IHLP5050CE01 0.33µH

–50 25 75 100 125

50

TEMPERATURE (°C)

3816 G12

V

OSC

= 12V

= 0.75V

= 400kHz

20µs/DIV

0

–25

IN

CC(CORE)

f

3816 G11

FORCED CONTINUOUS MODE

AVP SLOPE = –3mV/A

Narrow TG Pulse Width with Low

V_CC(CORE)Ripple

Pulse-Skipping Mode at No Load

with Low V_CC(CORE)Ripple

Pulse-Skipping Mode

at 0.2A Load

V

CC(CORE)

20mV/DIV

V

CC(CORE)

20mV/DIV

CC(CORE)

20mV/DIV

V

-V

TG SW

2V/DIV

V

BG

5V/DIV

V

-V

TG SW

2V/DIV

V

-V

TG SW

2V/DIV

ZOOM IN

V

-V

TG SW

1V/DIV

V

BG

V

BG

5V/DIV

20ns/DIV

∆t = 24.6ns

5V/DIV

3816 G13

3816 G14

3816 G15

V

OSC

= 28V

20µs/DIV

= 0.5V (I = 0.5A)

V

OSC

= 12V

100µs/DIV

V

OSC

= 12V

5µs/DIV

= 0.75V (I = 0.2A)

IN

CC(CORE)

IN

CC(CORE)

IN

CC(CORE)

= 0.75V, NO LOAD

LOAD

f

= 400kHz

f

= 400kHz

f

= 400kHz

FORCED CONTINUOUS MODE

PULSE-SKIPPING MODE

3816f

ꢆ

LTC3816

Typical perForMance characTerisTics

Start-Up to V_BOOT

V_BOOTto PWRGD Delay

VR_ONShutdown

V

CC(CORE)

V

CC(CORE)

200mV/DIV

CC(CORE)

200mV/DIV

CLKEN#

5V/DIV

CLKEN#

5V/DIV

PWRGD

5V/DIV

CLKEN#

5V/DIV

PWRGD

5V/DIV

PWRGD

5V/DIV

VR

ON

5V/DIV

VR

ON

5V/DIV

3816 G16

3816 G17

3816 G18

V

= 12V

100µs/DIV

IMVP6 CONFIGURATION

= 470pF

V

= 12V

2ms/DIV

IMVP6 CONFIGURATION

C = 470pF

SS

V = 12V

IN

VID = 0.75V

NO LOAD

10µs/DIV

IN

C

SS

VID = 0.75V

NO LOAD

VID = 0.75V

NO LOAD

Momentary Overcurrent,

45µs I_MAXPulse

Momentary Overcurrent,

90µs I_MAXPulse

2x Overcurrent

V

CC(CORE)

100mV/DIV

60µs I

LOAD

20µs I

LOAD

20A/DIV

LOAD

10A/DIV

I

L

10A/DIV

20A/DIV

V

RIMAX

20mV/DIV

3816 G19

3816 G20

3816 G21

V

R

= 12V

10µs/DIV

V

R

= 12V

20µs/DIV

V

R

= 12V

10µs/DIV

IN

CC(CORE)

IN

CC(CORE)

IN

CC(CORE)

= 1V

= 1.5k

= 1mΩ

= 1V

= 1.5k

= 1mΩ

= 1V

= 1.5k

IMAX

= 1mΩ

SENSE

FORCED CONTINUOUS MODE

Current Comparator Offset

vs Common Mode Range

Current Comparator Offset

vs Temperature

Duty Cycle vs V_COMPwith Line

Feedforward

100

90

80

70

60

50

40

30

20

10

0

2.0

1.5

1.0

0.5

V

= 12V

– V

V

= 12V

IN

IMAX

IN

ISENN

= 20mV

ISENN

= 1V

– V

1.5

1.0

= 20mV

IMAX

ISENN

0.5

0

–0.5

–1.0

–1.5

f

= 400kHz

OSC

LFF = FLOAT

–1.0

–1.5

–2.0

V

= 5V

IN

= 12V

= 24V

= 36V

–2.0

0.25

0.5

1

–25

0

50

75 100 125

1.8

(V)

2.4

0

1.25

1.5

–50

25

1.0

1.4 1.6

V

2.0

0.75

1.2

2.2

V

(V)

TEMPERATURE (°C)

COMP

ISENN

3816 G22

3816 G23

3816 G24

3816f

ꢇ

LTC3816

Typical perForMance characTerisTics

Duty Cycle vs V_COMPwithout Line

Feedforward

f_OSCvs Temperature

V_RPTCvs Temperature

100

90

80

70

60

50

40

30

20

10

0

700

600

500

400

480

475

470

465

120

115

110

105

V

= 12V

IN

f

= 400kHz

OSC

LFF = 0V

V

= 2.5V

RFREQ

V

POSITIVE THRESHOLD

NEGATIVE THRESHOLD

RPTC

RFREQ FLOATS

V

RPTC

300

200

100

460

455

450

100

95

V

= 0V

50

RFREQ

25

90

100 125

50

100 125

–50 –25

0

75

–50 –25

0

25

75

1.0

1.4 1.6 1.8

(V)

2.0 2.2 2.4

1.2

V

TEMPERATURE (°C)

COMP

3816 G26

3816 G27

3816 G25

I_IMAX, I_RFREQand I_RPTC

vs Temperature

VR_ONvs Temperature

INTV_CCUVLO vs Temperature

11.50

11.25

11.00

10.75

10.50

10.25

10.00

9.75

105.0

102.5

100.0

97.5

95.0

92.5

90.0

87.5

85.0

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

4.1

4.0

V

= 0V

EXTVCC

VR RAMPS HIGH,

ON

REGULATOR ON THRESHOLD

I

RPTC

V

RAMPS HIGH

IN

VR RAMPS LOW,

ON

REGULATOR OFF THRESHOLD

3.9

3.8

3.7

3.6

3.5

VR RAMPS HIGH,

ON

POWER-UP THRESHOLD

I

, I

RFREQ IMAX

V

RAMPS LOW

IN

VR RAMPS LOW,

ON

POWER-DOWN THRESHOLD

9.50

3.4

0.5

50

TEMPERATURE (°C)

100 125

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

–50 –25

0

25

75

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

3816 G28

3816 G30

3816 G29

INTV_CCLine Regulation

INTV_CCLoad Regulation

INTV_CCDropout vs Temperature

0

–0.2

–0.4

–0.6

–0.8

–1.0

5.4

5.2

0

–10

–20

–30

–40

0

V

= 0V

V

= 0V

V

OSC

= 0V

EXTVCC

f

= 400kHz

f

= 400kHz

OSC

LOAD CURRENT = 20mA

∆INTV = –1%

–300

–600

–900

CC

5.0

4.8

4.6

4.4

4.2

V

= 12V

IN

V

= 5V

IN

4.0

–1200

50

10 15 20 25

40

50

TEMPERATURE (°C)

125

0

5

30 35

0

10

30

40

–50 –25

0

25

75 100

20

V

(V)

I

(mA)

LOAD

IN

3816 G31

3816 G32

3816 G33

3816f

ꢈ

LTC3816

Typical perForMance characTerisTics

EXTV_CCSwitchover Voltage

vs Temperature

EXTV_CCVoltage Drop

vs Temperature

I_VIN

15

14

13

12

11

10

50

40

30

20

10

0

120

100

80

4.8

4.7

4.6

4.5

4.4

4.3

4.2

4.1

4.0

V

OSC

= 0V

V

f

= 5V

EXTVCC

OSC

f

= 400kHz

I

= 50mA

= 20mA

LOAD

EXTV RAMPS HIGH

CC

I

(SHUTDOWN)

VIN

60

I

40

20

0

I

VIN

EXTV RAMPS LOW

CC

NO LOAD

3.9

20

(V)

0

5

10 15

25 30 35 40

50

100 125

–50 –25

0

25

75

–50 –25

0

25

125

50

75 100

V

TEMPERATURE (°C)

IN

3816 G36

3816 G35

3816 G34

I_VIN(Shutdown) vs Temperature

I

_VINand I_EXTVCCvs Temperature

60

50

40

30

15

14

V

= VR = 0V

ON

EXTVCC

V

OSC

= 12V

IN

f

= 400kHz

V

= 40V

IN

13

12

11

10

9

V

= 0V, I

VIN

EXTVCC

V

= 12V

= 5V

IN

V

= 5V, I

EXTVCC

V

20

10

0

IN

8

50

100 125

–50 –25

0

25

75

50

100 125

–50 –25

0

25

75

TEMPERATURE (°C)

3816 G37

3816 G38

V_CC(SEN)and I_SENNInput Current

vs Common Mode Range

V

_SS(SEN)Input Current

20

15

10

5

0

–10

–20

–30

V

= 12V

V

= 12V

IN

= V

ISENN

ITC

CC(SEN)

ITCFB

= 0V

ISENN

ITC

CC(SEN)

ITCFB

= V

SS(SEN)

V

= 0.3V

CC(CORE)

I

VCC(SEN)

V

= 0.9V

= 1.5V

CC(CORE)

I

ISENN

0

–40

–50

–5

–10

0

0.50 0.75 1.00

(V)

1.25 1.50

0.25

–0.3

–0.1

0

0.1

0.2

0.3

–0.2

V

CC(SEN)

V

(V)

SS(SEN)

3816 G39

3816 G40

3816f

ꢀ0

LTC3816

pin FuncTions ^(eTSSOP/QFN)

I

(Pin 1/Pin 36): Current Sense Negative Input. Con-

VR (Pin 7/Pin 4): Voltage Regulator Enable Input. The

ON

SENN

nect this pin to the negative terminal of the current sense

resistor or the negative terminal of the inductor DCR

lowpass ﬁlter.

VR pin power-up threshold is 1.2V. When forced below

ON

0.65V, a power-down sequence is initiated where the

V

output is ramped down near 0V before the IC

CC(CORE)

is put into a low current shutdown mode. The VR pin

ON

I

(Pin 2/Pin 37): Inductor DCR Temperature Compen-

TCFB

has an internal 1µA pull-up current.

sation Amplifer Feedback Input. To derive the temperature

compensated voltage dropped across the inductor DCR,

connect a resistor from the SW node to this pin. An NTC

network, in parallel with a capacitor, forms the feedback

path of this ampliﬁer. For applications that use a discrete

resistor for current sensing, replace the NTC network

with a resistor.

V

(Pin 8/Pin 5): Processor V

Negative

CC(CORE)

SS(SEN)

Terminal Voltage Sense. Negative input of the differential

sense ampliﬁer. Connect to the processor V pin.

SS(SEN)

V

(Pin 9/Pin 6): Processor V

Positive

CC(CORE)

CC(SEN)

Terminal Voltage Sense. Positive input of the differential

sense ampliﬁer. Connect to the processor V pin.

CC(SEN)

I

(Pin 3/Pin 38): Inductor DCR Temperature Compen-

TC

SERVO (Pin 10/Pin 7): Error Ampliﬁer AC Input. The

controller servos the switcher output voltage to the VID

DAC voltage through the error ampliﬁer.

sation Amplifer Output. The I

circuitry and the error

MON

ampliﬁerobtainthetemperaturecompensatedDCRvoltage

through this ampliﬁer.

V

FB

(Pin 11/Pin 8): Error Ampliﬁer Negative Input Pin.

is servoed to 1.3V.

FB

PREI

(Pin 4/Pin 1): I

Current Output Setting.

potential. A resistor from

MON

V

PREI

is servoed to the I

SENN

COMP (Pin 12/Pin 9): Error Ampliﬁer Output. The COMP

pin is connected directly to the error ampliﬁer output and

theinputofthelinefeedforwardcircuit.UseanRCnetwork

PRE

toI setstheI

outputcurrent.FortheIMVP-6

IMON

TC

MON

conﬁguration, connect this pin to INTV .

CC

I

(Pin5/Pin2):IMVP-6/IMVP-6.5ConﬁgurationSelec-

MON

between the COMP pin and the V pin to compensate

FB

tionandOutputCurrentMonitor.ConnectthispintoINTV

CC

the feedback loop for stability and optimum transient

toselecttheIMVP-6conﬁguration.Atstart-up,theswitcher

is ramped to 1.2V (V ). In deeper sleep mode,

response.

V

OUT

BOOT

SS (Pin 13/Pin 10): Soft-Start Input. The SS pin has an

internal1µAcurrentsourcepull-up.Acapacitorconnected

to this pin controls the output voltage start-up. SS is

the controller enables the slow V

slew rate. Connect a

OUT

resistor to V

to select the IMVP-6.5 conﬁguration.

equals 1.1V, slow slew rate is disabled

current source is proportional to the load. In

SS(SEN)

BOOT

MON

In this case, V

forced low if VR or PWRGD is low, or if an overvoltage

and the I

ON

or overcurrent fault occurs. If the potential at SS is less

the IMVP-6.5 conﬁguration, this pin is internally clamped

to 1.1V with respect to the V pin.

than 0.3V, the I

sourcing current is reduced to 2.5µA

MAX

SS(SEN)

and the current limit threshold is reduced to 25% of its

nominal value.

RPTC (Pin 6/Pin 3): Nonlinear PTC Thermistor Input.

Connect to a nonlinear PTC thermistor for MOSFET or

inductortemperaturesensing. Thispinispulledupbya

100µA current source. If the potential at RPTCis higher

than 0.47V, thermal ﬂag VRTT# is pulled low. RPTC is

sensitivetonoisepickup.Avoidcouplinghighfrequency

switching signals to this pin. If required, bypass this

pin with a capacitor to GND.

DPRSLPVR (Pin 14/Pin 11): Deeper Sleep Mode. For the

IMVP-6 conﬁguration, 25µs after DPRSLPVR is asserted

high, the controller enables the V

slow slew rate tran-

OUT

sition. To disable slow slew rate mode, force DPRSLPVR

low. Upon power-up, the DPRSLPVR input is ignored until

PWRGD is asserted.

3816f

ꢀꢀ

LTC3816

pin FuncTions ^(eTSSOP/QFN)

CSLEW (Pin 15/Pin 12): VID DAC Slew Rate Control.

CSLEW is internally pulled up by a current source. Add a

capacitor to program the VID DAC transition slew rate. If

slow slew rate is selected, a 100pF capacitor connected

to CSLEW results in a VID DAC slew rate of 1.25mV/µs.

When slow slew rate is disabled, a 100pF capacitor results

in a VID DAC slew rate of 5mV/µs. Avoid coupling high

frequency switching signals to this pin. For the IMVP-6.5

conﬁguration, the slow slew rate function is disabled.

BSOURCE(Pin25/Pin22):BottomMOSFETSource. Con-

nect this pin to the source of the bottom power MOSFET.

Do not short BSOURCE to the LTC3816 exposed pad

directly.

BG (Pin 26/Pin 23): Bottom Gate Drive. The BG pin drives

the gate of the bottom N-channel synchronous switch

MOSFET.

INTV (Pin 27/Pin 24): Output of the Internal Linear

CC

Low Dropout Regulator. The driver and control circuits

VID0-VID6 (Pins 16-22/Pins 13-19): VID DAC Voltage

Control Logic Inputs. See Table 1.

are powered from this voltage source. The INTV pin

CC

must be decoupled to GND with a minimum 4.7µF low

RFREQ (Pin 23/Pin 20): Frequency Setting. The voltage

on the RFREQ pin determines the free-running operating

frequency. The RFREQ pin has an internal 10µA current

source pull-up allowing the switching frequency to be

programmed by a single external resistor to GND. Alter-

natively, this pin can be driven with a DC voltage source

to control the frequency of the internal oscillator. Floating

ESR ceramic capacitor (X5R or better).

EXTV (Pin 28/Pin 25): External Power Input to an Inter-

CC

nal Switch Connected to INTV . This switch closes and

CC

supplies the IC power, bypassing the internal low dropout

regulator, whenever EXTV is higher than 4.5V. Do not

CC

exceed 6V on this pin.

V (Pin 29/Pin 26): Main Supply Pin. A bypass capacitor

this pin or shorting this pin to INTV allows the controller

IN

CC

should be connected from this pin to the GND pin.

to run at a ﬁxed 400kHz frequency.

BOOST(Pin30/Pin27):TopGateDriverSupply.TheBOOST

pin should be decoupled to the SW node with a 0.1µF low

ESR(X5Rorbetter)ceramiccapacitor.AnexternalSchottky

MODE/SYNC (Pin 24/Pin 21): Mode Select/Synchroniza-

tion Input. This pin is pulled up by an internal 1µA current

source. Floating this pin or shorting it to INTV enables

CC

diode from INTV to BOOST creates a complete ﬂoating

pulse-skipping mode. Shorting this pin to ground con-

ﬁgures forced continuous mode. During frequency syn-

chronization, the phase-locked loop forces the controller

to operate in continuous mode with the falling top gate

signal synchronized to the falling edge of the MODE/SYNC

input pulse. During start-up, the controller is forced to run

in pulse-skipping mode.

CC

charge-pumped supply from BOOST to SW.

TG (Pin 31/Pin 28): Top Gate Drive. The TG pin drives

the top N-channel MOSFET with a voltage swing equal to

INTV superimposed on the switch node voltage.

CC

3816f

ꢀꢁ

LTC3816

pin FuncTions ^(eTSSOP/QFN)

SW (Pin 32/Pin 29): Switching Node. Connect SW to the

source of the upper power MOSFET and to the negative

terminal of the BOOST pin decoupling capacitor.

LFF (Pin 36/Pin 33): Line Feedforward. This pin has a

1µA pull-up current source to INTV . Floating this pin

CC

or connecting it to INTV enables the line feedforward

CC

compensation. Connect this pin to GND to disable the line

PWRGD (Pin 33/Pin 30): Open-Drain Power Good Out-

put/Power Bad Latchoff Input. PWRGD is an open-drain

output pin and can be connected to other open-drain

outputs to implement wire-ORing. PWRGD is externally

pulledhigh10msaftertheoutputregulates. Afterstart-up,

if a fault condition causes PWRGD to go low, or PWRGD

is externally pulled low, the regulator output voltage is

actively ramped to 0V and PWRGD remains latched low

feedforward compensation.

I

(Pin 37/Pin 34): Current Sense Positive Input. Con-

SENP

nect this pin to the positive terminal of the current sense

resistor or to the output of the inductor DCR lowpass

ﬁlter.

I

(Pin 38/Pin 35): Current Comparator Threshold Set-

MAX

ting. The I

pin has an internal 10µA pull-up current

MAX

until either the power is cycled or VR toggles. PWRGD

ON

source, allowing the current limit comparator threshold to

be programmed by a single external resistor. The control-

ler allows a momentary 45µs overcurrent event to occur

within a period of 630µs. See Current Sense and Current

Limit in Applications Information.

has a 750µs de-glitch delay and is masked for 100µs after

the VID code changes. In deeper sleep mode, the PWRGD

comparators are disabled and not allowed to de-assert

the PWRGD pin.

CLKEN#(Pin34/Pin31):Open-DrainClockEnableIndica-

GND (Exposed Pad Pin 39/Exposed Pad Pin 39): Ground.

The soft-start and slew rate control capacitors as well as

the frequency setting and thermal shutdown resistors

should return to this exposed pad ground pin. This GND

pin should also be connected to the negative terminals of

the local voltage regulator output capacitors through vias

to the PCB ground plane.

tor.75µsafterV

reachestheV

voltage,CLKEN#

CC(CORE)

BOOT

pulls low to enable the processor phase-locked loop.

VRTT# (Pin 35/Pin 32): Open-Drain Output for Voltage

Regulator Thermal Throttling. The VRTT# pin pulls low if

the RPTC voltage exceeds 0.47V or if the control IC junc-

tion temperature exceeds 150°C.

3816f

ꢀꢂ

LTC3816

FuncTional DiagraM

3.3V

1.1V

C

INTVCC

1.9k

56Ω

PWRGD

CLKEN#

EN CLK

VRTT#

DPRSLPVR

LFF

EXTV

INTV

CC

V

IN

V

IN

+

–

+

C

IN

LDO

100µA

PWRGD

4.7V

RPTC

+

–

+

TSD

VID0-VID6

BANDGAP

CHIP TSD

INTV

CC

0.47V

PTC

0.5V/1.6V

–

INTV

CC

D

B

10µA/40µA

BOOST

TG

DAC

1µA

C

B

CSLEW

Q

T

C

SLEW

L

SW

INTV

CC

SAW

V

OUT

+

–

+

INTV

CC

LOGIC

PWM

C

D

B

OUT

BG

LFF

NTC

1µA

V

IN

MODE/SYNC

RFREQ

EN CLK

BSOURCE

10µA

INTV

DELAY

AND

LATCH

CC

POWER

DOWN

PWRGD

–

OVP

–

+

I

LIM

+

OVF

+

I

REV

10µA

R

FREQ

R

IDCR

I

SENP

DAC

+ 25mV

1.65V/1.53V

IMVP-6

R

IMAX

C

IDCR

I

MAX

I

SENN

1µA

R

VR

ON

AVPDCRN

ON

+

–

+

I

AITC

TCFB

+

V

AVP

R

PAR

SER

–

+

NPG

PPG

1x

1.2V

INTV

–

I

C

VDCR

INTV

TC

2.4V

CC

R

PREIMON

PREI

I

MON

DAC + 0.175V

DAC – 0.270V

1µA

MON

SS

I

MON

C

IMON

DA OUT

DAC – V

OC FAULT

OV FAULT

R

IMON

C

SS

AVP

V

1.3V

–

+

SS(SEN)

CC(SEN)

+

–

EA

V

DAMP

GND

V

COMP

SERVO

FB

C

R

R1

C

C1

C

FF

Figure 1. Functional Diagram

3816f

ꢀꢃ

LTC3816

operaTion ^{(Refer to Funtional Diagram)}

Table 1. IMVP-6/IMVP-6.5 VID Output Voltage Programming

VID6 VID5 VID4 VID3 VID2 VID1 VID0

V

VID6 VID5 VID4 VID3 VID2 VID1 VID0

V

CC(CORE)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.5000

1.4875

1.4750

1.4625

1.4500

1.4375

1.4250

1.4125

1.4000

1.3875

1.3750

1.3625

1.3500

1.3375

1.3250

1.3125

1.3000

1.2875

1.2750

1.2625

1.2500

1.2375

1.2250

1.2125

1.2000

1.1875

1.1750

1.1625

1.1500

1.1375

1.1250

1.1125

1.1000

1.0875

1.0750

1.0625

1.0500

1.0375

1.0250

1.0125

1.0000

0.9875

0.9750

0.9625

0.9500

0.9375

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

0.7500

0.7375

0.7250

0.7125

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

0.3625

0.3500

0.3375

0.3250

0.3125

0.3000

0.2875

0.2750

0.2625

0.2500

0.2375

0.2250

0.2125

0.2000

0.1875

0.1750

0.1625

0.1500

0.1375

0.1250

0.1125

0.1000

0.0875

0.0750

0.0625

0.0500

0.0375

0.0250

0.0125

0.0000

3816f

ꢀꢄ

LTC3816

operaTion ^{(Refer to Funtional Diagram)}

TheLTC3816isaconstantfrequency,voltagemodeDC/DC

step-down controller that complies with the Intel IMVP-6/

IMVP-6.5 speciﬁcations. The 7-bit VID code programs the

switcher output voltage as speciﬁed in Table 1. Figure 2

shows the timing diagram. Upon start-up, the switcher

V

and V

pins. The AITC ampliﬁer monitors

CC(SEN)

SS(SEN)

the inductor current and computes the load dependent

output droop required to implement the active voltage

positioning features in IMVP-6/IMVP-6.5. The IC servos

the differential output voltage to the VID DAC voltage

minus the small load dependent AVP droop.

output soft-start ramps to the V

voltage. 75µs after

BOOT

reaching the V

power good threshold, which is about

, the controller forces the CLKEN# pin

BOOT

The LTC3816 feedback loop is capable of dynamically

changingtheregulatoroutputtodifferentVIDDACvoltages.

Upon receiving a new VID code, the LTC3816 regulates to

its new potential with a programmable slew rate which is

selected to prevent the converter from generating audible

noise. The switcher output load current can be monitored

45mV below V

BOOT

lowandtheVIDcodeisloaded. Next, theoutputisservoed

to its VID DAC potential. 10ms after regulation, PWRGD

pulls high to indicate that the switcher is regulating and

has completed its start-up phase.

The LTC3816 uses two external synchronous N-channel

MOSFETs. A ﬂoating topside driver and a simple external

charge pump provide full gate drive to the upper MOSFET.

The controller uses a leading edge modulation architec-

ture to allow extremely low duty cycles and fast load

step response. In a typical LTC3816 switching cycle, the

PWM comparator turns on the top MOSFET to charge the

output capacitor. An internal clock resets the top MOSFET

and turns on the bottom MOSFET to reduce the output

charging current. This switching cycle repeats itself at an

internally ﬁxed frequency, or in synchronization with an

external oscillator.

by measuring the I

pin potential. The LTC3816 forces

MON

the I

pin voltage to be proportional to the average

MON

load current with a gain conﬁgured by the R

and

PREIMON

R

resistors.

IMON

The LTC3816 includes an onboard current limit circuit that

senses the inductor current through an external sense

resistor or the inductor DCR. The peak inductor current

can be controlled by selecting the current limit R

IMAX

resistance. The LTC3816 current limit architecture allows

momentary overcurrent events for a predeﬁned duration

(see the Current Sense and Current Limit sections). Upon

current limit, the top gate is shut off, the SS external

capacitor is discharged to limit the top gate duty cycle,

and the switcher output voltage is reduced until the load

fault is removed.

The top gate duty cycle is controlled by the voltage feed-

back loop which includes an internal differential ampliﬁer

that senses the differential output voltage between the

VR

ON

VID

DPRSLPVR

INTV

NORMAL

SLEW RATE

CC

IMVP-6

SLOW SLEW RATE

45mV

V

BOOT

V

CC(CORE)

t

CLKEN#

t

PWRGD

CLK(PWRGD)

3816 F02

Figure 2. LTC3816 Power-Up and Power-Down Timing Diagram

3816f

ꢀꢅ

LTC3816

applicaTions inForMaTion

LDO, INTV /EXTV POWER SUPPLY

advisable to short EXTV to V . In this case, the INTV

CC

IN

CC

output voltage becomes:

The LTC3816 is designed to operate with a wide range of

V input voltages. The IC includes a 5.2V LDO to power

V

= V

– I

• R

Q(TOT) EXTVCC

IN

INTVCC(EXTVCC)

EXTVCC

the driver and control circuits. The LDO output, INTV

CC

whereR

istheinternalEXTV switchon-resistance.

CC

EXTVCC

should be bypassed with a minimum 4.7µF low ESR

ceramic capacitor. The INTV regulator can supply up to

It has a typical value of 2Ω at 25°C and has a temperature

coefﬁcient of approximately 4000ppm/°C.

CC

50mA of total LTC3816 quiescent current, I

consists of the static supply current, I , and the current

required to charge the gate capacitance, Q

top and bottom power MOSFETs.

, which

Q(TOT)

Q

UNDERVOLTAGE LOCKOUT AND SHUTDOWN

, of the

G(TOT)

A precision undervoltage lockout (UVLO) comparator

monitors the INTV voltage and enables soft-start opera-

CC

I

= I + Q • f

G(TOT) OSC

Q(TOT)

Q

tion once INTV is above 3.9V. For power supplies that

CC

P

DISS

= V • (I + Q

• f

)

IN

Q

G(TOT) OSC

start-up slowly, the gate drivers could begin switching

when V is well below its steady-state value. The high

T = T + P

• θ

JA

IN

J

A

DISS

inrush current through the input power cable could cause

The value of Q

can be obtained from the MOSFET

IN

G(TOT)

the V supply to dip below the UVLO threshold and result

IN

data sheets. For high V and high frequency operation,

in hiccup operation at start-up. This problem can be eas-

care must be taken to ensure that the maximum junction

ily overcome by adding a V UVLO function as shown in

IN

temperature T

of the IC is never exceeded.

JMAX

Figure 3. Connect an external resistive divider from V to

IN

When the EXTV pin is left open or tied to a voltage less

VR . Set the resistive divider according to the following

CC

ON

than 4.5V, the 5.2V LDO powers INTV . If EXTV is taken

equation:

CC

above 4.5V, the LDO is turned off and an internal switch

connects INTV to EXTV . Do not apply greater than 6V

R_ON1

V_UVLO=1.2V = V

CC

IN(UVLO)

R

+R_ON2

ON1

to the EXTV pin, and ensure that EXTV < V + 0.3V

CC

IN

unless EXTV is shorted to the V supply. Using the

CC

IN

where V

is the desired V UVLO threshold. The

IN

IN(UVLO)

EXTV pin allows INTV to be powered from an external

CC

resistances are normally chosen so that the error caused

by the internal 1µA pull-up current has a negligible effect

ontheUVLOthreshold.Becarefulnottoallowtheresistive

divider output voltage to exceed the 6V maximum rating

source reducing LDO losses and improving the regulator

efﬁciency, especially at high V . When the EXTV pin is

IN

CC

used, the chip power dissipation reduces to:

P

DISS

= V

• (I + Q

• f

)

of the VR pin.

EXTVCC

Q

G(TOT) OSC

ON

If the V supply is low enough for the INTV LDO to enter

If the external resistive divider is not used, upon power-

IN

CC

dropout, the output voltage of the LDO becomes:

up, the VR pin is pulled up by an internal 1µA pull-up

ON

current. The LTC3816 can be put into a low power shut-

V

= V – V

INTVCC(DROPOUT)

IN

DROPOUT

V

IN

The LDO dropout voltage is a function of the total quies-

centcurrentI , V voltageandjunctiontemperature.

LTC3816

ON

1µA

+

–

Q(TOT) IN

R

ON2

VR

ON

The temperature coefﬁcient of the LDO dropout voltage

is approximately 6400ppm/°C. To enable proper opera-

tion, make sure that the LDO output voltage meets the

SHUTDOWN

R

ON1

1.2V

3816 F03

INTV undervoltage and minimum MOSFET gate driver

CC

Figure 3. V_INUVLO Circuit

requirements. If V is connected to a ﬁxed 5V supply, it is

IN

3816f

ꢀꢆ

LTC3816

applicaTions inForMaTion

down mode by pulling the VR pin below 0.65V. In the

pin to GND. An internal 1µA current source charges this

capacitor, creating a voltage ramp on the SS pin. As the

SS pin voltage rises from 0V to 1.3V, the output voltage,

ON

shutdown mode, the internal circuitry and the INTV

CC

regulator are off and the supply current drops well below

100µA. When the VR pin voltage is between 0.65V and

V

, rises smoothly from 0V to its V

value. Once

ON

OUT

BOOT

1.2V, the INTV regulator and internal circuitry power up

the soft-start interval is over, the internal current source

continues charging the SS capacitor until the SS poten-

tial is internally clamped at about 2.7V. For the IMVP-6

conﬁguration, a 1000pF SS capacitor generates roughly

a 1.6ms start-up time. With the IMVP-6.5 conﬁguration,

the start-up time is about 1.5ms.

CC

but the driver outputs remain low.

TOPSIDE MOSFET DRIVER SUPPLY

An external bootstrap capacitor, C , connected from the

B

BOOST pin to the SW pin supplies the topside gate driver

Duringsevereoverloadconditions,theLTC3816discharges

theSScapacitortolowertheswitcheroutputvoltage.Ifthe

potential at SS is forced below 0.3V, the controller reduces

as shown in Figure 1. Capacitor C is charged though the

B

external diode, D , from INTV when the SW pin is low.

B

CC

When the topside MOSFET is turned on, the top driver

its I

sourcing current from 10µA to 2.5µA and cuts the

MAX

places the C voltage across the gate source of the top

B

short-circuit current to about 25% of its nominal value.

MOSFET. This enhances the MOSFET and turns on the

top switch. The switch node voltage, SW, rises to V and

IN

the BOOST pin follows. With the topside MOSFET on, the

CURRENT SENSE AND CURRENT LIMIT

boost voltage is above the input supply:

The LTC3816 features an onboard cycle-by-cycle user-

programmable current limit circuit that controls the peak

V

= V + V

IN INTVCC

BOOST

inductor current. The I

pin has an internal 10µA pull-

MAX

The value of the boost capacitor, C , needs to be at least

B

up current source, allowing the maximum load current

to be programmed by a single external resistor

100 times that of the total input capacitance of the topside

I

LOAD(MAX)

MOSFET. The reverse breakdown of the external Schottky

R

IMAX

connected between the I

and I

pins.

MAX

SENN

diode, D , must be greater than V

.

B

IN(MAX)

I

_IMAX•R_IMAX

I_L(PEAK)

=

R_SENSE

IMVP-6/IMVP-6.5 SELECTION AND V

VOLTAGE

BOOT

∆I_L

2

I

_IMAX•R_IMAX∆I_L

The LTC3816 can be conﬁgured to meet either IMVP-6

or IMVP-6.5 requirements. To select IMVP-6 operation,

I_LOAD(MAX)<I_LIMIT=I_L(PEAK)

–

=

–

R_SENSE

2

shortbothI

andPREI

toINTV . Atstart-up, when

MON

MON CC

whereI

isthepeakinductorcurrent,I

istheI

L(PEAK)

IMAX

MAX

VR is asserted, the switcher output ramps to V

=

BOOT

ON

pin pull-up current, R

is the current sense resistor

SENSE

1.2V regardless of the VID code. To conﬁgure IMVP-6.5

value and ∆I is the inductor ripple current.

L

operation, connect a resistor from I

to V

and

MON

SS(SEN)

another resistor from PREI

to I . The I

MON

TC

MON





V_OUT

1

∆I_L=

V_OUT1–

PREI

resistance set the I

gain (see the I

sec-







MON

f

_OSC•L

V



IN

tion). The V

voltage for IMVP-6.5 is 1.1V.

BOOT

Note that the output ripple current varies with the switch-

ing frequency, inductor value and duty cycle. Hence, the

current limit value should be checked on the application

LOAD(MAX) LIMIT

conditions and temperature variations.

SOFT-START OPERATION

The start-up of V is controlled by the LTC3816’s SS

OUT

boardtoensurethatI

<I

underalloperating

pin. When the voltage at the SS pin is less than 1.3V, the

LTC3816 regulates the V voltage to the SS pin voltage

FB

instead of 1.3V. This allows the user to program the soft-

For current sensing using a low value sense resistor, the

sense resistor parasitic inductance must be considered to

start of the regulator output with a capacitor from the SS

3816f

ꢀꢇ

LTC3816

applicaTions inForMaTion

achieve accurate current sensing. Figure 4 shows a real

V

IN

I

L

LTC3816

TG

current sensing resistor, R

, which can be modeled

SENSE

Q

T

ESL

R

SEN

L

with an ideal resistance, R , in series with its parasitic

SEN

V

SW

BG

OUT

SENSE RESISTOR

ESL. As shown in Figure 4, the voltage across the sense

resistor includes the voltage across the parasitic induc-

tor which is a strong function of inductor ripple current

and the switching frequency. This effectively reduces the

current limit threshold, typically by more than 30%. The

voltage across the sense resistor can be extracted from

a lowpass ﬁlter placed close to the controller input sense

pins as shown in Figure 4. The voltage across the sensing

Q

D

+

B

C

OUT

BSOURCE

R

ISR

I

SENP

C

V

ISR

I

SENN

R

IMAX

I

MAX

V

= V

+ V

ISR

RSEN ESL

capacitor, C , is:

ISR

V

ESL(ON)

V

= I • R

L SEN

RSEN

sESL

R_SEN

1+sR_ISR•C









1+



V_CISR=I_L•R_SEN

_ISR









V

ESL(OFF)

3816 F04

In the frequency domain, the second term in the above

equation must be equal to 1 to ensure that the voltage

across the ﬁlter capacitor is independent of operating

frequency. To meet this requirement, the value of the RC

ﬁlter should fulﬁll the following condition:

Figure 4. Current Limit Sensing Using

a Low Value Sense Resistor

V

IN

I

L

LTC3816

TG

Q

T

ESL

L

DCR

R_ISR•C_ISR

=

V

SW

BG

OUT

R_SEN

INDUCTOR

Q

B

D

+

C

OUT

BSOURCE

The ESL value can be obtained from the manufacturer’s

data sheet or estimated with an oscilloscope, as shown in

the Figure 4 waveform, using the following equation:

R

IDCR

I

SENP

C

IDCR

3916 F05

I

SENN

R

IMAX

I

MAX

V_ESL(ON)+ V_ESL(OFF)

ESL =







1

_OFF

Figure 5. Current Limit Sensing Using Inductor DCR

∆I_L

+



t



ON

datasheet.Similartothesenseresistorapplicationcircuit,

thevoltageacrosstheinductorDCRcanbeextractedfrom

a lowpass ﬁlter and the current limit threshold is given by

the following equation:

where t is the TG on time and t is the TG off time.

ON

OFF

Forhighefﬁciencyapplications,theinductorDCRprovides

amethodofsensingtheinductorcurrentwithoutincurring

additional power loss from a sense resistor. The DCR of

the inductor represents the small amount of resistance

in the copper winding, which can be less than 1mΩ for

today’s low value, high current inductors. Figure 5 shows

asimpliﬁedinductormodel,whichcanbemodeledwithan

ideal inductor, L, in series with its parasitic DCR. The DCR

value can be obtained from the inductor manufacturer’s

I

_IMAX•R_IMAX

I_L(PEAK)

=

R_DCR

∆I_L

2

I_IMAX•R_IMAX∆I_L

I_LOAD(MAX)<I_LIMIT=I_L(PEAK)

–

=

–

R_DCR

2

L

R_DCR

if R_IDCR•C_IDCR

=

3816f

ꢀꢈ

LTC3816

applicaTions inForMaTion

NotethatthevalueofR

mustaccountforitstemperature

anothercycle.After90µs,theI

currentreturnsto10µA,

MAX

DCR

coefﬁcient, which is approximately 0.39%/°C.

and the output load is limited to 1× for the next 630µs as

shown in Figure 6c. Figure 6d shows the condition when

a repetitive overload event triggers current limit.

The current limit architecture of the LTC3816 allows short

durations of instantaneous overload. Upon power-up, the

current limit threshold is set to 1×, equal to I

. The

Figure 6e shows that at any instant, if the load current

is above 1× for more than 90µs, or higher than 2×, the

controllerenterscurrentlimit.Underthiscondition,theTG

duty cycle is reduced and the SS capacitor is discharged

LIMIT

load is limited to I

until the switcher output reaches

LIMIT

its V

potential. Beyond this point, during the VID DAC

slewing interval, the I

BOOT

sourcing current automatically

MAX

switchesfrom10µAto20µAandthecurrentlimitthreshold

increases to 2× to enable the output capacitor voltage to

track the DAC transition. If the controller detects that there

is an overload condition when the DAC is not slewing, the

current limit threshold increases to 2× for a duration of

45µs. If the overload interval is shorter than 45µs, the IC

allows another overcurrent event within the next 630µs,

as shown in Figure 6a. However, if an overload occurs

withinthe630µsfollowingthesecondevent,thecontroller

current limits, as shown in Figure 6b.

CURRENT LIMITED

20µA

I

IMAX

10µA

90µs

45µs

2s

1s

I

LOAD

<45µs

45µs < t < 90µs

3816 F06c

>630µs

Figure 6c. Allowable Longer Overload Condition

If the overload condition persists for more than 45µs,

the LTC3816 allows the 2× current limit to continue for

CURRENT LIMITED

20µA

CURRENT LIMITED

20µA

I

IMAX

10µA

I

IMAX

90µs

10µA

2s

1s

45µs

2s

1s

I

LOAD

<45µs

45µs < t < 90µs

I

LOAD

3816 F06d

<630µs

<45µs

>630µs

3816 F06a

Figure 6d. Allowable Longer Overload Condition,

<630µs

Followed by Repeated Overload Triggers Current Limit

Figure 6a. Permissible Overload

CURRENT LIMITED

20µA

CURRENT LIMITED

20µA

I

IMAX

I

10µA

IMAX

10µA

90µs

45µs

2s

1s

2s

1s

I

LOAD

I

LOAD

>90µs

>630µs

<45µs

3816 F06e

3816 F06b

<630µs

Figure 6e. Long Overload or Excessive Loading

Triggers Current Limit Condition

Figure 6b. Repeated Overload Triggers Current Limit

3816f

ꢁ0

LTC3816

applicaTions inForMaTion

1.03

1.00

0.97

0.94

3

to lower the regulator output voltage. This current limit

condition persists until the fault condition disappears or

the controller detects a low output voltage fault and forces

the switcher output to latch off. Once the output voltage

is lower than the power good threshold, the controller

limits the maximum load to 1× to reduce the short-circuit

current.

0

PROGRAMMABLE

AVP SLOPE

–3

–6

–9

0.91

0.88

ACTIVE VOLTAGE POSITIONING (AVP)

–12

30

0

10

15

20

25

In a conventional buck converter, the feedback control

regulates the output voltage to the same level for the

entire load range as shown in Figure 7a. The peak-to-peak

output voltage spikes resulting from the load step must

be smaller than the voltage tolerance window.

5

I

(A)

LOAD

3816 F07b

Figure 7b. AVP DC Transfer Curve

To reduce the regulator output voltage peak-to-peak

perturbation resulting from a load transient, the LTC3816

modulates the output voltage based on the output loading

current. The built-in AVP circuit lowers the output voltage

proportional to the load current as shown in Figure 7b.

Figure 7c shows the transient response with the AVP

function.TheAVPvoltagedroopreducesthepeak-to-peak

output voltage perturbation. As a result, the AVP topology

requiresfewercapacitorsattheregulatoroutputtoachieve

the same voltage tolerance window.

V

OUT

50mV/DIV

I

LOAD

10A/DIV

V

SW

20V/DIV

3816 F07c

V

= 12V

20µs/DIV

IN

= 1V

OUT

LOAD

I

= 0A TO 20A

The AVP circuit obtains the load current information from

thesenseresistorortheinductorDCRasshowninFigure 8.

The voltage drop across the sense resistor is extracted

Figure 7c. Transient Waveform with AVP Slope = –3mV/A, Using

The Same Inductor and Output Capacitor as Figure 7a. The

Transient Peak-to-Peak Perturbation is Reduced to About 85mV

by the AITC ampliﬁer and summed with the differential

ampliﬁer output voltage. The resulting output is servoed

to the VID DAC voltage. At higher load current, the volt-

age drop across the sense resistor increases, resulting

in a lower switcher output voltage. Typically, the system

requirement deﬁnes the amount of AVP gain ensuring

that the output voltage remains within the regulator sup-

ply tolerance band over the full range of load conditions.

Figure8includesthecomponentsrequiredtocompensate

for the sense resistor parasitic inductance. The AVP DC

transfer function is:

V

OUT

50mV/DIV

I

LOAD

10A/DIV

V

SW

20V/DIV

3816 F07a

20µs/DIV

V

= 12V

IN

= 1V

OUT

LOAD

I

= 0A TO 20A

V

OUT

= V

– A

• I = V

L

– A

• I • R

G(SR) L SEN

DAC

AVP(SR)

DAC

Figure 7a. Transient Waveform Without AVP. The Transient

Peak-to-Peak Spike ≈ 130mV. The AITC Ampliﬁer is

Conﬁgured as a Unity-Gain Ampliﬁer

3816f

ꢁꢀ

LTC3816

applicaTions inForMaTion

V

IN

where A

is the AVP gain with sense resistor con-

G(SR)

AVP(SR)

ﬁguration and A

I

L

is the sense resistor gain:

Q

TG

SW

BG

T

L

ESL

R

SEN

V

R_VSR

R_AVPSR

OUT

SENSE RESISTOR

A_AVP(SR)= A_G(SR)•R_SENand A_G(SR)

=

t

Q

D

+

B

C

OUT

LTC3816

R

AVPSR

BSOURCE

ESL

R_SEN

R

_VSR•C_VSR=

I

TCFB

C

R

VSR

–

I

TC

AITC

+

I

SENN

3916 F08

Figure 9 shows the AVP conﬁguration with current sense

implementedusingtheinductorDCR.TheAVPDCtransfer

function is:

Figure 8. AVP Conﬁguration with a Sense Resistor

V

OUT

=V

–A

•I =V

L

–A

•I •R

G(DCR) L DCR

DAC

AVP(DCR)

DAC

where:

V

IN

I

L

R_VDCR

R_AVPDCR

Q

TG

SW

BG

T

L

DCR

A_AVP(DCR)= A_G(DCR)•R_DCRand A_G(DCR)

=

V

OUT

INDUCTOR

Q

B

D

+

L

C

OUT

LTC3816

R

AVPDCR

R_VDCR•C_VDCR

=

BSOURCE

R_DCR

I

TCFB

C

VDCR

–

I

TC

AITC

+

TEMPERATURE COMPENSATED ACTIVE VOLTAGE

POSITIONING (AVP) WITH INDUCTOR DCR

I

SENN

3916 F09

TheinductorDCRAVPconﬁgurationimprovestheregula-

tor efﬁciency by eliminating the power losses associated

withasenseresistor.However,withoutpropertemperature

compensation, the positive temperature coefﬁcient of the

inductorDCR,0.39%/°C,maycompromisetheoutputvolt-

age accuracy. As the temperature of the inductor rises, its

DCRvalueincreases,resultinginagreaterV_OUTdrooprate

(higherAVPgain).TocompensatefortheDCRtemperature

shift, replace the resistor R_VDCRin Figure 9 with an NTC

resistorplacedascloseaspossibletotheinductor.Ideally,

theNTCresistorshouldhavethesametemperatureasthe

inductor. As temperature increases, the NTC resistance

drops,resultinginareductionintheAITCampliﬁervoltage

gain.ThiscompensatesfortheincreaseinDCRresistance

and maintains the AVP gain. The NTC resistor, however, is

highly nonlinear and must be linearized. Figure 10 shows

Figure 9. AVP Conﬁguration with Inductor DCR Current Sense

V

IN

I

L

Q

TG

SW

BG

T

L

DCR

V

OUT

INDUCTOR

NTC

Q

B

D

+

R

C

OUT

AVPDCRN

LTC3816

BSOURCE

R

PAR

I

TCFB

C

VDCRN

SER

–

I

TC

AITC

+

I

SENN

3916 F10

Figure 10. AVP with Inductor DCR Current Sense

and NTC Temperature Compensation

3816f

ꢁꢁ

LTC3816

applicaTions inForMaTion

1.02

1.01

1.00

0.99

theNTCcompensationnetwork.Todeterminethecompo-

nent values, ﬁrst, select the NTC with room temperature

resistance approximately equal to R_VDCRthat has the

smallest temperature coefﬁcient (β constant in the NTC

data sheet. Using an NTC with a higher β constant gen-

erates a less optimal temperature compensation). Next,

calculatetheresistancesR_PARandR_SERfromthefollowing

equationswheretheNTCresistancesatdifferenttempera-

tures is obtained from the manufacturer’s data sheet.

T

= 25°C

A

IDEAL + 1.5%

IDEAL

0.98

0.97

IDEAL – 1.5%

WITH NTC

0.96

0.95

0.94

WITHOUT NTC

R_PAR=R_NTCat 25°C

5

10

20

0

25

30

15

I

(A)

10

3

LOAD





R_SER

≈

R

|| R

at 0°C – R || R

at 75°C

(

)

(

)

(

) (

)

3816 F11a

PAR

NTC

PAR

NTC





Figure 11a. AVP Transfer Curve Using Vishay

IHLP-5050CE-01 0.33µH (DCR = 1.3mΩ) Inductor

DCR Current Sense with A_G(DCRN)= 1 at T_A= 25°C

– R || R

(

at 25°C

(

)

PAR

NTC

Note that the above equations optimize temperature

compensation at hot. At extreme cold temperature, the

temperature compensation is less effective.

1.02

T

= 125°C

A

1.01

1.00

0.99

With the NTC resistor network, the temperature compen-

sated AVP transfer function becomes:

IDEAL + 1.5%

IDEAL

0.98

0.97

V

OUT

=V

–A

•I =V

–A •I •R

G(DCRN) L DCR

DAC

AVP(DCRN)

L

DAC

IDEAL – 1.5%

where A

and A

are the AVP and DCR gain

AVP(DCRN)

G(DCRN)

0.96

0.95

0.94

usingtheinductorDCRcurrentsensewithNTCtemperature

compensation conﬁguration.

WITH NTC

WITHOUT NTC

5

10

20

0

25

30

15

R_NTCNET

R_AVPDCRN

A_AVP(DCRN)= A_G(DCRN)•R_DCRand A_G(DCRN)

=

I

(A)

LOAD

3816 F11b

L

Figure 11b. Same Setup as Figure 11a. Improvement

in AVP Accuracy with NTC Temperature Compensation

Network at T_A= 125°C

C_VDCRN

=

R_NTCNET•R_DCR





R_NTCNET= R_SER+ R_PAR||R_NTC

(

)





V

IN

I

L

Figure 11a shows the room temperature AVP DC transfer

curvesobtainedusinginductorDCRcurrentsensewithand

without NTC temperature compensation. There is only a

slight difference in the transfer curve at heavy load. Figure

11b shows the AVP transfer curve obtained at 125°C, it

shows the improvement in AVP accuracy with the NTC

resistor network.

Q

TG

SW

BG

T

L

DCR

V

OUT

INDUCTOR

LPTC

Q

B

D

+

C

OUT

LTC3816

BSOURCE

I

TCFB

C

R

VDCRP

–

I

TC

AITC

+

Figure 12 shows another easy way to compensate for the

inductor DCR temperature coefﬁcient. In this conﬁgura-

tion, a linear PTC resistor is connected from the SW node

I

SENN

3916 F12

LPTC: VISHAY TPFT1206 SERIES, 4110ppm/°C

Figure 12. AVP Using Inductor DCR Current Sense

with Linear PTC Temperature Compensation

to the I

pin. The PTC thermistor’s temperature coef-

TCFB

ﬁcient of 0.411%/°C compensates for the change in DCR

3816f

ꢁꢂ

LTC3816

applicaTions inForMaTion

resistance (0.39%/°C) and produces a near perfect AVP

slope across temperature.

the negative terminal of the resistor R

should be

IMON

connected directly to the CPU V

pin. Depending

SS(SEN)

on the output load requirements, the I

voltage gain

MON

V

=V

–A

•I =V

L

–A •I •R

G(DCRP) L DCR

OUT

DAC

AVP(DCRP)

DAC

can be programmed by changing the ratio of the R

IMON

where:

and R

resistances. A capacitor should be added

PREIMON

in parallel with the resistor R

R_VDCRP

R_LPTC

to remove the switching

IMON

A_AVP(DCRP)= A_G(DCRP)•R_DCRand A_G(DCRP)

=

ripple. The value of the capacitor C

the following equation:

is determined by

IMON

L

C_VDCRP

=

t_IMON

R_IMON

R_VDCRP•R_DCR

C_IMON

=

I

MON

where t

is the I

time constant and must be larger

MON

IMON

than300µs.

TofacilitateCPUmonitoringofloadcurrentinanIMVP-6.5

application, the LTC3816 forces the I pin voltage to

MON

be proportional to the average load current. As shown in

In the IMVP-6.5 conﬁguration, the I

internally clamped to 1.1V with respect to the V

voltage. ForcingthePREI

LTC3816 as an IMVP-6 regulator.

pin potential is

MON

Figure 13, the AITC and the unity-gain ampliﬁers force

SS(SEN)

the voltage across the resistor R

to be equal to

pintoINTV conﬁguresthe

PREIMON

MON

CC

the voltage drop across the sense resistor. A current is

supplied to R that is three times greater than the cur-

IMON

rent in R

. The voltage across the R

PREIMON

resistor

IMON

FEEDBACK CONTROL

is equal to:

= 3• I •R

SEN

The LTC3816 feedback loop consists of the line feed-

forward circuit, the modulator, the external inductor, the

output capacitor, the AITC and differential ampliﬁer, and

the feedback ampliﬁer with its compensation network. All

of these components affect loop behavior and need to be

accounted for in the loop compensation.

R_VSR

R_IMON

V

•

(

)

R_AVPSRR_PREIMON

IMON

L

To prevent the ground difference between the CPU and

the regulator from affecting the I voltage accuracy,

MON

Line Feedforward and Modulator

V

IN

I

L

The modulator consists of the PWM generator, the output

MOSFET drivers and the external MOSFETs themselves.

The modulator gain varies linearly with the input voltage.

Thelinefeedforwardcircuitcompensatesforthischangein

gain and provides a constant gain from the error ampliﬁer

output to the SW node regardless of input voltage. From

a feedback loop point of view, the combination of the line

feedforward circuit and the modulator looks like a linear

voltage transfer function from COMP to the SW node and

has a gain roughly equal to:

Q

TG

SW

BG

T

ESL

R

SEN

L

V

OUT

SENSE RESISTOR

Q

B

D

+

LTC3816

C

R

OUT

AVPSR

BSOURCE

I

TCFB

C

R

VSR

I

TC

–

AITC

+

I

INTV

SENN

CC

3816 F13

1X

R

PREIMON

PREI

MON

I

MON

A

MOD

≈ 25V/V ≈ 28dB

I

MON

C

R

IMON

It has a fairly benign AC behavior at typical loop compen-

sation frequencies with signiﬁcant phase shift appearing

at half the switching frequency.

V

SS(SEN)

Figure 13. I_MONConﬁguration

3816f

ꢁꢃ

LTC3816

applicaTions inForMaTion

LC Filter

where:

The external inductor and output capacitor combination

causes a second order LC roll-off at the output with 180°

of phase shift. At higher frequencies, the reactance of the

outputcapacitorapproachesitsESR,andtheroll-offdueto

thecapacitorstops,leaving–20dB/decadeand90°ofphase

shift.BeyondtheESRzero,theceramiccapacitorcreatesa

high frequency pole. The LC ﬁlter transfer function, poles

and zero locations are given by the following equations:

A

B

= R

= A

• C

+ A

• R

• C

(SR)

ESR

BULK

G(SR)

SEN

OUT

CER

• R

• C

G(SR)

SEN

ESR

BULK

Similarly, for the DCR conﬁguration with NTC compen-

sation, the simpliﬁed low frequency transfer function is

given by:

1+sA_(DCR)+s²B

V_SERVO

(DCR)

≈

V_OUT

1+sR_ESR•C_BULK

V_OUT

V_SW

1+sR_ESR•C_BULK

s²L_LC_OUT+SR_LC_OUT+1

A_LC=

≈

where:

(

)

A

B

= R

= A

• C

+ A

• R

• C

DCR OUT

(DCR)

ESR

BULK

G(DCR)

1

•

C

_BULK•C_CER

• R

• C

BULK CER

(DCR)

G(DCRN)

DCR

ESR

1+sR_ESR

C_OUT

Note that with either the sense resistor or the DCR current

sense conﬁguration, the AVP circuitry introduces a pole at

the same location as the LC lowpass ﬁlter ESR zero. This

cancels the increase in gain and phase caused by the ESR

zero. Fortunately, the zero in the AVP transfer function is

typically within the closed-loop bandwidth and provides a

beneﬁcial phase boost at the crossover frequency.

1

2π L_LC_OUT

f_{LC(DOUBLE_POLE)}

=

1

f_ESR(ZERO)

=

2π •R_ESR•C_BULK

1

f_CER(POLE)

C_BULK•C_CER

2π •R_ESR

Error Ampliﬁer

C_OUT

The error ampliﬁer provides most of the low frequency

loop gain and servos the switcher output voltage to the

VID DAC potential minus the AVP droop. After selecting

the inductor, the output capacitor and the AVP component

values, the control loop is compensated by tailoring the

frequencyresponseoftheerrorampliﬁer.AtypicalLTC3816

application uses Type 3 compensation to frequency com-

pensate the feedback loop. Figure 14a and Figure 14b

show the LTC3816 error ampliﬁer Type 3 conﬁguration.

The transfer function of this ampliﬁer is given by the fol-

lowing equation:

where:

R includesDCR,senseresistance,PCBtraceresistance

L

and the turn-on resistance of the power MOSFET.

L includes the inductor inductance, PCB trace induc-

L

tance and sense resistor ESL.

C

= C

+ C

BULK CER

OUT

AITC and Differential Ampliﬁers

With the sense resistor conﬁguration, the AITC and the

differential ampliﬁers add a double zero and a pole in the

vicinity of the feedback loop crossover frequency, f , and

multiple poles at higher frequencies. The simpliﬁed low

frequencytransferfunctionfromtheregulatoroutputnode

to the SERVO pin, as shown in Figure 14a, is given by the

following equation:

1+sR •C 1+sR1•C

V_COMP

V_SERVO

(

)

(

)

C

FF

C

= –







C_C•C_C1

sR1 C +C

1+sR

(

)

^CC_C+C

C

C1





_C1

The error ampliﬁer component values can be obtained

using the following guidelines.

1+sA_(SR)+s²B_(SR)

V_SERVO

V_OUT

≈

1+sR_ESR•C_BULK

3816f

ꢁꢄ

LTC3816

applicaTions inForMaTion

C

FF

R

C

C1

R1

V

IN

I

L

SERVO V

COMP

TG

SW

BG

–

+

FB

ESL

R

SEN

L

SW

EA

V

OUT

1.3V

SENSE RESISTOR

R

ESR

C

CER

R

LTC3816

+

AVPSR

C

BULK

BSOURCE

+

–

DAMP

I

TCFB

–

AITC

+

C

R

VSR

I

TC

I

SENN

SS(SEN)

CC(SEN)

V

3816 F14a

Figure 14a. LTC3816 Frequency Compensation with Sense Resistor Conﬁguration

C

FF

R

C

C1

R1

V

IN

I

L

SERVO V

COMP

TG

SW

BG

–

+

FB

L

DCR

SW

EA

V

OUT

1.3V

INDUCTOR

NTC

R

ESR

C

R

CER

AVPDCRN

LTC3816

+

C

BULK

BSOURCE

+

–

DAMP

R

PAR

I

TCFB

–

AITC

+

C

VDCRN

R

SER

I

TC

I

SENN

SS(SEN)

CC(SEN)

V

3816 F14b

Figure 14b. LTC3816 Frequency Compensation with DCR Conﬁguration

3816f

ꢁꢅ

LTC3816

applicaTions inForMaTion

LINE FEEDFORWARD (LFF)

f_OSC

N

1. Select f = feedback crossover frequency =

C

The LTC3816 incorporates a line feedforward function to

compensate for changes in the line voltage and to simplify

the frequency compensation. On the other hand, with

the line feedforward enabled, the feedback loop has high

modulator gain and is more sensitive to noise pickup.

If the input supply voltage is low (e.g., around 5V) and

well regulated, it is better to disable the LFF function by

shorting the LFF pin to GND. Without LFF, the modulator

where N is between 5 and 10.

2. At the feedback loop crossover frequency, f , the loop

C

gain is unity, therefore the error ampliﬁer gain is:

V_COMP

V_SERVO

1

=

V_SERVO

V_OUT

A

_MOD• A_LC•

gain A

is reduced and the control loop is less

MOD(WOLFF)

sensitive to noise injection.

3. Place the error ampliﬁer zero near the LC ﬁlter double-

pole frequency:

A

≈ 0.85 • V

MOD(WOLFF)

IN

1

If line feedforward is disabled, the control loop needs to

be recompensated in order to account for the reduction

in modulator gain.

f_EA(ZERO)

=

≈

2π •R_C•C_C

2π L_LC_OUT

4. The feedforward zero is positioned to give the required

phase boost at the crossover frequency:

DPRSLPVR AND VID DAC SLEW RATE CONTROL

1

The LTC3816 allows the user to program the VID DAC

voltage transition slew rate by adding a capacitor at the

CSLEW pin. In the IMVP-6.5 mode, CSLEW is internally

pulledupbya40µAcurrentsource. Uponacodetransition

command, CSLEW is ramped up by the internal current

f_FF(ZERO)

=

2π •R1•C_FF

5. Place the error ampliﬁer pole at 5f to suppress the

C

switching noise.

source. When the capacitor, C

, potential reaches 1V,

1

SLEW

f_EA(POLE)

=

= 5f_C

the VID DAC output voltage jumps by 1 LSB (12.5mV) and

the controller resets the C capacitor. This operation





C_C•C_C1

C +C

2π •R_C

SLEW







_C1

C

repeats until the DAC reaches its target value. The DAC

voltage slew rate is given by the following equation:

Compensating the switching power supply voltage feed-

backloopisacomplextask. Thefrequencycompensation

equations shown in this data sheet were obtained using

some approximations to simplify the calculations. The

compensation values shown in this data sheet are typi-

cal values, optimized for the power components shown

in the circuit. Though similar power components should

sufﬁce, substantially changing even one major power

component or circuit layout may degrade performance

signiﬁcantly. To verify the calculated component values,

all new circuit designs should be prototyped and tested

for stability.

dV_DAC

dt

I_CSLEW

C_SLEW

=12.5mV •

where I

= 40µA.

CSLEW

When the IMVP-6 conﬁguration is selected, the LTC3816

allows two different slew rates as shown in Figure 15.

Toconﬁgurethenormalslewrate,shortthepinDPRSLPVR

to ground. To conﬁgure for a slower slew rate, force the

DPRSLPVRpinpotentialabove1.6V. 25µsafterthecontrol-

ler detects a low-to-high transition at the DPRSLPVR pin,

3816f

ꢁꢆ

LTC3816

applicaTions inForMaTion

drops, which further improves efﬁciency by minimizing

gate charge losses.

ForcingtheMODE/SYNCpinlowenablesforcedcontinuous

mode operation. In forced continuous mode, the bottom

MOSFETisalwaysonwhenthetopMOSFETisoff,allowing

the inductor current to reverse at low currents. This mode

is less efﬁcient due to conduction and switching losses,

but has the advantage of better transient response at low

currents, constant frequency operation, and the ability to

maintain regulation when sinking current.

V

OUT

100mV/DIV

VID5

1V/DIV

DPRSLPVR

5V/DIV

3816 F15

V

C

= 12V

0.1ms/DIV

IN

= 0.75V TO 1.15V

OUT

SLEW

= 47pF

During soft-start, the LTC3816 forces the controller to

operate in pulse-skipping mode until the switcher output

IMVP-6 CONFIGURATION

Figure 15. Programmable VID Slew Rate

voltage reaches its V

power good threshold. During

BOOT

VID code transitions, however, the controller always oper-

ates in forced continuous mode to allow the switcher to

sink current.

thecontrollerreducestheI

pull-upcurrentfrom40µA

CSLEW

to 10µA (deeper sleep mode). This effectively reduces the

VID DAC slew rate to 1/4 of its original value. If IMVP-6.5

is selected, the slow slew rate function is disabled.

OPERATING FREQUENCY/FREQUENCY

SYNCHRONIzATION

PULSE-SKIPPING AND FORCED CONTINUOUS MODE

OPERATION

Theselectionofswitchingfrequencyisatrade-offbetween

efﬁciency and component size. Low frequency operation

increasesefﬁciencybyreducingMOSFETswitchinglosses,

but requires a larger inductance and/or capacitance to

maintain low output voltage ripple. For converters with

The LTC3816 can operate in one of two modes select-

able with the MODE/SYNC pin: pulse-skipping mode

or forced continuous mode. Shorting the MODE/SYNC

pin to INTV selects pulse-skipping mode. Pulse-skip-

CC

high step-down V -to-V

ratios, another consideration

IN

OUT

ping mode is selected when high efﬁciency at very light

loads is desired. In this mode, when the inductor current

reverses, the bottom MOSFET turns off to minimize the

efﬁciency loss due to reverse current ﬂow. This reduces

the conduction loss and slightly improves the efﬁciency.

As the load reduces, the top gate duty cycle shrinks to

maintain regulation. The LTC3816 is capable of operating

at extremely low duty cycles; hence, TG will continue to

run at a constant switching frequency until the top gate

on-timeislessthan40nsto50ns.Whentheloaddecreases

beyond this point, the LTC3816 TG begins to skip cycles

to maintain regulation. The driver switching frequency

is the minimum on-time of the converter.

V_OUT

_IN(MAX)• f_OSC

t_ON(MIN)

=

V

If the MODE/SYNC pin is not driven by an external clock,

the RFREQ pin voltage conﬁgures the LTC3816 free-run-

ning switching frequency. Floating or shorting the RFREQ

pin to INTV allows the controller to run at the nominal

CC

400kHz frequency. Connecting the RFREQ pin to GND

selects 210kHz. Tying RFREQ to a potential between 2.5V

and 3.5V selects 580kHz. The RFREQ pin has an internal

3816f

ꢁꢇ

LTC3816

applicaTions inForMaTion

10µA current source pull-up. Placing a resistor between

RFREQ and GND creates a potential given by the follow-

ing equation:

CLKEN#, OVF AND PWRGD

CLKEN# is an open-drain output used to enable the CPU’s

PLL.Uponpower-up,thisopen-drainpull-downisdisabled,

and CLKEN# is pulled high by an external resistor. During

the soft-start ramp, when the switcher output is 45mV

V

RFREQ

= I

• R

RFREQ RFREQ

whereI

=10µAandallowstheoscillatorfree-running

RFREQ

from the V

voltage, the controller completes its soft-

BOOT

frequency to be programmed between 210kHz to 580kHz

as shown in Figure 16.

start cycle and 75µs later, CLKEN# pulls low to enable the

processor PLL as shown in Figure 2.

An internal phase-locked loop (PLL) allows the LTC3816

to synchronize the internal oscillator to an external clock.

WhenthereisaclockingsignalattheMODE/SYNCpin, the

LTC3816phasedetectoradjuststheinternalPLLVCOinput,

synchronizingtheswitchingfrequencytotheexternalclock

frequency, and aligning the TG falling edge to the external

clock’s falling edge. During synchronization, the oscillator

frequency range widens to 120kHz to 650kHz.

At any instant, if the switcher output voltage rises above

the OVF threshold, the PWRGD pulls low, the regulator

output voltage is actively ramped to 0V and PWRGD

remains latched low until either the power is cycled or

VR toggles. In the IMVP-6 conﬁguration, the maximum

ON

OVF threshold is 1.7V. In the IMVP-6.5 conﬁguration, the

maximum threshold reduces to 1.55V.

The PWRGD pin is an open-drain output that indicates the

regulator output voltage has stabilized. At start-up, once

theswitcheroutputhassettledtoitsVIDpotentialformore

than 10ms, this open-drain releases and is pulled high by

theexternalpull-upresistor.Itpullslowagainiftheswitcher

output voltage remains outside of the +175mV/–270mV

window around its nominal VID set point for more than

750µs. Once pulled low, the PWRGD state is latched and

the control logic initiates a shutdown sequence. After the

For rapid frequency lock-in, the VCO input voltage can be

pre-biased to the desired operating frequency before the

external clock is applied. A resistor connected between

the RFREQ pin and GND can pre-bias the VCO’s input

voltage to the desired potential. Once pre-biased, the PLL

loop only needs to make slight changes to the VCO input

voltage in order to synchronize. The ability to pre-bias the

loop ﬁlter allows the PLL to lock-in rapidly.

700

600

SYNCHRONIZATION

500

400

300

200

100

FREE

RUNNING

1.5 1.8

(V)

0

0.3 0.6 0.9 1.2

2.1 2.4

V

RFREQ

3816 F16

Figure 16. VCO Transfer Curve

3816f

ꢁꢈ

LTC3816

applicaTions inForMaTion

output voltage is ramped down, the controller continues

event. The controller continues its normal operation with

no disruption to the output voltage. To reset this thermal

comparator, the voltage at the RPTC pin must drop below

0.1V. To accurately reﬂect the system temperature, the

nonlinear PTC thermistor should be mounted as close as

thermally possible to the hottest device, e.g., the inductor

or the MOSFET. To prevent the switching noise from af-

fecting the thermal sensing circuit, add a small capacitor

near the RPTC pin.

to hold the regulator output and PWRGD low until the

VR pin toggles or the input supply resets.

ON

During a VID transition, the power good comparators

are masked for 100µs. In deeper sleep mode (25µs after

DPRSLPVR pin transitions high), the power good com-

parators are disabled and PWRGD stays high unless the

switcher output voltage rises above its overvoltage fault

threshold OVF or the controller detects that the regulator

output voltage is 370mV lower than its nominal value.

Figure 17 shows the Murata PTC PRF18 series typical re-

sistance-temperaturecharacteristics.Atroomtemperature,

all parts have about 470Ω nominal resistance. At higher

temperatures, the resistance increases exponentially. An

overtemperature event is detected by the LTC3816 when

thePTCthermistor’sresistanceexceeds4.7k.Byselecting

the appropriate thermistor from the series, this thermal

monitoring threshold can be set anywhere from 65°C to

145°C with 10°C resolution.

The LTC3816 PWRGD pin can be conﬁgured for wire-OR

operation. Shorting PWRGD to ground externally triggers

a latchoff function. The regulator forces the output to a

zero voltage condition and stays in this state until either

the VR pin or the input supply resets.

ON

VRTT# AND THERMAL SHUTDOWN

The LTC3816 includes a thermal monitoring circuit that

senses the potential at the RPTC pin. An internal 100µA

pull-up current source connects to an external nonlinear

PTC thermistor through this pin. At room temperature, the

low resistance PTC creates a low voltage at the RPTC pin.

At high temperatures, the PTC resistance increases expo-

nentially.IftheresultingRPTCvoltageishigherthan0.47V,

it trips the thermal monitor comparator, causing the open-

drain pin VRTT# to pull low signaling an overtemperature

TheLTC3816includesasecondthermalprotectionfeature.

If the LTC3816 die temperature is higher than 150°C, the

controller pulls down the VRTT# pin. Under this condition

the CPU should initiate its thermal management opera-

tion. To untrip the VRTT# ﬂag, the die temperature must

be dropped below 130°C. If the LTC3816 die temperature

exceeds 165°C, the driver is disabled and the controller is

latchedinathermalshutdownstateuntilthepowersupply

is cycled or the VR input toggles.

ON

1000

BG

BF

BE

BD

BC

BB

BA

AR

AS

100

10

1

0

–20

0

20 40 60 80 100 120 140 160

TEMPERATURE (°C)

3816 F17

Figure 17. Murata Nonlinear PTC PRF18 Series Typical

Resistance-Temperature Characteristics. Extracted From

Murata PTC PRF18**471QB1RB Data Sheet

3816f

ꢂ0

LTC3816

applicaTions inForMaTion

POWER MOSFET AND SCHOTTKY DIODE SELECTION

estimate the C

term is to take the change in gate

MILLER

charge from points A and B on a manufacturers data sheet

The LTC3816 requires two external N-channel power

MOSFETs:Oneforthetop(main)switchandone(ormore)

for the bottom (synchronous) switch.

and divide by the stated V voltage speciﬁed. C

is

DS

MILLER

the most important selection criteria for determining the

transition loss term in the top MOSFET but is not directly

The peak-to-peak MOSFET gate drive levels are set by the

speciﬁed on MOSFET data sheets. C

and C

are

RSS

OSS

5.2VINTV supply,requiringtheuseoflogic-levelthresh-

speciﬁed sometimes but deﬁnitions of these parameters

are not included.

CC

old MOSFETs in most applications. Pay close attention to

the BV

speciﬁcation for the MOSFETs as well; many

DSS

When the controller is operating in continuous mode the

duty cycles for the top and bottom MOSFETs are given

by:

logic-level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs includes the

input capacitance, the on-resistance R

, the input

DS(ON)

V_OUT

voltage and the maximum output current. MOSFET input

capacitance is a combination of several components

but can be derived from the typical gate-charge curve

included on most data sheets as shown in Figure 18. The

curve is generated by forcing a constant input current

into the gate of a common source, current source loaded

stage and then plotting the gate voltage versus time. The

initial slope is the effect of the gate-to-source and the

gate-to-drain capacitances. The ﬂat portion of the curve

is the result of the Miller multiplication effect of the drain-

to-gate capacitance as the drain drops the voltage across

the current source load. The upper sloping line is due to

the drain-to-gate accumulation capacitance and the gate-

to-source capacitance.

Main Switch Duty Cycle =

V

IN

V – V_OUT

IN

Synchronous Switch Duty Cycle =

V

IN

The power dissipation for the main and synchronous

MOSFETs at maximum output current are given by:

2

V_OUT

P_MAIN

=

I

1+δ R

+

(

)

(

)

(

DS(ON)

LOAD MAX

(

)

V

IN

₂I_LOAD(MAX)

V

R

_DR)(

C

•

(

)

IN

MILLER

2







1

+

f

(

)



OSC

V_INTVCC– V_GS(MIL)

V



_GS(MIL)

The Miller charge (the increase in coulombs on the hori-

zontal axis from A to B while the curve is ﬂat) is speciﬁed

2

V – V_OUT

IN

P_SYNC

=

I

(

1+δ R

DS(ON)

(

)

for a given V drain voltage, but can be adjusted for

LOAD(MAX)

DS

V

IN

different V voltages by multiplying the ratio of the ap-

DS

plication V to the curve speciﬁed V values. A way to

DS

where δ is the temperature dependency of R

and

DS(ON)

R

is the effective top driver resistance (approximately

DR

2.6Ω). V

V

IN

is the MOSFET V at the Miller effect

GS(MIL)

GS

MILLER EFFECT

transition. C

is the calculated capacitance using

V

GS

MILLER

V

GS(MIL)

the gate-charge curve from the MOSFET data sheet as

A

B

+

–

described above. The term (1 + δ) is generally given for

V

DS

+

Q

V

IN

a MOSFET in the form of a normalized R

versus

GS

DS(ON)

–

C

= (Q – Q )/V

B A DS

MILLER

temperature curve, but δ = 0.005/°C can be used as an

3816 F18

approximation for low voltage MOSFETs.

Figure 18. MOSFET Miller Capacitance

3816f

ꢂꢀ

LTC3816

applicaTions inForMaTion

BothMOSFETshaveI RlosseswhilethetopsideN-channel

2

ThisequationhasamaximumRMScurrentatV =2V

,

OUT

IN

equation includes an additional term for transition losses,

whicharehighestatthehighestinputvoltage.Thenumber,

type and on-resistance of all MOSFETs selected take into

account the voltage step-down ratio as well as the actual

position (main or synchronous) in which the MOSFET is

used. A much smaller, lower input capacitance MOSFET

should be used for the top MOSFET in applications where

where I

= I

/2. This simple worst-case

RMS(MAX)

LOAD(MAX)

condition is commonly used for design because even

signiﬁcant deviations do not offer much relief. A typical

LTC3816 application operates at low duty cycle, hence,

the maximum input supply ripple current occurs at

V = V

, and typically I

< I

/2.5.

LOAD(MAX)

IN

IN(MIN)

RMS(MAX)

Note that capacitor manufacturers’ ripple current ratings

are often based on only 2000 hours of life. This makes

it advisable to further derate the capacitor or to choose

a capacitor rated at a higher temperature than required.

Several capacitors may also be paralleled to meet size or

height requirements in the design. Sanyo OS-CON SVP,

SVPD series or aluminum electrolytic capacitors from

Panasonic WA series in parallel with a couple of high

performance ceramic capacitors should be used as the

input supply bypass. Ceramic capacitors placed next to

the top MOSFET drain helps to reduce the input supply

voltage ripple.

V >> V . The top MOSFET’s on-resistance is normally

IN

OUT

less important for overall efﬁciency than its input capaci-

tance at operating frequencies above 300kHz. MOSFET

manufacturershavedesignedspecialpurposedevicesthat

provide reasonably low on-resistance with signiﬁcantly

reducedinputcapacitanceforthemainswitchinswitching

regulators. The synchronous MOSFET losses are greatest

at high input voltages when the top switch duty cycle is

low or during a short circuit when the synchronous switch

is on close to 100% of the period.

The Schottky diode, D, shown in Figure 1 conducts during

the dead-time between the conduction of the two large

power MOSFETs. This prevents the body diode of the bot-

tom MOSFET from turning on, storing charge during the

dead time and requiring a reverse-recovery period which

could cost as much as several percent in efﬁciency. Due

to the relatively small average current, a 2A to 8A Schottky

is generally acceptable while offering a good compromise

between series resistance and capacitance. Larger diodes

result in additional transition loss due to their larger junc-

tion capacitance.

C

SELECTION

OUT

Theoutputcapacitorchoiceisprimarilydeterminedbythe

voltage tolerance speciﬁcations due to large load current

transients encountered in typical LTC3816 applications.

The capacitance must be sufﬁcient to absorb the change

in inductor current when a high current to low current

transition occurs. The opposite load current transition is

generally determined by the control loop compensation

components, so make sure not to overcompensate and

slow down the response. The minimum capacitance to

assure the inductor’s energy is adequately absorbed is:

C SELECTION

IN

Incontinuousmode, thesourcecurrentofthetopN-chan-

2

L ∆I

(

)

nel MOSFET is a square wave of duty cycle V /V . To

LOAD

OUT IN

C_BULK+C_CER

=

preventlargevoltagetransients, alowESRinputcapacitor

sized for the maximum RMS current must be used. The

maximum RMS capacitor current is given by:

2V_OUT∆V

(

)

OUT(LOAD)

where C

is the amount of bulk capacitance and C

BULK

CER

is the total amount of ceramic capacitance. To minimize

the output voltage overshoot during a load step, set:

V_OUTV – V

(

)

IN

OUT

I_RMS(MAX)≈I_LOAD(MAX)

V

IN

∆V

= ∆V

OUT(AVP)

OUT(LOAD)

3816f

ꢂꢁ

LTC3816

applicaTions inForMaTion

The resistive component of the bulk capacitor ESR must

be small enough that under a load release, ESR multiplied

by the change in load current must meet the following

criteria:

The Sanyo OS-CON semiconductor electrolyte capacitor

is one possible choice for high performance through-hole

capacitors. In surface mount applications, multiple paral-

lel capacitors are required to meet the ESR or transient

current handling requirements. Aluminum electrolytic

and dry tantalum capacitors are both available in surface

mountconﬁgurations.Newspecialpolymersurfacemount

capacitors offer very low ESR but have much lower ca-

pacitive density per unit volume. In the case of tantalum,

it is critical that the capacitors are surge tested for use in

switchingpowersupplies.Severalexcellentoutputcapaci-

tor choices are the Sanyo POSCAP TPF, TPL and TPLF, or

the Panasonic SP series. Consult the manufacturer for

other speciﬁc recommendations.

∆V

> ∆I • R

LOAD ESR

OUT(LOAD)

The ceramic capacitors at the regulator output help to

absorb some of the change in the load current and reduce

theESRvoltagesteppredictedbytheaboveequation.High

performance ceramic capacitors also help to lower the

regulator output voltage perturbation caused by the high

slew rate change in the inductor current ﬂowing through

the bulk capacitor parasitic ESL.

The total amount of output capacitance required is also

restricted by the steady-state output voltage ripple. The

output ripple, ∆V , in continuous mode is determined

INDUCTOR SELECTION

OUT

by:

TheinductorinatypicalLTC3816circuitischosenprimarily

for its saturation current and inductance value. The induc-

tor DC rated current should be larger than the expected

peak current which is equal to:





1

∆V_OUT≈ ∆I R

+

_L



ESR

8• f_OSC• C_BULK+C_CER

(

)





∆I_L(MAX)

where f

= operating frequency and ∆I = ripple current

L

OSC

I_L(PEAK)=I_LOAD(MAX)

+

in the inductor. The output ripple is highest at maximum

2

input voltage since ∆I increases with input voltage. The

L

Inaddition,theselectedinductormustbeabletowithstand

ﬁrst term in the ripple voltage equation relates to the

ripple current into the ESR of the output capacitor, which

dominates the output ripple voltage. The second term

guarantees that the output capacitance does not signiﬁ-

cantly discharge during the operating frequency period

due to ripple current.

2 × I

for a short duration without saturation (see

LOAD(MAX)

the Current Limit section).

The inductor value sets the ripple current, which is com-

monly chosen at around 20% to 30% of the anticipated

full load current. Higher inductance reduces ripple cur-

rent, core losses in the inductor, ESR losses in the output

capacitors and output voltage ripple. But, under rapid

loading conditions, higher inductance results in higher

peak-to-peak transient deviations. A lower value inductor

reduces the number of output capacitors and requires a

smaller PCB footprint for the LC ﬁlter. Highest efﬁciency

operation is obtained at low frequency with small ripple

current. However, achieving this requires a large induc-

tor and higher output ripple under transient conditions.

There is a trade-off between component size, efﬁciency

Note that the IMVP-6 or IMVP-6.5 application speciﬁes

extremely low output voltage deviations. Therefore, the

output capacitor selection should be carefully considered.

The regulator should be located in close proximity to the

CPU. The bulk capacitor needs to be as close as possible

to the power supply pins of the processor to minimize the

parasiticinductancebetweenthedecouplingcapacitorand

the load. In addition, multiple high performance ceramic

capacitors are normally placed in the processor socket

cavity to compensate for the PCB parasitic resistance

and inductance.

3816f

ꢂꢂ

LTC3816

applicaTions inForMaTion

and operating frequency. Given a speciﬁed limit for ripple

current, the inductor value can be obtained using the fol-

lowing equation:

V

BAT

IN

12V

LTC3816

TG

Q

T

L

V

C

SW

BG

OUT









V_OUT

f_OSC• ∆I

V_OUT

+

Q

B

D

L =

1–

OUT

V

_L(MAX)

_IN(MAX)

BSOURCE

3816 F19

Once the value for L is known, the type of inductor must

be selected. High efﬁciency converters generally cannot

affordthecorelossfoundinlowcostpowderedironcores,

forcing the use of more expensive ferrite cores. Ferrite

designs have very low core loss and are thus preferred

at high switching frequencies. Ferrite core materials

saturate hard, which means that inductance collapses

abruptly when the peak design current is exceeded. This

results in an abrupt increase in inductor ripple current and

consequent output voltage ripple. Do not allow the core to

saturate! A variety of inductors designed for high current,

low voltage applications are available from manufacturers

such as Vishay, Sumida, Pulse, Wurth Elektronik, Vitec

and Toko.

Figure 19. Automotive Application Protection

transient suppressor clamps the input voltage during

load dump. Note that the transient suppressor should not

conduct during double-battery operation, but must still

clamptheinputvoltagebelowbreakdownoftheconverter.

Although the IC has a maximum input voltage of 40V on

the SW pins, most applications will be limited to 30V by

the MOSFET BV

.

DSS

CHECKING TRANSIENT RESPONSE

For all new LTC3816 PCB circuits, transient tests need to

beperformedtoverifytheproperfeedbackloopoperation.

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

AUTOMOTIVE CONSIDERATIONS

Before you connect an LTC3816 converter to an automo-

tive cigarette lighter supply, be advised: you are plugging

into the supply from hell. The main battery line in an

automobile is the source of a number of nasty potential

transients, including load dump, reverse battery and

double battery.

load current. When a load step occurs, V

shifts by an

OUT

amount equal to ∆V . ∆I

also begins to charge or

AVP

LOAD

discharge C

generating the feedback error signal that

OUT

forces the regulator to adapt to the current change and

return V to its steady-state value. During this recovery

OUT

time V

can be monitored for excessive overshoot or

OUT

ringing, which would indicate a stability problem.

Load dump is the result of a loose battery cable. When the

cable breaks connection, the ﬁeld collapse in the alterna-

tor can cause a positive spike as high as 60V which takes

several hundred milliseconds to decay. Reverse battery is

just what it says, while double battery is a consequence of

tow truck operators ﬁnding that a 24V jump start cranks

cold engines faster than 12V.

Measuring transient response presents challenges in two

respects:obtaininganaccuratemeasurementandgenerat-

ing a suitable transient to use to test the circuit. Output

measurementsshouldbetakenwithascopeprobedirectly

acrosstheoutputcapacitor.Properhighfrequencyprobing

techniques should be used. In particular, don’t use the 6"

groundleadthatcomeswiththeprobe!Useanadapterthat

ﬁts on the tip of the probe and has a short ground clip to

ensure that inductance in the ground path doesn’t cause

a bigger spike than the transient signal being measured.

ThenetworkshowninFigure19isthemoststraightforward

approach to protect a DC/DC converter from the ravages

of an automotive battery line. The series diode prevents

current from ﬂowing during reverse battery, while the

3816f

ꢂꢃ

LTC3816

applicaTions inForMaTion

Conveniently, the typical probe tip ground clip is spaced

just right to span the leads of a typical output capacitor. In

general,itisbesttotakethismeasurementwiththe20MHz

bandwidth limit on the oscilloscope turned on to limit high

frequencynoise.Notethatmicroprocessormanufacturers

typically specify ripple ≤20MHz, as energy above 20MHz

is generally radiated and not conducted and will not affect

the load even if it appears at the output capacitor.

A DESIGN EXAMPLE

As a design example, consider an IMVP-6.5 application

with inductor DCR current sense (see the last page

schematic) and the following requirements: assume V

IN

= 12V (nominal), V = 24V (maximum), V

= 0.75V,

LOAD(MAX) LOAD(MIN)

IN

OUT

V

(minimum) = 0.725V, I

= 1.5A, AVP = –3mV/A, f

= 27A, I

OUT

= 400kHz, V

= 1.0V.

OSC

IMON

For the input and output conditions given above, the

steady-state minimum on-time for this application at

V = 24V is approximately:

IN

Now that we know how to measure the signal, we need to

have something to measure. The ideal situation is to use

the actual load for the test, and switch it on and off while

watching the output. If this isn’t convenient, a current

step generator is needed. This generator needs to be able

to turn on and off in nanoseconds to simulate a typical

switching logic load, so stray inductance and long clip

leads between the LTC3816 and the transient generator

must be minimized.

V_OUT(MIN)

0.725V

t_ON(MIN)

=

= 75.5ns

V

_IN(MAX)• f_OSC24V •400kHz

This is much longer than the LTC3816 minimum on-time.

To program the 400kHz operation, ﬂoat the RFREQ pin.

Theinductancevalueischosenﬁrstbasedona20%ripple

current assumption. The highest value of ripple current

occurs at the maximum input voltage:

Figure 20 shows an example of a simple transient gen-

erator. Be sure to use a noninductive resistor as the load

element—many power resistors use an inductive spiral

pattern and are not suitable for use here. A simple solution

is to take ten 1/4W ﬁlm resistors and wire them in parallel

to get the desired value. This gives a noninductive resis-

tive load which can dissipate 2.5W continuously or 50W

if pulsed with a 5% duty cycle, enough for most LTC3816

circuits. Solder the MOSFET and the resistor(s) as close

to the output of the LTC3816 circuit as possible and set

up the signal generator to pulse at a 100Hz rate with a 5%

duty cycle. This pulses the LTC3816 with 500µs transients

10ms apart, adequate for viewing the entire transient

recovery time for both positive and negative transitions

while keeping the load resistor cool.









V_OUT

f_OUT• ∆I

V_OUT

L =

1–

V

_L(MAX)

_IN(MAX)

0.75V

400kHz •0.2•27A

0.75V

24V





=

1–

= 0.33µH









A commonly available 0.33µH inductor is chosen. This

results in 5.5A of ripple current. The peak inductor cur-

rent is the maximum DC load current plus one-half the

ripple current, or:

1

2

I_L(PEAK)= 27A + •5.5A = 29.75A

LTC3816

V

OUT

R

LOAD

50Ω

PULSE

GENERATOR

RENESAS RJK0305DPB

OR EQUIVALENT

10k

0V TO 10V

100Hz, 1% TO 5%

3816 F20

DUTY CYCLE

LOCATE CLOSE TO THE OUTPUT

Figure 20. Transient Load Generator PC Board

3816f

ꢂꢄ

LTC3816

applicaTions inForMaTion

Forthisexample,aVishayIHLP-5050CE-010.33µHinduc-

tor is chosen. According to the inductor data sheet, it has

a maximum DC current rating of 36.5A and a saturation

current of 62A. At room temperature, the typical DCR is

1.3mΩ and the maximum DCR is 1.5mΩ. At 125°C, the

DCR increases to approximately 2.085mΩ. The R

resistor value can be calculated.

ToderivethevoltagedropacrosstheinductorDCR(typically

1.3mΩ), place a 0.1µF capacitor across the current sense

inputpins,I

andI

.Thecurrentsenseﬁlterresistor

SENP

SENN

value R

can be calculated from the equation:

IDCR

L

0.33µH

R_IDCR

=

= 2.538k

IMAX

R_DCR•C_IDCR1.3mΩ•0.1µF

R_DCR



I

IMAX(MIN)

Select R

= 2.55k.

∆I

_L

2



IDCR

R_IMAX= I

+





 ^LIMIT

For the AVP section (refer to Figure 10), ﬁrst select a 10k

NTC thermistor. In this example, the Murata NCP18XH103

is chosen. Next, select:

2.085mΩ

= 29.75A •

= 6.89k

9µA

R

= R

at 25°C = 10k

PAR

NTC

Choose 1% resistor R

regulator can supply the maximum load current under

the worst-case conditions.

= 6.98k to ensure that the

IMAX

The R

ing equation:

resistor value can be obtained from the follow-

SER

10

3

If this large DCR variation is a problem, replace this induc-

tor with another inductor with a smaller DCR variation or

useanNTCtemperaturecompensationcircuitasshownin

Figure 21. Please refer to the Temperature Compensated

Active Voltage Positioning with Inductor DCR section.

Note that Figure 21 uses a resistive divider and requires

different component values for optimal temperature

compensation.





R_SER

≈

R

|| R

at 0°C – R || R

at 75°C

(

)

(

)

(

) (

)

PAR

NTC

PAR

NTC





– R || R

(

at 25°C

(

)

PAR

NTC

From the NTC data sheet:

R

at 0°C = 27.2k

NTC

at 75°C = 1.925k

V

IN

I

L

LTC3816

TG

Q

T

L

DCR

V

SW

BG

OUT

INDUCTOR

NTC

Q

B

D

+

C

OUT

R

S

BSOURCE

R

PAR

SER

3816 F21

I

SENP

SENN

C

IDCR

I

R

IMAX

I

MAX

Figure 21. Inductor DCR Current Sense Using

NTC Temperature Compensation

3816f

ꢂꢅ

LTC3816

applicaTions inForMaTion

Therefore R

is calculated to be 13.99k and standard

Select R

= 21k. The value of C

is selected to

IMON

SER

IMON

valueR =14kisused.Next,theresistorR

value

satisfy the desired I

time constant:

SER

AVPDCRN

MON

is obtained from the AVP slope requirement:

t_IMON

R_IMON

300µs

21k

C_IMON

=

=14.28nF







R_SER+ R_PAR||R_NTC

(

)



A

_AVP== 3mV/A =

•R_DCR

R_AVPDCRN

Select C

= 15nF.

IMON





14k + 10k||10k

(

)





The power MOSFETs chosen for this application are the

Renesas RJK0305DPB (top) and 2 × RJK0330DPB (bot-

tom). The upper MOSFET, which is optimized for low

⇒R_AVPDCRN

=

•1.3mΩ= 8.233k

3mV/A

Selectthestandardvalue8.25k.ThecapacitorvalueC

is given by the following equation:

VDCRN

switching losses, has a typical R

of 10mΩ at V

DS(ON)

GS

= 4.5V, a total gate charge of 8nC, and a minimum BV

DSS

of 30V. The bottom MOSFET which is optimized for low

L

C_VDCRN

=

on-resistance, has a typical R

of 2.8mΩ at V

=

DS(ON)

GS





R_SER+ R_PAR||R_NTC•R_DCR

(

)





4.5V, a total gate charge of 27nC, and a minimum BV

of 30V.

DSS

0.33µH

14k + 10k||10k •1.3mΩ

=13.36nF





(

)





From the RJK0305DPB upper MOSFET data sheet, the

Miller capacitance is calculated to be:

Use the standard value C

= 15nF.

VDCRN

∆Q_G

∆V_DS12V

2nC

To program the I

PREIMON

to 20µA:

voltage, ﬁrst select the resistor

PREIMON

C_MILLER

≈

=

=167pF

MON

such that I

R

bias current is around 10µA

Assuming a top MOSFET junction temperature of 75°C,

δ = 0.25 and the power dissipation in this MOSFET is:

I

_LOAD(MAX)•R_DCR

R_NTCNET

R_AVPDCRN

R_PREIMON

=

•

I_PREIMON

2

V_OUT

P_MAIN

=

I

(

1+δ R_DS(ON)+ t

(

)

LOAD(MAX)





V

14k + 10k||10k

(

)

27A •1.3mΩ

IN





•

₂I_LOAD(MAX)

15µA

8.25k

V

R

(

C

•

(

)

_DR)(

)

IN

MILLER

= 5.389k

2







1

SelectastandardvalueR

PREIMON

be obtained from the following equation:

= 5.1k. Oncethe resistor

IMON

PREIMON

value is chosen, the R

+

f



(

)

OSC

V

_{ INTVCC}– V_GS(MIL)

V

R

resistor value can



^GS(MIL)^

0.75V

12V

2

P_MAIN

27A 1+0.25 10mΩ+

) (

(

)

V

_IMON•R_PREIMON

R_AVPDCRN

R_NTCNET

R_IMON

=

•

₂27A

3• I_LOAD(MAX)•R_DCR

(

)

12V

2.6Ω 167pF •

(

)

(

)(

)

2

1.0V •5.1k

•

8.25k

1







3• 27A •1.3mΩ





+

400kHz

14k + 10k||10k

(

)

(

)

(

)









5.2V –3V 3V



= 21.03k

P_MAIN= 0.57W+0.266W ≈0.836W

3816f

ꢂꢆ

LTC3816

applicaTions inForMaTion

For the synchronous MOSFETs, assume that the two

bottom MOSFETs share the inductor current equally. The

power dissipation for one MOSFET is:

Most regulator designs allow a slight transient overshoot

for a short duration. If this is limited to 40mV, we have:

∆V_OUT(AVP)= AVP • I_LOAD(MAX)–I_LOAD(MIN)

(

)

2

V – V_OUT

IN

P_SYNC

=

I

1+δ R

DS(ON)

(

)

mV

A

(

)

LOAD(MAX)

V

= 3

• 27A –1.5A = 76.5mV

(

)

IN

12V –0.75V

12V

2

∆V_OUT(LOAD)= ∆V_OUT(AVP)+ ∆V_OVERSHOOT

P_SYNC

=

13.5A 1+0.25 2.8mΩ

(

) (

)

= 76.5mV+ 40mV=116.5mV

= 0.598W

2

0.33µH 27A –1.5A

2 0.75V 116.5mV

( )(

(

)

The total power dissipation of the bottom MOSFETs is

2 × 0.598W = 1.196W.

C_BULK+C_CER

=

=1228µF

)

For this application, the maximum input RMS current

The ESR of the output capacitor is determined by the load

transient requirement. If the output voltage jump due to

happens when V = V

and can be determined from

IN

IN(MIN)

the formula:

the capacitor ESR is limited to ∆V

:

OUT(AVP)

∆V_OUT(AVP)

V_OUT

V_IN(MIN)– V_OUT

75mV

27A –1.5A

(

)

R_ESR

<

=

= 2.94mΩ

I_RMS(MAX)≈I_LOAD(MAX)

∆I_LOAD

(

)

V

IN(MIN)

The above requirements are easily satisﬁed by three

Sanyo POSCAP 2TPF330M6 330µF (ESR = 6mΩ) bulk

capacitors in parallel, twenty 10µF and some 1µF high

performance ceramic capacitors in the processor socket

cavity. With three bulk capacitors in parallel, the effective

ESR is 2mΩ, and the maximum steady-state output ripple

voltage is given by:

0.75V 5V –0.75V

(

)

≈9.64A

I_RMS(MAX)≈27A

5V

The minimum RMS current rating of the input capacitor

mustexceed9.64A.Tomeetthisripplecurrentrequirement

with V

= 24V, select two Sanyo OS-CON 25SVP56

IN(MAX)

capacitors or higher voltage rating capacitor as the input

supply bulk capacitance. In addition, place a couple of

high performance ceramic capacitors in parallel with the

bulk capacitors.







1

∆V_OUT≈ ∆I R

_L

+

ESR

8• f_OSC• C_BULK+C_CER

(

)









The output capacitor value is determined by:









1

= 5.5A 2mΩ+



2

8•400kHz • 3•330µF +20•10µF

(

)



L ∆I

(

)

LOAD

C_BULK+C_CER

=

=11mV+1.44mV =12.44mV

2V_OUT∆V

(

)

OUT(LOAD)

3816f

ꢂꢇ

LTC3816

applicaTions inForMaTion

Ascanbeseenfromtheaboveequation,thebiggestportion

of the output ripple comes from the ESR of the capacitor.

This is why low ESR capacitors are so important in low

voltage, high current applications.

6. The AITC ampliﬁer external components should be

placed close to the LTC3816. Only the NTC or PTC

thermistor should be placed near the inductor.

7. Are the V

and V

, I

and I

leads

CC(SEN)

SS(SEN) SENP

SENN

routed together with minimum PC trace spacing? The

ﬁlter capacitor between V and V and the

PC BOARD LAYOUT CHECKLIST

CC(SEN)

SS(SEN)

should be as

ﬁlter capacitor between I

and I

SENP

SENN

When laying out the printed circuit board, start with the

power devices. Be sure to orient the power circuitry so

that a clean ﬂow of the power path is achieved. Conductor

widths should be maximized and lengths minimized. After

you are satisﬁed with the power path, the control circuitry

should be laid out. It is much easier to ﬁnd routes for the

relatively small traces in the control circuits than it is to

ﬁnd circuitous routes for high current paths. After the

layout, the following checklist should be used to ensure

proper operation of the LTC3816.

close as possible to the LTC3816. Ensure accurate

current sensing with Kelvin connections as shown in

Figure 22.

8. To prevent I

current from affecting the output

MON

voltage kelvin sense accuracy, the I

resistor and

MON

V

should be connected to the CPU V

SS(SEN)

using separate PCB traces.

9. Since the IC ground will normally return to the ground

planes on the PCB through an array of vias, be sure

to avoid having any high di/dt power path currents

ﬂowing under the IC.

1. KeeptheGNDandBSOURCEtracesseparate.Thesignal

ground consists of the LTC3816 GND pin and the (–)

terminal of V . The power ground consists of the

OUT

10. Any external small-signal components that are con-

nected to ground should be located as close as pos-

sible to the IC, with local connections to GND or the

ground plane using vias.

BSOURCE pin, the Schottky diode anode, the source

of the bottom side MOSFET, and the (–) terminal of the

input capacitor. Also, try to connect the (–) terminal

of the output capacitor as close as possible to the (–)

terminalsoftheinputcapacitor.PlacetheLDOceramic

INDUCTOR

capacitor C

next to the IC, between INTV and

INTVCC

CC

GND. The negative terminals of C , C

and C

INTVCC

IN OUT

LTC3816

R_ISR

should be as close as possible to one another.

I

SENP

SENSE

RESISTOR

C

ISR

I

2. The high di/dt loop formed by the top MOSFET, the

SENN

bottom MOSFET and the C capacitor should have

IN

short leads and PC trace lengths to minimize high

frequency noise and voltage stress from inductive

ringing.

OUTPUT CAPACITOR

SW

3. ConnectthedrainofthetopsideMOSFETdirectlytothe

(+) plate of C , and connect the source of the bottom

LTC3816

R_ISR

IN

I

SENP

side MOSFET directly to the (–) terminal of C . This

IN

C

INDUCTOR

ISR

I

capacitor provides the AC current to the MOSFETs.

SENN

4. The charge pump capacitor, C , should also be next

B

3816 F22

OUTPUT CAPACITOR

to the IC between BOOST and SW.

5. Place the small-signal components away from high

frequency switching nodes (BOOST, SW, TG and

BG).

Figure 22. Sense Resistor and Inductor DCR

Kelvin Current Sensing

3816f

ꢂꢈ

LTC3816

Typical applicaTions

An IMVP-6 Converter Using Current Sense Resistor with –5.7mV/A AVP Slope

4.75k 3.32k

33pF

1000pF 124Ω

1.1V

2.37k

I

3.3V

INTV

CC

GND

I

SGND I

I

LFF

56Ω 1.9k 1.9k

TC

TCFB

SENN

MAX SENP

PREI

VRTT#

CLKEN#

PWRGD

VRTT#

MON

RPTC

I

CLKEN#

PTC

4.5V TO 25V

V

C

1000pF

IN

+

8

VR

ON

SW

TG

IN

1

5

4

V

SS(SEN)

CC(SEN)

R

C

L

0.1µF

SEN

6, 7

V

BOOST

CC(CORE)

+

C

BULK

CER

SERVO

I

V

LOAD(MAX)

LTC3816

IN

330µF

10µF

4A

1µF

D

22pF

20k

s2

s6

2, 3

10k

10pF

EXTV

CC

B

SS(CORE)

V

FB

INTV

CC

4.7µF

INTV

CC

Si4816BDY

100Ω

COMP

BG

BSOURCE

MODE/SYNC

RFREQ

1500pF

DPRSLPVR

SS

DPRSLPVR

CSLEW

f

SYNC

C

: SANYO POSCAP 2TPF330M6

BULK

470pF

22pF

VID0 VID1 VID2 VID3 VID4 VID5 VID6

L: VISHAY IHLP2525CZ-06 (1µH, DCR = 8.44mΩ)

PTC: MURATA PRF18BC471QB1RB

R

: PANASONIC ERJM1WTF4M0U

SEN

3816 TA02

Efﬁciency

Transient Waveform

100

90

V

OSC

V

= 1V

CC(CORE)

f

= 400kHz

= 0V

EXTVCC

80

V

70

CC(CORE)

20mV/DIV

60

50

V

= 5V

IN

V

IN

= 12V

40

30

20

10

0

I

LOAD

2A/DIV

CONTINUOUS MODE

PULSE-SKIPPING MODE

3816 TA02b

0.01

0.1

LOAD CURRENT (A)

1

20µs/DIV

3816 TA02b

3816f

ꢃ0

LTC3816

Typical applicaTions

3816f

ꢃꢀ

LTC3816

package DescripTion

FE Package

38-Lead Plastic eTSSOP (4.4mm)

(Reference LTC DWG # 05-08-1772 Rev B)

Exposed Pad Variation AA

4.75 REF

9.60 – 9.80*

(.378 – .386)

4.75

(.187)

REF

38

20

6.60 0.10

2.74 REF

4.50 REF

SEE NOTE 4

6.40

REF (.252)

BSC

2.74

(.108)

0.315 0.05

1.05 0.10

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

19

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0o – 8o

0.50

(.0196)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.17 – 0.27

FE38 (AA) eTSSOP REV B 0510

(.0067 – .0106)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

2. DIMENSIONS ARE IN

FOR EXPOSED PAD ATTACHMENT

MILLIMETERS

(INCHES)

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

3. DRAWING NOT TO SCALE

3816f

ꢃꢁ

LTC3816

package DescripTion

UHF Package

38-Lead Plastic QFN (5mm × 7mm)

(Reference LTC DWG # 05-08-1701 Rev C)

0.70 p 0.05

5.50 p 0.05

4.10 p 0.05

3.00 REF

5.15 0.05

3.15 0.05

PACKAGE

OUTLINE

0.25 p 0.05

0.50 BSC

5.5 REF

6.10 p 0.05

7.50 p 0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

R = 0.30 TYP OR

0.35 s 45o CHAMFER

0.75 p 0.05

3.00 REF

5.00 p 0.10

37

38

0.00 – 0.05

0.40 p0.10

PIN 1

TOP MARK

1

2

(SEE NOTE 6)

5.15 0.10

5.50 REF

7.00 p 0.10

3.15 0.10

(UH) QFN REF C 1107

0.200 REF 0.25 p 0.05

R = 0.125

TYP

R = 0.10

TYP

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE

OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3. ALL DIMENSIONS ARE IN MILLIMETERS

3816f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3816

Typical applicaTion

An IMVP-6.5 Converter Using Temperature Compensated Inductor DCR Sensing with –3mV/A AVP Slope

10k

14k

8.25k

I

SENN

15nF

6.98k

0.1µF

I

MAX

TCFB

TC

2.55k

SENP

LFF

5.1k

15nF

21k

PREI

56Ω

1.9k

MON

VRTT#

CLKEN#

PWRGD

1.1V

I

MON

LT3816

CLKEN#

PWRGD

RPTC

3.3V

V

IN

4.5V TO 24V

1000pF

VR

ON

V

+

SS(SEN)

CC(SEN)

NTC

L

100Ω

SW

TG

C

VIN

V

Q

T

SERVO

0.1µF

10k

BOOST

V

FB

+

12k

D

B

10pF

2.2nF

V

IN

Q

B

CC(CORE)

C

CER

C

COMP

BULK

I

= 27A

LOAD(MAX)

EXTV

INTV

5V

CC

PTC

22pF

CC

SS

BG

BSOURCE

MODE/SYNC

RFREQ

DPRSLPVR

CSLEW

470pF 22pF

4.7µF

C

: 3 s SANYO 2TPF330M6 (330µF)

BULK

C

: 20 s 10µF + 2 s 1µF

CER

IN

: 2 s SANYO OS-CON 35SVPD47M + 2 s 10µF

VID0

VID1

VID2

VID3

D : CMDSH-4E

B

VID6

L: IHLP-5050CE-01 (0.33µH, DCR = 1.3mΩ)

NTC: MURATA NCP18XH103

VID5

VID0

VID1

VID2

VID3

VID4

VID5

VID6

PTC: MURATA PRF18BC471QB1RB

VID4

GND

Q : 2 s RENESAS RJK0330DPB

B

Q : RENESAS RJK0305DPB

T

relaTeD parTs

PART NUMBER DESCRIPTION

COMMENTS

LTC3732

LTC3733

LTC3734

3-Phase, 5-Bit VID, 600kHz Synchronous Buck Switching Regulator Controller

Single-Phase, High Efﬁciency DC/DC Controller for Intel Mobile CPUs

VRM9.0 and VRM9.1, VID = 1.1V to 1.85V

AMD Opteron (VID = 0.8V to 1.55V)

6-Bit IMVP-4 VID: 0.7V ≤ V

≤ 1.708V, I

≤ 25A,

OUT

LOAD

Lossless Voltage Positioning

6-Bit IMVP-IV, VID Code: V = 0.7V to 1.708V

OUT

LTC3735

LTC3738

LTC3819

LTC3850

2-Phase, High Efﬁciency DC/DC Controller for Intel Mobile CPUs

3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning VID = 1.1V to 1.85V

2-Phase, High Efﬁciency, Step-Down Controller for AMD CPUs

Dual 2-Phase Synchronous Controller

4V ≤ V ≤ 36V, VID =1.025V to 1.4125V

IN

Dual 180° Phase Controllers, 4V ≤ V ≤ 28V,

IN

97% Duty Cycle

LTC3851A

LTC3853

No R

™ Wide Input Range Step-Down Controller

4V ≤ V ≤ 38V, Very Low Dropout with Tracking

SENSE

IN

Triple Output, Multiphase Synchronous Step-Down Controller

Triple Phase Version of LTC3850 in a 40-Lead

6mm × 6mm QFN Package

3816f

LT 0710 • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

ꢀꢀ

●

 LINEAR TECHNOLOGY CORPORATION 2010

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3816EFE#TRPBF
厂家：	Linear
描述：	LTC3816 - Single-Phase Wide VIN Range DC/DC Controller for Intel IMVP-6/IMVP-6.5 CPUs; Package: TSSOP; Pins: 38; Temperature Range: -40°C to 85°C 开关光电二极管
文件：	总44页 (文件大小：758K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3816EFE#TRPBF [Linear]

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