LTC3831IGN#PBF [Linear]
LTC3831 - High Power Synchronous Switching Regulator Controller for DDR Memory Termination; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LTC3831IGN#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3831 - High Power Synchronous Switching Regulator Controller for DDR Memory Termination; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 双倍数据速率 开关 光电二极管 |
| 文件： | 总20页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3831
High Power Synchronous
Switching Regulator Controller
for DDR Memory Termination
DESCRIPTION
FEATURES
The LTC®3831 is a high power, high efficiency switching
regulator controller designed for DDR memory termina-
tion. The LTC3831 generates an output voltage equal
to 1/2 of an external supply or reference voltage. The
LTC3831 uses a synchronous switching architecture
with N-channel MOSFETs. Additionally, the chip senses
output current through the drain-source resistance of the
upperN-channelFET,providinganadjustablecurrentlimit
without a current sense resistor.
n
High Power Switching Regulator Controller
for DDR Memory Termination
OUT
n
V
Tracks 1/2 of V or External V
IN REF
n
n
n
n
n
n
No Current Sense Resistor Required
Low Input Supply Voltage Range: 3V to 8V
Maximum Duty Cycle >91% Over Temperature
Drives All N-Channel External MOSFETs
High Efficiency: Over 95% Possible
Programmable Fixed Frequency Operation:
100kHz to 500kHz
The LTC3831 operates with input supply voltage as low as
3V and with a maximum duty cycle of >91%. It includes
a fixed frequency PWM oscillator for low output ripple
operation. The 200kHz free-running clock frequency can
be externally adjusted or synchronized with an external
signal from 100kHz to above 500kHz. In shutdown mode,
the LTC3831 supply current drops to <10μA.
n
n
n
n
n
External Clock Synchronization Operation
Programmable Soft-Start
Low Shutdown Current: <10μA
Overtemperature Protection
Available in 16-Pin Narrow SSOP Package
APPLICATIONS
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
n
DDR SDRAM Termination
n
SSTL_2 Interface
n
SSTL_3 Interface
TYPICAL APPLICATION
V
DDQ
2.5V
5V
Efficiency vs Load Current
100
+
C
IN
MBR0530T1
90
80
70
60
50
40
30
20
10
0
330μF
×2
0.1μF
1k
1μF
PV
PV
Q1
MBRS340T3
10k
CC2
CC1
TG
V
CC
0.1μF
L
O
0.1μF
SS
I
MAX
1.2μH
V
TT
0.01μF
130k
+
1.25V
6A
LTC3831
I
FB
4.7μF
Q2
MBRS340T3
FREQSET
SHDN
BG
PGND
GND
+
C
OUT
470μF
SHDN
T
V
V
= 25°C
A
= 2.5V
IN
OUT
COMP
×3
C
: SANYO POSCAP 6TPB330M
C : SANYO POSCAP 4TPB470M
OUT
Q1, Q2: SILICONIX Si4410DY
IN
= 1.25V
C1
33pF
R
+
C
R
15k
3831 F01
0
1
3
4
5
6
2
FB
C
C
–
R
LOAD CURRENT (A)
1500pF
2831 G01
Figure 1. Typical DDR Memory Termination Application
3831fb
1
LTC3831
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Supply Voltage
TG
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BG
PV
V
V ..............................................................................9V
CC
PV
CC1
CC2
PV
......................................................................14V
CC1,2
PGND
GND
CC
Input Voltage
I , I
I
I
FB
MAX
..................................................... –0.3V to 14V
–
FB MAX
R
+
–
R , R , FB, SHDN, FREQSET.......... –0.3V to V to 0.3V
CC
FB
FREQSET
COMP
SS
Junction Temperature (Note 9) ............................. 125°C
Operating Temperature Range Note 4).....–40°C to 85°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
+
R
SHDN
GN PACKAGE
16-LEAD PLASTIC SSOP
= 125°C, θ = 130°C/W
T
JMAX
JA
ORDER INFORMATION
LEAD FREE FINISH
LTC3831EGN#PBF
LTC3831IGN#PBF
LEAD BASED FINISH
LTC3831EGN
TAPE AND REEL
PART MARKING
3831
PACKAGE DESCRIPTION
16-Lead Plastic SSOP
16-Lead Plastic SSOP
PACKAGE DESCRIPTION
16-Lead Plastic SSOP
16-Lead Plastic SSOP
TEMPERATURE RANGE
LTC3831EGN#TRPBF
LTC3831IGN#TRPBF
TAPE AND REEL
–40°C to 85°C
3831
–40°C to 85°C
PART MARKING
3831
TEMPERATURE RANGE
–40°C to 85°C
LTC3831EGN#TR
LTC3831IGN#TR
LTC3831IGN
3831
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC, PVCC1, PVCC2 = 5V, VR+ = 2.5V, VR– = GND, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
3
TYP
MAX
8
UNITS
l
l
V
Supply Voltage
5
V
V
V
V
CC
PV
PV , PV , Voltage
(Note 7)
3
13.2
2.9
CC
UVLO
FB
CC1
CC2
V
V
Undervoltage Lockout Voltage
Feedback Voltage
2.4
l
V + = 2.5V, V – = 0V, V
R
= 1.25V
1.231
1.25
1.269
R
COMP
ΔV
OUT
Output Load Regulation
Output Line Regulation
I
= 0A to 10A (Note 6)
= 4.75V to 5.25V
2
0.1
mV
mV
OUT
CC
V
l
l
I
I
Supply Current
Figure 2, V
SHDN
= V
CC
0.7
1
1.6
10
mA
μA
VCC
SHDN
V
= 0V
l
l
PV Supply Current
CC
Figure 2, V
= 0V
= V (Note 3)
14
0.1
20
10
mA
μA
PVCC
SHDN
CC
V
SHDN
l
Δf
Internal Oscillator Frequency
FREQSET Floating
160
200
1.2
2.2
240
kHz
V
OSC
V
V
V
COMP
COMP
at Minimum Duty Cycle
at Maximum Duty Cycle
SAWL
SAWH
V
V
3831fb
2
LTC3831
ELECTRICAL CHARACTERISTICS The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC, PVCC1, PVCC2 = 5V, VR+ = 2.5V, VR– = GND, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
Maximum V
CONDITIONS
MIN
TYP
2.85
10
MAX
UNITS
V
V
V
= 0V, PV
= 8V
COMPMAX
COMP
FB
CC1
Δf /ΔI
OSC FREQSET
Frequency Adjustment
kHz/μA
dB
A
V
Error Amplifier Open-Loop DC Gain
Error Amplifier Transconductance
●
●
46
55
g
m
520
650
100
780
μmho
μA
I
Error Amplifier Output Sink/Source
Current
COMP
I
I
Sink Current
V
V
= V
CC
9
4
12
12
15
20
μA
μA
MAX
MAX
IMAX
●
I
Sink Current Tempco
= V (Note 6)
3300
ppm/°C
MAX
IMAX
CC
V
V
SHDN Input High Voltage
SHDN Input Low Voltage
SHDN Input Current
Soft-Start Current
●
●
●
●
2.4
–8
V
V
IH
0.8
1
IL
I
I
I
V
V
V
= V
CC
0.1
–12
1.6
μA
μA
mA
IN
SHDN
= 0V, V
= 0V, V = V
CC
–16
SS
SS
IMAX
IFB
Maximum Soft-Start Sink Current
Undercurrent Limit
= V , V = 0V, V = V (Note 8),
CC IFB SS CC
= 8V
SSIL
IMAX
PV
CC1
+
+
R
R Input Resistance
49.5
80
kΩ
ns
ns
%
t t
r, f
Driver Rise/Fall Time
Figure 2, PV
Figure 2, PV
= PV
= PV
= 5V (Note 5)
= 5V (Note 5)
●
●
●
250
250
CC1
CC2
t
Driver Nonoverlap Time
Maximum TG Duty Cycle
25
91
120
95
NOV
CC1
CC2
DC
Figure 2, V = 0V (Note 5), PV
= 8V
MAX
FB
CC1
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 3: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This will vary with
the LTC3831 operating frequency, operating voltage and the external FETs
used.
Note 4: The LTC3831EGN is guaranteed to meet performance
specifications from 0°C to 85°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization
and correlation with statistical process controls. The LTC 3831IGN is
guaranteed to meet performance specifications over the full –40°C to 85°C
temperature range.
Note 5: Rise and fall times are measured using 10% and 90% levels. Duty
cycle and nonoverlap times are measured using 50% levels.
Note 6: Guaranteed by design, not subject to test.
Note 7: PV
must be higher than V by at least 2.5V for TG to operate
CC1
CC
at 95% maximum duty cycle and for the current limit protection circuit to
be active.
Note 8: The current limiting amplifier can sink but cannot source current.
Under normal (not current limited) operation, the output current will be
zero.
Note9:ThisICincludesovertemperatureprotectionthatisintendedtoprotect
the device during momentary overload conditions. Junction temperature
will exceed 125°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature may
impair device reliability.
3831fb
3
LTC3831
TYPICAL PERFORMANCE CHARACTERISTICS
Error Amplifier Transconductance
vs Temperature
Load Regulation
Line Regulation
800
750
700
650
1.270
1.265
1.260
1.255
1.250
1.245
1.240
1.235
1.230
1.260
1.258
1.256
1.254
1.252
1.250
1.248
1.246
1.244
1.242
1.240
10
8
T
= 25°C
T
= 25°C
A
A
REFER TO FIGURE 1
NEGATIVE OUTPUT CURRENT
INDICATES CURRENT SINKING
6
4
2
0
–2
–4
–6
–8
–10
600
550
500
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–4
–2
2
4
6
–6
0
3
4
5
6
7
8
OUTPUT CURRENT (A)
SUPPLY VOLTAGE (V)
3831 G05
3831 G02
3831 G03
Error Amplifier Sink/Source
Current vs Temperature
Error Amplifier Open-Loop Gain
vs Temperature
Output Temperature Drift
1.270
1.265
1.260
1.255
1.250
1.245
1.240
1.235
1.230
20
15
10
5
200
180
160
140
120
100
80
60
55
50
45
REFER TO FIGURE 1
OUTPUT = NO LOAD
0
–5
–10
–15
–20
60
40
40
–25
0
50
75
100
–25
0
50
75 100 125
–50
25
–50
25
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3831 G04
3831 G06
3831 G07
Oscillator Frequency
vs Temperature
Oscillator Frequency
Oscillator (VSAWH – VSAWL
)
vs FREQSET Input Current
vs External Sync Frequency
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
250
240
230
220
210
200
190
180
170
600
500
400
300
200
100
0
T
= 25°C
FREQSET FLOATING
T
= 25°C
A
A
160
–40
–20
–10
0
10
20
100
200
300
500
–30
400
–50 –25
0
25
125
50
75 100
FREQSET INPUT CURRENT (μA)
EXTERNAL SYNC FREQUENCY (kHz)
TEMPERATURE (°C)
3831 G09
3831 G10
3831 G08
3831fb
4
LTC3831
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum TG Duty Cycle
vs Temperature
IMAX Sink Current
vs Temperature
Output Overcurrent Protection
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
20
18
16
14
12
10
8
100
99
98
97
96
95
94
93
92
V
= 0V
FB
REFER TO FIGURE 3
6
T
= 25°C
A
REFER TO FIGURE 1
4
91
8
0
2
4
6
10
–25
0
50
75 100 125
–50
25
–50 –25
0
25
125
50
75 100
OUTPUT CURRENT (A)
TEMPERATURE (°C)
TEMPERATURE (°C)
3831 G13
3831 G12
3831 G11
Output Current Limit Threshold
vs Temperature
Soft-Start Source Current
vs Temperature
Soft-Start Sink Current
vs (VIFB – VIMAX
)
–8
–9
10
9
8
7
6
5
4
3
2
1
0
2.00
1.75
1.50
1.25
REFER TO FIGURE 1
T
= 25°C
A
–10
–11
–12
–13
–14
–15
–16
1.00
0.75
0.50
0.25
0
–25
0
50
75 100 125
–50
25
–125 –100
–50
–150
–25
0
–50
0
25
50
75 100 125
–75
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
V
– V
(mV)
IMAX
IFB
3831 G15
3831 G16
3831 G14
Undervoltage Lockout Threshold
Voltage vs Temperature
VCC Operating Supply Current
vs Temperature
PVCC Supply Current
vs Oscillator Frequency
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
90
80
70
60
50
40
30
20
10
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
T
= 25°C
FREQSET FLOATING
A
TG AND BG LOADED
WITH 6800pF,
PV
= 12V
CC1,2
TG AND BG
LOADED
TG AND BG
LOADED
WITH 6800pF,
PV
WITH 1000pF,
= 5V
CC1,2
PV
= 5V
CC1,2
0
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
0
400
500
–25
–25
100
200
300
TEMPERATURE (°C)
TEMPERATURE (°C)
OSCILLATOR FREQUENCY (kHz)
3831 G17
3831 G18
3831 G19
3831fb
5
LTC3831
TYPICAL PERFORMANCE CHARACTERISTICS
PVCC Supply Current
vs Gate Capacitance
TG Rise/Fall Time
vs Gate Capacitance
Transient Response
50
40
30
200
180
160
140
120
100
80
T
= 25°C
T
= 25°C
A
A
V
OUT
PV
= 12V
CC1,2
50mV/
DIV
t AT PV
f
= 5V
CC1,2
t AT PV
r
= 5V
CC1,2
20
10
0
I
LOAD
PV
= 5V
CC1,2
2A/DIV
60
40
3831 G22
t AT PV
f
= 12V
CC1,2
50μs/DIV
20
t AT PV
r
= 12V
CC1,2
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
GATE CAPACITANCE AT TG AND BG (nF)
GATE CAPACITANCE AT TG AND BG (nF)
3831 G20
3831 G21
PIN FUNCTIONS
TG ( Pin 1): Top Driver Output. Connect this pin to the
resistor divider. The FB pin is servoed to the ratiometric
reference under closed-loop conditions. The LTC3831 can
gate of the upper N-channel MOSFET, Q1. This output
swings from PGND to PV . It remains low if BG is high
operate with a minimum V of 1.1V and maximum V
CC1
FB FB
or during shutdown mode.
of (V – 1.75V).
CC
PV (Pin2):PowerSupplyInputforTG.Connectthispin
SHDN (Pin 8): Shutdown. A TTL compatible low level at
SHDN for longer than 100μs puts the LTC3831 into shut-
down mode. In shutdown, TG and BG go low, all internal
circuits are disabled and the quiescent current drops to
10μA max. A TTL compatible high level at SHDN allows
the part to operate normally. This pin also double as an
external clock input to synchronize the internal oscillator
with an external clock.
CC1
to a potential of at least V + V
. This potential
IN
GS(ON)(Q1)
can be generated using an external supply or a simple
charge pump connected to the switching node between
the upper MOSFET and the lower MOSFET.
PGND (Pin 3): Power Ground. Both drivers return to
this pin. Connect this pin to a low impedance ground in
close proximity to the source of Q2. Refer to the Layout
Consideration section for more details on PCB layout
techniques.
SS (Pin 9): Soft-Start. Connect this pin to an external
capacitor, C , to implement a soft-start function. If the
SS
LTC3831 goes into current limit, C is discharged to
SS
GND (Pin 4): Signal Ground. All low power internal cir-
cuitry returns to this pin. To minimize regulation errors
due to ground currents, connect GND to PGND right at
the LTC3831.
reduce the duty cycle. C must be selected such that
SS
during power-up, the current through Q1 will not exceed
the current limit level.
COMP(Pin10):ExternalCompensation.Thispininternally
connects to the output of the error amplifier and input of
the PWM comparator. Use a RC + C network at this pin
to compensate the feedback loop to provide optimum
transient response.
–
+
R , R (Pins 5, 7): These two pins connect to the internal
resistordividerthatgeneratetheinternalratiometricrefer-
ence for the error amplifier. The reference voltage is set
at 0.5 • (V + – V –).
R
R
FB (Pin 6): Feedback Voltage. FB senses the regulated
output voltage either directly or through an external
3831fb
6
LTC3831
PIN FUNCTIONS
FREQSET (Pin 11): Frequency Set. Use this pin to adjust
the free-running frequency of the internal oscillator. With
the pin floating, the oscillator runs at about 200kHz. A
resistorfromFREQSETtogroundspeedsuptheoscillator;
througha1kresistor. The1kresistorisrequiredtoprevent
voltage transients from damaging I .This pin is used
FB
for sensing the voltage drop across the upper N-channel
MOSFET, Q1.
a resistor to V slows it down.
CC
V
(Pin 14): Power Supply Input. All low power internal
CC
I
(Pin 12): Current Limit Threshold Set. I
sets the
circuits draw their supply from this pin. This pin requires
MAX
MAX
threshold for the internal current limit comparator. If I
a 4.7μF bypass capacitor to GND.
FB
drops below I
with TG on, the LTC3831 goes into cur-
MAX
PV
(Pin 15): Power Supply Input for BG. Connect this
CC2
rent limit. I
has an internal 12μA pull-down to GND.
MAX
pin to the main high power supply.
Connect this pin to the main V supply at the drain of
IN
BG (Pin 16): Bottom Driver Output . Connect this pin to
Q1, through an external resistor to set the current limit
threshold. Connect a 0.1μF decoupling capacitor across
this resistor to filter switching noise.
the gate of the lower N-channel MOSFET, Q2. This output
swingsfromPGNDtoPV .ItremainslowwhenTGishigh
CC2
or during shutdown mode. To prevent output undershoot
during a soft-start cycle, BG is held low until TG first goes
high (FFBG in the Block Diagram).
I
(Pin 13): Current Limit Sense. Connect this pin to the
FB
switching node at the source of Q1 and the drain of Q2
BLOCK DIAGRAM
DISABLE GATE DRIVE
LOGIC AND
THERMAL SHUTDOWN
V
CC
SHDN
100μs DELAY
POWER DOWN
INTERNAL
OSCILLATOR
PV
TG
PV
BG
CC1
–
FREQSET
COMP
S
R
Q
PWM
+
Q
CC2
FFBG
12μA
PGND
FB
S
Q
ENABLE
BG
QSS
SS
POR
R
+
R
ERR
MIN
MAX
24k
+
+
+
–
–
–
V
V
+ 3%
REF
REF
750Ω
750Ω
24k
V
V
REF
V
– 3%
V
I
+ 3%
REF
REF
REF
–
FB
CC
– 3%
+
I
MAX
–
R
DISABLE
12μA
2.2V
1.2V
I
LIM
Q
C
GND
+
PV
V
CC1
3830 BD
V
+ 2.5V
–
CC1
3831fb
7
LTC3831
TEST CIRCUITS
PV
CC
+
V
V
V
SHDN
CC
0.1μF
10μF
SHDN
PV
PV
I
FB
CC
CC2
CC1
TG RISE/FALL
6800pF
NC
NC
SS
FREQSET
FB
TG
BG
V
FB
LTC3831
V
COMP
COMP
2.5V
+
BG RISE/FALL
6800pF
R
–
R
I
GND
PGND
MAX
3831 F02
Figure 2
APPLICATIONS INFORMATION
OVERVIEW
THEORY OF OPERATION
Primary Feedback Loop
The LTC3831 is a voltage mode feedback, synchronous
switching regulator controller (see Block Diagram) de-
signed for use in high to medium power, DDR memory
termination. It includes an onboard PWM generator, a
ratiometric reference, two high power MOSFET gate
drivers and all necessary feedback and control circuitry
to form a complete switching regulator circuit. The PWM
loop nominally runs at 200kHz.
The LTC3831 senses the output voltage of the circuit
through the FB pin and feeds this voltage back to the
internal transconductance error amplifier, ERR. The er-
ror amplifier compares the output voltage to the internal
ratiometric reference, V , and outputs an error signal to
REF
the PWM comparator. V is set to 0.5 multiplied by the
REF
+
–
voltage difference between the R and R pins, using an
The LTC3831 is designed to generate an output voltage
that tracks at 1/2 of the external voltage connected be-
internal resistor divider.
+
–
This error signal is compared with a fixed frequency
ramp waveform, from the internal oscillator, to generate
a pulse width modulated signal. This PWM signal drives
the external MOSFETs through the TG and BG pins. The
resulting chopped waveform is filtered by L and C
which closes the loop. Loop compensation is achieved
with an external compensation network at the COMP pin,
the output node of the error amplifier.
tween the R and R pins. The LTC3831 can be used to
generate the termination voltage, V , for interface like
TT
the SSTL_2 where V is a ratio of the interface supply
TT
voltage, V . It is a requirement in the SSTL_2 interface
DDQ
standard for V to track the interface supply voltage to
O
OUT
TT
improve noise immunity. Using the LTC3831 to supply the
interface termination voltage allows large current sourc-
ing and sinking through the termination resistors during
bus transitions.
MIN, MAX Feedback Loops
The LTC3831 includes a current limit sensing circuit that
uses the topside external N-channel power MOSFET as
a current sensing element, eliminating the need for an
external sense resistor. Also included is an internal soft-
start feature that requires only a single external capacitor
to operate. In addition, the part features an adjustable
oscillator which can free run or synchronize to an external
signal with frequencies from 100kHz to 500kHz, allowing
added flexibility in external component selection.
Two additional comparators in the feedback loop provide
high speed output voltage correction in situations where
the error amplifier may not respond quickly enough. MIN
compares the feedback signal to a voltage 3% below V
.
REF
If the signal is below the comparator threshold, the MIN
comparator overrides the error amplifier and forces the
loop to maximum duty cycle, >91%. Similarly, the MAX
comparator forces the output to 0% duty cycle if the feed-
3831fb
8
LTC3831
APPLICATIONS INFORMATION
backsignalisgreaterthan3%aboveV .Topreventthese
in proportion to the voltage difference between I and
FB
MAX
REF
twocomparatorsfromtriggeringduetonoise,theMINand
MAXcomparators’responsetimesaredeliberatelydelayed
by two to three microseconds. These two comparators
helppreventextremeoutputperturbationswithfastoutput
load current transients, while allowing the main feedback
loop to be optimally compensated for stability.
I
. Under minor overload conditions, the SS pin falls
gradually, creating a time delay before current limit takes
effect.Veryshort,mildoverloadsmaynotaffecttheoutput
voltage at all. More significant overload conditions allow
the SS pin to reach a steady state, and the output remains
atareducedvoltageuntiltheoverloadisremoved. Serious
overloads generate a large overdrive at CC, allowing it to
pullSSdownquicklyandpreventingdamagetotheoutput
Thermal Shutdown
components. By using the R
of Q1 to measure the
DS(ON)
The LTC3831 has a thermal protection circuit that dis-
ables both gate drivers if activated. If the chip junction
temperature reaches 150°C, both TG and BG are pulled
low. TG and BG remain low until the junction temperature
drops below 125°C, after which, the chip resumes normal
operation.
output current, the current limiting circuit eliminates an
expensive discrete sense resistor that would otherwise be
required. This helps minimize the number of components
in the high current path.
The current limit threshold can be set by connecting an
external resistor R
from the I
pin to the main V
IMAX
IMAX
MAX IN
Soft-Start and Current Limit
supply at the drain of Q1. The value of R
is determined
by:
The LTC3831 includes a soft-start circuit that is used for
start-upandcurrentlimitoperation.TheSSpinrequiresan
external capacitor, CSS, to GND with the value determined
by the required soft-start time. An internal 12μA current
R
= (I
= I
)(R
)/I
IMAX
LMAX
DS(ON)Q1 IMAX
where:
I
source is included to charge C . During power-up, the
+ (I
/2)
SS
LMAX
LOAD
RIPPLE
COMP pin is clamped to a diode drop (B-E junction of QSS
in the Block Diagram) above the voltage at the SS pin.
This prevents the error amplifier from forcing the loop to
maximum duty cycle. The LTC3831 operates at low duty
I
I
= Maximum load current
LOAD
= Inductor ripple current
RIPPLE
V – V
V
OUT
(
OUT )(
)
IN
cycle as the SS pin rises above 0.6V (V
≈ 1.2V). As
=
COMP
f
L
V
IN
(
)
SS continues to rise, Q turns off and the error amplifier
OSC
O
SS
takes over to regulate the output. The MIN comparator is
disabled during soft-start to prevent it from overriding the
soft-start function.
f
= LTC3831 oscillator frequency = 200kHz
OSC
L = Inductor value
O
TheLTC3831includesyetanotherfeedbacklooptocontrol
operation in current limit. Just before every falling edge
of TG, the current comparator, CC, samples and holds the
voltagedropmeasuredacrosstheexternalupperMOSFET,
Q1, at the I pin. CC compares the voltage at I to the
R
= On-resistance of Q1 at I
LMAX
DS(ON)Q1
I
= Internal 12μA sink current at I
MAX
IMAX
The R
of Q1 usually increases with temperature.
DS(ON)
To keep the current limit threshold constant, the internal
12μA sink current at I is designed with a positive
FB
FB
voltage at the I
pin. As the peak current rises, the
MAX
MAX
measured voltage across Q1 increases due to the drop
temperature coefficient to provide first order correction
for the temperature coefficient of R
across the R
of Q1. When the voltage at I drops
.
DS(ON)
FB
DS(ON)Q1
belowI
,indicatingthatQ1’sdraincurrenthasexceeded
MAX
Inorderforthecurrentlimitcircuittooperateproperlyand
to obtain a reasonably accurate current limit threshold,
the I
the maximum level, CC starts to pull current out of C ,
SS
cutting the duty cycle and controlling the output current
and I pins must be Kelvin sensed at Q1’s drain
IMAX
FB
level. The CC comparator pulls current out of the SS pin
3831fb
9
LTC3831
APPLICATIONS INFORMATION
and source pins. In addition, connect a 0.1μF decoupling
ing a 50k resistor from FREQSET to ground forces 25μA
out of the pin, causing the internal oscillator to run at
approximately 450kHz. Forcing an external 10μA current
into FREQSET cuts the internal frequency to 100kHz. An
internalclamppreventstheoscillatorfromrunningslower
capacitor across R
to filter switching noise. Other-
IMAX
wise, noise spikes or ringing at Q1’s source can cause the
actual current limit to be greater than the desired current
limit set point. Due to switching noise and variation of
R , the actual current limit trip point is not highly
DS(ON)
than about 50kHz. Tying FREQSET to V forces the chip
CC
accurate. The current limiting circuitry is primarily meant
to prevent damage to the power supply circuitry during
fault conditions. The exact current level where the limit-
ing circuit begins to take effect will vary from unit to unit
to run at this minimum speed.
Shutdown
The LTC3831 includes a low power shutdown mode,
controlled by the logic at the SHDN pin. A high at SHDN
allows the part to operate normally. A low level at SHDN
for more than 100μs forces the LTC3831 into shutdown
mode.Inthismode,allinternalswitchingstops,theCOMP
and SS pins pull to ground and Q1 and Q2 turn off. The
LTC3831 supply current drops to <10μA, although off-
state leakage in the external MOSFETs may cause the total
as the R
of Q1 varies. Typically, R
varies as
DS(ON)
DS(ON)
much as 40% and with 25% variation on the LTC3831’s
current, this can give a 65% variation on the current
I
MAX
limit threshold.
The R is high if the V applied to the MOSFET is
DS(ON)
GS
low. This occurs during power up, when PV is ramping
CC1
up. To prevent the high R
from activating the cur-
DS(ON)
V current to be somewhat higher, especially at elevated
rent limit, the LTC3831 disables the current limit circuit
if PV is less than 2.5V above V . To ensure proper
IN
temperatures. If SHDN returns high, the LTC3831 reruns
CC1
CC
a soft-start cycle and resumes normal operation.
operation of the current limit circuit, PV
least 2.5V above V when TG is high. PV
when TG is low, allowing the use of an external charge
pump to power PV
must be at
can go low
CC1
CC1
CC
External Clock Synchronization
.
The LTC3831 SHDN pin doubles as an external clock input
for applications that require a synchronized clock. An
internal circuit forces the LTC3831 into external synchro-
nization mode if a negative transition at the SHDN pin is
detected. In this mode, every negative transition on the
SHDN pin resets the internal oscillator and pulls the ramp
signal low. This forces the LTC3831 internal oscillator to
lock to the external clock frequency.
CC1
V
IN
LTC3831
+
+
R
0.1μF
IMAX
C
IN
+
12
I
MAX
12μA
CC
TG
BG
Q1
I
FB
L
1k
O
V
13
–
OUT
Q2
C
OUT
The LTC3831 internal oscillator can be externally syn-
chronized from 100kHz to 500kHz. Frequencies above
300kHz can cause a decrease in the maximum obtainable
duty cycle as rise/fall time and propagation delay take up
a larger percentage of the switch cycle. The low period of
this clock signal must not be >100μs or else the LTC3831
enters into the shutdown mode.
3831 F03
Figure 3. Current Limit Setting
Oscillator Frequency
The LTC3831 includes an onboard current controlled os-
cillator that typically free-runs at 200kHz. The oscillator
frequency can be adjusted by forcing current into or out of
the FREQSET pin. With the pin floating, the oscillator runs
at about 200kHz. Every additional 1μA of current into/out
of the FREQSET pin decreases/increases the frequency by
10kHz. The pin is internally servoed to 1.265V, connect-
Figure4describestheoperationoftheexternalsynchroni-
zationfunction.AnegativetransitionattheSHDNpinforces
the internal ramp signal low to restart a new PWM cycle.
Notice that the ramp amplitude is lowered as the external
clock frequency goes higher. The effect of this decrease
in ramp amplitude increases the open-loop gain of the
3831fb
10
LTC3831
APPLICATIONS INFORMATION
supply input) by at least one power MOSFET V
for
CC1
GS(ON)
efficientoperation. AninternallevelshifterallowsPV to
SHDN
operateatvoltagesaboveV andV ,upto14Vmaximum.
CC
IN
Thishighervoltagecanbesuppliedwithaseparatesupply,
or it can be generated using a charge pump.
200kHz
FREE RUNNING
RAMP SIGNAL
RAMP SIGNAL
WITH EXT SYNC
Gate drive for the bottom MOSFET Q2 is provided through
TRADITIONAL
SYNC METHOD
WITH EARLY
RAMP
PV .ThissupplyonlyneedtobeabovethepowerMOSFET
CC2
GS(ON)
V
for efficient operation. PV
can also be driven
CC2
fromthesamesupply/chargepumpforthePV , oritcan
be connected to a lower supply to improve efficiency.
TERMINATION
CC1
Figure 6 shows a doubling charge pump circuit that can be
used to provide 2V gate drive for Q1. The charge pump
IN
RAMP AMPLITUDE
ADJUSTED
consists of a Schottky diode from V to PV and a 0.1μF
IN
CC1
LTC3831
KEEPS RAMP
AMPLITUDE
CONSTANT
capacitor from PV to the switching node at the drain of
CC1
Q2. This circuit provides 2V – V to PV while Q1 is
IN
F
CC1
ON and V – V while Q1 is OFF where V is the forward
UNDER SYNC
IN
F
F
voltage of the Schottky diode. Ringing at the drain of Q2
3831 F04
can cause transients above 2V at PV ; if V is higher
IN
CC1
IN
Figure 4. External Synchronization Operation
V
CC
PV
PV
V
IN
CC2
CC1
controller feedback loop. As a result, the loop crossover
frequency increases and it may cause the feedback loop
to be unstable if the phase margin is insufficient.
TG
BG
Q1
L
O
INTERNAL
CIRCUITRY
V
OUT
To overcome this problem, the LTC3831 monitors the
peak voltage of the ramp signal and adjust the oscillator
charging current to maintain a constant ramp peak.
+
C
Q2
OUT
3831 F05
LTC3831
Input Supply Considerations/Charge Pump
Figure 5. Supplies Input
The LTC3831 requires four supply voltages to operate: V
IN
for the main power input, PV
and PV
for MOSFET
CC1
CC2
V
IN
gate drive and a clean, low ripple V for the LTC3831
CC
internal circuitry (Figure 5).
OPTIONAL
USE FOR V ≥ 7V
MBR0530T1
IN
In many applications, V can be powered from V
CC
IN
D
Z
PV
PV
12V
CC2
CC1
TG
through an RC filter. This supply can be as low as 3V. The
low quiescent current (typically 800μA) allows the use
of relatively large filter resistors and correspondingly
small filter capacitors. 100Ω and 4.7μF usually provide
0.1μF
1N5242
Q1
L
O
V
OUT
+
adequate filtering for V . For best performance, connect
BG
CC
Q2
C
OUT
the 4.7μF bypass capacitor as close to the LTC3831 V
CC
3831 F06a
pin as possible.
LTC3831
Gate drive for the top N-channel MOSFET Q1 is supplied
fromPV .ThissupplymustbeaboveV (themainpower
Figure 6. Doubling Charge Pump
CC1
IN
3831fb
11
LTC3831
APPLICATIONS INFORMATION
than 7V, a 12V zener diode should be included from PV
D
1N5817
CC1
Z
V
IN
12V
toPGNDtopreventtransientsfromdamagingthecircuitry
1N5242
1N5817
1N5817
at PV or the gate of Q1.
CC1
0.1μF
10μF
PV
PV
CC2
CC1
TG
For applications with a lower V supply, a tripling charge
IN
0.1μF
pump circuit shown in Figure 7 can be used to provide
Q1
2V and 3V gate drive for the external top and bottom
IN
IN
L
O
MOSFETs respectively. This circuit provides 3V – 3V to
V
OUT
IN
F
PV
while Q1 is ON and 2V – 2V to PV
where V
CC2 F
+
CC1
IN
F
BG
Q2
C
OUT
is the forward voltage of the Schottky diode. The circuit
requires the use of Schottky diodes to minimize forward
drop across the diodes at start-up. The tripling charge
pump circuit can rectify any ringing at the drain of Q2 and
3831 F07
LTC3831
Figure 7. Tripling Charge Pump
providemorethan3V atPV ;a12Vzenerdiodeshould
IN
CC1
beincludedfromPV toPGNDtopreventtransientsfrom
CC1
Connecting the Ratiometric Reference Input
The LTC3831 derives its ratiometric reference, VREF
using an internal resistor divider. The top and bottom of
the resistor divider is connected to the R+ and R– pins
respectively. This permits the output voltage to track at
a ratio of the differential voltage at R+ and R–.
damaging the circuitry at PV
or the gate of Q1.
CC1
,
The charge pump capacitors for PV
refresh when the
CC1
BG pin goes high and the switch node is pulled low by
Q2. The BG on time becomes narrow when the LTC3831
operates at maximum duty cycle (95% typical) which
can occur if the input supply rises more slowly than the
soft-start capacitor or the input voltage droops during
load transients. If the BG on time gets so narrow that the
switch node fails to pull completely to ground, the charge
pumpvoltagemaycollapseorfailtostartcausingexcessive
dissipationinexternalMOSFETQ1. Thisismostlikelywith
The LTC3831 can operate with a minimum V of 1.1V
FB
–
and maximum V of (V – 1.75V). With R connected
FB
CC
+
to GND, this gives a V input range of 2.2V to (2 • V
R
CC
+
– 3.5V). If V is higher than the permitted input voltage,
R
increase the V voltage to raise the input range.
CC
low V voltages and high switching frequencies, coupled
CC
InatypicalDDRmemoryterminationapplicationasshown
with large external MOSFETs that slow the BG and switch
+
in Figure 1, R is connected to V , the supply voltage
DDQ
node slew rates.
–
of the interface, and R to GND. The output voltage V is
TT
The LTC3831 overcomes this problem by sensing the
connected to the FB pin, so V = 0.5 • V
.
TT
DDQ
PV
voltage when TG is high. If PV
CC
is less than 2.5V
CC1
CC1
If a ratio greater than 0.5 is desired, it can be achieved
above V , the maximum TG duty cycle is reduced to
using an external resistor divider connected to V and
TT
70% by clamping the COMP pin at 1.8V (Q in the Block
C
FB pin. Figure 8 shows an application that generates a
Diagram). This increases the BG on time and allows the
V of 0.6 • V
.
TT
DDQ
charge pump capacitors to be refreshed.
For applications using an external supply to power PV
,
CC1
this supply must also be higher than V by at least 2.5V
CC
to ensure normal operation.
3831fb
12
LTC3831
APPLICATIONS INFORMATION
V
DDQ
2.5V
5V
+
C
IN
MBR0530T1
330μF
×2
1μF
10k
0.1μF
1k
PV
PV
CC1
Q1
MBRS340T3
CC2
V
TG
CC
0.1μF
L
O
0.1μF
SS
I
MAX
1.2μH
V
1.5V
6A
TT
0.01μF
130k
+
I
LTC3831
FB
4.7μF
MBRS340T3
Q2
FREQSET
SHDN
BG
PGND
GND
+
C
OUT
SHDN
470μF
COMP
×3
C
: SANYO POSCAP 6TPB330M
: SANYO POSCAP 4TPB470M
IN
OUT
C1
33pF
2k
1%
R
C
+
C
R
15k
Q1, Q2: SILICONIX Si4410DY
FB
C
C
–
R
1500pF
10k
1%
3831 F08
Figure 8. Typical Application with VTT = 0.6 • VDDQ
Power MOSFETs
After the MOSFET threshold voltage is selected, choose
theR basedontheinputvoltage, theoutputvoltage,
allowablepowerdissipationandmaximumoutputcurrent.
InatypicalLTC3831circuitoperatingincontinuousmode,
the average inductor current is equal to the output load
current.ThiscurrentflowsthrougheitherQ1orQ2withthe
power dissipation split up according to the duty cycle:
DS(ON)
Two N-channel power MOSFETs are required for most
LTC3831circuits.Theseshouldbeselectedbasedprimarily
on threshold voltage and on-resistance considerations.
Thermal dissipation is often a secondary concern in high
efficiencydesigns.TherequiredMOSFETthresholdshould
be determined based on the available power supply volt-
ages and/or the complexity of the gate drive charge pump
scheme. In 3.3V input designs where an auxiliary 12V
supply is available to power PV
MOSFETs with R
be used with good results. The current drawn from this
supply varies with the MOSFETs used and the LTC3831’s
operating frequency, but is generally less than 50mA.
VOUT
DC(Q1)=
V
IN
and PV , standard
GS
VOUT V – VOUT
CC1
CC2
IN
DC(Q2)=1–
=
specified at V = 5V or 6V can
DS(ON)
V
V
IN
IN
The R
required for a given conduction loss can now
DS(ON)
2
be calculated by rearranging the relation P = I R.
LTC3831 applications that use 5V or lower V voltage and
PMAX(Q1)
V •PMAX(Q1)
IN
IN
RDS(ON)Q1
=
=
=
doubling/tripling charge pumps to generate PV
and
CC1
2
2
DC(Q1) •(ILOAD
PMAX(Q2)
)
VOUT •(ILOAD)
PV , do not provide enough gate drive voltage to fully
CC2
V •PMAX(Q2)
enhance standard power MOSFETs. Under this condition,
IN
RDS(ON)Q2
=
2
2
the effective MOSFET R
may be quite high, raising
DS(ON)
DC(Q2) •(ILOAD
)
(V – VOUT )•(ILOAD
)
IN
the dissipation in the FETs and reducing efficiency. Logic-
level FETs are the recommended choice for 5V or lower
voltage systems. Logic-level FETs can be fully enhanced
with a doubler/tripling charge pump and will operate at
maximum efficiency.
P
MAX
should be calculated based primarily on required
efficiency or allowable thermal dissipation. A typical high
efficiency circuit designed for 2.5V input and 1.25V at 5A
3831fb
13
LTC3831
APPLICATIONS INFORMATION
output might allow no more than 3% efficiency loss at full
higher P
value in the R
calculations generally
MAX
DS(ON)
load for each MOSFET. Assuming roughly 90% efficiency
decreases the MOSFET cost and the circuit efficiency and
increases the MOSFET heat sink requirements.
at this current level, this gives a P
value of:
MAX
(1.25V)(5A/0.9)(0.03) = 0.21W per FET
and a required R of:
Table 1 highlights a variety of power MOSFETs that are
for use in LTC3831 applications.
DS(ON)
Inductor Selection
(2.5V)•(0.21W)
(1.25V)(5A)2
(2.5V)•(0.21W)
(2.5V –1.25V)(5A)2
RDS(ON)Q1
RDS(ON)Q2
=
=
= 0.017Ω
TheinductorisoftenthelargestcomponentinanLTC3831
design and must be chosen carefully. Choose the inductor
value and type based on output slew rate requirements.
The maximum rate of rise of inductor current is set by
the inductor’s value, the input-to-output voltage differen-
tial and the LTC3831’s maximum duty cycle. In a typical
2.5V input 1.25V output application, the maximum rise
time will be:
= 0.017Ω
Note that while the required R
values suggest large
DS(ON)
MOSFETs, the power dissipation numbers are only 0.21W
per device or less; large TO-220 packages and heat sinks
arenotnecessarilyrequiredinhighefficiencyapplications.
Siliconix Si4410DY or International Rectifier IRF7413
(both in SO-8) or Siliconix SUD50N03-10 (TO-252) or ON
SemiconductorMTD20N03HDL(DPAK)aresmallfootprint
DCMAX •(V – VOUT
)
1.138 A
IN
=
LO
LO μs
surface mount devices with R
values below 0.03Ω
DS(ON)
whereL istheinductorvalueinμH.Withproperfrequency
O
at 5V of V that work well in LTC3831 circuits. Using a
GS
compensation,thecombinationoftheinductorandoutput
Table 1. Recommended MOSFETs for LTC3831 Applications
TYPICAL INPUT
CAPACITANCE
R
DS(ON)
PARTS
θ
(°C/W)
T
(°C)
JMAX
JC
AT 25ºC (mΩ)
RATED CURRENT (A)
C
(pF)
ISS
Siliconix SUD50N03-10
T0-252
19
15 at 25°C
3200
2700
880
1.8
175
10 at 100°C
Siliconix Si4410DY
SO-8
20
35
8
10 at 25°C
8 at 70°C
150
150
150
150
150
175
175
150
ON Semiconductor MTD20N03DHL
D PAK
20 at 25°C
16 at 100°C
1.67
25
Fairchild FDS6670A
SO-8
13 at 25°C
3200
2070
4025
1600
3300
1750
Fairchild FDS6680
SO-8
10
9
11.5 at 25°C
25
ON Semiconductor MTB75N03HDL
DS PAK
75 at 25°C
59 at 100°C
1
IR IRL3103S
DD PAK
19
28
37
64 at 25°C
45 at 100°C
1.4
1
IR IRLZ44
TO-220
50 at 25°C
36 at 100°C
Fuji 2SK1388
TO-220
35 at 25°C
2.08
Note: Please refer to the manufacturer’s data sheet for testing conditions and detailed information.
3831fb
14
LTC3831
APPLICATIONS INFORMATION
capacitor values determine the transient recovery time.
In general, a smaller value inductor improves transient
responseattheexpenseofrippleandinductorcoresatura-
tion rating. A 2μH inductor has a 0.57A/μs rise time in this
application,resultingina8.8μsdelayinrespondingtoa5A
loadcurrentstep.Duringthis8.8μs,thedifferencebetween
the inductor current and the output current is made up
by the output capacitor. This action causes a temporary
voltage droop at the output. To minimize this effect, the
inductorvalueshouldusuallybeinthe1μHto5μHrangefor
mostLTC3831circuits.Tooptimizeperformance,different
combinations of input and output voltages and expected
loads may require different inductor values.
short circuit or fault conditions; the inductor should be
sized accordingly to withstand this additional current.
Inductorswithgradualsaturationcharacteristicsareoften
the best choice.
Input and Output Capacitors
A typical LTC3831 design places significant demands on
both the input and the output capacitors. During normal
steady load operation, a buck converter like the LTC3831
draws square waves of current from the input supply at
the switching frequency. The peak current value is equal
to the output load current plus 1/2 the peak-to-peak ripple
current.Mostofthiscurrentissuppliedbytheinputbypass
capacitor. The resulting RMS current flow in the input ca-
pacitor heats it and causes premature capacitor failure in
extreme cases. Maximum RMS current occurs with 50%
PWM duty cycle, giving an RMS current value equal to
Once the required value is known, the inductor core type
can be chosen based on peak current and efficiency re-
quirements. Peak current in the inductor will be equal to
the maximum output load current plus half of the peak-
to-peak inductor ripple current. Ripple current is set by
the inductor value, the input and output voltage and the
operating frequency. The ripple current is approximately
equal to:
I
/2. A low ESR input capacitor with an adequate ripple
OUT
current rating must be used to ensure reliable operation.
Note that capacitor manufacturers’ ripple current ratings
are often based on only 2000 hours (3 months) lifetime at
rated temperature. Further derating of the input capacitor
ripple current beyond the manufacturer’s specification
is recommended to extend the useful life of the circuit.
Lower operating temperature has the largest effect on
capacitor longevity.
(V − VOUT )•(VOUT
)
IN
IRIPPLE
=
fOSC •LO • VIN
f
= LTC3831 oscillator frequency = 200kHz
OSC
L = Inductor value
O
The output capacitor in a buck converter under steady-
state conditions sees much less ripple current than the
input capacitor. Peak-to-peak current is equal to inductor
ripple current, usually 10% to 40% of the total load cur-
rent.Outputcapacitordutyplacesapremiumnotonpower
dissipation but on ESR. During an output load transient,
the output capacitor must supply all of the additional load
current demanded by the load until the LTC3831 adjusts
the inductor current to the new value. ESR in the output
capacitor results in a step in the output voltage equal to
the ESR value multiplied by the change in load current. A
5A load step with a 0.05Ω ESR output capacitor results
in a 250mV output voltage shift; this is 20% of the output
voltage for a 1.25V supply! Because of the strong rela-
tionship between output capacitor ESR and output load
transient response, choose the output capacitor for ESR,
Solving this equation with our typical 2.5V to 1.25V ap-
plication with 2μH inductor, we get:
(2.5V –1.25V)•1.25V
=1.56AP-P
200kHz •2μH•2.5V
Peak inductor current at 5A load:
5A + (1.56A/2) = 5.78A
The ripple current should generally be between 10% and
40% of the output current. The inductor must be able to
withstand this peak current without saturating, and the
copper resistance in the winding should be kept as low
as possible to minimize resistive power loss. Note that in
circuits not employing the current limit function, the cur-
rent in the inductor may rise above this maximum under
3831fb
15
LTC3831
APPLICATIONS INFORMATION
not for capacitance value. A capacitor with suitable ESR
will usually have a larger capacitance value than is needed
to control steady-state output ripple.
The ESR of the output capacitor and the output capacitor
value form a zero at the frequency:
fESR =1/ 2π(ESR)(C
)
⎤
⎦
⎡
OUT
⎣
Electrolytic capacitors, such as the Sanyo MV-WX series,
rated for use in switching power supplies with specified
ripple current ratings and ESR, can be used effectively
in LTC3831 applications. OS-CON electrolytic capaci-
tors from Sanyo and other manufacturers give excellent
performance and have a very high performance/size ratio
for electrolytic capacitors. Surface mount applications
can use either electrolytic or dry tantalum capacitors.
Tantalum capacitors must be surge tested and specified
for use in switching power supplies. Low cost, generic
tantalums are known to have very short lives followed by
explosive deaths in switching power supply applications.
Other capacitor series that can be used include Sanyo
POSCAPs and the Panasonic SP line.
The compensation network used with the error amplifier
must provide enough phase margin at the 0dB crossover
frequency for the overall open-loop transfer function. The
zero and pole from the compensation network are:
f = 1/[2π(R )(C )] and
Z
C
C
f = 1/[2π(R )(C1)] respectively.
P
C
Figure 9b shows the Bode plot of the overall transfer
function.
Althoughamathematicalapproachtofrequencycompensa-
tion can be used, the added complication of input and/or
outputfilters,unknowncapacitorESR,andgrossoperating
A common way to lower ESR and raise ripple current ca-
pability is to parallel several capacitors. A typical LTC3831
application might exhibit 5A input ripple current. Sanyo
OS-CONcapacitors,partnumber10SA220M(220μF/10V),
feature 2.3A allowable ripple current at 85°C; three in
parallel at the input (to withstand the input ripple current)
meet the above requirements. Similarly, Sanyo POSCAP
4TPB470M (470μF/4V) capacitors have a maximum rated
ESRof0.04Ω,threeinparallellowerthenetoutputcapaci-
tor ESR to 0.013Ω.
LTC3831
V
FB
–
+
V
6
TT
COMP
10
ERR
R
C
V
REF
C1
C
C
3831 F09a
Figure 9a. Compensation Pin Hook-Up
Feedback Loop Compensation
The LTC3831 voltage feedback loop is compensated at the
COMP pin, which is the output node of the error amplifier.
The feedback loop is generally compensated with an RC +
C network from COMP to GND as shown in Figure 9a.
f
f
= LTC3831 SWITCHING
FREQUENCY
= CLOSED-LOOP CROSSOVER
FREQUENCY
SW
CO
f
Z
Loop stability is affected by the values of the inductor,
the output capacitor, the output capacitor ESR, the error
amplifier transconductance and the error amplifier com-
pensation network. The inductor and the output capacitor
create a double pole at the frequency:
20dB/DECADE
f
P
FREQUENCY
f
f
ESR
LC
⎡
⎤
f
CO
fLC =1/ 2π (LO)(COUT
)
⎣
⎦
3830 F10b
Figure 9b. Bode Plot of the LTC3831 Overall Transfer Function
3831fb
16
LTC3831
APPLICATIONS INFORMATION
point changes with input voltage, load current variations,
all suggest a more practical empirical method. This can be
done by injecting a transient current at the load and using
an RC network box to iterate toward the final values, or
by obtaining the optimum loop response using a network
analyzer to find the actual loop poles and zeros.
Table 2 shows the suggested compensation component
value for 2.5V to 1.25V applications based on the 470μF
Sanyo POSCAP 4TPB470M output capacitors.
Table 3 shows the suggested compensation component
values for 2.5V to 1.25V applications based on 1500μF
Sanyo MV-WX output capacitors.
Table 2. Recommended Compensation Network for 2.5V to 1.25V
Applications Using Multiple Paralleled 470μF Sanyo
POSCAP 4TPB470M Output Capacitors
Table 3. Recommended Compensation Network for 2.5V to 1.25V
Applications Using Multiple Paralleled 1500μF Sanyo
MV-WX Output Capacitors
L1 (μH)
1.2
C
OUT
(μF)
R (kΩ)
C (nF)
C1(pF)
33
L1 (μH)
1.2
C
OUT
(μF)
R (kΩ)
C (nF)
C1(pF)
120
82
C
C
C
C
1410
2820
4700
1410
2820
4700
1410
2820
4700
6.8
15
22
15
36
47
33
68
120
3.3
3.3
1.5
10
4500
6000
9000
4500
6000
9000
4500
6000
9000
20
27
1.5
1
1.2
33
1.2
1.2
33
1.2
43
0.47
1
56
2.4
33
2.4
51
56
2.4
3.3
4.7
10
10
2.4
62
1
33
2.4
10
2.4
82
0.47
3.3
1
27
4.7
10
4.7
82
33
4.7
22
10
4.7
100
150
15
4.7
10
10
4.7
1
15
PV
V
CC
IN
100Ω
1μF
10k
+
4.7μF
+
V
PV
CC2
CC
C
IN
0.1μF
1μF
PV
PGND
CC1
OPTIONAL
Q1
Q2
TG
LTC3831
GND
MBRS340T3
MBRS340T3
I
MAX
L
O
1k
FREQSET
SHDN
COMP
SS
I
V
OUT
NC
FB
+
R
BG
FB
C1
+
–
C
R
OUT
R
C
GND
PGND
PGND
C
C
SS
C
3830 F11
GND
Figure 10. Typical Schematic Showing Layout Considerations
3831fb
17
LTC3831
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS
tors and the source connection of the bottom MOSFET
Q2. Do not tie this single point ground in the trace run
between the Q2 source and the input capacitor ground,
as this area of the ground plane will be very noisy.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3831. These items are also illustrated graphically
in the layout diagram of Figure 10. The thicker lines show
the high current paths. Note that at 5A current levels or
above, current density in the PC board itself is a serious
concern.Tracescarryinghighcurrentshouldbeaswideas
possible. For example, a PCB fabricated with 2oz copper
requires a minimum trace width of 0.15” to carry 5A.
3. Thesmall-signalresistorsandcapacitorsforfrequency
compensationandsoft-startshouldbelocatedveryclose
to their respective pins and the ground ends connected
to the signal ground pin through a separate trace. Do
not connect these parts to the ground plane!
4. TheV ,PV andPV decouplingcapacitorsshould
CC
CC1
CC2
1. In general, layout should begin with the location of the
power devices. Be sure to orient the power circuitry so
that a clean power flow path is achieved. Conductor
widths should be maximized and lengths minimized.
After you are satisfied with the power path, the control
circuitry should be laid out. It is much easier to find
routes for the relatively small traces in the control cir-
cuits than it is to find circuitous routes for high current
paths.
be as close to the LTC3831 as possible. The 4.7μF and
1μF bypass capacitors shown at V , PV and PV
CC
CC1
CC2
will help provide optimum regulation performance.
5. The (+) plate of C should be connected as close as
IN
possible to the drain of the upper MOSFET, Q1. An ad-
ditional 1μF ceramic capacitor between V and power
IN
ground is recommended.
6. TheV pinisverysensitivetopickupfromtheswitching
FB
node. Care should be taken to isolate V from possible
FB
2. The GND and PGND pins should be shorted directly at
the LTC3831. This helps to minimize internal ground
disturbances in the LTC3831 and prevents differences
in ground potential from disrupting internal circuit
operation. This connection should then tie into the
ground plane at a single point, preferably at a fairly
quiet point in the circuit such as close to the output
capacitors. This is not always practical, however, due
to physical constraints. Another reasonably good point
to make this connection is between the output capaci-
capacitive coupling to the inductor switching signal.
+
7. In a typical SSTL application, if the R pin is to be con-
nected to V , which is also the main supply voltage
DDQ
+
for the switching regulator, do not connect R along the
high current flow path; it should be connected to the
–
SSTL interface supply output. R should be connected
to the interface supply GND.
8. Kelvin sense I
pins.
and I at Q1’s drain and source
MAX
FB
3831fb
18
LTC3831
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
3831fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3831
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PART NUMBER
DESCRIPTION
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LTC1929
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Dual Synchronous Switching Regulator with 5-Bit Desktop VID
1.3V to 3.5V Programmable Core Output Plus I/O Output
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IN
I
Up to 40A
OUT
LTC3413
LTC3713
LTC3778
LTC3717
3A, Monolithic Synchronous Regulator for DDR/QDR
Memory Termination
Low R
Internal Switch: 85mꢀ, 3A Output Current
DS(ON)
(Sink and Source), V
= V /2
REF
OUT
Low Input Voltage, High Power, No R , Step-Down
SENSE
Synchronous Controller
Minimum V : 1.5V, Uses Standard Logic-Level N-Channel
MOSFETs
IN
Wide Operating Range, No R , Step-Down Controller
SENSE
V Up to 36V, Current Mode, Power Good, Stable with
IN
Ceramic C
OUT
Wide V Step-Down Controller for DDR Memory Termination
Current Mode Operation, V
= 1/2 V , V
(V )
IN
OUT
IN OUT TT
Tracks V (V ), No R
, Symmetrical Sink and Source
SENSE
IN DDQ
Output Current Limit
LTC3718
LTC3832
Bus Termination Supply for Low Voltage V
1.5V ≤ V , Generates 5V Gate Drive for Standard N-Ch MOSFETs,
IN
IN
2A ≤ I
≤ 25A
OUT
High Power Synchronous Switching Regulator Controller
V
OUT
as low as 0.6V
No R
is a trademark of Linear Technology Corporation.
SENSE
3831fb
LT 0908 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2001
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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