LTC3832EGN [Linear]
High Power Step-Down Synchronous DC/DC Controllers for Low Voltage Operation; 高功率降压型同步DC / DC控制器，用于低电压操作
| 型号： | LTC3832EGN |
| 厂家： | 
Linear |
| 描述： | High Power Step-Down Synchronous DC/DC Controllers for Low Voltage Operation |
| 文件： | 总24页 (文件大小：317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3832/LTC3832-1
High Power Step-Down
Synchronous DC/DC Controllers
for Low Voltage Operation
U
FEATURES
DESCRIPTIO
The LTC®3832/LTC3832-1 are high power, high effi-
ciency switching regulator controllers optimized for
3.3V-5V to 0.6V-3.xV step-down applications. A preci-
sion internal reference and feedback system provide
±1% output regulation over temperature, load current
andlinevoltagevariations. TheLTC3832/LTC3832-1use
a synchronous switching architecture with N-channel
MOSFETs. Additionally, the chip senses output current
through the drain-source resistance of the upper
N-channelMOSFET, providinganadjustablecurrentlimit
without a current sense resistor.
■
VOUT as Low as 0.6V
■
High Power Switching Regulator Controller
for 3.3V-5V to 0.6V-3.xV Step-Down Applications
■
No Current Sense Resistor Required
■
Low Input Supply Voltage Range: 3V to 8V
■
Maximum Duty Cycle >91% Over Temperature
■
All N-Channel External MOSFETs
■
Excellent Output Regulation: ±1% Over Line, Load
and Temperature Variations
■
High Efficiency: Over 95% Possible
■
Adjustable or Fixed 2.5V Output (LTC3832)
■
Programmable Fixed Frequency Operation: 100kHz to
The LTC3832/LTC3832-1 operate with an input supply
voltage as low as 3V and with a maximum duty cycle of
>91% over temperature. They include a fixed frequency
PWMoscillatorforlowoutputrippleoperation.The300kHz
free-running clock frequency can be externally adjusted or
synchronizedwithanexternalsignalfrom100kHzto500kHz.
In shutdown mode, the LTC3832 supply current drops to
<10µA.TheLTC3832-1istheSO-8versionwithoutcurrent
limit, frequency adjustment and shutdown functions.
, LTC and LT are registered trademarks of Linear Technology Corporation.
500kHz
■
External Clock Synchronization
■
Soft-Start
■
Low Shutdown Current: <10µA
■
Overtemperature Protection
■
Available in SO-8 and SSOP-16 Packages
U
APPLICATIO S
■
CPU Power Supplies
■
Multiple Logic Supply Generator
■
Distributed Power Applications
High Efficiency Power Conversion
■
U
TYPICAL APPLICATIO
V
IN
Efficiency
4.7µF
3V TO 7V
5.1Ω
100
+
V
= 2.5V
OUT
MBR0520T1
90
0.1µF
LTC3832-1
SS
V
/PV
CC
CC2
0.01µF
V
= 1V
80
70
OUT
Si9426DY
Si9426DY
COMP
GND
FB
G1
L1
3.2µH
0.1µF
15k
V
1V
9A
OUT
PV
CC1
G2
60
50
40
6.49k
+
C
OUT
270µF
2V
3832 F01
4.32k
680pF
V
= 3.3V
IN
L1: SUMIDA CDEP105-3R2MC-88
: PANASONIC EEFUEOD271R
0
1
2
3
4
5
6
7
8
9
10
C
OUT
LOAD CURRENT (A)
3832 F01b
Figure 1. High Efficiency 3.3V to 1V Power Converter
sn3832 3832fs
1
LTC3832/LTC3832-1
W W
U W
ABSOLUTE AXI U RATI GS (Note 1)
Supply Voltage
Junction Temperature........................................... 125°C
Operating Temperature Range (Note 9) .. –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
VCC ....................................................................... 9V
PVCC1,2 ................................................................ 14V
Input Voltage
IFB, IMAX ............................................... –0.3V to 14V
SENSE+, SENSE–, FB,
SHDN, FREQSET ....................... –0.3V to VCC + 0.3V
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
ORDER PART
NUMBER
NUMBER
G1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
G2
PV
V
TOP VIEW
PV
CC1
CC2
LTC3832EGN
LTC3832-1ES8
G1
1
2
3
4
8
7
6
5
G2
PGND
GND
CC
PV
V /PV
CC CC2
CC1
I
I
FB
MAX
–
GND
FB
COMP
SS
SENSE
FB
FREQSET
COMP
SS
GN
S8
+
SENSE
PART MARKING
PART MARKING
S8 PACKAGE
8-LEAD PLASTIC SO
SHDN
3832
38321
TJMAX = 125°C, θJA = 130°C/ W
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC, PVCC1, PVCC2 = 5V, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
3
TYP
MAX
8
UNITS
V
Supply Voltage
●
●
5
V
V
V
CC
PV
PV , PV Voltage
CC1 CC2
(Note 7)
3
13.2
2.9
CC
UVLO
FB
V
V
Undervoltage Lockout Voltage
Feedback Voltage
2.4
V
V
= 1.25V
= 1.25V
0.595
0.593
0.6
0.6
0.605
0.607
V
V
COMP
COMP
●
●
V
Output Voltage
2.462
2.450
2.5
2.5
2.538
2.550
V
V
OUT
∆V
Output Load Regulation
Output Line Regulation
I
V
= 0A to 10A (Note 6)
= 4.75V to 5.25V
2
0.1
mV
mV
OUT
OUT
CC
sn3832 3832fs
2
LTC3832/LTC3832-1
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC, PVCC1, PVCC2 = 5V, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
I
f
Supply Current
Figure 2, V
= V
CC
●
●
0.7
1
1.6
10
mA
µA
VCC
SHDN
V
= 0V
SHDN
PV Supply Current
CC
Figure 2, V
= 0V
= V (Note 3)
●
●
20
0.1
30
10
mA
µA
PVCC
SHDN
CC
V
SHDN
Internal Oscillator Frequency
FREQSET Floating
●
230
300
1.2
2.2
2.85
10
360
kHz
OSC
V
V
V
V
V
at Minimum Duty Cycle
at Maximum Duty Cycle
V
SAWL
COMP
COMP
V
V
SAWH
Maximum V
V
= 0V, PV
= 8V
COMPMAX
COMP
FB
CC1
∆f /∆I
Frequency Adjustment
kHz/µA
dB
OSC FREQSET
A
Error Amplifier Open-Loop DC Gain
Measured from FB to COMP,
●
●
50
65
V
+
–
SENSE and SENSE Floating, (Note 4)
g
Error Amplifier Transconductance
Measured from FB to COMP,
1600
2000
2400
µmho
m
+
–
SENSE and SENSE Floating, (Note 4)
I
I
Error Amplifier Output Sink/Source Current
100
µA
COMP
MAX
I
Sink Current
V
= V
CC
8
4
12
12
16
20
µA
µA
MAX
IMAX
(Note 10)
●
I
Sink Current Tempco
V
= V (Note 6)
3300
ppm/°C
MAX
IMAX
CC
V
V
SHDN Input High Voltage
SHDN Input Low Voltage
SHDN Input Current
●
●
●
●
2.4
–8
V
V
IH
IL
0.8
1
I
I
I
V
V
= V
CC
0.1
–12
1.6
µA
µA
mA
IN
SHDN
Soft-Start Source Current
= 0V, V
= 0V, V = V
CC
–18
SS
SS
IMAX
IFB
Maximum Soft-Start Sink Current
In Current Limit
V
V
= V , V = 0V,
IMAX CC IFB
SSIL
= V (Note 8), PV = 8V
SS
CC
CC1
R
R
SENSE Input Resistance
SENSE to FB Resistance
Driver Rise/Fall Time
23.7
18
kΩ
kΩ
ns
ns
%
SENSE
SENSEFB
t , t
r
Figure 2, PV
Figure 2, PV
= PV
= PV
= 5V (Note 5)
= 5V (Note 5)
●
●
●
80
250
250
f
CC1
CC2
CC2
t
Driver Nonoverlap Time
Maximum G1 Duty Cycle
25
91
120
95
NOV
CC1
DC
Figure 2, V = 0V (Note 5), PV
= 8V
MAX
FB
CC1
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 7: PV
must be higher than V by at least 2.5V for G1 to operate
CC1 CC
at 95% maximum duty cycle and for the current limit protection circuit to
be active.
Note 8: The current limiting amplifier can sink but cannot source current.
Under normal (not current limited) operation, the output current will be
zero.
Note 9: The LTC3832E/LTC3832-1E are guaranteed to meet performance
specifications from 0°C to 70°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 3: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This will vary with
the LTC3832 operating frequency, operating voltage and the external FETs
used.
+
Note 4: The open-loop DC gain and transconductance from the SENSE
–
and SENSE pins to COMP pin will be (A )(0.6/2.5) and (g )(0.6/2.5)
Note 10: The minimum and maximum limits for I
over temperature
V
m
MAX
respectively.
includes the intentional temperature coefficient of 3300ppm/°C. This
induced temperature coefficient counteracts the typical temperature
coefficient of the external power MOSFET on-resistance. This results in a
relatively flat current limit over temperature for the application.
Note 5: Rise and fall times are measured using 10% and 90% levels. Duty
cycle and nonoverlap times are measured using 50% levels.
Note 6: Guaranteed by design, not subject to test.
sn3832 3832fs
3
LTC3832/LTC3832-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Error Amplifier Transconductance
vs Temperature
Load Regulation
Line Regulation
0.605
0.604
0.603
0.602
0.601
0.600
0.599
0.598
0.597
0.596
0.595
5
2400
2.54
2.53
2.52
2.51
T
A
= 25°C
T
= 25°C
A
4
REFER TO FIGURE 12
2300
2200
3
2
2100
2000
1900
1800
1700
1
2.50
2.49
0
–1
–2
–3
–4
–5
2.48
2.47
2.46
1600
–10
–5
5
4
6
–25
0
50
75 100 125
–15
10
15
3
5
7
8
–50
25
0
OUTPUT CURRENT (A)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
3832 G01
3832 G02
3832 G03
Error Amplifier Sink/Source
Current vs Temperature
Error Amplifier Open-Loop Gain
vs Temperature
Output Voltage Temperature Drift
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
50
70
65
60
55
200
REFER TO FIGURE 12
OUTPUT = NO LOAD
40
180
160
140
120
100
80
30
20
10
0
–10
–20
–30
–40
–50
60
50
40
–50
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–25
–25
0
50
75 100 125
–50
25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3832 G04
3832 G06
3830 G05
Oscillator Frequency
vs Temperature
Oscillator Frequency
Oscillator (VSAWH – VSAWL
)
vs FREQSET Input Current
vs External Sync Frequency
360
350
340
330
320
310
300
290
280
270
260
250
240
700
600
500
400
300
200
100
0
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
FREQSET FLOATING
T
A
= 25°C
T = 25°C
A
–50
0
25
50
75 100 125
–25
10
FREQSET INPUT CURRENT (µA)
30
–30 –20
–10
0
20
100
200
300
400
500
TEMPERATURE (°C)
EXTERNAL SYNC FREQUENCY (kHz)
3832 G07
3832 G08
3832 G09
sn3832 3832fs
4
LTC3832/LTC3832-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum G1 Duty Cycle
vs Temperature
IMAX Sink Current
vs Temperature
Output Overcurrent Protection
3.0
100
99
98
97
96
95
94
93
92
20
18
16
14
12
10
8
V
= 0V
T = 25°C
A
REFER TO FIGURE 12
FB
REFER TO FIGURE 3
2.5
2.0
1.5
1.0
0.5
0
6
91
4
0
2
4
6
8
10 12 14 16 18 20
–50 –25
0
25
125
–50 –25
0
25
50
75 100 125
50
75 100
OUTPUT CURRENT (A)
TEMPERATURE (°C)
TEMPERATURE (°C)
3832 G12
3832 G10
3832 G11
Output Current Limit Threshold
vs Temperature
Soft-Start Source Current
vs Temperature
Soft-Start Sink Current
vs (VIFB – VIMAX
)
20
19
18
17
16
15
14
13
12
11
10
–8
–9
2.00
1.75
1.50
1.25
T
= 25°C
REFER TO FIGURE 12 AND NOTE 10 OF
THE ELECTRICAL CHARACTERISTICS
A
–10
–11
–12
–13
–14
–15
–16
1.00
0.75
0.50
0.25
0
–50
0
25
50
75 100 125
–25
–25
0
50
75 100 125
–125 –100
–50
–50
25
–150
–25
0
–75
TEMPERATURE (°C)
TEMPERATURE (°C)
V
– V
(mV)
IMAX
IFB
3832 G13
3830 G14
3832 G15
Undervoltage Lockout Threshold
Voltage vs Temperature
VCC Operating Supply Current
vs Temperature
PVCC Supply Current
vs Oscillator Frequency
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
90
80
70
60
50
40
30
20
10
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
T
= 25°C
FREQSET FLOATING
A
G1 AND G2 LOADED
WITH 6800pF,
PV
= 12V
CC1,2
G1 AND G2
LOADED
G1 AND G2
LOADED
WITH 6800pF,
PV
WITH 1000pF,
= 5V
CC1,2
PV
= 5V
CC1,2
0
–50
0
25
50
75 100 125
–25
–50
0
25
50
75 100 125
0
400
500
–25
100
200
300
TEMPERATURE (°C)
TEMPERATURE (°C)
OSCILLATOR FREQUENCY (kHz)
3832 G16
3832 G17
3832 G18
sn3832 3832fs
5
LTC3832/LTC3832-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
PVCC Supply Current
vs Gate Capacitance
G1 Rise/Fall Time
vs Gate Capacitance
Transient Response
80
70
60
50
40
30
20
10
0
200
180
160
140
120
100
80
T
= 25°C
T
= 25°C
A
A
VOUT
50mV/DIV
PV
= 12V
t AT PV
f
= 5V
CC1,2
CC1,2
ILOAD
2AV/DIV
t AT PV
r
= 5V
CC1,2
PV
6
= 5V
CC1,2
60
40
50µs/DIV
3832 G21
t AT PV
f
= 12V
CC1,2
20
t AT PV
r
= 12V
CC1,2
0
0
1
2
3
4
5
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
GATE CAPACITANCE AT G1 AND G2 (nF)
GATE CAPACITANCE AT G1 AND G2 (nF)
3832 G19
3832 G20
U
U
U
PI FU CTIO S (LTC3832/LTC3832-1)
G1 (Pin 1/Pin 1): Top Gate Driver Output. Connect this pin
to the gate of the upper N-channel MOSFET, Q1. This
output swings from PGND to PVCC1. It remains low if G2
is high or during shutdown mode.
dividertosettheoutputvoltage,floatSENSE+ andSENSE–
andconnecttheexternalresistordividertoFB.Theinternal
resistor divider is not included in the LTC3832-1.
SHDN (Pin 8/NA): Shutdown. A TTL compatible low level
at SHDN for longer than 100µs puts the LTC3832 into
shutdown mode. In shutdown, G1 and G2 go low, all
internal circuits are disabled and the quiescent current
drops to 10µA max. A TTL compatible high level at SHDN
allows the part to operate normally. This pin also doubles
as an external clock input to synchronize the internal
oscillator with an external clock. The shutdown function is
disabled in the LTC3832-1.
PVCC1 (Pin 2/Pin 2): Power Supply Input for G1. Connect
this pin to a potential of at least VIN + VGS(ON)(Q1). This
potential can be generated using an external supply or
charge pump.
PGND (Pin 3/Pin 3): Power Ground. Both drivers return to
this pin. Connect this pin to a low impedance ground in
close proximity to the source of Q2. Refer to the Layout
Consideration section for more details on PCB layout
techniques. The LTC3832-1 has PGND and GND tied
together internally at Pin 3.
SS(Pin9/Pin5):Soft-Start.Connectthispintoanexternal
capacitor, CSS, to implement a soft-start function. If the
LTC3832 goes into current limit, CSS is discharged to
reduce the duty cycle. CSS must be selected such that
during power-up, the current through Q1 will not exceed
the current limit level.
GND (Pin 4/Pin 3): Signal Ground. All low power internal
circuitry returns to this pin. To minimize regulation errors
due to ground currents, connect GND to PGND right at the
LTC3832.
COMP (Pin 10/Pin 6): External Compensation. This pin
internally connects to the output of the error amplifier and
inputofthePWMcomparator.UseaRC+Cnetworkatthis
pin to compensate the feedback loop to provide optimum
transient response.
SENSE–, FB, SENSE+ (Pins 5, 6, 7/Pin 4): These three
pinsconnecttotheinternalresistordividerandinputofthe
error amplifier. To use the internal divider to set the output
voltage to 2.5V, connect SENSE+ to the positive terminal
of the output capacitor and SENSE– to the negative termi-
nal. FB should be left floating. To use an external resistor
sn3832 3832fs
6
LTC3832/LTC3832-1
U
U
U
PI FU CTIO S
VCC (Pin 14/Pin 7): Power Supply Input. All low power
internal circuits draw their supply from this pin. Connect
this pin to a clean power supply, separate from the main
VIN supply at the drain of Q1. This pin requires a 4.7µF
bypass capacitor. The LTC3832-1has VCC and PVCC2 tied
together at Pin 7 and requires a 10µF bypass capacitor to
GND.
FREQSET (Pin 11/NA): Frequency Set. Use this pin to
adjustthefree-runningfrequencyoftheinternaloscillator.
With the pin floating, the oscillator runs at about 300kHz.
A resistor from FREQSET to ground speeds up the oscil-
lator; a resistor to VCC slows it down.
IMAX (Pin 12/NA): Current Limit Threshold Set. IMAX sets
the threshold for the internal current limit comparator. If
PVCC2 (Pin15/Pin7):PowerSupplyInputforG2. Connect
this pin to the main high power supply.
IFB drops below IMAX with G1 on, the LTC3832 goes into
current limit. IMAX has an internal 12µA pull-down to GND.
Connect this pin to the main VIN supply at the drain of Q1,
through an external resistor to set the current limit thresh-
old. Connect a 0.1µF decoupling capacitor across this
resistor to filter switching noise.
G2 (Pin 16/Pin 8): Bottom Gate Driver Output. Connect
this pin to the gate of the lower N-channel MOSFET, Q2.
This output swings from PGND to PVCC2. It remains low
when G1 is high or during shutdown mode. To prevent
output undershoot during a soft-start cycle, G2 is held low
until G1 first goes high (FFBG in the Block Diagram).
I
FB (Pin 13/NA): Current Limit Sense. Connect this pin to
the switching node at the source of Q1 and the drain of Q2
througha1kresistor.The1kresistorisrequiredtoprevent
voltage transients from damaging IFB.This pin is used for
sensing the voltage drop across the upper N-channel
MOSFET, Q1.
W
BLOCK DIAGRA
(LTC3832)
DISABLE GATE DRIVE
LOGIC AND
THERMAL SHUTDOWN
SHDN
100µs DELAY
POWER DOWN
INTERNAL
OSCILLATOR
PV
G1
PV
G2
CC1
–
FREQSET
COMP
S
R
Q
Q
PWM
CC2
+
FFBG
12µA
S
R
Q
ENABLE
G2
PGND
SS
QSS
POR
V
CC
MAX
ERR
GND
+
–
+
–
FB
18k
+
–
V
REF
+ 10%
SENSE
V
REF
5.7k
I
FB
SENSE
–
CC
V
REF
BG
+
I
MAX
V
REF
+ 10%
3832 BD
12µA
2.2V
1.2V
DISABLE
LIM
QC
I
PV
CC1
+
V
V
CC
+ 2.5V
–
sn3832 3832fs
7
LTC3832/LTC3832-1
W
BLOCK DIAGRA
(LTC3832-1)
DISABLE GATE DRIVE
THERMAL SHUTDOWN
POWER DOWN
INTERNAL
OSCILLATOR
PV
G1
V
CC1
–
+
S
R
Q
Q
PWM
/PV
CC
CC2
COMP
SS
G2
FFG2
12µA
S
Q
ENABLE
G2
PGND
FB
QSS
MAX
POR
R
ERR
+
–
+
–
V
REF
2.2V
1.2V
V
+ 10%
REF
QC
PV
+
–
CC1
V
V
REF
BG
V
CC
+ 2.5V
V
+ 10%
REF
3832 BD2
TEST CIRCUITS
5V
PV
CC
V
V
V
+
SHDN
CC
CC
0.1µF
10µF
SHDN
PV
PV
I
I
FB
V
PV
PV
CC1 CC2
CC2
CC1
FB
CC
G1 RISE/FALL
NC
NC
NC
NC
FB
SS
FREQSET
COMP
G1
V
COMP
G1
G2
COMP
6800pF
6800pF
6800pF
LTC3832
LTC3832
GND
G2 RISE/FALL
I
G2
+
V
FB
I
MAX
FB
–
PGND
6800pF
MAX
GND
PGND SENSE
SENSE
3832 F03
3832 F02
Figure 2
Figure 3
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APPLICATIO S I FOR ATIO
OVERVIEW
feedback and control circuitry to form a complete switch-
ing regulator circuit. The PWM loop nominally runs at
300kHz.
The LTC3832/LTC3832-1 are voltage mode feedback,
synchronous switching regulator controllers (see Block
Diagram) designed for use in high power, low voltage
step-down (buck) converters. They include an onboard
PWM generator, a precision reference trimmed to ±0.8%,
two high power MOSFET gate drivers and all necessary
The LTC3832 includes a current limit sensing circuit that
uses the topside external N-channel power MOSFET as a
current sensing element, eliminating the need for an
external sense resistor.
sn3832 3832fs
8
LTC3832/LTC3832-1
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APPLICATIO S I FOR ATIO
U
Also included in the LTC3832 is an internal soft-start
feature that requires only a single external capacitor to
operate. In addition, the LTC3832 features an adjustable
oscillator that can free run or synchronize to external
signalwithfrequenciesfrom100kHz to500kHz,allowing
added flexibility in external component selection. The
LTC3832-1 does not include current limit, frequency
adjustability, external synchronization and the shutdown
function.
Thermal Shutdown
The LTC3832/LTC3832-1 have a thermal protection cir-
cuit that disables both gate drivers if activated. If the chip
junction temperature reaches 150°C, both G1 and G2 are
pulled low. G1 and G2 remain low until the junction
temperature drops below 125°C, after which, the chip
resumes normal operation.
Soft-Start and Current Limit
The LTC3832 includes a soft-start circuit that is used for
start-up and current limit operation. The LTC3832-1 only
has the soft-start function; the current limit function is
disabled. The SS pin requires an external capacitor, CSS,
to GND with the value determined by the required soft-
start time. An internal 12µA current source is included to
chargeCSS. Duringpower-up, theCOMPpinisclampedto
a diode drop (B-E junction of QSS in the Block Diagram)
above the voltage at the SS pin. This prevents the error
amplifier from forcing the loop to maximum duty cycle.
The LTC3832/LTC3832-1 operate at low duty cycle as the
SS pin rises above 0.6V (VCOMP ≈ 1.2V). As SS continues
to rise, QSS turns off and the error amplifier takes over to
regulate the output.
THEORY OF OPERATION
Primary Feedback Loop
The LTC3832/LTC3832-1 sense the output voltage of the
circuit at the output capacitor and feeds this voltage back
to the internal transconductance error amplifier, ERR,
through a resistor divider network. The error amplifier
compares the resistor-divided output voltage to the inter-
nal 0.6V reference and outputs an error signal to the PWM
comparator. This error signal is compared with a fixed
frequency ramp waveform, from the internal oscillator, to
generateapulsewidthmodulatedsignal.ThisPWMsignal
drives the external MOSFETs through the G1 and G2 pins.
TheresultingchoppedwaveformisfilteredbyLO andCOUT
which closes the loop. Loop compensation is achieved
with an external compensation network at the COMP pin,
the output node of the error amplifier.
The LTC3832 includes yet another feedback loop to con-
trol operation in current limit. Just before every falling
edge of G1, the current comparator, CC, samples and
holds the voltage drop measured across the external
upperMOSFET,Q1,attheIFB pin.CCcomparesthevoltage
at IFB to the voltage at the IMAX pin. As the peak current
rises,themeasuredvoltageacrossQ1increasesduetothe
drop across the RDS(ON) of Q1. When the voltage at IFB
drops below IMAX, indicating that Q1’s drain current has
exceeded the maximum level, CC starts to pull current out
of CSS, cutting the duty cycle and controlling the output
current level. The CC comparator pulls current out of the
SS pin in proportion to the voltage difference between IFB
and IMAX. Under minor overload conditions, the SS pin
falls gradually, creating a time delay before current limit
takes effect. Very short, mild overloads may not affect the
output voltage at all. More significant overload conditions
allow the SS pin to reach a steady state, and the output
MAX Feedback Loop
An additional comparator in the feedback loop provides
high speed output voltage correction in situations where
the error amplifier may not respond quickly enough. MAX
comparesthefeedbacksignaltoavoltage60mVabovethe
internal reference. If the signal is above the comparator
threshold, the MAX comparator overrides the error ampli-
fier and forces the loop to minimum duty cycle, 0%. To
prevent this comparator from triggering due to noise, the
MAX comparator’s response time is deliberately delayed
by two to three microseconds. This comparator helps
prevent extreme output perturbations with fast output
load current transients, while allowing the main feedback
loop to be optimally compensated for stability.
sn3832 3832fs
9
LTC3832/LTC3832-1
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APPLICATIO S I FOR ATIO
remains at a reduced voltage until the overload is re-
moved. Serious overloads generate a large overdrive at
CC, allowing it to pull SS down quickly and preventing
damage to the output components. By using the RDS(ON)
of Q1 to measure the output current, the current limiting
circuiteliminatesanexpensivediscretesenseresistorthat
would otherwise be required. This helps minimize the
number of components in the high current path.
meant to prevent damage to the power supply circuitry
during fault conditions. The exact current level where the
limiting circuit begins to take effect will vary from unit to
unit as the RDS(ON) of Q1 varies. Typically, RDS(ON) varies
as much as ±40%, and with ±33% variation on the
LTC3832’sIMAX current, thiscangivea±73%variationon
the current limit threshold.
The RDS(ON) is high if the VGS applied to the MOSFET is
low. This occurs during power up when PVCC1 is ramping
up.TopreventthehighRDS(ON) fromactivatingthecurrent
limit, the LTC3832 will disable the current limit circuit if
PVCC1 is less than 2.5V above VCC. To ensure proper
operation of the current limit circuit, PVCC1 must be at
least 2.5V above VCC when G1 is high. PVCC1 can go low
when G1 is low, allowing the use of the external charge
The current limit threshold can be set by connecting an
external resistor RIMAX from the IMAX pin to the main VIN
supply at the drain of Q1. The value of RIMAX is determined
by:
R
IMAX = (ILMAX)(RDS(ON)Q1)/IIMAX
where:
ILMAX = ILOAD + (IRIPPLE/2)
pump to power PVCC1
.
V
IN
ILOAD = Maximum load current
IRIPPLE = Inductor ripple current
LTC3832
+
+
R
0.1µF
IMAX
C
IN
+
12
V – V
V
OUT
(
OUT)(
)
IN
I
=
MAX
12µA
CC
G1
G2
Q1
f
L
V
( )(
)
(
)
OSC
O IN
I
FB
L
O
1k
V
13
–
OUT
fOSC = LTC3832 oscillator frequency = 300kHz
Q2
C
OUT
LO = Inductor value
3832 F04
RDS(ON)Q1 = On-resistance of Q1 at ILMAX
IIMAX= Internal 12µA sink current at IMAX
Figure 4. Current Limit Setting
Oscillator Frequency
The RDS(ON) of Q1 usually increases with temperature. To
keep the current limit threshold constant, the internal
12µA sink current at IMAX is designed with a positive
temperature coefficient to provide first order correction
The LTC3832 includes an onboard current controlled
oscillator that typically free-runs at 300kHz. The oscillator
frequencycanbeadjustedbyforcingcurrentintooroutof
the FREQSET pin. With the pin floating, the oscillator runs
at about 300kHz. Every additional 1µA of current into/out
oftheFREQSETpindecreases/increasesthefrequencyby
10kHz. The pin is internally servoed to 1.265V. The
frequency can be estimated as:
for the temperature coefficient of RDS(ON)Q1
.
Inorderforthecurrentlimitcircuittooperateproperlyand
toobtainareasonablyaccuratecurrentlimitthreshold,the
IMAX and IFB pins must be Kelvin sensed at Q1’s drain and
source pins. In addition, connect a 0.1µF decoupling
capacitor across RIMAX to filter switching noise. Other-
wise, noise spikes or ringing at Q1’s source can cause the
actual maximum current to be greater than the desired
I
1.265V – VEXT 10kHz
f = 300kHz +
•
RFSET
1µA
current limit set point. Due to switching noise and varia- where RFSET is a frequency programming resistor con-
tion of RDS(ON), the actual current limit trip point is not nected between FREQSET and the external voltage source
highly accurate. The current limiting circuitry is primarily VEXT
.
sn3832 3832fs
10
LTC3832/LTC3832-1
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APPLICATIO S I FOR ATIO
U
Connecting a 82k resistor from FREQSET to ground
forces 15µA out of the pin, causing the internal oscillator
to run at approximately 450kHz. Forcing an external 20µA
current into FREQSET cuts the internal frequency to
100kHz. An internal clamp prevents the oscillator from
running slower than about 50kHz. Tying FREQSET to VCC
forces the chip to run at this minimum speed. The
LTC3832-1 does not have this frequency adjustment
function.
Figure 5 describes the operation of the conventional
synchronization function. A negative transition at the
SHDN pin forces the internal ramp signal low to restart a
newPWMcycle.Noticethattherampamplitudeislowered
as the external clock frequency goes higher. The effect of
this decrease in ramp amplitude increases the open-loop
gain of the controller feedback loop. As a result, the loop
crossover frequency increases and it may cause the feed-
backlooptobeunstableifthephasemarginisinsufficient.
To overcome this problem, the LTC3832 monitors the
peak voltage of the ramp signal and adjusts the oscillator
charging current to maintain a constant ramp peak.
Shutdown
The LTC3832 includes a low power shutdown mode,
controlled by the logic at the SHDN pin. A high at SHDN
allowstheparttooperatenormally.AlowlevelatSHDNfor
more than 100µs forces the LTC3832 into shutdown
mode.Inthismode,allinternalswitchingstops,theCOMP
and SS pins pull to ground and Q1 and Q2 turn off. The
LTC3832 supply current drops to <10µA, although off-
state leakage in the external MOSFETs may cause the total
VIN current to be some what higher, especially at elevated
temperatures. If SHDN returns high, the LTC3832 reruns
a soft-start cycle and resumes normal operation. The
LTC3832-1 does not have this shutdown function.
SHDN
300kHz
FREE RUNNING
RAMP SIGNAL
RAMP SIGNAL
WITH EXT SYNC
TRADITIONAL
SYNC METHOD
WITH EARLY
RAMP
TERMINATION
External Clock Synchronization
The LTC3832 SHDN pin doubles as an external clock
input for applications that require a synchronized clock.
An internal circuit forces the LTC3832 into external
synchronizationmodeifanegativetransitionattheSHDN
pin is detected. In this mode, every negative transition on
the SHDN pin resets the internal oscillator and pulls the
ramp signal low, this forces the LTC3832 internal oscil-
latortolocktotheexternalclockfrequency.TheLTC3832-1
does not have this external synchronization function.
RAMP AMPLITUDE
ADJUSTED
LTC3832
KEEPS RAMP
AMPLITUDE
CONSTANT
UNDER SYNC
3832 F05
Figure 5. External Synchronization Operation
TheLTC3832internaloscillatorcanbeexternallysynchro-
nized from 100kHz to 500kHz. Frequencies above 300kHz
can cause a decrease in the maximum obtainable duty
cycle as rise/fall time and propagation delay take up a
larger percentage of the switch cycle. Circuits using these
frequencies should be checked carefully in applications
where operation near dropout is important—like 3.3V to
2.5V converters. The low period of this clock signal must
not be >100µs, or else the LTC3832 enters shutdown
mode.
Input Supply Considerations/Charge Pump
TheLTC3832requiresfoursupplyvoltagestooperate:VIN
for the main power input, PVCC1 and PVCC2 for MOSFET
gate drive and a clean, low ripple VCC for the LTC3832
internal circuitry (Figure 6). The LTC3832-1 has the PVCC2
and VCC pins tied together inside the package (Figure 7).
This pin, brought out as VCC/PVCC2, has the same low
ripplerequirementsastheLTC3832, butmustalsobeable
to supply the gate drive current to Q2.
sn3832 3832fs
11
LTC3832/LTC3832-1
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APPLICATIO S I FOR ATIO
V
CC
PV
CC2
PV
CC1
V
IN
Figure 8 shows a tripling charge pump circuit that can be
used to provide 2VIN and 3VIN gate drive for the external
top and bottom MOSFETs respectively. These should fully
enhance MOSFETs with 5V logic level thresholds. This
circuit provides 3VIN – 3VF to PVCC1 while Q1 is ON and
2VIN – 2VF to PVCC2 where VF is the forward voltage of the
Schottky diodes. The circuit requires the use of Schottky
diodes to minimize forward drop across the diodes at
start-up. The tripling charge pump circuit can rectify any
ringing at the drain of Q2 and provide more than 3VIN at
PVCC1; a 12V zener diode should be included from PVCC1
to PGND to prevent transients from damaging the circuitry
at PVCC1 or the gate of Q1.
G1
G2
Q1
L
O
INTERNAL
CIRCUITRY
V
OUT
+
C
Q2
OUT
3832 F6
LTC3832
Figure 6. LTC3832 Power Supplies
V
CC
/PV
PV
CC1
V
IN
CC2
The charge pump capacitors for PVCC1 refresh when the
G2 pin goes high and the switch node is pulled low by Q2.
The G2 on-time becomes narrow when LTC3832/
LTC3832-1 operates at a maximum duty cycle (95%
typical), which can occur if the input supply rises more
slowly than the soft-start capacitor or if the input voltage
droops during load transients. If the G2 on-time gets so
narrow that the switch node fails to pull completely to
ground, the charge pump voltage may collapse or fail to
start, causing excessive dissipation in external MOSFET,
Q1. This condition is most likely with low VCC voltages and
high switching frequencies, coupled with large external
MOSFETs which slow the G2 and switch node slew rates.
G1
G2
Q1
L
O
INTERNAL
CIRCUITRY
V
OUT
+
C
Q2
OUT
3832 F7
LTC3832-1
Figure 7. LTC3832-1 Power Supplies
In many applications, VCC can be powered from VIN
through an RC filter. This supply can be as low as 3V. The
low quiescent current (typically 800µA) allows the use of
relatively large filter resistors and correspondingly small
filter capacitors. 100Ω and 4.7µF usually provide ad-
equatefilteringforVCC. Forbestperformance, connectthe
4.7µFbypasscapacitorasclosetotheLTC3832VCC pinas
possible.
TheLTC3832/LTC3832-1overcomethisproblembysens-
ingthePVCC1 voltagewhenG1ishigh. IfPVCC1 islessthan
2.5V above VCC, the maximum G1 duty cycle is reduced to
70% by clamping the COMP pin at 1.8V (QC in the Block
Gate drive for the top N-channel MOSFET Q1 is supplied
from PVCC1. This supply must be above VIN (the main
powersupplyinput)byatleastonepowerMOSFETVGS(ON)
forefficientoperation.AninternallevelshifterallowsPVCC1
to operate at voltages above VCC and VIN, up to 14V maxi-
mum. This higher voltage can be supplied with a separate
supply, or it can be generated using a charge pump.
D
1N5817
Z
V
IN
12V
1N5242
1N5817
1N5817
0.1µF
10µF
PV
CC2
PV
CC1
0.1µF
G1
Q1
L
O
V
OUT
Gate drive for the bottom MOSFET Q2 is provided through
PVCC2 for the LTC3832 or VCC/PVCC2 for the LTC3832-1.
This supply only needs to be above the power MOSFET
VGS(ON) for efficient operation. PVCC2 can also be driven
fromthesamesupply/chargepumpforthePVCC1,oritcan
be connected to a lower supply to improve efficiency.
+
G2
Q2
C
OUT
3832 F08
LTC3832
Figure 8. Tripling Charge Pump
sn3832 3832fs
12
LTC3832/LTC3832-1
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APPLICATIO S I FOR ATIO
U
Diagram). This increases the G2 on-time and allows the
enhance standard power MOSFETs. Under this condition,
the effective MOSFET RDS(ON) may be quite high, raising
the dissipation in the FETs and reducing efficiency. Logic
level FETs are the recommended choice for 5V or lower
voltage systems. Logic level FETs can be fully enhanced
with a doubler/tripling charge pump and will operate at
maximum efficiency.
charge pump capacitors to be refreshed.
For applications using an external supply to PVCC1, this
supply must also be higher than VCC by at least 2.5V to
ensure normal operation.
For applications with a 5V or higher VIN supply, PVCC2 can
be tied to VIN if a logic level MOSFET is used. PVCC1 can be
supplied using a doubling charge pump as shown in
Figure 9. This circuit provides 2VIN – VF to PVCC1 while Q1
is ON.
AftertheMOSFETthresholdvoltageisselected,choosethe
R
DS(ON) based on the input voltage, the output voltage,
allowablepowerdissipationandmaximumoutputcurrent.
InatypicalLTC3832circuit,operatingincontinuousmode,
the average inductor current is equal to the output load
current.ThiscurrentflowsthrougheitherQ1orQ2withthe
power dissipation split up according to the duty cycle:
V
IN
OPTIONAL
USE FOR V ≥ 7V
MBR0530T1
IN
D
Z
PV
CC2
PV
CC1
12V
0.1µF
1N5242
VOUT
V
IN
G1
DC(Q1) =
Q1
L
O
VOUT V – VOUT
IN
V
OUT
DC(Q2) = 1–
=
V
V
IN
+
G2
IN
Q2
C
OUT
The RDS(ON) required for a given conduction loss can now
be calculated by rearranging the relation P = I2R.
3832 F09
LTC3832
Figure 9. Doubling Charge Pump
PMAX(Q1)
DC(Q1)•(ILOAD
PMAX(Q2)
V •PMAX(Q1)
IN
RDS(ON)Q1
RDS(ON)Q2
=
=
=
2
2
Power MOSFETs
)
VOUT •(ILOAD
)
Two N-channel power MOSFETs are required for most
LTC3832 circuits. These should be selected based
primarilyonthresholdvoltageandon-resistanceconsid-
erations. Thermal dissipation is often a secondary con-
cern in high efficiency designs. The required MOSFET
threshold should be determined based on the available
power supply voltages and/or the complexity of the gate
drive charge pump scheme. In 3.3V input designs where
an auxiliary 12V supply is available to power PVCC1 and
PVCC2, standard MOSFETs with RDS(ON) specified at VGS
= 5V or 6V can be used with good results. The current
drawn from this supply varies with the MOSFETs used
and the LTC3832’s operating frequency, but is generally
less than 50mA.
V •PMAX(Q2)
IN
=
2
2
DC(Q2)•(ILOAD
)
(V – VOUT)•(ILOAD)
IN
PMAX should be calculated based primarily on required
efficiency or allowable thermal dissipation. A typical high
efficiency circuit designed for 3.3V input and 2.5V at 10A
output might allow no more than 3% efficiency loss at full
load for each MOSFET. Assuming roughly 90% efficiency
at this current level, this gives a PMAX value of:
(2.5V)(10A/0.9)(0.03) = 0.83W per FET
and a required RDS(ON) of:
(3.3V)•(0.83W)
RDS(ON)Q1
RDS(ON)Q2
=
=
= 0.011Ω
(2.5V)(10A)2
LTC3832 applications that use 5V or lower VIN voltage and
a doubling/tripling charge pump to generate PVCC1 and
PVCC2, do not provide enough gate drive voltage to fully
(3.3V)•(0.83W)
(3.3V – 2.5V)(10A)2
= 0.034Ω
sn3832 3832fs
13
LTC3832/LTC3832-1
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APPLICATIO S I FOR ATIO
Note that the required RDS(ON) for Q2 is roughly three the LTC3832’s maximum duty cycle. In a typical 3.3V in-
times that of Q1 in this example. Note also that while the put,2.5Voutputapplication,themaximumrisetimewillbe:
required RDS(ON) values suggest large MOSFETs, the
DCMAX •(V – VOUT
)
0.76 A
LO µs
IN
power dissipation numbers are only 0.83W per device or
less; large TO-220 packages and heat sinks are not neces-
sarily required in high efficiency applications. Siliconix
Si4410DY or International Rectifier IRF7413 (both in
SO-8) or Siliconix SUD50N03-10 (TO-252) or ON Semi-
conductor MTD20N03HDL (DPAK) are small footprint
surface mount devices with RDS(ON) values below 0.03Ω
at 5V of VGS that work well in LTC3832 circuits. Using a
higher PMAX value in the RDS(ON) calculations generally
decreases the MOSFET cost and the circuit efficiency and
increases the MOSFET heat sink requirements.
=
LO
where LO is the inductor value in µH. With proper fre-
quency compensation, the combination of the inductor
andoutputcapacitorvaluesdeterminethetransientrecov-
ery time. In general, a smaller value inductor improves
transient response at the expense of ripple and inductor
core saturation rating. A 1µH inductor has a 0.76A/µs rise
time in this application, resulting in a 6.6µs delay in
responding to a 5A load current step. During this 6.6µs,
thedifferencebetweentheinductorcurrentandtheoutput
current is made up by the output capacitor. This action
causes a temporary voltage droop at the output. To
minimize this effect, the inductor value should usually be
in the 1µH to 5µH range for most 3.3V input LTC3832
circuits. To optimize performance, different combinations
of input and output voltages and expected loads may
require different inductor values.
Table 1 highlights a variety of power MOSFETs for use in
LTC3832 applications.
Inductor Selection
TheinductorisoftenthelargestcomponentinanLTC3832
design and must be chosen carefully. Choose the inductor
valueandtypebasedonoutputslewraterequirements.The
maximum rate of rise of inductor current is set by the
inductor’svalue,theinput-to-outputvoltagedifferentialand
Once the required value is known, the inductor core type
can be chosen based on peak current and efficiency
Table 1. Recommended MOSFETs for LTC3832 Applications
TYPICAL INPUT
CAPACITANCE
R
DS(ON)
PARTS
AT 25°C (mΩ)
RATED CURRENT (A)
C
(pF)
θ
(°C/W)
T
JMAX
(°C)
ISS
JC
Siliconix SUD50N03-10
TO-252
19
15 at 25°C
3200
2700
880
1.8
175
10 at 100°C
Siliconix Si4410DY
SO-8
20
35
8
10 at 25°C
8 at 70°C
150
150
150
150
150
175
175
150
ON Semiconductor MTD20N03HDL
DPAK
20 at 25°C
16 at 100°C
1.67
25
Fairchild FDS6670A
S0-8
13 at 25°C
3200
2070
4025
1600
3300
1750
Fairchild FDS6680
SO-8
10
9
11.5 at 25°C
25
ON Semiconductor MTB75N03HDL
DD PAK
75 at 25°C
59 at 100°C
1
IR IRL3103S
DD PAK
19
28
37
64 at 25°C
45 at 100°C
1.4
1
IR IRLZ44
TO-220
50 at 25°C
36 at 100°C
Fuji 2SK1388
TO-220
35 at 25°C
2.08
Note: Please refer to the manufacturer’s data sheet for testing conditions and detailed information.
sn3832 3832fs
14
LTC3832/LTC3832-1
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APPLICATIO S I FOR ATIO
U
to IOUT/2. A low ESR input capacitor with an adequate
ripple current rating must be used to ensure reliable
operation. Note that capacitor manufacturers’ ripple cur-
rentratingsareoftenbasedononly2000hours(3months)
lifetime at rated temperature. Further derating of the input
capacitor ripple current beyond the manufacturer’s speci-
fication is recommended to extend the useful life of the
circuit. Loweroperatingtemperaturehasthelargesteffect
on capacitor longevity.
requirements. Peak current in the inductor will be equal to
the maximum output load current plus half of the peak-to-
peak inductor ripple current. Ripple current is set by the
inductor value, the input and output voltage and the
operating frequency. The ripple current is approximately
equal to:
(V − VOUT)•(VOUT
)
IN
IRIPPLE
=
fOSC •LO • V
IN
fOSC = LTC3832 oscillator frequency = 300kHz
LO = Inductor value
The output capacitor in a buck converter under steady-
state conditions sees much less ripple current than the
input capacitor. Peak-to-peak current is equal to inductor
ripple current, usually 10% to 40% of the total load
current. Output capacitor duty places a premium not on
power dissipation but on ESR. During an output load
transient, the output capacitor must supply all of the
additional load current demanded by the load until the
LTC3832 adjusts the inductor current to the new value.
ESR in the output capacitor results in a step in the output
voltage equal to the ESR value multiplied by the change in
load current. An 5A load step with a 0.05Ω ESR output
capacitor results in a 250mV output voltage shift; this is
10% of the output voltage for a 2.5V supply! Because of
the strong relationship between output capacitor ESR and
output load transient response, choose the output capaci-
tor for ESR, not for capacitance value. A capacitor with
suitable ESR will usually have a larger capacitance value
than is needed to control steady-state output ripple.
Solving this equation with our typical 3.3V to 2.5V appli-
cation with a 1µH inductor, we get:
(3.3V – 2.5V)• 2.5V
= 2AP-P
300kHz •1µH • 3.3V
Peak inductor current at 10A load:
10A + (2A/2) = 11A
The ripple current should generally be between 10% and
40% of the output current. The inductor must be able to
withstand this peak current without saturating, and the
copper resistance in the winding should be kept as low as
possible to minimize resistive power loss. Note that in
circuits not employing the current limit function, the
current in the inductor may rise above this maximum
undershort-circuitorfaultconditions;theinductorshould
be sized accordingly to withstand this additional current.
Inductorswithgradualsaturationcharacteristicsareoften
the best choice.
Electrolytic capacitors rated for use in switching power
supplies with specified ripple current ratings and ESR can
be used effectively in LTC3832 applications. OS-CON
electrolytic capacitors from Sanyo and other manufactur-
ers give excellent performance and have a very high
performance/size ratio for electrolytic capacitors. Surface
mount applications can use either electrolytic or dry
tantalum capacitors. Tantalum capacitors must be surge
tested and specified for use in switching power supplies.
Low cost, generic tantalums are known to have very short
lives followed by explosive deaths in switching power
supply applications. Other capacitors that can be used
include the Sanyo POSCAP and MV-WX series.
Input and Output Capacitors
A typical LTC3832 design places significant demands on
both the input and the output capacitors. During normal
steady load operation, a buck converter like the LTC3832
drawssquarewavesofcurrentfromtheinputsupplyatthe
switchingfrequency. Thepeakcurrentvalueisequaltothe
output load current plus 1/2 the peak-to-peak ripple cur-
rent. Most of this current is supplied by the input bypass
capacitor. The resulting RMS current flow in the input
capacitor heats it and causes premature capacitor failure
in extreme cases. Maximum RMS current occurs with
50% PWM duty cycle, giving an RMS current value equal
A common way to lower ESR and raise ripple current
capability is to parallel several capacitors. A typical
sn3832 3832fs
15
LTC3832/LTC3832-1
W U U
U
APPLICATIO S I FOR ATIO
Loop stability is affected by the values of the inductor, the
output capacitor, the output capacitor ESR, the error
amplifier transconductance and the error amplifier com-
pensation network. The inductor and the output capacitor
create a double pole at the frequency:
LTC3832 application might exhibit 5A input ripple cur-
rent. Sanyo OS-CON capacitors, part number 10SA220M
(220µF/10V), feature 2.3A allowable ripple current at
85°C; three in parallel at the input (to withstand the input
ripple current) meet the above requirements. Similarly,
SanyoPOSCAP4TPB470M(470µF/4V)capacitorshavea
maximum rated ESR of 0.04Ω; three in parallel lower the
net output capacitor ESR to 0.013Ω.
fLC = 1/ 2π (LO)(COUT
)
The ESR of the output capacitor and the output capacitor
value form a zero at the frequency:
Feedback Loop Compensation
TheLTC3832voltagefeedbackloopiscompensatedatthe
COMP pin, which is the output node of the error amplifier.
The feedback loop is generally compensated with an RC +
C network from COMP to GND as shown in Figure 10a.
fESR = 1/ 2π(ESR)(C
)
[
]
OUT
The compensation network used with the error amplifier
must provide enough phase margin at the 0dB crossover
frequency for the overall open-loop transfer function. The
zero and pole from the compensation network are:
fZ = 1/[2π(RC)(CC)] and
+
SENSE
7
C2
fP = 1/[2π(RC)(C1)] respectively
LTC3832
R2
V
FB
–
+
Figure 10b shows the Bode plot of the overall transfer
function.
6
COMP
10
ERR
R1
–
SENSE
5
When low ESR output capacitors (Sanyo OS-CON) are
used, the ESR zero can be high enough in frequency that
it provides little phase boost at the loop crossover fre-
quency. As a result, the phase margin becomes
inadequate and the load transient is not optimized. To
resolve this problem, a small capacitor can be connected
R
C
V
C1
REF
C
C
3832 F10a
Figure 10a. Compensation Pin Hook-Up
f
f
= LTC3832 SWITCHING
FREQUENCY
= CLOSED-LOOP CROSSOVER
FREQUENCY
f
f
= LTC3832 SWITCHING
FREQUENCY
= CLOSED-LOOP CROSSOVER
FREQUENCY
SW
SW
f
Z
CO
CO
f
Z
20dB/DECADE
20dB/DECADE
f
CO
f
f
f
PC2
P
P
FREQUENCY
FREQUENCY
f
f
f
f
ZC2
LC
ESR
LC
f
CO
f
ESR
3832 F10b
3832 F10c
Figure 10b. Bode Plot of the LTC3832 Overall Transfer Function
Figure 10c. Bode Plot of the LTC3832 Overall
Transfer Function Using a Low ESR Output Capacitor
sn3832 3832fs
16
LTC3832/LTC3832-1
W U U
APPLICATIO S I FOR ATIO
U
betweenthetopoftheresistordividernetworkandtheVFB
pin to create a pole-zero pair in the loop compensation.
The zero location is prior to the pole location and thus,
phase lead can be added to boost the phase margin at the
loopcrossoverfrequency. Thepoleandzerolocationsare
located at:
Table 3 shows the suggested compensation component
valuesfor3.3Vto2.5Vapplicationsbasedon470µFSanyo
POSCAP 4TPB470M output capacitors.
Table 3. Recommended Compensation Network for 3.3V to 2.5V
Applications Using Multiple Paralleled 470µF Sanyo POSCAP
4TPB470M Output Capacitors
L1 (µH)
C
(µF)
R (kΩ)
C (µF)
C1 (pF)
100
56
OUT
C
C
fZC2 = 1/[2π(R2)(C2)] and
fPC2 = 1/[2π(R1||R2)(C2)]
1.2
1410
13
27
0.0047
0.0018
0.0015
0.0033
0.0022
0.001
1.2
2820
4700
1410
2820
4700
1410
2820
4700
1.2
51
47
whereR1||R2istheparallelcombinationresistanceofR1
and R2. For low R2/R1 ratios there is not much separa-
tion between fCZ2 and fPC2. In this case, use multiple
capacitorswithahighESR•capacitanceproducttobring
fESR close to fCO. Choose C2 so that the zero is located at
a lower frequency compared to fCO and the pole location
is high enough that the closed loop has enough phase
marginforstability.Figure10cshowstheBodeplotusing
phase lead compensation around the LTC3832 resistor
divider network.
2.4
33
56
2.4
62
15
2.4
82
39
4.7
62
0.0022
0.0015
0.0015
15
4.7
150
220
10
4.7
2
Table 4 shows the suggested compensation component
values for 3.3V to 2.5V applications based on 1500µF
Sanyo MV-WX output capacitors.
Table 4. Recommended Compensation Network for 3.3V to 2.5V
Applications Using Multiple Paralleled 1500µF Sanyo MV-WX
Output Capacitors
Although a mathematical approach to frequency compen-
sationcanbeused, theaddedcomplicationofinputand/or
output filters, unknown capacitor ESR, and gross operat-
ing point changes with input voltage, load current varia-
tions, all suggest a more practical empirical method. This
can be done by injecting a transient current at the load and
using an RC network box to iterate toward the final values,
or by obtaining the optimum loop response using a
network analyzer to find the actual loop poles and zeros.
L1 (µH)
C
(µF)
R (kΩ)
C (µF)
C1 (pF)
180
120
100
82
OUT
C
C
1.2
4500
39
56
0.0042
0.0033
0.0033
0.0033
0.0022
0.0022
0.0022
0.0022
0.0015
1.2
6000
9000
4500
6000
9000
4500
6000
9000
1.2
82
2.4
82
2.4
100
150
120
220
220
56
2.4
68
4.7
39
Table 2 shows the suggested compensation component
valuefor3.3Vto2.5VapplicationsbasedonSanyoOS-CON
4SP820M low ESR output capacitors.
4.7
27
4.7
33
Table 2. Recommended Compensation Network for 3.3V to 2.5V
Applications Using Multiple Paralleled 820µF Sanyo OS-CON
4SP820M Output Capacitors
LAYOUT CONSIDERATIONS
When laying out the printed circuit board, use the follow-
ing checklist to ensure proper operation of the LTC3832.
These items are also illustrated graphically in the layout
diagram of Figure 11. The thicker lines show the high
current paths. Note that at 10A current levels or above,
current density in the PC board itself is a serious concern.
Traces carrying high current should be as wide as pos-
sible. For example, a PCB fabricated with 2oz copper
requires a minimum trace width of 0.15" to carry 10A.
L1 (µH)
1.2
C
(µF)
R (kΩ)
C (nF)
C1 (pF)
560
330
270
330
220
180
120
100
100
C2 (pF)
1500
1500
1500
1500
1500
1500
1500
1500
1500
OUT
C
C
1640
9.1
15
24
22
33
43
33
56
91
4.7
4.7
3.3
4.7
3.3
2.2
3.3
2.2
2.2
1.2
2460
4100
1640
2460
4100
1640
2460
4100
1.2
2.4
2.4
2.4
4.7
4.7
4.7
sn3832 3832fs
17
LTC3832/LTC3832-1
W U U
U
APPLICATIO S I FOR ATIO
1. In general, layout should begin with the location of the
powerdevices.Besuretoorientthepowercircuitrysothat
a clean power flow path is achieved. Conductor widths
shouldbemaximizedandlengthsminimized.Afteryouare
satisfied with the power path, the control circuitry should
belaidout. Itismucheasiertofindroutesfortherelatively
small traces in the control circuits than it is to find
circuitous routes for high current paths.
3. The small-signal resistors and capacitors for frequency
compensation and soft-start should be located very close
to their respective pins and the ground ends connected to
the signal ground pin through a separate trace. Do not
connect these parts to the ground plane!
4.TheVCC,PVCC1 andPVCC2 decouplingcapacitorsshould
be as close to the LTC3832 as possible. The 4.7µF and 1µF
bypasscapacitorsshownatVCC,PVCC1 andPVCC2 willhelp
provide optimum regulation performance.
2. The GND and PGND pins should be shorted directly at
the LTC3832. This helps to minimize internal ground dis-
turbancesintheLTC3832andpreventdifferencesinground
potential from disrupting internal circuit operation. This
connectionshouldthentieintothegroundplaneatasingle
point, preferablyatafairlyquietpointinthecircuitsuchas
closetotheoutputcapacitors. Thisisnotalwayspractical,
however, due to physical constraints. Another reasonably
good point to make this connection is between the output
capacitors and the source connection of the bottom
MOSFETQ2.Donottiethissinglepointgroundinthetrace
runbetweentheQ2sourceandtheinputcapacitorground,
as this area of the ground plane will be very noisy.
5. The (+) plate of CIN should be connected as close as
possibletothedrainoftheupperMOSFET,Q1.Anadditional
1µF ceramic capacitor between VIN and power ground is
recommended.
6.TheSENSEandVFB pinsareverysensitivetopickupfrom
the switching node. Care should be taken to isolate SENSE
and VFB from possible capacitive coupling to the inductor
switchingsignal.ConnectingtheSENSE+andSENSE–close
to the load can significantly improve load regulation.
7. Kelvin sense IMAX and IFB at Q1’s drain and source pins.
PV
CC
V
IN
100Ω
+
+
1µF
C
IN
4.7µF
V
PV
CC2
CC
0.1µF
1µF
PV
PGND
CC1
Q1A
Q1B
G1
LTC3832
GND
I
MAX
L
O
1k
FREQSET
SHDN
COMP
SS
I
V
OUT
NC
FB
+
SENSE
Q2
G2
NC
FB
–
C1
R
+
C
SENSE
OUT
C
GND
PGND
PGND
C
C
SS
C
3832 F11
GND
Figure 11. Typical Schematic Showing Layout Considerations
sn3832 3832fs
18
LTC3832/LTC3832-1
W U U
APPLICATIO S I FOR ATIO
U
V
IN
3.3V
+
C
IN
OPTIONAL
330µF
×2
D
Z
12V
1N5242
1N5817
1N5817
1N5817
+
10µF
0.1µF
5.6k
100Ω
Q1A, Q1B
PV
PV
CC1
CC2
0.1µF
2 IN PARALLEL
V
G1
+
CC
1µF
L
O
1.3µH
4.7µF
0.1µF
SS
I
MAX
V
2.5V
14A
1k
OUT
0.01µF
I
FB
LTC3832
+
C
OUT
Q2
D1
NC
FREQSET
SHDN
G2
470µF
×3
SHDN
PGND
GND
COMP
C1
180pF
R
C
18k
+
3832 F12a
SENSE
FB
–
NC
C
C
: SANYO 6TPB330M
C
C
1500pF
IN
SENSE
: SANYO 4TPB470M
OUT
D1: MBRS330T3
L : SUMIDA CDEP105-1R3-MC-S
O
Q1A, Q1B, Q2: FAIRCHILD FDS6670A
Figure 12. Typical 3.3V to 2.5V, 14A Application
Efficiency vs Load Current
100
90
80
70
60
50
40
30
T
V
V
= 25°C
A
20
10
0
= 3.3V
IN
OUT
= 2.5V
REFER TO FIGURE 12
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
LOAD CURRENT (A)
3832 F12b
sn3832 3832fs
19
LTC3832/LTC3832-1
U
TYPICAL APPLICATIO S
Typical 3.3V to 5V, 5A Synchronous Boost Converter
V
IN
3.3V
+
C
5mΩ
MBR0520
MBR0520
IN
10µF
330µF
L
O
1.3µH
10µF
0.1µF
10Ω
5.6k
PV
PV
CC2
CC1
V
0.1µF
100Ω
CC
MBR330T3
Q2
2.2µF
SS
I
MAX
V
5V
5A
OUT
0.47µF
NC
I
LTC3832
FB
+
C
OUT
Q1
10µF
FREQSET
SHDN
G1
PGND
GND
G2
330µF
×2
93.1k
1%
SHUTDOWN
COMP
C1
68pF
12.7k
1%
R
+
C
6.8k
NC
SENSE
FB
C
C
3832 TA03
–
SENSE
0.01µF
C
, C : SANYO POSCAP 6TPB330M
IN OUT
L : SUMIDA CDEP105-1R3-MC-S
O
Q1, Q2: SILICONIX Si4864DY
NC
sn3832 3832fs
20
LTC3832/LTC3832-1
U
TYPICAL APPLICATIO S
Typical 3.3V to –5V, 5A Positive-to-Negative Converter
V
IN
3.3V
+
C
IN
330µF
MBR0520
100Ω
1µF
1µF
10µF
3.5k
PV
PV
CC1
CC2
Q1
Q2
0.1µF
V
G1
CC
L
O
0.1µF
SS
I
MAX
D
Z
1.3µH
1k
0.01µF
NC
8.2V
I
LTC3832
FB
+
C
FREQSET
SHDN
G2
OUT
330µF
10µF
93.1k
1%
13V
SHUTDOWN
COMP
FB
PGND
GND
12.7k
1%
+
SENSE
NC
V
–5V
5A
R
C
OUT
15k
C1
180pF
3832 TA04
–
SENSE
C
C
C
, C : SANYO POSCAP 6TPB330M
IN OUT
1.5nF
L : SUMIDA CDEP105-1R3-MC-S
O
NC
Q1, Q2: SILICONIX Si7440DP
sn3832 3832fs
21
LTC3832/LTC3832-1
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.053 – .068
(1.351 – 1.727)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN16 (SSOP) 0502
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
sn3832 3832fs
22
LTC3832/LTC3832-1
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
.045 ±.005
NOTE 3
.050 BSC
N
7
5
8
6
N
.245
MIN
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
1
2
3
N/2
N/2
4
.030 ±.005
TYP
RECOMMENDED SOLDER PAD LAYOUT
1
3
2
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SO8 0502
sn3832 3832fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
23
LTC3832/LTC3832-1
U
TYPICAL APPLICATIO
Typical 5V to 3.3V, 10A Application
5V
+
C
IN
MBR0530T1
20k
330µF
×2
+
100Ω 1µF
Q1A, Q1B
2 IN PARALLEL
PV
PV
CC1
CC2
0.1µF
0.1µF
V
G1
+
CC
0.1µF
L
O
1.3µH
4.7µF
SS
I
MAX
1k
0.01µF
3.3V
10A
I
LTC3832
FB
+
C
OUT
NC
Q2
FREQSET
SHDN
G2
PGND
GND
45k
1%
470µF
×3
SHUTDOWN
COMP
C1
180pF
10k
1%
R
+
C
SENSE
NC
18k
FB
–
C
C
3830 TA02
SENSE
C
C
O
: SANYO 6TPB330M
IN
0.01µF
: SANYO 4TPB470M
OUT
L : SUMIDA CDEP105-1R3-MC-S
NC
Q1A, Q1B, Q2: ON SEMICONDUCTOR MTD20N03HDL
RELATED PARTS
PART NUMBER
LTC1530
DESCRIPTION
High Power Synchronous Switching Regulator Controller
COMMENTS
SO-8 with Current Limit. No R
TM Required
SENSE
LTC1628
Dual High Efficiency 2-Phase Synchronous Step-Down Controller Constant Frequency, Standby 5V and 3.3V LDOs,
3.5V ≤ V ≤ 36V
IN
LTC1702
LTC1705
Dual High Efficiency 2-Phase Synchronous Step-Down Controller 550kHz, 25MHz GBW Voltage Mode, V ≤ 7V, No R
IN SENSE
Dual 550kHz Synchronous 2-Phase Switching Regulator
Controller with 5-Bit VID Plus LDO
Provides CPU Core, I/O and CLK Supplies for Portable Systems
LTC1709
LTC1736
LTC1753
2-Phase, 5-Bit Desktop VID Synchronous Step-Down Controller
Current Mode, V to 36V, I Up to 42A
IN
OUT
Synchronous Step-Down Controller with 5-Bit Mobile VID Control Fault Protection, Power Good, 3.5V to 36V Input, Current Mode
5-Bit Desktop VID Programmable Synchronous
Switching Regulator
1.3V to 3.5V Programmable Output Using Internal 5-Bit DAC
LTC1773
Synchronous Step-Down Controller in MS10
Up to 95% Efficiency, 550kHz, 2.65V ≤ V ≤ 8.5V,
IN
0.8V ≤ V
≤ V , Synchronizable to 750kHz
OUT
IN
LTC1778
LTC1873
LTC1876
Wide Operating Range/Step-Down Controller, No R
V Up to 36V, Current Mode, Power Good
IN
SENSE
Dual Synchronous Switching Regulator with 5-Bit Desktop VID
1.3V to 3.5V Programmable Core Output Plus I/O Output
2-Phase, Dual Step-Down Synchronous Controller with
Integrated Step-Up DC/DC Regulator
Step-Down DC/DC Conversion from 3V , Minimum C and
IN
IN
C
, Uses Logic-Level N-Channel MOSFETs
OUT
LTC1929
LTC3713
LTC3831
2-Phase, Synchronous High Efficiency Converter
with Mobile VID
Current Mode Ensures Accurate Current Sensing V Up to 36V,
IN
I
Up to 40A
OUT
Low Input Voltage, High Power, No R
Synchronous Controller
, Step-Down
SENSE
Minimum V : 1.5V, Uses Standard Logic-Level N-Channel
IN
MOSFETs
High Power Synchronous Switching Regulator Controller for
DDR Memory Termination
V
Tracks 1/2 of V or External Reference
OUT IN
No R
is a trademark of Linear Technology Corporation.
SENSE
sn3832 3832fs
LT/TP 1002 2K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002
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LTC3833 - Fast Accurate Step-Down DC/DC Controller with Differential Output Sensing; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C
Linear
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