LTC3835IGN-1-TRPBF [Linear]
Low IQ Synchronous Step-Down Controller; 智商低的同步降压型控制器
| 型号： | LTC3835IGN-1-TRPBF |
| 厂家： | 
Linear |
| 描述： | Low IQ Synchronous Step-Down Controller |
| 文件： | 总28页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3835-1
Low I Synchronous
Q
Step-Down Controller
FEATURES
DESCRIPTION
The LTC®3835-1 is a high performance step-down switch-
ingregulatorcontrollerthatdrivesanallN-channelsynchro-
nous power MOSFET stage. A constant-frequency current
mode architecture allows a phase-lockable frequency of
up to 650kHz.
n
Wide Output Voltage Range: 0.8V ≤ V
≤ 10V
OUT
n
Low Operating I : 80μA
Q
OPTI-LOOP® Compensation Minimizes C
1ꢀ Output Voltage Accuracy
n
OUT
n
n
n
n
n
n
n
n
n
n
Wide V Range: 4V to 36V Operation
IN
Phase-Lockable Fixed Frequency 140kHz to 650kHz
Dual N-Channel MOSFET Synchronous Drive
Very Low Dropout Operation: 99% Duty Cycle
Adjustable Output Voltage Soft-Start or Tracking
Output Current Foldback Limiting
The 80μA no-load quiescent current extends operating
life in battery powered systems. OPTI-LOOP compensa-
tion allows the transient response to be optimized over
a wide range of output capacitance and ESR values. The
LTC3835-1featuresaprecision0.8Vreferenceandapower
good output indicator. The 4V to 36V input supply range
encompasses a wide range of battery chemistries.
Output Overvoltage Protection
Low Shutdown I : 10μA
Selectable Continuous, Pulse-Skipping or
Burst Mode® Operation at Light Loads
Small 16-Lead Narrow SSOP or 3mm × 5mm
DFN Package
Q
The TRACK/SS pin ramps the output voltage during start-
up.CurrentfoldbacklimitsMOSFETheatdissipationduring
short-circuit conditions.
n
Comparison of LTC3835 and LTC3835-1
CLKOUT/
APPLICATIONS
PART #
PHASMD
EXTV
PGOOD
PACKAGES
CC
n
Automotive Systems
LTC3835
LTC3835-1
YES
YES
NO
YES
FE20/4 × 5 QFN
GN16/3 × 5 DFN
n
Telecom Systems
NO
NO
n
Battery-Operated Digital Devices
L, LT, LTC, LTM, Burst Mode, and OPTI-LOOP are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5408150, 5481178, 5705919, 5929620, 6304066,
6498466, 6580258, 6611131.
n
Distributed DC Power Systems
TYPICAL APPLICATION
High Efficiency Step-Down Converter
Efficiency and Power Loss
V
IN
vs Load Current
PLLLPF
V
IN
4V TO 36V
100000
10000
1000
100
100
90
10μF
RUN
TG
0.01μF
V
= 12V; V
OUT
= 3.3V
EFFICIENCY
IN
0.22μF
TRACK/SS
80
BOOST
SW
3.3μH
V
3.3V
5A
0.012Ω
OUT
I
TH
70
330pF
LTC3835-1
60
50
100pF
33k
150μF
SGND
PLLIN/MODE
INTV
CC
40
30
20
10
0
POWER LOSS
10
4.7μF
20k
V
FB
BG
1
–
+
SENSE
SENSE
62.5k
0.1
PGND
0.001 0.01 0.1
1
10 100 1000 10000
LOAD CURRENT (mA)
38351 TA01b
38351 TA01
38351fc
1
LTC3835-1
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage (V )......................... 36V to –0.3V
INTV Peak Output Current ................................. 50mA
IN
CC
Top Side Driver Voltage (BOOST)............... 42V to –0.3V
Operating Temperature Range (Note 2).... –40°C to 85°C
Junction Temperature (Note 3) ............................. 125°C
Storage Temperature Range
Switch Voltage (SW)..................................... 36V to –5V
INTV , (BOOST-SW) ............................... 8.5V to –0.3V
CC
RUN, TRACK/SS ......................................... 7V to –0.3V
GN Package ....................................... –65°C to 150°C
Storage Temperature Range
DHC Package .................................... –65°C to 125°C
Lead Temperature (GN Package, Soldering, 10 sec).... 300°C
+
–
SENSE , SENSE Voltages ........................ 11V to –0.3V
PLLIN/MODE, PLLLPF .........................INTVCC to –0.3V
I , V Voltages ...................................... 2.7V to –0.3V
TH FB
Peak Output Current <10μs (TG, BG)..........................3A
PIN CONFIGURATION
TOP VIEW
TOP VIEW
PLLLPF
1
2
3
4
5
6
7
8
16 PLLIN/MODE
PLLLPF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PLLIN/MODE
+
I
TH
15 SENSE
+
I
TH
SENSE
–
TRACK/SS
14 SENSE
–
TRACK/SS
SENSE
V
FB
13 RUN
12 BOOST
11 TG
17
V
FB
RUN
BOOST
TG
SGND
PGND
BG
SGND
PGND
BG
10 SW
SW
INTV
9
V
IN
CC
INTV
CC
V
IN
DHC PACKAGE
GN PACKAGE
16-LEAD PLASTIC SSOP
16-Pin (5mm s 3mm) PLASTIC DFN
T
= 125°C, θ = 43.5°C/W
JA
JMAX
T
= 150°C, θ = 90°C/W
JA
JMAX
EXPOSED PAD (PIN 17) IS SGND
MUST BE SOLDERED TO PCB
ORDER INFORMATION
(Note 2)
LEAD FREE FINISH
LTC3835EDHC-1#PBF
LTC3835IDHC-1#PBF
LTC3835EGN-1#PBF
LTC3835IGN-1#PBF
LEAD BASED FINISH
LTC3835EDHC-1
TAPE AND REEL
PART MARKING*
38351
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
LTC3835EDHC-1#TRPBF
LTC3835IDHC-1#TRPBF
LTC3835EGN-1#TRPBF
LTC3835IGN-1#TRPBF
TAPE AND REEL
16-Lead (5mm × 3mm) Plastic DFN
16-Lead (5mm × 3mm) Plastic DFN
16-Lead Plastic SSOP
38351
–40°C to 85°C
38351
–40°C to 85°C
38351
16-Lead Plastic SSOP
–40°C to 85°C
PART MARKING*
38351
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
LTC3835EDHC-1#TR
LTC3835IDHC-1#TR
LTC3835EGN-1#TR
LTC3835IGN-1#TR
16-Lead (5mm × 3mm) Plastic DFN
16-Lead (5mm × 3mm) Plastic DFN
16-Lead Plastic SSOP
LTC3835IDHC-1
38351
–40°C to 85°C
LTC3835EGN-1
38351
–40°C to 85°C
LTC3835IGN-1
38351
16-Lead Plastic SSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
38351fc
2
LTC3835-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VRUN = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
l
V
Regulated Feedback Voltage
Feedback Current
(Note 4); I Voltage = 1.2V
0.792
0.800
–5
0.808
–50
V
nA
FB
TH
I
(Note 4)
VFB
V
V
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
= 4V to 30V (Note 4)
0.002
0.02
%/V
REFLNREG
IN
(Note 4)
Measured in Servo Loop; ΔI Voltage = 1.2V to 0.7V
Measured in Servo Loop; ΔI Voltage = 1.2V to 2V
LOADREG
l
l
0.1
–0.1
0.5
–0.5
%
%
TH
TH
g
m
Transconductance Amplifier g
I = 1.2V; Sink/Source 5μA (Note 4)
TH
1.55
mmho
m
I
Q
Input DC Supply Current
Sleep Mode
Shutdown
(Note 5)
RUN = 5V, V = 0.83V (No Load)
80
10
125
20
μA
μA
FB
V = 0V
RUN
l
UVLO
Undervoltage Lockout
V
Ramping Down
3.5
10
4
V
%
μA
%
μA
V
IN
V
Feedback Overvoltage Lockout
Sense Pins Total Source Current
Maximum Duty Factor
Measured at V Relative to Regulated V
8
12
OVL
FB
FB
–
+
I
V
= V = 0V
SENSE
–660
99.4
1.0
SENSE
SENSE
DF
In Dropout
= 0V
98
0.75
0.5
MAX
I
Soft-Start Charge Current
V
TRACK
1.35
0.9
TRACK/SS
V
V
ON
RUN Pin ON Threshold
V
, V
Rising
0.7
RUN
RUN1 RUN2
–
Maximum Current Sense Threshold
V
V
= 0.7V, V
= 0.7V, V
= 3.3V
= 3.3V
90
80
100
100
110
115
mV
mV
SENSE(MAX)
FB
FB
SENSE
–
l
SENSE
TG Transition Time:
Rise Time
Fall Time
(Note 6)
TG1, 2 t
TG1, 2 t
C
C
= 3300pF
50
50
90
90
ns
ns
r
f
LOAD
LOAD
= 3300pF
BG Transition Time:
Rise Time
Fall Time
(Note 6)
LOAD
LOAD
BG1, 2 t
BG1, 2 t
C
C
= 3300pF
= 3300pF
40
40
90
80
ns
ns
r
f
TG/BG t
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
C
= 3300pF
70
ns
ns
ns
1D
LOAD
BG/TG t
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
C
LOAD
= 3300pF
70
2D
t
Minimum On-Time
(Note 7)
8.5V < V < 30V
180
ON(MIN)
INTV Linear Regulator
CC
V
V
Internal V Voltage
5.0
5.25
0.2
5.5
1.0
V
INTVCCVIN
LDOVIN
CC
IN
INTV Load Regulation
I
CC
= 0mA to 20mA
%
CC
Oscillator and Phase-Locked Loop
f
f
f
f
f
I
Nominal Frequency
Lowest Frequency
Highest Frequency
V
V
V
= No Connect
= 0V
360
220
475
400
250
530
115
800
440
280
580
140
kHz
kHz
kHz
kHz
kHz
NOM
PLLLPF
PLLLPF
PLLLPF
LOW
= INTV
HIGH
CC
Minimum Synchronizable Frequency PLLIN/MODE = External Clock; V
Maximum Synchronizable Frequency PLLIN/MODE = External Clock; V
Phase Detector Output Current
Sinking Capability
Sourcing Capability
= 0V
= 2V
SYNCMIN
SYNCMAX
PLLLPF
PLLLPF
650
PLLLPF
f
f
< f
> f
–5
5
μA
μA
PLLIN/MODE
PLLIN/MODE
OSC
OSC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3835E-1 is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3835I-1 is guaranteed to
meet performance specificatons over the full –40°C to 85°C operating
temperature range.
38351fc
3
LTC3835-1
ELECTRICAL CHARACTERISTICS
Note 3: T is calculated from the ambient temperature T and power
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
J
A
dissipation P according to the following formulas:
D
LTC3835GN-1: T = T + (P • 90°C/W)
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
J
A
D
LTC3835EDHC-1: T = T + (P • 43.5°C/W)
J
A
D
Note 4: The LTC3835-1 is tested in a feedback loop that servos V to a
Note 7: The minimum on-time condition is specified for an inductor
ITH
specified voltage and measures the resultant V
.
peak-to-peak ripple current ≥40% of I
(see Minimum On-Time
FB
MAX
Considerations in the Applications Information section).
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Efficiency and Power Loss
vs Output Current
Efficiency vs Load Current
Efficiency vs Input Voltage
10000
1000
100
10
100
90
100
90
80
70
60
50
40
98
96
94
92
90
88
86
84
82
Burst Mode OPERATION
FORCED CONTINUOUS MODE
PULSE SKIPPING MODE
V
V
V
= 12V
= 5V
OUT
IN
IN
V
= 3.3V
OUT
FIGURE 10 CIRCUIT
= 3.3V
80
V
V
= 12V
= 3.3V
IN
OUT
70
60
50
40
30
20
10
0
1
FIGURE 10 CIRCUIT
FIGURE 10 CIRCUIT
0.1
0.001 0.01 0.1
1
10 100 1000 10000
0.001 0.01 0.1
1
10 100 1000 10000
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
38351 G03
0
LOAD CURRENT (mA)
LOAD CURRENT (mA)
38351 G01
38351 G02
Load Step
(Burst Mode Operation)
Load Step
(Forced Continuous Mode)
Load Step
(Pulse-Skipping Mode)
V
V
OUT
OUT
V
OUT
100mV/DIV
AC
100mV/DIV
AC
100mV/DIV
AC
COUPLED
COUPLED
COUPLED
I
I
I
L
L
L
2A/DIV
2A/DIV
2A/DIV
38351 G05
38351 G04
38351 G06
20μs/DIV
20ms/DIV
20μs/DIV
FIGURE 10 CIRCUIT
OUT
FIGURE 10 CIRCUIT
OUT
FIGURE 10 CIRCUIT
OUT
V
= 3.3V
V
= 3.3V
V
= 3.3V
38351fc
4
LTC3835-1
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Soft Start-Up
Tracking Start-Up
Inductor Current at Light Load
V
OUT2
FORCED
CONTIN-
UOUS
2V/DIV
(MASTER)
MODE
V
OUT1
2V/DIV
2A/DIV
Burst Mode
OPERATION
(SLAVE)
V
OUT
1V/DIV
PULSE-
SKIPPING
MODE
38351 G07
38351 G08
38351 G09
20ms/DIV
4μs/DIV
20ms/DIV
FIGURE 10 CIRCUIT
FIGURE 10 CIRCUIT
FIGURE 10 CIRCUIT
V
= 3.3V
OUT
I
= 300μA
LOAD
Total Input Supply Current
vs Input Voltage
EXTVCC Switchover and INTVCC
Voltages vs Temperature
INTVCC Line Regulation
5.50
5.45
5.40
5.35
5.30
5.25
5.20
5.15
5.10
5.05
5.00
350
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
300
250
200
150
100
50
INTV
CC
300μA LOAD
NO LOAD
EXTV RISING
CC
EXTV FALLING
CC
0
25
INPUT VOLTAGE (V)
35
0
35
5
10
15
20
30
35
TEMPERATURE (°C)
5
10 15 20 25 30
INPUT VOLTAGE (V)
40
–45
–5
15
55
75
95
–25
38351 G12
38351 G10
38351 G11
Maximum Current Sense Voltage
vs ITH Voltage
Sense Pins Total Input
Bias Current
Maximum Current Sense Threshold
vs Duty Cycle
100
80
120
100
200
100
PULSE SKIPPING
FORCED CONTINUOUS
BURST MODE (RISING)
BURST MODE (FALLING)
0
60
40
20
0
–100
–200
–300
–400
–500
–600
–700
80
60
40
20
0
–20
10% DUTY CYCLE
–40
0.8
PIN VOLTAGE (V)
1.2
1.4
0
0.2
0.4 0.6
1.0
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
0
1
2
3
4
5
10
6
7
8
9
I
V
COMMON MODE VOLTAGE (V)
TH
SENSE
38351 G13
38351 G15
38351 G14
38351fc
5
LTC3835-1
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current
SENSE Pins Total Input
Foldback Current Limit
vs Temperature
Bias Current vs ITH
12
120
100
100
95
90
85
80
75
70
65
60
V
= 3.3V
SENSE
TRACK/SS = 1V
PLLIN/MODE = 0V
10
8
80
60
40
6
4
2
20
0
0
0
0.4
0.6 0.8 1.0 1.2
VOLTAGE (V)
1.4
0.2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
FEEDBACK VOLTAGE (V)
15 30
0
TEMPERATURE (°C)
–45 –30 –15
45 60 75 90
I
TH
38351 G18
38351 G16
38351 G17
TRACK/SS Pull-Up Current
vs Temperature
Shutdown (RUN) Threshold
vs Temperature
Regulated Feedback Voltage
vs Temperature
808
806
804
802
800
798
796
794
792
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
15 30
TEMPERATURE (°C)
–45 –30 –15
0
45 60 75 90
15 30
TEMPERATURE (°C)
15 30
–45 –30 –15
0
45 60 75 90
–45 –30 –15
0
45 60 75 90
TEMPERATURE (°C)
38351 G21
38351 G19
38351 G20
SENSE Pins Total Input Current
vs Temperature
Shutdown Current
vs Input Voltage
Oscillator Frequency
vs Temperature
200
100
25
20
15
10
5
800
700
600
500
V
V
= 10V
OUT
= 3.3V
OUT
0
V
V
= INTV
CC
–100
–200
–300
–400
–500
–600
–700
–800
PLLLPF
PLLLPF
= FLOAT
400
300
200
100
V
= GND
PLLLPF
V
= 0V
OUT
0
0
–45 –30 –15
0
15 30 45 60 75 90
5
10
15
20
25
30
35
–45
–5
15
35
55
75
–25
TEMPERATURE (°C)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
38351 G22
38351 G23
38351 G24
38351fc
6
LTC3835-1
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency
vs Input Voltage
Shutdown Current
vs Temperature
Undervoltage Lockout Threshold
vs Temperature
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
404
402
12
10
400
8
RISING
398
396
6
4
FALLING
394
392
2
0
–45
–15
0
15 30 45 60 75 90
15 30
TEMPERATURE (°C)
–30
25
INPUT VOLTAGE (V)
35
–45 –30 –15
0
45 60 75 90
5
10
15
20
30
TEMPERATURE (°C)
38351 G26
38351 G25
38351 G27
PIN FUNCTIONS (DHC Package/GN Package)
PLLLPF(Pin1/Pin1):Thephase-lockedloop’slowpassfilter
BG (Pin 7/Pin 7): High Current Gate Drive for Bottom
is tied to this pin when synchronizing to an external clock.
(Synchronous) N-Channel MOSFET. Voltage swing at this
Alternatively, tie this pin to GND, INTV or leave floating to
pin is from ground to INTV .
CC
CC
select 250kHz, 530kHz or 400kHz switching frequency.
INTV (Pin 8/Pin 8): Output of the Internal Linear Low
CC
I
(Pin 2/Pin 2): Error Amplifier Outputs and Switching
Dropout Regulator. The driver and control circuits are
powered from this voltage source. Must be decoupled to
power ground with a minimum of 4.7μF tantalum or other
low ESR capacitor.
TH
Regulator Compensation Points. The current comparator
trip point increases with this control voltage.
TRACK/SS (Pin 3/Pin 3): External Tracking and Soft-Start
Input.TheLTC3835-1regulatestheV voltagetothesmaller
V
(Pin 9/Pin 9): Main Supply Pin. A bypass capacitor
FB
IN
of 0.8V or the voltage on the TRACK/SS pin. A internal 1μA
pull-up current source is connected to this pin. A capacitor
to ground at this pin sets the ramp time to final regulated
output voltage. Alternatively, a resistor divider on another
voltage supply connected to this pin allows the LTC3835-1
output to track the other supply during start-up.
should be tied between this pin and the signal ground pin.
SW(Pin10/Pin10):SwitchNodeConnectionstoInductor.
VoltageswingatthispinisfromaSchottkydiode(external)
voltage drop below ground to V .
IN
TG (Pin 11/Pin 11): High Current Gate Drive for Top
N-ChannelMOSFET.Thesearetheoutputsoffloatingdrivers
V (Pin4/Pin4):Receivestheremotelysensedfeedbackvolt-
FB
withavoltageswingequaltoINTV –0.5Vsuperimposed
CC
age from an external resistive divider across the output.
on the switch node voltage SW.
SGND(Pin5/Pin5):Small-SignalGround. Mustberouted
separately from high current grounds to the common (–)
terminals of the input capacitor.
BOOST(Pin12/Pin12):BootstrappedSupplytotheTopside
Floating Driver. A capacitor is connected between the
BOOST and SW pins and a Schottky diode is tied between
PGND(Pin6/Pin6):DriverPowerGround.Connectstothe
the BOOST and INTV pins. Voltage swing at the BOOST
CC
sourceofbottom(synchronous)N-channelMOSFET,anode
pin is from INTV to (V + INTV ).
CC
IN
CC
of the Schottky rectifier and the (–) terminal of C .
IN
38351fc
7
LTC3835-1
PIN FUNCTIONS (DHC Package/GN Package)
RUN (Pin 13/Pin 13): Digital Run Control Input for
Controller. Forcing this pin below 0.7V shuts down all
controller functions, reducing the quiescent current that
the LTC3835-1 draws to approximately 10μA.
Input. When an external clock is applied to this pin, the
phase-locked loop will force the rising TG signal to be
synchronized with the rising edge of the external clock. In
this case, an R-C filter must be connected to the PLLLPF
pin.Whennotsynchronizingtoanexternalclock,thisinput
determines how the LTC3835-1 operates at light loads.
Pulling this pin below 0.7V selects Burst Mode operation.
–
SENSE (Pin 14/Pin 14): The (–) Input to the Differential
Current Comparator.
+
SENSE (Pin 15/Pin 15): The (+) Input to the Differential
TyingthispintoINTV forcescontinuousinductorcurrent
CC
Current Comparator. The I pin voltage and controlled
operation. Tying this pin to a voltage greater than 0.9V and
TH
–
+
offsets between the SENSE and SENSE pins in conjunc-
less than INTV selects pulse-skipping operation.
CC
tion with R
set the current trip threshold.
SENSE
Exposed Pad (Pin 17, DHC Package): SGND. Must be
soldered to PCB.
PLLIN/MODE (Pin 16/Pin 16): External Synchronization
Input to Phase Detector and Forced Continuous Control
FUNCTIONAL DIAGRAM
INTV
V
IN
CC
PLLIN/MODE
F
IN
PHASE DET
D
B
BOOST
TG
PLLLPF
C
R
B
LP
DROP
OUT
DET
CLK
TOP
BOT
C
IN
D
OSCILLATOR
BOT
TOP ON
FC
SW
C
LP
S
R
Q
Q
SWITCH
LOGIC
INTV
CC
BG
–
+
INTV –0.5V
CC
FC
BURSTEN
SLEEP
C
OUT
PGND
B
+
–
0.4V
V
OUT
–
+
PLLIN/MODE
BURSTEN
SHDN
R
0.8V
SENSE
L
ICMP
IR
+
–
–
+ +
–
–
+
+
SENSE
SENSE
6mV
0.45V
2(V
)
FB
–
SLOPE
COMP
V
FB
R
B
V
FB
–
+
V
TRACK/SS
0.80V
EA
OV
IN
R
A
V
IN
+
–
0.88V
1μA
LDO
0.5μA
C
C
I
5.25V
TH
INTV
CC
R
C
C
6V
C2
+
INTERNAL
SUPPLY
TRACK/SS
SGND
RUN
SHDN
C
SS
3835-1 FD
38351fc
8
LTC3835-1
OPERATION (Refer to Functional Diagram)
Main Control Loop
Shutdown and Start-Up (RUN and TRACK/SS Pins)
TheLTC3835-1canbeshutdownusingtheRUNpin.Pulling
thispinbelow0.7Vshutsdownthemaincontrolloopforthe
controller. A low disables the controller and most internal
The LTC3835-1 uses a constant-frequency, current mode
step-down architecture. During normal operation, each
external top MOSFET is turned on when the clock sets the
RSlatch,andisturnedoffwhenthemaincurrentcompara-
tor, ICMP, resets the RS latch. The peak inductor current
at which ICMP trips and resets the latch is controlled by
circuits, including the INTV regulator, at which time the
CC
LTC3835-1 draws only 10μA of quiescent current.
Releasing the RUN pin allows an internal 0.5μA current
to pull up the pin and enable that controller. Alternatively,
the RUN pin may be externally pulled up or driven directly
by logic. Be careful not to exceed the Absolute Maximum
rating of 7V on this pin.
the voltage on the I pin, which is the output of the error
TH
amplifierEA.Theerroramplifiercomparestheoutputvolt-
agefeedbacksignalattheV pin,(whichisgeneratedwith
FB
an external resistor divider connected across the output
voltage, V , to ground) to the internal 0.800V reference
OUT
The start-up of the output voltage V
is controlled by
OUT
voltage.Whentheloadcurrentincreases,itcausesaslight
the voltage on the TRACK/SS pin. When the voltage on
the TRACK/SS pin is less than the 0.8V internal reference,
decrease in V relative to the reference, which cause the
FB
EA to increase the I voltage until the average inductor
TH
the LTC3835-1 regulates the V voltage to the TRACK/SS
current matches the new load current.
FB
pin voltage instead of the 0.8V reference. This allows
the TRACK/SS pin to be used to program a soft-start by
connecting an external capacitor from the TRACK/SS pin
to SGND. An internal 1μA pull-up current charges this
capacitor creating a voltage ramp on the TRACK/SS pin.
As the TRACK/SS voltage rises linearly from 0V to 0.8V
After the top MOSFET is turned off each cycle, the bottom
MOSFETisturnedonuntileithertheinductorcurrentstarts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
INTV Power
CC
(and beyond), the output voltage V
from zero to its final value.
rises smoothly
OUT
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTV pin.
CC
Alternatively the TRACK/SS pin can be used to cause the
start-up of V to “track” that of another supply. Typi-
An internal 5.25V low dropout linear regulator supplies
OUT
INTV power from V .
CC
IN
cally, this requires connecting to the TRACK/SS pin an
external resistor divider from the other supply to ground
(see Applications Information section).
ThetopMOSFETdriverisbiasedfromthefloatingbootstrap
capacitor C , which normally recharges during each off
B
cycle through an external diode when the top MOSFET
When the RUN pin is pulled low to disable the LTC3835-1,
turns off. If the input voltage V decreases to a voltage
IN
or when V drops below its undervoltage lockout thresh-
IN
close to V , the loop may enter dropout and attempt
OUT
old of 3.5V, the TRACK/SS pin is pulled low by an internal
MOSFET. When in undervoltage lockout, the controller is
disabled and the external MOSFETs are held off.
to turn on the top MOSFET continuously. The dropout
detector detects this and forces the top MOSFET off for
about one twelfth of the clock period every tenth cycle to
allow C to recharge.
B
38351fc
9
LTC3835-1
OPERATION (Refer to Functional Diagram)
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping, or Continuous Conduction)
(PLLIN/MODE Pin)
Mode operation. However, continuous operation has the
advantages of lower output ripple and less interference
to audio circuitry. In forced continuous mode, the output
ripple is independent of load current.
The LTC3835-1 can be enabled to enter high efficiency
BurstModeoperation,constant-frequencypulse-skipping
mode, or forced continuous conduction mode at low load
currents. To select Burst Mode operation, tie the PLLIN/
MODE pin to a DC voltage below 0.8V (e.g., SGND). To
select forced continuous operation, tie the PLLIN/MODE
pin to INTVCC. To select pulse-skipping mode, tie the
PLLIN/MODE pin to a DC voltage greater than 0.8V and
When the PLLIN/MODE pin is connected for pulse-skip-
ping mode or clocked by an external clock source to
use the phase-locked loop (see Frequency Selection and
Phase-Locked Loop section), the LTC3835-1 operates in
PWM pulse-skipping mode at light loads. In this mode,
constant-frequency operation is maintained down to ap-
proximately 1% of designed maximum output current.
At very light loads, the current comparator ICMP may
remaintrippedforseveralcyclesandforcetheexternaltop
MOSFET to stay off for the same number of cycles (i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuousoperation, exhibitslowoutputrippleaswellas
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
efficiency than forced continuous mode, but not nearly as
high as Burst Mode operation.
less than INTV – 0.5V.
CC
When the LTC3835-1 is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-tenth of the maximum sense voltage even though the
voltage on the I pin indicates a lower value. If the aver-
TH
age inductor current is lower than the load current, the
error amplifier EA will decrease the voltage on the I pin.
TH
When the I voltage drops below 0.4V, the internal sleep
TH
signalgoeshigh(enabling“sleep”mode)andbothexternal
MOSFETs are turned off. The I pin is then disconnected
TH
from the output of the EA and “parked” at 0.425V.
Frequency Selection and Phase-Locked Loop
(PLLLPF and PLLIN/MODE Pins)
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3835-1 draws
to only 80μA. In sleep mode, the load current is supplied
by the output capacitor. As the output voltage decreases,
the EA’s output begins to rise. When the output voltage
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
drops enough, the I pin is reconnected to the output
TH
of the EA, the sleep signal goes low, and the controller
resumes normal operation by turning on the top external
MOSFET on the next cycle of the internal oscillator.
The switching frequency of the LTC3835-1’s controllers
can be selected using the PLLLPF pin.
IfthePLLIN/MODEpinisnotbeingdrivenbyanexternalclock
When the LTC3835-1 is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative, thus
operating in discontinuous operation.
source, the PLLLPF pin can be floated, tied to INTV , or tied
CC
to SGND to select 400kHz, 530kHz or 250kHz, respectively.
A phase-locked loop (PLL) is available on the LTC3835-1
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. In this
case, a series R-C should be connected between the
PLLLPF pin and SGND to serve as the PLL’s loop filter.
The LTC3835-1 phase detector adjusts the voltage on the
PLLLPFpintoaligntheturn-onoftheexternaltopMOSFET
to the rising edge of the synchronizing signal.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. Thepeakinductorcurrentisdeterminedbythe
voltage on the I pin, just as in normal operation. In this
TH
mode, the efficiency at light loads is lower than in Burst
38351fc
10
LTC3835-1
OPERATION (Refer to Functional Diagram)
The typical capture range of the LTC3835-1’s phase-
locked loop is from approximately 115kHz to 800kHz,
with a guarantee to be between 140kHz and 650kHz. In
other words, the LTC3835-1’s PLL is guaranteed to lock
to an external clock source whose frequency is between
140kHz and 650kHz.
Output Overvoltage Protection
An overvoltage comparator guards against transient over-
shoots as well as other more serious conditions that may
overvoltage the output. When the V pin rises to more
than10%higherthanitsregulationpointof0.800V,thetop
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
FB
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
APPLICATIONS INFORMATION
R
SENSE
Selection for Output Current
The internal oscillator of the LTC3835-1 runs at a nominal
400kHz frequency when the PLLLPF pin is left floating
and the PLLIN/MODE pin is a DC low or high. Pulling the
R
is chosen based on the required output current.
SENSE
The current comparator has a maximum threshold of
PLLLPF to INTV selects 530kHz operation; pulling the
CC
100mV/R
and an input common mode range of
SENSE
PLLLPF to SGND selects 250kHz operation.
SGND to 10V. The current comparator threshold sets the
peak of the inductor current, yielding a maximum average
Alternatively, the LTC3835-1 will phase-lock to a clock
signal applied to the PLLIN/MODE pin with a frequency
between 140kHz and 650kHz (see Phase-Locked Loop
and Frequency Synchronization).
output current I
equal to the peak value less half the
MAX
peak-to-peak ripple current, ΔI .
L
Allowing a margin for variations in the IC and external
component values yields:
Inductor Value Calculation
80mV
IMAX
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
RSENSE
=
When using the controller in very low dropout conditions,
themaximumoutputcurrentlevelwillbereducedduetothe
internal compensation required to meet stability criterion
for buck regulators operating at greater than 50% duty
factor. A curve is provided to estimate this reduction in
peak output current level depending upon the operating
duty factor.
The inductor value has a direct effect on ripple current.
The inductor ripple current ΔI decreases with higher
Operating Frequency and Synchronization
L
inductance or frequency and increases with higher V :
IN
The choice of operating frequency, is a trade-off between
efficiency and component size. Low frequency operation
improvesefficiencybyreducingMOSFETswitchinglosses,
both gate charge loss and transition loss. However, lower
frequency operation requires more inductance for a given
amount of ripple current.
⎛
⎞
VOUT
1
ΔIL =
VOUT 1–
⎜
⎝
⎟
V
f L
( )( )
⎠
IN
38351fc
11
LTC3835-1
APPLICATIONS INFORMATION
Accepting larger values of ΔI allows the use of low
Power MOSFET and Schottky Diode (Optional)
Selection
L
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
Two external power MOSFETs must be selected for each
controller in the LTC3835-1: One N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
setting ripple current is ΔI = 0.3(I
). The maximum
MAX
L
ΔI occurs at the maximum input voltage.
L
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
Thepeak-to-peakdrivelevelsaresetbytheINTV voltage.
CC
This voltage is typically 5V during start-up (see EXTV
CC
10% of the current limit determined by R
. Lower
SENSE
Pin Connection). Consequently, logic-level threshold
inductor values (higher ΔI ) will cause this to occur at
L
MOSFETs must be used in most applications. The only
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
exception is if low input voltage is expected (V < 5V);
IN
GS(TH)
then, sub-logic level threshold MOSFETs (V
< 3V)
shouldbeused. PaycloseattentiontotheBV specification
for the MOSFETs as well; most of the logic level MOSFETs
are limited to 30V or less.
Inductor Core Selection
SelectioncriteriaforthepowerMOSFETsincludethe“ON”
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
affordthecorelossfoundinlowcostpowderedironcores,
forcingtheuseofmoreexpensiveferriteormolypermalloy
cores. Actual core loss is independent of core size for a
fixedinductorvalue,butitisverydependentoninductance
selected. As inductance increases, core losses go down.
Unfortunately, increased inductance requires more turns
of wire and therefore copper losses will increase.
resistance R
, Miller capacitance C
, input
DS(ON)
MILLER
voltage and maximum output current. Miller capacitance,
, can be approximated from the gate charge curve
C
MILLER
usually provided on the MOSFET manufacturers’ data
sheet. C is equal to the increase in gate charge
MILLER
along the horizontal axis while the curve is approximately
flat divided by the specified change in V . This result is
DS
then multiplied by the ratio of the application applied V
DS
to the Gate charge curve specified V . When the IC is
DS
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
VOUT
Main Switch Duty Cycle =
V
IN
V – VOUT
IN
Synchronous Switch Duty Cycle =
V
IN
38351fc
12
LTC3835-1
APPLICATIONS INFORMATION
The MOSFET power dissipations at maximum output
could cost as much as 3% in efficiency at high V . A 1A
IN
current are given by:
to 3A Schottky is generally a good compromise for both
regions of operation due to the relatively small average
current.Largerdiodesresultinadditionaltransitionlosses
due to their larger junction capacitance.
VOUT
2
PMAIN
=
I
1+ δ R
+
(
MAX) (
)
DS(ON)
V
IN
⎛
⎝
⎞
IMAX
2
2
V
R
C
•
(
)
(
DR )(
)
C and C
Selection
IN
MILLER
⎜
⎟
⎠
IN
OUT
Incontinuousmode,thesourcecurrentofthetopMOSFET
is a square wave of duty cycle (V )/(V ). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
⎡
⎢
⎣
⎤
1
1
+
f
( )
OUT
IN
⎥
⎦
V
INTVCC – VTHMIN VTHMIN
V – VOUT
2
IN
PSYNC
=
I
I+ δ R
(
MAX) (
)
DS(ON)
VIN
1/2
⎦
IMAX
⎡
⎤
CIN Required IRMS
≈
V
V – V
IN OUT
(
OUT )(
)
⎣
where δ is the temperature dependency of R
and
V
DS(ON)
IN
R
(approximately 2Ω) is the effective driver resistance
DR
This formula has a maximum at V = 2V , where I
RMS
at the MOSFET’s Miller threshold voltage. V
typical MOSFET minimum threshold voltage.
is the
IN
OUT
THMIN
= I /2. This simple worst-case condition is commonly
OUT
usedfordesignbecauseevensignificantdeviationsdonot
offermuchrelief.Notethatcapacitormanufacturers’ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operatingfrequencyoftheLTC3835-1, ceramiccapacitors
2
BothMOSFETshaveI RlosseswhilethetopsideN-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V < 20V
IN
the high current efficiency generally improves with larger
MOSFETs, while for V > 20V the transition losses rapidly
IN
increasetothepointthattheuseofahigherR
device
DS(ON)
withlowerC
actuallyprovideshigherefficiency.The
MILLER
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
can also be used for C . Always consult the manufacturer
IN
if there is any question.
The selection of C
is driven by the effective series
OUT
resistance (ESR). Typically, once the ESR requirement
The term (1 + δ) is generally given for a MOSFET in the
is satisfied, the capacitance is adequate for filtering. The
form of a normalized R
vs Temperature curve, but
DS(ON)
output ripple (ΔV ) is approximated by:
OUT
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
⎛
⎜
⎝
⎞
1
ΔVOUT ≈IRIPPLE ESR +
⎟
8fCOUT
TheoptionalSchottkydiodeD1showninFigure8conducts
during the dead-time between the conduction of the two
power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on, storing charge during
the dead-time and requiring a reverse recovery period that
⎠
where f is the operating frequency, C
is the output
OUT
capacitance and I
is the ripple current in the induc-
RIPPLE
tor. The output ripple is highest at maximum input voltage
since I increases with input voltage.
RIPPLE
38351fc
13
LTC3835-1
APPLICATIONS INFORMATION
Setting Output Voltage
200
100
The LTC3835-1 output voltage is set by an external feed-
back resistor divider carefully placed across the output,
as shown in Figure 1. The regulated output voltage is
determined by:
0
–100
–200
–300
–400
–500
–600
–700
⎛
⎞
RB
RA
VOUT = 0.8V • 1+
⎜
⎝
⎟
⎠
To improve the frequency response, a feed-forward ca-
0
1
2
3
4
5
10
6
7
8
9
pacitor, C , may be used. Great care should be taken to
FF
V
COMMON MODE VOLTAGE (V)
SENSE
route the V line away from noise sources, such as the
38351 F02
FB
inductor and the SW line.
Figure 2. SENSE Pins Input Bias Current
vs Common Mode (Output) Voltage
V
OUT
Tracking and Soft-Start (TRACK/SS Pin)
R
C
FF
B
A
LTC3835-1
V
The start-up of V
is controlled by the voltage on the
OUT
FB
TRACK/SS pin. When the voltage on the TRACK/SS pin is
less than the internal 0.8V reference, the LTC3835-1 regu-
R
3835-1 F01
lates the V pin voltage to the voltage on the TRACK/SS
FB
pin instead of 0.8V. The TRACK/SS pin can be used to
Figure 1. Setting Output Voltage
–
program an external soft-start function or to allow V
to “track” another supply during start-up.
OUT
+
SENSE and SENSE Pins
The common mode input range of the current comparator
is from 0V to 10V. Continuous linear operation is provided
throughout this range allowing output voltages from 0.8V
to 10V. The input stage of the current comparator requires
thatcurrenteitherbesourcedorsunkfromtheSENSEpins
depending on the output voltage, as shown in the curve in
Figure 2. If the output voltage is below 1.5V, current will
flow out of both SENSE pins to the main output. In these
LTC3835-1
TRACK/SS
C
SS
SGND
3835-1 F03
Figure 3. Using the TRACK/SS Pin to Program Soft-Start
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground, as shown in Figure 3.
An internal 1μA current source charges up the capacitor,
providing a linear ramping voltage at the TRACK/SS pin.
cases, the output can be easily pre-loaded by the V
OUT
resistordividertocompensateforthecurrentcomparator’s
negative input bias current. Since V is servoed to the
FB
The LTC3835-1 will regulate the V pin (and hence V
)
FB
OUT
0.8V reference voltage, R in Figure 1 should be chosen
A
according to the voltage on the TRACK/SS pin, allowing
to be less than 0.8V/I
, with I
determined from
SENSE
SENSE
V
OUT
to rise smoothly from 0V to its final regulated value.
Figure 2 at the specified output voltage.
The total soft-start time will be approximately:
0.8V
1μA
tSS = CSS
•
38351fc
14
LTC3835-1
APPLICATIONS INFORMATION
Alternatively, the TRACK/SS pin can be used to track two
(or more) supplies during start-up, as shown qualitatively
in Figures 4a and 4b. To do this, a resistor divider should
INTV Regulators
CC
TheLTC3835-1featuresaninternalP-channellowdropout
linear regulator (LDO) that supplies power at the INTV
CC
be connected from the master supply (V ) to the TRACK/
X
pin from the V supply pin. INTV powers the gate
IN
CC
SS pin of the slave supply (V ), as shown in Figure 5.
OUT
drivers and much of the LTC3835-1’s internal circuitry.
The V LDO regulates the voltage at the INTV pin to
During start-up V
will track V according to the ratio
OUT
X
IN
CC
set by the resistor divider:
5.25V. It can supply a peak current of 50mA and must be
bypassed to ground with a minimum of 4.7μF tantalum,
10μF special polymer, or low ESR electrolytic capacitor.
A ceramic capacitor with a minimum value of 4.7μF can
also be used if a 1Ω resistor is added in series with the
capacitor.Nomatterwhattypeofbulkcapacitorisused,an
additional 1μF ceramic capacitor placed directly adjacent
RTRACKA +RTRACKB
RA +RB
VX
RA
=
•
VOUT RTRACKA
For coincident tracking (V
= V during start-up),
OUT
X
R = R
A
TRACKA
TRACKB
to the INTV and PGND IC pins is highly recommended.
R = R
B
CC
Good bypassing is needed to supply the high transient
currents required by the MOSFET gate drivers and to
prevent interaction between the channels.
V (MASTER)
X
V (MASTER)
X
V
(SLAVE)
V
(SLAVE)
OUT
OUT
3835-1 F04B
TIME
TIME
3835-1 F04A
(4a) Coincident Tracking
(4b) Ratiometric Tracking
Figure 4. Two Different Modes of Output Voltage Tracking
V
V
OUT
x
LTC3835-1
FB
RB
V
RA
R
R
TRACKB
TRACK/SS
38351 F05
TRACKA
Figure 5. Using the TRACK/SS Pin for Tracking
38351fc
15
LTC3835-1
APPLICATIONS INFORMATION
Fault Conditions: Current Limit and Current Foldback
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the
maximum junction temperature rating for the LTC3835-1
The LTC3835-1 includes current foldback to help limit load
current when the output is shorted to ground. If the output
falls below 70% of its nominal output level, then the maxi-
mum sense voltage is progressively lowered from 100mV
to 30mV. Under short-circuit conditions with very low duty
cycles, the LTC3835-1 will begin cycle skipping in order to
limit the short-circuit current. In this situation the bottom
MOSFET will be dissipating most of the power but less than
innormaloperation.Theshort-circuitripplecurrentisdeter-
to be exceeded. The INTV current, which is dominated
CC
by the gate charge current, is supplied by the 5.25V V
IN
LDO. Power dissipation for the IC in this case is equal
to V • I . The gate charge current is dependent
IN
INTVCC
on operating frequency as discussed in the Efficiency
Considerations section. The junction temperature can be
estimated by using the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC3835-1
mined by the minimum on-time t
of the LTC3835-1
ON(MIN)
INTV current is limited to less than 25mA from a 24V
CC
(≈180ns), the input voltage and inductor value:
supply when in the GN package:
ΔI = t (V /L)
L(SC)
ON(MIN) IN
T = 70°C + (25mA)(24V)(90°C/W) = 125°C
J
The resulting short-circuit current is:
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (PLLIN/MODE
10mV
RSENSE
1
2
ISC =
– ΔIL(SC)
= INTV ) at maximum V .
CC
IN
Fault Conditions: Overvoltage Protection (Crowbar)
Topside MOSFET Driver Supply (C , D )
B
B
The overvoltage crowbar is designed to blow a system input
fusewhentheoutputvoltageoftheregulatorrisesmuchhigher
thannominallevels.Thecrowbarcauseshugecurrentstoflow,
that blow the fuse to protect against a shorted top MOSFET
if the short occurs while the controller is operating.
External bootstrap capacitors C connected to the BOOST
B
pins supply the gate drive voltages for the topside MOSFET.
Capacitor C in the Functional Diagram is charged though
B
externaldiodeD fromINTV whentheSWpinislow. When
B
CC
oneofthetopsideMOSFETistobeturnedon,thedriverplaces
A comparator monitors the output for overvoltage condi-
tions.Thecomparator(OV)detectsovervoltagefaultsgreater
than 10% above the nominal output voltage. When this
condition is sensed, the top MOSFET is turned off and the
bottomMOSFETisturnedonuntiltheovervoltagecondition
is cleared. The bottom MOSFET remains on continuously
theC voltageacrossthegate-sourceofthedesiredMOSFET.
B
This enhances the MOSFET and turns on the topside switch.
The switch node voltage, SW, rises to V and the BOOST pin
IN
follows. With the topside MOSFET on, the boost voltage is
above the input supply: V
= V + V
. The value
BOOST
IN
INTVCC
of the boost capacitor C needs to be 100 times that of the
B
for as long as the OV condition persists; if V
returns to
totalinputcapacitanceofthetopsideMOSFET(s).Thereverse
OUT
a safe level, normal operation automatically resumes. A
shorted top MOSFET will result in a high current condition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
breakdown of the external Schottky diode must be greater
than V . When adjusting the gate drive level, the final
IN(MAX)
arbiter is the total input current for the regulator. If a change
is made and the input current decreases, then the efficiency
has improved. If there is no change in input current, then
there is no change in efficiency.
38351fc
16
LTC3835-1
APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization
The output of the phase detector is a pair of complementary
currentsourcesthatchargeordischargetheexternalfilternet-
work connected to the PLLLPF pin. The relationship between
thevoltageonthePLLLPFpinandoperatingfrequency,when
there is a clock signal applied to PLLIN/MODE, is shown in
Figure 6 and specified in the Electrical Characteristics table.
NotethattheLTC3835-1canonlybesynchronizedtoanexter-
nalclockwhosefrequencyiswithinrangeoftheLTC3835-1’s
internal VCO, which is nominally 115kHz to 800kHz. This is
guaranteed to be between 140kHz and 650kHz. A simplified
block diagram is shown in Figure 7.
The LTC3835-1 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the top MOSFET
to be locked to the rising edge of an external clock signal
applied to the PLLIN/MODE pin. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
900
800
700
600
500
400
300
200
100
0
0
0.5
1
1.5
2
2.5
PLLLPF PIN VOLTAGE (V)
38351 F06
Figure 6. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
R
2.4V
LP
C
LP
PLLLPF
PLLIN/
MODE
DIGITAL
PHASE/
EXTERNAL
OSCILLATOR
FREQUENCY
DETECTOR
OSCILLATOR
3835-1 F07
Figure 7. Phase-Locked Loop Block Diagram
38351fc
17
LTC3835-1
APPLICATIONS INFORMATION
If the external clock frequency is greater than the internal
Minimum On-Time Considerations
Minimumon-timet isthesmallesttimedurationthat
the LTC3835-1 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
oscillator’s frequency, f , then current is sourced con-
OSC
ON(MIN)
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f , current is sunk continuously, pulling down
OSC
the PLLLPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
VOUT
tON(MIN)
<
V (f)
IN
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
the filter capacitor C holds the voltage.
LP
The loop filter components, C and R , smooth out the
LP
LP
current pulses from the phase detector and provide a stable
input to the voltage-controlled oscillator. The filter compo-
nents C and R determine how fast the loop acquires
Theminimumon-timefortheLTC3835-1isapproximately
180ns. However, as the peak sense voltage decreases the
minimum on-time gradually increases up to about 200ns.
This is of particular concern in forced continuous applica-
tions with low ripple current at light loads. If the duty cycle
drops below the minimum on-time limit in this situation,
a significant amount of cycle skipping can occur with cor-
respondingly larger current and voltage ripple.
LP
LP
lock. Typically R = 10k and C is 2200pF to 0.01μF.
LP
LP
Typically,theexternalclock(onPLLIN/MODEpin)inputhigh
threshold is 1.6V, while the input low threshold is 1.2V.
Table 1 summarizes the different states in which the
PLLLPF pin can be used.
Table 1
PLLLPF PIN
0V
PLLIN/MODE PIN
DC Voltage
FREQUENCY
250kHz
400kHz
Floating
DC Voltage
INTV
DC Voltage
530kHz
CC
RC Loop Filter
Clock Signal
Phase-Locked to External Clock
38351fc
18
LTC3835-1
APPLICATIONS INFORMATION
Efficiency Considerations
R
, but is “chopped” between the topside MOSFET
SENSE
andthesynchronousMOSFET.IfthetwoMOSFETshave
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
approximately the same R
, then the resistance
DS(ON)
of one MOSFET can simply be summed with the resis-
2
tances of L, R
and ESR to obtain I R losses. For
DS(ON)
SENSE
example, if each R
= 30mΩ, R = 50mΩ, R
L SENSE
= 10mΩ and R
= 40mΩ (sum of both input and
ESR
output capacitance losses), then the total resistance
is 130mΩ. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
a 5V output, or a 4% to 20% loss for a 3.3V output.
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Efficiency varies as the inverse square of V
for the
OUT
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
sameexternalcomponentsandoutputpowerlevel. The
combined effects of increasingly lower output voltages
andhighercurrentsrequiredbyhighperformancedigital
systemsisnotdoublingbutquadruplingtheimportance
of loss terms in the switching regulator system!
losses in LTC3835-1 circuits: 1) IC V current, 2) INTV
IN
CC
2
regulator current, 3) I R losses, 4) Topside MOSFET
transition losses.
1. The V current has two components: the first is the
IN
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
DCsupplycurrentgivenintheElectricalCharacteristics
table, which excludes MOSFET driver and control cur-
rents; the second is the current drawn from the 3.3V
linear regulator output. V current typically results in
IN
2
Transition Loss = (1.7) V
I
C
f
IN O(MAX) RSS
a small (<0.1%) loss.
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is
very important to include these “system” level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
2. INTV current is the sum of the MOSFET driver and
CC
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTV to ground. The resulting dQ/dt is a cur-
CC
C
has adequate charge storage and very low ESR at
IN
rent out of INTV that is typically much larger than the
CC
the switching frequency. A 25W supply will typically
require a minimum of 20μF to 40μF of capacitance hav-
ing a maximum of 20mΩ to 50mΩ of ESR. Other losses
including Schottky conduction losses during dead-time
and inductor core losses generally account for less than
2% total additional loss.
control circuit current. In continuous mode, I
GATECHG
= f(Q + Q ), where Q and Q are the gate charges of
T
B
T
B
the topside and bottom side MOSFETs.
2
3. I R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resis-
tor, and input and output capacitor ESR. In continuous
mode the average output current flows through L and
38351fc
19
LTC3835-1
APPLICATIONS INFORMATION
Checking Transient Response
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and I pin waveforms that will
TH
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive) load
give a sense of the overall loop stability without break-
ing the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
current. When a load step occurs, V
shifts by an amount
OUT
equal to ΔI
(ESR), where ESR is the effective series re-
LOAD
sistance of C . ΔI
also begins to charge or discharge
OUT
LOAD
C
OUT
generating the feedback error signal that forces the
regulator to adapt to the current change and return V
to
OUT
its steady-state value. During this recovery time V can be
OUT
is why it is better to look at the I pin signal which is in
TH
monitored for excessive overshoot or ringing, which would
indicateastabilityproblem.OPTI-LOOPcompensationallows
the transient response to be optimized over a wide range of
output capacitance and ESR values. The availability of the
the feedback loop and is the filtered and compensated
control loop response. The gain of the loop will be in-
creased by increasing R and the bandwidth of the loop
C
will be increased by decreasing C . If R is increased by
C
C
I pin not only allows optimization of control loop behavior
TH
the same factor that C is decreased, the zero frequency
C
but also provides a DC coupled and AC filtered closed-loop
response test point. The DC step, rise time and settling at
this test point truly reflects the closed-loop response. As-
sumingapredominantlysecondordersystem,phasemargin
and/or damping factor can be estimated using the percent-
age of overshoot seen at this pin. The bandwidth can also
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
be estimated by examining the rise time at the pin. The I
A second, more severe transient is caused by switching in
loads with large (>1μF) supply bypass capacitors. The dis-
charged bypass capacitors are effectively put in parallel with
TH
external components shown in Figure 10 circuit will provide
an adequate starting point for most applications.
C
, causing a rapid drop in V . No regulator can alter
OUT
OUT
The I series R -C filter sets the dominant pole-zero
TH
C
C
its delivery of current quickly enough to prevent this sudden
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
step change in output voltage if the load switch resistance
is low and it is driven quickly. If the ratio of C
to C
is
LOAD
OUT
greater than 1:50, the switch rise time should be controlled
so that the load rise time is limited to approximately 25 •
C
. Thus a 10μF capacitor would require a 250μs rise
LOAD
time, limiting the charging current to about 200mA.
38351fc
20
LTC3835-1
APPLICATIONS INFORMATION
Design Example
1.8V
22V
2
⎡
⎤
PMAIN
=
5
1+ 0.005 50°C – 25°C •
( )
(
)(
)
⎣
⎦
As a design example, assume V = 12V(nominal), V =
IN
IN
22V(max), V
= 1.8V, I
= 5A and f = 250kHz.
⎛
⎝
⎞
OUT
MAX
2 5A
0.035Ω + 22V
4Ω 215pF •
(
) (
)
(
)(
)
⎜
⎟
⎠
2
Theinductancevalueischosenfirstbasedona30%ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLLPF
pin to GND, generating 250kHz operation. The minimum
inductance for 30% ripple current is:
⎡
⎤
1
1
+
300kHz = 332mW
(
)
⎢
⎣
⎥
⎦
5 – 2.3 2.3
A short-circuit to ground will result in a folded back cur-
rent of:
⎛
⎞
VOUT
f L
( )( )
VOUT
ΔIL =
1–
⎜
⎟
V
⎝
⎠
⎛
⎞
25mV 1 120ns(22V)
IN
ISC =
–
= 2.1A
⎜
⎟
⎠
0.01Ω 2
3.3μH
⎝
A 4.7μH inductor will produce 23% ripple current and a
3.3μH will result in 33%. The peak inductor current will
be the maximum DC value plus one half the ripple cur-
rent, or 5.84A, for the 3.3μH value. Increasing the ripple
current will also help ensure that the minimum on-time
of 180ns is not violated. The minimum on-time occurs at
withatypicalvalueofR
The resulting power dissipated in the bottom MOSFET is:
andδ=(0.005/°C)(20)=0.1.
DS(ON)
22V – 1.8V
22V
2
PSYNC
=
2.1A 1.125 0.022Ω
(
) (
)(
)
maximum V :
= 100mW
IN
VOUT
IN(MAX)f
1.8V
which is less than under full-load conditions.
C is chosen for an RMS current rating of at least 3A at
tON(MIN)
=
=
= 327ns
V
22V 250kHz
(
)
IN
temperature assuming only this channel is on. C
is
OUT
The R
resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
SENSE
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
80mV
5.84A
RSENSE
≤
≈ 0.012Ω
V
= R (ΔI ) = 0.02Ω(1.67A) = 33mV
ESR L P-P
ORIPPLE
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
ThepowerdissipationonthetopsideMOSFETcanbeeasily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: R
= 0.035Ω/0.022Ω, C
= 215pF. At
DS(ON)
MILLER
maximum input voltage with T(estimated) = 50°C:
38351fc
21
LTC3835-1
APPLICATIONS INFORMATION
PC Board Layout Checklist
–
+
4. Are the SENSE and SENSE leads routed together with
minimumPCtracespacing?Thefiltercapacitorbetween
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 8. The Figure 9 illustrates the
current waveforms present in the various branches of the
synchronous regulator operating in the continuous mode.
Check the following in your layout:
+
–
SENSE and SENSE should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
5. Is the INTV decoupling capacitor connected close to
CC
theIC, betweentheINTV andthepowergroundpins?
CC
ThiscapacitorcarriestheMOSFETdriverscurrentpeaks.
Anadditional1μFceramiccapacitorplacedimmediately
1. Is the top N-channel MOSFET M1 located within 1cm
next to the INTV and PGND pins can help improve
CC
of C ?
IN
noise performance substantially.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
6. Keep the switching node (SW), top gate node (TG), and
boost node (BOOST) away from sensitive small-signal
nodes, especially from the opposites channel’s voltage
and current sensing feedback pins. All of these nodes
have very large and fast moving signals and therefore
should be kept on the “output side” of the LTC3835-1
and occupy minimum PC trace area.
of C
must return to the combined C
(–) ter-
INTVCC
OUT
minals. The path formed by the top N-channel MOSFET,
Schottky diode and the C capacitor should have short
IN
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
3. Does the LTC3835-1 V pin resistive divider connect to the
FB
capacitors with tie-ins for the bottom of the INTV
CC
(+) terminals of C ? The resistive divider must be con-
OUT
decouplingcapacitor,thebottomofthevoltagefeedback
nected between the (+) terminal of C and signal ground.
OUT
resistive divider and the SGND pin of the IC.
The feedback resistor connections should not be along the
high current input feeds from the input capacitor(s).
TRACK/SS
+
L1
R
SENSE
V
SENSE
TG
OUT
–
SENSE
SW
C
D
LTC3835EGN-1
BOOST
B
M1
M2
D1
OPTIONAL
V
FB
PLLLPF
V
IN
C
OUT
f
IN
PLLIN/MODE
RUN
BG
1μF
CERAMIC
R
+
IN
B
C
VIN
+
GND
+
I
INTV
TH
CC
C
IN
V
IN
C
INTVCC
SGND
PGND
3835-1 F08
Figure 8. LTC3835-1 Recommended Printed Circuit Layout Diagram
38351fc
22
LTC3835-1
APPLICATIONS INFORMATION
L1
R
SW
V
OUT
V
SENSE
IN
R
IN
C
IN
D1
C
R
L1
OUT
3835-1 F09
BOLD LINES INDICATE HIGH SWITCHING
CURRENT. KEEP LINES TO A MINIMUM LENGTH.
Figure 9. Branch Current Waveforms
PC Board Layout Debugging
Investigatewhetheranyproblemsexistonlyathigheroutput
currentsoronlyathigherinputvoltages.Ifproblemscoincide
with high input voltages and low output currents, look for
capacitive coupling between the BOOST, SW, TG, and pos-
sibly BG connections and the sensitive voltage and current
pins. The capacitor placed across the current sensing pins
needs to be placed immediately adjacent to the pins of the
IC.Thiscapacitorhelpstominimizetheeffectsofdifferential
noise injection due to high frequency capacitive coupling. If
problems are encountered with high current output loading
at lower input voltages, look for inductive coupling between
It is helpful to use a DC-50MHz current probe to monitor
thecurrentintheinductorwhiletestingthecircuit.Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator and probe the actual
outputvoltageaswell. Checkforproperperformanceover
the operating voltage and current range expected in the
application. The frequency of operation should be main-
tained over the input voltage range down to dropout and
until the output load drops below the low current opera-
tion threshold—typically 10% of the maximum designed
current level in Burst Mode operation.
C , Schottky and the top MOSFET components to the
IN
sensitive current and voltage sensing traces. In addition,
investigate common ground path voltage pickup between
these components and the SGND pin of the IC.
Thedutycyclepercentageshouldbemaintainedfromcycle
tocycleinawell-designed,lownoisePCBimplementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
Reduce V from its nominal level to verify operation
IN
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering V while
IN
monitoring the outputs to verify operation.
38351fc
23
LTC3835-1
TYPICAL APPLICATIONS
High Efficiency 9.5V, 3A Step-Down Converter
V
IN
PLLLPF
RUN
V
IN
4V TO 36V
C
10μF
IN
M1
TG
0.01μF
C
B
0.22μF
TRACK/SS
BOOST
SW
7.2μH
V
0.012Ω
OUT
9.5V
3A
I
TH
560pF
LTC3835-1
100pF
35k
C
OUT
SGND
PLLIN/MODE
INTV
150μF
CC
4.7μF
39.2k
M2
V
BG
FB
–
+
SENSE
SENSE
432k
PGND
38351 TA02
High Efficiency 12V to 1.8V, 2A Step-Down Converter
V
12V
IN
PLLLPF
RUN
V
IN
C
10μF
IN
M1
TG
0.01μF
C
B
0.22μF
TRACK/SS
BOOST
SW
3.3μH
V
1.8V
2A
0.020Ω
OUT
I
TH
330pF
33k
LTC3835-1
100pF
C
OUT
100μF
CERAMIC
SGND
PLLIN/MODE
INTV
CC
4.7μF
20k
M2
V
BG
FB
–
+
SENSE
SENSE
62.5k
PGND
38351 TA03
M1, M2: Si4840DY
L1 TOKO 053LC A915AY-3R3M
38351fc
24
LTC3835-1
TYPICAL APPLICATIONS
High Efficiency 5V, 5A Step-Down Converter
V
IN
PLLLPF
RUN
V
IN
4V TO
36V
C
10μF
IN
M1
TG
0.01μF
C
B
0.22μF
TRACK/SS
BOOST
SW
3.3μH
V
5V
5A
0.012Ω
OUT
I
TH
470pF
LTC3835-1
100pF
10k
C
OUT
150μF
SGND
PLLIN/MODE
INTV
CC
4.7μF
69.8k
M2
V
BG
FB
–
+
SENSE
SENSE
365k
PGND
38351 TA04
High Efficiency 1.2V, 5A Step-Down Converter
V
IN
GND
PLLLPF
RUN
V
IN
4V TO
36V
C
10μF
IN
M1
TG
0.01μF
C
B
0.22μF
TRACK/SS
BOOST
SW
2.2μH
V
1.2V
5A
0.012Ω
OUT
I
TH
2.2nF
10k
LTC3835-1
100pF
C
OUT
SGND
PLLIN/MODE
INTV
150μF
CC
4.7μF
118k
M2
V
BG
FB
–
+
SENSE
SENSE
59.5k
PGND
38351 TA05
38351fc
25
LTC3835-1
PACKAGE DESCRIPTION
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
0.65 0.05
3.50 0.05
1.65 0.05
2.20 0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
4.40 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
0.40 0.10
5.00 0.10
(2 SIDES)
9
16
R = 0.20
TYP
3.00 0.10
(2 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PIN 1
NOTCH
(DHC16) DFN 1103
8
1
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
4.40 0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
38351fc
26
LTC3835-1
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 .005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 .004
(0.38 0.10)
s 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
38351fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC3835-1
TYPICAL APPLICATION
V
IN
PLLLPF
RUN
V
IN
4V TO 36V
C
10μF
IN
TG
0.01μF
C
B
0.22μF
TRACK/SS
L1
3.3μH 0.012Ω
BOOST
SW
V
OUT
I
TH
3.3V
5A
1200pF
LTC3835-1
D
B
100pF
10k
CMDSH-3
C
OUT
150μF
SGND
PLLIN/MODE
INTV
CC
4.7μF
68.1k
V
BG
FB
–
+
SENSE
SENSE
215k
PGND
39pF
38351 TA06
M1, M2: Si7848DD
L1: CDEP 105-3R2M
C
: SANYO 10TPD150M
OUT
Figure 10. High Efficiency 3.3V, 5A Step-Down Converter
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Reduces C and C , Power Good Output Signal,
LTC1628/LTC1628-PG/ 2-Phase, Dual Output Synchronous Step-Down
IN
OUT
LTC1628-SYNC
DC/DC Controller
Synchronizable, 3.5V ≤ V ≤ 36V, I
Up to 20A,
OUT
IN
0.8V ≤ V
≤ 5V
OUT
LTC1629/
LTC1629-PG
20A to 200A PolyPhase® Synchronous Controllers
Expandable from 2-Phase to 12-Phase, Uses All
Surface Mount Components, No Heat Sink, V Up to 36V
IN
LTC1708-PG
2-Phase, Dual Synchronous Controller with Mobile VID
3.5V ≤ V ≤ 36V, VID Sets V
, PGOOD
OUT1
IN
LT1709/
LT1709-8
High Efficiency, 2-Phase Synchronous Step-Down
Switching Regulators with 5-Bit VID
1.3V ≤ V
≤ 3.5V, Current Mode Ensures
OUT
Accurate Current Sharing, 3.5V ≤ V ≤ 36V
IN
LTC1735
LTC1736
High Efficiency Synchronous Step-Down Switching Regulator Output Fault Protection, 16-Pin SSOP
High Efficiency Synchronous Controller with 5-Bit Mobile
VID Control
Output Fault Protection, 24-Pin SSOP,
3.5V ≤ V ≤ 36V
IN
LTC1778/LTC1778-1
No R
Current Mode Synchronous Step-Down
Up to 97% Efficiency, 4V ≤ V ≤ 36V, 0.8V ≤ V
≤ (0.9)(V ),
OUT IN
SENSE
IN
Controllers
I
Up to 20A
OUT
LTC3708
LTC3711
Dual, 2-Phase, DC/DC Controller with Output Tracking
Current Mode, No R
, Up/Down Tracking, Synchronizable
SENSE
No R
Current Mode Synchronous Step-Down
Up to 97% Efficiency, Ideal for Pentium® III Processors,
0.925V ≤ V ≤ 2V, 4V ≤ V ≤ 36V, I Up to 20A
SENSE
Controller with Digital 5-Bit Interface
OUT
IN
OUT
LTC3728
LTC3729
LTC3731
Dual, 550kHz, 2-Phase Synchronous Step-Down
Controller
Dual 180° Phased Controllers, V 3.5V to 35V, 99% Duty Cycle,
IN
5 × 5 QFN Package, SSOP-28
20A to 200A, 550kHz PolyPhase Synchronous Controller
Expandable from 2-Phase to 12-Phase, Uses All Surface Mount
Components, V Up to 36V
IN
3- to 12-Phase Step-Down Synchronous Controller
60A to 240A Output Current, 0.6V ≤ V
≤ 6V, 4.5V ≤ V ≤ 32V
IN
OUT
LTC3827/
LTC3827-1
Low I Dual Synchronous Controllers
2-Phase Operation; 115μA Total No Load I , 4V ≤ V ≤ 36V
Q IN
80μA No Load I with One Channel On
Q
Q
No R
is a trademark of Linear Technology Corporation. PolyPhase is a registered trademark of Linear Technology Corporation.
SENSE
38351fc
LT 0208 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 2006
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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