LTC3851EGN#PBF_技术文档

LTC3851

Synchronous

Step-Down Switching

Regulator Controller

FEATURES

DESCRIPTION

The LTC^®3851 is a high performance synchronous

step-down switching regulator controller that drives

an all N-channel synchronous power MOSFET stage. A

n

Wide V Range: 4V to 38V Operation

SENSE

±±1 Output Voltage Accuracy

IN

n

R

or DCR Current Sensing

n

Phase-Lockable Fixed Frequency: 250kHz to 750kHz constant frequency current mode architecture allows a

Dual N-Channel MOSFET Synchronous Drive

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Output Voltage Soft-Start or Tracking

Output Current Foldback Limiting

phase-lockable frequency of up to 750kHz.

OPTI-LOOP compensation allows the transient response

to be optimized over a wide range of output capacitance

and ESR values. The LTC3851 features a precision 0.8V

reference that is compatible with a wide 4V to 38V input

supply range.

Output Overvoltage Protection

5V Internal Regulator

OPTI-LOOP^®Compensation Minimizes C

OUT

The TK/SS pin ramps the output voltage during start-up.

Current foldback limits MOSFET heat dissipation during

short-circuit conditions. The MODE/PLLIN pin selects

among Burst Mode operation, pulse skipping mode or

continuousinductorcurrentmodeatlightloadsandallows

the IC to be synchronized to an external clock.

Selectable Continuous, Pulse-Skipping or

Burst Mode^®Operation at Light Loads

n

Low Shutdown I : 20μA

Q

V

Range: 0.8V to 5.5V

OUT

Thermally Enhanced 16-Lead MSOP, 16-Lead Narrow

SSOP or 3mm × 3mm QFN Package

The LTC3851-1 is a version with a power good output

signal instead of adjustable current limit.

L, LT, LTC, LTM, Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology

Corporation. All other trademarks are the property of their respective owners. Protected by

U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6304066, 6498466, 6580258,

6611131.

APPLICATIONS

n

Automotive Systems

n

Telecom Systems

Industrial Equipment

n

Distributed DC Power Systems

TYPICAL APPLICATION

High Efﬁciency Synchronous Step-Down Converter

Efﬁciency and Power Loss

vs Load Current

V

IN

4.5V TO 36V

I

V

IN

LIM

100

95

10000

1000

100

22μF

V

= 12V

IN

OUT

FREQ/PLLFLTR TG

= 3.3V

0.68μH

3.01k

V

OUT

0.1μF

82.5k

RUN

SW

3.3V

15A

90

LTC3851

0.1μF

EFFICIENCY

85

TK/SS

BOOST

330μF

s2

0.1μF

80

75

INTV

POWER LOSS

CC

2200pF

4.7μF

70

65

60

55

50

BG

I

TH

GND

330pF

15k

+

SENSE

MODE/PLLIN

SENSE

0.047μF

30.1k

–

154k

10

100

1000

10000

100000

V

FB

LOAD CURRENT (mA)

48.7k

3851TA01b

3851 TA01a

3851fb

1

LTC3851

ABSOLUTE MAXIMUM RATINGS ^{(Note ±)}

Input Supply Voltage (V ).........................40V to –0.3V

I , V Voltages..........................................3V to –0.3V

IN

TH FB

Topside Driver Voltage (BOOST) ................46V to –0.3V

INTV Peak Output Current ..................................50mA

CC

Switch Voltage (SW).....................................40V to –5V

Operating Temperature Range (Note 2)..–40°C to 125°C

Junction Temperature (Note 3) ............................. 125°C

Storage Temperature Range...................–65°C to 150°C

Lead Temperature (Soldering, 10 sec)

INTV , (BOOST – SW), RUN ......................6V to –0.3V

CC

TK/SS, I ............................................ INTV to –0.3V

LIM

CC

+

–

SENSE , SENSE ..........................................6V to –0.3V

MODE/PLLIN, FREQ/PLLFLTR............... INTV to –0.3V

GN/MSE............................................................ 300°C

CC

PIN CONFIGURATION

TOP VIEW

17

MODE/PLLIN

FREQ/PLLFLTR

RUN

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SW

1

2

3

4

5

6

7

8

MODE/PLLIN

FREQ/PLLFLTR

RUN

16 SW

TG

16 15 14 13

15 TG

14 BOOST

BOOST

RUN

1

2

3

4

12 BOOST

TK/SS

13 V

IN

TK/SS

V

IN

TK/SS

11

10

9

V

IN

I

12 INTV

11 BG

TH

CC

17

FB

I

INTV

I

TH

INTV

CC

–

+

TH

CC

SENSE

10 GND

9

I

FB

BG

LIM

FB

BG

–

5

6

7

8

MSE PACKAGE

16-LEAD PLASTIC MSOP

SENSE

GND

+

SENSE

I

LIM

T

= 125°C, θ = 35°C/W TO 40°C/W

JA

JMAX

EXPOSED PAD (PIN 17) IS GND,

MUST BE SOLDERED TO PCB

GN PACKAGE

16-LEAD PLASTIC SSOP NARROW

UD PACKAGE

16-LEAD (3mm s 3mm) PLASTIC QFN

T

JMAX

= 125°C, θ = 110°C/W

JA

T

= 125°C, θ = 68°C/W, θ = 4.2°C/W

JA JC

JMAX

EXPOSED PAD (PIN 17) IS GND,

MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC3851EGN#PBF

LTC3851IGN#PBF

LTC3851EMSE#PBF

LTC3851IMSE#PBF

LTC3851EUD#PBF

LTC3851IUD#PBF

TAPE AND REEL

PART MARKING*

3851

PACKAGE DESCRIPTION

16-Lead Plastic SSOP

16-Lead Plastic MSOP

TEMPERATURE RANGE

LTC3851EGN#TRPBF

LTC3851IGN#TRPBF

LTC3851EMSE#TRPBF

LTC3851IMSE#TRPBF

LTC3851EUD#TRPBF

LTC3851IUD#TRPBF

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

3851

LCXN

16-Lead (3mm × 3mm) Plastic QFN

LCXN

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

3851fb

2

LTC3851

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= ±5V, V_RUN= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loops

l

V

Operating Input Voltage Range

Regulated Feedback Voltage

Feedback Current

4

38

0.808

–50

V

IN

I

= 1.2V (Note 4)

0.792

0.800

–10

FB

TH

I

FB

(Note 4)

= 6V to 38V (Note 4)

nA

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

0.002

0.02

%/V

REFLNREG

LOADREG

IN

(Note 4)

l

Measured in Servo Loop,

0.01

0.1

%

ΔI = 1.2V to 0.7V

TH

(Note 4)

Measured in Servo Loop,

–0.01

–0.1

ΔI = 1.2V to 1.6V

TH

g

Transconductance Ampliﬁer g

I

TH

I

TH

= 1.2V, Sink/Source = 5μA (Note 4)

= 1.2V

2

3

mmho

MHz

m

GBW

Transconductance Amp Gain Bandwidth

m

I

Q

Input DC Supply Current

Normal Mode

Shutdown

(Note 5)

RUN

V

= 5V

= 0V

1.2

20

mA

μA

35

UVLO

Undervoltage Lockout on INTV

UVLO Hysteresis

V

Ramping Down

INTVCC

3.25

0.4

0.88

1

V

CC

UVLO Hys

l

V

Feedback Overvoltage Lockout

SENSE Pins Current

Measured at V

0.86

0.90

2

V

OVL

FB

I

μA

V

SENSE

TK/SS

Soft-Start Charge Current

RUN Pin On Threshold

RUN Pin On Hysteresis

V

TK/SS

= 0V

0.6

1

2

V

Rising

1.10

1.25

130

1.35

RUN

mV

RUNHYS

SENSE(MAX)

l

Maximum Current Sense Threshold

V

= 0.7V, V

= 3.3V, I = 0V

20

40

65

30

50

75

40

65

90

mV

FB

SENSE

LIM

= 3.3V, I = Float

= 3.3V, I = INTV

CC

TG R

BG R

TG Driver Pull-Up On-Resistance

TG Driver Pull-Down On-Resistance

BG Driver Pull-Up On-Resistance

BG Driver Pull-Down On-Resistance

TG High

TG Low

BG High

BG Low

(Note 6)

2.6

1.5

2.4

1.1

Ω

UP

DOWN

UP

DOWN

TG Transition Time

Rise Time

Fall Time

TG t

C

= 3300pF

25

ns

r

f

LOAD

= 3300pF

BG Transition Time

Rise Time

Fall Time

(Note 6)

LOAD

BG tr

BG tf

C

= 3300pF

25

ns

TG/BG t

Top Gate Off to Bottom Gate On Delay

Bottom Switch-On Delay Time

C

= 3300pF Each Driver

30

90

ns

1D

2D

LOAD

(Note 6)

BG/TG t

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

C

= 3300pF Each Driver

LOAD

(Note 6)

t

Minimum On-Time

(Note 7)

ON(MIN)

INTV Linear Regulator

CC

V

Internal V Voltage

6V < V < 38V

4.8

5

5.2

2

V

INTVCC

CC

IN

INT

INTV Load Regulation

I = 0mA to 50mA

CC

0.5

%

LDO

CC

3851fb

3

LTC3851

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= ±5V, V_RUN= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Oscillator and Phase-Locked Loop

f

Nominal Frequency

R

= 60k

= 160k

= 36k

480

220

710

500

250

750

100

530

280

790

kHz

kΩ

NOM

LOW

HIGH

FREQ

Lowest Frequency

Highest Frequency

R

MODE/PLLIN Input Resistance

MODE/PLLIN

MODE

f

MODE/PLLIN Minimum Input Frequency

MODE/PLLIN Maximum Input Frequency V

V

MODE

= External Clock

250

750

kHz

I

Phase Detector Output Current

Sinking Capability

Sourcing Capability

FREQ

f

> f

< f

–10

10

μA

MODE

OSC

Note ±: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: The LTC3851 is tested in a feedback loop that servos V to a

ITH

speciﬁed voltage and measures the resultant V

.

FB

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 2: The LTC3851E is guaranteed to meet performance speciﬁcations

from 0°C to 85°C. Speciﬁcations over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls. The LTC3851I is guaranteed to meet

speciﬁcations over the –40°C to 125°C operating temperature range.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 7: The minimum on-time condition is speciﬁed for an inductor

peak-to-peak ripple current ~40% of I

(see Minimum On-Time

MAX

Considerations in the Applications Information section).

Note 3: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formulas:

D

LTC3851GN: T = T + (P • 110°C/W)

J

A

D

LTC3851UD: T = T + (P • 68°C/W)

J

A

D

LTC3851MSE: T = T + (P • 40°C/W)

J

A

D

TYPICAL PERFORMANCE CHARACTERISTICS

Efﬁciency vs Output Current

and Mode

Efﬁciency vs Output Current

and Mode

Efﬁciency vs Output Current

and Mode

100

90

100

90

100

90

V

= 12V

IN

OUT

= 1.5V

BURST

80

BURST

70

PULSE

SKIP

PULSE

SKIP

60

50

60

50

60

50

PULSE

SKIP

CCM

40

30

20

10

0

40

30

20

10

0

40

30

20

10

0

CCM

V

= 12V

IN

OUT

V

= 12V

= 5V

= 3.3V

IN

OUT

V

FIGURE 11 CIRCUIT

10000 100000

LOAD CURRENT (mA)

10

100

1000

10000

100000

10

100

1000

10

100

1000

10000

100000

LOAD CURRENT (mA)

3851 G01

3851 G02

3851 G03

3851fb

4

LTC3851

TYPICAL PERFORMANCE CHARACTERISTICS

Efﬁciency and Power Loss

vs Input Voltage

Load Step

(Burst Mode Operation)

100

95

10000

1000

100

I

LOAD

EFFICIENCY,

= 5A

5A/DIV

I

POWER LOSS,

= 5A

OUT

0.2A TO 7.5A

I

OUT

I

L

90

5A/DIV

85

80

EFFICIENCY,

= 0.5A

V

OUT

I

OUT

100mV/DIV

AC-COUPLED

POWER LOSS,

I

= 0.5A

OUT

3851 G05

V

= 1.5V

OUT

IN

100μs/DIV

V

= 12V

75

70

IN

OUT

= 12V

= 3.3V

FIGURE 11 CIRCUIT

4

8

12

16

20 28

24 32

INPUT VOLTAGE (V)

3851 G04

Load Step

(Forced Continuous Mode)

Load Step

(Pulse-Skip Mode)

I

LOAD

5A/DIV

0.2A TO 7.5A

I

L

5A/DIV

V

OUT

100mV/DIV

AC-COUPLED

3851 G07

3851 G06

V

= 1.5V

100μs/DIV

V

= 1.5V

100μs/DIV

OUT

IN

OUT

IN

= 12V

FIGURE 11 CIRCUIT

Coincident Tracking with Master

Supply

Start-Up with Prebiased Output

at 2V

Inductor Current at Light Load

FORCED

CONTINOUS

MODE

V

MASTER

V

OUT

0.5V/DIV

V

2V/DIV

OUT

5A/DIV

TK/SS

0.5V/DIV

2A LOAD

0.5V/DIV

Burst Mode

OPERATION

5A/DIV

V

FB

0.5V/DIV

PULSE SKIP

MODE

5A/DIV

3851 G08

3851 G09

3851 G10

V

LOAD

= 1.5V

= 1mA

1μs/DIV

20ms/DIV

10ms/DIV

OUT

IN

= 12V

I

FIGURE 11 CIRCUIT

3851fb

5

LTC3851

TYPICAL PERFORMANCE CHARACTERISTICS

Ratiometric Tracking with Master

Supply

Input DC Supply Current

vs Input Voltage

INTV_CCLine Regulation

5.3

5.1

4.9

4.7

4.5

4.3

4.1

3.9

3.7

3.0

2.5

2.0

1.5

1.0

0.5

0

I

= 0mA

LOAD

V

MASTER

I

= 25mA

LOAD

0.5V/DIV

V

OUT

2A LOAD

0.5V/DIV

3851 G11

10ms/DIV

3.5

4

8

12 16 20 24 28 32 36 40

INPUT VOLTAGE (V)

4

8

12 16 20 24

INPUT VOLTAGE (V)

40

28 32 36

3851 G12

3851 G13

Burst Mode Peak Current Sense

Threshold vs I_THVoltage

Maximum Current Sense Threshold

vs Common Mode Voltage

Maximum Peak Current Sense

Threshold vs I_THVoltage

90

80

70

60

50

40

30

20

10

0

60

90

80

70

60

50

40

30

20

10

0

DUTY CYCLE RANGE: 0% TO 100%

MAXIMUIM

I

= INTV

CC

LIM

50

40

30

20

10

0

I

= INTV

LIM

CC

I

= FLOAT

I

= FLOAT

LIM

I

= GND

LIM

I

= GND

LIM

MINIMUIM

I

= FLOAT

LIM

BURST COMPARATOR FALLING THESHOLD:

= 0.4V

–10

–20

V

ITH

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

(V)

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

(V)

0

0.5

1

1.5

2

2.5

5

3

3.5 4 4.5

V

ITH

V

ITH

V

COMMON MODE VOLTAGE (V)

SENSE

3851 G16

3851 G15

3851 G14

Maximum Current Sense

Threshold vs Feedback Voltage

(Current Foldback)

TK/SS Pull-Up Current

vs Temperature

Maximum Current Sense

Threshold vs Duty Cycle

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

I

= INTV

CC

I

= INTV

CC

LIM

I

= FLOAT

= GND

I

= FLOAT

= GND

LIM

I

LIM

0

–50

0

25

50

75 100 125

–25

0.4 0.5

FEEDBACK VOLTAGE (V)

0

0.1 0.2 0.3

0.6 0.7 0.8

0

80

100

20

40

60

TEMPERATURE (°C)

DUTY CYCLE (%)

3851 G19

3851 G18

3851 G17

3851fb

6

LTC3851

TYPICAL PERFORMANCE CHARACTERISTICS

Oscillator Frequency

vs Temperature

Shutdown (RUN) Threshold

vs Temperature

Regulated Feedback Voltage

vs Temperature

1.4

1.3

1.2

1.1

1.0

0.9

900

800

806

804

802

800

R

= 36k

FREQ

RUN RISING THRESHOLD (ON)

RUN FALLING THRESHOLD (OFF)

700

600

500

400

300

R

= 60k

798

796

794

R

= 150k

50

FREQ

200

100 125

–50 –25

0

25

50

75 100 125

–50 –25

0

25

75

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

TEMPERATURE (°C)

3851 G20

3851 G22

3851 G21

Oscillator Frequency

vs Input Voltage

Undervoltage Lockout Threshold

(INTV_CC) vs Temperature

Shutdown Input DC Supply

Current vs Input Voltage

420

5

4

3

2

1

0

40

35

30

25

20

15

10

5

R

= 80k

FREQ

415

410

INTV RAMPING UP

CC

405

400

395

390

385

INTV RAMPING DOWN

CC

380

0

10

15

25

30

35

40

5

20

20 25

INPUT VOLTAGE (V)

0

5

10 15

30 35 40

–50 –25

0

25

50

75 100 125

INPUT VOLTAGE (V)

TEMPERATURE (°C)

3851 G23

3851 G25

3851 G24

Shutdown Input DC Supply

Current vs Temperature

Input DC Supply Current

vs Temperature

Maximum Current Sense

Threshold vs INTV_CCVoltage

40

3.0

2.5

2.0

1.5

90

80

70

60

50

40

30

20

10

I

= INTV

CC

SET

35

30

25

20

15

10

5

I

= FLOAT

SET

I

= GND

SET

1.0

0.5

0

–25

0

50

75 100 125

50

TEMPERATURE (°C)

100 125

–50

25

–50 –25

0

25

75

3.2 3.4 3.6 3.8 4.0 4.2

5.0

4.4 4.6 4.8

TEMPERATURE (°C)

INTV VOLTAGE(V)

CC

3851 G26

3851 G27

38511 G28

3851fb

7

LTC3851

PIN FUNCTIONS ^{(GN and MSE/UD)}

MODE/PLLIN (Pin ±/Pin ±5): Forced Continuous Mode,

Burst Mode or Pulse-Skipping Mode Selection Pin

and External Synchronization Input to Phase Detector

I

(Pin 9/Pin 7): Current Comparator Sense Voltage

LIM

Range Input. Tying this pin to GND, FLOAT or INTV

CC

selects the maximum current sense threshold from three

different levels.

Pin. Connect this pin to INTV to force continuous

CC

conduction mode of operation. Connect to GND to enable

GND(Pin±0/Pin8):Ground. Allsmall-signalcomponents

pulse-skipping mode of operation. To select Burst Mode

andcompensationcomponentsshouldbeKelvinconnected

operation, tie this pin to INTV through a resistor no less

CC

tothisground.The(–)terminalofCV andthe(–)terminal

CC

than 50k, but no greater than 250k. A clock on the pin will

cause the controller to operate in forced continuous mode

of operation and synchronize the internal oscillator.

of C should be closely connected to this pin.

IN

BG (Pin ±±/Pin 9): Bottom Gate Driver Output. This pin

drives the gate of the bottom N-channel MOSFET between

FREQ/PLLFLTR (Pin 2/Pin ±6): The phase-locked loop’s

lowpass ﬁlter is tied to this pin. Alternatively, a resistor

can be connected between this pin and GND to vary the

frequency of the internal oscillator.

GND and INTV .

CC

INTV (Pin±2/Pin±0):Internal5VRegulatorOutput. The

CC

control circuit is powered from this voltage. Decouple this

pin to GND with a minimum 2.2ꢀF low ESR tantalum or

ceramic capacitor.

RUN (Pin 3/Pin ±): Run Control Input. A voltage above

1.25V on this pin turns on the IC. However, forcing this

pin below 1.1V causes the IC to shut down the IC. There

is a 2ꢀA pull-up current on this pin.

V (Pin ±3/Pin ±±): Main Input Supply. Decouple this pin

to GND with a capacitor.

IN

BOOST (Pin ±4/Pin ±2): Boosted Floating Driver Supply.

The (+) terminal of the boost-strap capacitor is connected

to this pin. This pin swings from a diode voltage drop

below INTV up to V + INTV .

TK/SS(Pin4/Pin2):OutputVoltageTrackingandSoft-Start

Input. A capacitor to ground at this pin sets the ramp rate

for the output voltage. An internal soft-start current of of

1ꢀA charges this capacitor.

CC

IN

CC

TG (Pin ±5/Pin ±3): Top Gate Driver Output. This is the

I

(Pin 5/Pin 3): Current Control Threshold and Error

TH

output of a ﬂoating driver with a voltage swing equal to

Ampliﬁer Compensation Point. The current comparator

INTV superimposed on the switch node voltage.

tripping threshold increases with its I control voltage.

CC

TH

SW (Pin ±6/Pin ±4): Switch Node Connection to the

FB (Pin 6/Pin 4): Error Ampliﬁer Feedback Input. This pin

receives the remotely sensed feedback voltage from an

external resistive divider across the output.

Inductor.VoltageswingatthispinisfromaSchottkydiode

(external) voltage drop below ground to V .

IN

–

Exposed Pad (Pin ±7, UD and MSE Packages Only):

Ground. Must be soldered to PCB, providing a local

ground for the IC.

SENSE (Pin7/Pin5):CurrentSenseComparatorInverting

Input.The(–)inputtothecurrentcomparatorisconnected

to the output.

+

SENSE (Pin 8/Pin 6): Current Sense Comparator Non-

inverting Input. The (+) input to the current comparator

is normally connected to the DCR sensing network or

current sensing resistor.

3851fb

8

LTC3851

FUNCTIONAL DIAGRAM

V

IN

FREQ/PLLFLTR

MODE/PLLIN

V

IN

+

C

IN

100k

5V REG

0.8V

MODE/SYNC

DETECT

PLL-SYNC

–

+

BOOST

BURSTEN

C

B

TG

OSC

S

R

PULSE SKIP

ON

M1

Q

I

SW

SWITCH

LOGIC

AND

ANTI-

SHOOT

THROUGH

5k

+

SENSE

D

+

–

+

B

L1

I

V

CMP

REV

OUT

–

RUN

OV

INTV

BG

CC

+

I

LIM

C

OUT

M2

C

VCC

SLOPE COMPENSATION

GND

INTV

CC

UVLO

R2

1

100k

V

FB

I

THB

R1

+

–

V

SLEEP

IN

OV

0.88V

RUN

SS

–

+

0.8V

REF

1μA

EA

+ –

–

+

0.64V

1.25V

2μA

0.4V

3851 FD

I

TH

RUN

TK/SS

C

SS

R

C

C1

3851fb

9

LTC3851

OPERATION

Main Control Loop

pin and enable that controller. Alternatively, the RUN pin

may be externally pulled up or driven directly by logic.

Be careful not to exceed the absolute maximum rating of

6V on this pin.

The LTC3851 is a constant frequency, current mode step-

downcontroller.Duringnormaloperation,thetopMOSFET

isturnedonwhentheclocksetstheRSlatch, andisturned

off when the main current comparator, I

RS latch. The peak inductor current at which I

, resets the

CMP

The start-up of the controller’s output voltage, V , is

CMP

OUT

resets

controlled by the voltage on the TK/SS pin. When the

the RS latch is controlled by the voltage on the I pin,

voltage on the TK/SS pin is less than the 0.8V internal

TH

FB

which is the output of the error ampliﬁer EA. The V pin

reference, the LTC3851 regulates the V voltage to the

FB

receives the voltage feedback signal, which is compared

TK/SS pin voltage instead of the 0.8V reference. This

allows the TK/SS pin to be used to program a soft-start

by connecting an external capacitor from the TK/SS pin to

GND.Aninternal1μApull-upcurrentchargesthiscapacitor

creating a voltage ramp on the TK/SS pin. As the TK/SS

voltage rises linearly from 0V to 0.8V (and beyond), the

to the internal reference voltage by the EA. When the

load current increases, it causes a slight decrease in V

FB

relative to the 0.8V reference, which in turn causes the

I

voltage to increase until the average inductor current

TH

matches the new load current. After the top MOSFET has

turned off, the bottom MOSFET is turned on until either

the inductor current starts to reverse, as indicated by the

output voltage V

rises smoothly from zero to its ﬁnal

OUT

value. Alternatively, the TK/SS pin can be used to cause

the start-up of V to “track” another supply. Typically,

reverse current comparator, I , or the beginning of the

next cycle.

REV

OUT

this requires connecting to the TK/SS pin an external

resistor divider from the other supply to ground (see the

Applications Information section). When the RUN pin

INTV Power

CC

is pulled low to disable the controller, or when INTV

CC

Power for the top and bottom MOSFET drivers and most

drops below its undervoltage lockout threshold of 3.2V,

the TK/SS pin is pulled low by an internal MOSFET. When

in undervoltage lockout, the controller is disabled and the

external MOSFETs are held off.

other internal circuitry is derived from the INTV pin. An

CC

internal 5V low dropout linear regulator supplies INTV

CC

power from V .

IN

The top MOSFET driver is biased from the ﬂoating boot-

strapcapacitor, C , whichnormallyrechargesduringeach

Light Load Current Operation (Burst Mode Operation,

Pulse-Skipping or Continuous Conduction)

B

off cycle through an external diode when the top MOSFET

turns off. If the input voltage, V , decreases to a voltage

IN

The LTC3851 can be enabled to enter high efﬁciency Burst

Modeoperation,constantfrequencypulse-skippingmode

or forced continuous conduction mode. To select forced

close to V , the loop may enter dropout and attempt

OUT

to turn on the top MOSFET continuously. The dropout

detector detects this and forces the top MOSFET off for

about 1/10 of the clock period every tenth cycle to allow

continuous operation, tie the MODE/PLLIN pin to INTV .

CC

To select pulse-skipping mode of operation, ﬂoat the

C to recharge. However, it is recommended that there is

B

MODE/PLLIN pin or tie it to GND. To select Burst Mode

always a load present during the drop-out transition to

operation, tie MODE/PLLIN to INTV through a resistor

CC

ensure C is recharged.

B

no less than 50k, but no greater than 250k.

Shutdown and Start-Up (RUN and TK/SS)

When the controller is enabled for Burst Mode operation,

the peak current in the inductor is set to approximately

one-forth of the maximum sense voltage even though

The LTC3851 can be shut down using the RUN pin. Pulling

this pin below 1.1V disables the controller and most of the

the voltage on the I pin indicates a lower value. If the

TH

internalcircuitry,includingtheINTV regulator.Releasing

CC

average inductor current is higher than the load current,

the RUN pin allows an internal 2μA current to pull up the

3851fb

10

LTC3851

OPERATION

Frequency Selection and Phase-Locked Loop

the error ampliﬁer, EA, will decrease the voltage on the I

TH

(FREQ/PLLFLTR and MODE/PLLIN Pins)

pin. When the I voltage drops below 0.4V, the internal

TH

sleep signal goes high (enabling “sleep” mode) and both

Theselectionofswitchingfrequencyisatrade-offbetween

efﬁciency and component size. Low frequency operation

increasesefﬁciencybyreducingMOSFETswitchinglosses,

butrequireslargerinductanceand/orcapacitancetomain-

tain low output ripple voltage. The switching frequency

of the LTC3851 can be selected using the FREQ/PLLFLTR

pin. If the MODE/PLLIN pin is not being driven by an

external clock source, the FREQ/PLLFLTR pin can be used

to program the controller’s operating frequency from

250kHz to 750kHz.

external MOSFETs are turned off.

In sleep mode, the load current is supplied by the output

capacitor. Astheoutputvoltagedecreases, theEA’soutput

begins to rise. When the output voltage drops enough, the

sleep signal goes low, and the controller resumes normal

operation by turning on the top external MOSFET on the

next cycle of the internal oscillator. When a controller is

enabled for Burst Mode operation, the inductor current is

not allowed to reverse. The reverse current comparator,

I

, turnsoffthebottomexternalMOSFETjustbeforethe

REV

A phase-locked loop (PLL) is available on the LTC3851

to synchronize the internal oscillator to an external clock

source that is connected to the MODE/PLLIN pin. The

controlleroperatesinforcedcontinuousmodeofoperation

when it is synchronized. A series RC should be connected

between the FREQ/PLLFLTR pin and GND to serve as the

PLL’s loop ﬁlter. It is suggested that the external clock be

applied before enabling the controller unless a second

resistorisconnectedinparallelwiththeseriesRCnetwork.

Thesecondresistorpreventsverylowswitchingfrequency

operation if the controller is enabled before the clock.

inductor current reaches zero, preventing it from revers-

ing and going negative. Thus, the controller operates in

discontinuous operation. In forced continuous operation,

the inductor current is allowed to reverse at light loads

or under large transient conditions. The peak inductor

current is determined by the voltage on the I pin, just

TH

as in normal operation. In this mode the efﬁciency at light

loads is lower than in Burst Mode operation. However,

continuous mode has the advantages of lower output

ripple and less interference to audio circuitry.

When the MODE/PLLIN pin is connected to GND, the

LTC3851 operates in PWM pulse-skipping mode at light

Output Overvoltage Protection

loads.Atverylightloadsthecurrentcomparator,I

,may

CMP

An overvoltage comparator, OV, guards against transient

overshoots (>10%) as well as other more serious con-

ditions that may overvoltage the output. In such cases,

the top MOSFET is turned off and the bottom MOSFET is

turned on until the overvoltage condition is cleared.

remaintrippedforseveralcyclesandforcetheexternaltop

MOSFET to stay off for the same number of cycles (i.e.,

skipping pulses). The inductor current is not allowed to

reverse (discontinuous operation). This mode, like forced

continuousoperation, exhibitslowoutputrippleaswellas

low audio noise and reduced RF interference as compared

to Burst Mode operation. It provides higher low current

efﬁciency than forced continuous mode, but not nearly as

high as Burst Mode operation.

3851fb

11

LTC3851

APPLICATIONS INFORMATION

The Typical Application on the ﬁrst page of this data sheet

is a basic LTC3851 application circuit. The LTC3851 can

be conﬁgured to use either DCR (inductor resistance)

sensing or low value resistor sensing. The choice of the

two current sensing schemes is largely a design trade-off

between cost, power consumption and accuracy. DCR

sensing is becoming popular because it saves expensive

current sensing resistors and is more power efﬁcient,

especially in high current applications. However, current

sensing resistors provide the most accurate current limits

for the controller. Other external component selection

is driven by the load requirement, and begins with the

V

IN

INTV

CC

BOOST

TG

R

LTC3851

SENSE

V

OUT

SW

BG

GND

+

SENSE

–

SENSE

3851 F01

FILTER COMPONENTS

PLACED NEAR SENSE PINS

selection of R

(if R

is used) and the inductor

SENSE

value. Next, the power MOSFETs and Schottky diodes are

selected. Finally, input and output capacitors are selected.

The circuit shown on the ﬁrst page can be conﬁgured for

Figure ±. Using a Resistor to Sense Current with the LTC385±

The current comparator has a maximum threshold, V

,

MAX

operation up to 38V at V .

IN

determined by the I

setting. The current comparator

LIM

threshold sets the maximum peak of the inductor current,

Current Limit Programming

yieldingamaximumaverageoutputcurrent,I

,equalto

MAX

The I

pin is a tri-level logic input to set the maximum

the maximum peak value less half the peak-to-peak ripple

LIM

current limit of the controller. When I is grounded, the

current, ΔI . Allowing a margin of 20% for variations in

LIM

L

maximum current limit threshold of the current compara-

the IC and external component values yields:

tor is programmed to be 30mV. When I is ﬂoated, the

LIM

V_MAX

R_SENSE= 0.8 •

maximum current limit threshold is 50mV. When I

is

LIM

I_MAX+ ΔI_L/2

tied to INTV , the maximum current limit threshold is

CC

set to 75mV.

Inductor DCR Sensing

+

–

SENSE and SENSE Pins

Forapplicationsrequiringthehighestpossibleefﬁciency,

theLTC3851iscapableofsensingthevoltagedropacross

the inductor DCR, as shown in Figure 2. The DCR of the

inductor represents the small amount of DC winding

resistance of the copper, which can be less than 1mΩ for

today’s low value, high current inductors. If the external

R1||R2 • C1 time constant is chosen to be exactly equal

to the L/DCR time constant, the voltage drop across the

external capacitor is equal to the voltage drop across

the inductor DCR multiplied by R2/(R1 + R2). Therefore,

R2 may be used to scale the voltage across the sense

terminals when the DCR is greater than the target sense

resistance. Check the manufacturer’s data sheet for

speciﬁcations regarding the inductor DCR, in order to

properly dimension the external ﬁlter components. The

DCR of the inductor can also be measured using a good

+

–

The SENSE and SENSE pins are the inputs to the current

comparators. The common mode input voltage range of

the current comparators is 0V to 5.5V. Both SENSE pins

are high impedance inputs with small base currents of

less than 1ꢀA. When the SENSE pins ramp up from 0V

to 1.4V, the small base currents ﬂow out of the SENSE

pins. When the SENSE pins ramp down from 5V to 1.1V,

the small base currents ﬂow into the SENSE pins. The

high impedance inputs to the current comparators allow

accurate DCR sensing. However, care must be taken not

to ﬂoat these pins during normal operation.

Low Value Resistors Current Sensing

A typical sensing circuit using a discrete resistor is shown

in Figure 1. R

current.

is chosen based on the required output

SENSE

RLC meter.

3851fb

12

LTC3851

APPLICATIONS INFORMATION

Accepting larger values of ΔI allows the use of low

L

V

IN

V

IN

inductances, but results in higher output voltage ripple

INTV

CC

and greater core losses. A reasonable starting point for

BOOST

TG

setting ripple current is ΔI = 0.3(I

L

). The maximum

MAX

L

INDUCTOR

ΔI occurs at the maximum input voltage.

LTC3851

L

DCR

SW

V

OUT

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

BG

GND

R1

R2

+

SENSE

≈10% of the current limit determined by R

. Lower

SENSE

C1*

inductor values (higher ΔI ) will cause this to occur at

L

–

SENSE

lower load currents, which can cause a dip in efﬁciency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to increase.

L

DCR

+

–

3851 F02

R1||R2 • C1 =

*PLACE C1 NEAR SENSE , SENSE PINS

R2

R1 + R2

R

= DCR

SENSE(EQ)

Figure 2. Current Mode Control Using the Inductor DCR

Inductor Core Selection

Slope Compensation and Inductor Peak Current

Once the value for L is known, the type of inductor must

be selected. High efﬁciency converters generally cannot

affordthecorelossfoundinlowcostpowderedironcores,

forcingtheuseofmoreexpensiveferriteormolypermalloy

cores. Actual core loss is independent of core size for a

ﬁxedinductorvalue,butitisverydependentoninductance

selected. As inductance increases, core losses go down.

Unfortunately, increased inductance requires more turns

of wire and therefore copper losses will increase.

Slope compensation provides stability in constant

frequency architectures by preventing sub-harmonic

oscillationsathighdutycycles.Itisaccomplishedinternally

by adding a compensating ramp to the inductor current

signal. Normally, this results in a reduction of maximum

inductor peak current for duty cycles > 40%. However, the

LTC3851 uses a novel scheme that allows the maximum

inductor peak current to remain unaffected throughout

all duty cycles.

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

Inductor Value Calculation

The operating frequency and inductor selection are inter-

relatedinthathigheroperatingfrequenciesallowtheuseof

smaller inductor and capacitor values. A higher frequency

generally results in lower efﬁciency because of MOSFET

gate charge losses. In addition to this basic trade-off, the

effect of inductor value on ripple current and low current

operation must also be considered.

Power MOSFET and Schottky Diode (Optional)

Selection

The inductor value has a direct effect on ripple current.

The inductor ripple current ΔI decreases with higher

L

Two external power MOSFETs must be selected for the

LTC3851 controller: one N-channel MOSFET for the top

(main) switch, and one N-channel MOSFET for the bottom

(synchronous) switch.

inductance or frequency and increases with higher V :

IN

⎛

⎞

⎟

⎠

V_OUT

1

f •L

ΔI_L=

V_OUT1–

⎜

V

⎝

IN

3851fb

13

LTC3851

APPLICATIONS INFORMATION

2

BothMOSFETshaveI RlosseswhilethetopsideN-channel

Thepeak-to-peakdrivelevelsaresetbytheINTV voltage.

CC

equation includes an additional term for transition losses,

This voltage is typically 5V during start-up. Consequently,

logic-level threshold MOSFETs must be used in most ap-

plications. The only exception is if low input voltage is ex-

which are highest at high input voltages. For V < 20V,

IN

the high current efﬁciency generally improves with larger

MOSFETs, while for V > 20V, the transition losses rapidly

pected(V <5V);then,sub-logiclevelthresholdMOSFETs

IN

increasetothepointthattheuseofahigherR

device

(V

< 3V) should be used. Pay close attention to the

DS(ON)

GS(TH)

withlowerC

actuallyprovideshigherefﬁciency.The

BV

speciﬁcation for the MOSFETs as well; most of the

MILLER

DSS

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

short-circuit when the synchronous switch is on close to

100% of the period.

logic-level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the on-

resistance, R , Miller capacitance, C , input

DS(ON) MILLER

voltage and maximum output current. Miller capacitance,

, can be approximated from the gate charge curve

The term (1 + δ) is generally given for a MOSFET in the

C

MILLER

form of a normalized R

vs Temperature curve, but

usually provided on the MOSFET manufacturers’ data

sheet. C is equal to the increase in gate charge

DS(ON)

δ = 0.005/°C can be used as an approximation for low

MILLER

voltage MOSFETs.

along the horizontal axis while the curve is approximately

ﬂat divided by the speciﬁed change in V . This result is

DS

TheoptionalSchottkydiodeconductsduringthedeadtime

between the conduction of the two power MOSFETs. This

preventsthebodydiodeofthebottomMOSFETfromturn-

ing on, storing charge during the dead time and requiring

a reverse recovery period that could cost as much as 3%

then multiplied by the ratio of the application applied V

DS

to the gate charge curve speciﬁed V . When the IC is

DS

operating in continuous mode, the duty cycles for the top

and bottom MOSFETs are given by:

in efﬁciency at high V . A 1A to 3A Schottky is generally

V_OUT

Main Switch Duty Cycle =

V_IN

IN

a good size due to the relatively small average current.

Larger diodes result in additional transition losses due to

their larger junction capacitance.

V – V_OUT

IN

Synchronous Switch Duty Cycle =

V

IN

Soft-Start and Tracking

The MOSFET power dissipations at maximum output

current are given by:

The LTC3851 has the ability to either soft-start by itself

with a capacitor or track the output of another channel

or external supply. When the LTC3851 is conﬁgured to

soft-start by itself, a capacitor should be connected to

the TK/SS pin. The LTC3851 is in the shutdown state if

the RUN pin voltage is below 1.25V. TK/SS pin is actively

pulled to ground in this shutdown state.

V_OUT

2

P_MAIN

=

I

(

1+ δ R

+

(

)

MAX

DS(ON)

V

IN

I

⎛

⎞

⎠

2

MAX

2

V

R

C

•

(

)

(

_DR)(

)

IN

⎜

⎝

⎟

MILLER

⎡

⎢

⎤

⎥

1

Once the RUN pin voltage is above 1.25V, the LTC3851

powersup.Asoft-startcurrentof1ꢀAthenstartstocharge

its soft-start capacitor. Note that soft-start or tracking is

achieved not by limiting the maximum output current of

the controller but by controlling the output ramp voltage

according to the ramp rate on the TK/SS pin. Current

foldback is disabled during this phase to ensure smooth

soft-start or tracking. The soft-start or tracking range is

+

(f)

V

_{⎢ INTVCC}– V_TH(MIN)V_{TH(MIN) ⎥}

⎣

⎦

V – V_OUT

2

IN

P_SYNC

=

I

1+ δ R

DS(ON)

(

)

(

MAX

V

IN

where δ is the temperature dependency of R

and

DS(ON)

R

(approximately 2Ω) is the effective driver resistance

DR

at the MOSFET’s Miller threshold voltage. V

is the

TH(MIN)

typical MOSFET minimum threshold voltage.

3851fb

14

LTC3851

APPLICATIONS INFORMATION

0V to 0.8V on the TK/SS pin. The total soft-start time can

be calculated as:

Output Voltage Tracking

The LTC3851 allows the user to program how its output

ramps up and down by means of the TK/SS pins. Through

this pin, the output can be set up to either coincidentally or

ratiometricallytrackwithanothersupply’soutput,asshown

C_SS

t_SOFT-START= 0.8 •

1.0µA

inFigure3. Inthefollowingdiscussions, V

refersto

Regardless of the mode selected by the MODE/PLLIN pin,

the regulator will always start in pulse-skipping mode up

to TK/SS = 0.64V. Between TK/SS = 0.64V and 0.72V, it

will operate in forced continuous mode and revert to the

selected mode once TK/SS > 0.72V. The output ripple

is minimized during the 80mV forced continuous mode

window.

MASTER

a master supply and V

refers to the LTC3851’s output

OUT

as a slave supply. To implement the coincident tracking

in Figure 3a, connect a resistor divider to V and

MASTER

connect its midpoint to the TK/SS pin of the LTC3851. The

ratio of this divider should be selected the same as that of

the LTC3851’s feedback divider as shown in Figure 4a. In

this tracking mode, V

must be higher than V

.

MASTER

OUT

When the regulator is conﬁgured to track another supply,

the feedback voltage of the other supply is duplicated by a

resistordividerandappliedtotheTK/SSpin.Therefore,the

voltageramprateonthispinisdeterminedbytheramprate

of the other supply’s voltage. Note that the small soft-start

capacitor charging current is always ﬂowing, producing

a small offset error. To minimize this error, one can select

the tracking resistive divider value to be small enough to

make this error negligible.

To implement ratiometric tracking, the ratio of the resistor

divider connected to V

is determined by:

MASTER

⎛

⎞

⎠

V_OUT

R2 R3+R4

=

⎜

⎟

V_MASTERR4 R1+R2

⎝

So which mode should be programmed? While either

mode in Figure 4 satisﬁes most practical applications,

the coincident mode offers better output regulation.

This concept can be better understood with the help of

Figure 5. At the input stage of the error ampliﬁer, two

common anode diodes are used to clamp the equivalent

reference voltage and an additional diode is used to match

the shifted common mode voltage. The top two current

sources are of the same amplitude. In the coincident

In order to track down another supply after the soft-start

phase expires, the LTC3851 must be conﬁgured for forced

continuous operation by connecting MODE/PLLIN to

INTV .

CC

V

MASTER

OUT

MASTER

V

OUT

3851 F03

TIME

(3a) Coincident Tracking

(3b) Ratiometric Tracking

Figure 3. Two Different Modes of Output Voltage Tracking

3851fb

15

LTC3851

APPLICATIONS INFORMATION

V

OUT

MASTER

OUT

R3

R1

R2

R3

R4

TO

TK/SS

TO

FB

TO

TK/SS

TO

FB

V

R4

3851 F04

(4a) Coincident Tracking Setup

(4b) Ratiometric Tracking Setup

Figure 4. Setup for Coincident and Ratiometric Tracking

what type of bulk capacitor is used, an additional 0.1ꢀF

ceramic capacitor placed directly adjacent to the INTV

I

CC

and GND pins is highly recommended. Good bypassing

is needed to supply the high transient currents required

by the MOSFET gate drivers.

+

–

D1

D2

EA

TK/SS

0.8V

D3

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3851 to be

3851 F05

V

FB

Figure 5. Equivalent Input Circuit of Error Ampliﬁer

exceeded. The INTV current, which is dominated by the

CC

gate charge current, is supplied by the 5V LDO.

mode, the TK/SS voltage is substantially higher than

0.8V at steady-state and effectively turns off D1. D2 and

D3 will therefore conduct the same current and offer

Power dissipation for the IC in this case is highest and

is approximately equal to V • I

. The gate charge

IN INTVCC

current is dependent on operating frequency as discussed

in the Efﬁciency Considerations section. The junction

temperaturecanbeestimatedbyusingtheequationsgiven

in Note 3 of the Electrical Characteristics. For example,

tight matching between V and the internal precision

FB

0.8V reference. In the ratiometric mode, however, TK/SS

equals 0.8V at steady-state. D1 will divert part of the bias

current to make V slightly lower than 0.8V.

FB

the LTC3851 INTV current is limited to less than 14mA

CC

Although this error is minimized by the exponential I-V

characteristic of the diode, it does impose a ﬁnite amount

ofoutputvoltagedeviation.Furthermore,whenthemaster

supply’s output experiences dynamic excursion (under

load transient, for example), the slave channel output will

be affected as well. For better output regulation, use the

coincident tracking mode instead of ratiometric.

from a 36V supply in the GN package:

T = 70°C + (14mA)(36V)(110°C/W) = 125°C

J

To prevent the maximum junction temperature from being

exceeded, the input supply current must be checked while

operating in continuous conduction mode (MODE/PLLIN

= INTV ) at maximum V .

CC

IN

INTV Regulator

CC

Topside MOSFET Driver Supply (C , D )

B

TheLTC3851featuresaPMOSlowdropoutlinearregulator

An external bootstrap capacitor C connected to the

B

(LDO) that supplies power to INTV from the V supply.

CC

IN

BOOST pin supplies the gate drive voltage for the topside

INTV powersthegatedriversandmuchoftheLTC3851’s

CC

MOSFET.CapacitorC intheFunctionalDiagramischarged

B

internal circuitry. The LDO regulates the voltage at the

though external diode D from INTV when the SW pin

B

CC

INTV pin to 5V.

CC

is low. When the topside MOSFET is to be turned on, the

driver places the C voltage across the gate source of the

The LDO can supply a peak current of 50mA and must

be bypassed to ground with a minimum of 2.2ꢀF ceramic

capacitor or low ESR electrolytic capacitor. No matter

B

MOSFET. This enhances the MOSFET and turns on the

topside switch. The switch node voltage, SW, rises to V

IN

3851fb

16

LTC3851

APPLICATIONS INFORMATION

and the BOOST pin follows. With the topside MOSFET on,

the boost voltage is above the input supply:

any question.

Selection

C

OUT

V

= V + V

IN INTVCC

BOOST

The selection of C

is primarily determined by the

OUT

effective series resistance, ESR, to minimize voltage

The value of the boost capacitor C needs to be 100 times

B

ripple. The output ripple, ΔV , in continuous mode is

determined by:

that of the total input capacitance of the topside MOSFET.

OUT

The reverse breakdown of the external Schottky diode

must be greater than V

.

IN(MAX)

⎛

⎞

⎟

⎠

1

ΔV_OUT≈ ΔI ESR+

⎜

L

Undervoltage Lockout

8fC_OUT

⎝

The LTC3851 has two functions that help protect the

controller in case of undervoltage conditions. A precision

where f = operating frequency, C

= output capaci-

OUT

tance and ΔI = ripple current in the inductor. The output

UVLOcomparatorconstantlymonitorstheINTV voltage

L

CC

ripple is highest at maximum input voltage since ΔI

to ensure that an adequate gate-drive voltage is present.

L

increases with input voltage. Typically, once the ESR

It locks out the switching action when INTV is below

CC

requirementforC hasbeenmet,theRMScurrentrating

3.2V. To prevent oscillation when there is a disturbance

OUT

generally far exceeds the I

requirement. With

on the INTV , the UVLO comparator has 400mV of preci-

RIPPLE(P-P)

CC

ΔI = 0.3I

L

and allowing 2/3 of the ripple to be

sion hysteresis.

OUT(MAX)

due to ESR, the output ripple will be less than 50mV at

maximum V if the I pin is conﬁgured to ﬂoat and:

Another way to detect an undervoltage condition is to

IN

LIM

monitortheV supply.BecausetheRUNpinhasaprecision

IN

C_OUTRequired ESR < 2.2R_SENSE

1

turn-on reference of 1.25V, one can use a resistor divider

to V to turn on the IC when V is high enough.

IN

C_OUT

>

8fR_SENSE

C Selection

IN

Incontinuousmode,thesourcecurrentofthetopN-channel

TheﬁrstconditionrelatestotheripplecurrentintotheESR

oftheoutputcapacitancewhilethesecondtermguarantees

thattheoutputcapacitancedoesnotsigniﬁcantlydischarge

duringtheoperatingfrequencyperiodduetoripplecurrent.

The choice of using smaller output capacitance increases

the ripple voltage due to the discharging term but can be

compensated for by using capacitors of very low ESR to

MOSFET is a square wave of duty cycle V /V . To

OUT IN

preventlargevoltagetransients, alowESRinputcapacitor

sized for the maximum RMS current must be used. The

maximum RMS capacitor current is given by:

1/2

⎛

⎞

V_OUT

V_IN

I_RMS≅I_O(MAX)

–1

⎜

⎟

maintain the ripple voltage at or below 50mV. The I pin

V

⎝

⎠

TH

OUT

OPTI-LOOP compensation components can be optimized

to provide stable, high performance transient response

regardless of the output capacitors selected.

This formula has a maximum at V = 2V , where

IN

OUT

I

= I

/2. This simple worst-case condition is

RMS

O(MAX)

commonly used for design because even signiﬁcant

deviations do not offer much relief. Note that capacitor

manufacturers’ ripple current ratings are often based on

only 2000 hours of life. This makes it advisable to further

derate the capacitor or to choose a capacitor rated at a

higher temperature than required. Several capacitors may

also be paralleled to meet size or height requirements in

the design. Always consult the manufacturer if there is

The selection of output capacitors for applications with

largeloadcurrenttransientsisprimarilydeterminedbythe

voltage tolerance speciﬁcations of the load. The resistive

component of the capacitor, ESR, multiplied by the load

current change, plus any output voltage ripple must be

within the voltage tolerance of the load.

3851fb

17

LTC3851

APPLICATIONS INFORMATION

The required ESR due to a load current step is:

ΔV

AVX TPSV or the KEMET T510 series of surface mount

tantalums, available in case heights ranging from 1.5mm

to 4.1mm. Aluminum electrolytic capacitors can be used

in cost-driven applications, provided that consideration

is given to ripple current ratings, temperature and long-

term reliability. A typical application will require several

to many aluminum electrolytic capacitors in parallel. A

combination of the above mentioned capacitors will often

result in maximizing performance and minimizing overall

cost.OthercapacitortypesincludeNichiconPLseries,NEC

Neocap, Panasonic SP and Sprague 595D series. Consult

manufacturers for other speciﬁc recommendations.

R_ESR

≤

ΔI

whereΔIisthechangeincurrentfromfullloadtozeroload

(orminimumload)andΔVistheallowedvoltagedeviation

(not including any droop due to ﬁnite capacitance).

The amount of capacitance needed is determined by the

maximum energy stored in the inductor. The capacitance

must be sufﬁcient to absorb the change in inductor

current when a high current to low current transition

occurs. The opposite load current transition is generally

determined by the control loop OPTI-LOOP components,

so make sure not to over compensate and slow down

the response. The minimum capacitance to assure the

inductors’ energy is adequately absorbed is:

Like all components, capacitors are not ideal. Each

capacitor has its own beneﬁts and limitations. Combina-

tions of different capacitor types have proven to be a very

cost effective solution. Remember also to include high

frequency decoupling capacitors. They should be placed

as close as possible to the power pins of the load. Any

inductance present in the circuit board traces negates

their usefulness.

2

L ΔI

( )

C_OUT

where

>

2 ΔV V

(

)

OUT

Δ

I is the change in load current.

Setting Output Voltage

Manufacturers such as Nichicon, United Chemi-Con and

Sanyo can be considered for high performance through-

hole capacitors. The OS-CON semiconductor electrolyte

capacitor available from Sanyo has the lowest (ESR)(size)

product of any aluminum electrolytic at a somewhat

higher price. An additional ceramic capacitor in parallel

with OS-CON capacitors is recommended to reduce the

inductance effects.

The LTC3851 output voltage is set by an external feedback

resistive divider carefully placed across the output,

as shown in Figure 6. The regulated output voltage is

determined by:

⎛

⎞

⎟

R_B

R_A

V_OUT= 0.8V 1+

⎜

⎝

⎠

Insurfacemountapplications,ESR,RMScurrenthandling

andloadstepspeciﬁcationsmayrequiremultiplecapacitors

in parallel. Aluminum electrolytic, dry tantalum and

special polymer capacitors are available in surface mount

packages.Specialpolymersurfacemountcapacitorsoffer

very low ESR but have much lower capacitive density per

unit volume than other capacitor types. These capacitors

offeraverycost-effectiveoutputcapacitorsolutionandare

an ideal choice when combined with a controller having

highloopbandwidth.Tantalumcapacitorsofferthehighest

capacitancedensityandareoftenusedasoutputcapacitors

for switching regulators having controlled soft-start.

Several excellent surge-tested choices are the AVX TPS,

To improve the transient response, a feed-forward ca-

pacitor, C , may be used. Great care should be taken to

FF

route the V line away from noise sources, such as the

FB

inductor or the SW line.

V

OUT

R

C

FF

LTC3851

B

A

V

FB

R

3851 F06

Figure 6. Settling Output Voltage

3851fb

18

LTC3851

APPLICATIONS INFORMATION

Fault Conditions: Current Limit and Current Foldback

Phase-Locked Loop and Frequency Synchronization

The LTC3851 includes current foldback to help limit load

current when the output is shorted to ground. If the

output falls below 40% of its nominal output level, the

maximum sense voltage is progressively lowered from

its maximum programmed value to about 25% of the that

value. Foldback current limiting is disabled during soft-

start or tracking. Under short-circuit conditions with very

low duty cycles, the LTC3851 will begin cycle skipping in

order to limit the short-circuit current. In this situation

the bottom MOSFET will be dissipating most of the power

but less than in normal operation. The short-circuit ripple

current is determined by the minimum on-time t_ON(MIN)

of the LTC3851 (≈90ns), the input voltage and inductor

value:

The LTC3851 has a phase-locked loop (PLL) comprised of

an internal voltage-controlled oscillator (V ) and a phase

CO

detector. This allows the turn-on of the top MOSFET to

be locked to the rising edge of an external clock signal

applied to the MODE/PLLIN pin. This phase detector is

an edge sensitive digital type that provides zero degrees

phase shift between the external and internal oscillators.

This type of phase detector does not exhibit false lock to

harmonics of the external clock.

Theoutputofthephasedetectorisapairofcomplementary

current sources that charge or discharge the external ﬁlter

network connected to the FREQ/PLLFLTR pin. Note that

the LTC3851 can only be synchronized to an external clock

whose frequency is within range of the LTC3851’s internal

V

V .Thisisguaranteedtobebetween250kHzand750kHz.

CO

IN

L

ΔI_L(SC)= t_ON(MIN)

•

A simpliﬁed block diagram is shown in Figure 8.

The resulting short-circuit current is:

If the external clock frequency is greater than the internal

oscillator’s frequency, f

, then current is sunk con-

OSC

1/4MaxV_SENSE

R_SENSE

1

2

tinuouslyfromthephasedetectoroutput,pullingdownthe

I_SC=

– ΔI_L(SC)

FREQ/PLLFLTR pin. When the external clock frequency is

less than f

, current is sourced continuously, pulling up

OSC

Programming Switching Frequency

theFREQ/PLLFLTRpin.Iftheexternalandinternalfrequen-

ciesarethesamebutexhibitaphasedifference,thecurrent

sourcesturnonforanamountoftimecorrespondingtothe

phase difference. The voltage on the FREQ/PLLFLTR pin is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

To set the switching frequency of the LTC3851, connect

a resistor, R , between FREQ/PLLFLTR and GND. The

FREQ

relationship between the oscillator frequency and R

is shown in Figure 7. A 0.1μF bypass capacitor should be

FREQ

connected in parallel with R

.

FREQ

750

700

650

600

550

500

450

400

350

300

250

the ﬁlter capacitor C holds the voltage.

LP

R

LP

2.7V

C

LP

FREQ/PLLFLTR

VCO

MODE/

PLLIN

DIGITAL

PHASE/

FREQUENCY

DETECTOR

EXTERNAL

OSCILLATOR

20

40

60

80 100 120 140 160

(k)

R

FREQ

3851 F07

3851 F08

Figure 7. Relationship Between Oscillator Frequency

and Resistor Connected Between FREQ/PLLFLTR and GND

Figure 8. Phase-Locked Loop Block Diagram

3851fb

19

LTC3851

APPLICATIONS INFORMATION

amount of cycle skipping can occur with correspondingly

larger current and voltage ripple.

The loop ﬁlter components, C and R , smooth out

LP

the current pulses from the phase detector and provide

a stable input to the voltage-controlled oscillator. The

Efﬁciency Considerations

ﬁlter components C and R determine how fast the

LP

loop acquires lock. Typically R is 1k to 10k and C is

LP

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Percent efﬁciency can

be expressed as:

2200pF to 0.01ꢀF.

When the external oscillator is active before the LTC3851

is enabled, the internal oscillator frequency will track the

externaloscillatorfrequencyasdescribedinthepreceding

paragraphs. In situations where the LTC3851 is enabled

before the external oscillator is active, a low free-running

oscillatorfrequencyofapproximately50kHzwillresult.Itis

possibletoincreasethefree-running,pre-synchronization

frequency by adding a second resistor in parallel with

%Efﬁciency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

R

LP

and C . The second resistor will also cause a phase

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

LP

difference between the internal and external oscillator

signals.Themagnitudeofthephasedifferenceisinversely

proportional to the value of the second resistor.

losses in LTC3851 circuits: 1) IC V current, 2) INTV

IN

CC

2

regulator current, 3) I R losses, 4) topside MOSFET

transition losses.

The external clock (on MODE/PLLIN pin) input high

threshold is nominally 1.6V, while the input low threshold

is nominally 1.2V.

1. The V current is the DC supply current given in the

IN

ElectricalCharacteristicstable,whichexcludesMOSFET

driver current. V current typically results in a small

IN

Minimum On-Time Considerations

(<0.1%) loss.

Minimum on-time t

is the smallest time duration

ON(MIN)

2. INTV_CCcurrent is the sum of the MOSFET driver and

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge dQ moves

fromINTV_CCtoground. TheresultingdQ/dtisacurrent

out of INTV_CCthat is typically much larger than the

control circuit current. In continuous mode, I_GATECHG

= f(Q_T+ Q_B), where Q_Tand Q_Bare the gate charges of

the topside and bottom side MOSFETs.

that the LTC3851 is capable of turning on the top MOSFET.

It is determined by internal timing delays and the gate

charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

V_OUT

t_ON(MIN)

<

V (f)

IN

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

2

3. I R losses are predicted from the DC resistances of

the fuse (if used), MOSFET, inductor and current sense

resistor.Incontinuousmode,theaverageoutputcurrent

ﬂows through L and R

, but is “chopped” between

SENSE

The minimum on-time for the LTC3851 is approximately

90ns. However, as the peak sense voltage decreases the

minimum on-time gradually increases. This is of particu-

lar concern in forced continuous applications with low

ripple current at light loads. If the duty cycle drops below

the minimum on-time limit in this situation, a signiﬁcant

the topside MOSFET and the synchronous MOSFET. If

thetwoMOSFETshaveapproximatelythesameR

,

DS(ON)

then the resistance of one MOSFET can simply be

summed with the resistances of L and R

to obtain

SENSE

= 10mꢁ, DCR

2

I R losses. For example, if each R

DS(ON)

= 10mꢁ and R

= 5mꢁ, then the total resistance

SENSE

3851fb

20

LTC3851

APPLICATIONS INFORMATION

is 25mꢁ. This results in losses ranging from 2% to

8% as the output current increases from 3A to 15A for

a 5V output, or a 3% to 12% loss for a 3.3V output.

rise time and settling at this test point truly reﬂects the

closed-loop response. Assuming a predominantly second

ordersystem, phasemarginand/ordampingfactorcanbe

estimated using the percentage of overshoot seen at this

pin.Thebandwidthcanalsobeestimatedbyexaminingthe

Efﬁciency varies as the inverse square of V

for the

OUT

sameexternalcomponentsandoutputpowerlevel. The

combined effects of increasingly lower output voltages

andhighercurrentsrequiredbyhighperformancedigital

systemsisnotdoublingbutquadruplingtheimportance

of loss terms in the switching regulator system!

rise time at the pin. The I external components shown

TH

in the Typical Application circuit will provide an adequate

starting point for most applications.

The I series R -C ﬁlter sets the dominant pole-zero

TH

C

4. Transition losses apply only to the topside MOSFET(s),

and become signiﬁcant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

loop compensation. The values can be modiﬁed slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the ﬁnal PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1ꢀs to 10ꢀs will

2

Transition Loss = (1.7)V • I

• C

• f

RSS

IN

O(MAX)

Other “hidden” losses such as copper trace and the bat-

tery internal resistance can account for an additional 5%

to 10% efﬁciency degradation in portable systems. It is

very important to include these “system” level losses

during the design phase. The internal battery and fuse

resistance losses can be minimized by making sure that

produce output voltage and I pin waveforms that will

TH

give a sense of the overall loop stability without breaking

the feedback loop. Placing a power MOSFET directly

across the output capacitor and driving the gate with an

appropriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This

C has adequate charge storage and very low ESR at the

IN

switching frequency. A 25W supply will typically require a

minimum of 20ꢀF to 40ꢀF of capacitance having a maxi-

mum of 20mꢁ to 50mꢁ of ESR. Other losses including

Schottky conduction losses during dead time and induc-

tor core losses generally account for less than 2% total

additional loss.

is why it is better to look at the I pin signal which is in

TH

the feedback loop and is the ﬁltered and compensated

control loop response. The midband gain of the loop will

Checking Transient Response

be increased by increasing R and the bandwidth of the

C

loop will be increased by decreasing C . If R is increased

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

C

bythesamefactorthatC isdecreased,thezerofrequency

C

will be kept the same, thereby keeping the phase shift the

same in the most critical frequency range of the feedback

loop. The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

the actual overall supply performance.

load current. When a load step occurs, V

shifts by an

OUT

amount equal to ΔI

(ESR), where ESR is the effective

LOAD

series resistance of C . ΔI

also begins to charge or

OUT LOAD

discharge C

generating the feedback error signal that

OUT

forces the regulator to adapt to the current change and

A second, more severe transient is caused by switching

in loads with large (>1ꢀF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

return V

time V

to its steady-state value. During this recovery

can be monitored for excessive overshoot or

OUT

ringing, which would indicate a stability problem. The

with C , causing a rapid drop in V . No regulator can

OUT

availability of the I pin not only allows optimization of

TH

alter its delivery of current quickly enough to prevent this

control loop behavior but also provides a DC coupled and

sudden step change in output voltage if the load switch

AC ﬁltered closed-loop response test point. The DC step,

resistance is low and it is driven quickly. If the ratio of

3851fb

21

LTC3851

APPLICATIONS INFORMATION

C

to C

is greater than 1:50, the switch rise time

2. Does the V pin connect directly to the feedback resis-

LOAD

OUT

FB

should be controlled so that the load rise time is limited

to approximately 25 • C . Thus a 10ꢀF capacitor would

tors? The resistive divider R1, R2 must be connected

between the (+) plate of C

and signal ground. The

LOAD

OUT

require a 250ꢀs rise time, limiting the charging current

to about 200mA.

47pF to 100pF capacitor should be as close as possible

to the LTC3851. Be careful locating the feedback resis-

tors too far away from the LTC3851. The V line should

FB

PC Board Layout Checklist

not be routed close to any other nodes with high slew

rates.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3851. These items are also illustrated graphically

in the layout diagram of Figure 9. Check the following in

your layout:

–

+

3. Are the SENSE and SENSE leads routed together

with minimum PC trace spacing? The ﬁlter capaci-

+

–

tor between SENSE and SENSE should be as close

as possible to the LTC3851. Ensure accurate current

sensing with Kelvin connections as shown in Figure

10. Series resistance can be added to the SENSE lines

to increase noise rejection and to compensate for the

1. Are the board signal and power grounds segregated?

The LTC3851 GND pin should tie to the ground plane

closetotheinputcapacitor(s).Thelowcurrentorsignal

ground lines should make a single point tie directly to

the GND pin. The synchronous MOSFET source pins

should connect to the input capacitor(s) ground.

ESL of R

.

SENSE

+

0.1μF

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

MODE/PLLIN

SW

TG

R

FREQ

C

IN

M1

FREQ/PLLFLTR

C

D

B

RUN

BOOST

V

IN

LTC3851

C

SS

TK/SS

V

IN

B

C

C2

C

R

C

I

TH

INTV

CC

47pF

+

M2

V

BG

4.7μF

FB

–

+

SENSE

GND

–

1000pF

10Ω

I

LIM

L1

10Ω

–

R1

C

OUT

V

OUT

+

R

SENSE

R2

+

3851 F09

Figure 9. LTC385± Layout Diagram

3851fb

22

LTC3851

APPLICATIONS INFORMATION

gest noise pick-up at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regulator

bandwidth optimization is not required.

HIGH CURRENT PATH

Reduce V from its nominal level to verify operation

3851 F10

IN

of the regulator in dropout. Check the operation of the

undervoltage lockout circuit by further lowering V while

IN

CURRENT SENSE

RESISTOR

(R

monitoring the outputs to verify operation.

)

SENSE

+

–

SENSE SENSE

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

Figure ±0. Kelvin Sensing R_SENSE

4. Does the (+) terminal of C connect to the drain of

IN

the topside MOSFET(s) as closely as possible? This

capacitor provides the AC current to the MOSFET(s).

5. Is the INTV decoupling capacitor connected closely

CC

between INTV and GND? This capacitor carries the

CC

MOSFETdriverpeakcurrents.Anadditional1ꢀFceramic

capacitor placed immediately next to the INTV and

CC

GND pins can help improve noise performance.

for inductive coupling between C , the Schottky and the

IN

6. Keep the switching node (SW), top gate node (TG) and

boost node (BOOST) away from sensitive small-signal

nodes, especially from the voltage and current sensing

feedback pins. All of these nodes have very large and

fast moving signals and therefore should be kept on

the “output side” (Pin 9 to Pin 16) of the LTC3851EGN

and occupy minimum PC trace area.

top MOSFET to the sensitive current and voltage sensing

traces. In addition, investigate common ground path

voltage pickup between these components and the GND

pin of the IC.

Design Example

As a design example, assume V = 12V (nominal), V =

IN

MAX

IN

22V (maximum), V

Refer to Figure 13.

= 1.8V, I

= 5A, and f = 250kHz.

OUT

PC Board Layout Debugging

It is helpful to use a DC-50MHz current probe to monitor

thecurrentintheinductorwhiletestingthecircuit.Monitor

the output switching node (SW pin) to synchronize the

oscilloscope to the internal oscillator and probe the actual

outputvoltageaswell. Checkforproperperformanceover

the operating voltage and current range expected in the

application. The frequency of operation should be main-

tained over the input voltage range down to dropout and

until the output load drops below the low current opera-

tion threshold—typically 10% of the maximum designed

current level in Burst Mode operation.

The inductance value is chosen ﬁrst based on a 30%

ripple current assumption. The highest value of ripple

current occurs at the maximum input voltage. Connect a

160k resistor between the FREQ/PLLFLTR and GND pins,

generating 250kHz operation. The minimum inductance

for 30% ripple current is:

⎛

⎞

⎟

⎠

V_OUT

V_IN

1

ΔI_L=

V_OUT1−

⎜

f L

( )( )

⎝

A 4.7μH inductor will produce 28% ripple current and

a 3.3μH will result in 40%. The peak inductor current

will be the maximum DC value plus one-half the ripple

current, or 6A, for the 3.3μH value. Increasing the ripple

Thedutycyclepercentageshouldbemaintainedfromcycle

tocycleinawelldesigned, lownoisePCBimplementation.

Variation in the duty cycle at a subharmonic rate can sug-

3851fb

23

LTC3851

APPLICATIONS INFORMATION

A short-circuit to ground will result in a folded back cur-

rent of:

current will also help ensure that the minimum on-time

of 90ns is not violated. The minimum on-time occurs at

maximum V :

IN

⎛

⎞

90ns 22V

29mV

0.0125Ω 2

1

(

)

I_SC=

–

= 2.02A

⎜

⎟

V_OUT

V_IN(MAX)

1.8V

3.3µH

⎝

⎠

t_ON(MIN)

=

= 327ns

f

( )

22V 250kHz

(

)

with a typical value of R

and δ = (0.005/°C)(25°C)

DS(ON)

The R

resistor value can be calculated by connect-

= 0.125. The resulting power dissipated in the bottom

SENSE

ing I to INTV and using the maximum current sense

MOSFET is:

LIM

CC

voltage speciﬁcation with some accommodation for toler-

ances. Tie I to INTV .

22V

=101.0mW

2

P_SYNC

=

2.02A 1.125 0.022Ω

(

) (

)(

)

LIM

CC

75mV

6A

R_SENSE

≤

= 0.0125Ω, so 0.01Ω is selected

which is less than under full-load conditions.

C is chosen for an RMS current rating of at least 3A at

Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields

an output voltage of 1.816V.

IN

temperature. C

is chosen with an ESR of 0.02ꢁ for

OUT

ThepowerdissipationonthetopsideMOSFETcanbeeasily

estimated. Choosing a Fairchild FDS6982S dual MOSFET

low output ripple. The output ripple in continuous mode

will be highest at the maximum input voltage. The output

voltage ripple due to ESR is approximately:

results in: R

= 0.035ꢁ/0.022ꢁ, C

= 215pF. At

DS(ON)

MILLER

maximum input voltage with T (estimated) = 50°C:

V

= R (ΔI ) = 0.02ꢁ (2A) = 40mV

ESR L P-P

ORIPPLE

1.8V

22V

2

⎡

⎤

P_MAIN

=

5

( )

1+ 0.005 50°C− 25°C •

(

)(

)

⎣

⎦

5A

2

⎛

⎞

2

0.035Ω + 22V

) (

2Ω 215pF •

)(

(

)

(

)

⎜

⎝

⎟

⎠

1

⎡

⎤

+

250kHz =185mW

(

)

⎢

⎣

⎥

⎦

5− 2.3 2.3

3851fb

24

LTC3851

TYPICAL APPLICATIONS

V

IN

4.5V TO 32V

MODE/PLLIN

V

IN

+

C

R

IN

FREQ

22μF

82.5k

M1

FREQ/PLLFLTR

TG

HAT2170H

L1

C

B

0.1μF

RUN

BOOST

C20

0.1μF

C

SS

LTC3851

0.1μF

0.68μH

V

3.3V

15A

OUT

TK/SS

SW

C

D

R

C2

B

R2

154k

1%

C

2200pF

R27

C15

47pF

330pF

CMDSH05-4

15k

3.01k

I

TH

INTV

CC

+

C

OUT

4.7μF

330μF

M2

HAT2170H

s2

R1

48.7k

1%

V

FB

BG

–

+

SENSE

GND

C5

0.047μF

30.1k

C

: SANYO 6TPE330MIL

OUT

IN

I

LIM

: SANYO 63HVH22M

L1: VISHAY IHLP5050-EZERR68MO1

3851 F11

Figure ±±. High Efﬁciency 3.3V/±5A Step-Down Converter

V

IN

6V TO 14V

PLLIN

350kHz

MODE/PLLIN

V

IN

C2

0.01μF

+

R5

10k

C

IN

180μF

M1

FREQ/PLLFLTR

TG

RJK0305DPB

C

B

0.1μF

RUN

BOOST

C

SS

0.1μF

L1

0.68μH

C1

1000pF

R

SENSE

0.002Ω

LTC3851

V

1.5V

15A

OUT

TK/SS

SW

C

1000pF

D

B

R

R2

43.2k

1%

C

C2

CMDSH-3

C10

33pF

7.5k

100pF

I

INTV

TH

CC

+

C

OUT

4.7μF

330μF

M2

RJK0301DPB

R1

20k

1%

s2

V

BG

FB

–

+

SENSE

GND

1000pF

I

C

: SANYO 2R5TPE330M9

LIM

OUT

L1: SUMIDA CEP125-OR6MC

R22 10Ω

R20 10Ω

3851 F12

Figure ±2. ±.5V/±5A Synchronized at 350kHz

3851fb

25

LTC3851

PACKAGE DESCRIPTION

GN Package

±6-Lead Plastic SSOP (Narrow .±50 Inch)

(Reference LTC DWG # 05-08-1641)

.189 – .196*

(4.801 – 4.978)

.045 p.005

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 p.0015

.0250 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 p .004

(0.38 p 0.10)

s 45o

.0532 – .0688

(1.35 – 1.75)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0o – 8o TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

GN16 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

3851fb

26

LTC3851

PACKAGE DESCRIPTION

MSE Package

±6-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1667 Rev A)

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.845 p 0.102

(.112 p .004)

2.845 p 0.102

(.112 p .004)

0.889 p 0.127

(.035 p .005)

1

8

0.35

REF

5.23

(.206)

MIN

1.651 p 0.102

(.065 p .004)

1.651 p 0.102

(.065 p .004)

3.20 – 3.45

(.126 – .136)

0.12 REF

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

DETAIL “B”

16

9

0.305 p 0.038

(.0120 p .0015)

TYP

0.50

(.0197)

BSC

NO MEASUREMENT PURPOSE

4.039 p 0.102

(.159 p .004)

(NOTE 3)

0.280 p 0.076

(.011 p .003)

RECOMMENDED SOLDER PAD LAYOUT

16151413121110

9

REF

DETAIL “A”

0o – 6o TYP

0.254

(.010)

3.00 p 0.102

(.118 p .004)

(NOTE 4)

4.90 p 0.152

(.193 p .006)

GAUGE PLANE

0.53 p 0.152

(.021 p .006)

1 2 3 4 5 6 7 8

DETAIL “A”

0.86

(.034)

REF

1.10

(.043)

MAX

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 p 0.0508

(.004 p .002)

MSOP (MSE16) 0608 REV A

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

UD Package

±6-Lead Plastic QFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1691)

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.20 TYP

OR 0.25 s 45o CHAMFER

R = 0.115

TYP

0.75 p 0.05

3.00 p 0.10

(4 SIDES)

15 16

0.70 p0.05

PIN 1

TOP MARK

(NOTE 6)

0.40 p 0.10

1

2

1.45 p 0.10

(4-SIDES)

3.50 p 0.05

2.10 p 0.05

1.45 p 0.05

(4 SIDES)

PACKAGE

OUTLINE

(UD16) QFN 0904

0.25 p 0.05

0.50 BSC

0.200 REF

0.25 p0.05

0.50 BSC

0.00 – 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3851fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LTC3851

TYPICAL APPLICATION

V

IN

4.5V TO 22V

MODE/PLLIN

V

IN

+

C

22μF

25V

IN

R

FREQ

160k

M1A

FREQ/PLLFLTR

TG

FDS6982S

L1

C

B

0.1μF

RUN

BOOST

0.1μF

C

SS

R

SENSE

LTC3851

0.1μF

3.3μH

V

1.8V

5A

0.01Ω

OUT

TK/SS

SW

C

D

C

B

R

C

470pF

C2

CMDSH-3

R2

32.4k

1%

33k

220pF

C

I

TH

INTV

OUT

CC

+

150μF

6.3V

s2

4.7μF

M1B

FDS6982S

R1

25.5k

1%

V

FB

BG

PANASONIC SP

–

+

SENSE

GND

1000pF

SENSE

I

LIM

C

: PANASONIC EEFUEOG151R

10Ω 10Ω

OUT

IN

: MARCON THCR70LE1H226ZT

L1: PANASONIC ETQP6F3R3HFA

: IRC LR 2010-01-R010F

R

SENSE

3851 F13

Figure ±3. ±.8V/5A Converter from Design Example with Pulse Skip Operation

RELATED PARTS

PART NUMBER

LTC3727A-1

LTC3728

DESCRIPTION

COMMENTS

Dual, 2-Phase Synchronous Controller

2-Phase 550kHz, Dual Synchronous Step-Down Controller

20A to 200A PolyPhase^®Synchronous Controllers

Very Low Dropout, V

≤ 14V

OUT

QFN and SSOP Packages

LTC3729/

LTC3729L-6

Expandable from 2-Phase to 12-Phase, Uses All Surface

Mount Components, No Heat Sink

LTC3731

LTC3810

LTC3811

3-Phase, 600kHz Synchronous Step-Down Controller

0.6V ≤ V

≤ 6V, 4.5V ≤ V ≤ 32V, I

≤ 60A, Integrated

OUT

IN

MOSFET Drivers

100V Current Mode Synchronous Nonisolated Switching

Regulator Controller

6.2V ≤ V ≤ 100V, 0.8V ≤ V

≤ 0.9V , No R

,

SENSE

IN

OUT

IN

Tracking and Synchronizable

Dual, PolyPhase Synchronous Step-Down Controller, 20A to 200A Differential Remote Sense Ampliﬁer, R

Sense

or DCR Current

SENSE

LTC3826/LTC3826-1 Low I Dual Synchronous Step-Down Controllers

4V ≤ V ≤ 36V, 0.8V ≤ V

≤ 10V, 30μA Quiescent Current

Q

IN

OUT

LTC3834/LTC3834-1 Low I Synchronous Step-Down Controllers

Single Channel LTC3826/LTC3826-1

4V ≤ V ≤ 60V, 1.23V ≤ V ≤ 36V, 120μA Quiescent Current

Q

LT^®3845

Low I Synchronous Step-Down Controller

Q

IN

OUT

LTC3850/LTC3850-1/ Dual, 2-Phase Synchronous Step-Down Controller

LTC3850-2

R

SENSE

or DCR Current Sensing, Tracking and Synchronizable

LTC3853

LTC3878

Triple Output, Multiphase Synchronous Step-Down Controller

R

or DCR Current Sensing, Tracking and Synchronizable

SENSE

No R

Wide Input Range Constant On-Time Synchronous

Up to 97% Efﬁciency, 4V ≤ V ≤ 38V,

IN

0.8V ≤ V

SENSE

Step-Down Controller

≤ (0.9)(V ), I

Up to 20A

OUT

IN OUT

LTM4600HV

10A Complete Switch Mode Power Supply

92% Efﬁciency, V : 4.5V to 28V, True Current Mode Control,

IN

Ultrafast™ Transient Response

LTM4601AHV

12A Complete Switch Mode Power Supply

92% Efﬁciency, V : 4.5V to 28V, True Current Mode Control,

IN

Ultrafast Transient Response

PolyPhase is a registered trademark of Linear Technology Corporation. No R

and Ultrafast are trademarks of Linear Technology Corporation.

SENSE

3851fb

LT 0409 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3851EGN#PBF
厂家：	Linear
描述：	LTC3851 - Synchronous Step-Down Switching Regulator Controller; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 开关光电二极管
文件：	总28页 (文件大小：327K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3851EGN#PBF [Linear]

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