LTC3851EMSE-1-PBF_技术文档

LTC3851-1

Synchronous

Step-Down Switching

Regulator Controller

FEATURES

DESCRIPTION

The LTC^®3851-1 is a high performance synchronous

step-down switching regulator controller that drives

an all N-channel synchronous power MOSFET stage. A

constant frequency current mode architecture allows a

phase-lockable frequency of up to 750kHz.

n

Wide V Range: 4V to 38V Operation

SENSE

±±1 Output Voltage Accuracy

IN

n

R

or DCR Current Sensing

n

Power Good Output Voltage Monitor

Phase-Lockable Fixed Frequency: 250kHz to 750kHz

Dual N-Channel MOSFET Synchronous Drive

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Output Voltage Soft-Start or Tracking

Output Current Foldback Limiting

OPTI-LOOP compensation allows the transient response

to be optimized over a wide range of output capacitance

and ESR values. The LTC3851-1 features a precision 0.8V

referenceandapowergoodindicator.Awide4Vto38V(40V

absolutemaximum)inputsupplyrangeencompassesmost

battery conﬁgurations and intermediate bus voltages.

Output Overvoltage Protection

OPTI-LOOP^®Compensation Minimizes C

OUT

Selectable Continuous, Pulse-Skipping or

Burst Mode^®Operation at Light Loads

The TK/SS pin ramps the output voltage during start-up

and shutdown with coincident or ratiometric tracking.

Current foldback limits MOSFET heat dissipation during

short-circuit conditions. The MODE/PLLIN pin selects

among Burst Mode operation, pulse skipping mode or

continuousinductorcurrentmodeatlightloadsandallows

the IC to be synchronized to an external clock.

n

Low Shutdown I : 20μA

Q

V

Range: 0.8V to 5.5V

OUT

Thermally Enhanced 16-Lead MSOP

or 3mm × 3mm QFN Package

APPLICATIONS

n

Automotive Systems

The LTC3851-1 is identical to the LTC3851 except that the

n

Telecom Systems

I

pin is replaced by PGOOD.

LIM

n

Industrial Equipment

Distributed DC Power Systems

L, LT, LTC, LTM, Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology

Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6304066,

6498466, 6580258, 6611131.

n

TYPICAL APPLICATION

High Efﬁciency Synchronous Step-Down Converter

Efﬁciency and Power Loss

vs Load Current

100k

V

IN

PGO0D

FREQ/PLLFLTR TG

INTV

V

CC

IN

4.5V TO 38V

100

95

10000

1000

100

22μF

V

= 12V

IN

OUT

0.68μH

3.01k

V

3.3V

15A

330μF

s2

= 3.3V

OUT

0.1μF

82.5k

RUN

LTC3851-1

SW

EFFICIENCY

90

0.1μF

TK/SS

BOOST

85

0.1μF

80

75

POWER LOSS

INTV

CC

2200pF

4.7μF

BG

I

70

65

60

55

50

TH

GND

15k

330pF

+

SENSE

PLLIN/MODE

SENSE

0.047μF

30.1k

–

154k

10

V

FB

10

100

1000

10000

100000

LOAD CURRENT (mA)

48.7k

38511TA01b

38511 TA01a

38511f

1

LTC3851-1

ABSOLUTE MAXIMUM RATINGS ^{(Note ±)}

Input Supply Voltage (V )......................... 40V to –0.3V

I , V Voltages.......................................... 3V to –0.3V

IN

TH FB

Topside Driver Voltage (BOOST) ................ 46V to –0.3V

INTV Peak Output Current ..................................50mA

CC

Switch Voltage (SW)..................................... 40V to –5V

Operating Junction Temperature Range

INTV , (BOOST – SW), RUN, PGOOD ........ 6V to –0.3V

(Notes 2, 3)............................................ –40°C to 125°C

Storage Temperature Range................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

CC

TK/SS.................................................... INTV to –0.3V

CC

+

–

SENSE , SENSE .......................................... 6V to –0.3V

MODE/PLLIN, FREQ/PLLFLTR............... INTV to –0.3V

MSE.................................................................. 300°C

CC

PIN CONFIGURATION

TOP VIEW

1

2

3

4

5

6

7

8

MODE/PLLIN

FREQ/PLLFLTR

RUN

16 SW

16 15 14 13

15 TG

14 BOOST

RUN

1

2

3

4

12 BOOST

TK/SS

13 V

IN

17

TK/SS

11

10

9

V

IN

I

12 INTV

11 BG

TH

CC

17

FB

I

INTV

BG

–

TH

CC

SENSE

10 GND

+

SENSE

9

PGOOD

FB

5

6

7

8

MSE PACKAGE

16-LEAD PLASTIC MSOP

T

= 125°C, θ = 35°C/W TO 40°C/W

JA

JMAX

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

UD PACKAGE

16-LEAD (3mm s 3mm) PLASTIC QFN

T

= 125°C, θ = 68°C/W, θ = 4.2°C/W

JA JC

JMAX

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC3851EMSE-1#PBF

LTC3851IMSE-1#PBF

LTC3851EUD-1#PBF

LTC3851IUD-1#PBF

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3851EMSE-1#TRPBF 38511

16-Lead Plastic MSOP

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

LTC3851IMSE-1#TRPBF

LTC3851EUD-1#TRPBF

LTC3851IUD-1#TRPBF

38511

LDNT

16-Lead Plastic MSOP

16-Lead (3mm × 3mm) Plastic QFN

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

38511f

2

LTC3851-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

junction temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= ±5V, V_RUN= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loops

V

Input Operating Voltage Range

Regulated Feedback Voltage

Feedback Current

4

38

0.808

–50

V

IN

l

I

= 1.2V (Note 4)

0.792

0.800

–10

FB

TH

I

(Note 4)

= 6V to 38V (Note 4)

nA

FB

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

0.002

0.02

%/V

REFLNREG

LOADREG

IN

(Note 4)

l

Measured in Servo Loop,

0.01

0.1

%

ΔI = 1.2V to 0.7V

TH

(Note 4)

Measured in Servo Loop,

–0.01

–0.1

ΔI = 1.2V to 1.6V

TH

g

Transconductance Ampliﬁer g

I

TH

I

TH

= 1.2V, Sink/Source = 5μA (Note 4)

= 1.2V

2

3

mmho

MHz

m

GBW

Transconductance Amp Gain Bandwidth

m

I

Input DC Supply Current

Normal Mode

Shutdown

(Note 5)

OUT

RUN

Q

V

= 5V

= 0V

1

20

mA

μA

35

UVLO

Undervoltage Lockout on INTV

UVLO Hysteresis

V

Ramping Down

INTVCC

3.25

0.4

0.88

1

V

CC

UVLO Hys

l

V

Feedback Overvoltage Lockout

SENSE Pins Total Current

Soft-Start Charge Current

RUN Pin On Threshold

Measured at V

0.86

0.90

2

V

OVL

FB

I

μA

V

SENSE

TK/SS

V

TK/SS

= 0V

0.6

1

2

l

V

Rising

RUN

1.10

1.22

130

50

1.35

RUN

RUN Pin On Hysteresis

mV

Ω

RUNHYS

SENSE(MAX)

Maximum Current Sense Threshold

TG Driver Pull-Up On-Resistance

TG Driver Pull-Down On-Resistance

BG Driver Pull-Up On-Resistance

BG Driver Pull-Down On-Resistance

V

= 0.7V, V

= 3.3V

40

65

FB

SENSE

TG R

BG R

TG High

TG Low

BG High

BG Low

(Note 6)

2.6

1.5

2.4

1.1

UP

Ω

DOWN

UP

Ω

DOWN

TG Transition Time

Rise Time

Fall Time

TG t

C

= 3300pF

25

ns

r

f

LOAD

BG Transition Time

Rise Time

Fall Time

(Note 6)

LOAD

BG tr

BG tf

C

= 3300pF

25

ns

TG/BG t

Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

C

= 3300pF Each Driver

30

90

ns

1D

2D

LOAD

BG/TG t

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

C

LOAD

= 3300pF Each Driver

t

Minimum On-Time

(Note 7)

ON(MIN)

INTV Linear Regulator

CC

V

Internal V Voltage

6V < V < 38V

4.8

5

5.2

V

INTVCC

CC

IN

INT

INTV Load Regulation

I = 0mA to 50mA

CC

0.5

%

LDO

CC

38511f

3

LTC3851-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

junction temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= ±5V, V_RUN= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Oscillator and Phase-Locked Loop

f

Nominal Frequency

R

= 60k

= 160k

= 36k

480

220

710

500

250

750

100

530

280

790

kHz

kΩ

NOM

LOW

HIGH

FREQ

Lowest Frequency

Highest Frequency

R

MODE/PLLIN Input Resistance

MODE/PLLIN

FREQ

I

Phase Detector Output Current

Sinking Capability

Sourcing Capability

f

> f

< f

–10

10

μA

MODE

OSC

PGOOD Output

V

PGOOD Voltage Low

PGOOD Leakage Current

PGOOD Trip Level

I

= 2mA

= 5V

0.1

0.3

1

V

PGL

PGOOD

I

V

μA

PGOOD

V

with Respect to Set Regulated Voltage

Ramping Negative

Ramping Positive

PG

FB

V

FB

V

FB

–12

8

–10

10

–8

12

%

Note ±: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: The LTC3851-1 is tested in a feedback loop that servos V to a

ITH

speciﬁed voltage and measures the resultant V

.

FB

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 2: The LTC3851E-1 is guaranteed to meet performance speciﬁcations

from 0°C to 85°C. Speciﬁcations over the –40°C to 85°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls. The LTC3851I-1 is guaranteed

over the –40°C to 125°C operating junction temperature range.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 7: The minimum on-time condition is speciﬁed for an inductor

peak-to-peak ripple current ~40% of I

(see Minimum On-Time

MAX

Considerations in the Applications Information section).

Note 3: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formulas:

D

LTC3851MSE-1: T = T + (P • 90°C/W)

J

A

D

LTC3851UD-1: T = T + (P • 68°C/W)

J

A

D

TYPICAL PERFORMANCE CHARACTERISTICS

Efﬁciency vs Output Current and

Mode

Efﬁciency vs Output Current

and Mode

Efﬁciency vs Output Current and

Mode

100

90

100

90

100

90

V

= 12V

IN

OUT

= 1.5V

BURST

80

BURST

70

PULSE

SKIP

PULSE

SKIP

60

50

60

50

60

50

PULSE

SKIP

CCM

40

30

20

10

0

40

30

20

10

0

40

30

20

10

0

CCM

V

= 12V

IN

OUT

V

= 12V

OUT

= 3.3V

IN

= 5V

FIGURE 11 CIRCUIT

10000 100000

LOAD CURRENT (mA)

10

100

1000

10000

100000

10

100

1000

10000

100000

10

100

1000

LOAD CURRENT (mA)

38511 G03

38511 G01

38511 G02

38511f

4

LTC3851-1

TYPICAL PERFORMANCE CHARACTERISTICS

Load Step

(Burst Mode Operation)

Load Step

(Forced Continuous Mode)

Efﬁciency and Power Loss vs

Input Voltage

100

95

10000

1000

100

I

LOAD

EFFICIENCY,

OUT

5A/DIV

I

= 5A

POWER LOSS,

= 5A

0.2A TO 7.5A

I

OUT

I

L

I

L

5A/DIV

90

5A/DIV

85

80

V

OUT

EFFICIENCY,

= 0.5A

V

OUT

100mV/DIV

I

OUT

100mV/DIV

AC COUPLED

POWER LOSS,

I

= 0.5A

OUT

38511 G05

38511 G06

V

= 1.5V

100μs/DIV

V

= 1.5V

OUT

100μs/DIV

OUT

IN

V

= 12V

75

70

IN

OUT

= 12V

IN

= 3.3V

FIGURE 11 CIRCUIT

4

8

12

16

20 28

24 32

INPUT VOLTAGE (V)

38511 G04

Load Step

(Pulse skip Mode)

Start-Up with Prebiased Output

at 2V

Inductor Current at Light Load

I

LOAD

FORCED

CONTINOUS

MODE

5A/DIV

V

OUT

0.2A TO 7.5A

2V/DIV

5A/DIV

TK/SS

0.5V/DIV

I

L

Burst Mode

OPERATION

5A/DIV

V

FB

V

OUT

0.5V/DIV

PULSE SKIP

MODE

100mV/DIV

AC COUPLED

5A/DIV

38511 G08

3851 G07

38511 G09

V

I

= 1.5V

= 1mA

1μs/DIV

V

= 1.5V

100μs/DIV

20ms/DIV

OUT

IN

LOAD

OUT

IN

= 12V

FIGURE 11 CIRCUIT

Coincident Tracking with Master

Supply

Ratiometric Tracking with Master

Supply

Input DC Supply Current vs Input

Voltage

3.0

2.5

2.0

1.5

1.0

0.5

0

V

MASTER

0.5V/DIV

V

MASTER

V

OUT

0.5V/DIV

2A LOAD

0.5V/DIV

V

OUT

2A LOAD

0.5V/DIV

38511 G10

38511 G11

10ms/DIV

4

8

12 16 20 24 28 32 36 40

INPUT VOLTAGE (V)

38511 G12

38511f

5

LTC3851-1

TYPICAL PERFORMANCE CHARACTERISTICS

Maximum Current Sense

Threshold vs Common Mode

Maximum Peak Current Sense

Threshold vs I_THVoltage

INTV_CCLine Regulation

Voltage

90

80

70

60

50

40

30

20

10

0

5.3

5.1

4.9

4.7

4.5

4.3

4.1

3.9

3.7

90

80

70

60

50

40

30

20

10

0

DUTY CYCLE RANGE: 0% TO 100%

I

= 0mA

LOAD

I

= 25mA

LOAD

–10

–20

3.5

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

(V)

4

8

12 16 20 24

INPUT VOLTAGE (V)

40

28 32 36

0

0.5

1

1.5

2

2.5

5

3

3.5 4 4.5

V

ITH

V

COMMON MODE VOLTAGE (V)

SENSE

38511 G15

38511 G13

38511 G14

Maximum Current Sense

Threshold vs Feedback Voltage

(Current Foldback)

Burst Mode Peak Current Sense

Threshold vs I_THVoltage

Maximum Current Sense

Threshold vs Duty Cycle

90

80

70

60

50

40

30

20

10

0

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

MAXIMUIM

MINIMUIM

BURST COMPARATOR FALLING THESHOLD:

V

= 0.4V

ITH

0

0.4 0.5

FEEDBACK VOLTAGE (V)

0

0.1 0.2 0.3

0.6 0.7 0.8

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

(V)

0

80

100

20

40

60

V

DUTY CYCLE (%)

ITH

38511 G18

38511 G16

38511 G17

TK/SS Pull-Up Current vs

Temperature

Shutdown (RUN) Threshold vs

Temperature

Regulated Feedback Voltage vs

Temperature

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

1.4

1.3

1.2

1.1

1.0

0.9

806

804

802

800

RUN RISING THRESHOLD (ON)

RUN FALLING THRESHOLD (OFF)

798

796

794

–50

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

–25

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

TEMPERATURE (°C)

38511 G19

38511 G20

38511 G21

38511f

6

LTC3851-1

TYPICAL PERFORMANCE CHARACTERISTICS

Oscillator Frequency vs

Temperature

Oscillator Frequency vs Input

Voltage

Undervoltage Lockout Threshold

(INTV_CC) vs Temperature

900

800

5

4

3

2

1

0

420

R

= 80k

FREQ

415

410

R

= 36k

= 60k

FREQ

INTV RAMPING UP

CC

700

600

500

400

300

405

400

395

390

385

INTV RAMPING DOWN

CC

R

= 150k

50

FREQ

25

200

380

100 125

–50 –25

0

75

–50 –25

0

25

50

75 100 125

10

15

25

30

35

40

5

20

TEMPERATURE (°C)

INPUT VOLTAGE (V)

38511 G22

38511 G24

38511 G23

Shutdown Input DC Supply

Current vs Input Voltage

Shutdown Input DC Supply

Current vs Temperature

40

35

30

25

20

15

10

5

35

30

25

20

15

10

5

0

–25

0

50

75 100 125

20 25

10 15

INPUT VOLTAGE (V)

–50

25

0

5

30 35 40

TEMPERATURE (°C)

38511 G26

38511 G25

Input DC Supply Current vs

Temperature

Maximum Current Sense

Threshold vs INTV_CCVoltage

3.0

2.5

2.0

1.5

90

80

70

60

50

40

30

20

10

1.0

0.5

0

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

3.2 3.4 3.6 3.8 4.0 4.2

5.0

4.4 4.6 4.8

INTV VOLTAGE(V)

CC

38511 G27

38511 G28

38511f

7

LTC3851-1

PIN FUNCTIONS ^(MSE/UD)

MODE/PLLIN (Pin ±/Pin ±5): Force Continuous Mode,

Burst Mode or Pulse skipping Mode Selection Pin and

External Synchronization Input to Phase Detector Pin.

PGOOD(Pin9/Pin7):PowerGoodIndicatorOutput.Open-

drain logic out that is pulled to ground when the output

voltage exceeds the 10% regulation window, after the

internal 17μs power bad mask timer expires.

ConnectthispintoINTV toforcecontinuousconduction

CC

mode of operation. Connect to GND to enable pulse skip-

GND(Pin±0/Pin8):Ground. Allsmall-signalcomponents

ping mode of operation. To select Burst Mode operation,

andcompensationcomponentsshouldbeKelvinconnected

tie this pin to INTV through a resistor no less than 50k,

CC

tothisground.The(–)terminalofCV andthe(–)terminal

CC

but no greater than 250k. A clock on the pin will force the

controller into forced continuous mode of operation and

synchronize the internal oscillator.

of C should be closely connected to this pin.

IN

BG (Pin ±±/Pin 9): Bottom Gate Driver Output. This pin

drives the gate of the bottom N-channel MOSFET between

FREQ/PLLFLTR (Pin 2/Pin ±6): The phase-locked loop’s

lowpass ﬁlter is tied to this pin. Alternatively, a resistor

can be connected between this pin and GND to vary the

frequency of the internal oscillator.

GND and INTV .

CC

INTV (Pin±2/Pin±0):Internal5VRegulatorOutput. The

CC

control circuit is powered from this voltage. Decouple this

pin to GND with a minimum 2.2ꢀF low ESR tantalum or

ceramic capacitor.

RUN (Pin 3/Pin ±): Run Control Input. A voltage above

1.25V on this pin turns on the IC. However, forcing this

pin below 1.1V causes the IC to shut down the IC. There

is a 2ꢀA pull-up current on this pin.

V (Pin ±3/Pin ±±): Main Input Supply. Decouple this pin

IN

to GND with a capacitor.

BOOST (Pin ±4/Pin ±2): Boosted Floating Driver Supply.

The (+) terminal of the boost-strap capacitor is connected

to this pin. This pin swings from a diode voltage drop

below INTV up to V + INTV .

TK/SS(Pin4/Pin2):OutputVoltageTrackingandSoft-Start

Input. A capacitor to ground at this pin sets the ramp rate

for the output voltage. An internal soft-start current of of

1ꢀA charges this capacitor.

CC

IN

CC

TG (Pin ±5/Pin ±3): Top Gate Driver Output. This is the

I

(Pin 5/Pin 3): Current Control Threshold and Error

TH

output of a ﬂoating driver with a voltage swing equal to

Ampliﬁer Compensation Point. The current comparator

INTV superimposed on the switch node voltage.

tripping threshold increases with its I control voltage.

CC

TH

SW (Pin ±6/Pin ±4): Switch Node Connection to the In-

FB (Pin 6/Pin 4): Error Ampliﬁer Feedback Input. This pin

receives the remotely sensed feedback voltage from an

external resistive divider across the output.

ductor. Voltage swing at this pin is from a Schottky diode

(external) voltage drop below ground to V .

IN

–

Exposed Pad (Pin ±7): Ground. Must be soldered to PCB,

providing a local ground for the IC.

SENSE (Pin7/Pin5):CurrentSenseComparatorInverting

Input.The(–)inputtothecurrentcomparatorisconnected

to the output.

+

SENSE (Pin 8/Pin 6): Current Sense Comparator Non-

inverting Input. The (+) input to the current comparator

is normally connected to the DCR sensing network or

current sensing resistor.

38511f

8

LTC3851-1

FUNCTIONAL DIAGRAM

V

IN

FREQ/PLLFLTR

MODE/PLLIN

V

IN

+

C

IN

100k

5V REG

0.8V

MODE/SYNC

DETECT

PLL-SYNC

–

+

BOOST

BURSTEN

C

B

TG

OSC

S

R

PULSE SKIP

ON

M1

Q

I

SW

SWITCH

LOGIC

AND

ANTI-

SHOOT

THROUGH

5k

+

SENSE

D

+

–

+

B

L1

I

V

OUT

CMP

REV

–

RUN

OV

+

INTV

BG

CC

C

OUT

M2

C

VCC

SLOPE COMPENSATION

GND

PGOOD

INTV

CC

UVLO

1

+

–

0.72V

100k

R2

UV

OV

I

V

THB

FB

R1

+

–

V

SLEEP

IN

0.88V

RUN

SS

–

+

0.8V

REF

1μA

EA

+ –

–

+

0.64V

1.25V

2μA

0.4V

38511 FD

I

TH

RUN

TK/SS

C

R

C

SS

C

C1

38511f

9

LTC3851-1

OPERATION

Main Control Loop

by logic. Be careful not to exceed the absolute maximum

rating of 6V on this pin.

The LTC3851-1 is a constant frequency, current mode

step-down controller. During normal operation, the top

MOSFET is turned on when the clock sets the RS latch,

The start-up of the controller’s output voltage, V , is

OUT

controlled by the voltage on the TK/SS pin. When the

and is turned off when the main current comparator, I

,

voltage on the TK/SS pin is less than the 0.8V internal

CMP

resets the RS latch. The peak inductor current at which

resets the RS latch is controlled by the voltage on

reference, the LTC3851-1 regulates the V voltage to

FB

I

the TK/SS pin voltage instead of the 0.8V reference. This

allows the TK/SS pin to be used to program a soft-start

by connecting an external capacitor from the TK/SS pin to

GND.Aninternal1μApull-upcurrentchargesthiscapacitor

creating a voltage ramp on the TK/SS pin. As the TK/SS

voltage rises linearly from 0V to 0.8V (and beyond), the

CMP

the I pin, which is the output of the error ampliﬁer EA.

TH

The V pin receives the voltage feedback signal, which is

FB

comparedtotheinternalreferencevoltagebytheEA.When

the load current increases, it causes a slight decrease in

V relative to the 0.8V reference, which in turn causes the

FB

TH

I

voltage to increase until the average inductor current

output voltage V

rises smoothly from zero to its ﬁnal

OUT

matches the new load current. After the top MOSFET has

turned off, the bottom MOSFET is turned on until either

the inductor current starts to reverse, as indicated by the

value. Alternatively, the TK/SS pin can be used to cause

the start-up of V to “track” another supply. Typically,

OUT

this requires connecting to the TK/SS pin an external

resistor divider from the other supply to ground (see the

Applications Information section). When the RUN pin

reverse current comparator, I , or the beginning of the

REV

next cycle.

is pulled low to disable the controller, or when INTV

CC

INTV Power

drops below its undervoltage lockout threshold of 3.2V,

the TK/SS pin is pulled low by an internal MOSFET. When

in undervoltage lockout, the controller is disabled and the

external MOSFETs are held off.

CC

Power for the top and bottom MOSFET drivers and most

other internal circuitry is derived from the INTV pin. An

CC

internal 5V low dropout linear regulator supplies INTV

CC

power from V .

IN

Light Load Current Operation (Burst Mode Operation,

Pulse skipping or Continuous Conduction)

The top MOSFET driver is biased from the ﬂoating boot-

strap capacitor, C , which normally recharges during each

B

The LTC3851-1 can be enabled to enter high efﬁciency

Burst Mode operation, constant frequency pulse skipping

mode or forced continuous conduction mode. To select

forced continuous operation, tie the MODE/PLLIN pin to

off cycle through an external diode when the top MOSFET

turns off. If the input voltage, V , decreases to a voltage

IN

close to V , the loop may enter dropout and attempt

OUT

to turn on the top MOSFET continuously. The dropout

detector detects this and forces the top MOSFET off for

about 1/10 of the clock period every tenth cycle to allow

INTV . To select pulse skipping mode of operation, ﬂoat

CC

the MODE/PLLIN pin or tie it to GND. To select Burst Mode

operation, tie MODE/PLLIN to INTV through a resistor

CC

C to recharge. However, it is recommended that there is

B

no less than 50k, but no greater than 250k.

always a load present during the drop-out transition to

ensure C is recharged.

When the controller is enabled for Burst Mode operation,

the peak current in the inductor is set to approximately

one-forth of the maximum sense voltage even though

B

Shutdown and Start-Up (RUN and TK/SS)

the voltage on the I pin indicates a lower value. If the

TH

The LTC3851-1 can be shut down using the RUN pin. Pull-

ing this pin below 1.1V disables the controller and most

average inductor current is higher than the load current,

the error ampliﬁer, EA, will decrease the voltage on the I

TH

of the internal circuitry, including the INTV regulator.

CC

pin. When the I voltage drops below 0.4V, the internal

TH

Releasing the RUN pin allows an internal 2μA current to

pull up the pin and enable that controller. Alternatively,

the RUN pin may be externally pulled up or driven directly

sleep signal goes high (enabling “sleep” mode) and both

external MOSFETs are turned off.

38511f

10

LTC3851-1

OPERATION

pin. If the MODE/PLLIN pin is not being driven by an ex-

ternal clock source, the FREQ/PLLFLTR pin can be used

to program the controller’s operating frequency from

250kHz to 750kHz.

In sleep mode, the load current is supplied by the output

capacitor. As the output voltage decreases, the EA’s output

begins to rise. When the output voltage drops enough, the

sleep signal goes low, and the controller resumes normal

operation by turning on the top external MOSFET on the

next cycle of the internal oscillator. When a controller is

enabled for Burst Mode operation, the inductor current is

not allowed to reverse. The reverse current comparator,

A phase-locked loop (PLL) is available on the LTC3851-1

to synchronize the internal oscillator to an external clock

source that is connected to the MODE/PLLIN pin. The

controlleroperatesinforcedcontinuousmodeofoperation

when it is synchronized. A series RC should be connected

between the FREQ/PLLFLTR pin and GND to serve as the

PLL’s loop ﬁlter.

I

, turnsoffthebottomexternalMOSFETjustbeforethe

REV

inductor current reaches zero, preventing it from revers-

ing and going negative. Thus, the controller operates in

discontinuous operation. In forced continuous operation,

the inductor current is allowed to reverse at light loads or

under large transient conditions. The peak inductor cur-

It is suggested that the external clock be applied before

enabling the controller unless a second resistor is con-

nected in parallel with the series RC loop ﬁlter network.

The second resistor prevents low switching frequency

operation if the controller is enabled before the clock.

rent is determined by the voltage on the I pin, just as in

TH

normal operation. In this mode the efﬁciency at light loads

is lower than in Burst Mode operation. However, continu-

ous mode has the advantages of lower output ripple and

less interference to audio circuitry.

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transient

overshoots (>10%) as well as other more serious con-

ditions that may overvoltage the output. In such cases,

the top MOSFET is turned off and the bottom MOSFET is

turned on until the overvoltage condition is cleared.

When the MODE/PLLIN pin is connected to GND, the

LTC3851-1 operates in PWM pulse skipping mode at

light loads. At very light loads the current comparator,

I

, may remain tripped for several cycles and force the

CMP

external top MOSFET to stay off for the same number of

cycles (i.e., skipping pulses). The inductor current is not

allowed to reverse (discontinuous operation). This mode,

likeforcedcontinuousoperation,exhibitslowoutputripple

as well as low audio noise and reduced RF interference

as compared to Burst Mode operation. It provides higher

low current efﬁciency than forced continuous mode, but

not nearly as high as Burst Mode operation.

Power Good (PGOOD) Pin

ThePGOODpinisconnectedtoanopendrainofaninternal

N-channel MOSFET. The MOSFET turns on and pulls the

pin voltage is not within

PGOOD pin low when the V

FB

10% of the 0.8V reference voltage. The PGOOD pin is

also pulled low when the RUN pin is low (shut down) or

when the LTC3851-1 is in the soft-start or tracking phase.

Frequency Selection and Phase-Locked Loop

(FREQ/PLLFLTR and MODE/PLLIN Pins)

When the V pin voltage is within the 10% requirement,

FB

the MOSFET is turned off and the pin is allowed to be

pulled up by an external resistor to a source of up to 6V.

The PGOOD pin will ﬂag power good immediately when

Theselectionofswitchingfrequencyisatrade-offbetween

efﬁciency and component size. Low frequency operation

increasesefﬁciencybyreducingMOSFETswitchinglosses,

butrequireslargerinductanceand/orcapacitancetomain-

tain low output ripple voltage. The switching frequency of

the LTC3851-1 can be selected using the FREQ/PLLFLTR

the V pin is within the 10% window. However, there is

FB

an internal 17μs power bad mask when V goes out of

FB

the 10% window.

38511f

11

LTC3851-1

APPLICATIONS INFORMATION

The Typical Application on the ﬁrst page of this data sheet

is a basic LTC3851-1 application circuit. The LTC3851-1

can be conﬁgured to use either DCR (inductor resistance)

sensing or low value resistor sensing. The choice of the

two current sensing schemes is largely a design trade-off

between cost, power consumption and accuracy. DCR

sensing is becoming popular because it saves expensive

current sensing resistors and is more power efﬁcient,

especially in high current applications. However, current

sensing resistors provide the most accurate current limits

for the controller. Other external component selection

is driven by the load requirement, and begins with the

V

IN

INTV

CC

BOOST

TG

R

SENSE

V

SW

OUT

LTC3851-1

BG

GND

+

SENSE

–

SENSE

38511 F01

FILTER COMPONENTS

PLACED NEAR SENSE PINS

selection of R

(if R

is used) and the inductor

SENSE

value. Next, the power MOSFETs and Schottky diodes are

selected. Finally, input and output capacitors are selected.

The circuit shown on the ﬁrst page can be conﬁgured for

Figure ±. Using a Resistor to Sense Current with the LTC385±-±

of 20% for variations in the IC and external component

values yields:

operation up to 40V at V .

IN

+

–

SENSE and SENSE Pins

V_MAX

R_SENSE= 0.8 •

+

–

I_MAX+ ΔI_L/2

The SENSE and SENSE pins are the inputs to the current

comparators. The common mode input voltage range of

the current comparators is 0V to 5.5V. Both SENSE pins

are high impedance inputs with small base currents of

less than 1ꢀA. When the SENSE pins ramp up from 0V to

1.4V, the small base currents ﬂow out of the SENSE pins.

When the SENSE pins ramp down from 5V to 1.1V, the

small base currents ﬂow into the SENSE pins. The high

impedance inputs to the current comparators allow ac-

curate DCR sensing. However, care must be taken not to

ﬂoat these pins during normal operation.

Inductor DCR Sensing

Forapplicationsrequiringthehighestpossibleefﬁciency,

the LTC3851-1 is capable of sensing the voltage drop

across the inductor DCR, as shown in Figure 2. The

DCR of the inductor represents the small amount of

DC winding resistance of the copper, which can be less

than 1mΩ for today’s low value, high current inductors.

If the external R1||R2 • C1 time constant is chosen to

be exactly equal to the L/DCR time constant, the voltage

drop across the external capacitor is equal to the voltage

dropacrosstheinductorDCRmultipliedbyR2/(R1+R2).

Therefore,R2maybeusedtoscalethevoltageacrossthe

sense terminals when the DCR is greater than the target

sense resistance. Check the manufacturer’s data sheet

for speciﬁcations regarding the inductor DCR, in order

to properly dimension the external ﬁlter components.

The DCR of the inductor can also be measured using a

good RLC meter.

Low Value Resistors Current Sensing

A typical sensing circuit using a discrete resistor is shown

in Figure 1. R

current.

is chosen based on the required output

SENSE

The current comparator has a maximum threshold, V

MAX

= 50mV. The current comparator threshold sets the maxi-

mum peak of the inductor current, yielding a maximum

average output current, I

, equal to the peak value less

MAX

halfthepeak-to-peakripplecurrent,ΔI .Allowingamargin

L

38511f

12

LTC3851-1

APPLICATIONS INFORMATION

Accepting larger values of ΔI allows the use of low

L

V

IN

inductances, but results in higher output voltage ripple

INTV

CC

and greater core losses. A reasonable starting point for

BOOST

TG

setting ripple current is ΔI = 0.3(I

). The maximum

MAX

L

INDUCTOR

ΔI occurs at the maximum input voltage.

L

DCR

SW

V

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

OUT

LTC3851-1

BG

GND

R1

R2

+

≈10% of the current limit determined by R

. Lower

SENSE

C1*

inductor values (higher ΔI ) will cause this to occur at

L

–

SENSE

lower load currents, which can cause a dip in efﬁciency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to increase.

L

DCR

+

–

38511 F02

R1||R2 • C1 =

*PLACE C1 NEAR SENSE , SENSE PINS

R2

R1 + R2

R

= DCR

SENSE(EQ)

Figure 2. Current Mode Control Using the Inductor DCR

Inductor Core Selection

Slope Compensation and Inductor Peak Current

Once the value for L is known, the type of inductor must

be selected. High efﬁciency converters generally cannot

affordthecorelossfoundinlowcostpowderedironcores,

forcingtheuseofmoreexpensiveferriteormolypermalloy

cores. Actual core loss is independent of core size for a

ﬁxedinductorvalue,butitisverydependentoninductance

selected. As inductance increases, core losses go down.

Unfortunately, increased inductance requires more turns

of wire and therefore copper losses will increase.

Slope compensation provides stability in constant fre-

quency architectures by preventing sub-harmonic oscil-

lations at high duty cycles. It is accomplished internally

by adding a compensating ramp to the inductor current

signal. Normally, this results in a reduction of maximum

inductor peak current for duty cycles >40%. However, the

LTC3851-1 uses a novel scheme that allows the maximum

inductor peak current to remain unaffected throughout all

duty cycles.

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

Inductor Value Calculation

The operating frequency and inductor selection are inter-

relatedinthathigheroperatingfrequenciesallowtheuseof

smaller inductor and capacitor values. A higher frequency

generally results in lower efﬁciency because of MOSFET

gate charge losses. In addition to this basic trade-off, the

effect of inductor value on ripple current and low current

operation must also be considered.

Power MOSFET and Schottky Diode (Optional)

Selection

The inductor value has a direct effect on ripple current.

Two external power MOSFETs must be selected for the

LTC3851-1 controller: one N-channel MOSFET for the top

(main) switch, and one N-channel MOSFET for the bottom

(synchronous) switch.

The inductor ripple current ΔI decreases with higher

L

inductance or frequency and increases with higher V :

IN

⎛

⎞

V_OUT

1

f •L

ΔI_L=

V_OUT1–

⎜

⎝

⎟

V

⎠

IN

38511f

13

LTC3851-1

APPLICATIONS INFORMATION

2

BothMOSFETshaveI RlosseswhilethetopsideN-channel

Thepeak-to-peakdrivelevelsaresetbytheINTV voltage.

CC

equation includes an additional term for transition losses,

This voltage is typically 5V during start-up. Consequently,

logic-level threshold MOSFETs must be used in most ap-

plications. The only exception is if low input voltage is ex-

which are highest at high input voltages. For V < 20V,

IN

the high current efﬁciency generally improves with larger

MOSFETs, while for V > 20V, the transition losses rapidly

pected(V <5V);then,sub-logiclevelthresholdMOSFETs

IN

increasetothepointthattheuseofahigherR

device

(V

< 3V) should be used. Pay close attention to the

DS(ON)

GS(TH)

withlowerC

actuallyprovideshigherefﬁciency.The

BV

speciﬁcation for the MOSFETs as well; most of the

MILLER

DSS

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

short-circuit when the synchronous switch is on close to

100% of the period.

logic-level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the on-

resistance, R , Miller capacitance, C , input

DS(ON) MILLER

voltage and maximum output current. Miller capacitance,

, can be approximated from the gate charge curve

The term (1 + δ) is generally given for a MOSFET in the

C

MILLER

form of a normalized R

vs Temperature curve, but

usually provided on the MOSFET manufacturers’ data

sheet. C is equal to the increase in gate charge

DS(ON)

δ = 0.005/°C can be used as an approximation for low

MILLER

voltage MOSFETs.

along the horizontal axis while the curve is approximately

ﬂat divided by the speciﬁed change in V . This result is

DS

TheoptionalSchottkydiodeconductsduringthedeadtime

between the conduction of the two power MOSFETs. This

preventsthebodydiodeofthebottomMOSFETfromturn-

ing on, storing charge during the dead time and requiring

a reverse recovery period that could cost as much as 3%

then multiplied by the ratio of the application applied V

DS

to the gate charge curve speciﬁed V . When the IC is

DS

operating in continuous mode, the duty cycles for the top

and bottom MOSFETs are given by:

in efﬁciency at high V . A 1A to 3A Schottky is generally

V_OUT

Main Switch Duty Cycle =

V_IN

IN

a good size due to the relatively small average current.

Larger diodes result in additional transition losses due to

their larger junction capacitance.

V – V_OUT

IN

Synchronous Switch Duty Cycle =

V

IN

Soft-Start and Tracking

The MOSFET power dissipations at maximum output

current are given by:

The LTC3851-1 has the ability to either soft-start by itself

with a capacitor or track the output of another channel

or external supply. When the LTC3851-1 is conﬁgured

to soft-start by itself, a capacitor should be connected to

the TK/SS pin. The LTC3851-1 is in the shutdown state if

the RUN pin voltage is below 1.25V. TK/SS pin is actively

pulled to ground in this shutdown state.

V_OUT

2

P_MAIN

=

I

1+ δ R

+

)

(

)

(

)

MAX

DS(ON)

V

IN

I

⎛

⎝

⎞

2

MAX

V

R

C

•

(

)

( _DR)(

IN ⎜

⎟

⎠

MILLER

2

⎡

⎢

⎤

⎥

1

Once the RUN pin voltage is above 1.25V, the LTC3851-1

powersup.Asoft-startcurrentof1ꢀAthenstartstocharge

its soft-start capacitor. Note that soft-start or tracking is

achieved not by limiting the maximum output current of

the controller but by controlling the output ramp voltage

according to the ramp rate on the TK/SS pin. Current

foldback is disabled during this phase to ensure smooth

soft-start or tracking. The soft-start or tracking range is

+

(f)

V

_{⎢ INTVCC}– V_TH(MIN)V_TH(MIN)⎥

⎣

⎦

V – V_OUT

2

IN

P_SYNC

=

I

(

1+ δ R

DS(ON)

(

)

MAX

V

IN

where δ is the temperature dependency of R

and

DS(ON)

R

(approximately 2Ω) is the effective driver resistance

DR

at the MOSFET’s Miller threshold voltage. V

is the

TH(MIN)

typical MOSFET minimum threshold voltage.

38511f

14

LTC3851-1

APPLICATIONS INFORMATION

0V to 0.8V on the TK/SS pin. The total soft-start time can

be calculated as:

Output Voltage Tracking

The LTC3851-1 allows the user to program how its output

ramps up and down by means of the TK/SS pins. Through

this pin, the output can be set up to either coincidentally or

ratiometricallytrackwithanothersupply’soutput,asshown

C_SS

t_SOFT-START= 0.8 •

1.0μA

inFigure3. Inthefollowingdiscussions, V

refersto

Regardless of the mode selected by the MODE/PLLIN pin,

the regulator will always start in pulse skipping mode up

to TK/SS = 0.64V. Between TK/SS = 0.64V and 0.72V, it

will operate in forced continuous mode and revert to the

selected mode once TK/SS > 0.72V. The output ripple

is minimized during the 80mV forced continuous mode

window.

MASTER

amastersupplyandV

referstotheLTC3851-1’soutput

OUT

as a slave supply. To implement the coincident tracking in

Figure 3a, connect a resistor divider to V and con-

MASTER

nect its midpoint to the TK/SS pin of the LTC3851-1. The

ratio of this divider should be selected the same as that of

the LTC3851-1’s feedback divider as shown in Figure 4a.

In this tracking mode, V

must be higher than V

.

MASTER

OUT

When the regulator is conﬁgured to track another supply,

the feedback voltage of the other supply is duplicated by a

resistordividerandappliedtotheTK/SSpin.Therefore,the

voltageramprateonthispinisdeterminedbytheramprate

of the other supply’s voltage. Note that the small soft-start

capacitor charging current is always ﬂowing, producing

a small offset error. To minimize this error, one can select

the tracking resistive divider value to be small enough to

make this error negligible.

To implement ratiometric tracking, the ratio of the resistor

divider connected to V is determined by:

MASTER

V_MASTER

V_OUT

R2 R3+R4

⎛

⎞

=

⎜

⎟

⎠

⎝

R4 R1+R2

So which mode should be programmed? While either

mode in Figure 4 satisﬁes most practical applications,

the coincident mode offers better output regulation.

This concept can be better understood with the help

of Figure 5. At the input stage of the LTC3851-1’s error

ampliﬁer, two common anode diodes are used to clamp

the equivalent reference voltage and an additional diode

In order to track down another supply after the soft-start

phase expires, the LTC3851-1 must be conﬁgured for

forced continuous operation by connecting MODE/PLLIN

to INTV .

CC

V

MASTER

OUT

MASTER

V

OUT

38511 F03

TIME

(3a) Coincident Tracking

(3b) Ratiometric Tracking

Figure 3. Two Different Modes of Output Voltage Tracking

38511f

15

LTC3851-1

APPLICATIONS INFORMATION

V

OUT

V

OUT

MASTER

R3

R1

R2

R3

R4

TO

TK/SS

TO

FB

TO

TK/SS

TO

FB

V

R4

38511 F04

(4a) Coincident Tracking Setup

(4b) Ratiometric Tracking Setup

Figure 4. Setup for Coincident and Ratiometric Tracking

The LDO can supply a peak current of 50mA and must

be bypassed to ground with a minimum of 2.2ꢀF ceramic

capacitor or low ESR electrolytic capacitor. No matter

what type of bulk capacitor is used, an additional 0.1ꢀF

I

+

–

D1

D2

EA

ceramic capacitor placed directly adjacent to the INTV

CC

TK/SS

0.8V

and GND pins is highly recommended. Good bypassing

is needed to supply the high transient currents required

by the MOSFET gate drivers.

D3

38511 F05

V

FB

Figure 5. Equivalent Input Circuit of Error Ampliﬁer

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3851-1 to be

is used to match the shifted common mode voltage. The

top two current sources are of the same amplitude. In the

coincidentmode, theTK/SSvoltageissubstantiallyhigher

than 0.8V at steady-state and effectively turns off D1. D2

and D3 will therefore conduct the same current and offer

exceeded. The INTV current, which is dominated by the

CC

gate charge current, is supplied by the 5V LDO.

Power dissipation for the IC in this case is highest and

is approximately equal to V • I . The gate charge

tight matching between V and the internal precision

IN

INTVCC

FB

current is dependent on operating frequency as discussed

intheEfﬁciencyConsiderationssection. Thejunctiontem-

perature can be estimated by using the equations given in

Note 3 of the Electrical Characteristics. For example, the

0.8V reference. In the ratiometric mode, however, TK/SS

equals 0.8V at steady-state. D1 will divert part of the bias

current to make V slightly lower than 0.8V.

FB

Although this error is minimized by the exponential I-V

characteristic of the diode, it does impose a ﬁnite amount

ofoutputvoltagedeviation.Furthermore,whenthemaster

supply’s output experiences dynamic excursion (under

load transient, for example), the slave channel output will

be affected as well. For better output regulation, use the

coincident tracking mode instead of ratiometric.

LTC3851-1 INTV current is limited to less than 17mA

CC

from a 36V supply in the GN package:

T = 70°C + (17mA)(36V)(90°C/W) = 125°C

J

To prevent the maximum junction temperature from being

exceeded, the input supply current must be checked while

operating in continuous conduction mode (MODE/PLLIN

= INTV ) at maximum V .

CC

IN

INTV Regulator

CC

Topside MOSFET Driver Supply (C , D )

The LTC3851-1 features a PMOS low dropout linear

B

regulator (LDO) that supplies power to INTV from the

CC

An external bootstrap capacitor C connected to the

B

V supply. INTV powers the gate drivers and much of

IN

CC

BOOST pin supplies the gate drive voltage for the topside

the LTC3851-1 ’s internal circuitry. The LDO regulates the

MOSFET.CapacitorC intheFunctionalDiagramischarged

B

voltage at the INTV pin to 5V.

CC

though external diode D from INTV when the SW pin

B

CC

38511f

16

LTC3851-1

APPLICATIONS INFORMATION

required.Severalcapacitorsmayalsobeparalleledtomeet

size or height requirements in the design. Always consult

the manufacturer if there is any question.

is low. When the topside MOSFET is to be turned on, the

driver places the C voltage across the gate source of the

B

MOSFET. This enhances the MOSFET and turns on the

topside switch. The switch node voltage, SW, rises to V

IN

C

OUT

Selection

and the BOOST pin follows. With the topside MOSFET on,

The selection of C

is primarily determined by the

OUT

the boost voltage is above the input supply:

effective series resistance, ESR, to minimize voltage

V

= V + V

IN INTVCC

BOOST

ripple. The output ripple, ΔV , in continuous mode is

determined by:

OUT

The value of the boost capacitor C needs to be 100 times

B

that of the total input capacitance of the topside MOSFET.

⎛

⎞

1

The reverse breakdown of the external Schottky diode

ΔV_OUT≈ ΔI_LESR +

⎜

⎝

⎟

8fC_OUT

⎠

must be greater than V

.

IN(MAX)

Undervoltage Lockout

where f = operating frequency, C

= output capacitance

OUT

and ΔI = ripple current in the inductor. The output ripple

The LTC3851-1 has two functions that help protect the

controller in case of undervoltage conditions. A precision

L

is highest at maximum input voltage since ΔI increases

with input voltage. Typically, once the ESR requirement

L

UVLOcomparatorconstantlymonitorstheINTV voltage

CC

for C

has been met, the RMS current rating gener-

to ensure that an adequate gate-drive voltage is present.

OUT

ally far exceeds the I

requirement. With ΔI =

It locks out the switching action when INTV is below

RIPPLE(P-P)

L

CC

0.3I

and allowing 2/3 of the ripple to be due to

3.2V. To prevent oscillation when there is a disturbance

OUT(MAX)

ESR, the output ripple will be less than 50mV at maximum

on the INTV , the UVLO comparator has 400mV of preci-

CC

V and:

IN

sion hysteresis.

C_OUTRequired ESR < 2.2R_SENSE

1

Anotherwaytodetectanundervoltageconditionistomoni-

tor the V supply. Because the RUN pin has a precision

IN

C_OUT

>

turn-on reference of 1.25V, one can use a resistor divider

8fR_SENSE

to V to turn on the IC when V is high enough.

IN

TheﬁrstconditionrelatestotheripplecurrentintotheESR

oftheoutputcapacitancewhilethesecondtermguarantees

thattheoutputcapacitancedoesnotsigniﬁcantlydischarge

duringtheoperatingfrequencyperiodduetoripplecurrent.

The choice of using smaller output capacitance increases

the ripple voltage due to the discharging term but can be

compensated for by using capacitors of very low ESR to

C Selection

IN

Incontinuousmode, thesourcecurrentofthetopN-chan-

nel MOSFET is a square wave of duty cycle V /V . To

preventlargevoltagetransients, alowESRinputcapacitor

sized for the maximum RMS current must be used. The

maximum RMS capacitor current is given by:

OUT IN

maintain the ripple voltage at or below 50mV. The I pin

TH

1/2

⎛

⎞

V_OUT

V_IN

OPTI-LOOP compensation components can be optimized

to provide stable, high performance transient response

regardless of the output capacitors selected.

I_RMS≅ I_O(MAX)

– 1

⎜

⎟

V

⎝

⎠

OUT

This formula has a maximum at V = 2V , where I =

RMS

O(MAX)

IN

OUT

The selection of output capacitors for applications with

largeloadcurrenttransientsisprimarilydeterminedbythe

voltage tolerance speciﬁcations of the load. The resistive

component of the capacitor, ESR, multiplied by the load

current change, plus any output voltage ripple must be

within the voltage tolerance of the load.

I

/2. This simple worst-case condition is commonly

usedfordesignbecauseevensigniﬁcantdeviationsdonot

offermuchrelief.Notethatcapacitormanufacturers’ripple

current ratings are often based on only 2000 hours of life.

This makes it advisable to further derate the capacitor or

to choose a capacitor rated at a higher temperature than

38511f

17

LTC3851-1

APPLICATIONS INFORMATION

The required ESR due to a load current step is:

ΔV

AVX TPSV or the KEMET T510 series of surface mount

tantalums, available in case heights ranging from 1.5mm

to 4.1mm. Aluminum electrolytic capacitors can be used

in cost-driven applications, provided that consideration is

given to ripple current ratings, temperature and long-term

reliability. Atypicalapplicationwillrequireseveraltomany

aluminum electrolytic capacitors in parallel. A combina-

tion of the above mentioned capacitors will often result

in maximizing performance and minimizing overall cost.

Other capacitor types include Nichicon PL series, NEC

Neocap, Panasonic SP and Sprague 595D series. Consult

manufacturers for other speciﬁc recommendations.

R_ESR

≤

ΔI

whereΔIisthechangeincurrentfromfullloadtozeroload

(orminimumload)andΔVistheallowedvoltagedeviation

(not including any droop due to ﬁnite capacitance).

The amount of capacitance needed is determined by the

maximum energy stored in the inductor. The capacitance

must be sufﬁcient to absorb the change in inductor

current when a high current to low current transition

occurs. The opposite load current transition is generally

determined by the control loop OPTI-LOOP components,

so make sure not to over compensate and slow down

the response. The minimum capacitance to assure the

inductors’ energy is adequately absorbed is:

Like all components, capacitors are not ideal. Each

capacitor has its own beneﬁts and limitations. Combina-

tions of different capacitor types have proven to be a very

cost effective solution. Remember also to include high

frequency decoupling capacitors. They should be placed

as close as possible to the power pins of the load. Any

inductance present in the circuit board traces negates

their usefulness.

L ΔI ²

( )

C_OUT

>

2 ΔV V

(

)

OUT

where ΔI is the change in load current.

Setting Output Voltage

Manufacturers such as Nichicon, United Chemi-Con and

Sanyo can be considered for high performance through-

hole capacitors. The OS-CON semiconductor electrolyte

capacitor available from Sanyo has the lowest (ESR)(size)

product of any aluminum electrolytic at a somewhat

higher price. An additional ceramic capacitor in parallel

with OS-CON capacitors is recommended to reduce the

inductance effects.

The LTC3851-1 output voltage is set by an external feed-

back resistive divider carefully placed across the output,

as shown in Figure 6. The regulated output voltage is

determined by:

⎛

⎞

⎟

R_B

R_A

V_OUT= 0.8V 1+

⎜

⎝

⎠

Insurfacemountapplications,ESR,RMScurrenthandling

and load step speciﬁcations may require multiple capaci-

tors in parallel. Aluminum electrolytic, dry tantalum and

special polymer capacitors are available in surface mount

packages.Specialpolymersurfacemountcapacitorsoffer

very low ESR but have much lower capacitive density per

unit volume than other capacitor types. These capacitors

offeraverycost-effectiveoutputcapacitorsolutionandare

an ideal choice when combined with a controller having

highloopbandwidth.Tantalumcapacitorsofferthehighest

capacitance density and are often used as output capaci-

tors for switching regulators having controlled soft-start.

Several excellent surge-tested choices are the AVX TPS,

To improve the transient response, a feed-forward ca-

pacitor, C , may be used. Great care should be taken to

FF

route the V line away from noise sources, such as the

FB

inductor or the SW line.

V

OUT

R

C

FF

LTC3851-1

B

A

V

FB

R

38511 F06

Figure 6. Settling Output Voltage

38511f

18

LTC3851-1

APPLICATIONS INFORMATION

Fault Conditions: Current Limit and Current Foldback

Phase-Locked Loop and Frequency Synchronization

The LTC3851-1 includes current foldback to help limit

load current when the output is shorted to ground. If the

output falls below 40% of its nominal output level, the

maximum sense voltage is progressively lowered from

its maximum programmed value to about 25% of the that

value. Foldback current limiting is disabled during soft-

start or tracking. Under short-circuit conditions with very

low duty cycles, the LTC3851-1 will begin cycle skipping

in order to limit the short-circuit current. In this situation

the bottom MOSFET will be dissipating most of the power

but less than in normal operation. The short-circuit ripple

The LTC3851-1 has a phase-locked loop (PLL) comprised

of an internal voltage-controlled oscillator (V ) and a

CO

phase detector. This allows the turn-on of the top MOSFET

to be locked to the rising edge of an external clock signal

applied to the MODE/PLLIN pin. This phase detector is

an edge sensitive digital type that provides zero degrees

phase shift between the external and internal oscillators.

This type of phase detector does not exhibit false lock to

harmonics of the external clock.

Theoutputofthephasedetectorisapairofcomplementary

current sources that charge or discharge the external ﬁlter

networkconnectedtotheFREQ/PLLFLTRpin.Notethatthe

LTC3851-1 can only be synchronized to an external clock

whosefrequencyiswithinrangeoftheLTC3851-1’sinternal

current is determined by the minimum on-time t

ON(MIN)

of the LTC3851-1 (≈90ns), the input voltage and inductor

value:

V .Thisisguaranteedtobebetween250kHzand750kHz.

V

L

CO

IN

ΔI_L(SC)= t_ON(MIN)

•

A simpliﬁed block diagram is shown in Figure 8.

If the external clock frequency is greater than the internal

The resulting short-circuit current is:

oscillator’s frequency, f

, then current is sunk con-

OSC

1/4MaxV_SENSE

R_SENSE

1

2

tinuouslyfromthephasedetectoroutput,pullingdownthe

I_SC

=

– ΔI_L(SC)

FREQ/PLLFLTR pin. When the external clock frequency is

less than f

, current is sourced continuously, pulling up

OSC

Programming Switching Frequency

theFREQ/PLLFLTRpin.Iftheexternalandinternalfrequen-

ciesarethesamebutexhibitaphasedifference,thecurrent

sourcesturnonforanamountoftimecorrespondingtothe

phase difference. The voltage on the FREQ/PLLFLTR pin is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

To set the switching frequency of the LTC3851-1, connect

a resistor, R

, between FREQ/PLLFLTR and GND. The

FREQ

relationship between the oscillator frequency and R

is shown in Figure 7. A 0.1μF bypass capacitor should be

FREQ

connected in parallel with R

.

FREQ

750

700

650

600

550

500

450

400

350

300

250

the ﬁlter capacitor C holds the voltage.

LP

R

LP

2.7V

C

LP

FREQ/PLLFLTR

VCO

MODE/

PLLIN

DIGITAL

PHASE/

FREQUENCY

DETECTOR

EXTERNAL

OSCILLATOR

20

60

80 100 120 140 160

(kΩ)

40

R

FREQ

38511 F07

38511 F08

Figure 7. Relationship Between Oscillator Frequency

and Resistor Connected Between FREQ/PLLFLTR and GND

Figure 8. Phase-Locked Loop Block Diagram

38511f

19

LTC3851-1

APPLICATIONS INFORMATION

amount of cycle skipping can occur with correspondingly

larger current and voltage ripple.

The loop ﬁlter components, C and R , smooth out

LP

the current pulses from the phase detector and provide

a stable input to the voltage-controlled oscillator. The

Efﬁciency Considerations

ﬁlter components C and R determine how fast the

LP

loop acquires lock. Typically R is 1k to 10k and C is

LP

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Percent efﬁciency can

be expressed as:

2200pF to 0.01ꢀF.

When the external oscillator is active before the LTC3851

is enabled, the internal oscillator frequency will track the

externaloscillatorfrequencyasdescribedinthepreceding

paragraphs. In situations where the LTC3851 is enabled

before the external oscillator is active, a low free-running

oscillator frequency of approximately 50kHz will result. It

is possible to increase the free-running, pre-synchroniza-

tion frequency by adding a second resistor in parallel with

%Efﬁciency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

R

and C . The second resistor will also cause a phase

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of

LP

difference between the internal and external oscillator

signals.Themagnitudeofthephasedifferenceisinversely

proportional to the value of the second resistor.

the losses in LTC3851-1 circuits: 1) IC V current, 2)

IN

2

INTV regulatorcurrent,3)I Rlosses,4)topsideMOSFET

CC

transition losses.

The external clock (on MODE/PLLIN pin) input high

threshold is nominally 1.6V, while the input low threshold

is nominally 1.2V.

1. The V current is the DC supply current given in the

IN

ElectricalCharacteristicstable,whichexcludesMOSFET

driver current. V current typically results in a small

IN

Minimum On-Time Considerations

(<0.1%) loss.

Minimumon-timet

isthesmallesttimedurationthat

ON(MIN)

2. INTV_CCcurrent is the sum of the MOSFET driver and

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge dQ moves

fromINTV_CCtoground. TheresultingdQ/dtisacurrent

out of INTV_CCthat is typically much larger than the

control circuit current. In continuous mode, I_GATECHG

= f(Q_T+ Q_B), where Q_Tand Q_Bare the gate charges of

the topside and bottom side MOSFETs.

the LTC3851-1 is capable of turning on the top MOSFET.

It is determined by internal timing delays and the gate

charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

V_OUT

t_ON(MIN)

<

V (f)

IN

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

2

3. I R losses are predicted from the DC resistances of

the fuse (if used), MOSFET, inductor and current sense

resistor.Incontinuousmode,theaverageoutputcurrent

ﬂows through L and R

, but is “chopped” between

SENSE

Theminimumon-timefortheLTC3851-1isapproximately

90ns. However, as the peak sense voltage decreases the

minimum on-time gradually increases. This is of particu-

lar concern in forced continuous applications with low

ripple current at light loads. If the duty cycle drops below

the minimum on-time limit in this situation, a signiﬁcant

the topside MOSFET and the synchronous MOSFET. If

thetwoMOSFETshaveapproximatelythesameR

,

DS(ON)

then the resistance of one MOSFET can simply be

summed with the resistances of L and R

to ob-

SENSE

2

tain I R losses. For example, if each R

= 10mΩ,

DS(ON)

38511f

20

LTC3851-1

APPLICATIONS INFORMATION

control loop behavior but also provides a DC coupled and

AC ﬁltered closed-loop response test point. The DC step,

rise time and settling at this test point truly reﬂects the

closed-loop response. Assuming a predominantly second

ordersystem, phasemarginand/ordampingfactorcanbe

estimated using the percentage of overshoot seen at this

pin.Thebandwidthcanalsobeestimatedbyexaminingthe

DCR = 10mΩ and R

= 5mΩ, then the total resis-

SENSE

tance is 25mΩ. This results in losses ranging from 2%

to 8% as the output current increases from 3A to 15A

for a 5V output, or a 3% to 12% loss for a 3.3V output.

Efﬁciency varies as the inverse square of V

for the

OUT

sameexternalcomponentsandoutputpowerlevel. The

combined effects of increasingly lower output voltages

andhighercurrentsrequiredbyhighperformancedigital

systemsisnotdoublingbutquadruplingtheimportance

of loss terms in the switching regulator system!

rise time at the pin. The I external components shown

TH

in the Typical Application circuit will provide an adequate

starting point for most applications.

The I series R -C ﬁlter sets the dominant pole-zero

4. Transition losses apply only to the topside MOSFET(s),

and become signiﬁcant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

TH

C

loop compensation. The values can be modiﬁed slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the ﬁnal PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1ꢀs to 10ꢀs will

2

Transition Loss = (1.7)V • I

• C

• f

RSS

IN

O(MAX)

Other “hidden” losses such as copper trace and the bat-

tery internal resistance can account for an additional 5%

to 10% efﬁciency degradation in portable systems. It is

very important to include these “system” level losses

during the design phase. The internal battery and fuse

resistance losses can be minimized by making sure that

produce output voltage and I pin waveforms that will

TH

give a sense of the overall loop stability without breaking

the feedback loop. Placing a power MOSFET directly

across the output capacitor and driving the gate with an

appropriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This

C has adequate charge storage and very low ESR at the

IN

switching frequency. A 25W supply will typically require a

minimum of 20ꢀF to 40ꢀF of capacitance having a maxi-

mum of 20mΩ to 50mΩ of ESR. Other losses including

Schottky conduction losses during dead time and induc-

tor core losses generally account for less than 2% total

additional loss.

is why it is better to look at the I pin signal which is in

TH

the feedback loop and is the ﬁltered and compensated

Checking Transient Response

control loop response. The midband gain of the loop will

be increased by increasing R and the bandwidth of the

C

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

loop will be increased by decreasing C . If R is increased

C

bythesamefactorthatC isdecreased,thezerofrequency

C

will be kept the same, thereby keeping the phase shift the

same in the most critical frequency range of the feedback

loop. The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

the actual overall supply performance.

load current. When a load step occurs, V

shifts by an

OUT

amount equal to ΔI

(ESR), where ESR is the effective

LOAD

series resistance of C . ΔI

also begins to charge or

generating the feedback error signal that

forces the regulator to adapt to the current change and

OUT LOAD

discharge C

OUT

return V

to its steady-state value. During this recovery

can be monitored for excessive overshoot or

OUT

A second, more severe transient is caused by switching

in loads with large (>1ꢀF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

time V

OUT

ringing, which would indicate a stability problem. The

availability of the I pin not only allows optimization of

TH

with C , causing a rapid drop in V . No regulator can

OUT OUT

38511f

21

LTC3851-1

APPLICATIONS INFORMATION

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

the GND pin. The synchronous MOSFET source pins

should connect to the input capacitor(s) ground.

2. Does the V pin connect directly to the feedback resis-

FB

C

to C

is greater than 1:50, the switch rise time

LOAD

OUT

tors? The resistive divider R1, R2 must be connected

should be controlled so that the load rise time is limited

to approximately 25 • C . Thus a 10ꢀF capacitor would

between the (+) plate of C

and signal ground. The

OUT

LOAD

47pF to 100pF capacitor should be as close as possible

to the LTC3851-1. Be careful locating the feedback

require a 250ꢀs rise time, limiting the charging current

to about 200mA.

resistors too far away from the LTC3851-1. The V

FB

line should not be routed close to any other nodes with

PC Board Layout Checklist

high slew rates.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

theLTC3851-1.Theseitemsarealsoillustratedgraphically

in the layout diagram of Figure 9. Check the following in

your layout:

–

+

3. Are the SENSE and SENSE leads routed together

with minimum PC trace spacing? The ﬁlter capacitor

+

–

between SENSE and SENSE should be as close as

possible to the LTC3851-1. Ensure accurate current

sensingwithKelvinconnectionsasshowninFigure 10.

Series resistance can be added to the SENSE lines to

increase noise rejection and to compensate for the ESL

1. Are the board signal and power grounds segregated?

The LTC3851-1 GND pin should tie to the ground plane

closetotheinputcapacitor(s).Thelowcurrentorsignal

ground lines should make a single point tie directly to

of R

.

SENSE

+

0.1mF

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

MODE/PLLIN

SW

TG

R

FREQ

C

IN

M1

FREQ/PLLFLTR

RUN

BOOST

V

IN

LTC3851-1

C

SS

D1

TK/SS

V

IN

C

C2

C

B

C

D

B

C

R

C

M2

I

TH

INTV

CC

47pF

+

V

FB

BG

GND

4.7μF

–

+

SENSE

–

1000pF

R

PGOOD

V

PULL-UP

L1

–

R1

R2

C

OUT

V

OUT

+

R

SENSE

38511 F09

Figure 9. LTC385±-± Layout Diagram

38511f

22

LTC3851-1

APPLICATIONS INFORMATION

HIGH CURRENT PATH

Thedutycyclepercentageshouldbemaintainedfromcycle

tocycleinawelldesigned, lownoisePCBimplementation.

Variation in the duty cycle at a subharmonic rate can sug-

gest noise pick-up at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regulator

bandwidth optimization is not required.

38511 F10

CURRENT SENSE

RESISTOR

(R

)

Reduce V from its nominal level to verify operation

SENSE

+

–

IN

SENSE SENSE

of the regulator in dropout. Check the operation of the

undervoltage lockout circuit by further lowering V while

IN

Figure ±0. Kelvin Sensing R_SENSE

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

4. Does the (+) terminal of C connect to the drain of

IN

the topside MOSFET(s) as closely as possible? This

capacitor provides the AC current to the MOSFET(s).

5. Is the INTV decoupling capacitor connected closely

CC

between INTV and GND? This capacitor carries the

CC

MOSFETdriverpeakcurrents.Anadditional1ꢀFceramic

capacitor placed immediately next to the INTV and

CC

GND pins can help improve noise performance.

6. Keep the switching node (SW), top gate node (TG) and

boost node (BOOST) away from sensitive small-signal

nodes, especially from the voltage and current sensing

feedback pins. All of these nodes have very large and

fast moving signals and therefore should be kept on

the “output side” (Pin 9 to Pin 16) of the LTC3851-1

and occupy minimum PC trace area.

for inductive coupling between C , the Schottky and the

IN

top MOSFET to the sensitive current and voltage sens-

ing traces. In addition, investigate common ground path

voltage pickup between these components and the GND

pin of the IC.

PC Board Layout Debugging

Design Example

It is helpful to use a DC-50MHz current probe to monitor

thecurrentintheinductorwhiletestingthecircuit.Monitor

the output switching node (SW pin) to synchronize the

oscilloscope to the internal oscillator and probe the actual

outputvoltageaswell. Checkforproperperformanceover

the operating voltage and current range expected in the

application. The frequency of operation should be main-

tained over the input voltage range down to dropout and

until the output load drops below the low current opera-

tion threshold—typically 10% of the maximum designed

current level in Burst Mode operation.

As a design example, assume V = 12V (nominal), V =

IN

22V (maximum), V

= 1.8V, I

= 5A, and f = 250kHz

OUT

MAX

(refer to Figure 12).

The inductance value is chosen ﬁrst based on a 30%

ripple current assumption. The highest value of ripple

current occurs at the maximum input voltage. Connect a

160k resistor between the FREQ/PLLFLTR and GND pins,

generating 250kHz operation. The minimum inductance

for 30% ripple current is:

⎛

⎞

V_OUT

V_IN

1

f L

( )( )

ΔI_L=

V_OUT1−

⎜

⎝

⎟

⎠

38511f

23

LTC3851-1

APPLICATIONS INFORMATION

A short-circuit to ground will result in a folded back cur-

rent of:

A 4.7μH inductor will produce 28% ripple current and

a 3.3μH will result in 40%. The peak inductor current

will be the maximum DC value plus one-half the ripple

current, or 6A, for the 3.3μH value. Increasing the ripple

current will also help ensure that the minimum on-time

of 90ns is not violated. The minimum on-time occurs at

⎛

⎞

90ns 22V

29mV

0.0125Ω 2

1

(

)

I_SC

=

–

= 2.02A

⎜

⎟

3.3μH

⎝

⎠

with a typical value of R

and δ = (0.005/°C)(25°C)

DS(ON)

maximum V :

IN

= 0.125. The resulting power dissipated in the bottom

V_OUT

V_IN(MAX)

1.8V

MOSFET is:

t_ON(MIN)

=

= 327ns

f

( )

22V 250kHz

(

)

22V

2

P_SYNC

=

2.02A 1.125 0.022Ω = 101.0mW

(

) (

)(

)

The R

resistor value can be calculated by using the

SENSE

maximum current sense voltage speciﬁcation with some

accommodation for tolerances.

which is less than under full-load conditions.

C is chosen for an RMS current rating of at least 3A at

IN

50mV

6A

temperature. C

is chosen with an ESR of 0.02Ω for

OUT

R_SENSE

≤

= 0.0083Ω

low output ripple. The output ripple in continuous mode

will be highest at the maximum input voltage. The output

voltage ripple due to ESR is approximately:

Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields

an output voltage of 1.816V.

V

= R (ΔI ) = 0.02Ω (2A) = 40mV

ESR L P-P

ORIPPLE

ThepowerdissipationonthetopsideMOSFETcanbeeasily

estimated. Choosing a Fairchild FDS6982S dual MOSFET

results in: R

= 0.035Ω/0.022Ω, C

= 215pF. At

DS(ON)

MILLER

maximum input voltage with T (estimated) = 50°C:

1.8V

⎡

⎤

P_MAIN

=

5 ²1+ 0.005 50°C − 25°C •

( )

(

)(

)

⎣

⎦

22V

0.035Ω + 22V

5A

2

⎛

⎞

2

2Ω 215pF •

)(

(

) (

)

(

)

⎜

⎝

⎟

⎠

1

⎡

⎤

+

250kHz = 185mW

(

)

⎢

⎣

⎥

⎦

5− 2.3 2.3

38511f

24

LTC3851-1

TYPICAL APPLICATIONS

V

IN

4.5V TO 32V

MODE/PLLIN

V

IN

+

C

R

IN

FREQ

22μF

82.5k

M1

FREQ/PLLFLTR

TG

BOOST

SW

HAT2170H

C

B

0.1μF

RUN

C20

0.1μF

C

SS

L1

0.68μH

LTC3851-1

0.1μF

V

3.3V

15A

OUT

TK/SS

C

D

C

B

R

C2

R2

154k

1%

C

C15

47pF

2200pF

R27

3.01k

CMDSH05-4

330pF

15k

I

INTV

CC

+

C

TH

OUT

330μF

4.7μF

s2

R1

48.7k

1%

M2

HAT2170H

V

BG

GND

FB

–

+

SENSE

C5

0.047μF

R

PG

30.1k

C

: SANYO 6TPE330MIL

OUT

IN

V

PGOOD

PULL-UP

: SANYO 63HVH22M

L1: VISHAY IHLP5050-EZERR68M01

38511 F11

Figure ±±. High Efﬁciency 3.3V/±5A Step-Down Converter

V

IN

4.5V TO 22V

MODE/PLLIN

V

IN

C

22μF

25V

+

IN

R

FREQ

160k

M1

FREQ/PLLFLTR

TG

BOOST

SW

FDS6982S

C

B

0.1μF

RUN

C

SS

L1

3.3μH

R

SENSE

0.01Ω

LTC3851-1

0.1μF

V

1.8V

5A

OUT

TK/SS

C

R2

32.4k

1%

D

B

R

C

470pF

C2

CMDSH-3

C

OUT

33k

220pF

+

150μF

I

INTV

CC

TH

6.3V

s2

PANASONIC SP

R1

25.5k

1%

4.7μF

M2

FDS6982S

V

BG

GND

FB

–

+

SENSE

1000pF

R

PG

PGOOD

V

PULL-UP

C

: PANASONIC EEFUEOG151R

OUT

IN

: MARCON THCR70LE1H226ZT

L1: PANASONIC ETQP6F3R3HFA

: IRC LR 2010-01-R010F

R

SENSE

38511 TA02

Figure ±2. ±.8V/5A Converter from Design Example with Pulse Skip Operation

38511f

25

LTC3851-1

TYPICAL APPLICATIONS

±.5V/±5A Synchronized at 350kHz

V

IN

6V TO 14V

PLLIN

350kHz

MODE/PLLIN

V

IN

C2

+

R5

10k

C

0.01μF

IN

180μF

M1

FREQ/PLLFLTR

TG

BOOST

SW

RJK0305DPB

C

B

C1

1000pF

0.1μF

RUN

C

SS

L1

0.68μH

R

SENSE

0.002Ω

LTC3851-1

0.1μF

V

1.5V

15A

OUT

TK/SS

C

R2

43.2k

1%

D

R

B

C

7.5k

C10

33pF

C

C2

1000pF

CMDSH-3

100pF

+

C

OUT

I

INTV

CC

TH

330μF

R1

20k

1%

s2

4.7μF

M2

RJK0301DPB

V

BG

GND

FB

–

+

SENSE

C

: SANYO 2R5TPE330M9

1000pF

OUT

R

PG

L1: SUMIDA CEP125-OR6MC

SENSE

V

PULL-UP

PGOOD

R22 10Ω

R20 10Ω

38511 TA03

38511f

26

LTC3851-1

PACKAGE DESCRIPTION

MSE Package

16-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1667 Rev A)

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.845 p 0.102

(.112 p .004)

2.845 p 0.102

(.112 p .004)

0.889 p 0.127

(.035 p .005)

1

8

0.35

REF

5.23

(.206)

MIN

1.651 p 0.102

(.065 p .004)

1.651 p 0.102

(.065 p .004)

3.20 – 3.45

(.126 – .136)

0.12 REF

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

DETAIL “B”

16

9

0.305 p 0.038

(.0120 p .0015)

TYP

0.50

(.0197)

BSC

NO MEASUREMENT PURPOSE

4.039 p 0.102

(.159 p .004)

(NOTE 3)

0.280 p 0.076

(.011 p .003)

RECOMMENDED SOLDER PAD LAYOUT

16151413121110

9

REF

DETAIL “A”

0o – 6o TYP

0.254

(.010)

3.00 p 0.102

(.118 p .004)

(NOTE 4)

4.90 p 0.152

(.193 p .006)

GAUGE PLANE

0.53 p 0.152

(.021 p .006)

1 2 3 4 5 6 7 8

DETAIL “A”

0.86

(.034)

REF

1.10

(.043)

MAX

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 p 0.0508

(.004 p .002)

MSOP (MSE16) 0608 REV A

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

UD Package

16-Lead Plastic QFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1691)

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.20 TYP

OR 0.25 s 45o CHAMFER

R = 0.115

TYP

0.75 p 0.05

3.00 p 0.10

(4 SIDES)

15 16

0.70 p0.05

PIN 1

TOP MARK

(NOTE 6)

0.40 p 0.10

1

2

1.45 p 0.10

(4-SIDES)

3.50 p 0.05

2.10 p 0.05

1.45 p 0.05

(4 SIDES)

PACKAGE

OUTLINE

(UD16) QFN 0904

0.25 p 0.05

0.50 BSC

0.200 REF

0.25 p0.05

0.50 BSC

0.00 – 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

38511f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LTC3851-1

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1625/LTC1775

No R

^TMCurrent Mode Synchronous Step-Down

97% Efﬁciency, No Sense Resistor, 16-Pin SSOP

SENSE

Controllers

LTC1735

LTC1778

High Efﬁciency Synchronous Step-Down Switching Regulator Output Fault Protection, 16-Pin SSOP

No R Wide Input Range Synchronous Step-Down Up to 97% Efﬁciency, 4V ≤ V ≤ 36V,

SENSE

IN

Controller

0.8V ≤ V

≤ (0.9)(V ), I

Up to 20A

OUT

IN OUT

LT^®3724

Low I High Voltage Current Mode Switching Regulator

V

up to 60V, I

≤ 5A, 16-Lead TSSOP FE Package, 100μA I ,

OUT Q

Q

IN

Controller

Onboard Bias Regulator, Burst Mode Operation, 200kHz Operation

LTC3727A-1

LTC3728

Dual, 2-Phase Synchronous Controller

2-Phase 550kHz, Dual Synchronous Step-Down Controller

20A to 200A PolyPhase^®Synchronous Controller

Very Low Dropout, V ≤ 14V

OUT

QFN and SSOP Packages, High Frequency for Smaller L and C

LTC3729L-6

Expandable from 2-Phase to 12-Phase, Uses All Surface Mount

Components, No Heat Sink

LTC3731

LTC3773

LT3800

3-Phase, 600kHz Synchronous Step-Down Controller

Triple Output DC/DC Synchronous Controller

0.6V ≤ V

≤ 6V, 4.5V ≤ V ≤ 32V, I

≤ 60A, Integrated

OUT

IN

MOSFET Drivers

3-Phase Step-Down DC/DC Controller, 3.3V ≤ V ≤ 36V, Fixed

Frequency 160kHz to 700kHz

IN

Low I High Voltage Synchronous Regulator Controller

V

IN

up to 60V, I

≤ 20A, Current Mode, Onboard Bias Regulator,

Q

OUT

100μA I , Burst Mode Operation, 16-Lead TSSOP FE Package

Q

LTC3810

LTC3811

LTC3824

100V Current Mode Nonisolated Switching Regulator

Controller

6.2V ≤ V ≤ 100, 0.8V ≤ V

≤ 0.9V , No R

, Tracking and

IN

OUT

IN

SENSE

Synchronizable

Dual, PolyPhase Synchronous Step-Down Controller,

20A to 200A

Differential Remote Sense Ampliﬁer, R

or DCR Current Sense

SENSE

Low I High Voltage 100% Duty Cycle Step-Down Controller

4V ≤ V ≤ 60V, 0.8V ≤ V

≤ V , 40μA Quiescent Current,

Q

IN

OUT

IN

MSOP-10 Package

LTC3826/LTC3826-1 Low I Dual Synchronous Controllers

4V ≤ V ≤ 36V, 0.8V ≤ V

≤ 10V, 30μA Quiescent Current

Q

IN

OUT

LTC3834/LTC3834-1 Low I Synchronous Step-Down Controllers

Single Channel LTC3826/LTC3826-1

V up to 60V, I ≤ 5A, Onboard Bias Regulator, Burst Mode

IN

Q

LTC3844

Low I High Voltage Current Mode Controller with

Q

OUT

Programmable Operating Frequency

Operation, 120μA I , Sync Capability, 16-Lead TSSOP FE Package

Q

LTC3845

Low I Synchronous Step-Down Controller

4V ≤ V ≤ 60V, 1.23V ≤ V

≤ 36V, 120μA Quiescent Current

Q

IN

OUT

LTC3850/LTC3850-1 Dual, 2-Phase Synchronous Step-Down Controllers

LTC3850-2

R

SENSE

or DCR Current Sensing, Tracking and Synchronizable

LTC3853

LTM^®4600

Triple Output, Mulitphase Synchronous Step-Down Controller

10A Complete Switch Mode Power Supply

R

or DCR Current Sensing, Tracking and Synchronizable

SENSE

92% Efﬁciency, V : 4.5V to 28V, V

Control, UltraFast™ Transient Response

= 0.6V, True Current Mode

OUT

IN

OUT

LTM4601A

LTM8020

LTM8021

12A Complete Switch Mode Power Supply

92% Efﬁciency, V : 4.5V to 28V, V

Control, UltraFast Transient Response

IN

High V 0.2A DC/DC Step-Down μModule

4V ≤ V ≤ 36V, 1.25V ≤ V

LGA Package

≤ 5V, 6.25mm × 6.25mm × 2.3mm

IN

OUT

High V 0.5A DC/DC Step-Down μModule

3V ≤ V ≤ 36V, 0.8V ≤ V

LGA Package

≤ 5V, 6.25mm × 11.25mm × 2.8mm

IN

OUT

LTM8022/LTM8023 36V , 1A and 2A DC/DC μModule

Pin Compatible, 4.5V ≤ V ≤ 36V, 9mm × 11.25mm × 2.8mm

IN

LGA Package

PolyPhase is a registered trademark of Linear Technology Corporation. No R

and UltraFast are trademarks of Linear Technology Corporation.

SENSE

38511f

LT 1108 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3851EMSE-1-PBF
厂家：	Linear
描述：	Synchronous Step-Down Switching Regulator Controller 同步降压型开关稳压控制器开关控制器
文件：	总28页 (文件大小：337K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3851EMSE-1-PBF [Linear]

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