LTC3855IUJ#PBF [Linear]
LTC3855 - Dual, Multiphase Synchronous DC/DC Controller with Differential Remote Sense; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C;
| 型号： | LTC3855IUJ#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3855 - Dual, Multiphase Synchronous DC/DC Controller with Differential Remote Sense; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总44页 (文件大小：2146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3855
Dual, Multiphase
Synchronous DC/DC Controller
with Differential Remote Sense
FeaTures
DescripTion
TheLTC®3855isadualPolyPhase® currentmodesynchro-
n
Dual, 180° Phased Controllers Reduce Required
Input Capacitance and Power Supply Induced Noise
High Efficiency: Up to 95%
SENSE
Programmable DCR Temperature Compensation
0ꢀ.5% 0ꢀꢁ6 ꢂutput 6oltage Accuracy
nous step-down switching regulator controller that drives
all N-channel power MOSFET stages. It includes a high
speed differential remote sense amplifier. The maximum
current sense voltage is programmable for either 30mV,
50mVor75mV, allowingtheuseofeithertheinductorDCR
or a discrete sense resistor as the sensing element.
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
R
or DCR Current Sensing
Phase-Lockable Fixed Frequency 250kHz to ..0kHz
True Remote Sensing Differential Amplifier
Dual N-Channel MOSFET Synchronous Drive
The LTC3855 features a precision 0.6V reference and can
produce output voltages up to 12.5V. A wide 4.5V to 38V
input supply range encompasses most intermediate bus
voltages and battery chemistries. Power loss and supply
noiseareminimizedbyoperatingthetwocontrolleroutput
stages out of phase. Burst Mode® operation, continuous
or pulse-skipping modes are supported.
Wide V Range: 4.5V to 38V
IN
V
V
Range: 0.6V to 12.5V without Differential Amplifier
Range: 0.6V to 3.3V with Differential Amplifier
OUT
OUT
Clock Input and Output for Up to 12-Phase Operation
Adjustable Soft-Start or V
Tracking
OUT
Foldback Output Current Limiting
The LTC3855 can be configured for up to 12-phase op-
eration, has DCR temperature compensation, two power
good signals and two current limit set pins. The LTC3855
is available in low profile 40-pin 6mm × 6mm QFN and
38-lead exposed pad FE packages.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and PolyPhase are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620, 6100678,
6144194, 6177787, 6304066, 6580258.
Output Overvoltage Protection
40-Pin (6mm × 6mm) QFN and 38-Lead FE Packages
applicaTions
n
Computer Systems
n
Telecom Systems
n
Industrial and Medical Instruments
DC Power Distribution Systems
n
Typical applicaTion
High Efficiency Dual 1ꢀ86/1ꢀ26 Step-Down Converter
V
IN
Load Step
(Forced Continuous Mode)
4.5V TO
20V
+
22µF
1µF
4.7µF
V
IN
INTV
CC
TG1
TG2
I
LOAD
0.1µF
0.1µF
5A/DIV
BOOST1
SW1
BOOST2
SW2
0.4µH
0.56µH
300mA TO 5A
BG1
BG2
I
L
PGND1
PGND2
FREQ
5A/DIV
LTC3855
+
+
SENSE1
SENSE1
SENSE2
–
–
SENSE2
V
OUT
20k
V
100mV/DIV
OUT1
1.8V
15A
V
DIFFOUT
OUT2
AC-COUPLED
V
FB1
1.2V
V
FB2
15A
40.2k
I
I
TH1
TK/SS1 DIFFP SGND DIFFN TK/SS2
TH2
470pF
470pF
7.5k
20k
+
+
330µF
×2
330µF
×2
3855 TA01a
20k
100k
15k
50µs/DIV
0.1µF
0.1µF
V
V
= 12V
IN
OUT
= 1.8V
3855 TA01
3855f
ꢀ
LTC3855
absoluTe MaxiMuM raTings
(Note 1)
Input Supply Voltage (V ).........................–0.3V to 40V
DIFFP, DIFFN..........................................–0.3V to INTV
ITEMP1, ITEMP2 Voltages ....................–0.3V to INTV
TH1 TH2 FB1 FB2
IN
CC
CC
CC
Top Side Driver Voltages
BOOST1, BOOST2..................................–0.3V to 46V
Switch Voltage (SW1, SW2) .........................–5V to 40V
I
, I , V , V Voltages..............–0.3V to INTV
INTV Peak Output Current (Note 8) ..................100mA
CC
INTV , RUN1, RUN2, PGOOD(s), EXTV ,
Operating Junction Temperature Range (Notes 2, 3)
LTC3855.............................................–40°C to 125°C
Storage Temperature Range...................–65°C to 125°C
Lead Temperature (Soldering, 10 sec)
CC
CC
(BOOST1-SW1), (BOOST2-SW2).............–0.3V to 6V
+
+
–
SENSE1 , SENSE2 , SENSE1 ,
–
SENSE2 Voltages .................................–0.3V to 13V
MODE/PLLIN, I
, I
, TK/SS1, TK/SS2, FREQ,
(FE Package)..................................................... 300°C
LIM1 LIM2
DIFFOUT, PHASMD Voltages.............–0.3V to INTV
CC
pin conFiguraTion
TOP VIEW
1
2
FREQ
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
ITEMP2
ITEMP1
RUN1
TOP VIEW
MODE/PLLIN
PHASMD
CLKOUT
SW1
3
+
4
SENSE1
–
5
SENSE1
40 39 38 37 36 35 34 33 32 31
6
TG1
TK/SS1
TK/SS1
1
2
3
4
5
6
7
8
9
30
29
28
TG1
7
BOOST1
PGND1
BG1
I
TH1
I
BOOST1
PGND1
TH1
8
V
V
I
V
FB1
FB2
FB1
9
SGND
27 BG1
39
SGND
10
11
12
13
14
15
16
17
18
19
V
V
26
25
V
IN
IN
FB2
41
SGND
TH2
I
INTV
INTV
CC
TK/SS2
TH2
CC
+
TK/SS2
24 EXTV
23 BG2
EXTV
CC
CC
SENSE2
+
–
SENSE2
BG2
SENSE2
–
SENSE2
22 PGND2
21
PGND2
BOOST2
TG2
DIFFP
DIFFN
DIFFP 10
BOOST2
11 12 13 14 15 16 17 18 19 20
DIFFOUT
RUN2
SW2
PGOOD2
PGOOD1
I
LIM1
LIM2
UJ PACKAGE
40-LEAD (6mm s 6mm) PLASTIC QFN
I
T
= 125°C, θ = 33°C/W
JA
JMAX
FE PACKAGE
38-LEAD PLASTIC SSOP
EXPOSED PAD (PIN 41) IS SGND, MUST BE SOLDERED TO PCB
T
= 125°C, θ = 25°C/W
JA
JMAX
EXPOSED PAD (PIN 39) IS SGND, MUST BE SOLDERED TO PCB
3855f
ꢁ
LTC3855
orDer inForMaTion
LEAD FREE FINISH
LTC3855EFE#PBF
LTC3855IFE#PBF
LTC3855EUJ#PBF
LTC3855IUJ#PBF
TAPE AND REEL
PART MARKING*
LTC3855FE
PACKAGE DESCRIPTIꢂN
TEMPERATURE RANGE
–40°C to 85°C
LTC3855EFE#TRPBF
LTC3855IFE#TRPBF
LTC3855EUJ#TRPBF
LTC3855IUJ#TRPBF
38-Lead Plastic TSSOP
LTC3855FE
38-Lead Plastic TSSOP
–40°C to 125°C
–40°C to 85°C
LTC3855UJ
LTC3855UJ
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
junction temperature range (E-Grade), otherwise specifications are at TA = 25°Cꢀ 6IN = 156, 6RUN1,2 = 56 unless otherwise notedꢀ
SYMBꢂL
PARAMETER
CꢂNDITIꢂNS
MIN
TYP
MAX UNITS
Main Control Loops
V
V
V
Input Voltage Range
4.5
0.6
38
V
V
IN
Output Voltage Range
Regulated Feedback Voltage
12.5
OUT
FB1,2
l
l
I
I
Voltage = 1.2V (Note 4)
0.5955
0.594
0.600
0.600
0.6045
0.606
V
V
TH1,2
TH1,2
Voltage = 1.2V (Note 4), T = 125°C
A
I
Feedback Current
(Note 4)
= 4.5V to 38V (Note 4)
–15
–50
nA
FB1,2
V
V
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
IN
0.002
0.02
%/V
REFLNREG
LOADREG
(Note 4)
Measured in Servo Loop; ∆I Voltage = 1.2V to 0.7V
Measured in Servo Loop; ∆I Voltage = 1.2V to 1.6V
l
l
0.01
–0.01
0.1
–0.1
%
%
TH
TH
g
Transconductance Amplifier g
I = 1.2V; Sink/Source 5µA; (Note 4)
TH1,2
2
mmho
m1,2
m
I
Input DC Supply Current
Normal Mode
(Note 5)
IN
RUN1,2
Q
V
V
= 15V
3.5
30
mA
µA
Shutdown
= 0V
50
DF
Maximum Duty Factor
Undervoltage Lockout
UVLO Hysteresis
In Dropout, f
= 500kHz
94
95
3.2
0.6
0.66
1
%
V
MAX
OSC
l
UVLO
UVLO
V
Ramping Down
3.0
3.4
INTVCC
V
HYS
l
l
l
l
l
V
Feedback Overvoltage Lockout
Sense Pins Bias Current
Measured at V
0.64
0.68
2
V
OVL1,2
FB1,2
I
I
I
(Each Channel); V
= 3.3V
µA
µA
µA
V
SENSE1,2
TEMP1,2
TK/SS1,2
SENSE1,2
DCR Tempco Compensation Current
Soft-Start Charge Current
V
= 0.2V
= 0V
9
1
10
11
ITEMP1,2
V
1.2
1.22
80
1.4
1.35
TK/SS1,2
V
V
V
RUN Pin ON Threshold
V , V Rising
RUN1 RUN2
1.1
RUN1,2
RUN Pin ON Hysteresis
mV
RUN1,2HYS
SENSE(MAX)
l
l
l
Maximum Current Sense Threshold
V
FB1,2
V
FB1,2
V
FB1,2
= 0.5V, V
= 0.5V, V
= 0.5V, V
= 3.3V, I = 0V
25
45
68
30
50
75
35
55
82
mV
mV
mV
SENSE1,2
SENSE1,2
SENSE1,2
LIM
LIM
LIM
= 3.3V, I = Float
= 3.3V, I = INTV
CC
TG1, 2 t
TG1, 2 t
TG Transition Time:
Rise Time
(Note 6)
r
f
C
C
= 3300pF
25
25
ns
ns
LOAD
LOAD
Fall Time
= 3300pF
BG1, 2 t
BG1, 2 t
BG Transition Time:
Rise Time
(Note 6)
LOAD
LOAD
r
f
C
C
= 3300pF
= 3300pF
25
25
ns
ns
Fall Time
3855f
ꢂ
LTC3855
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
junction temperature range (E-Grade), otherwise specifications are at TA = 25°Cꢀ 6IN = 156, 6RUN1,2 = 56 unless otherwise notedꢀ
SYMBꢂL
PARAMETER
CꢂNDITIꢂNS
MIN
TYP
MAX UNITS
TG/BG t
Top Gate Off to Bottom Gate On Delay C
Synchronous Switch-On Delay Time
= 3300pF Each Driver
30
ns
1D
LOAD
BG/TG t
Bottom Gate Off to Top Gate On Delay C
Top Switch-On Delay Time
= 3300pF Each Driver
30
90
ns
ns
2D
LOAD
t
Minimum On-Time
(Note 7)
ON(MIN)
CC
INTVCC
INT6 Linear Regulator
V
V
V
V
V
Internal V Voltage
6V < V < 38V
4.8
4.5
5
5.2
2
V
%
CC
IN
INT
INTV Load Regulation
I = 0mA to 20mA
CC
0.5
4.7
50
LDO
CC
l
EXTV Switchover Voltage
EXTV Ramping Positive
V
EXTVCC
CC
CC
EXT
EXTV Voltage Drop
I
= 20mA, V = 5V
EXTVCC
100
mV
mV
LDO
CC
CC
EXTV Hysteresis
200
LDOHYS
CC
ꢂscillator and Phase-Locked Loop
f
f
f
Nominal Frequency
V
V
V
= 1.2V
= 0V
450
210
700
500
250
770
250
10
550
290
850
kHz
kHz
kHz
kΩ
µA
NOM
LOW
HIGH
FREQ
FREQ
FREQ
Lowest Frequency
Highest Frequency
≥ 2.4V
R
MODE/PLLIN Input Resistance
Frequency Setting Current
Phase (Relative to Controller 1)
MODE/PLLIN
I
9
11
FREQ
CLKOUT
PHASMD = GND
PHASMD = Float
PHASMD = INTV
60
90
120
Deg
Deg
Deg
CC
CLK
CLK
Clock High Output Voltage
Clock Low Output Voltage
4
5
0
V
V
HIGH
LOW
0.2
PGꢂꢂD ꢂutput
V
PGOOD Voltage Low
I
= 2mA
= 5V
0.1
0.3
2
V
PGL
PGOOD
I
PGOOD Leakage Current
PGOOD Trip Level, Either Controller
V
V
µA
PGOOD
PGOOD
V
PG
with Respect to Set Output Voltage
FB
V
V
Ramping Negative
Ramping Positive
–10
10
%
%
FB
FB
Differential Amplifier
l
A
Gain
0.998
1
1.002
2
V/V
kΩ
DA
R
Input Resistance
Measured at DIFFP Input
= V = 1.5V, I = 100µA
DIFFOUT
80
IN
V
Input Offset Voltage
V
DIFFP
mV
dB
OS
DIFFOUT
PSRR
Power Supply Rejection Ratio
Maximum Output Current
Maximum Output Voltage
Gain Bandwidth Product
Differential Amplifier Slew Rate
5V < V < 38V
100
3
OA
IN
I
CL
2
mA
V
V
I
= 300µA
V
–1.4 V
–1.1
OUT(MAX)
DIFFOUT
INTVCC
INTVCC
GBW
(Note 8)
(Note 8)
3
2
MHz
V/µs
Slew Rate
3855f
ꢃ
LTC3855
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
junction temperature range (E-Grade), otherwise specifications are at TA = 25°Cꢀ 6IN = 156, 6RUN/SS = 56 unless otherwise notedꢀ
SYMBꢂL
PARAMETER
CꢂNDITIꢂNS
MIN
TYP
MAX UNITS
ꢂn Chip Driver
TG R
TG R
BG R
BG R
TG Pull-Up R
TG High
TG Low
BG High
BG Low
2.6
1.5
2.4
1.1
Ω
Ω
Ω
Ω
UP
DS(ON)
TG Pull-Down R
DOWN
UP
DS(ON)
BG Pull-Up R
DS(ON)
BG Pull-Down R
DOWN
DS(ON)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The LTC3855 is tested in a feedback loop that servos V
to a
ITH1,2
specified voltage and measures the resultant V
.
FB1,2
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note ꢁ: Rise and fall times are measured using 10% and 90% levels. Delay
Note 2: The LTC3855E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3855I is guaranteed
to meet performance specifications over the full –40°C to 125°C operating
junction temperature range.
times are measured using 50% levels.
Note .: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥40% of I
(see Minimum On-Time
MAX
Considerations in the Applications Information section).
Note 8: Guaranteed by design.
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formulas:
D
LTC3855UJ: T = T + (P • 33°C/W)
J
A
D
LTC3855FE: T = T + (P • 25°C/W)
J
A
D
Typical perForMance characTerisTics
Efficiency vs ꢂutput Current
and Mode
Efficiency vs ꢂutput Current
and Mode
Full Load Efficiency and Power
Loss vs Input 6oltage
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
90
85
80
75
5
4
3
2
1.8V
Burst Mode
OPERATION
EFFICIENCY
Burst Mode
OPERATION
1.2V
DCM
DCM
V
V
= 12V
= 1.8V
V
V
= 12V
= 1.2V
IN
OUT
IN
OUT
1.8V
CCM
CCM
POWER LOSS
1.2V
CIRCUIT OF FIGURE 19
10 100
CIRCUIT OF FIGURE 19
1 10 100
CIRCUIT OF FIGURE 19
5
10
15
20
0.01
0.1
1
0.01
0.1
LOAD CURRENT (A)
LOAD CURRENT (A)
INPUT VOLTAGE (V)
3855 G23
3855 G24
3855 G24
3855f
ꢄ
LTC3855
Typical perForMance characTerisTics
Load Step
(Burst Mode ꢂperation)
Load Step
(Forced Continuous Mode)
I
LOAD
I
LOAD
5A/DIV
5A/DIV
300mA TO 5A
300mA TO 5A
I
I
L
L
5A/DIV
5A/DIV
V
V
OUT
OUT
100mV/DIV
100mV/DIV
AC-COUPLED
AC-COUPLED
3855 G01
3855 G02
50µs/DIV
50µs/DIV
V
V
= 12V
V
V
= 12V
IN
OUT
IN
OUT
= 1.8V
= 1.8V
Load Step
(Pulse-Skipping Mode)
Inductor Current at Light Load
I
LOAD
FORCED
CONTINUOUS MODE
5A/DIV
5A/DIV
300mA TO 5A
I
L
Burst Mode
OPERATION
5A/DIV
5A/DIV
V
OUT
100mV/DIV
PULSE-SKIPPING
MODE
AC-COUPLED
5A/DIV
3855 G03
3855 G04
50µs/DIV
1µs/DIV
V
V
= 12V
V
V
LOAD
= 12V
IN
IN
OUT
= 1.8V
= 1.8V
OUT
I
= 400mA
Prebiased ꢂutput at 26
Coincident Tracking
V
OUT
RUN
2V/DIV
2V/DIV
V
V
OUT1
OUT2
V
FB
V
500mV/DIV
OUT1
OUT2
V
TK/SS
500mV/DIV
1V/DIV
3855 G05
3855 G06
2ms/DIV
5ms/DIV
= 1.8V, 1.5Ω LOAD
= 1.2V, 1Ω LOAD
V
V
= 12V
IN
OUT
V
V
OUT1
OUT2
= 3.3V
3855f
ꢅ
LTC3855
Typical perForMance characTerisTics
Tracking Up and Down
with External Ramp
Quiescent Current
vs Temperature without EXT6CC
INT6CC Line Regulation
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
TK/SS1
TK/SS2
2V/DIV
V
V
OUT1
OUT2
V
V
OUT1
OUT2
500mA/DIV
3855 G07
10ms/DIV
= 1.8V, 1.5Ω LOAD
V
V
V
= 12V
IN
OUT1
OUT2
= 1.2V, 1Ω LOAD
–50 –25
0
25
50
75 100 125
0
10
20
30
40
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3855 G08
3855 G09
Maximum Current Sense
Threshold vs Common Mode
6oltage
Current Sense Threshold
vs ITH 6oltage
Maximum Current Sense
Threshold vs Duty Cycle
80
60
80
70
60
50
40
30
20
10
0
80
70
60
50
I
= INTV
CC
LIM
I
= INTV
CC
LIM
I
= INTV
CC
LIM
I
= FLOAT
LIM
40
20
I
= FLOAT
= GND
I
= FLOAT
= GND
LIM
LIM
40
30
I
= GND
LIM
0
–20
–40
I
I
LIM
LIM
20
10
0
0
0.5
1
1.5
2
20
40
80
2
4
6
0
100
0
8
10
12
60
V
(V)
DUTY CYCLE (%)
ITH
V
COMMON MODE VOLTAGE (V)
SENSE
3855 G10
3855 G12
3855 G11
Maximum Current Sense 6oltage
vs Feedback 6oltage (Current
Foldback)
TK/SS Pull-Up Current
vs Temperature
1.6
1.4
1.2
1.0
90
I
= INTV
CC
LIM
80
70
60
50
40
30
20
10
0
I
= FLOAT
LIM
I
= GND
LIM
–50 –25
0
25
50
75 100 125
0.1
0.2
0.3
0
0.4
0.5
0.6
TEMPERATURE (°C)
FEEDBACK VOLTAGE (V)
3855 G14
3855 G13
3855f
ꢆ
LTC3855
Typical perForMance characTerisTics
Shutdown (RUN) Threshold
vs Temperature
Regulated Feedback 6oltage
vs Temperature
ꢂscillator Frequency
vs Temperature
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
612
610
608
606
604
602
600
598
596
594
592
900
800
700
600
500
400
300
200
100
0
V
= INTV
= 1.2V
FREQ
CC
ON
V
FREQ
V
= GND
FREQ
OFF
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
–50 –25
0
25
75
3855 G15
3855 G16
3855 G17
Undervoltage Lockout Threshold
(INT6CC) vs Temperature
ꢂscillator Frequency
vs Input 6oltage
Shutdown Current
vs Input 6oltage
4.1
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
520
510
500
490
480
60
50
40
30
20
10
0
RISING
FALLING
40
TEMPERATURE (°C)
80 100
–40 –20
0
20
60
5
10
15
20
25
30
35
40
5
10
15
20
25
30
35
40
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3855 G18
3855 G19
3855 G20
Shutdown Current
vs Temperature
Quiescent Current
vs Input 6oltage without EXT6CC
60
50
40
30
20
10
0
4.5
4.3
4.1
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
5
10
15
20
25
30
35
40
INPUT VOLTAGE (V)
3855 G21
3855 G22
3855f
ꢇ
LTC3855
pin FuncTions (FE38/UJ40)
ITEMP1, ITEMP2 (Pin 2, Pin 1/Pin 3., Pin 3ꢁ): Inputs of
the temperature sensing comparators. Connect each of
these pins to external NTC resistors placed near induc-
tors. Floating these pins disables the DCR temperature
compensation function.
DIFFP (Pin 14/Pin 10): Positive Input of Remote Sens-
ing Differential Amplifier. Connect this to the remote load
voltage of one of the two channels directly.
DIFFN (Pin 15/Pin 11): Negative Input of Remote Sensing
DifferentialAmplifier. Connectthistothenegativeterminal
of the output capacitors.
RUN1, RUN2 (Pin 3, Pin 1./Pin 38, Pin 13): Run Control
Inputs. A voltage above 1.2V on either pin turns on the IC.
However, forcing either of these pins below 1.2V causes
theICtoshutdownthecircuitryrequiredforthatparticular
channel. There are 1µA pull-up currents for these pins.
Once the Run pin rises above 1.2V, an additional 4.5µA
pull-up current is added to the pin.
DIFFꢂUT (Pin 1ꢁ/Pin 12): Output of Remote Sensing Dif-
ferential Amplifier. Connect this to V or V through
FB1
FB2
a resistive divider.
I
, I (Pin 18, Pin 19/Pin 14, Pin 15): Current
LIM1 LIM2
Comparator Sense Voltage Range Inputs. This pin can
be tied to SGND, tied to INTV or left floating to set the
maximum current sense threshold for each comparator.
CC
+
+
SENSE1 , SENSE2 (Pin 4, Pin 12/Pin 39, Pin 8):Current
Sense Comparator Inputs. The (+) inputs to the current
comparators are normally connected to DCR sensing
networks or current sensing resistors.
PGꢂꢂD1,PGꢂꢂD2(Pin20,Pin21/Pin1ꢁ,Pin1.):Power
Good Indicator Output for Each Channel. Open drain logic
out that is pulled to ground when either channel output
exceeds 10% regulation window, after the internal 20µs
power bad mask timer expires.
–
–
SENSE1 , SENSE2 (Pin 5, Pin 13/Pin 40, Pin 9):Current
Sense Comparator Inputs. The (–) inputs to the current
comparators are connected to the outputs.
EXT6 (Pin 2./Pin 24): External Power Input to an Inter-
CC
TK/SS1, TK/SS2 (Pin ꢁ, Pin 11/Pin 1, Pin .): Output Volt-
age Tracking and Soft-Start Inputs. When one particular
channel is configured to be the master of two channels,
a capacitor to ground at this pin sets the ramp rate for
the master channel’s output voltage. When the channel
nal Switch Connected to INTV . This switch closes and
CC
supplies the IC power, bypassing the internal low dropout
regulator, whenever EXTV is higher than 4.7V. Do not
CC
exceed 6V on this pin.
INT6 (Pin28/Pin25):Internal5VRegulatorOutput. The
is configured to be the slave of two channels, the V
CC
FB
control circuits are powered from this voltage. Decouple
this pin to PGND with a minimum of 4.7µF low ESR tan-
talum or ceramic capacitor.
voltage of the master channel is reproduced by a resistor
divider and applied to this pin. Internal soft-start currents
of 1.2µA are charging these pins.
6 (Pin 29/Pin 2ꢁ): Main Input Supply. Decouple this pin
I
, I
(Pin ., Pin 10/Pin 2, Pin ꢁ): Current Control
IN
TH1 TH2
to PGND with a capacitor (0.1µF to 1µF).
Thresholds and Error Amplifier Compensation Points.
Each associated channels’ current comparator tripping
BG1, BG2 (Pin 30, Pin 2ꢁ/Pin 2., Pin 23): Bottom Gate
threshold increases with its I control voltage.
TH
Driver Outputs. These pins drive the gates of the bottom
N-Channel MOSFETs between PGND and INTV .
6
, 6
FB1
(Pin 8, Pin 9/Pin 3, Pin 5): Error Amplifier
FB2
CC
Feedback Inputs. These pins receive the remotely sensed
feedback voltages for each channel from external resistive
dividers across the outputs.
PGND1, PGND2 (Pin 31, Pin 25/Pin 28, Pin 22): Power
Ground Pin. Connect this pin closely to the sources of the
bottom N-channel MOSFETs, the (–) terminal of C
and
VCC
the (–) terminal of C .
IN
3855f
ꢈ
LTC3855
pin FuncTions (FE38/UJ40)
BꢂꢂST1,BꢂꢂST2(Pin32,Pin24/Pin29,Pin21):Boosted
Floating Driver Supplies. The (+) terminal of the bootstrap
capacitors connect to these pins. These pins swing from a
MꢂDE/PLLIN (Pin 3./Pin 34): This is a dual purpose pin.
When external frequency synchronization is not used,
this pin selects the operating mode. The pin can be tied
diode voltage drop below INTV up to V + INTV .
to SGND, tied to INTV or left floating. SGND enables
CC
IN
CC
CC
forced continuous mode. INTV enables pulse-skipping
CC
TG1, TG2 (Pin 33, Pin 23/Pin 30, Pin 20): Top Gate
mode.FloatingenablesBurstModeoperation.Forexternal
sync, apply a clock signal to this pin. Both channels will
go into forced continuous mode and the internal PLL will
synchronize the internal oscillator to the clock. The PLL
compensation network is integrated into the IC.
Driver Outputs. These are the outputs of floating drivers
with a voltage swing equal to INTV superimposed on
CC
the switch nodes voltages.
SW1, SW2 (Pin 34, Pin 22/Pin 31, Pin 19): Switch Node
Connections to Inductors. Voltage swing at these pins
is from a Schottky diode (external) voltage drop below
FREQ (Pin 38/Pin 35): There is a precision 10µA current
flowing out of this pin. A resistor to ground sets a voltage
which in turn programs the frequency. Alternatively, this
pin can be driven with a DC voltage to vary the frequency
of the internal oscillator.
ground to V .
IN
PHASMD (Pin 3ꢁ/Pin 33): This pin can be tied to SGND,
tied to INTV or left floating. This pin determines the
CC
relative phases between the internal controllers as well
as the phasing of the CLKOUT signal. See Table 1 in the
Operation section.
SGND (Exposed Pad Pin 39/ Pin 4, Exposed Pad Pin 41):
Signal Ground. All small-signal components and com-
pensation components should connect to this ground,
which in turn connects to PGND at one point. Exposed
pad must be soldered to PCB, providing a local ground
for the control components of the IC, and be tied to the
PGND pin under the IC.
CLKꢂUT(Pin35/Pin32):Clockoutputwithphasechange-
able by PHASMD to enable usage of multiple LTC3855 in
multiphase systems.
3855f
ꢀ0
LTC3855
FuncTional block DiagraM
FREQ
MODE/PLLIN
PHASMD
ITEMP
EXTV
V
IN
CC
V
IN
4.7V
+
C
IN
–
+
TEMPSNS
F
0.6V
5V
REG
MODE/SYNC
DETECT
PLL-SYNC
INTV
CC
–
+
INTV
CC
F
BOOST
CLKOUT
BURSTEN
OSC
S
C
B
TG
FCNT
ON
R
Q
I
M1
SW
L1
SWITCH
LOGIC
AND
ANTI-
SHOOT
THROUGH
V
OUT
3k
+
–
–
+
+
D
SENSE
SENSE
B
I
CMP
REV
–
+
C
OUT
RUN
OV
BG
M2
C
VCC
SLOPE COMPENSATION
I
LIM
PGND
PGOOD
DIFFP
INTV
CC
UVLO
40k
+
–
+
–
0.54V
R2
SLOPE RECOVERY
ACTIVE CLAMP
1
UV
OV
DIFFAMP
V
40k
FB
51k
I
THB
DIFFN
40k
40k
+
–
V
SLEEP
IN
R1
0.66V
SGND
SS
RUN
–
–
+
+
0.6V
REF
1.2µA
EA
+ –
–
+
+
0.5V
1.2V
1µA
0.55V
3855 FBD
C
C
SS
C1
I
TH
RUN
TK/SS
DIFFOUT
R
C
3855f
ꢀꢀ
LTC3855
operaTion
Main Control Loop
Shutdown and Start-Up (RUN1, RUN2 and TK/SS1,
TK/SS2 Pins)
The LTC3855 is a constant-frequency, current mode step-
down controller with two channels operating 180 degrees
out-of-phase. During normal operation, each top MOSFET
is turned on when the clock for that channel sets the RS
latch, and turned off when the main current comparator,
The two channels of the LTC3855 can be independently
shut down using the RUN1 and RUN2 pins. Pulling either
of these pins below 1.2V shuts down the main control
loopforthatcontroller. Pullingbothpinslowdisablesboth
I
, resets the RS latch. The peak inductor current at
controllersandmostinternalcircuits,includingtheINTV
CMP
which I
CC
resets the RS latch is controlled by the voltage
regulator. Releasing either RUN pin allows an internal
1µA current to pull up the pin and enable that controller.
Alternatively, the RUN pin may be externally pulled up
or driven directly by logic. Be careful not to exceed the
Absolute Maximum Rating of 6V on this pin.
CMP
TH
on the I pin, which is the output of each error ampli-
fier EA. The V pin receives the voltage feedback signal,
FB
which is compared to the internal reference voltage by the
EA. When the load current increases, it causes a slight
decrease in V relative to the 0.6V reference, which in
FB
The start-up of each controller’s output voltage V
is
OUT
turn causes the I voltage to increase until the average
TH
controlled by the voltage on the TK/SS1 and TK/SS2 pins.
When the voltage on the TK/SS pin is less than the 0.6V
inductor current matches the new load current. After the
top MOSFET has turned off, the bottom MOSFET is turned
on until either the inductor current starts to reverse, as
indicated by the reverse current comparator I , or the
beginning of the next cycle.
internal reference, the LTC3855 regulates the V voltage
FB
totheTK/SSpinvoltageinsteadofthe0.6Vreference. This
allows the TK/SS pin to be used to program the soft-start
periodbyconnectinganexternalcapacitorfromtheTK/SS
pin to SGND. An internal 1.2µA pull-up current charges
this capacitor, creating a voltage ramp on the TK/SS pin.
As the TK/SS voltage rises linearly from 0V to 0.6V (and
REV
INT6 /EXT6 Power
CC
CC
Power for the top and bottom MOSFET drivers and most
otherinternalcircuitryisderivedfromtheINTV pin.When
beyond),theoutputvoltageV risessmoothlyfromzero
CC
OUT
the EXTV pin is left open or tied to a voltage less than
to its final value. Alternatively the TK/SS pin can be used
CC
4.7V,aninternal5VlinearregulatorsuppliesINTV power
to cause the start-up of V
to “track” that of another
CC
OUT
from V . If EXTV is taken above 4.7V, the 5V regulator is
supply. Typically, this requires connecting to the TK/SS
pin an external resistor divider from the other supply to
ground (see the Applications Information section). When
the corresponding RUN pin is pulled low to disable a
IN
CC
turned off and an internal switch is turned on connecting
EXTV . Using the EXTV pin allows the INTV power
CC
CC
CC
to be derived from a high efficiency external source such
as one of the LTC3855 switching regulator outputs.
controller, or when INTV drops below its undervoltage
CC
lockout threshold of 3.2V, the TK/SS pin is pulled low by
an internal MOSFET. When in undervoltage lockout, both
controllers are disabled and the external MOSFETs are
held off.
Each top MOSFET driver is biased from the floating
bootstrap capacitor C , which normally recharges during
B
each off cycle through an external diode when the top
MOSFET turns off. If the input voltage V decreases to
IN
a voltage close to V , the loop may enter dropout and
OUT
Light Load Current ꢂperation (Burst Mode ꢂperation,
Pulse-Skipping, or Continuous Conduction)
attempt to turn on the top MOSFET continuously. The
dropout detector detects this and forces the top MOSFET
off for about one-twelfth of the clock period plus 100ns
The LTC3855 can be enabled to enter high efficiency Burst
Modeoperation,constant-frequencypulse-skippingmode,
or forced continuous conduction mode. To select forced
continuous operation, tie the MODE/PLLIN pin to a DC
every third cycle to allow C to recharge. However, it is
B
recommended that a load be present or the IC operates
at low frequency during the drop-out transition to ensure
C is recharged.
B
3855f
ꢀꢁ
LTC3855
operaTion
voltage below 0.6V (e.g., SGND). To select pulse-skipping
mode of operation, tie the MODE/PLLIN pin to INTV . To
Multichip ꢂperations (PHASMD and CLKꢂUT Pins)
CC
The PHASMD pin determines the relative phases between
the internal controllers as well as the CLKOUT signal as
shown in Table 1. The phases tabulated are relative to
zero phase being defined as the rising edge of the clock
of phase 1.
select Burst Mode operation, float the MODE/PLLIN pin.
When a controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-third of the maximum sense voltage even though
the voltage on the I pin indicates a lower value. If the
TH
Table 1ꢀ
average inductor current is higher than the load current,
PHASMD
Phase1
GND
0°
FLꢂAT
0°
INT6cc
0°
the error amplifier EA will decrease the voltage on the I
TH
pin. When the I voltage drops below 0.5V, the internal
TH
sleep signal goes high (enabling sleep mode) and both
Phase2
180°
60°
180°
90°
240°
120°
external MOSFETs are turned off.
CLKOUT
In sleep mode, the load current is supplied by the output
capacitor. Astheoutputvoltagedecreases, theEA’s output
begins to rise. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When a controller is
enabled for Burst Mode operation, the inductor current is
not allowed to reverse. The reverse current comparator
The CLKOUT signal can be used to synchronize additional
powerstagesinamultiphasepowersupplysolutionfeeding
a single, high current output or separate outputs. Input
capacitance ESR requirements and efficiency losses are
substantiallyreducedbecausethepeakcurrentdrawnfrom
the input capacitor is effectively divided by the number
of phases used and power loss is proportional to the
RMS current squared. A two stage, single output voltage
implementation can reduce input path power loss by 75%
and radically reduce the required RMS current rating of
the input capacitor(s).
(I ) turns off the bottom external MOSFET just before
REV
the inductor current reaches zero, preventing it from
reversing and going negative. Thus, the controller oper-
ates in discontinuous operation. In forced continuous
operation, the inductor current is allowed to reverse at
light loads or under large transient conditions. The peak
Single ꢂutput Multiphase ꢂperation
The LTC3855 can be used for single output multiphase
converters by making these connections
inductor current is determined by the voltage on the I
TH
pin. In this mode, the efficiency at light loads is lower than
in Burst Mode operation. However, continuous mode has
theadvantagesofloweroutputrippleandlessinterference
with audio circuitry.
• Tie all of the I pins together
TH
• Tie all of the V pins together
FB
• Tie all of the TK/SS pins together
• Tie all of the RUN pins together
• Tie all of the ITEMP pins together
When the MODE/PLLIN pin is connected to INTV , the
CC
LTC3855 operates in PWM pulse-skipping mode at light
loads.Atverylight loads,thecurrentcomparatorI
may
CMP
remaintrippedforseveralcyclesandforcetheexternaltop
MOSFET to stay off for the same number of cycles (i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuousoperation, exhibitslowoutputrippleaswellas
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
efficiency than forced continuous mode, but not nearly as
high as Burst Mode operation.
• Tie all of the I
pins together, or tie the I
pins to
LIM
LIM
the same potential
For three or more phases, tie the inputs of the unused dif-
ferential amplifier(s) to ground. Examples of single output
multiphase converters are shown in Figures 20 to 23.
3855f
ꢀꢂ
LTC3855
operaTion
Sensing the ꢂutput 6oltage with a Differential
Where:
Amplifier
V
isthemaximumadjustedcurrentsense
is the maximum current sense threshold
SENSEMAX(ADJ)
threshold.
The LTC3855 includes a low offset, unity gain, high band-
widthdifferentialamplifierforapplicationsthatrequiretrue
remote sensing. Sensing the load across the load capaci-
torsdirectlygreatlybenefitsregulationinhighcurrent,low
voltage applications, where board interconnection losses
can be a significant portion of the total error budget.
V
SENSE(MAX)
specified in the electrical characteristics table. It is typi-
cally 75mV, 50mV, or 30mV depending on the setting
I
pins.
LIM
V
ITEMP
is the voltage of ITEMP pin.
TheLTC3855differentialamplifierhasatypicaloutputslew
rate of 2V/μs. The amplifier is configured for unity gain,
meaning that the difference between DIFFP and DIFFN is
translated to DIFFOUT, relative to SGND.
The valid voltage range for DCR temperature compensa-
tion on the ITEMP pin is between 0.5V to 0.2V, with 0.5V
or above being no DCR temperature correction and 0.2V
the maximum correction. However, if the duty cycle of the
controller is less than 25%, the ITEMP range is extended
from 0.5V to 0V.
Care should be taken to route the DIFFP and DIFFN PCB
traces parallel to each other all the way to the terminals
of the output capacitor or remote sensing points on the
board. In addition, avoid routing these sensitive traces
near any high speed switching nodes in the circuit. Ideally,
the DIFFP and DIFFN traces should be shielded by a low
impedance ground plane to maintain signal integrity.
An NTC resistor has a negative temperature coefficient,
that means that its value decreases as temperature rises.
The V
voltage, therefore, decreases as temperature
ITEMP
increases and in turn the V
will increase to
SENSEMAX(ADJ)
compensate the DCR temperature coefficient. The NTC
resistor, however, is non-linear and user can linearize its
value by building a resistor network with regular resis-
tors. Consult the NTC manufacture datasheets for detailed
information.
Inductor DCR Sensing Temperature Compensation and
the ITEMP Pins
Inductor DCR current sensing provides a lossless method
of sensing the instantaneous current. Therefore, it can
provide higher efficiency for applications of high output
currents. However the DCR of a copper inductor typically
has a positive temperature coefficient. As the temperature
of the inductor rises, its DCR value increases. The current
limit of the controller is therefore reduced.
Another use for the ITEMP pins, in addition to NTC com-
pensated DCR sensing, is adjusting V
to values
SENSE(MAX)
between the nominal values of 30mV, 50mV and 75mV for
a more precise current limit. This is done by applying a
voltage less than 0.5V to the ITEMP pin. V
will
SENSE(MAX)
be varied per the above equation and the same duty cycle
limitationswillapply.Thecurrentlimitcanbeadjustedusing
this method either with a sense resistor or DCR sensing.
LTC3855 offers a method to counter this inaccuracy by
allowing the user to place an NTC temperature sensing
resistor near the inductor. ITEMP pin, when left floating, is
at a voltage around 5V and DCR temperature compensa-
tion is disabled. ITEMP pin has a constant 10µA precision
current flowing out the pin. By connecting an NTC resistor
from ITEMP pin to SGND, the maximum current sense
threshold can be varied over temperature according the
following equation:
FormoreinformationseetheNTCCompensatedDCRSens-
ing paragraph in the Applications Information section.
Frequency Selection and Phase-Locked Loop
(FREQ and MꢂDE/PLLIN Pins)
Theselectionofswitchingfrequencyisatrade-offbetween
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage. The switching
1.8 – V
ITEMP
VSENSEMAX(ADJ) = VSENSE(MAX)
•
1.3
3855f
ꢀꢃ
LTC3855
operaTion
frequency of the LTC3855’s controllers can be selected
using the FREQ pin. If the MODE/PLLIN pin is not being
driven by an external clock source, the FREQ pin can be
usedtoprogramthecontroller’soperatingfrequencyfrom
250kHz to 770kHz.
Power Good (PGꢂꢂD Pins)
When V pin voltage is not within 10% of the 0.6V refer-
FB
ence voltage, the PGOOD pin is pulled low. The PGOOD
pin is also pulled low when the RUN pin is below 1.2V or
when the LTC3855 is in the soft-start or tracking phase.
The PGOOD pin will flag power good immediately when
There is a precision 10µA current flowing out of the FREQ
pin, so the user can program the controller’s switching
frequency with a single resistor to SGND. A curve is
provided later in the application section showing the
relationship between the voltage on the FREQ pin and
switching frequency.
the V pin is within the 10% of the reference window.
FB
However, there is an internal 20µs power bad mask when
V goes out the 10% window. Each channel has its own
FB
PGOOD and only responds to its own channel signals.
The PGOOD pins are allowed to be pulled up by external
resistors to sources of up to 6V.
A phase-locked loop (PLL) is integrated on the LTC3855
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The
controller is operating in forced continuous mode when
it is synchronized.
ꢂutput ꢂvervoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious condi-
tions that may overvoltage the output. In such cases, the
topMOSFETisturnedoffandthebottomMOSFETisturned
on until the overvoltage condition is cleared.
ThePLLloopfilternetworkisintegratedinsidetheLTC3855.
The phase-locked loop is capable of locking any frequency
withintherangeof250kHzto770kHz.Thefrequencysetting
resistorshouldalwaysbepresenttosetthecontroller’sinitial
switching frequency before locking to the external clock.
applicaTions inForMaTion
TheTypicalApplicationonthefirstpageisabasicLTC3855
applicationcircuit.LTC3855canbeconfiguredtouseeither
DCR (inductor resistance) sensing or low value resistor
sensing. The choice between the two current sensing
schemes is largely a design trade-off between cost, power
consumption, and accuracy. DCR sensing is becoming
popular because it saves expensive current sensing resis-
tors and is more power efficient, especially in high current
applications. However, current sensing resistors provide
the most accurate current limits for the controller. Other
externalcomponentselectionisdrivenbytheloadrequire-
for the maximum current sense threshold will be 30mV,
50mV or 75mV, respectively. The maximum current sense
thresholdwillbeadjustedtovaluesbetweenthesesettings
by applying a voltage less than 0.5V to the ITEMP pin. See
the Operation section for more details.
Which setting should be used? For the best current limit
accuracy, use the 75mV setting. The 30mV setting will
allow for the use of very low DCR inductors or sense
resistors, but at the expense of current limit accuracy.
The 50mV setting is a good balance between the two. For
single output dual phase applications, use the 50mV or
75mV setting for optimal current sharing.
ment, and begins with the selection of R
(if R
is
SENSE
SENSE
used)andinductorvalue.Next,thepowerMOSFETsarese-
lected. Finally, input and output capacitors are selected.
+
–
SENSE and SENSE Pins
+
–
The SENSE and SENSE pins are the inputs to the current
comparators. The common mode input voltage range of
the current comparators is 0V to 12.5V. Both SENSE pins
are high impedance inputs with small base currents of
Current Limit Programming
The I pin is a tri-level logic input which sets the maxi-
LIM
mum current limit of the controller. When I
is either
LIM
grounded, floated or tied to INTV , the typical value
CC
3855f
ꢀꢄ
LTC3855
applicaTions inForMaTion
less than 1µA. When the SENSE pins ramp up from 0V to
1.4V, the small base currents flow out of the SENSE pins.
When the SENSE pins ramp down from 12.5V to 1.1V,
the small base currents flow into the SENSE pins. The
high impedance inputs to the current comparators allow
accurate DCR sensing. However, care must be taken not
to float these pins during normal operation.
BecauseofpossiblePCBnoiseinthecurrentsensingloop,
theACcurrentsensingrippleof∆V
=∆I •R also
SENSE
L
SENSE
needs to be checked in the design to get a good signal-to-
noiseratio. Ingeneral, forareasonablygoodPCBlayout, a
10mV ∆V
voltage is recommended as a conservative
SENSE
number to start with, either for R
or DCR sensing
SENSE
applications, for duty cycles less than 40%.
Filter components mutual to the sense lines should be
placed close to the LTC3855, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), sense resistor R1 should be placed
closetotheswitchingnode,topreventnoisefromcoupling
intosensitivesmall-signalnodes. ThecapacitorC1should
be placed close to the IC pins.
For previous generation current mode controllers, the
maximum sense voltage was high enough (e.g., 75mV for
theLTC1628/LTC3728family)thatthevoltagedropacross
the parasitic inductance of the sense resistor represented
a relatively small error. For today’s highest current density
solutions, however, the value of the sense resistor can
be less than 1mΩ and the peak sense voltage can be as
low as 20mV. In addition, inductor ripple currents greater
than 50% with operation up to 1MHz are becoming more
common. Under these conditions the voltage drop across
the sense resistor’s parasitic inductance is no longer neg-
ligible. A typical sensing circuit using a discrete resistor is
showninFigure2a. Inpreviousgenerationsofcontrollers,
a small RC filter placed near the IC was commonly used to
reducetheeffectsofcapacitiveandinductivenoisecoupled
inthe sense traces on the PCB. A typical filter consists of
two series 10Ω resistors connected to a parallel 1000pF
capacitor, resulting in a time constant of 20ns.
TO SENSE FILTER,
NEXT TO THE CONTROLLER
C
OUT
R
SENSE
3855 F01
Figure 1ꢀ Sense Lines Placement with Sense Resistor
This same RC filter, with minor modifications, can be used
to extract the resistive component of the current sense
signalinthepresenceofparasiticinductance.Forexample,
Figure 3 illustrates the voltage waveform across a 2mΩ
sense resistor with a 2010 footprint for the 1.2V/15A
converter operating at 100% load. The waveform is the
superposition of a purely resistive component and a
purely inductive component. It was measured using two
scope probes and waveform math to obtain a differential
measurement. Based on additional measurements of the
inductor ripple current and the on-time and off-time of
the top switch, the value of the parasitic inductance was
determined to be 0.5nH using the equation:
Low 6alue Resistors Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. R
output current.
is chosen based on the required
SENSE
The current comparator has a maximum threshold
determined by the I setting. The input
V
SENSE(MAX)
LIM
common mode range of the current comparator is 0V to
12.5V. The current comparator threshold sets the peak of
the inductor current, yielding a maximum average output
current I
equal to the peak value less half the peak-to-
MAX
peak ripple current, ∆I . To calculate the sense resistor
L
value, use the equation:
VESL(STEP)
tON • tOFF
tON + tOFF
ESL=
∆IL
VSENSE(MAX)
RSENSE
=
∆IL
I(MAX)
+
If the RC time constant is chosen to be close to the
parasitic inductance divided by the sense resistor (L/R),
3855f
2
ꢀꢅ
LTC3855
applicaTions inForMaTion
V
V
IN
V
V
IN
IN
IN
INTV
INTV
CC
CC
BOOST
TG
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
INDUCTOR
BOOST
TG
OPTIONAL
TEMP COMP
NETWORK
V
L
DCR
SW
OUT
R
S
ESL
V
OUT
SW
LTC3855
ITEMP
LTC3855
BG
BG
C
• 2 ≤ ESL/R
RF
F
S
R
S
PGND
POLE-ZERO
PGND
R1**
CANCELLATION
+
R
R
F
F
SENSE
+
SENSE
R
NTC
R
P
C1*
||
R2
C
F
–
–
SENSE
SENSE
SGND
SGND
3855 F02a
L
DCR
R2
R1 + R2
+
FILTER COMPONENTS
PLACED NEAR SENSE PINS
R
= DCR
**PLACE R1 NEXT TO *PLACE C1 NEAR SENSE , R1 R2 × C1 =
SENSE(EQ)
–
INDUCTOR
SENSE PINS
3855 F02b
(2a) Using a Resistor to Sense Current
(2b) Using the Inductor DCR to Sense Current
Figure 2ꢀ Two Different Methods of Sensing Current
The above generally applies to high density/high current
applications where I >10A and low values of induc-
the resulting waveform looks resistive again, as shown
in Figure 4. For applications using low maximum sense
voltages, check the sense resistor manufacturer’s data
sheet for information about parasitic inductance. In the
absence of data, measure the voltage drop directly across
the sense resistor to extract the magnitude of the ESL
step and use the equation above to determine the ESL.
However,donotover-filter.KeeptheRCtimeconstantless
than or equal to the inductor time constant to maintain a
(MAX)
tors are used. For applications where I
<10A, set R
(MAX)
F
to 10 Ohms and C to 1000pF. This will provide a good
F
starting point.
The filter components need to be placed close to the IC.
The positive and negative sense traces need to be routed
as a differential pair and Kelvin connected to the sense
resistor.
high enough ripple voltage on V
.
RSENSE
Inductor DCR Sensing
Forapplicationsrequiringthehighestpossibleefficiencyat
high load currents, the LTC3855 is capable of sensing the
voltage drop across the inductor DCR, as shown in Figure
2b. The DCR of the inductor represents the small amount
of DC winding resistance of the copper, which can be less
than 1mΩ for today’s low value, high current inductors.
In a high current application requiring such an inductor,
conduction loss through a sense resistor would cost sev-
eral points of efficiency compared to DCR sensing.
V
ESL(STEP)
V
SENSE
20mV/DIV
3855 F03
500ns/DIV
Figure 3ꢀ 6oltage Waveform Measured
Directly Across the Sense Resistorꢀ
If the external R1||R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
V
SENSE
20mV/DIV
3855 F04
500ns/DIV
Figure 4ꢀ 6oltage Waveform Measured After the
Sense Resistor Filterꢀ CF = 1000pF, RF = 100Ωꢀ
3855f
ꢀꢆ
LTC3855
applicaTions inForMaTion
always the same and varies with temperature; consult the
manufacturers’ datasheets for detailed information.
V
IN(MAX) − VOUT • V
(
)
OUT
PLOSS R1=
R1
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
totheextraswitchinglossesincurredthroughR1.However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
VSENSE(MAX)
RSENSE(EQUIV)
=
∆IL
I(MAX)
+
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimumvaluefortheMaximumCurrentSenseThreshold
(V
)intheElectricalCharacteristicstable(25mV,
SENSE(MAX)
45mV, or 68mV, depending on the state of the I pin).
To maintain a good signal to noise ratio for the current
LIM
sense signal, use a minimum ∆V
of 10mV for duty
cycles less than 40%. For a DCR sensing application, the
actual ripple voltage will be determined by the equation:
SENSE
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of resistance, which is approximately 0.4%/°C
oruseLTC3855DCRtemperaturecompensationfunction.
V − VOUT VOUT
IN
∆VSENSE
=
R1•C1 V • fOSC
IN
A conservative value for T
is 100°C.
L(MAX)
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
NTC Compensated DCR Sensing
For DCR sensing applications where a more accurate
current limit is required, a network consisting of an NTC
thermistor placed from the ITEMP pin to ground will
provide correction of the current limit over temperature.
RSENSE(EQUIV)
RD =
DCR(MAX) at TL(MAX)
Figure 2b shows this network. Resistors R and R will
S
P
C1 is usually selected to be in the range of 0.047µF to
0.47µF. This forces R1||R2 to around 2kΩ, reducing error
that might have been caused by the SENSE pins’ 1µA
linearize the impedance the ITEMP pin sees. To implement
NTC compensated DCR sensing, design the DCR sense
filter network per the same procedure mentioned in the
previousselection,exceptcalculatethedividercomponents
using the room temperature value of the DCR. For a single
output rail operating from one phase:
current. T
is the maximum inductor temperature.
L(MAX)
The equivalent resistance R1||R2 is scaled to the room
temperature inductance and maximum DCR:
L
R1||R2=
1. Set the ITEMP pin resistance to 50k at 25°C. With
10µA flowing out of the ITEMP pin, the voltage on the
ITEMP pin will be 0.5V at room temperature. Current
limit correction will occur for inductor temperatures
greater than 25°C.
(DCR at 20°C) • C1
The sense resistor values are:
R1||R2
RD
R1• RD
1−RD
R1=
; R2=
2. Calculate the ITEMP pin resistance and the maximum
inductor temperature which is typically 100°C. Use the
following equations:
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
3855f
ꢀꢇ
LTC3855
applicaTions inForMaTion
After determining the components for the temperature
compensation network, check the results by plotting
MAX
V
ITEMP100C
10µA
RITEMP100C
=
I
versus inductor temperature using the following
equations:
VITEMP100C = 0.5V −1.3•
IMAX
=
IMAX •DCR(MAX)•R2
R1+R2
(100°C− 25°C)•0.4
•
VSENSEMAX(ADJ) − ∆VSENSE
100
VSENSE(MAX)
2
0.4
100
DCR(MAX) at 25°C• 1+ T
− 25°C •
Calculate the values for R and R . A simple method is to
L(MAX)
P
S
graph the following R versus R equations with R on
S
P
S
the y-axis and R on the x-axis.
P
where
VSENSEMAX(ADJ) = VSENSE(MAX)
R = R
– R ||R
NTC25C P
S
ITEMP25C
1.8V − V
ITEMP
•
− A
R = R
– R ||R
NTC100C P
1.3
S
ITEMP100C
Next, find the value of R that satisfies both equations
P
V
= 10µA • (R + R ||R
)
ITEMP
S
P
NTC
which will be the point where the curves intersect. Once
Use typical values for V
A will provide a minimum value for V
values are summarized in Table 2.
. Subtracting constant
SENSE(MAX)
R is known, solve for R .
P
S
. These
SENSE(MAX)
The resistance of the NTC thermistor can be obtained
from the vendor’s data sheet either in the form of graphs,
tabulated data, or formulas. The approximate value for the
NTC thermistor for a given temperature can be calculated
from the following equation:
Table 2ꢀ
I
GND
30mV
5mV
FLꢂAT
INT6
CC
LIM
V
A
TYP
50mV
5mV
75mV
7mV
SENSE(MAX)
1
1
R=RO •exp B•
−
T + 273 T + 273
The resulting current limit should be greater than or
equal to I for inductor temperatures between 25°C
and 100°C.
O
MAX
where
R = Resistance at temperature T, which is in degrees C
R = Resistance at temperature T , typically 25°C
Typical values for the NTC compensation network are:
• NTC R = 100k, B-constant = 3000 to 4000
O
O
O
B = B-constant of the thermistor
• R ≈ 20k
S
Figure5showsatypicalresistancecurvefora100ktherm-
istor and the ITEMP pin network over temperature.
• R ≈ 50k
P
GeneratingtheI
versusinductortemperaturecurveplot
MAX
Starting values for the NTC compensation network are:
first using the above values as a starting point and then
adjusting the R and R values as necessary is another
S
P
• NTC R = 100k
O
approach. Figure 6 shows a typical curve of I
versus
MAX
• R = 20k
S
inductor temperature. For PolyPhase applications, tie the
ITEMP pins together and calculate for an ITEMP pin cur-
rent of 10µA • #phases.
• R = 50k
P
But, the final values should be calculated using the above
equations and checked at 25°C and 100°C.
The same thermistor network can be used to correct for
temperatures less than 25°C. But make sure V
is
ITEMP
3855f
ꢀꢈ
LTC3855
applicaTions inForMaTion
10000
25
20
15
10
5
THERMISTOR RESISTANCE
R
= 100k, T = 25°C
O
O
1000
100
10
B = 4334 for 25°C/100°C
CORRECTED I
MAX
NOMINAL I
MAX
UNCORRECTED I
MAX
RITMP
R
R
= 20kΩ
S
P
R
S
R
P
= 20kΩ
= 43.2kΩ
= 43.2kΩ
NTC THERMISTOR:
= 100k
= 25°C
100k NTC
R
O
O
T
B = 4334
1
0
–40 –20
0
20 40 60 80 100 120
–40 –20
0
20 40 60 80 100 120
INDUCTOR TEMPERATURE (°C)
INDUCTOR TEMPERATURE (°C)
3855 F05
3855 F06
Figure 5ꢀ Resistance 6ersus Temperature for
ITEMP Pin Network and the 100k NTC
Figure ꢁꢀ Worst Case IMAX 6ersus Inductor Temperature
Curve with and without NTC Temperature Compensation
greater than 0.2V for duty cycles of 25% or more, oth-
erwise temperature correction may not occur at elevated
ambients. For the most accurate temperature detection,
place the thermistors next to the inductors as shown in
Figure 7. Take care to keep the ITEMP pins away from the
switch nodes.
maximum inductor peak current to remain unaffected
throughout all duty cycles.
Inductor 6alue Calculation
Given the desired input and output voltages, the inductor
value and operating frequency f
directly determine the
OSC
inductor’s peak-to-peak ripple current:
Slope Compensation and Inductor Peak Current
VOUT V – VOUT
IN
Slope compensation provides stability in constant-
frequencyarchitecturesbypreventingsubharmonicoscil-
lations at high duty cycles. It is accomplished internally by
addingacompensatingramptotheinductorcurrentsignal
at duty cycles in excess of 40%. Normally, this results in
a reduction of maximum inductor peak current for duty
cycles >40%. However, the LTC3855 uses a scheme that
counteracts this compensating ramp, which allows the
IRIPPLE
=
V
fOSC •L
IN
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
CONNECT TO
ITEMP1
CONNECT TO
ITEMP2
NETWORK
NETWORK
V
V
V
OUT
OUT1
L1
OUT2
L2
R
NTC1
R
NTC2
R
NTC
L1
L2
GND
GND
SW1
SW2
SW1
SW2
3855 F07a
3855 F07b
(.a) Dual ꢂutput Dual Phase DCR Sensing Application
(.b) Single ꢂutput Dual Phase DCR Sensing Application
Figure .ꢀ Thermistor Locationsꢀ Place Thermistor Next to Inductor(s) for Accurate Sensing of the Inductor
Temperature, but Keep the ITEMP Pins Away from the Switch Nodes and Gate Drive Traces
3855f
ꢁ0
LTC3855
applicaTions inForMaTion
A reasonable starting point is to choose a ripple current
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
that is about 40% of I
for a duty cycle less than
OUT(MAX)
40%. Note that the largest ripple current occurs at the
highestinputvoltage.Toguaranteethatripplecurrentdoes
not exceed a specified maximum, the inductor should be
chosen according to:
Power MꢂSFET and Schottky Diode
(ꢂptional) Selection
VIN – VOUT VOUT
fOSC •IRIPPLE VIN
L ≥
•
Two external power MOSFETs must be selected for each
controller in the LTC3855: one N-channel MOSFET for the
top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
For duty cycles greater than 40%, the 10mV current
sense ripple voltage requirement is relaxed because the
slope compensation signal aids the signal-to-noise ratio
and because a lower limit is placed on the inductor value
to avoid subharmonic oscillations. To ensure stability for
duty cycles up to the maximum of 95%, use the following
equation to find the minimum inductance.
The peak-to-peak drive levels are set by the INTV
CC
voltage. This voltage is typically 5V during start-up
(see EXTV Pin Connection). Consequently, logic-level
CC
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected (V
IN
VOUT
fSW •ILOAD(MAX)
LMIN
>
•1.4
< 5V); then, sub-logic level threshold MOSFETs (V
GS(TH)
< 3V) should be used. Pay close attention to the BV
DSS
specification for the MOSFETs as well; most of the logic
level MOSFETs are limited to 30V or less.
where
L
f
is in units of µH
MIN
Selection criteria for the power MOSFETs include the
is in units of MHz
on-resistance R
, Miller capacitance C , input
MILLER
SW
DS(ON)
voltage and maximum output current. Miller capacitance,
, can be approximated from the gate charge curve
Inductor Core Selection
C
MILLER
usually provided on the MOSFET manufacturers’ data
sheet. C is equal to the increase in gate charge
Once the inductance value is determined, the type of in-
ductor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
MILLER
along the horizontal axis while the curve is approximately
flat divided by the specified change in V . This result is
DS
then multiplied by the ratio of the application applied V
DS
to the gate charge curve specified V . When the IC is
DS
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
VOUT
Main SwitchDuty Cycle=
V
IN
V – VOUT
IN
Synchronous SwitchDuty Cycle=
V
IN
3855f
ꢁꢀ
LTC3855
applicaTions inForMaTion
The MOSFET power dissipations at maximum output
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance. A Schottky diode in parallel with the bottom
FET may also provide a modest improvement in Burst
Mode efficiency.
current are given by:
VOUT
2
PMAIN
=
(
I
1+d R
+
DS(ON)
(
MAX ) (
)
V
IN
I
2 MAX
V
R
DR)(
C
•
)
(
)
IN
MILLER
Soft-Start and Tracking
2
1
The LTC3855 has the ability to either soft-start by itself
with a capacitor or track the output of another channel or
externalsupply.Whenoneparticularchannelisconfigured
to soft-start by itself, a capacitor should be connected to
its TK/SS pin. This channel is in the shutdown state if its
RUN pin voltage is below 1.2V. Its TK/SS pin is actively
pulled to ground in this shutdown state.
1
+
• fOSC
VINTVCC – VTH(MIN)
V
TH(MIN)
V – VOUT
2
IN
PSYNC
=
I
1+d R
(
MAX ) (
)
DS(ON)
V
IN
Once the RUN pin voltage is above 1.2V, the channel pow-
ers up. A soft-start current of 1.2µA then starts to charge
its soft-start capacitor. Note that soft-start or tracking is
achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
according to the ramp rate on the TK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
defined to be the voltage range from 0V to 0.6V on the
TK/SS pin. The total soft-start time can be calculated as:
where d is the temperature dependency of R
DR
and
DS(ON)
R
(approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. V
is the
TH(MIN)
typical MOSFET minimum threshold voltage.
2
BothMOSFETshaveI RlosseswhilethetopsideN-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V < 20V
IN
the high current efficiency generally improves with larger
MOSFETs, while for V > 20V the transition losses rapidly
IN
increasetothepointthattheuseofahigherR
device
DS(ON)
CSS
tSOFTSTART = 0.6 •
1.2µA
withlowerC
actuallyprovideshigherefficiency.The
MILLER
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
Regardless of the mode selected by the MODE/PLLIN pin,
the regulator will always start in pulse-skipping mode
up to TK/SS = 0.5V. Between TK/SS = 0.5V and 0.54V, it
will operate in forced continuous mode and revert to the
selected mode once TK/SS > 0.54V. The output ripple
is minimized during the 40mV forced continuous mode
window ensuring a clean PGOOD signal.
The term (1 + d) is generally given for a MOSFET in the
form of a normalized R
vs Temperature curve, but
DS(ON)
d = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
TheoptionalSchottkydiodesconductduringthedeadtime
betweentheconductionofthetwopowerMOSFETs.These
preventthebodydiodesofthebottomMOSFETsfromturn-
ing on, storing charge during the dead time and requiring
a reverse recovery period that could cost as much as 3%
When the channel is configured to track another supply,
the feedback voltage of the other supply is duplicated by
a resistor divider and applied to the TK/SS pin. Therefore,
the voltage ramp rate on this pin is determined by the
ramp rate of the other supply’s voltage. Note that the small
soft-start capacitor charging current is always flowing,
in efficiency at high V . A 1A to 3A Schottky is generally
IN
a good compromise for both regions of operation due to
3855f
ꢁꢁ
LTC3855
applicaTions inForMaTion
producingasmalloffseterror.Tominimizethiserror,select
the tracking resistive divider value to be small enough to
make this error negligible.
To implement the coincident tracking in Figure 8a, con-
nect an additional resistive divider to V
and connect
OUT1
its midpoint to the TK/SS pin of the slave channel. The
ratio of this divider should be the same as that of the slave
channel’s feedback divider shown in Figure 9a. In this
In order to track down another channel or supply after
the soft-start phase expires, the LTC3855 is forced into
tracking mode, V
must be set higher than V . To
OUT2
OUT1
continuous mode of operation as soon as V is below the
FB
implementtheratiometrictrackinginFigure9b,theratioof
theV dividershouldbeexactlythesameasthemaster
undervoltage threshold of 0.54V regardless of the setting
on the MODE/PLLIN pin. However, the LTC3855 should
always be set in force continuous mode tracking down
when there is no load. After TK/SS drops below 0.1V, its
channel will operate in discontinuous mode.
OUT2
channel’s feedback divider shown in Figure 9b. By select-
ing different resistors, the LTC3855 can achieve different
modes of tracking including the two in Figure 8.
So which mode should be programmed? While either
mode in Figure 8 satisfies most practical applications,
some tradeoffs exist. The ratiometric mode saves a pair
of resistors, but the coincident mode offers better output
regulation.
ꢂutput 6oltage Tracking
The LTC3855 allows the user to program how its output
ramps up and down by means of the TK/SS pins. Through
thesepins, theoutputcanbesetuptoeithercoincidentally
or ratiometrically track another supply’s output, as shown
When the master channel’s output experiences dynamic
excursion (under load transient, for example), the slave
channel output will be affected as well. For better output
regulation, use the coincident tracking mode instead of
ratiometric.
in Figure 8. In the following discussions, V
refers to
OUT1
the LTC3855’s output 1 as a master channel and V
OUT2
refers to the LTC3855’s output 2 as a slave channel. In
practice, though, either phase can be used as the master.
V
V
OUT1
OUT1
V
V
OUT2
OUT2
3855 F08b
TIME
TIME
3855 F08a
(8a) Coincident Tracking
(8b) Ratiometric Tracking
Figure 8ꢀ Two Different Modes of ꢂutput 6oltage Tracking
V
OUT1
V
OUT1
V
OUT2
V
OUT2
R3
R4
R1
R2
R3
R4
R1
R2
R3
R4
TO
TK/SS2
PIN
TO
TK/SS2
PIN
TO
FB1
PIN
TO
FB2
PIN
TO
FB2
PIN
TO
V
V
V
V
FB1
PIN
3855 F09
(9a) Coincident Tracking Setup
(9b) Ratiometric Tracking Setup
Figure 9ꢀ Setup for Coincident and Ratiometric Tracking
3855f
ꢁꢂ
LTC3855
applicaTions inForMaTion
INT6 Regulators and EXT6
from the INTV when the output is out of regulation
CC
CC
CC
(e.g., start-up, short-circuit). If more current is required
The LTC3855 features a true PMOS LDO that supplies
power to INTV from the V supply. INTV powers the
throughtheEXTV thanisspecified, anexternalSchottky
CC
CC
IN
CC
diode can be added between the EXTV and INTV pins.
CC
CC
gate drivers and much of the LTC3855’s internal circuitry.
ThelinearregulatorregulatesthevoltageattheINTV pin
Do not apply more than 6V to the EXTV pin and make
CC
CC
sure that EXTV < V .
CC
IN
to 5V when V is greater than 5.5V. EXTV connects to
IN
CC
INTV through a P-channel MOSFET and can supply the
Significant efficiency and thermal gains can be realized by
powering INTV from the output, since the V current
CC
needed power when its voltage is higher than 4.7V. Each
of these can supply a peak current of 100mA and must
be bypassed to ground with a minimum of 4.7µF ceramic
capacitor or low ESR electrolytic capacitor. No matter
what type of bulk capacitor is used, an additional 0.1µF
CC
IN
resultingfromthedriverandcontrolcurrentswillbescaled
by a factor of (Duty Cycle)/(Switcher Efficiency).
Tying the EXTV pin to a 5V supply reduces the junction
CC
temperature in the previous example from 125°C to:
ceramic capacitor placed directly adjacent to the INTV
CC
and PGND pins is highly recommended. Good bypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers and to prevent interaction
between the channels.
T = 70°C + (44mA)(5V)(33°C/W) = 77°C
J
However, for 3.3V and other low voltage outputs, addi-
tional circuitry is required to derive INTV power from
CC
the output.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3855 to be
The following list summarizes the four possible connec-
tions for EXTV :
CC
1. EXTV left open (or grounded). This will cause
exceeded. The INTV current, which is dominated by the
CC
CC
INTV to be powered from the internal 5V regulator
gatechargecurrent,maybesuppliedbyeitherthe5Vlinear
CC
resulting in an efficiency penalty of up to 10% at high
input voltages.
regulator or EXTV . When the voltage on the EXTV pin
CC
CC
is less than 4.7V, the linear regulator is enabled. Power
dissipation for the IC in this case is highest and is equal
2. EXTV connected directly to V . This is the
CC
OUT
to V • I
. The gate charge current is dependent
IN
INTVCC
normal connection for a 5V regulator and provides
the highest efficiency.
on operating frequency as discussed in the Efficiency
Considerations section. The junction temperature can be
estimated by using the equations given in Note 3 of the
3. EXTV connected to an external supply. If a 5V
CC
external supply is available, it may be used to power
ElectricalCharacteristics.Forexample,theLTC3855INTV
CC
EXTV providing it is compatible with the MOSFET
current is limited to less than 44mA from a 38V supply in
CC
gate drive requirements.
the UJ package and not using the EXTV supply:
CC
4. EXTV connected to an output-derived boost net-
T = 70°C + (44mA)(38V)(33°C/W) = 125°C
CC
J
work. For 3.3V and other low voltage regulators,
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operatingincontinuousconductionmode(MODE/PLLIN=
efficiency gains can still be realized by connecting
EXTV to an output-derived voltage that has been
CC
boosted to greater than 4.7V.
SGND) at maximum V . When the voltage applied to EXT-
IN
For applications where the main input power is below 5V,
tie the V and INTV pins together and tie the combined
V
rises above 4.7V, the INTV linear regulator is turned
CC
CC
offandtheEXTV isconnectedtotheINTV .TheEXTV
IN
CC
CC
CC
CC
pins to the 5V input with a 1Ω or 2.2Ω resistor as shown
remainsonaslongasthevoltageappliedtoEXTV remains
CC
in Figure 10 to minimize the voltage drop caused by the
above 4.5V. Using the EXTV allows the MOSFET driver
CC
gate charge current. This will override the INTV linear
andcontrolpowertobederivedfromoneoftheLTC3855’s
CC
regulator and will prevent INTV from dropping too low
switching regulator outputs during normal operation and
CC
3855f
ꢁꢃ
LTC3855
applicaTions inForMaTion
due to the dropout voltage. Make sure the INTV voltage
Another way to detect an undervoltage condition is to
CC
is at or exceeds the R
test voltage for the MOSFET
monitor the V supply. Because the RUN pins have a
DS(ON)
IN
which is typically 4.5V for logic level devices.
precision turn-on reference of 1.2V, one can use a resistor
divider to V to turn on the IC when V is high enough.
IN
IN
An extra 4.5µA of current flows out of the RUN pin once
the RUN pin voltage passes 1.2V. One can program the
hysteresis of the run comparator by adjusting the values
V
IN
LTC3855
INTV
R
VIN
5V
CC
of the resistive divider. For accurate V undervoltage
1Ω
IN
CINTV
4.7µF
CC
+
detection, V needs to be higher than 4.5V.
C
IN
IN
C and C
Selection
3855 F07
IN
ꢂUT
Figure 10ꢀ Setup for a 56 Input
The selection of C is simplified by the 2-phase architec-
IN
ture and its impact on the worst-case RMS current drawn
throughtheinputnetwork(battery/fuse/capacitor).Itcanbe
shown that the worst-case capacitor RMS current occurs
when only one controller is operating. The controller with
Topside MꢂSFET Driver Supply (C , DB)
B
External bootstrap capacitors C connected to the BOOST
B
pinssupplythegatedrivevoltagesforthetopsideMOSFETs.
the highest (V )(I ) product needs to be used in the
Capacitor C in the Functional Diagram is charged though
OUT OUT
B
formula below to determine the maximum RMS capacitor
current requirement. Increasing the output current drawn
from the other controller will actually decrease the input
RMS ripple current from its maximum value. The out-of-
phasetechniquetypicallyreducestheinputcapacitor’sRMS
ripple current by a factor of 30% to 70% when compared
to a single phase power supply solution.
external diode DB from INTV when the SW pin is low.
CC
When one of the topside MOSFETs is to be turned on,
the driver places the C voltage across the gate source
B
of the desired MOSFET. This enhances the MOSFET and
turns on the topside switch. The switch node voltage, SW,
rises to V and the BOOST pin follows. With the topside
IN
MOSFET on, the boost voltage is above the input supply:
V
B
= V + V
. The value of the boost capacitor
BOOST
IN
INTVCC
Incontinuousmode,thesourcecurrentofthetopMOSFET
C needs to be 100 times that of the total input capa-
is a square wave of duty cycle (V )/(V ). To prevent
OUT
IN
citance of the topside MOSFET(s). The reverse break-
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
down of the external Schottky diode must be greater
than V
. When adjusting the gate drive level, the
IN(MAX)
final arbiter is the total input current for the regulator. If
a change is made and the input current decreases, then
the efficiency has improved. If there is no change in input
current, then there is no change in efficiency.
IMAX
1/2
CIN Required IRMS
≈
V
OUT )(
V – V
IN OUT
(
)
V
IN
This formula has a maximum at V = 2V , where I
OUT
=
IN
OUT
RMS
I
/2.Thissimpleworst-caseconditioniscommonlyused
Undervoltage Lockout
for design because even significant deviations do not of-
fer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3855, ceramic capacitors
The LTC3855 has two functions that help protect the
controller in case of undervoltage conditions. A precision
UVLOcomparatorconstantlymonitorstheINTV voltage
CC
to ensure that an adequate gate-drive voltage is present. It
locks out the switching action when INTV is below 3.2V.
CC
To prevent oscillation when there is a disturbance on the
INTV , the UVLO comparator has 600mV of precision
CC
hysteresis.
3855f
ꢁꢄ
LTC3855
applicaTions inForMaTion
can also be used for C . Always consult the manufacturer
output, as shown in Figure 11. The regulated output
voltage is determined by:
IN
if there is any question.
The benefit of the LTC3855 2-phase operation can be cal-
culated by using the equation above for the higher power
controller and then calculating the loss that would have
resultedifbothcontrollerchannelsswitchedonatthesame
time.ThetotalRMSpowerlostislowerwhenbothcontrol-
lers are operating due to the reduced overlap of current
pulses required through the input capacitor’s ESR. This is
whytheinputcapacitor’srequirementcalculatedabovefor
theworst-casecontrollerisadequateforthedualcontroller
design. Also, the input protection fuse resistance, battery
resistance, and PC board trace resistance losses are also
reduced due to the reduced peak currents in a 2-phase
system. The overall benefit of a multiphase design will
only be fully realized when the source impedance of the
power supply/battery is included in the efficiency testing.
The sources of the top MOSFETs should be placed within
RB
R
VOUT = 0.6V • 1+
A
To improve the frequency response, a feed-forward ca-
pacitor, C , may be used. Great care should be taken to
FF
route the V line away from noise sources, such as the
FB
inductor or the SW line.
V
OUT
R
C
FF
B
A
1/2 LTC3855
V
FB
R
3855 F11
Figure 11ꢀ Setting ꢂutput 6oltage
1cmofeachotherandshareacommonC (s). Separating
IN
Fault Conditions: Current Limit and Current Foldback
the sources and C may produce undesirable voltage and
IN
current resonances at V .
The LTC3855 includes current foldback to help limit load
current when the output is shorted to ground. If the out-
put falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from its
maximumprogrammedvaluetoone-thirdofthemaximum
value. Foldback current limiting is disabled during the
soft-start or tracking up. Under short-circuit conditions
with very low duty cycles, the LTC3855 will begin cycle
skipping in order to limit the short-circuit current. In this
situation the bottom MOSFET will be dissipating most of
the power but less than in normal operation. The short-
circuit ripple current is determined by the minimum on-
IN
A small (0.1µF to 1µF) bypass capacitor between the chip
V pin and ground, placed close to the LTC3855, is also
IN
suggested. A 2.2Ω to 10Ω resistor placed between C
IN
(C1) and the V pin provides further isolation between
IN
the two channels.
The selection of C
is driven by the effective series
OUT
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆V ) is approximated by:
OUT
1
time t
of the LTC3855 (≈ 90ns), the input voltage
and inductor value:
ON(MIN)
∆VOUT ≈IRIPPLE ESR+
8fC
OUT
V
L
IN
∆IL(SC) = tON(MIN)
•
where f is the operating frequency, C
is the output
OUT
capacitance and I
is the ripple current in the induc-
RIPPLE
tor. The output ripple is highest at maximum input voltage
since I increases with input voltage.
The resulting short-circuit current is:
RIPPLE
1/3 VSENSE(MAX)
1
ISC =
– ∆IL(SC)
Setting ꢂutput 6oltage
RSENSE
2
The LTC3855 output voltages are each set by an external
feedback resistive divider carefully placed across the
3855f
ꢁꢅ
LTC3855
applicaTions inForMaTion
Phase-Locked Loop and Frequency Synchronization
The LTC3855 has a phase-locked loop (PLL) comprised of
900
800
700
600
500
400
300
200
100
0
an internal voltage-controlled oscillator (V ) and a phase
CO
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the MODE/PLLIN pin. The turn-on
of controller 2’s top MOSFET is thus 180 degrees out-
of-phase with the external clock. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
0
0.5
1
1.5
2
2.5
FREQ PIN VOLTAGE (V)
3855 F12
Figure 12ꢀ Relationship Between ꢂscillator
Frequency and 6oltage at the FREQ Pin
Theoutputofthephasedetectorisapairofcomplementary
current sources that charge or discharge the internal filter
network. There is a precision 10µA of current flowing out
of FREQ pin. This allows the user to use a single resistor
to SGND to set the switching frequency when no external
clockisappliedtotheMODE/PLLINpin.Theinternalswitch
between FREQ pin and the integrated PLL filter network
is ON, allowing the filter network to be pre-charged to the
same voltage potential as the FREQ pin. The relationship
between the voltage on the FREQ pin and the operating
frequency is shown in Figure 12 and specified in the Elec-
trical Characteristic table. If an external clock is detected
on the MODE/PLLIN pin, the internal switch mentioned
above will turn off and isolate the influence of FREQ pin.
Note that the LTC3855 can only be synchronized to an
external clock whose frequency is within range of the
2.4V 5V
10µA
R
SET
FREQ
MODE/
PLLIN
DIGITAL
PHASE/
FREQUENCY
DETECTOR
SYNC
EXTERNAL
OSCILLATOR
VCO
3855 F13
Figure 13ꢀ Phase-Locked Loop Block Diagram
Typically, the external clock (on MODE/PLLIN pin)
input high threshold is 1.6V, while the input low threshold
is 1V. It is not recommended to apply the external clock
when IC is in shutdown.
LTC3855’s internal V . This is guaranteed to be between
CO
250kHz and 770kHz. A simplified block diagram is shown
in Figure 13.
If the external clock frequency is greater than the internal
Minimum ꢂn-Time Considerations
oscillator’s frequency, f , then current is sourced continu-
OSC
Minimum on-time t
is the smallest time duration
ON(MIN)
ously from the phase detector output, pulling up the filter
that the LTC3855 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
network.Whentheexternalclockfrequencyislessthanf
,
OSC
currentissunkcontinuously,pullingdownthefilternetwork.If
theexternalandinternalfrequenciesarethesamebutexhibit
aphasedifference,thecurrentsourcesturnonforanamount
oftimecorrespondingtothephasedifference.Thevoltageon
thefilternetworkisadjusteduntilthephaseandfrequencyof
theinternalandexternaloscillatorsareidentical.Atthestable
operatingpoint,thephasedetectoroutputishighimpedance
and the filter capacitor holds the voltage.
VOUT
tON(MIN)
<
V (f)
IN
3855f
ꢁꢆ
LTC3855
applicaTions inForMaTion
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
from INTV to ground. The resulting dQ/dt is a cur-
CC
rent out of INTV that is typically much larger than the
CC
control circuit current. In continuous mode, I
GATECHG
= f(Q + Q ), where Q and Q are the gate charges of
T
B
T
B
the topside and bottom side MOSFETs.
The minimum on-time for the LTC3855 is approximately
90ns, with reasonably good PCB layout, minimum 30%
inductor current ripple and at least 10mV – 15mV ripple
on the current sense signal. The minimum on-time can be
affected by PCB switching noise in the voltage and current
loop. As the peak sense voltage decreases the minimum
on-time gradually increases to 130ns. This is of particular
concern in forced continuous applications with low ripple
current at light loads. If the duty cycle drops below the
minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
Supplying INTV power through EXTV from an out-
CC
CC
put-derived source will scale the V current required
IN
for the driver and control circuits by a factor of (Duty
Cycle)/(Efficiency). Forexample, ina20Vto5Vapplica-
tion, 10mA of INTV current results in approximately
CC
2.5mAofV current.Thisreducesthemid-currentloss
IN
from 10% or more (if the driver was powered directly
from V ) to only a few percent.
IN
2
3. I R losses are predicted from the DC resistances of the
fuse(ifused), MOSFET, inductor, currentsenseresistor.
In continuous mode, the average output current flows
through L and R , but is “chopped” between the
SENSE
Efficiency Considerations
topside MOSFET and the synchronous MOSFET. If the
two MOSFETs have approximately the same R
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
,
DS(ON)
then the resistance of one MOSFET can simply be
summed with the resistances of L and R
to ob-
SENSE
2
tain I R losses. For example, if each R
= 10mΩ,
DS(ON)
R = 10mΩ, R
= 5mΩ, then the total resistance
L
SENSE
is 25mΩ. This results in losses ranging from 2% to
8% as the output current increases from 3A to 15A for
a 5V output, or a 3% to 12% loss for a 3.3V output.
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Efficiency varies as the inverse square of V
for the
OUT
sameexternalcomponentsandoutputpowerlevel. The
combined effects of increasingly lower output voltages
andhighercurrentsrequiredbyhighperformancedigital
systemsisnotdoublingbutquadruplingtheimportance
of loss terms in the switching regulator system!
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3855 circuits: 1) IC V current, 2) INTV
IN
CC
2
regulator current, 3) I R losses, 4) Topside MOSFET
transition losses.
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
1. The V current is the DC supply current given in
IN
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. V current typi-
IN
cally results in a small (<0.1%) loss.
2
Transition Loss = (1.7) V
I
C
f
IN O(MAX) RSS
2. INTV current is the sum of the MOSFET driver and
CC
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
3855f
ꢁꢇ
LTC3855
applicaTions inForMaTion
losses can be minimized by making sure that C has
The I series R -C filter sets the dominant pole-zero
TH C C
IN
adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a
minimum of 20µF to 40µF of capacitance having
a maximum of 20mΩ to 50mΩ of ESR. The LTC3855
2-phasearchitecturetypicallyhalvesthisinputcapacitance
requirement over competing solutions. Other losses
including Schottky conduction losses during dead time
and inductor core losses generally account for less than
2% total additional loss.
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1µs to 10µs will
produce output voltage and I pin waveforms that will
TH
give a sense of the overall loop stability without break-
ing the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
Modest improvements in Burst Mode efficiency may be
realized by using a smaller inductor value, a lower switch-
ingfrequencyorforDCRsensingapplications, makingthe
DCR filter’s time constant smaller than the L/DCR time
constant for the inductor. A small Schottky diode with a
current rating equal to about 20% of the maximum load
current or less may yield minor improvements, too.
is why it is better to look at the I pin signal which is in
Checking Transient Response
TH
the feedback loop and is the filtered and compensated
control loop response. The gain of the loop will be in-
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
creased by increasing R and the bandwidth of the loop
C
will be increased by decreasing C . If R is increased by
C
C
load current. When a load step occurs, V
shifts by an
OUT
the same factor that C is decreased, the zero frequency
C
amount equal to ∆I
(ESR), where ESR is the effective
LOAD
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
series resistance of C . ∆I
also begins to charge or
generating the feedback error signal that
OUT
LOAD
discharge C
OUT
forces the regulator to adapt to the current change and
return V to its steady-state value. During this recovery
OUT
time V
can be monitored for excessive overshoot or
OUT
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
ringing, which would indicate a stability problem. The
availability of the I pin not only allows optimization of
TH
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
order system, phasemarginand/or dampingfactorcanbe
estimated using the percentage of overshoot seen at this
pin.Thebandwidthcanalsobeestimatedbyexaminingthe
with C , causing a rapid drop in V . No regulator can
OUT
OUT
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
is greater than 1:50, the switch rise time
OUT
should be controlled so that the load rise time is limited
to approximately 25 • C . Thus a 10µF capacitor would
rise time at the pin. The I external components shown
TH
LOAD
in the Typical Application circuit will provide an adequate
require a 250µs rise time, limiting the charging current
to about 200mA.
starting point for most applications.
3855f
ꢁꢈ
LTC3855
applicaTions inForMaTion
PC Board Layout Checklist
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), andboostnodes(BOOST1, BOOST2)away
from sensitive small-signal nodes, especially from the
opposite channel’s voltage and current sensing feed-
back pins. All of these nodes have very large and fast
moving signals and therefore should be kept on the
“output side” of the LTC3855 and occupy minimum
PC trace area. If DCR sensing is used, place the top
resistor (Figure 2b, R1) close to the switching node.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 14. Figure 15 illustrates the
current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1 cm of each other with a common drain con-
7. AreDIFFPandDIFFNleadsroutedtogetherandcorrectly
Kelvin sensing the output voltage?
nection at C ? Do not attempt to split the input de-
IN
coupling for the two channels as it can cause a large
8. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
capacitors with tie-ins for the bottom of the INTV
CC
decouplingcapacitor,thebottomofthevoltagefeedback
of C
must return to the combined C
(–) ter-
INTVCC
OUT
resistive divider and the SGND pin of the IC.
minals. The V and I traces should be as short as
FB
TH
possible.ThepathformedbythetopN-channelMOSFET,
Schottky diode and the C capacitor should have short
PC Board Layout Debugging
IN
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
totheinternaloscillatorandprobetheactualoutputvoltage
as well. Check for proper performance over the operating
voltage and current range expected in the application.
The frequency of operation should be maintained over
the input voltage range down to dropout and until the
output load drops below the low current operation
threshold—typically 10% of the maximum designed cur-
rent level in Burst Mode operation.
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Do the LTC3855 V pins’ resistive dividers connect to
FB
the (+) terminals of C ? The resistive divider must be
OUT
connected between the (+) terminal of C
and signal
OUT
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
+
–
4. Are the SENSE and SENSE leads routed together with
minimumPCtracespacing?Thefiltercapacitorbetween
The duty cycle percentage should be maintained from
cycletocycleinawell-designed,lownoisePCBimplemen-
tation. Variation in the duty cycle at a subharmonic rate
can suggest noise pickup at the current or voltage sensing
inputs or inadequate loop compensation. Overcompensa-
tion of the loop can be used to tame a poor PC layout if
regulatorbandwidthoptimizationisnotrequired.Onlyafter
each controller is checked for its individual performance
should both controllers be turned on at the same time.
A particularly difficult region of operation is when one
controller channel is nearing its current comparator trip
pointwhentheotherchannelisturningonitstopMOSFET.
3855f
+
–
SENSE and SENSE should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connectionsatthesenseresistororinductor,whichever
is used for current sensing.
5. Is the INTV decoupling capacitor connected close to
CC
theIC, betweentheINTV andthepowergroundpins?
CC
ThiscapacitorcarriestheMOSFETdriverscurrentpeaks.
Anadditional1µFceramiccapacitorplacedimmediately
next to the INTV and PGND pins can help improve
CC
noise performance substantially.
ꢂ0
LTC3855
applicaTions inForMaTion
R
TK/SS1
PU2
CLKOUT
V
PULL-UP
PGOOD
I
PGOOD
DIFFP
TH1
LTC3855
V
FB1
DIFFN
L1
R
SENSE
D1
DIFFOUT
TG1
+
–
V
OUT1
SENSE1
SENSE1
FREQ
SW1
BOOST1
BG1
C
B1
M1
M2
I
LIM
1µF
CERAMIC
f
IN
MODE/PLLIN
RUN1
C
C
OUT1
V
IN
R
IN
C
VIN
PGND
RUN2
V
GND
IN
EXTV
CC
C
IN
SGND
C
INTVCC
–
INTV
SENSE2
CC
OUT2
D2
1µF
CERAMIC
+
BG2
SENSE2
M4
M3
BOOST2
V
FB2
TH2
C
B2
SW2
TG2
I
R
SENSE
V
OUT2
TK/SS2
L2
3855 F14
Figure 14ꢀ Recommended Printed Circuit Layout Diagram
SW1
L1
R
SENSE1
V
OUT1
D1
C
R
L1
OUT1
V
IN
R
IN
C
IN
SW2
L2
R
SENSE2
V
OUT2
D2
C
R
L2
OUT2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
3855 F15
Figure 15ꢀ Branch Current Waveforms
3855f
ꢂꢀ
LTC3855
applicaTions inForMaTion
This occurs around 50% duty cycle on either channel due
to the phasing of the internal clocks and may cause minor
duty cycle jitter.
input voltage:
VOUT
f • ∆IL(MAX)
VOUT
L =
1−
V
IN(MAX)
Reduce V from its nominal level to verify operation
IN
of the regulator in dropout. Check the operation of the
Channel 1 will require 0.78µH, and channel 2 will require
0.54µH. The Vishay IHLP4040DZ-01, 0.56µH inductor is
chosen for both rails. At the nominal input voltage (12V),
the ripple current will be:
undervoltage lockout circuit by further lowering V while
IN
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
VOUT
f • L
VOUT
V
IN(NOM)
∆IL(NOM)
=
1−
Channel 1 will have 6.8A (46%) ripple, and channel 2 will
have 4.8A (32%) ripple. The peak inductor current will be
the maximum DC value plus one-half the ripple current,
or 18.4A for channel 1 and 17.4A for channel 2.
Theminimumon-timeoccursonchannel2atthemaximum
V , and should not be less than 90ns:
IN
for inductive coupling between C , Schottky and the top
IN
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
VOUT
IN(MAX) f 20V(400kHz)
1.2V
tON(MIN)
=
=
=150ns
resistor value
SENSE
V
With I
floating, the equivalent R
LIM
can be calculated by using the minimum value for the
maximum current sense threshold (45mV).
Design Example
Asadesignexampleforatwochannelhighcurrentregula-
VSENSE(MIN)
tor, assume V = 12V(nominal), V = 20V(maximum),
IN
IN
RSENSE(EQUIV)
=
V
= 1.8V, V
= 1.2V, I = 15A, and f = 400kHz
∆IL(NOM)
OUT1
OUT2
MAX1,2
ILOAD(MAX)
+
(see Figure 16).
2
The regulated output voltages are determined by:
The equivalent required R
value is 2.4mΩ for chan-
SENSE
nel 1 and 2.6mΩ for channel 2. The DCR of the 0.56µH
inductor is 1.7mΩ typical and 1.8mΩ maximum for a
25°C ambient. At 100°C, the estimated maximum DCR
value is 2.3mΩ. The maximum DCR value is just slightly
RB
R
VOUT = 0.6V • 1+
A
Using 20k 1% resistors from both V nodes to ground,
FB
under the equivalent R
values. Therefore, R2 is not
SENSE
the top feedback resistors are (to the nearest 1% standard
required to divide down the signal.
value) 40.2k and 20k.
For each channel, 0.1µF is selected for C1.
The frequency is set by biasing the FREQ pin to 1V (see
Figure 12).
L
0.56µH
R1=
=
= 3.11k
The inductance values are based on a 35% maximum
ripple current assumption (5.25A for each channel). The
highest value of ripple current occurs at the maximum
(DCRMAX at 25°C)•C1 1.8mΩ •0.1µF
Choose R1 = 3.09k
3855f
ꢂꢁ
LTC3855
applicaTions inForMaTion
V
IN
4.5V TO
82µF 20V
25V
+
10µF
25V
s2
1µF
2.2Ω
4.7µF
D3
D4
V
PGOOD EXTV INTV
CC CC
IN
M1
M2
M3
M4
TG1
TG2
0.1µF
0.1µF
L1
L2
0.56µH
BOOST1
SW1
BOOST2
SW2
0.56µH
LTC3855
BG2
CLKOUT
PGND
3.09k
BG1
3.09k
1%
1%
MODE/PLLIN
I
FREQ
LIM1
I
LIM2
+
+
SENSE1
SENSE2
0.1µF
0.1µF
–
–
SENSE1
SENSE2
ITEMP2
DIFFP
DIFFN
ITEMP1
RUN2
RUN1
20k, 1%
40.2k
1%
V
OUT1
1.8V
15A
V
1.2V
15A
DIFFOUT
OUT2
V
TH1
V
TH2
FB1
FB2
I
I
1nF
1nF
TK/SS1
TK/SS2
SGND
+
+
150pF
150pF
0.1µF
C
C
OUT1
330µF
20k
1%
12.1k
1%
100k
1%
4.99k
1%
20k
1%
OUT2
330µF
0.1µF
s2
s2
3855 F16
L1, L2: VISHAY IHLP4040DZ-01, 0.56µH
M1, M3: RENESAS RJK0305DPB
M2, M4: RENESAS RJK0330DPB
Figure 1ꢁꢀ High Efficiency Dual 400kHz 1ꢀ86/1ꢀ26 Step-Down Converter
The power loss in R1 at the maximum input voltage is:
95
90
85
80
75
70
5
V
= 12V
1.8V R
SENSE
IN
(VIN(MAX) − VOUT )• VOUT
MODE = CCM
1.8V DCR SENSE
PLOSSR1=
4
3
2
1
0
R1
EFFICIENCY
The resulting power loss for R1 is 11mW for channel 1
and 7mW for channel 2.
The sum of the sense resistor and DCR is 2.5mΩ (max)
POWER LOSS
for the R
application whereas the inductor DCR for
SENSE
the DCR sense application is 1.8mΩ (max). As a result of
1.2V R
SENSE
1.2V DCR SENSE
thelowerconductionlossesfromtheswitchnodetoV
the DCR sensing application has higher efficiency.
,
OUT
0
2
4
6
8
10 12 14 16
LOAD CURRENT (A)
3855 F17
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Renesas RJK0305DPB
DCR SENSE APP: SEE FIGURE 16
SENSE
R
APP: SEE FIGURE 19
Figure 1.ꢀ DCR Sense Efficiency vs RSENSE Efficiency
3855f
ꢂꢂ
LTC3855
applicaTions inForMaTion
MOSFET results in: R
= 13mΩ (max), V
=
J
A Renesas RJK0330DPB, R
= 3.9mΩ, is chosen for
DS(ON)
DS(ON)
MILLER
2.6V, C
≅ 150pF. At maximum input voltage with T
the bottom FET. The resulting power loss is:
MILLER
(estimated) = 75°C:
20V –1.8V
2
PSYNC
=
15A •
(
)
1.8V
2
20V
PMAIN
=
15A 1+(0.005)(75°C – 25°C) •
(
)
[
]
20V
0.013Ω + 20V
1+ 0.005 • 75°C – 25°C •0.0039Ω
15A
2
2Ω 150pF •
)(
(
) (
)
(
)
P
SYNC
= 1W
2
1
1
C is chosen for an RMS current rating of at least 7.5A at
IN
+
400kHz
(
)
temperature assuming only channel 1 or 2 is on. C
is
5V – 2.6V 2.6V
= 329mW + 288mW
= 617mW
OUT
chosen with an equivalent ESR of 4.5mΩ for low output
ripple.Theoutputrippleincontinuousmodewillbehighest
at the maximum input voltage. The output voltage ripple
due to ESR is approximately:
For a 2mΩ sense resistor, a short-circuit to ground will
result in a folded back current of:
V
= R (∆I ) = 0.0045Ω • 6.8A = 31mV
ESR L P–P
ORIPPLE
Further reductions in output voltage ripple can be made
1/ 3 50mV
0.002Ω
90ns(20V)
0.56µH
(
)
1
2
ISC =
–
= 6.7A
by placing a 100µF ceramic across C .
OUT
Typical applicaTions
20k
20k
0.1µF
R
R
NTC1
100k
NTC2
49.9k
0.1µF
49.9k
63.4k
86.6k
100k
V
IN
4.5V TO
20V
+
10µF
82µF
25V
s2
24.9k
s2
M1
3.01k
RJK0305DPB
V
OUT1
0.1µF
+
2.5V
15A
L1
0.68µH
TK/SS1
TG1
BOOST1
PGND1
BG1
20k
C
OUT1
C
OUT2
1nF
100µF
6.3V
330µF
4V
I
TH1
20k
100pF
100pF
V
CMDSH-3
2.2Ω
s2
FB1
M2
SGND
RJK0330DPB
V
V
IN
FB2
LTC3855
20k
I
INTV
TH2
CC
CC
4.7µF
TK/SS2
SENSE2
SENSE2
DIFFP
EXTV
0.1µF
+
–
BG2
PGND2
15k
1nF
0.1µF
BOOST2
0.1µF
40.2k
CMDSH-3
0.1µF
M3
L2
0.68µH
RJK0305DPB
V
1.8V
15A
OUT2
+
C
C
OUT4
OUT3
M4
100k
100k
100µF
6.3V
330µF
4V
RJK0330DPB
PGOOD1
PGOOD2
3.01k
24.9k
s2
L1, L2: VISHAY IHLP5050CE-01, 0.68µH
3855 F18
C
C
, C
: MURATA GRM32ER60J107ME20
: KEMET T520V337M004ATE009
OUT1 OUT3
, C
OUT2 OUT4
RNTC1, RNTC2: MURATA NCP18WF104J03RB
Figure 18ꢀ 2ꢀ56, 15A and 1ꢀ86, 15A Supply with NTC Temperature Compensated DCR Sensing, fSW = 350kHz
3855f
ꢂꢃ
LTC3855
Typical applicaTions
100Ω
100Ω
1nF
100k
V
IN
4.5V TO
20V
+
10µF
82µF
25V
s2
40.2k
0.1µF
s2
M1
RJK0305DPB
1nF
0.002Ω
18k
V
OUT1
0.1µF
1.8V
15A
+
L1
0.4µH
TK/SS1
TG1
BOOST1
PGND1
BG1
C
OUT1
C
OUT2
100µF
6.3V
330µF
2.5V
s2
I
TH1
20k
150pF
150pF
V
CMDSH-3
2.2Ω
FB1
M2
SGND
RJK0330DPB
V
V
IN
FB2
LTC3855
20k
I
INTV
TH2
CC
CC
4.7µF
TK/SS2
EXTV
0.1µF
+
SENSE2
SENSE2
DIFFP
BG2
PGND2
5.49k
1.5nF
1nF
–
BOOST2
0.1µF
100Ω
100Ω
20k
M3
CMDSH-3
0.1µF
RJK0305DPB
L2
0.4µH
0.002Ω
V
1.2V
15A
OUT2
+
C
C
OUT4
OUT3
M4
100k
100k
100µF
6.3V
330µF
2.5V
s2
RJK0330DPB
PGOOD1
PGOOD2
L1, L2: VITEC 59PR9875
3855 F19
C
, C
: MURATA GRM31CR60J107ME39L
: SANYO 2R5TPE330M9
OUT1 OUT3
C
, C
OUT2 OUT4
Figure 19ꢀ 1ꢀ86, 15A and 1ꢀ26, 15A Supply, fSW = 400kHz
3855f
ꢂꢄ
LTC3855
Typical applicaTions
100Ω
100Ω
RUN
1nF
V
IN
250kHz
4.5V TO
14V
+
10µF
s4
270µF
16V
M1
0.001Ω
1%
RJK0305DPB
0.1µF
L1
TK/SS1
TG1
BOOST1
PGND1
BG1
0.44µH
0.1µF
I
TH1
V
CMDSH-3
2.2Ω
FB1
M2
SGND
RJK0330DPB
s2
V
V
IN
FB2
LTC3855
20k
I
INTV
TH2
CC
CC
V
1.2V
40A
OUT
4.7µF
TK/SS2
EXTV
2200pF
1nF
+
C
C
OUT2
OUT1
0.1µF
+
SENSE2
SENSE2
DIFFP
BG2
PGND2
100µF
6.3V
s4
330µF
2.5V
s4
100pF
–
20k
5.9k
BOOST2
M3
CMDSH-3
0.1µF
RJK0305DPB
L2
0.44µH
0.001Ω
1%
RUN
PGOOD
M4
100k
RJK0330DPB
100Ω
100Ω
s2
L1, L2: PULSE PA0513.441NLT
3855 F20
C : MURATA GRM31CR60J107ME39L
OUT1
C : SANYO 2R5TPE330M9
OUT2
Figure 20ꢀ High Efficiency Dual Phase 1ꢀ26, 40A Supply, fSW = 250kHz
3855f
ꢂꢅ
LTC3855
Typical applicaTions
0.1µF
V
IN
4.5V TO
14V
+
10µF
s4
270µF
16V
3.92k
M1
RJK0305DPB
0.1µF
L1
0.47µH
TK/SS1
TG1
BOOST1
PGND1
BG1
0.1µF
I
TH1
V
CMDSH-3
2.2Ω
FB1
M2
SGND
RJK0330DPB
s2
V
V
IN
FB2
LTC3855
20k
I
INTV
EXTV
TH2
CC
CC
V
1.2V
40A
OUT
4.7µF
1µF
TK/SS2
SENSE2
SENSE2
DIFFP
3300pF
0.1µF
+
C
C
OUT2
OUT1
+
–
BG2
PGND2
100µF
6.3V
s4
330µF
2.5V
s4
330pF
20k
10k
BOOST2
CMDSH-3
0.1µF
M3
L2
0.47µH
RJK0305DPB
M4
100k
RJK0330DPB
PGOOD
s2
3.92k
L1, L2: VISHAY IHLP5050FD-01, 0.47µH
3855 F21
C
C
: MURATA GRM31CR60J107ME39L
OUT1
: SANYO 2R5TPE330M9
OUT2
Figure 21ꢀ High Efficiency Dual Phase 1ꢀ26, 40A Supply with DCR Sensing, fSW = 250kHz
3855f
ꢂꢆ
LTC3855
Typical applicaTions
100Ω
100Ω
1nF
V
IN
400kHz
4.5V TO
14V
+
10µF
s4
270µF
16V
100k
M1
RJK0305DPB
s2
0.001Ω
1%
0.1µF
L1
TK/SS1
TG1
0.23µH
0.1µF
I
BOOST1
PGND1
BG1
TH1
V
CMDSH-3
2.2Ω
FB1
M2
SGND
RJK0330DPB
s2
V
V
IN
FB2
LTC3855
10k
I
INTV
TH2
CC
CC
V
0.9V
50A
OUT
4.7µF
1µF
TK/SS2
EXTV
2700pF
1nF
+
C
C
OUT2
OUT1
+
SENSE2
SENSE2
DIFFP
BG2
PGND2
100µF
6.3V
s2
330µF
2.5V
s4
220pF
–
20k
5.1k
BOOST2
M3
CMDSH-3
RJK0305DPB
0.1µF
s2
L2
0.001Ω
1%
0.23µH
M4
100k
RJK0330DPB
100Ω
100Ω
PGOOD
s2
L1, L2: VITEC 59PR9873
3855 F22
C : MURATA GRM31CR60J107ME39L
OUT1
C : SANYO 2R5TPE330M9
OUT2
Figure 22ꢀ Small Size, Dual Phase 0ꢀ96, 50A Supply, fSW = 400kHz
3855f
ꢂꢇ
LTC3855
Typical applicaTions
100Ω
100Ω
RUN1
1nF
V
IN
4.5V TO
14V
+
10µF
s3
270µF
16V
100k
M1
RJK0305DPB
0.002Ω
1%
0.1µF
L1
TK/SS1
TG1
BOOST1
PGND1
BG1
0.3µH
0.1µF
I
TH1
V
FB1
CMDSH-3
2.2Ω
M2
SGND
RJK0330DPB
V
FB2
V
IN
LTC3855
13.3k
I
INTV
TH2
CC
CC
4.7µF
1µF
TK/SS2
EXTV
4700pF
+
SENSE2
SENSE2
DIFFP
BG2
PGND2
330pF
1nF
–
20k
2k
BOOST2
M3
CMDSH-3
0.1µF
RJK0305DPB
L2
0.3µH
0.002Ω
1%
V
OUT1
RUN1
+
1V
C
C
OUT2
OUT1
M4
50A
100Ω
100Ω
100µF
6.3V
s3
470µF
2.5V
s4
RJK0330DPB
PGOOD1V
100k
100Ω
100Ω
RUN1
1nF
100k
M5
RJK0305DPB
0.002Ω
1%
0.1µF
L3
TK/SS1
TG1
BOOST1
PGND1
BG1
0.3µH
I
TH1
V
FB1
CMDSH-3
M6
SGND
RJK0330DPB
2.2Ω
V
FB2
V
IN
LTC3855
90.9k
I
INTV
TH2
CC
CC
4.7µF
1µF
TK/SS2
EXTV
3300pF
100pF
+
20k
0.1µF
SENSE2
SENSE2
DIFFP
BG2
PGND2
0.1µF
–
10µF
10k
BOOST2
CMDSH-3
M7
S4816BDY
0.1µF
L4
2.2µH
V
OUT2
3.3V
RUN2
PGOOD3.3V
C
OUT3 5A
100k
100µF
6.3V
2.49k
4.99k
3855 F23
L1, L2, L3: VITEC 59PR9874
L4: WURTH 744311220
C
C
, C
: TDK C3225X5R0J107M
: KEMET T530D477M2R5ATE006
OUT1 OUT3
OUT2
Figure 23ꢀ Triple Phase 16, 50A Supply with Auxillary 3ꢀ36, 5A Rail, fSW = 400kHz
3855f
ꢂꢈ
LTC3855
Typical applicaTions
V
IN
7V TO
24V
22µF
50V
2.2Ω
1µF
4.7µF
Si4816BDY
Si4816BDY
M2
D3
D4
V
PGOOD INTV
IN
CC
M1
TG1
TG2
0.1µF
0.1µF
L2
2.2µH
L2
3.3µH
BOOST1
SW1
BOOST2
SW2
LTC3855
BG2
BG1
CLKOUT
MODE/PLLIN
PGND
FREQ
I
LIM
10Ω
1000pF
10Ω
10Ω
+
+
SENSE1
SENSE2
1000pF
10Ω
8mΩ
8mΩ
–
–
SENSE1
RUN1
SENSE2
15pF
10pF
DIFFP
DIFFN
RUN2
V
EXTV
V
OUT1
3.3V
5A
CC
V
DIFFOUT
OUT2
V
5V
FB2
TH2
FB1
147k
1%
5A
90.9k
1%
I
I
TH1
1000pF
100pF
1000pF
TK/SS1
TK/SS2
SGND
+
+
20k
1%
C
10k
1%
20k
1%
C
OUT2
150µF
15k
1%
122k
1%
OUT1
220µF
100pF
0.1µF
0.1µF
3855 F24
L1: TDK RLF 7030T-2R2M5R4
L2: TDK ULF10045T-3R3N6R9
C
C
: SANYO 4TPE220MF
OUT1
: SANYO 6TPE150MI
OUT2
Figure 24ꢀ 3ꢀ36/5A, 56/5A Converter Using Sense Resistors
3855f
ꢃ0
LTC3855
Typical applicaTions
0.1µF
V
IN
13V TO
38V
+
+
383k
4.7µF
100µF
50V
0.1µF
24k
L1
s6
M1
18k
5.6nF
10k
BSC093N040LS
V
OUT1
0.1µF
12V
6A
TK/SS1
TG1
BOOST1
PGND1
BG1
C
OUT1
13µH
39µF
16V
s2
I
TH1
20k
20k
47pF
47pF
V
FB1
CMDSH-3
2.2Ω
M2
SGND
BSC093N040LS
V
FB2
V
IN
LTC3855
I
INTV
TH2
CC
CC
4.7µF
TK/SS2
SENSE2
SENSE2
DIFFP
EXTV
0.1µF
+
–
BG2
PGND2
4.99k
5.6nF
0.1µF
BOOST2
0.1µF
147k
CMDSH-3
0.1µF
L2
3.7µH
M3
BSC093N040LS
V
OUT2
5V
+
C
OUT2
10A
M4
100k
100k
39µF
16V
s2
BSC093N040LS
PGOOD1
PGOOD2
8.2k
24k
3855 F25
L1: WURTH 7443551131
L2: WURTH 7443551370
C , C : SANYO 16SVPC39MV
OUT1 OUT2
Figure 25ꢀ 126, ꢁA and 56, 10A Supply with DCR Sensing, fSW = 250kHz
3855f
ꢃꢀ
LTC3855
package DescripTion
FE Package
38-Lead Plastic TSSꢂP (4ꢀ4mm)
(Reference LTC DWG # 05-08-1772 Rev A)
Exposed Pad 6ariation AA
4.75 REF
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
REF
38
20
6.60 0.10
2.74 REF
4.50 REF
SEE NOTE 4
6.40
REF (.252)
BSC
2.74
(.108)
0.315 0.05
1.05 0.10
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
19
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0o – 8o
0.50
(.0196)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.17 – 0.27
FE38 (AA) TSSOP 0608 REV A
(.0067 – .0106)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN
FOR EXPOSED PAD ATTACHMENT
MILLIMETERS
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3. DRAWING NOT TO SCALE
3855f
ꢃꢁ
LTC3855
package DescripTion
UJ Package
40-Lead Plastic QFN (ꢁmm × ꢁmm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
0.70 0.05
6.50 0.05
5.ꢀ0 0.05
4.42 0.05
4.50 0.05
(4 SIDES)
4.42 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 0.05
R = 0.ꢀꢀ5
TYP
6.00 0.ꢀ0
(4 SIDES)
R = 0.ꢀ0
TYP
39 40
0.40 0.ꢀ0
PIN ꢀ TOP MARK
(SEE NOTE 6)
ꢀ
2
PIN ꢀ NOTCH
R = 0.45 OR
0.35 s 45°
CHAMFER
4.42 0.ꢀ0
4.50 REF
(4-SIDES)
4.42 0.ꢀ0
(UJ40) QFN REV Ø 0406
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
BOTTOM VIEW—EXPOSED PAD
ꢀ. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE TOP AND BOTTOM OF PACKAGE
3855f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ꢃꢂ
LTC3855
relaTeD parTs
PART NUMBER DESCRIPTIꢂN
CꢂMMENTS
Phase-Lockable Fixed 250kHz to 750kHz Frequency, 4V ≤ V ≤ 24V,
LTC3853
Triple Output, Multiphase Synchronous Step-Down DC/DC
Controller, R or DCR Current Sensing and Tracking
IN
V
Up to 13.5V
OUT3
SENSE
LTC3731
3-Phase Synchronous Controller, Expandable to 12 phases Phase-Lockable Fixed 250kHz to 600kHz Frequency, 0.6V ≤ V
≤ 5.25V,
OUT
Differential Amp, High Output Current 60A to 240A
4.5V ≤ V ≤ 32V,
IN
LTC3850/
LTC3850-1/
LTC3850-2
Dual 2-Phase, High Efficiency Synchronous Step-Down DC/ Phase-Lockable Fixed 250kHz to 780kHz Frequency, 4V ≤ V ≤ 30V,
IN
DC Controller, R
or DCR Current Sensing and Tracking 0.8V ≤ V
≤ 5.25V
OUT
SENSE
LTC3854
Small Footprint Wide V Range Synchronous Step-Down
Fixed 400kHz Operating Frequency 4.5V ≤ V ≤ 38V, 0.8V ≤ V
≤ 5.25V,
OUT
IN
IN
DC/DC Controller, R
or DCR Current Sensing
2mm × 3mm QFN-12
SENSE
LTC3851A/
LTC3851A-1
No R
™ Wide V Range Synchronous Step-Down DC/ Phase-Lockable Fixed 250kHz to 750kHz Frequency, 4V ≤ V ≤ 38V,
SENSE
IN
IN
DC Controller, R
or DCR Current Sensing and Tracking 0.8V ≤ V
≤ 5.25V, MSOP-16E, 3mm × 3mm QFN-16, SSOP-16
SENSE
OUT
LTC3878
No R
Constant On-Time Synchronous Step-Down
Very Fast Transient Response, t
= 43ns, 4V ≤ V ≤ 38V,
IN
SENSE
ON(MIN)
DC/DC Controller, No R
Required
0.8V ≤ V
≤ 0.9V , SSOP-16
OUT IN
SENSE
LTC3879
No R
Constant On-Time Synchronous Step-Down
Very Fast Transient Response, t
0.6V ≤ V
= 43ns, 4V ≤ V ≤ 38V,
IN
SENSE
ON(MIN)
DC/DC Controller, No R
Required
≤ 0.9V , MSOP-16E, 3mm × 3mm QFN-16
SENSE
OUT
IN
LTM4600HV
10A DC/DC µModule® Complete Power Supply
High Efficiency, Compact Size, Fast Transient Response 4.5V ≤ V ≤ 28V,
IN
0.8V ≤ V
≤ 5V, 15mm × 15mm × 2.8mm
OUT
LTM4601AHV 12A DC/DC µModule Complete Power Supply
High Efficiency, Compact Size, Fast Transient Response 4.5V ≤ V ≤ 28V,
IN
0.8V ≤ V
≤ 5V, 15mm × 15mm × 2.8mm
OUT
LTC3610
LTC3611
12A, 1MHz, Monolithic Synchronous Step-Down DC/DC
Converter
High Efficiency, Adjustable Constant On-Time 4V ≤ V ≤ 24V,
IN
OUT(MIN)
V
0.6V, 9mm × 9mm QFN-64
10A, 1MHz, Monolithic Synchronous Step-Down DC/DC
Converter
High Efficiency, Adjustable Constant On-Time 4V ≤ V ≤ 32V,
IN
V
0.6V, 9mm × 9mm QFN-64
OUT(MIN)
LTC3857/
LTC3857-1
Low I , Dual Output 2-Phase Synchronous Step-Down
Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz,
4V ≤ V ≤ 38V, 0.8V ≤ V ≤ 24V, I = 50µA
Q
DC/DC Controller with 99% Duty Cycle
IN
OUT
Q
LTC3868/
LTC3868-1
Low I , Dual Output 2-Phase Synchronous Step-Down
Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz,
4V ≤ V ≤ 24V, 0.8V ≤ V ≤ 14V, I = 170µA,
Q
DC/DC Controller with 99% Duty Cycle
IN
OUT
Q
LT3845
Low I , High Voltage Synchronous Step-Down DC/DC
Adjustable Fixed Operating Frequency 100kHz to 500kHz,
4V ≤ V ≤ 60V, 1.23V ≤ V ≤ 36V, I = 30µA, TSSOP-16
Q
Controller
IN
OUT
Q
No R
is a trademark of Linear Technology Corporation. µModule is a registered trademark of Linear Technology Corporation.
SENSE
3855f
LT 1009 • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
ꢃꢃ
●
●
LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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