LTC3856EUH-TRPBF_技术文档

LTC3856

2-Phase Synchronous

Step-Down DC/DC

Controller with Diffamp

FeaTures

n

DescripTion

PolyPhase^®Controller Reduces Input and Output

The LTC^®3856 is a single output, dual channel PolyPhase

synchronous step-down DC/DC controller that drives all

N-channel power MOSFET stages. This device includes a

high speed differential ampliﬁer for remote output volt-

age sense. Power loss and supply noise are minimized by

operating the two controller output stages out-of-phase

and up to 12-phase operation can be achieved.

Capacitance and Power Supply Induced Noise

n

Wide V Range: 4.5V to 38V Operation

IN

n

±±.ꢀ5ꢁ% ±.ꢂV Reꢃerence Voltage Accuracy

n

High Eꢃﬁciency: Up to 95ꢁ

Programmable Burst Mode^®Operation or

n

Stage Shedding™ ꢃor Highest Light Load Eꢃﬁciency

n

Active Voltage Positioning (AVP)

The LTC3856 monitors the output current by sensing

the voltage drop across the output inductor (DCR) or by

using a sense resistor. DCR temperature compensation

maintains an accurate current sense threshold over a

broad temperature range. A constant-frequency, current

mode architecture allows a phase-lockable frequency of

up to 770kHz.

n

R

SENSE

or DCR Current Sensing

n

Programmable DCR Temperature Compensation

Phase-Lockable Fixed Frequency: 25±kHz to ꢀꢀ±kHz

True Remote Sense Diꢃꢃerential Ampliﬁer

Dual N-Channel MOSFET Synchronous Drive

V

Range: 0.6V to 5V without Differential Ampliﬁer

Range: 0.6V to 3.3V with Differential Ampliﬁer

OUT

A wide 4.5V to 38V input supply range encompasses

most intermediate bus voltages and battery chemistries.

Burst Mode operation, continuous or Stage Shedding

modes are supported. A TK/SS pin shared by both chan-

nels ramps the output voltage during start-up.

L, LT, LTC, LTM, Linear Technology, the Linear logo, PolyPhase, Burst Mode and OPTI-LOOP

are registered trademarks and Stage Shedding is a trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents,

including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6498466,

6580258, 6611131, 6674274.

Adjustable Soft-Start or V

Tracking

OUT

Stackable for Up to 12-Phase Operation

32-Pin (5mm × 5mm) QFN and 38-Pin TSSOP Packages

applicaTions

n

Telecom and Datacom Systems

n

Industrial and Medical Instruments

n

DC Power Distribution Systems

Computer Systems

n

Typical applicaTion

Eꢃﬁciency and Power Loss

vs Output Current

High Eꢃﬁciency 1.5V/5±A Step-Down Converter

V

100

90

100

10

1

IN

V

= 12V

4.5V TO

20V

IN

OUT

10µF

s 4

30.1k

= 1.5V

DIFFOUT

TG1

BOOST1

SW1

V

IN

S

0.33µH

S

Burst Mode

OPERATION

V

FB

0.1µF

80

ILIM

20k

LTC3856

S

70

RUN

BG1

S

PLLIN

PGOOD

CLKOUT

PHASMD

MODE

ITEMP

FREQ

60

50

+

SENSE1

–

SENSE1

TG2

BOOST2

SW2

40

30

20

10

0

S

0.33µH

V

1.5V

50A

OUT

0.1µF

S

0

BG2

122k

EXTV

INTV

S

CC

+

100µF

s 8

DIFFN

DIFFP

SENSE2

4.7µF

–

–1

100

0.1

1

10

I

TH

TK/SS GND AVP ISET

2200pF

1.5k

LOAD CURRENT (A)

0.1µF

3856 TA01b

S

3856 TA01a

3856f

ꢀ

LTC3856

absoluTe MaxiMuM raTings ^{(Note 1)}

Input Supply Voltage (V )......................... 40V to –0.3V

I , V Voltages................................... INTV to –0.3V

IN

TH FB CC

Topside Driver Voltages (BOOSTn) ............ 46V to –0.3V

Switch Voltage (SWn)................................... 40V to –5V

INTV Peak Output Current ................................100mA

CC

Operating Junction Temperature Range

INTV , RUN, PGOOD, EXTV ,

(Notes 2, 3)............................................ –40°C to 125°C

Storage Temperature Range................... –65°C to 125°C

Reﬂow Peak Body Temperature (UH Package)...... 260°C

Lead Temperature (Soldering, 10 sec.)

CC

(BOOSTn – SWn)......................................... 6V to –0.3V

SENSEn Voltages ...................................... 5.5V to –0.3V

MODE, PLLIN, ILIM, TK/SS, AVP,

FREQ, ISET Voltages............................. INTV to –0.3V

FE Package............................................................ 300°C

CC

DIFFP, DIFFN, DIFFOUT, PHASMD,

ITEMP Voltages..................................... INTV to –0.3V

CC

pin conFiguraTion

TOP VIEW

1

2

PLLIN

CLKOUT

SW1

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

FREQ

RUN

TOP VIEW

+

SENSE1

3

–

SENSE1

4

TG1

NC

5

NC

TK/SS

32 31 30 29 28 27 26 25

6

BOOST1

PGND1

BG1

TK/SS

1

2

3

4

5

6

7

8

24 BOOST1

23 BG1

V

7

FB

V

I

FB

I

8

TH

V

22

21

TH

IN

SGND

AVP

9

V

IN

AVP

INTV

CC

10

11

12

13

14

15

16

17

18

19

INTV

CC

39

33

ITEMP

20 EXTV

CC

ITEMP

EXTV

CC

PHASMD

BG2

19

PHASMD

BG2

+

SENSE2

18 BOOST2

17 TG2

+

SENSE2

PGND2

NC

–

SENSE2

SENSE2–

DIFFP

9

10 11 12 13 14 15 16

BOOST2

TG2

DIFFN

DIFFOUT

ISET

SW2

PGOOD

MODE

UH PACKAGE

32-LEAD (5mm s 5mm) PLASTIC QFN

ILIM

T

= 125°C, θ = 34°C/W

JA

JMAX

EXPOSED PAD (PIN 33) IS SGND/PGND, MUST BE SOLDERED TO PCB

FE PACKAGE

38-LEAD PLASTIC TSSOP

T

= 125°C, θ = 25°C/W

JA

JMAX

EXPOSED PAD (PIN 39) IS SGND/PGND, MUST BE SOLDERED TO PCB

3856f

ꢁ

LTC3856

orDer inForMaTion

LEAD FREE FINISH

LTC3856EFE#PBF

LTC3856IFE#PBF

LTC3856EUH#PBF

LTC3856IUH#PBF

TAPE AND REEL

PART MARKING*

LTC3856FE

3856

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

LTC3856EFE#TRPBF

LTC3856IFE#TRPBF

LTC3856EUH#TRPBF

LTC3856IUH#TRPBF

38-Lead Plastic TSSOP

32-Lead (5mm × 5mm) Plastic QFN

3856

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

elecTrical characTerisTics ^Thel denotes the speciﬁcations which apply over the ꢃull operating

junction temperature range% otherwise speciﬁcations are at T_A= 25°C (Note 2). V_IN= 15V% V_RUN= 5V% unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Main Control Loops

V

Input Voltage

4.5

0.6

38

V

IN

Output Voltage

5.0

OUT

FB

l

Regulated Feedback Voltage

I

Voltage = 1.2V, E-Grade (Note 4)

Voltage = 1.2V, I-Grade (Note 4)

0.5955 0.600 0.6045

0.593 0.600 0.607

V

TH

I

Feedback Current

(Note 4)

= 4.5V to 38V (Note 4)

–15

–50

nA

FB

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

0.002 0.02

%/V

REFLNREG

LOADREG

IN

(Note 4)

Measured in Servo Loop, ∆I Voltage = 1.2V to 0.7V

Measured in Servo Loop, ∆I Voltage = 1.2V to 1.6V

l

0.01

–0.01 –0.1

0.1

%

TH

g

m

Transconductance Ampliﬁer g

I = 1.2V, Sink/Source 5µA (Note 4)

TH

2.0

mmho

m

I

Input DC Supply Current

Normal Mode

Shutdown

(Note 5)

Q

V

= 15V

4.0

40

mA

µA

IN

= 0V

70

RUN

DF

Maximum Duty Factor

Undervoltage Lockout

UVLO Hysteresis

In Dropout; f

= 500kHz

93

94

%

V

MAX

OSC

l

UVLO

V

Ramping Down

3.0

3.2

0.6

0.66

1

3.4

INTVCC

UVLO Hyst

V

l

V

Feedback Overvoltage Lockout

Measured at V

0.64

0.68

2

V

OVL

FB

+

I

SENSE Pins Bias Current

Each Channel, V

= 3.3V

µA

V

SENSE

TEMP

TK/SS

SENSE1,2

DCR Tempco Compensation Current

Soft-Start Charge Current

RUN Pin On Threshold

V

= 0.3V

= 0V

9

10

11

ITEMP

V

TK/SS

1.0

1.1

1.25

1.22

80

1.5

1.35

V

Rising

RUN

RUN Pin On Hysteresis

mV

RUNHYS

Maximum Current Sense Threshold

(E-Grade)

V

= 0.5V, V

= 3.3V

SENSE1,2

SENSE(MAX)

FB

l

I

= 0V

25

45

68

30

50

75

35

55

82

mV

LIM

= Float

= INTV

CC

V

Maximum Current Sense Threshold

(I-Grade)

V

= 0.5V, V

= 3.3V

SENSE1,2

SENSE(MAX)

FB

l

I

= 0V

23

43

66

30

50

75

37

57

84

mV

LIM

= Float

= INTV

CC

3856f

ꢂ

LTC3856

elecTrical characTerisTics ^Thel denotes the speciﬁcations which apply over the ꢃull operating

junction temperature range% otherwise speciﬁcations are at T_A= 25°C (Note 2). V_IN= 15V% V_RUN= 5V% unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

TG Transition Time

Rise Time

Fall Time

(Note 6)

TG1,2 t

C

= 3300pF

25

ns

r

f

LOAD

BG Transition Time

Rise Time

Fall Time

(Note 6)

BG1,2 t

C

= 3300pF

25

ns

r

f

LOAD

TG/BG t

Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

C

= 3300pF Each Driver

30

90

ns

1D

LOAD

BG/TG t

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

= 3300pF Each Driver

2D

LOAD

t

Minimum On-Time

(Note 7)

ON(MIN)

INTV Linear Regulator

CC

V

Internal V Voltage

6V < V ≤ 38V

4.8

4.5

5.0

0.5

4.7

50

5.2

2.0

V

%

INTVCC

CC

IN

INT

INTV Load Regulation

I

CC

= 0mA to 20mA

LDO

CC

l

EXTV Switchover Voltage

EXTV Ramping Positive

V

EXTVCC

CC

EXT

EXTV Voltage Drop

I

CC

= 20mA, V = 5V

EXTVCC

100

mV

LDO

CC

EXTV Hysteresis

200

LDOHYS

CC

Oscillator and Phase-Locked Loop

f

Nominal Frequency

V

= 1.2V

= 0V

450

210

700

500

250

770

250

10

550

290

850

kHz

kΩ

µA

NOM

LOW

HIGH

FREQ

Lowest Frequency

Highest Frequency

≥ 2.4V

R

MODE Input Resistance

Frequency Setting Output Current

Phase (Relative to Controller 1)

MODE

I

9

11

FREQ

CLKOUT

PHASMD = GND; Non Stage Shedding Mode

PHASMD = FLOAT; Non Stage Shedding Mode

60

90

120

180

Deg

PHASMD = INTV ; Non Stage Shedding Mode

CC

Stage Shedding Mode

CLKHIGH

Clock High Output Voltage

Clock Low Output Voltage

4

5

0

V

CLKLOW

0.2

PGOOD Output

V

PGOOD Voltage Low

I

= 2mA

= 5V

0.1

0.2

2

V

PGL

PGOOD

I

PGOOD Leakage Current

PGOOD Trip Level, Either Controller

V

µA

PGOOD

V

with Respect to Set Output Voltage

Ramping Negative

Ramping Positive

PG

FB

V

–10

10

%

FB

V

3856f

ꢃ

LTC3856

elecTrical characTerisTics ^Thel denotes the speciﬁcations which apply over the ꢃull operating

junction temperature range% otherwise speciﬁcations are at T_A= 25°C (Note 2). V_IN= 15V% V_RUN= 5V% unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Diꢃꢃerential Ampliﬁer

l

A

Gain

E-Grade

I-Grade

0.998

0.997

1

1.002

1.003

V/V

DA

R

Input Resistance

Measured at DIFFP Input

80

kΩ

mV

dB

mA

V

IN

V

Input Offset Voltage

V

= V

= 1.5V, I = 100µA

DIFFOUT

2

OS

DIFFP

DIFFOUT

PSRR

Power Supply Rejection Ratio

Maximum Output Current

Maximum Output Voltage

4.5V < V < 38V

100

3

IN

I

2

CL

V

I

= 300µA

V

INTVCC INTVCC

OUT(MAX)

DIFFOUT

–1.4

–1.1

On-Chip Driver

TG R

BG R

GBW

SR

TG Pull-Up R

TG High

TG Low

BG High

BG Low

(Note 8)

2.6

1.5

2.4

1.1

3

Ω

UP

DS(ON)

TG Pull-Down R

DOWN

UP

DS(ON)

BG Pull-Up R

Ω

DS(ON)

BG Pull-Down R

Ω

DOWN

DS(ON)

Gain-Bandwidth Product

Slew Rate

MHz

V/µs

2

Stage Shedding Mode

I

Programmable Stage Shedding

Mode Current

6.5

7.5

8.5

µA

ISET

AVP (Active Voltage Positioning)

Maximum V with AVP

V

AVP

2.5

250

2

V

µA

OUT

+

I

Sink Current of AVP Pin

SENSE = 1.2V

SINK

+

Source Current of AVP Pin

SENSE = 1.2V

mA

mV

SOURCE

+

V

-V

Maximum Voltage Drop V

to V

O

SENSE = 1.2V

120

AVP O(MAX)

AVP

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: The LTC3856 is tested in a feedback loop that servos V to a

ITH

speciﬁed voltage and measures the resultant V

.

FB

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See the Applications Information

section.

Note 2: The LTC3856 is tested under pulse load conditions such that

T

≈

T . The LTC3856E is guaranteed to meet performance speciﬁcations

J

A

Note ꢂ: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note ꢀ: The minimum on-time condition corresponds to the on inductor

from 0°C to 85°C operating junction temperature. Speciﬁcations over

the –40°C to 125°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls.

The LTC3856I is guaranteed to meet performance speciﬁcations over the

full –40°C to 125°C operating junction temperature range.

peak-to-peak ripple current ≥40% of I

(see Minimum On-Time

MAX

Considerations in the Applications Information section).

Note 8: Guaranteed by design.

Note 3: T is calculated from the ambient temperature, T , and power

J

A

dissipation, P , according to the following formula:

D

LTC3856UH: T = T + (P • 34°C/W)

J

A

D

LTC3856FE: T = T + (P • 25°C/W)

J

A

D

3856f

ꢄ

LTC3856

Typical perForMance characTerisTics

Load Step:

Burst Mode Operation

Load Step:

Forced Continuous Mode

V

I

= 3.6V

= 200µA

= 2.2ΩF

V

I

= 3.6V

BAT

CPO

C

CPO

BAT

CPO

I

LOAD

40A/DIV

= 200µA

= 2.2ΩF

LOAD

40A/DIV

C

I

L1

I

L1

20A/DIV

I

L2

I

L2

20A/DIV

V

OUT

200mV/DIV

3856 G01

3856 G02

3856 G04

3856 G06

100µs/DIV

V

= 12V

OUT

LOAD

V

= 12V

OUT

LOAD

IN

= 1.5V

I

= 1A TO 40A

I

= 1A TO 40A

Eꢃﬁciency vs Output Current

and Mode

Inductor Current at Light Load

100

90

V

I

C

= 3.6V

Burst Mode

OPERATION

BAT

= 200µA

= 2.2ΩF

FORCED

CONTINUOUS

MODE, 5A/DIV

CPO

80

70

FORCED

60

50

Burst Mode

OPERATION, 5A/DIV

CONTINUOUS

Stage

MODE

Shedding

MODE

40

30

20

10

0

DCM OPERATION,

5A/DIV

1µs/DIV

V

= 12V

= 1.5V

IN

OUT

V

I

= 12V

IN

= 1.5V

= 400mA

OUT

0.1

1

10

100

LOAD

LOAD CURRENT (A)

3856 G03

Stage Shedding Transition%

1-Phase to 2-Phase

Stage Shedding Transition%

2-Phase to 1-Phase

OVERSHOOT

36mV

UNDERSHOOT

35mV

V

OUT

100mV/DIV

OUT

100mV/DIV

V

SW1

10V/DIV

SW1

10V/DIV

V

SW2

10V/DIV

SW2

10V/DIV

3856 G05

10µs/DIV

V

= 12V

V

= 12V

IN

OUT

IN

OUT

= 1.5V

3856f

ꢅ

LTC3856

Typical perForMance characTerisTics

Quiescent Current vs Input

Voltage without EXTV_CC

Load Step without AVP

Load Step with AVP

4.5

4.3

4.1

3.9

3.7

3.5

3.3

3.1

2.9

2.7

2.5

108mV

V

OUT

50mV/DIV

54mV

50A

I

L

25A

20A/DIV

3856 G07

3856 G07a

100µs/DIV

V

= 12V

V

= 12V

IN

OUT

IN

OUT

= 1.5V

5

15

20

25

30

35

40

10

INPUT VOLTAGE (V)

3856 G08

Current Sense Threshold

vs I_THVoltage

Maximum Current Sense Threshold

vs Common Mode Voltage

INTV_CCLine Regulation

80

60

80

70

60

50

40

30

20

10

0

5.25

5.00

4.75

4.50

4.25

4.00

3.75

3.50

3.25

3.00

I

= INTV

CC

LIM

I

= INTV

CC

LIM

I

= FLOAT

I

= FLOAT

LIM

40

20

I

= GND

LIM

I

= GND

LIM

0

–20

–40

0

0.5

1

1.5

2

3

4

5

0

1

15 20 25 30 35 40

0

5

10

V

(V)

V

COMMON MODE VOLTAGE (V)

INPUT VOLTAGE (V)

ITH

SENSE

3856 G09

3856 G10

3856 G11

Maximum Current Sense Voltage

vs Feedback Voltage

(Current Foldback)

Maximum Current Sense Voltage

vs Duty Cycle

TK/SS Pull-Up Current

vs Temperature

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

1.5

1.4

1.3

1.2

1.1

1.0

I

= INTV

CC

LIM

I

= INTV

LIM CC

I

= FLOAT

= GND

I

= FLOAT

= GND

LIM

I

LIM

0

0.2

0.3

0.4

0.5

0.6

–50 –25

0

25

50

75 100 125

0

20 30 40 50 60 70 80 90 100

0.1

10

FEEDBACK VOLTAGE (V)

DUTY CYCLE (%)

TEMPERATURE (°C)

3856 G13

3856 G12

3856 G14

3856f

ꢆ

LTC3856

Typical perForMance characTerisTics

Oscillator Frequency

vs Temperature

Shutdown (RUN) Threshold

vs Temperature

Regulated Feedback Voltage

vs Temperature

1.25

1.20

1.15

1.10

0.605

0.604

0.603

0.602

0.601

0.600

0.599

0.598

900

800

700

600

500

400

300

200

100

0

V

= INTV

CC

FREQ

ON

V

= 1.2V

= GND

FREQ

V

OFF

–25

0

25 50 75 100 125 150

–50

–25

0

25

50

75 100 125

–50

–25

0

25

50

75 100 125

–50

TEMPERATURE (°C)

3856 G15

3856 G16

3856 G17

Undervoltage Lockout Threshold

(INTV_CC) vs Temperature

Oscillator Frequency

vs Input Voltage

Shutdown Current

vs Input Voltage

60

50

40

30

20

10

0

520

510

500

490

480

4.0

3.8

3.6

3.4

3.2

3.0

ON

OFF

10 15 20 25 30 35 40

0

5

10

15

20

25

30

35

40

–25

0

25

50

75 100 125

–50

INPUT VOLTAGE (V)

3856 G20

TEMPERATURE (°C)

3856 G19

3856 G18

Quiescent Current vs Temperature

without EXTV_CC

Shutdown Current vs Temperature

6

5

4

3

2

1

0

70

60

50

40

30

20

10

0

–25

0

25

50

75 100 125

–50

–25

0

25

50

75 100 125

–50

TEMPERATURE (°C)

3856 G22

3856 G21

3856f

ꢇ

LTC3856

pin FuncTions ^(TSSOP/QFN)

FREQ (Pin 1/Pin 29): Frequency Setting Pin. A resistor

to ground sets the operating frequency of the controller.

This pin can also be driven with a DC voltage to vary the

frequency of the internal oscillator.

temperature coefﬁcient) resistor placed near the heat

source on the PCB board (e.g., inductors) changes the

controller’s current limit with temperature.

PHASMD(Pin12/Pinꢂ):ConnectthispintoSGND,INTV ,

CC

or ﬂoat this pin to select the phase of CLKOUT to be 60°,

RUN (Pin 2/Pin 3±): Run Control Input. A voltage above

1.22V on this pin turns on the IC. There is a 1µA pull-up

current for this pin. Once the RUN pin rises above 1.22V,

an additional 4.5µA pull-up current is added to the pin.

120° and 90°, respectively.

DIFFP (Pin 15/Pin 9): Positive Input of Remote Sensing

Differential Ampliﬁer. Connect this directly to the remote

load voltage.

+

SENSE1 % SENSE2 (Pins 3% 13/Pins 31% ꢀ): Current

Sense Comparator Inputs. The (+) inputs to the current

comparators are normally connected to DCR sensing

networks or current sensing resistors.

DIFFN (Pin 1ꢂ/Pin 1±): Negative Input of Remote Sens-

ing Differential Ampliﬁer. Connect this pin to the negative

terminal of output load capacitors.

–

SENSE1 % SENSE2 (Pins 4% 14/Pins 32% 8): Current

Sense Comparator Inputs. The (–) inputs to the current

comparators are connected to the outputs.

DIFFOUT (Pin 1ꢀ/Pin 11): Output of Remote Sensing

Differential Ampliﬁer. Connect this pin to V through a

FB

resistive divider.

NC (Pins 5% 25% 34) TSSOP Package: No Connections.

ISET (Pin 18/Pin 12): Stage Shedding Mode Comparator

and Burst Mode Comparator Programming Pin. A resistor

to ground programs the threshold of the Stage Shedding

mode comparator or Burst Mode comparator threshold

and current limit.

TK/SS (Pin ꢂ/Pin 1): Output Voltage Tracking and Soft-

Start Input. When one particular IC is conﬁgured to be the

master of two ICs, a capacitor to ground at this pin sets

the ramp rate for the master IC’s output voltage. When the

IC is conﬁgured to be the slave of two ICs, the V voltage

I

(Pin 19/Pin 13): Current Comparator Sense Volt-

FB

LIM

of the master IC is reproduced by a resistor divider and

applied to this pin. An internal soft-start current of 1.25µA

is charging this pin.

age Range Input. This pin is to be programmed to

SGND, FLOAT or INTV to set the maximum current

CC

sense threshold to one of three different levels for both

comparators.

V

(Pin ꢀ/Pin 2): Error Ampliﬁer Feedback Input. This

FB

pin receives the remotely sensed feedback voltage from

an external resistive divider.

MODE (Pin 2±/Pin 14): Forced Continuous Mode,

Burst Mode Operation or Stage Shedding Mode Selec-

tion Pin. Connect this pin to SGND to force IC in

I

(Pin 8/Pin 3): Current Control Threshold and Error

TH

continuous mode of operation. Connect to INTV to

CC

Ampliﬁer Compensation Point. Each associated channels’

enable Stage Shedding mode operation. Leaving the pin

ﬂoating enables Burst Mode operation.

current comparator tripping threshold increases with I

control voltage.

TH

PGOOD (Pin 21/Pin 15): Power Good Indicator Output.

Open-drain logic out that is pulled to ground when the

output exceeds the 10% regulation window, after the

internal 20µs power-bad mask timer expires.

SGND(Pin9/Pin33):SignalGroundandPowerGround.All

small-signalcomponentsandcompensationcomponents

should connect to this ground, which in turn connects to

PGND at one point.

EXTV (Pin 28/Pin 2±): External Power Input to an

CC

AVP (Pin1±/Pin 4):ActiveVoltagePositioningLoad Slope

Programming Pin. A resistor between this pin and the

DIFFP pin sets the load slope.

Internal Switch Connected to INTV . This switch closes

CC

and supplies the IC power, bypassing the internal low

dropout regulator, whenever EXTV is higher than 4.7V.

CC

ITEMP (Pin 11/Pin 5): Input to the Temperature Sensing

Circuit. Connect this pin to an external NTC (negative

Do not exceed 6V on this pin and ensure V > V

IN

EXTVCC

at all times.

3856f

ꢈ

LTC3856

pin FuncTions ^(TSSOP/QFN)

INTV (Pin29/Pin21):Internal5VRegulatorOutput. The

the sources of the bottom N-channel MOSFETs, the (–)

terminalofCV andthe(–)terminalofC .Allsmall-signal

CC

control circuits are powered from this voltage. Decouple

this pin to PGND with a minimum of 4.7µF low ESR tan-

talum or ceramic capacitor.

CC

IN

components and compensation components should also

connect to this ground.

V (Pin 3±/Pin 22): Main Input Supply. Decouple this pin

TG1% TG2 (Pins 35% 23/Pins 25% 1ꢀ): Top Gate Driver

IN

to PGND with a capacitor (0.1µF to 1µF).

Outputs. These are the outputs of ﬂoating drivers with

a voltage swing equal to INTV superimposed on the

CC

BG1% BG2 (Pins 31% 2ꢀ/Pins 23% 19): Bottom Gate Driver

switch nodes voltages.

Outputs. These pins drive the gates of the bottom N-chan-

nel MOSFETs between INTV and PGND.

SW1% SW2 (Pins 3ꢂ% 22/Pins 2ꢂ% 1ꢂ): Switch Node

Connections to Inductors. Voltage swing at these pins

is from a Schottky diode (external) voltage drop below

CC

PGND1% PGND2 (Pins 32% 2ꢂ) TSSOP Package: Power

Ground Pin. Connect this pin closely to the sources of the

ground to V .

IN

bottom N-channel MOSFETs, the (–) terminal of CV and

CC

the (–) terminal of C .

CLKOUT(Pin3ꢀ/Pin2ꢀ):Clockoutputwithphasechange-

able by PHASMD to enable usage of multiple LTC3856 ICs

in multiphase systems.

IN

BOOST1% BOOST2 (Pins 33% 24/Pins 24% 18): Boosted

Floating Driver Supplies. The (+) terminal of the boot-

strap capacitors connect to these pins. These pins swing

PLLIN (Pin 38/Pin 28): External Synchronization Pin. A

clock on the pin synchronizes the internal oscillator with

the clock on this pin.

from a diode voltage drop below INTV up to V

+

CC

IN

INTV .

CC

SGND/PGND (Exposed Pad Pin 33) QFN Package: Signal

Ground and Power Ground. Connect this pin closely to

SGND(ExposedPadPin39)TSSOPPackage:Theexposed

pad must be soldered to the PCB.

3856f

ꢀ0

LTC3856

FuncTional DiagraM

EXTV

CC

ITEMP

MODE PLLIN PHASMD

4.7V

FREQ

+

–

TEMPSNS

V

IN

F

V

IN

0.6V

MODE/SYNC

DETECT

+

C

IN

5V

REG

+

–

INTV

CC

F

PLL-SYNC

INTV

CC

BOOST

TG

D

B

BURSTEN

C

B

CLKOUT

FCNT

ON

OSC

M1

S

R

SW

Q

+

SENSE

SWITCH

LOGIC

AND

ANTISHOOT-

THROUGH

3k

–

+

–

L1

–

SENSE

V

C

I

REV

OUT

CMP

+

BG

OUT

ISET

RUN

OV

M2

ISET

C

PGND

VCC

I

LIM

R

AVP

PGOOD

SLOPE

DIFFP

DIFFOUT

R2

COMPENSATION

40k

+

–

+

–

0.54V

40k

INTV

UVLO

CC

UV

DIFFAMP

V

FB

1

51k

SLOPE RECOVERY

ACTIVE CLAMP

I

THB

DIFFN

+

–

40k

R1

SLEEP

OV

0.66V

SGND

ISET

R

PRE-AVP

V

IN

SENSE1

+

–

– ^SS

– ^RUN

+

1.25µA

–

SENSE1

EA

0.6V

REF

+

–

+ +

+

–

SENSE2

AVP

0.5V

1.22V

0.55V

1µA

C

C1

C

TK/SS

I

TH

RUN

SS

R

C

3856 FD

3856f

ꢀꢀ

LTC3856

(Reꢃer to Functional Diagram)

operaTion

Main Control Loop

which normally recharges during each off cycle through

an external diode when the top MOSFET turns off. If the

The LTC3856 uses a constant-frequency, current mode

step-down architecture. During normal operation, each

top MOSFET is turned on each cycle when the oscillator

sets the RS latch, and turned off when the main current

input voltage, V , decreases to a voltage close to V

,

IN

OUT

the loop may enter dropout and attempt to turn on the

top MOSFET continuously. The dropout detector detects

this and forces the top MOSFET off for about one-twelfth

of the clock period plus 100ns every third cycle to allow

comparator,I

,resetseachRSlatch.Thepeakinductor

CMP

current at which I

resets the RS latch is controlled

TH

C to recharge. However, it is recommended that a load

B

by the voltage on the I pin, which is the output of the

error ampliﬁer, EA. The V pin receives a portion of

be present or the IC operates at low frequency during the

FB

dropout transition to ensure C is recharged.

B

output voltage feedback signal via the DIFFOUT pin (if

DIFFAMP is used) through the external resistive divider

and is compared to the internal reference voltage. When

the load current increases, it causes a slight decrease in

Shutdown and Start-Up (RUN and TK/SS Pins)

The LTC3856 can be shut down using the RUN pin. Pulling

theRUNpinbelow1.22Vshutsdownthemaincontrolloop

for the controller and most internal circuits, including the

the V pin voltage relative to the 0.6V reference, which

FB

in turn causes the I voltage to increase until each

TH

INTV regulator. ReleasingtheRUNpinallowsaninternal

inductor’s average current matches half of the new load

current (assuming the two current sensing resistors are

equal). In Burst Mode operation, after each top MOSFET

has turned off, the bottom MOSFET is turned on until

either the inductor current starts to reverse, as indicated

CC

1µA current to pull up the pin and enable the controller.

Alternatively, the RUN pin may be externally pulled up or

driven directly by logic. Be careful not to exceed the ab-

solute maximum rating of 6V on this pin. The start-up of

the controller’s output voltage, V , is controlled by the

by the reverse current comparator, I , or the beginning

of the next cycle.

OUT

REV

voltage on the TK/SS pin. When the voltage on the TK/SS

pin is less than the 0.6V internal reference, the LTC3856

The main control loop is shut down by pulling the RUN pin

low. Releasing RUN allows an internal 1µA current source

to pull up the RUN pin. When the RUN pin reaches 1.22V,

the main control loop is enabled and the IC is powered

up. When the RUN pin is low, all functions are kept in a

controlled state.

regulates the V voltage to the TK/SS pin voltage instead

FB

of the 0.6V reference. This allows the TK/SS pin to be

used to program a soft-start by connecting an external

capacitor from the TK/SS pin to SGND. An internal 1.25µA

pull-up current charges this capacitor, creating a voltage

ramp on the TK/SS pin. As the TK/SS voltage rises linearly

from 0V to 0.6V (and beyond), the output voltage, V

,

OUT

INTV /EXTV Power

CC

rises smoothly from zero to its ﬁnal value. Alternatively,

Power for the top and bottom MOSFET drivers and most

the TK/SS pin can be used to cause the start-up of V

OUT

other internal circuitry is derived from the INTV pin.

to track that of another supply. Typically, this requires

connecting to the TK/SS pin an external resistor divider

from the other supply to ground (see the Applications

Information section). When the RUN pin is pulled low to

CC

When the EXTV pin is left open or tied to a voltage less

CC

than 4.7V, an internal 5V linear regulator supplies INTV

CC

power from V . If EXTV is taken above 4.7V, the 5V

IN

CC

regulator is turned off and an internal switch is turned on

disable the controller, or when INTV drops below its

CC

connectingEXTV .UsingtheEXTV pinallowstheINTV

undervoltage lockout threshold of 3.2V, the TK/SS pin is

pulled low by an internal MOSFET. When in undervoltage

lockout, all phases of the controller are disabled and the

external MOSFETs are held off.

CC

power to be derived from a high efﬁciency external source

such as a switching regulator output. Each top MOSFET

driver is biased from the ﬂoating bootstrap capacitor, C ,

B

3856f

ꢀꢁ

LTC3856

(Reꢃer to Functional Diagram)

operaTion

Light Load Current Operation (Burst Mode Operation%

Stage Shedding or Continuous Conduction)

threshold where the controller goes into Stage Shedding

mode is where the I voltage drops below 0.5V, but it can

TH

be programmed by the ISET pin. The inductor current is

not allowed to reverse in this mode (discontinuous op-

eration). At very light loads, the current comparator may

remaintrippedforseveralcyclesandforcetheexternaltop

MOSFET to stay off for the same number of cycles (i.e.,

skipping pulses). This mode exhibits low output ripple as

well as low audio noise and reduced RF interference as

compared to Burst Mode operation. It provides a higher

low current efﬁciency than forced continuous mode, but

not nearly as high as Burst Mode operation.

The LTC3856 can be enabled to enter high efﬁciency

Burst Mode operation, Stage Shedding mode or forced

continuousconductionmode.Toselectforcedcontinuous

operation, tie the MODE pin to a DC voltage below 0.6V

(e.g., SGND). To select Stage Shedding mode of opera-

tion, tie the MODE pin to INTV . To select Burst Mode

CC

operation, ﬂoat the MODE pin.

When the controller is enabled for Burst Mode operation,

the peak current in the inductor is set to approximately

one-sixth of the maximum sense voltage even though

the voltage on the I pin indicates a lower value. The

TH

Multichip Operations (PHASMD and CLKOUT Pins)

peak current can be programmed by the ISET pin. If the

average inductor current is higher than the load current,

the error ampliﬁer, EA, will decrease the voltage on the

TheLTC3856’stwochannelsare180°out-of-phase,provid-

ing multiphase operation. This conﬁguration can provide

enough power for most of the high current applications.

However, for even higher power applications, the LTC3856

can be conﬁgured for PolyPhase and multichip operation.

The LTC3856 features PHASMD and CLKOUT pins which

enable multiple LTC3856s to operate out-of-phase, as

shown in Table 1. The CLKOUT signal is out-of-phase

with respect to phase 1 of the controller depending on the

PHASMD pin setting. In Stage Shedding mode, however,

the CLKOUT signal is 180° out-of-phase with respect to

phase 1 of the controller.

I

pin. When the I voltage drops, the internal sleep

TH

signal goes high (enabling sleep mode) and the external

MOSFETs are turned off. In sleep mode, the load current

is supplied by the output capacitor. As the output voltage

decreases, the EA’s output begins to rise. When the output

voltage drops enough, the sleep signal goes low, and the

controller resumes normal operation by turning on the

top external MOSFET on the next cycle of the internal

oscillator. When a controller is enabled for Burst Mode

operation, the inductor current is not allowed to reverse.

The reverse current comparator, I , turns off the bottom

REV

Table 1.

external MOSFET just before the inductor current reaches

zero, preventing it from reversing and going negative.

Thus, the controller operates in discontinuous operation.

In forced continuous operation, the inductor current is

allowed to reverse at light loads or under large transient

conditions. The peak inductor current is determined by

PHASMD

Phase 1

Phase 2

CLKOUT

GND

0°

FLOAT

0°

INTV

CC

0°

180°

60°

180°

90°

240°

120°

Frequency Selection and Phase-Locked Loop

(FREQ and PLLIN Pins)

the voltage on the I pin, just as in normal operation. In

TH

this mode, the efﬁciency at light loads is lower than in

BurstModeoperation. However, continuousmodehasthe

advantages of lower output ripple and less interference

with audio circuitry.

Theselectionofswitchingfrequencyisatrade-offbetween

efﬁciency and component size. Low frequency opera-

tion increases efﬁciency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

When the MODE pin is connected to INTV , the LTC3856

CC

operates in Stage Shedding mode at light loads. The

controller will turn off channel 2 and increase the current

gain of the ﬁrst channel to ensure a smooth transition. The

If the PLLIN pin is not being driven by an external clock

source,theFREQpincanbeusedtoprogramthecontroller’s

3856f

ꢀꢂ

LTC3856

(Reꢃer to Functional Diagram)

operaTion

operating frequency from 250kHz to 770kHz. There is a

precision10µAcurrentﬂowingoutoftheFREQpinenabling

the user to program the controller’s switching frequency

with a single resistor to SGND. A curve is provided later in

theApplicationsInformationsectionshowingtherelation-

ship between the voltage on the FREQ pin and switching

frequency.

Power Good (PGOOD Pin)

ThePGOODpinisconnectedtoanopendrainofaninternal

N-channel MOSFET. The MOSFET turns on and pulls the

PGOOD pin low when either V pin voltage is not within

FB

10% of the 0.6V reference voltage. The PGOOD pin is

also pulled low when the RUN pin is below 1.22V or when

the LTC3856 is in the soft-start or tracking phase. When

A phase-locked loop (PLL) is available on the LTC3856

to synchronize the internal oscillator to an external clock

source that is connected to the PLLIN pin. The PLL loop

ﬁlter network is integrated inside the LTC3856. The

phase-locked loop is capable of locking any frequency

within the range of 250kHz to 770kHz. The frequency

setting resistor should always be present to set the

controller’s initial switching frequency before locking to

the external clock.

the V pin voltage is within the 10% regulation window,

FB

the MOSFET is turned off and the pin is allowed to be

pulled up by an external resistor to a source of up to 6V.

The PGOOD pin will ﬂag power good immediately when

V

is within the regulation window. However, there is an

FB

internal 20µs power-bad mask when V goes out of the

FB

regulation window.

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transient

overshoots (>10%) as well as other more serious condi-

tions that may overvoltage the output. In such cases, the

topMOSFETisturnedoffandthebottomMOSFETisturned

on until the overvoltage condition is cleared.

Sensing the Output Voltage with a Diꢃꢃerential Ampliﬁer

The LTC3856 includes a low offset, unity-gain, high band-

widthdifferentialampliﬁerforapplicationsthatrequiretrue

remote sensing. Sensing the load across the load capaci-

torsdirectlygreatlybeneﬁtsregulationinhighcurrent,low

voltage applications, where board interconnection losses

can be a signiﬁcant portion of the total error budget.

Undervoltage Lockout

The LTC3856 has two functions that help protect the

controller in case of undervoltage conditions. A precision

TheLTC3856differentialampliﬁerhasatypicaloutputslew

rate of 2V/µs. The ampliﬁer is conﬁgured for unity gain,

meaning that the difference between DIFFP and DIFFN is

translated to DIFFOUT, relative to SGND.

UVLOcomparatorconstantlymonitorstheINTV voltage

CC

to ensure that an adequate gate-drive voltage is present. It

locks out the switching action when INTV is below 3.2V.

CC

To prevent oscillation when there is a disturbance on the

Care should be taken to route the DIFFP and DIFFN PCB

traces parallel to each other all the way to the terminals

of the output capacitor or remote sensing points on the

board. In addition, avoid routing these sensitive traces

near any high speed switching nodes in the circuit. Ideally,

the DIFFP and DIFFN traces should be shielded by a low

impedance ground plane to maintain signal integrity.

INTV , the UVLO comparator has 600mV of precision

CC

hysteresis.

Another way to detect an undervoltage condition is

to monitor the V supply. Because the RUN pin has

IN

a precision turn-on reference of 1.22V, one can use a

resistor divider to V to turn on the IC when V is high

IN

enough. An extra 4.5µA of current ﬂows out of the RUN

pin once the RUN pin voltage passes 1.22V. The RUN

comparator itself has about 80mV of hysteresis. One

can program additional hysteresis for the RUN com-

parator by adjusting the values of the resistive divider.

The maximum output voltage when using the differential

ampliﬁer is INTV – 1.4V (typically 3.6V). The differential

CC

ampliﬁer should not be used above this voltage.

For accurate V undervoltage detection, V needs to

IN

be higher than 4.5V.

3856f

ꢀꢃ

LTC3856

applicaTions inForMaTion

+

–

The Typical Application on the ﬁrst page of this data sheet

is a basic LTC3856 application circuit. LTC3856 can be

conﬁgured to use either DCR (inductor resistance) sens-

ing or low value resistor sensing. The choice between the

two current sensing schemes is largely a design trade-off

between cost, power consumption and accuracy. DCR

sensing is becoming popular because it saves expensive

current sensing resistors and is more power efﬁcient,

especially in high current applications. However, current

sensing resistors provide the most accurate current limits

for the controller. Other external component selection is

driven by the load requirement, and begins with the se-

SENSE and SENSE Pins

+

–

The SENSE and SENSE pins are the inputs to the current

comparators. The common mode input voltage range of

the current comparators is 0V to 5V. All SENSE pins are

high impedance inputs with small currents of less than

1µA. The positive high impedance input to the current

comparatorsallowsaccurateDCRsensing.AllSENSE pins

andDIFFPshouldbeconnecteddirectlytoV

sensing is used. Care must be taken not to ﬂoat these pins

during normal operation. Filter components mutual to the

sense lines should be placed close to the LTC3856, and

the sense lines should run close together to a Kelvin con-

nection underneath the current sense element (shown in

Figure 1). Sensing current elsewhere can effectively add

parasitic inductance and capacitance to the current sense

element, degrading the information at the sense terminals

and making the programmed current limit unpredictable.

If DCR sensing is used (Figure 2b), sense resistor R1

should be placed close to the switching node, to prevent

noisefromcouplingintosensitivesmall-signalnodes.The

capacitor C1 should be placed close to the IC pins.

+

–

whenDCR

OUT

lection of R

(if R

is used) and inductor value.

SENSE

Next, the power MOSFETs are selected. Finally, input and

output capacitors are selected.

Current Limit Programming

The I pin is a tri-level logic input which sets the maxi-

LIM

mum current limit of the controller. When I

grounded, ﬂoated or tied to INTV , the typical value for

is either

LIM

CC

themaximumcurrentsensethresholdwillbe30mV,50mV

or 75mV, respectively.

TO SENSE FILTER,

NEXT TO THE CONTROLLER

Which setting should be used? For the best current limit

accuracy,usethe75mVsetting.The30mVsettingwillallow

for the use of very low DCR inductors or sense resistors,

but at the expense of current limit accuracy. The 50mV

setting is a good balance between the two.

C

OUT

R

3856 F01

SENSE

Figure 1. Sense Lines Placement with Sense Resistor

V

IN

V

IN

INTV

CC

INTV

CC

LTC3856

BOOST

SENSE RESISTOR

PLUS PARASITIC

INDUCTANCE

INDUCTOR

BOOST

TG

OPTIONAL

TEMP COMP

NETWORK

V

L

DCR

SW

OUT

R

ESL

V

OUT

SW

S

LTC3856

BG

ITEMP

SGND

BG

C

• 2R ≤ ESL/R

F

S

R

S

PGND

POLE-ZERO

PGND

R1

CANCELLATION

+

R

SENSE

F

+

SENSE

R

P

C1*

||

R2

NTC

C

F

–

SENSE

SGND

3856 F02a

3856 F02b

FILTER COMPONENTS

PLACED NEAR SENSE PINS

L

DCR

R2

R1 + R2

+

R

= DCR

*PLACE C1 NEAR SENSE , R1 R2 × C1 =

SENSE(EQ)

–

SENSE PINS

(2a) Using a Resistor to Sense Current

(2b) Using the Inductor DCR to Sense Current

Figure 2. Two Diꢃꢃerent Methods oꢃ Sensing Current

3856f

ꢀꢄ

LTC3856

applicaTions inForMaTion

Low Value Resistors Current Sensing

up to 1MHz are becoming more common. Under these

conditions the voltage drop across the sense resistor’s

parasiticinductanceisnolongernegligible.Atypicalsens-

ing circuit using a discrete resistor is shown in Figure 2a.

In previous generations of controllers, a small RC ﬁlter

placed near the IC was commonly used to reduce the ef-

fectsofcapacitiveandinductivenoisecoupledinthesense

traces on the PCB. A typical ﬁlter consists of two series

10Ω resistors connected to a parallel 1000pF capacitor,

resulting in a time constant of 20ns. This same RC ﬁlter,

with minor modiﬁcations, can be used to extract the resis-

tivecomponentofthecurrentsensesignalinthepresence

of parasitic inductance. For example, Figure 3 illustrates

the voltage waveform across a 2mΩ sense resistor with

a 2010 footprint for the 1.2V/15A converter operating at

100% load. The waveform is the superposition of a purely

resistive component and a purely inductive component.

It was measured using two scope probes and waveform

math to obtain a differential measurement. Based on

additional measurements of the inductor ripple current

and the on-time and off-time of the top switch, the value

of the parasitic inductance was determined to be 0.5nH

using the equation:

A typical sensing circuit using a discrete resistor is shown

in Figure 2a. R

is chosen based on the required

SENSE

output current. The current comparator has a maximum

threshold, V , determined by the I setting.

SENSE(MAX)

LIM

The input common mode range of the current compara-

tor is 0V to 5V. The current comparator threshold sets the

peak of the inductor current, yielding a maximum average

output current, I

, equal to the peak value less half the

MAX

peak-to-peak ripple current, ∆I . To calculate the sense

L

resistor value, use the equation:

V_SENSE(MAX)

R_SENSE

=

∆I_L

I_(MAX)

+

2

BecauseofpossiblePCBnoiseinthecurrentsensingloop,

the AC current sensing ripple of ∆V

= ∆I • R

SENSE

L SENSE

also needs to be checked in the design to get a good

signal-to-noise ratio. In general, for a reasonably good

PCB layout, a 10mV ∆V

voltage is recommended as

SENSE

a conservative number to start with, either for R

or

SENSE

DCRsensingapplications.Forpreviousgenerationcurrent

mode controllers, the maximum sense voltage was high

enough (e.g., 75mV for the LTC1628/LTC3728 family)

that the voltage drop across the parasitic inductance of

the sense resistor represented a relatively small error. For

today’s highest current density solutions, however, the

value of the sense resistor can be less than 1mΩ and the

peak sense voltage can be as low as 20mV. In addition,

inductor ripple currents greater than 50% with operation

V_ESL(STEP)

t_ON• t_OFF

t_ON+ t_OFF

ESL=

(1)

∆I_L

If the RC time constant is chosen to be close to the

parasitic inductance divided by the sense resistor (L/R),

the resulting waveform looks resistive again, as shown

in Figure 4. For applications using low maximum sense

voltages, check the sense resistor manufacturer’s data

V

ESL(STEP)

V

SENSE

20mV/DIV

3856 F03

3856 F04

500ns/DIV

Figure 3. Voltage Waveꢃorm Measured

Directly Across the Sense Resistor

Figure 4. Voltage Waveꢃorm Measured Aꢃter

the Sense Resistor Filter. C_F= 1±±±pF% R_F= 1±±Ω

3856f

ꢀꢅ

LTC3856

applicaTions inForMaTion

sheet for information about parasitic inductance. In the

absence of data, measure the voltage drop directly across

the sense resistor to extract the magnitude of the ESL step

and use Equation 1 to determine the ESL. However, do not

overﬁlter. Keep the RC time constant, less than or equal

to the inductor time constant to maintain a high enough

Using the inductor ripple current value from the Inductor

Value Calculation and Output Ripple Current section, the

target sense resistor value is:

V_SENSE(MAX)

R_SENSE(EQUIV)

=

∆I_L

I_(MAX)

+

ripple voltage of ∆V

. The equation generally applies

SENSE

2

to high density/high current applications where I

>

MAX

10A and low values of inductors are used. For applications

where I < 10A, set R to 10Ω and C to 1000pF. This

will provide a good starting point. The ﬁlter components

need to be placed close to the IC. The positive and nega-

tive sense traces need to be routed as a differential pair

and Kelvin connected to the sense resistor.

To ensure that the application will deliver full load current

over the full operating temperature range, choose the

minimum value for the maximum current sense threshold

MAX

F

(V

)intheElectricalCharacteristicstable(25mV,

SENSE(MAX)

45mV or 68mV, depending on the state of the I

pin).

LIM

Next, determine the DCR of the inductor. Where provided,

use the manufacturer’s maximum value, usually given at

20°C. Increase this value to account for the temperature

coefﬁcient of resistance, which is approximately 0.4%/°C.

Inductor DCR Sensing

For applications requiring the highest possible efﬁciency

at high load currents, the LTC3856 is capable of sensing

the voltage drop across the inductor DCR, as shown in

Figure 2b. The DCR of the inductor represents the small

amount of DC winding resistance of the copper, which

can be less than 1mΩ for today’s low value, high current

inductors. In a high current application requiring such an

inductor, conduction loss through a sense resistor would

costseveralpointsofefﬁciencycomparedtoDCRsensing.

If the external R1|| R2 • C1 time constant is chosen to be

exactly equal to the L/DCR time constant, the voltage drop

across the external capacitor is equal to the drop across

theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe

voltage across the sense terminals for applications where

the DCR is greater than the target sense resistor value.

To properly dimension the external ﬁlter components, the

DCR of the inductor must be known. It can be measured

using a good RLC meter, but the DCR tolerance is not

always the same and varies with temperature; consult the

manufacturers’ data sheets for detailed information.

A conservative value for T

is 100°C. To scale the

L(MAX)

maximum inductor DCR to the desired sense resistor

value, use the divider ratio:

R_SENSE(EQUIV)

R_D=

DCR_MAXat T_L(MAX)

C1 is usually selected to be in the range of 0.047µF to

0.47µF. This forces R1|| R2 to around 2k, reducing error

+

that might have been caused by the SENSE pins’ 1µA

current. T

is the maximum inductor temperature.

L(MAX)

The equivalent resistance R1|| R2 is scaled to the room

temperature inductance and maximum DCR:

L

R1||R2=

(DCR at 20°C) • C1

The sense resistor values are:

R1• R_D

R1||R2

R1=

; R2=

R_D

1−R_D

3856f

ꢀꢆ

LTC3856

applicaTions inForMaTion

The LTC3856 also features a DCR temperature compensa-

tion circuit by using a NTC temperature sensor. See the

Inductor DCR Sensing Temperature Compensation and

the ITEMP Pin section for details.

5V and DCR temperature compensation is disabled. The

ITEMP pin has a constant 10µA precision current ﬂow-

ing out of the pin. By connecting an NTC resistor from

the ITEMP pin to SGND, the maximum current sense

threshold can be varied over temperature according the

following equation:

The maximum power loss in R1 is related to duty cycle,

and will occur in continuous mode at the maximum input

voltage:

1.8 – V_ITEMP

V_{SENSEMAX(ADJ)}= V_SENSE(MAX)

where:

•

1.3

V

_IN(MAX)− V_OUT• V

(

)

OUT

P_LOSSR1=

R1

V

isthemaximumadjustedcurrentsense

SENSEMAX(ADJ)

threshold at temperature.

Ensure that R1 has a power rating higher than this value.

If high efﬁciency is necessary at light loads, consider this

power loss when deciding whether to use DCR sensing or

sense resistors. Light load power loss can be modestly

higher with a DCR network than with a sense resistor, due

totheextraswitchinglossesincurredthroughR1.However,

DCR sensing eliminates a sense resistor, reduces conduc-

tion losses and provides higher efﬁciency at heavy loads.

Peak efﬁciency is about the same with either method. To

maintainagoodsignal-to-noiseratioforthecurrentsense

V

is the maximum current sense threshold

SENSE(MAX)

speciﬁed in the Electrical Characteristics table. It is

typically 75mV, 50mV or 30mV, depending on the set-

ting I pins.

LIM

V

is the voltage of the ITEMP pin.

ITEMP

The valid voltage range for DCR temperature compensa-

tion on the ITEMP pin is between 0.5V to 0.2V, with 0.5V

or above being no DCR temperature correction and 0.2V

the maximum correction. However, if the duty cycle of the

controller is less than 25%, the ITEMP range is extended

from 0.5V to 0V.

signal, use a minimum ∆V

of 10mV for duty cycles

less than 40%. For a DCR sensing application, the actual

ripple voltage will be determined by the equation:

SENSE

V − V_OUTV_OUT

The NTC resistor has a negative temperature coefﬁcient,

meaning its value decreases as temperature rises. The

IN

∆V_SENSE

=

R1•C1 V • f_OSC

IN

V

voltage, therefore, decreases as temperature in-

ITEMP

creases and in turn, the V

will increase to

SENSEMAX(ADJ)

Inductor DCR Sensing Temperature Compensation

and the ITEMP Pin

compensate the DCR temperature coefﬁcient. The NTC

resistor, however, is nonlinear and the user can linear-

ize its value by building a resistor network with regular

resistors. Consult the NTC manufacture data sheets for

detailed information.

Inductor DCR current sensing provides a lossless method

of sensing the instantaneous current. Therefore, it can

provide higher efﬁciency for applications of high output

currents. However, the DCR of the inductor, which is the

small amount of DC winding resistance of the copper,

typically has a positive temperature coefﬁcient. As the

temperatureoftheinductorrises, itsDCRvalueincreases.

The current limit of the controller is therefore reduced.

Another use for the ITEMP pins, in addition to NTC com-

pensated DCR sensing, is adjusting V

to values

SENSE(MAX)

between the nominal values of 30mV, 50mV and 75mV

for a more precise current limit. This is done by applying

a voltage less than 0.5V to the ITEMP pin. V

SENSE(MAX)

The LTC3856 offers a method to counter this inaccuracy

by allowing the user to place an NTC temperature sensing

resistor near the inductor to actively correct this error.

The ITEMP pin, when left ﬂoating, is at a voltage around

will be varied per the previous equation and the same

duty cycle limitations will apply. The current limit can be

adjusted using this method either with a sense resistor

or DCR sensing.

3856f

ꢀꢇ

LTC3856

applicaTions inForMaTion

NTC Compensated DCR Sensing

The resistance of the NTC thermistor can be obtained

from the vendor’s data sheet either in the form of graphs,

tabulated data or formulas. The approximate value for the

NTC thermistor for a given temperature can be calculated

from the following equation:

For DCR sensing applications where a more accurate

current limit is required, a network consisting of an NTC

thermistor placed from the ITEMP pin to ground will

provide correction of the current limit over temperature.

Figure 2b shows this network. Resistors R and R will













S

P

1

R = R • exp B•

−



O

linearize the impedance the ITEMP pin sees. To implement

NTC compensated DCR sensing, design the DCR sense

ﬁlter network per the same procedure mentioned in the

previous selection, except calculate the divider compo-

nents using the room temperature value of the DCR. For

a typical application:





T + 273 T + 273





O



Where

R = resistance at temperature T, in degrees C

R = resistance at temperature T , typically 25°C

O

B = B-constant of the thermistor.

1. Set the ITEMP pin resistance to 50k at 25°C. With

10µA ﬂowing out of the ITEMP pin, the voltage on the

ITEMP pin will be 0.5V at room temperature. Current

limit correction will occur for inductor temperatures

greater than 25°C.

Figure5showsatypicalresistancecurvefora100ktherm-

istor and the ITEMP pin network over temperature.

Starting values for the NTC compensation network are:

• NTC R = 100k

O

2. Calculate the ITEMP pin resistance and the maximum

inductor temperature, which is typically 100°C. Use the

following equations:

• R = 20k

S

• R = 50k

P

But, the ﬁnal values should be calculated using the previ-

ous equations and checked at 25°C and 100°C.

V

ITEMP100C

R_ITEMP100C

=

10µA

V

= 0.5V − 1.3 •

ITEMP100C

10000

R2

0.4

100

THERMISTOR RESISTANCE:

I_MAX•DCR_MAX

•

•(100°C − 25°C)•

R

= 100k

= 25°C

O

R1+ R2

V_SENSE(MAX)

1000

100

10

T

B = 4334 for 25°C/100°C

Calculate the values for R and R . A simple method is to

P

S

P

R

:

ITMP

S

P

= 20k

graph the following R versus R equations with R on

S

= 43.2k

100k NTC

the y-axis and R on the x-axis.

P

R = R

– R ||R

NTC25C P

S

ITEMP25C

0

60 80

120

100

–40 –20

0

20 40

R = R

– R

||R

S

ITEMP100C

NTC100C P

INDUCTOR TEMPERATURE (°C)

3856 F05

Next, ﬁnd the value of R that satisﬁes both equations,

P

Figure 5. Resistance vs Temperature ꢃor the

ITEMP Pin Network and the 1±±k NTC

which will be the point where the curves intersect. Once

R is known, solve for R .

P

S

3856f

ꢀꢈ

LTC3856

applicaTions inForMaTion

After determining the components for the temperature

compensation network, check the results by plotting

Typical values for the NTC compensation network are:

• NTC R = 100k, B-constant = 3000 to 4000

O

I

versus inductor temperature using the following

MAX

equations:

• R ≈ 20k

S

• R ≈ 50k

I_MAX

=

P

Another approach for generating the I

versus inductor

∆V_SENSE

MAX

V_{SENSEMAX(ADJ)}

−

temperature curve plot is to ﬁrst use the aforementioned

2

values as a starting point and then adjusting the R and

S





0.4

100

DCR_MAXAT 25°C• 1+ (T_L(MAX)− 25°C)•

R values as necessary. Figure 6 shows a typical curve







P

of I



versus inductor temperature.

MAX

where

V_{SENSEMAX(ADJ)}= V_SENSE(MAX)

The same thermistor network can be used to correct for

temperatures less than 25°C. But, ensure that V is

ITEMP

1.8V− V

ITMP

•

− A

greater than 0.2V for duty cycles of 25% or more, oth-

erwise temperature correction may not occur at elevated

ambients. For the most accurate temperature detection,

place the thermistor next to the inductors, as shown in

Figure 7. Take care to keep the ITEMP pins away from the

switch nodes.

1.3

V

ITMP

= 10µA • (R + R ||R

)

S

P

NTC

UsetypicalvaluesforV

.Subtractingconstant A

SENSE(MAX)

willprovideaminimumvalueforV

are summarized in Table 2.

.Thesevalues

SENSE(MAX)

RNTC

Table 2. Values ꢃor V_SENSE(MAX)

V

OUT

I

GND

30mV

5mV

FLOAT

50mV

5mV

INTV

CC

LIM

V

A

Typ

75mV

7mV

SENSE(MAX)

L1

L2

SW1

SW2

The resulting current limit should be greater than or

MAX

and 100°C.

3856 F07

equal to I

for inductor temperatures between 25°C

Figure ꢀ. Thermistor Location. Place Thermistor Next to

Inductor(s) ꢃor Accurate Sensing oꢃ the Inductor Temperature%

But Keep the ITEMP Pin Away ꢃrom the Switch Nodes and

Gate Drive Traces.

25

20

15

10

5

CORRECTED

Slope Compensation and Inductor Peak Current

I

MAX

NOMINAL

MAX

I

Slopecompensationprovidesstabilityinconstant-frequen-

cy,currentmodearchitecturesbypreventingsubharmonic

oscillationathighdutycycles.Itisaccomplishedinternally

by adding a compensating ramp to the inductor current

signal at duty cycles in excess of 40%. Normally, this

results in a reduction of maximum inductor peak current

for duty cycles greater than 40%. However, the LTC3856

uses a scheme that counteracts this compensating ramp,

whichallowsthemaximuminductorpeakcurrenttoremain

unaffected throughout all duty cycles.

UNCORRECTED

I

MAX

R

= 20k

S

P

= 43.2k

NTC THERMISTOR:

= 100k

= 25°C

R

O

T

B = 4334

0

60 80

120

100

–40 –20

0

20 40

INDUCTOR TEMPERATURE (°C)

3856 F06

Figure ꢂ. Worst Case I_MAXvs Inductor Temperature Curve

with and without NTC Temperature Compensation

3856f

ꢁ0

LTC3856

applicaTions inForMaTion

Inductor Value Calculation and Output Ripple Current

output ripple current is plotted for a ﬁxed output voltage

as the duty factor is varied between 10% and 90% on the

x-axis. The output ripple current is normalized against the

inductor ripple current at zero duty factor. The graph can

be used in place of tedious calculations. The zero output

ripple current is obtained when:

The operating frequency and inductor selection are inter-

relatedinthathigheroperatingfrequenciesallowtheuseof

smaller inductor and capacitor values. A higher frequency

generally results in lower efﬁciency because of MOSFET

gate charge and transition losses. In addition to this basic

trade-off, the effect of inductor value on ripple current

and low current operation must also be considered. The

PolyPhase approach reduces both input and output ripple

currents while optimizing individual output stages to run

at a lower fundamental frequency, enhancing efﬁciency.

V_OUT

k

N

=

where k =1, 2,...,N–1

V

IN

Power MOSFET and Schottky Diode

(Optional) Selection

The inductor value has a direct effect on ripple current.

At least two external power MOSFETs must be selected

for each power stage: One N-channel MOSFET for the top

(main) switch and one or more N-channel MOSFET(s) for

the bottom (synchronous) switch. The number, type and

on-resistance of all MOSFETs selected take into account

the voltage step-down ratio as well as the actual position

(main or synchronous) in which the MOSFET will be used.

AmuchsmallerandmuchlowerinputcapacitanceMOSFET

should be used for the top MOSFET in applications that

haveanoutputvoltagethatislessthanone-thirdoftheinput

The inductor ripple current, ∆I , per individual section

L

N, decreases with higher inductance or frequency and

increases with higher V or V

:

IN

OUT





V_OUT

f_OSC• L

V_OUT

∆I_L=

1–





V





IN

where f

quency.

is the individual output stage operating fre-

OSC

In a PolyPhase converter, the net ripple current seen by

the output capacitor is much smaller than the individual

inductor ripple currents due to the ripple cancellation. The

details on how to calculate the net output ripple current

can be found in Application Note 77.

voltage.InapplicationswhereV >>V ,thetopMOSFETs’

IN

OUT

on-resistanceisnormallylessimportantforoverallefﬁciency

than its input capacitance at operating frequencies above

300kHz. MOSFET manufacturers have designed special

purpose devices that provide reasonably low on-resistance

with signiﬁcantly reduced input capacitance for the main

switch application in switching regulators.

Figure 8 shows the net ripple current seen by the output

capacitors for the different phase conﬁgurations. The

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1-PHASE

2-PHASE

3-PHASE

4-PHASE

6-PHASE

12-PHASE

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

3856 F08

Figure 8. Normalized Peak Output Current

vs Duty Factor [I_RMS= ±.3(I_OP-P)]

3856f

ꢁꢀ

LTC3856

applicaTions inForMaTion

The peak-to-peak MOSFET gate drive levels are set by the

mode, the duty cycles for the top and bottom MOSFETs

are given by:

voltage, V , requiring the use of logic-level threshold

CC

MOSFETs in most applications. Pay close attention to the

V_OUT

BV

speciﬁcation for the MOSFETs as well; many of the

Main SwitchDuty Cycle=

DSS

V

IN

logic-level MOSFETs are limited to 30V or less. Selection

criteria for the power MOSFETs include the on-resistance,





V – V_OUT

IN

Synchronous SwitchDuty Cycle=





R

, input capacitance, input voltage and maximum

DS(ON)

V





IN

outputcurrent.MOSFETinputcapacitanceisacombination

of several components but can be taken from the typical

gatecharge curveincludedonmostdatasheets(Figure9).

The curve is generated by forcing a constant input current

into the gate of a common source, current source loaded

stage, then plotting the gate voltage versus time.

The power dissipation for the main and synchronous

MOSFETs at maximum output current are given by:



²



V_OUT

I_MAX

N

P_MAIN

=

1+ δ R

+

(

)



DS(ON)

V





IN





I_MAX

2N

IN ²



MILLER

V

R

C

•

V

(

)

(

_DR)(

)

IN





MILLER EFFECT

V

GS





1



+

 • f



a

b

V – V

V

+

–





^TH(IL)

CC

TH(IL)

V

DS

+

Q

V

IN

GS

²

–

C

= (Q – Q )/V

B A DS

MILLER



V – V_OUT

I_MAX

N

3856 F09

IN

P_SYNC

=

1+ δ R

(

)





DS(ON)

V





IN

Figure 9. Gate Charge Characteristic

where N is the number of output stages, δ is the tem-

perature dependency of R , R is the effective top

DS(ON) DR

The initial slope is the effect of the gate-to-source and

the gate-to-drain capacitance. The ﬂat portion of the

curve is the result of the Miller multiplication effect of the

drain-to-gate capacitance as the drain drops the voltage

across the current source load. The upper sloping line is

due to the drain-to-gate accumulation capacitance and

the gate-to-source capacitance. The Miller charge (the

increase in coulombs on the horizontal axis from a to b

driver resistance (approximately 2Ω at V = V

),

GS

MILLER

V is the drain potential and the change in drain poten-

IN

tial in the particular application. V

is the data sheet

TH(IL)

speciﬁed typical gate threshold voltage speciﬁed in the

power MOSFET data sheet at the speciﬁed drain current.

C

isthecalculatedcapacitanceusingthegatecharge

MILLER

curve from the MOSFET data sheet and the technique just

described.

while the curve is ﬂat) is speciﬁed for a given V drain

DS

2

voltage, but can be adjusted for different V voltages by

BothMOSFETshaveI RlosseswhilethetopsideN-channel

DS

multiplying the ratio of the application V to the curve

equation includes an additional term for transition losses,

DS

speciﬁed V values. A way to estimate the C

which peak at the highest input voltage. For V < 20V,

DS

MILLER

IN

term is to take the change in gate charge from points

a and b on a manufacturer’s data sheet and divide by

the high current efﬁciency generally improves with larger

MOSFETs, while for V > 20V, the transition losses rapidly

IN

the stated V voltage speciﬁed. C

is the most

increasetothepointthattheuseofahigherR

device

DS

MILLER

DS(ON)

importantselectioncriteriafordeterminingthetransition

withlowerC

actuallyprovideshigherefﬁciency.The

MILLER

loss term in the top MOSFET but is not directly speciﬁed

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low, or during

a short-circuit when the synchronous switch is on close

to 100% of the period.

on MOSFET data sheets. C

and C are speciﬁed

OS

RSS

sometimes but deﬁnitions of these parameters are not

included. When the controller is operating in continuous

3856f

ꢁꢁ

LTC3856

applicaTions inForMaTion

The term (1 + δ ) is generally given for a MOSFET in the

output voltage, N(V ), is approximately equal to the

OUT

input voltage, V , or:

form of a normalized R

vs temperature curve, but

IN

DS(ON)

δ = 0.005/°C can be used as an approximation for low

V_OUT

k

N

voltage MOSFETs.

=

where k =1, 2,...,N–1

V

IN

The optional Schottky diodes conduct during the dead

time between the conduction of the two large power

MOSFETs. This prevents the body diode of the bottom

MOSFET from turning on, storing charge during the

dead time and requiring a reverse-recovery period which

could cost as much as several percent in efﬁciency. A 2A

to 8A Schottky is generally a good compromise for both

regions of operation due to the relatively small average

current. Larger diodes result in additional transition loss

due to their larger junction capacitance. A Schottky diode

in parallel with the bottom FET may also provide a modest

improvement in Burst Mode efﬁciency.

So, thephasenumbercanbechosentominimizetheinput

capacitor size for the given input and output voltages. In

the graph of Figure 10, the local maximum input RMS

capacitor currents are reached when:

V_OUT

2k –1

N

=

where k =1, 2,...,N

V

IN

Theseworst-caseconditionsarecommonlyusedfordesign

becauseevensigniﬁcantdeviationsdonotoffermuchrelief.

Note that capacitor manufacturer’s ripple current ratings

are often based on only 2000 hours of life. This makes

it advisable to further derate the capacitor or to choose

a capacitor rated at a higher temperature than required.

Several capacitors may also be paralleled to meet size or

height requirements in the design. Always consult the

capacitor manufacturer if there is any question.

C and C

Selection

IN

OUT

In continuous mode, the source current of each top

N-channel MOSFET is a square wave of duty cycle V

/

OUT

V . A low ESR input capacitor sized for the maximum

IN

RMS current must be used. The details of a close form

equation can be found in Application Note 77. Figure 10

showstheinputcapacitorripplecurrentfordifferentphase

conﬁgurationswiththeoutputvoltageﬁxedandinputvolt-

age varied. The input ripple current is normalized against

the DC output current. The graph can be used in place of

tedious calculations. The minimum input ripple current

can be achieved when the product of phase number and

The Figure 10 graph shows that the peak RMS input

current is reduced linearly, inversely proportional to the

number N of stages used. It is important to note that the

efﬁciency loss is proportional to the input RMS current

squared and therefore a 3-stage implementation results

in 90% less power loss when compared to a single-phase

design. Battery/input protection fuse resistance (if used),

PC board trace and connector resistance losses are also

0.6

0.5

0.4

0.3

0.2

0.1

0

1-PHASE

2-PHASE

3-PHASE

4-PHASE

6-PHASE

12-PHASE

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

3856 F10

Figure 1±. Normalized Input RMS Ripple Current

vs Duty Factor ꢃor One to Six Output Stages

3856f

ꢁꢂ

LTC3856

applicaTions inForMaTion

reduced by the reduction of the input ripple current in a

PolyPhase system. The required amount of input capaci-

tanceisfurtherreducedbythefactorN,duetotheeffective

increase in the frequency of the current pulses. Ceramic

capacitors are becoming very popular for small designs

but several cautions should be observed. X7R, X5R and

Y5V are examples of a few of the ceramic materials used

as the dielectric layer, and these different dielectrics have

very different effect on the capacitance value due to the

voltage and temperature conditions applied. Physically,

if the capacitance value changes due to applied voltage

change, there is a concomitant piezo effect which results

in radiating sound! A load that draws varying current at an

audible rate may cause an attendant varying input voltage

on a ceramic capacitor, resulting in an audible signal. A

secondary issue relates to the energy ﬂowing back into

a ceramic capacitor whose capacitance value is being

reducedbytheincreasingcharge.Thevoltagecanincrease

ataconsiderablyhigherratethantheconstantcurrentbeing

supplied because the capacitance value is decreasing as

thevoltageisincreasing!Nevertheless,ceramiccapacitors,

when properly selected and used, can provide the lowest

overall loss due to their extremely low ESR.

tions possible. The ability to externally compensate the

switching regulator loop using the I pin allows a much

TH

wider selection of output capacitor types. The impedance

characteristic of each capacitor type is signiﬁcantly differ-

ent than an ideal capacitor and therefore requires accurate

modelingorbenchevaluationduringdesign.Manufacturers

suchasNichicon,NipponChemi-ConandSanyoshouldbe

consideredforhighperformancethrough-holecapacitors.

TheOS-CONsemiconductordielectriccapacitorsavailable

from Sanyo and the Panasonic SP surface mount types

have a good (ESR)(size) product.

Once the ESR requirement for C

has been met, the

OUT

RMS current rating generally far exceeds the I

RIPPLE(P-P)

requirement. Ceramic capacitors from AVX, Taiyo Yuden

andMurataofferhighcapacitancevalueandverylowESR,

especially applicable for low output voltage applications.

In surface mount applications, multiple capacitors may

have to be paralleled to meet the ESR or RMS current

handling requirements of the application. Aluminum

electrolytic and dry tantalum capacitors are both available

in surface mount conﬁgurations. New special polymer

surface mount capacitors offer very low ESR also but

have much lower capacitive density per unit volume. In

the case of tantalum, it is critical that the capacitors are

surge tested for use in switching power supplies. Several

excellent choices are the AVX TPS, AVX TPSV, the KEMET

T510 series of surface mount tantalums or the Panasonic

SP series of surface mount special polymer capacitors

availableincaseheightsrangingfrom2mmto4mm.Other

capacitor types include Sanyo POSCAP, Sanyo OS-CON,

Nichicon PL series and Sprague 595D series. Consult the

manufacturers for other speciﬁc recommendations.

The selection of C

is driven by the required effective

OUT

seriesresistance(ESR).TypicallyoncetheESRrequirement

is satisﬁed the capacitance is adequate for ﬁltering. The

steady-state output ripple (∆V ) is determined by:

OUT









1

8NfC

∆V_OUT≈ ∆I_RIPPLEESR+



_OUT

where f = operating frequency of each stage, N = the

number of output stages, C = output capacitance and

OUT

∆I = ripple current in each inductor. The output ripple is

L

highestatmaximuminputvoltagesince∆I increaseswith

L

Diꢃꢃerential Ampliﬁer

input voltage. The output ripple will be less than 50mV at

maximum V with ∆I = 0.4I

assuming:

The LTC3856 has a true remote voltage sense capability.

The sensing connections should be returned from the

load, back to the differential ampliﬁer’s inputs through a

common, tightlycoupledpairofPCtraces. Thedifferential

ampliﬁer rejects common mode signals capacitively or

inductively radiated into the feedback PC traces as well as

groundloopdisturbances.Thedifferentialampliﬁeroutput

signal is divided by a pair of resistors and is compared

IN

L

OUT(MAX)

C

OUT

required ESR < N • R

SENSE

and

C_OUT

1

>

8Nf R

(

)

(

)

SENSE

TheemergenceofverylowESRcapacitorsinsmall,surface

mount packages makes very small physical implementa-

with the internal, precision 0.6V voltage reference by the

3856f

ꢁꢃ

LTC3856

applicaTions inForMaTion

error ampliﬁer. The ampliﬁer has an output swing range

of 0V to 3.6V. The output uses an NPN emitter follower

with 80k feedback resistance.

Programmable Stage Shedding Mode

When the MODE pin is tied to INTV , the LTC3856 en-

CC

ters Stage Shedding mode. This means that the second

channel will stop switching when I is below a certain

TH

Active Voltage Positioning (AVP)

programmed threshold. This threshold voltage on I is

TH

In an application, the AVP scheme modiﬁes the regulated

output voltage depending on its current loading. AVP

can improve overall transient response and save power

consumption.

programmed according to the following formula:

 

 3

5

V_SHED= 0.5 +

• 0.5 − V

(

)

ISET

 

TheLTC3856sensesinductorcurrentinformationbymoni-

The valid range of V

is between 0V to 0.5V, where V

ISET ISET

toring voltage drops across the sense resistors R

or

is the voltage on the ISET pin. There is a precision 7.5µA

ﬂowing out of the ISET pin. Connecting a resistor to SGND

SENSE

the DCR sensing network of the two channels. The voltage

dropsareaddedtogetherandappliedasV between

setstheV

voltage. Whenleftﬂoating, V

voltagewill

PRE-AVP

ISET

the AVP and DIFFP pins, which are connected through

resistor R . Then V is scaled through R

AVP

be at INTV . The Stage Shedding mode threshold voltage

CC

in this case will be 0.5V. There is a 50mV hysteresis for

PRE-AVP

and added to output voltage as the compensation for the

load voltage drop.

the Stage Shedding mode threshold comparator.

Programmable Burst Mode Operation

Let:

When the MODE pin is ﬂoating, the LTC3856 enters Burst

Mode operation. This means that both channels will stop

+

–

ꢀ ∆V = V

then:

– V

SENSE1

SENSE2

SENSE1

SENSE2

switching when I is below a certain threshold.

TH

The Burst Mode clamp, which sets the current limit when

bursting, can be programmed through V

the following formula:

according to

ISET







R_AVP

∆V_DIFFP,VOUT= 2• ∆V



R



_PRE-AVP

V

= 0.7 + 0.62 (0.5 – V

)

CLAMP

ISET

The ﬁnal load slope is deﬁned by the inductor current

sense resistors and the two external resistors previously

mentioned.

The valid range of V

ISET

is between 0.3V to 0.5V and

ISET

V

is the voltage on the ISET pin. There is a precision

7.5µA ﬂowing out of ISET. Connecting a resistor to SGND

sets the V

voltage. When left ﬂoating, V

will be at

ISET

In summary, the load slope is:

INTV . The Burst Mode clamp voltage in this case will

CC







R_AVP

_PRE-AVP

be 0.7V. There is a 50mV hysteresis for the Burst Mode

R_SENSE

•

V/A



comparator.

R



The recommended value for R

is 90Ω to 100Ω. The

AVP

maximum output voltage at AVP is 2.5V. Therefore, for

outputshigherthan2.5V,theAVPfunctionisnotsupported.

TheDIFFPpin,however,shouldalwaysbeconnectedtothe

output even when AVP or diffamp functions are not used.

3856f

ꢁꢄ

LTC3856

applicaTions inForMaTion

Soꢃt-Start and Tracking

when there is no load. After TK/SS drops below 0.1V, the

controller operates in discontinuous mode.

The LTC3856 has the ability to either soft-start by itself

with a capacitor or track the output of another external

supply. When the controller is conﬁgured to soft-start by

itself, a capacitor should be connected to its TK/SS pin.

The controller is in the shutdown state if its RUN pin volt-

age is below 1.22V and its TK/SS pin is actively pulled to

ground in this shutdown state.

The LTC3856 allows the user to program how its output

ramps up and down by means of the TK/SS pins. Through

thesepins, theoutputcanbesetuptoeithercoincidentally

or ratiometrically track another supply’s output, as shown

in Figure 11. In the following discussions, V

to the LTC3856’s output as a master and V

refers

OUT1

refers to

OUT2

another supply output as a slave. To implement the coinci-

denttrackingin Figure 11a, connect anadditionalresistive

Once the RUN pin voltage is above 1.22V, the controller

powers up. A soft-start current of 1.25µA then starts to

charge the TK/SS soft-start capacitor. Note that soft-start

or tracking is achieved not by limiting the maximum

output current of the controller but by controlling the

output ramp voltage according to the ramp rate on the

TK/SS pin. Current foldback is disabled during this phase

to ensure smooth soft-start or tracking. The soft-start or

tracking range is deﬁned to be the voltage range from 0V

to 0.6V on the TK/SS pin. The total soft-start time can be

calculated as:

dividertoV

andconnectitsmid-pointtotheTK/SSpin

OUT1

of the slave controller. The ratio of this divider should be

the same as that of the slave controller’s feedback divider

shown in Figure 12a. In this tracking mode, V

must

OUT1

be set higher than V

. To implement the ratiometric

OUT2

trackinginFigure11b,theratiooftheV

dividershould

OUT2

be exactly the same as the master controller’s feedback

divider shown in Figure 12b . By selecting different resis-

tors, the LTC3856 can achieve different modes of tracking

including the two in Figure 11.

C_SS

t_SOFTSTART= 0.6 •

1.25µA

So, which mode should be programmed? While either

mode in Figure 11 satisﬁes most practical applications,

some trade-offs exist. The ratiometric mode saves a pair

of resistors, but the coincident mode offers better output

regulation. Under ratiometric tracking, when the master

controller’s output experiences dynamic excursion (under

load transient, for example), the slave controller output

will be affected as well. For better output regulation, use

the coincident tracking mode instead of ratiometric.

Regardless of the mode selected by the MODE pin, the

controlleralwaysstartsindiscontinuousmodeuptoTK/SS

= 0.5V. Between TK/SS = 0.5V and 0.54V, it will operate in

forced continuous mode and revert to the selected mode

once TK/SS > 0.54V. The output ripple is minimized dur-

ing the 40mV forced continuous mode window ensuring

a clean PGOOD signal.

INTV (LDO) and EXTV

CC

When the channel is conﬁgured to track another supply,

the feedback voltage of the other supply is duplicated by a

resistordividerandappliedtotheTK/SSpin.Therefore,the

voltageramprateonthispinisdeterminedbytheramprate

of the other supply’s voltage. Note that the small soft-start

capacitor charging current is always ﬂowing, producing a

small offset error. To minimize this error, select the track-

ing resistive divider value to be small enough to make this

error negligible. In order to track down another channel or

supply after the soft-start phase expires, the LTC3856 is

The LTC3856 features a true PMOS LDO that supplies

power to INTV from the V supply. INTV powers

CC

IN

CC

the gate drivers and much of the LTC3856’s internal cir-

cuitry. The LDO regulates the voltage at the INTV pin

CC

to 5V when V is greater than 5.5V. EXTV connects

IN

CC

to INTV through a P-channel MOSFET and can supply

CC

the needed power when its voltage is higher than 4.7V.

Each of these can supply a peak current of 100mA and

must be bypassed to ground with a minimum of 4.7µF

ceramic capacitor or other low ESR capacitor. No matter

what type of bulk capacitor is used, an additional 0.1µF

forced into continuous mode of operation as soon as V

FB

isbelowtheundervoltagethresholdof0.54Vregardlessof

thesettingontheMODEpin.However,theLTC3856should

always be set in forced continuous mode tracking down

ceramic capacitor placed directly adjacent to the INTV

and PGND pins is highly recommended. Good bypassing

CC

3856f

ꢁꢅ

LTC3856

applicaTions inForMaTion

V

OUT1

V

OUT1

V

OUT2

V

OUT2

3856 F11b

TIME

3856 F11a

(11b) Ratiometric Tracking

(11a) Coincident Tracking

Figure 11. Two Diꢃꢃerent Modes oꢃ Output Voltage Tracking

V

OUT1

V

OUT2

OUT1

OUT2

R3

R4

R1

R2

R3

R4

R1

R2

R3

R4

TO

TK/SS2

TO

TK/SS2

TO

FB1

TO

FB2

TO

FB2

TO

V

FB1

3856 F12

(12a) Coincident Tracking Set-Up

(12b) Ratiometric Tracking Set-Up

Figure 12. Set-Up and Coincident and Ratiometric Tracking

is needed to supply the high transient currents required

by the MOSFET gate drivers and to prevent interaction

between the channels.

table. For example, the LTC3856 INTV current is limited

CC

to less than 42mA from a 38V supply in the UH package

and not using the EXTV supply:

CC

T = 70°C + (42mA)(38V)(34°C/W) = 125°C

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3856 to be

J

To prevent the maximum junction temperature from be-

ing exceeded, the input supply current must be checked

while operating in continuous conduction mode (MODE

exceeded. The INTV current, which is dominated by the

CC

gate charge current, may be supplied by either the 5V LDO

= SGND) at maximum V . When the voltage applied to

IN

or EXTV . When the voltage on the EXTV pin is less

CC

EXTV rises above 4.7V, the INTV LDO is turned off

CC

than 4.7V, the LDO is enabled. Power dissipation for the

and the EXTV is connected to the INTV . The EXTV

CC

IC in this case is highest and is equal to V • I . The

remainsonaslongasthevoltageappliedtoEXTV remains

IN INTVCC

CC

gate charge current is dependent on operating frequency

as discussed in the Efﬁciency Considerations section.

The junction temperature can be estimated by using the

equations given in Note 3 of the Electrical Characteristics

above 4.5V. Using the EXTV allows the MOSFET driver

CC

and control power to be derived from one of switching

regulator outputs during normal operation and from the

INTV when the output is out of regulation (e.g., start-up,

CC

3856f

ꢁꢆ

LTC3856

applicaTions inForMaTion

short circuit). If more current is required through the

For applications where the main input power is 5V, tie the

V and INTV pins together and tie the combined pins

EXTV than is speciﬁed, an external Schottky diode can

CC

IN

CC

be added between the EXTV and INTV pins. Do not

to the 5V input with a 1Ω or 2.2Ω resistor (as shown in

Figure 13) to minimize the voltage drop caused by the

CC

apply more than 6V to the EXTV pin and make sure that

CC

EXTV < V .

gate charge current. This will override the INTV linear

CC

IN

CC

regulator and will prevent INTV from dropping too low

CC

Signiﬁcant efﬁciency and thermal gains can be realized

by powering INTV from the output, since the V cur-

due to the dropout voltage. Make sure the INTV voltage

CC

IN

is at or exceeds the R

test voltage for the MOSFET,

DS(ON)

rent resulting from the driver and control currents will be

which is typically 4.5V for logic-level devices.

scaled by a factor of (duty cycle)/(switcher efﬁciency).

Tying the EXTV pin to a 5V supply reduces the junction

CC

Topside MOSFET Driver Supply (C % D )

B

temperature in the previous example from 125°C to:

External bootstrap capacitors, C , connected to the

B

T = 70°C + (42mA)(5V)(34°C/W) = 77°C

J

BOOST pins supply the gate drive voltages for the top-

However, for low voltage outputs, additional circuitry is

side MOSFETs. Capacitor C in the Functional Diagram

B

required to derive INTV power from the output.

is charged though external diode D from INTV when

B CC

CC

the SW pin is low. When one of the topside MOSFETs is

The following list summarizes the four possible connec-

to be turned on, the driver places the C voltage across

B

tions for EXTV :

CC

the gate source of the desired MOSFET. This enhances

1. EXTV leftopen(orgrounded).ThiswillcauseINTV

the MOSFET and turns on the topside switch. The switch

CC

to be powered from the internal 5V LDO resulting

in an efﬁciency penalty of up to 10% at high input

voltages.

node voltage, SW, rises to V and the BOOST pin follows.

IN

With the topside MOSFET on, the boost voltage is above

the input supply:

2. EXTV connected directly to V . This is the normal

V

= V + V

IN INTVCC

CC

OUT

BOOST

connection for a 5V regulator and provides the highest

The value of the boost capacitor, C , needs to be 100 times

B

efﬁciency.

thatofthetotalinputcapacitanceofthetopsideMOSFET(s).

3. EXTV connectedtoanexternalsupply.Ifa5Vexternal

The reverse breakdown of the external Schottky diode

CC

supply is available, it may be used to power EXTV

must be greater than V

. When adjusting the gate

CC

IN(MAX)

providing it is compatible with the MOSFET gate drive

drive level, the ﬁnal arbiter is the total input current for

the regulator. If a change is made and the input current

decreases, then the efﬁciency has improved. If there is

no change in input current, then there is no change in

efﬁciency.

requirements.

4. EXTV connected toan output-derived boostnetwork.

CC

For 3.3V and other low voltage regulators, efﬁciency

gains can still be realized by connecting EXTV to an

CC

output-derivedvoltagethathasbeenboostedtogreater

than 4.7V.

V

IN

R

VIN

LTC3856

1Ω

5V

INTV

CC

C

+

INTVCC

C

4.7µF

IN

3856 F13

Figure 13. Set-Up ꢃor a 5V Input

3856f

ꢁꢇ

LTC3856

applicaTions inForMaTion

Setting Output Voltage

Fault Conditions: Current Limit and Current Foldback

If the DIFFAMP is not used, the LTC3856 output voltage

is set by an external feedback resistive divider carefully

placed across the output, as shown in Figure 14. The

regulated output voltage is determined by:

The LTC3856 includes current foldback to help limit load

current when the output is shorted to ground. If the out-

put falls below 50% of its nominal output level, then the

maximum sense voltage is progressively lowered from its

maximumprogrammedvaluetoone-thirdofthemaximum

value. Foldback current limiting is disabled during the

soft-start or tracking up. Under short-circuit conditions

with very low duty cycles, the LTC3856 will begin cycle

skipping in order to limit the short-circuit current. In this

situation the bottom MOSFET will be dissipating most of

the power but less than in normal operation. The short

circuit ripple current is determined by the minimum on-





R_B

R

V_OUT= 0.6V • 1+







_A

To improve the frequency response, a feedforward ca-

pacitor, C , may be used. Great care should be taken to

FF

route the V line away from noise sources, such as the

FB

inductor or the SW line.

time t

of the LTC3856 (≈ 90ns), the input voltage

If the diffamp is used, then V should be connected to the

ON(MIN)

and inductor value:

FB

output of the diffamp, DIFFOUT, as shown in the Typical

Application on the ﬁrst page.

V

L

IN

∆I_L(SC)= t_ON(MIN)

•

V

/DIFFOUT

OUT

The resulting short-circuit current is:

R

C

FF

B

A

LTC3856





1/3 V_SENSE(MAX)

1

– ∆I

2

V

FB

I_SC

=

•2



_L(SC)

R

R_SENSE





3856 F14

Figure 14. Setting Output Voltage without the DIFFAMP

3856f

ꢁꢈ

LTC3856

applicaTions inForMaTion

Phase-Locked Loop and Frequency Synchronization

The LTC3856 has a phase-locked loop (PLL) comprised of

is applied to the PLLIN pin. The internal switch between

the FREQ pin and the integrated PLL ﬁlter network is on,

allowing the ﬁlter network to be pre-charged at the same

voltage as of the FREQ pin. The relationship between the

voltageontheFREQpinandoperatingfrequencyisshown

in Figure 15 and speciﬁed in the Electrical Characteristics

table. If an external clock is detected on the PLLIN pin, the

internal switch mentioned above turns off and isolates the

inﬂuence of the FREQ pin. Note that the LTC3856 can only

be synchronized to an external clock whose frequency is

an internal voltage-controlled oscillator (V ) and a phase

CO

detector. This allows the turn-on of the top MOSFET of

controller 1 to be locked to the rising edge of an external

clock signal applied to the PLLIN pin. The turn-on of the

second phase’s top MOSFETs is thus 180° out-of-phase

with the external clock, and so on. The phase detector is

an edge-sensitive digital type that provides zero degrees

phase shift between the external and internal oscillators.

This type of phase detector does not exhibit a false lock

to harmonics of the external clock.

within range of the LTC3856’s internal V . This is guar-

CO

anteed to be between 250kHz and 770kHz. A simpliﬁed

block diagram is shown in Figure 16.

Theoutputofthephasedetectorisapairofcomplementary

current sources that charge or discharge the internal ﬁlter

network. There is a precision 10µA of current ﬂowing out

of FREQ pin. This allows the user to use a single resistor to

SGNDtosettheswitchingfrequencywhennoexternalclock

If the external clock frequency is greater than the inter-

nal oscillator’s frequency, f , then current is sourced

OSC

continuously from the phase detector output, pulling up

the ﬁlter network. When the external clock frequency is

900

800

700

600

500

400

300

200

100

0

2.4V 5V

R

SET

FREQ

PLLIN

DIGITAL

PHASE/

FREQUENCY

DETECTOR

SYNC

EXTERNAL

OSCILLATOR

V

CO

3856 F16

0

0.5

1

1.5

2

2.5

FREQ/PLLFLTR PIN VOLTAGE (V)

3856 F15

Figure 15. Relationship Between Oscillator

Frequency and Voltage at the FREQ Pin

Figure 1ꢂ. Phase-Locked Loop Block Diagram

3856f

ꢂ0

LTC3856

applicaTions inForMaTion

less than f , current is sunk continuously, pulling down

Eꢃﬁciency Considerations

OSC

the ﬁlter network. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

the phase difference. The voltage on the ﬁlter network is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Percent efﬁciency can

be expressed as:

%Efﬁciency = 100% – (L1 + L2 + L3 + ...)

the ﬁlter capacitor C holds the voltage.

LP

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Typically, the external clock (on the PLLIN pin) input high

threshold is 1.6V, while the input low threshold is 1V.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

Minimum On-Time Considerations

Minimum on-time, t

, is the smallest time duration

ON(MIN)

losses in LTC3856 circuits: 1) IC V current, 2) INTV

IN

CC

2

that the LTC3856 is capable of turning on the top MOSFET.

It is determined by internal timing delays and the gate

charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

regulator current, 3) I R losses, 4) topside MOSFET

transition losses.

1. The V current is the DC supply current given in the

IN

ElectricalCharacteristicstable,whichexcludesMOSFET

driverandcontrolcurrents. V currenttypicallyresults

IN

in a small (<0.1%) loss.

V_OUT

t_ON(MIN)

<

V

f

_IN

( )

2. INTV current is the sum of the MOSFET driver and

CC

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge dQ moves

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase. The

minimum on-time for the LTC3856 is approximately 90ns,

with reasonably good PCB layout, minimum 30% induc-

tor current ripple and at least 10mV ripple on the current

sense signal. The minimum on-time can be affected by

PCB switching noise in the voltage and current loop. As

the peak sense voltage decreases the minimum on-time

gradually increases to 130ns. This is of particular concern

in forced continuous applications with low ripple current

at light loads. If the duty cycle drops below the minimum

on-timelimitinthissituation, asigniﬁcantamountofcycle

skipping can occur with correspondingly larger current

and voltage ripple.

fromINTV toground.TheresultingdQ/dtisacurrent

CC

out of INTV that is typically much larger than the

CC

controlcircuitcurrent.Incontinuousmode,I

=

GATECHG

f(Q +Q ), whereQ andQ arethegatechargesofthe

T

B

T

B

topside and bottom side MOSFETs. Supplying INTV

CC

powerthroughEXTV fromanoutput-derivedsource

CC

will scale the V current required for the driver and

IN

control circuits by a factor of (duty cycle)/(efﬁciency).

For example, in a 20V to 5V application, 10mA of

INTV current results in approximately 2.5mA of V

CC

IN

current. This reduces the mid-current loss from 10%

or more (if the driver was powered directly from V )

IN

to only a few percent.

2

3. I R losses are predicted from the DC resistances of

the fuse (if used), MOSFET, inductor and current sense

resistor.Incontinuousmode,theaverageoutputcurrent

ﬂows through L and R , but is chopped between

SENSE

3856f

ꢂꢀ

LTC3856

applicaTions inForMaTion

the topside MOSFET and the synchronous MOSFET. If

forces the regulator to adapt to the current change and

thetwoMOSFETshaveapproximatelythesameR

,

return V

to its steady-state value. During this recovery

DS(ON)

OUT

time V

can be monitored for excessive overshoot or

then the resistance of one MOSFET can simply be

OUT

ringing, which would indicate a stability problem. The

summed with the resistances of L and R

to ob-

SENSE

2

availability of the I pin not only allows optimization of

tain I R losses. For example, if each R

= 10mΩ,

TH

DS(ON)

control loop behavior but also provides a DC-coupled and

AC-ﬁltered closed-loop response test point. The DC step,

rise time and settling at this test point truly reﬂects the

closed-loop response. Assuming a predominantly second

ordersystem, phasemarginand/ordampingfactorcanbe

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining

the rise time at the pin.

R = 10mΩ, R

= 5mΩ, then the total resistance is

L

SENSE

25mΩ. This results in losses ranging from 2% to 8%

as the output current increases from 3A to 15A for a 5V

output, or a 3% to 12% loss for a 3.3V output.

Efﬁciency varies as the inverse square of V

for the

OUT

sameexternalcomponentsandoutputpowerlevel. The

combined effects of increasingly lower output voltages

andhighercurrentsrequiredbyhighperformancedigital

systemsisnotdoublingbutquadruplingtheimportance

of loss terms in the switching regulator system!

TheI externalcomponentsshownintheTypicalApplica-

TH

tioncircuitwillprovideanadequatestartingpointformost

applications. The I series R -C ﬁlter sets the dominant

TH

C

4. Transition losses apply only to the topside MOSFET(s),

and become signiﬁcant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

pole-zero loop compensation. The values can be modiﬁed

slightly (from 0.5 to 2 times their suggested values) to

optimize transient response once the ﬁnal PC layout is

done and the particular output capacitor type and value

have been determined. The output capacitors need to be

selected because the various types and values determine

the loop gain and phase. An output current pulse of 20%

to 80% of full-load current having a rise time of 1µs to

2

Transition Loss = (1.7) V • I

• C

• f

IN

O(MAX)

RSS

Other hidden losses such as copper trace and internal

battery resistances can account for an additional 5%

to 10% efﬁciency degradation in portable systems. It

is very important to include these system level losses

during the design phase. The internal battery and fuse

resistance losses can be minimized by ensuring that

10µs will produce output voltage and I pin waveforms

TH

that will give a sense of the overall loop stability without

breaking the feedback loop. Placing a power MOSFET

directly across the output capacitor and driving the gate

with an appropriate signal generator is a practical way to

produce a realistic load step condition. The initial output

voltage step resulting from the step change in output cur-

rentmaynotbewithinthebandwidthofthefeedbackloop,

so this signal cannot be used to determine phase margin.

C has adequate charge storage and very low ESR at

IN

the switching frequency. A 25W supply will typically

require a minimum of 20µF to 40µF of capacitance

having a maximum of 20mΩ to 50mΩ of ESR. Other

losses including Schottky conduction losses during

dead time and inductor core losses generally account

for less than 2% total additional loss.

This is why it is better to look at the I pin signal which

TH

is in the feedback loop and is the ﬁltered and compen-

sated control loop response. The gain of the loop will be

Checking Transient Response

increased by increasing R and the bandwidth of the loop

C

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

will be increased by decreasing C . If R is increased by

C

the same factor that C is decreased, the zero frequency

C

will be kept the same, thereby keeping the phase shift the

same in the most critical frequency range of the feedback

loop. The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

load current. When a load step occurs, V

shifts by an

OUT

amount equal to ∆I

, where ESR is the effective

also begins to charge or

LOAD

LOAD (ESR)

series resistance of C . ∆I

OUT

discharge C

generating the feedback error signal that

the actual overall supply performance.

OUT

3856f

ꢂꢁ

LTC3856

applicaTions inForMaTion

A second, more severe transient is caused by switching

in loads with large (>1µF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

A 2µH inductor will produce 20% ripple current. The peak

inductor current will be the maximum DC value plus one

half the ripple current, or 11A. The minimum on-time oc-

with C , causing a rapid drop in V . No regulator can

curs at maximum V :

OUT

IN

V_OUT

V_INf

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

1.8V

t_{ON MIN}

=

=1.1µs

(

)

5.5V 300kHz

(

)(

)

C

to C

is greater than 1:50, the switch rise time

LOAD

OUT

With the ILIM pin tied to ground, the R

resistors

SENSE

should be controlled so that the load rise time is limited

to approximately 25 • C . Thus a 10µF capacitor would

value can be calculated by using the minimum current

sense voltage speciﬁcation with some accommodation

for tolerances:

LOAD

require a 250µs rise time, limiting the charging current

to about 200mA.

25mV

11A

R_SENSE

=

≈ 0.002Ω

Design Example (Using Two Phases)

As a design example, assume:

Choosing 1% resistors: R1 = 10k and R2 = 20k yields an

output voltage of 1.80V.

V = 5V (nominal)

IN

V = 5.5V (max),

The power dissipation on the topside MOSFET can be

easily estimated. Using a Siliconix Si4420DY for example;

IN

V

= 1.8V,

= 20A

OUT

MAX

R

= 0.013Ω, C

= 300pF. At maximum input

DS(ON)

RSS

I

voltagewithT (estimated)=110°Catanelevatedambient

J

T = 70°C

A

temperature:

f = 300kHz

1.8V

5.5V

²



P_MAIN

=

10 1+ 0.005 110°C − 25°C

(

)

(

)(

)





Theinductancevalueischosenﬁrstbasedona30%ripple

current assumption. The highest value of ripple current

occursatthemaximuminputvoltage. Usea71.5kresistor

from FREQ to ground to set the switching frequency at

about 300kHz. The minimum inductance for 30% ripple

current is:







10A

²

• 0.013Ω + 5.5V

2Ω 300pF

(

)

(

)(

)

 2 









1

+

• 300kHz

(

)

 5V − 2.6V 2.6V





V_OUT

f ∆I

( )

V_OUT

V_IN

= 0.606 + 0.022 = 0.628W

L ≥

1−









The worst-case power dissipated by the synchronous

MOSFET under normal operating conditions at elevated

ambient temperature and estimated 50°C junction

temperature rise is:

1.8V

5.5V





≥

1−









300kHz 30% 10A

)( )(

(

)

≥1.35µH

5.5V − 1.8V

5.5V

= 1.09W

2

P_SYNC

=

10A 1.25 0.013Ω

(

) (

)(

)

3856f

ꢂꢂ

LTC3856

applicaTions inForMaTion

A short-circuit to ground will result in a folded back

current of:

input voltage, which is 5.5V, that provides a duty cycle

nearest to the peak.

From Figure 10, C will require an RMS current rating of:

25mV

IN









90ns 5.5V

(

)

1

2

3

I_SC

=

−

= 4.04A

C_INrequired I_RMS= 20A 0.23

(

)(

)

0.002Ω

2µH









= 4.6A_RMS

The worst-case power dissipated by the synchronous

MOSFET under short-circuit conditions at elevated ambi-

ent temperature and estimated 50°C junction temperature

rise is:

The output capacitor ripple current is calculated by using

theinductorripplealreadycalculatedforeachinductorand

multiplyingbythefactorobtainedfromFigure8alongwith

the calculated duty factor. The output ripple in continuous

mode will be highest at the maximum input voltage. From

Figure 8, the maximum output current ripple is:

5.5V − 1.8V

5.5V

= 0.18W

2

P_SYNC

=

4.04A 1.25 0.013Ω

(

) (

)(

)

V_OUT

fL

∆I_COUT

=

0.34

(

)

which is much less than normal, full-load conditions.

Incidentally, since the load no longer dissipates power in

the shorted condition, total system power dissipation is

decreased by over 99%.

1.8 0.34

300kHz 2µH

)(

(

)

∆I_COUTMAX

=

= 1A

(

)

Note that the PolyPhase technique will have its maximum

beneﬁtforinputandoutputripplecurrentswhenthenumber

of phases times the output voltage is approximately equal

to or greater than the input voltage.

ThedutycycleswhenthepeakRMSinputcurrentoccursis

at D = 0.25 and D = 0.75 according to Figure 10. Calculate

the worst-case required RMS input current rating at the

3856f

ꢂꢃ

LTC3856

applicaTions inForMaTion

PC Board Layout Checklist

4. Do the (+) plates of C

connect to the drains of the

PWR

topsideMOSFETsascloselyaspossible?Thiscapacitor

provides the pulsed current to the MOSFETs.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layout diagram of Figure 17. Check the following in the

PC layout:

5. Keeptheswitchingnodes,SWn,BOOSTnandTGnaway

+

–

from sensitive small-signal nodes (SENSE , SENSE ,

DIFFP, DIFFN, V , ITEMP). Ideally the SWn, BOOSTn

FB

and TGn printed circuit traces should be routed away

and separated from the IC and especially the “quiet”

sideoftheIC.Separatethehighdv/dttracesfromsensi-

tive small-signal nodes with ground traces or ground

planes.

1. ArethesignalandpowergroundpathsKelvinconnected?

Keep the SGND at one end of a printed circuit path thus

preventing MOSFET currents from traveling under the

IC. The INTV decoupling capacitor should be placed

CC

immediately adjacent to the IC between the INTV pin

CC

and PGND plane. A 1µF ceramic capacitor of the X7R or

X5R type is small enough to ﬁt very close to the IC to

minimizetheilleffectsofthelargecurrentpulsesdrawn

todrivethebottomMOSFETs.Anadditional5µFto10µF

of ceramic, tantalum or other very low ESR capacitance

is recommended in order to keep the internal IC supply

quiet. The power ground returns to the sources of the

bottom N-channel MOSFETs, anodes of the Schottky

6. Usealowimpedancesourcesuchasalogicgatetodrive

the PLLIN pin and keep the lead as short as possible.

7. The 47pF to 330pF ceramic capacitor between the I

TH

pinandsignalgroundshouldbeplacedascloseaspos-

sible to the IC. Figure 17 illustrates all branch currents

in a 2-phase switching regulator. It becomes very clear

afterstudyingthecurrentwaveformswhyitiscriticalto

keepthehighswitchingcurrentpathstoasmallphysical

size. High electric and magnetic ﬁelds will radiate from

these loops just as radio stations transmit signals. The

output capacitor ground should return to the negative

terminal of the input capacitor and not share a common

ground path with any switched current paths. The left

half of the circuit gives rise to the noise generated by

a switching regulator. The ground terminations of the

synchronous MOSFETs and Schottky diodes should

return to the bottom plate(s) of the input capacitor(s)

with a short isolated PC trace since very high switched

currents are present. External OPTI-LOOP^®compensa-

tion allows overcompensation for PC layouts which are

not optimized, but this is not the recommended design

procedure.

diodesand(–)platesofC , whichshouldhaveasshort

IN

lead lengths as possible.

2. Does the IC DIFFP pin connect to the (+) plates of

C

? A 30pF to 300pF feedforward capacitor between

OUT

the DIFFP and V pins should be placed as close as

FB

possible to the IC.

–

+

3. Are the SENSE and SENSE printed circuit traces for

each channel routed together with minimum PC trace

+

spacing? The ﬁlter capacitors between SENSE and

–

SENSE foreachchannelshouldbeascloseaspossible

–

+

to the pins of the IC. Connect the SENSE and SENSE

pins to the pads of the sense resistor as illustrated in

Figure 1.

3856f

ꢂꢄ

LTC3856

applicaTions inForMaTion

L1

SW1

R

SENSE1

D1

V

OUT

IN

R

IN

C

OUT

+

C

R

L

IN

SW2

L2

R

SENSE2

D2

BOLD LINES INDICATE

HIGH, SWITCHING

CURRENT LINES.

KEEP LINES TO A

MINIMUM LENGTH.

3856 F17

Figure 1ꢀ. Instantaneous Current Path Flow in a Multiple Phase Switching Regulation

3856f

ꢂꢅ

LTC3856

Typical applicaTion

V

IN

V

IN

4.5V

+

TO 14V

180µF

16V

s 2

1nF

V

IN

V

S

IN

0.1µF

2.2Ω

100Ω 100Ω

1nF

5.6k

S

Q1

22µF

100pF

RJK0305DPB

S

22µF

GND

L1

Q5

–

+

0.22µH

CLKOUT

V

SENSE1

IN

RJK0305DPB

0.001Ω

V

1.5V/

50A

OUT

PLLIN

FREQ

RUN

100k, 1%

100µF

0.1µF

Q6

RJK0330DPB

TG1

6.3V

Q2

+

330µF

2.5V

s 4

SW1

s 4

RJK0330DPB

0.1µF

TK/SS

4.7µF

6.3V

INTV

CC

BOOST1

BG1

I

TH

20k

D1, CMDSH-3

V

IN

S

V

FB

LTC3856

INTV

CC

4.7µF

Q3

INTV

CC

22µF

AVP

RJK0305DPB

22µF

ITEMP

PHASMD

DIFFP

30.1k

Q7

TG2

L2

RJK0305DPB

D2, CMDSH-3

BOOST2

0.22µH

0.001Ω

INTV

CC

DIFFN

DIFFOUT

ISET

0.1µF

Q8

RJK0330DPB

Q4

SW2

BG2

RJK0330DPB

EXTV

ILIM

CC

INTV

CC

+

SENSE2

100k

1nF

MODE

PGOOD PGND SGND SENSE2

–

S

PGOOD

100Ω

S

10Ω

3856 F18

Figure 18. 1.5V/5±A Converter Using Sense Resistors

3856f

ꢂꢆ

LTC3856

package DescripTion

FE Package

38-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1772 Rev A)

Exposed Pad Variation AA

4.75 REF

9.60 – 9.80*

(.378 – .386)

4.75

(.187)

REF

38

20

6.60 0.10

2.74 REF

4.50 REF

SEE NOTE 4

6.40

REF (.252)

BSC

2.74

(.108)

0.315 0.05

1.05 0.10

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

19

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0o – 8o

0.50

(.0196)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.17 – 0.27

FE38 (AA) TSSOP 0608 REV A

(.0067 – .0106)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

2. DIMENSIONS ARE IN

FOR EXPOSED PAD ATTACHMENT

MILLIMETERS

(INCHES)

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

3. DRAWING NOT TO SCALE

3856f

ꢂꢇ

LTC3856

package DescripTion

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693 Rev D)

0.57 p 0.05

5.35 p 0.05

4.20 p 0.05

3.45 p 0.05

(4 SIDES)

PACKAGE OUTLINE

0.23 p 0.05

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

BOTTOM VIEW—EXPOSED PAD

R = 0.115

TYP

0.75 p 0.05

0.40 p 0.10

5.00 p 0.10

(4 SIDES)

31 32

0.00 – 0.05

PIN 1

TOP MARK

1

2

3.45 p 0.10

(4-SIDES)

(UH) QFN 0102

0.200 REF

0.23 p 0.05

0.50 BSC

NOTE:

1. DRAWING PROPOSED TO INCLUDE JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

3856f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

ꢂꢈ

LTC3856

Typical applicaTion

V

IN

V

IN

4.5V

TO 14V

+

180µF

16V

s 2

330pF

47pF

V

IN

V

IN

S

0.1µF

2.2Ω

200Ω 200Ω

1nF

2.68k

S

Q1

22µF

RJK0305DPB

S

22µF

GND

L1

0.22µH

Q5

–

+

CLKOUT

PLLIN

FREQ

V

SENSE1

IN

RJK0305DPB

V

1.5V/

50A

0.001Ω

OUT

100k

100µF

0.1µF

Q6

RJK0330DPB

TG1

6.3V

Q2

330µF

2.5V

s 4

+

RUN

SW1

s 2

RJK0330DPB

INTV

0.1µF

TK/SS

4.7µF

6.3V

CC

I

TH

BOOST1

BG1

CMDSH-3

20k

V

IN

S

V

FB

INTV

49.9Ω

CC

LTC3856

Q3

INTV

CC

22µF

AVP

RJK0305DPB

S

22µF

ITEMP

PHASMD

DIFFP

4.7µF

100pF

30.1k

Q7

TG2

L2

0.22µH

RJK0305DPB

S

CMDSH-3

INTV

BOOST2

0.001Ω

DIFFN

DIFFOUT

ISET

CC

0.1µF

Q8

RJK0330DPB

Q4

SW2

BG2

RJK0330DPB

EXTV

ILIM

CC

INTV

CC

+

SENSE2

100Ω

100k

PGOOD

1nF

MODE

PGOOD PGND SGND SENSE2

–

S

200Ω

S

10Ω

–

+

V

S

O_SNS

3856 F19

Figure 19. 1.5V/5±A Converter with AVP

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

Phase-Lockable Fixed 250kHz to 770kHz Frequency,

4.5V ≤ V ≤ 38V, 0.8V ≤ V ≤ 5V

LTC3829

3-Phase, Single Output, Synchronous Step-Down Controller

with Diffamp and DCR Temperature Compensation

IN

OUT

LTC3860

LTC3855

LTC3853

Dual, Multiphase, Synchronous Step-Down DC/DC Controller

with Diffamp and Three-State Output Drive

Operates with Power Blocks, DRMOS Devices or External

MOSFETs, 3V ≤ V ≤ 24V, t = 20ns

IN

ON(MIN)

Dual, Multiphase, Synchronous Step-Down DC/DC Controller

with Diffamp and DCR Temperature Compensation

Phase-Lockable Fixed Frequency 250kHz to 770kHz,

4.5V ≤ V ≤ 38V, 0.8V ≤ V ≤ 12V

IN

OUT

Triple Output, Multiphase, Synchronous Step-Down DC/DC

Phase-Lockable Fixed 250kHz to 750kHz Frequency,

4V ≤ V ≤ 24V, V Up to 13.5V

Controller, R

or DCR Current Sensing and Tracking

SENSE

IN

OUT3

LTC3850/LTC3850-1/ Dual 2-Phase, High Efﬁciency, Synchronous Step-Down

Phase-Lockable Fixed 250kHz to 780kHz Frequency,

LTC3850-2

DC/DC Controller, R

SENSE

or DCR Current Sensing and Tracking 4V ≤ V ≤ 30V, 0.8V ≤ V ≤ 5.25V

IN

OUT

3856f

LT 0510 • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

ꢃ0

●

ꢀLINEAR TECHNOLOGY CORPORATION 2010

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3856EUH-TRPBF
厂家：	Linear
描述：	2-Phase Synchronous Step-Down DC/DC Controller with Diffamp 两相同步降压型DC / DC与Diffamp控制器控制器
文件：	总40页 (文件大小：2221K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3856EUH-TRPBF [Linear]

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