LTC3857EGN-1#PBF_技术文档

LTC3857-1

Low I , Dual, 2-Phase

Q

Synchronous Step-Down

Controller

FEATURES

DESCRIPTION

The LTC^®3857-1 is a high performance dual step-down

switching regulator controller that drives all N-channel

synchronouspowerMOSFETstages.Aconstantfrequency

current mode architecture allows a phase-lockable fre-

quency of up to 850kHz. Power loss and noise due to the

ESRoftheinputcapacitorESRareminimizedbyoperating

the two controller output stages out of phase.

n

Low Operating I : 50μA (One Channel On)

Q

n

Wide Output Voltage Range: 0.8V ≤ V

≤ 24V

OUT

Wide V Range: 4V to 38V

IN

R

or DCR Current Sensing

SENSE

Out-of-Phase Controllers Reduce Required Input

Capacitance and Power Supply Induced Noise

OPTI-LOOP^®Compensation Minimizes C

n

OUT

Phase-Lockable Frequency (75kHz-850kHz)

Programmable Fixed Frequency (50kHz-900kHz)

Selectable Continuous, Pulse-Skipping or Low Ripple

Burst Mode^®Operation at Light Loads

The 50ꢀA no-load quiescent current extends operating life

in battery-powered systems. The LTC3857-1 features a

precision0.8Vreferenceandapowergoodoutputindicator.

A wide 4V to 38V input supply range encompasses a wide

rangeofintermediatebusvoltagesandbatterychemistries.

n

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Output Voltage Soft-Start or Tracking

Power Good Output Voltage Monitor

Independent TRACK/SS pins for each controller ramp the

output voltages during start-up. Current foldback limits

MOSFET heat dissipation during short-circuit conditions.

The PLLIN/MODE pin selects among Burst Mode opera-

tion,pulse-skippingmode,orcontinuousinductorcurrent

mode at light loads.

Output Overvoltage Protection

Low Shutdown I : <8μA

Internal LDO Powers Gate Drive from V or EXTV

No Current Foldback During Start-Up

Narrow SSOP Package

Q

IN

CC

For a leadless 32-pin QFN package with the additional fea-

tures of adjustable current limit, clock out, phase modula-

tionandtwoPGOODoutputs,seetheLTC3857datasheet.

L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, μModule, Linear Technology and the Linear logo

APPLICATIONS

n

Automotive Always-On Systems

Battery Operated Digital Devices

n

are registered trademarks and No R

and UltraFast are trademarks of Linear Technology

SENSE

n

Distributed DC Power Systems

Corporation. All other trademarks are the property of their respective owners. Protected by

U.S. Patents, including 5481178, 5929620, 6177787, 6144194, 5408150, 6580258, 5705919,

6100678.

TYPICAL APPLICATION

High Efficiency Dual 3.3V/8.5V Step-Down Converter

V

Efficiency and Power Loss

IN

9V TO 38V

22μF

50V

vs Output Current

1μF

100

90

10000

1000

100

10

V

IN

INTV

CC

V

= 12V

IN

OUT

TG1

TG2

= 3.3V

0.1μF

FIGURE 13 CIRCUIT

BOOST1

SW1

BOOST2

SW2

80

3.3μH

7.2μH

70

BG1

BG2

60

50

LTC3857-1

PGND

+

40

30

20

10

0

SENSE1

SENSE2

0.010Ω

193k

0.007Ω

1

–

V

8.5V

3.5A

SENSE2

OUT2

V

OUT1

3.3V

5A

V

FB1

FB2

62.5k

I

TH2

TH1

TRACK/SS1 SGND TRACK/SS2

0.1μF

0.1

150μF

680pF

15k

680pF

150μF

0.000010.0001 0.001 0.01

0.1

1

10

20k

OUTPUT CURRENT (A)

20k

15k

0.1μF

3857 TA01b

38571 TA01

38571fc

1

LTC3857-1

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

Input Supply Voltage (V )......................... –0.3V to 40V

IN

Topside Driver Voltages

1

TRACK/SS1

PGOOD1

TG1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

I

TH1

2

3

V

BOOST1, BOOST2 ................................. –0.3V to 46V

Switch Voltage (SW1, SW2) ........................ –5V to 40V

FB1

+

SENSE1

–

4

SW1

(BOOST1-SW1), (BOOST2-SW2), INTV ... –0.3V to 6V

CC

5

BOOST1

BG1

FREQ

PLLIN/MODE

SGND

RUN1, RUN2................................................ –0.3V to 8V

6

Maximum Current Sourced into Pin

7

V

IN

from Source >8V...............................................100μA

8

PGND

RUN1

+

–

+

–

SENSE1 , SENSE2 , SENSE1

9

EXTV

CC

RUN2

SENSE2 Voltages...................................... –0.3V to 28V

–

10

11

12

13

14

INTV

CC

SENSE2

PLLIN/MODE, FREQ Voltages .............. –0.3V to INTV

+

CC

BG2

SENSE2

EXTV ...................................................... –0.3V to 14V

CC

BOOST2

SW2

V

FB2

TH2

I

, I ,V , V Voltages ...................... –0.3V to 6V

TH1 TH2 FB1 FB2

I

PGOOD1 Voltage ......................................... –0.3V to 6V

TRACK/SS1, TRACK/SS2 Voltages .............. –0.3V to 6V

Operating Junction Temperature Range

(Note 2).................................................. –40°C to 125°C

Maximum Junction Temperature (Note 3) ............ 125°C

Storage Temperature Range................... –65°C to 150°C

TG2

TRACK/SS2

GN PACKAGE

28-LEAD PLASTIC SSOP

T

= 125°C, θ = 90°C/W

JA

JMAX

ORDER INFORMATION

LEAD FREE FINISH

LTC3857EGN-1#PBF

LTC3857IGN-1#PBF

TAPE AND REEL

PART MARKING*

LTC3857GN-1

PACKAGE DESCRIPTION

28-Lead Plastic SSOP

TEMPERATURE RANGE

–40°C to 125°C

LTC3857EGN-1#TRPBF

LTC3857IGN-1#TRPBF

–40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

38571fc

2

LTC3857-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating junction

temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= 12V, V_RUN1,2= 5V, EXTV_CC= 0V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Input Supply Operating Voltage Range

Regulated Feedback Voltage

4

38

V

IN

(Note 4) I

Voltage = 1.2V

FB1,2

TH1,2

–40°C to 125°C

–40°C to 85°C

l

0.788

0.792

0.800

0.812

0.808

V

I

Feedback Current

(Note 4)

5

50

nA

FB1,2

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

(Note 4) V = 4.5V to 38V

0.002

0.02

%/V

REFLNREG

LOADREG

IN

(Note 4)

l

Measured in Servo Loop,

0.01

0.1

%

ΔI Voltage = 1.2V to 0.7V

TH

(Note 4)

Measured in Servo Loop,

–0.01

2

–0.1

%

ΔI Voltage = 1.2V to 2V

TH

g

m1,2

Transconductance Amplifier g

Input DC Supply Current

(Note 4) I = 1.2V, Sink/Source = 5μA

TH1,2

mmho

m

I

Q

(Note 5)

Pulse-Skipping or Forced Continuous RUN1 = 5V and RUN2 = 0V, V = 0.83V (No Load) or

2

mA

μA

FB1

Mode (One Channel On)

RUN1 = 0V and RUN2 = 5V, V = 0.83V (No Load)

FB2

Pulse-Skipping or Forced Continuous RUN1,2 = 5V, V

Mode (Both Channels On)

= 0.83V (No Load)

FB1,2

Sleep Mode (One Channel On)

RUN1 = 5V and RUN2 = 0V, V = 0.83V (No Load) or

50

75

FB1

RUN1 = 0V and RUN2 = 5V, V = 0.83V (No Load)

FB2

Sleep Mode (Both Channels On)

Shutdown

RUN1,2 = 5V, V

RUN1,2 = 0V

= 0.83V (No Load)

65

8

120

20

μA

FB1,2

l

UVLO

Undervoltage Lockout

INTV Ramping Up

4.0

3.8

4.2

4

V

CC

INTV Ramping Down

3.6

7

CC

V

Feedback Overvoltage Protection

Measured at V , Relative to Regulated V

FB1,2 FB1,2

Each Channel

10

13

1

%

OVL

+

–

+

I

SENSE Pin Current

μA

SENSE

–

SENSE Pins Current

Each Channel

–

V

SENSE

V

SENSE

< INTV – 0.5V

1

μA

CC

> INTV + 0.5V

550

99.4

1.0

CC

DF

MAX

Maximum Duty Factor

In Dropout, FREQ = 0V

98

0.7

%

μA

V

I

Soft-Start Charge Current

V = 0V

TRACK1,2

1.4

TRACK/SS1,2

l

V

On RUN Pin On Threshold

Hyst RUN Pin Hysteresis

V , V Rising

RUN1 RUN2

1.21

1.26

50

1.31

RUN1,2

mV

RUN1,2

Maximum Current Sense Threshold

V

FB1,2

= 0.7V, V –, – = 3.3V

SENSE1 2

43

50

57

SENSE(MAX)

Gate Driver

TG1,2

Pull-Up On-Resistance

Pull-Down On-Resistance

2.5

1.5

ꢁ

BG1,2

Pull-Up On-Resistance

Pull-Down On-Resistance

2.4

1.1

ꢁ

TG Transition Time:

Rise Time

Fall Time

(Note 6)

TG1,2 t

C

= 3300pF

25

16

ns

r

f

LOAD

= 3300pF

BG Transition Time:

Rise Time

Fall Time

(Note 6)

LOAD

BG1,2 t

C

= 3300pF

28

13

ns

r

f

38571fc

3

LTC3857-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating junction

temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= 12V, V_RUN1,2= 5V, EXTV_CC= 0V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

TG/BG t

Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

C

LOAD

= 3300pF Each Driver

30

ns

1D

BG/TG t

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

C

= 3300pF Each Driver

30

95

ns

1D

LOAD

t

Minimum On-Time

(Note 7)

ON(MIN)

INTV Linear Regulator

CC

V

Internal V Voltage

6V < V < 38V, V = 0V

EXTVCC

4.85

4.5

5.1

0.7

5.1

0.6

4.7

250

5.35

1.1

V

%

V

INTVCCVIN

LDOVIN

CC

IN

INTV Load Regulation

I

CC

= 0mA to 50mA, V

= 0V

CC

EXTVCC

Internal V Voltage

6V < V < 13V

EXTVCC

5.35

1.1

INTVCCEXT

LDOEXT

CC

INTV Load Regulation

I

CC

= 0mA to 50mA, V

= 8.5V

%

V

CC

EXTVCC

EXTV Switchover Voltage

EXTV Ramping Positive

4.9

EXTVCC

CC

EXTV Hysteresis

mV

LDOHYS

CC

Oscillator and Phase-Locked Loop

f

Programmable Frequency

Low Fixed Frequency

R

= 25k, PLLIN/MODE = DC Voltage

= 65k, PLLIN/MODE = DC Voltage

= 105k, PLLIN/MODE = DC Voltage

= 0V, PLLIN/MODE = DC Voltage

105

440

835

350

535

kHz

25kꢁ

65kꢁ

105kꢁ

LOW

FREQ

375

505

V

320

485

75

380

585

850

High Fixed Frequency

= INTV , PLLIN/MODE = DC Voltage

CC

HIGH

SYNC

l

Synchronizable Frequency

PLLIN/MODE = External Clock

PGOOD1 Output

V

PGOOD1 Voltage Low

PGOOD1 Leakage Current

PGOOD1 Trip Level

I

= 2mA

= 5V

0.2

0.4

1

V

PGL

PGOOD

I

V

μA

PGOOD

V

PG

with Respect to Set Regulated Voltage

Ramping Negative

FB1

–13

7

–10

2.5

–7

13

%

Hysteresis

V

with Respect to Set Regulated Voltage

Ramping Positive

FB1

10

2.5

%

Hysteresis

t

Delay for Reporting a Fault

25

μs

PG

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Ratings for extended periods may affect device reliability and

lifetime.

Note 3: T is calculated from the ambient temperature T and power

J A

dissipation P according to the following formula:

D

T = T + (P • 90°C/W)

J

A

D

Note 4: The LTC3857-1 is tested in a feedback loop that servos V

to

ITH1,2

Note 2: The LTC3857-1 is tested under pulsed conditions such that

a specified voltage and measures the resultant V . The specification at

FB1,2

T

≈

T . The LTC3857E-1 is guaranteed to meet performance specifications

J

A

85°C is not tested in production. This specification is assured by design,

characterization and correlation to production testing at 125°C.

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications information.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 7: The minimum on-time condition is specified for an inductor

from 0°C to 85°C. Specifications over the –40°C to 125°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls. The LTC3857I-1 is guaranteed

over the full –40°C to 125°C operating junction temperature range. Note

that the maximum ambient temperature is determined by specific operating

conditions in conjunction with board layout, the rated package thermal

resistance and other environmental factors.

peak-to-peak ripple current ≥40% of I

(See Minimum On-Time

MAX

Considerations in the Applications Information section).

38571fc

4

LTC3857-1

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency and Power Loss

Efficiency vs Output Current

Efficiency vs Input Voltage

vs Output Current

100

90

10000

1000

100

10

100

90

98

96

94

92

90

88

86

84

82

80

V

= 12V

IN

OUT

V

LOAD

= 3.3V

= 5A

OUT

= 3.3V

I

V

IN

= 5V

FIGURE 13 CIRCUIT

80

70

V

IN

= 12V

60

50

60

50

40

30

20

10

0

40

30

20

10

0

1

V

= 3.3V

OUT

FIGURE 13 CIRCUIT

0.1

0.000010.0001 0.001 0.01

0.1

1

10

20 25

10 15

INPUT VOLTAGE (V)

0.000010.0001 0.001 0.01

0.1

1

10

1

5

30 35 40

38571 G01

OUTPUT CURRENT (A)

BURST EFFICIENCY

PULSE-SKIPPING

EFFICIENCY

BURST LOSS

38571 G02

38571 G03

PULSE-SKIPPING

LOSS

CCM EFFICIENCY

CCM LOSS

Load Step

(Forced Continuous Mode)

Load Step

(Pulse-Skipping Mode)

Load Step (Burst Mode Operation)

V

OUT

100mV/DIV

INDUCTOR

CURRENT

2A/DIV

INDUCTOR

CURRENT

2A/DIV

INDUCTOR

CURRENT

2A/DIV

38571 G04

38571 G05

38571 G06

V

= 12V

20μs/DIV

V

= 12V

20μs/DIV

V

= 12V

20μs/DIV

IN

OUT

IN

OUT

IN

OUT

= 3.3V

FIGURE 13 CIRCUIT

Inductor Current at Light Load

Soft Start-Up

Tracking Start-Up

FORCED

CONTINUOUS

MODE

V

OUT2

2V/DIV

V

OUT2

2V/DIV

Burst Mode

OPERATION

1A/DIV

V

OUT1

2V/DIV

V

OUT1

2V/DIV

PULSE-

SKIPPING

MODE

38571 G08

38571 G07

38571 G09

20ms/DIV

FIGURE 13 CIRCUIT

V

LOAD

= 12V

5μs/DIV

20ms/DIV

FIGURE 13 CIRCUIT

IN

= 3.3V

OUT

I

= 200μA

FIGURE 13 CIRCUIT

38571fc

5

LTC3857-1

TYPICAL PERFORMANCE CHARACTERISTICS

Total Input Supply Current

vs Input Voltage

EXTV_CCSwitchover and INTV_CC

Voltages vs Temperature

INTV_CCLine Regulation

500

450

400

350

300

250

200

150

100

50

6.0

5.8

5.6

5.4

5.2

5.0

4.8

4.6

4.4

4.2

4.0

5.2

5.1

5.0

4.9

4.8

V

= 3.3V

OUT1

RUN2 = 0V

FIGURE 13 CIRCUIT

INTV

CC

500μA

EXTV RISING

CC

300μA

EXTV FALLING

CC

NO LOAD

0

5

15

20

25

30

35

40

–45

5

30

55

80

130

20 25

INPUT VOLTAGE (V)

10

–20

105

0

5

10 15

30 35 40

INPUT VOLTAGE (V)

TEMPERATURE (°C)

38571 G10

38571 G11

38571 G12

Maximum Current Sense Voltage

vs I_THVoltage

Maximum Current Sense

Threshold vs Duty Cycle

SENSE^–Pin Input Bias Current

80

60

40

20

0

–50

80

60

40

20

0

5% DUTY CYCLE

–100

–150

–200

–250

–300

–350

–400

–450

–500

–550

–600

PULSE-SKIPPING MODE

Burst Mode

OPERATION

0

–20

–40

FORCED CONTINUOUS MODE

0.8

(V)

1.2

1.4

0

10

COMMON MODE VOLTAGE (V)

15

20

25

0

0.2

0.4 0.6

V

1.0

5

0

10 20 30 40 50 60 70 80 90 100

V

DUTY CYCLE (%)

SENSE

ITH

38571 G13

38571 G14

38571 G15

INTV_CCand EXTV_CC

vs Load Current

Foldback Current Limit

Quiescent Current vs Temperature

80

5.20

5.15

5.10

90

80

70

60

50

40

30

20

10

V

IN

= 12V

75

70

65

60

55

50

45

EXTV = 0V

CC

5.05

5.00

4.95

EXTV = 8.5V

CC

40

0

–20

5

55

80 105 130

0

20 40 60

120 140 160 180 200

–45

30

80 100

0

0.1 0.2 0.3 0.4 0.5

0.9

0.6 0.7 0.8

TEMPERATURE (°C)

LOAD CURRENT (mA)

FEEDBACK VOLTAGE (V)

38571 G17

38571 G18

38571 G16

38571fc

6

LTC3857-1

TYPICAL PERFORMANCE CHARACTERISTICS

Regulated Feedback Voltage

vs Temperature

TRACK/SS Pull-Up Current

vs Temperature

Shutdown (RUN) Threshold

vs Temperature

1.40

1.35

1.30

1.25

1.10

1.05

1.00

0.95

800

806

804

RUN RISING

802

800

798

796

794

RUN FALLING

1.20

1.15

1.10

0.90

792

55

TEMPERATURE (°C)

105 130

–45 –20

5

30

80

–45 –20

5

30

55

80 105 130

–20

5

55

80 105 130

–45

30

TEMPERATURE (°C)

38571 G20

38571 G19

3857 G21

SENSE^–Pin Input Current

vs Temperature

Shutdown Current

vs Input Voltage

Oscillator Frequency

vs Temperature

50

0

–50

30

25

20

15

600

550

500

450

V

OUT

< INTV – 0.5V

CC

FREQ = INTV

CC

–100

–150

–200

–250

–300

–350

–400

–450

–500

–550

–600

10

5

400

350

300

FREQ = GND

V

5

> INTV – 0.5V

CC

OUT

0

25

INPUT VOLTAGE (V)

35

40

5

10

15

20

30

55

TEMPERATURE (°C)

105 130

–45 –20

5

30

80

–45 –20

30

55

80 105 130

TEMPERATURE (°C)

38571 G22

38571 G23

38571 G24

Oscillator Frequency

vs Input Voltage

Undervoltage Lockout Threshold

vs Temperature

Shutdown Current vs Temperature

4.4

4.3

4.2

4.1

4.0

3.9

3.8

3.7

3.6

3.5

3.4

356

354

352

350

20

FREQ = GND

18

16

14

12

10

8

348

346

344

6

4

25

INPUT VOLTAGE (V)

35

40

–45

5

30

55

80 105 130

5

10

15

20

30

–20

5

55

TEMPERATURE (°C)

80 105 130

–20

–45

30

TEMPERATURE (°C)

38571 G25

38571 G26

38571 G27

38571fc

7

LTC3857-1

PIN FUNCTIONS

TH1 TH2

Switching Regulator Compensation Points. Each associ-

ated channel’s current comparator trip point increases

with this control voltage.

I

, I

(Pin 1, Pin 13): Error Amplifier Outputs and

invokes Burst Mode operation when the pin is floated.

TyingthispintoINTV forcescontinuousinductorcurrent

CC

operation. Tying this pin to a voltage greater than 1.2V and

less than INTV – 1.3V selects pulse-skipping operation.

CC

This can be done by adding a 100k resistor between the

V

, V (Pin 2, Pin 12): Receives the remotely sensed

FB1 FB2

PLLIN/MODE pin and INTV .

CC

feedback voltage for each controller from an external

resistive divider across the output.

SGND (Pin 7): Small-signal ground common to both

controllers, must be routed separately from high current

groundstothecommon(–)terminalsoftheC_INcapacitors.

+

SENSE1 , SENSE2 (Pin 3, Pin 11): The (+) input to the

differential current comparators are normally connected

to DCR sensing networks or current sensing resistors.

RUN1, RUN2 (Pin 8, Pin 9): Digital Run Control Inputs for

Each Controller. Forcing either of these pins below 1.26V

shutsdownthatcontroller.Forcingbothofthesepinsbelow

0.7VshutsdowntheentireLTC3857-1,reducingquiescent

current to approximately 8μA. Do not float these pins.

The I pin voltage and controlled offsets between the

TH

–

+

SENSE and SENSE pins in conjunction with R

the current trip threshold.

set

SENSE

–

SENSE1 , SENSE2 (Pin 4, Pin 10): The (–) Input to

the Differential Current Comparators. When greater than

INTV (Pin19):OutputoftheInternalLinearLowDropout

CC

–

INTV – 0.5V, the SENSE pin supplies current to the

Regulator.Thedriverandcontrolcircuitsarepoweredfrom

this voltage source. Must be decoupled to power ground

with a minimum of 4.7μF ceramic or other low ESR ca-

CC

current comparator.

FREQ (Pin 5): The Frequency Control Pin for the Internal

pacitor. Do not use the INTV pin for any other purpose.

CC

VCO. Connecting the pin to GND forces the VCO to a fixed

low frequency of 350kHz. Connecting the pin to INTV

EXTV (Pin 20): External Power Input to an Internal LDO

CC

forces the VCO to a fixed high frequency of 535kHz.

Other frequencies between 50kHz and 900kHz can be

programmed using a resistor between FREQ and GND.

An internal 20μA pull-up current develops the voltage to

be used by the VCO to control the frequency

Connected to INTV . This LDO supplies INTV power,

CC

bypassing the internal LDO powered from V whenever

IN

EXTV is higher than 4.7V. See EXTV Connection in

CC

the Applications Information section. Do not exceed 14V

on this pin.

PLLIN/MODE (Pin 6): External Synchronization Input to

PhaseDetectorandForcedContinuousModeInput. When

an external clock is applied to this pin, the phase-locked

loop will force the rising TG1 signal to be synchronized

with the rising edge of the external clock. When not syn-

chronizing to an external clock, this input, which acts on

both controllers, determines how the LTC3857-1 operates

at light loads. Pulling this pin to ground selects Burst

Mode operation. An internal 100k resistor to ground also

PGND (Pin 21): Driver Power Ground. Connects to the

sources of bottom (synchronous) N-channel MOSFETs

and the (–) terminal(s) of C .

IN

V (Pin 22): Main Supply Pin. A bypass capacitor should

IN

be tied between this pin and the signal ground pin.

BG1, BG2 (Pin 23, Pin 18): High Current Gate Drives

for Bottom (Synchronous) N-Channel MOSFETs. Voltage

swing at these pins is from ground to INTV .

CC

38571fc

8

LTC3857-1

PIN FUNCTIONS

BOOST1,BOOST2(Pin24,Pin17):BootstrappedSupplies

to the Topside Floating Drivers. Capacitors are connected

betweentheBOOSTandSWpinsandSchottkydiodesare

tied between the BOOST and INTV_CCpins. Voltage swing

at the BOOST pins is from INTV_CCto (V_IN+ INTV_CC).

PGOOD1 (Pin 27): Open-Drain Logic Output. PGOOD1 is

pulled to ground when the voltage on the V pin is not

FB1

within 10% of its set point.

TRACK/SS1, TRACK/SS2(Pin28, Pin14):ExternalTrack-

ing and Soft-Start Input. The LTC3857-1 regulates the

SW1, SW2 (Pin 25, Pin 16): Switch Node Connections

to Inductors.

V

FB1,2

voltage to the smaller of 0.8V or the voltage on the

TRACK/SS1,2 pin. An internal 1μA pull-up current source

is connected to this pin. A capacitor to ground at this

pin sets the ramp time to final regulated output voltage.

Alternatively, a resistor divider on another voltage supply

connectedtothispinallowstheLTC3857-1outputtotrack

the other supply during start-up.

TG1, TG2 (Pin 26, Pin 15): High Current Gate Drives for

Top N-Channel MOSFETs. These are the outputs of float-

ing drivers with a voltage swing equal to INTV – 0.5V

CC

superimposed on the switch node voltage SW.

38571fc

9

LTC3857-1

FUNCTIONAL DIAGRAM

INTV

V

IN

CC

DUPLICATE FOR SECOND

CONTROLLER CHANNEL

BOOST

D

B

C

B

TG

DROP

OUT

DET

TOP

BOT

+

C

PGOOD1

0.88V

IN

D

BOT

–

SW

TOP ON

V

S

R

Q

FB1

+

INTV

CC

Q

–

SWITCH

LOGIC

0.72V

BG

SHDN

C

OUT

PGND

20μA

FREQ

V

OUT

VCO

CLK2

CLK1

+

–

R

SENSE

0.425V

SLEEP

L

ICMP

IR

–

+

–

PFD

C

LP

+

–

+

3mV

SENSE

SYNC

DET

2.7V

0.55V

PLLIN/MODE

–

100k

SLOPE COMP

V

FB

R

B

+

V

IN

0.80V

TRACK/SS

EA

–

R

A

EXTV

CC

+

–

OV

C

0.88V

I

TH

5.1V

LDO

EN

5.1V

LDO

EN

0.5μA

11V

C

C2

R

C

SHDN

RST

FB

1μA

TRACK/SS

+

–

FOLDBACK

2(V

)

4.7V

C

SHDN

SS

SGND

INTV

RUN

CC

38571 FD

38571fc

10

LTC3857-1

OPERATION ^{(Refer to the Functional Diagram)}

Main Control Loop

to turn on the top MOSFET continuously. The dropout

detector detects this and forces the top MOSFET off for

about one-twelfth of the clock period every tenth cycle to

The LTC3857-1 uses a constant frequency, current mode

step-down architecture with the two controller channels

operating 180 degrees out of phase. During normal op-

eration, each external top MOSFET is turned on when the

clock for that channel sets the RS latch, and is turned off

when the main current comparator, ICMP, resets the RS

latch. The peak inductor current at which ICMP trips and

allow C to recharge.

B

Shutdown and Start-Up (RUN1, RUN2 and

TRACK/ SS1, TRACK/SS2 Pins)

The two channels of the LTC3857-1 can be independently

shutdownusingtheRUN1andRUN2pins.Pullingeitherof

these pins below 1.26V shuts down the main control loop

for that controller. Pulling both pins below 0.7V disables

both controllers and most internal circuits, including the

resets the latch is controlled by the voltage on the I pin,

TH

which is the output of the error amplifier, EA. The error

amplifier compares the output voltage feedback signal at

the V pin, (which is generated with an external resistor

FB

INTV LDOs. In this state, the LTC3857-1 draws only 8μA

divider connected across the output voltage, V , to

CC

OUT

of quiescent current.

ground)totheinternal0.800Vreferencevoltage.Whenthe

load current increases, it causes a slight decrease in V

FB

The RUN pin may be externally pulled up or driven directly

by logic. When driving the RUN pin with a low impedance

source, do not exceed the absolute maximum rating of

8V. The RUN pin has an internal 11V voltage clamp that

allows the RUN pin to be connected through a resistor to a

relative to the reference, which causes the EA to increase

the I voltage until the average inductor current matches

TH

the new load current.

After the top MOSFET is turned off each cycle, the bottom

MOSFETisturnedonuntileithertheinductorcurrentstarts

to reverse, as indicated by the current comparator IR, or

the beginning of the next clock cycle.

highervoltage(forexample,V ),solongasthemaximum

IN

current into the RUN pin does not exceed 100μA.

The start-up of each controller’s output voltage V

is

OUT

controlled by the voltage on the TRACK/SS pin for that

channel. When the voltage on the TRACK/SS pin is less

than the 0.8V internal reference, the LTC3857-1 regulates

INTV /EXTV Power

CC

Power for the top and bottom MOSFET drivers and most

otherinternalcircuitryisderivedfromtheINTV pin.When

the V voltage to the TRACK/SS pin voltage instead of the

CC

FB

the EXTV pin is left open or tied to a voltage less than

0.8V reference. This allows the TRACK/SS pin to be used

toprogramasoft-startbyconnectinganexternalcapacitor

from the TRACK/SS pin to SGND. An internal 1μA pull-up

current charges this capacitor creating a voltage ramp on

the TRACK/SS pin. As the TRACK/SS voltage rises linearly

from 0V to 0.8V (and beyond up to the absolute maximum

CC

4.7V, the V LDO (low dropout linear regulator) supplies

IN

5.1V from V to INTV . If EXTV is taken above 4.7V,

IN

CC

the V LDO is turned off and an EXTV LDO is turned on.

IN

CC

Onceenabled,theEXTV LDOsupplies5.1VfromEXTV

CC

to INTV . Using the EXTV pin allows the INTV power

CC

to be derived from a high efficiency external source such

rating of 6V), the output voltage V

zero to its final value.

rises smoothly from

OUT

as one of the LTC3857-1 switching regulator outputs.

Alternatively the TRACK/SS pin can be used to cause the

start-up of V to track that of another supply. Typically,

this requires connecting to the TRACK/SS pin an external

resistor divider from the other supply to ground (see Ap-

plications Information section).

Each top MOSFET driver is biased from the floating boot-

strap capacitor C , which normally recharges during each

OUT

B

cycle through an external diode when the top MOSFET

turns off. If the input voltage, V , decreases to a voltage

IN

close to V , the loop may enter dropout and attempt

OUT

38571fc

11

LTC3857-1

OPERATION ^{(Refer to the Functional Diagram)}

Light Load Current Operation (Burst Mode Operation,

Pulse-Skipping or Forced Continuous Mode)

(PLLIN/MODE Pin)

In forced continuous operation or clocked by an external

clock source to use the phase-locked loop (see Frequency

Selection and Phase-Locked Loop section), the induc-

tor current is allowed to reverse at light loads or under

large transient conditions. The peak inductor current is

The LTC3857-1 can be enabled to enter high efficiency

Burst Mode operation, constant frequency pulse-skipping

mode, or forced continuous conduction mode at low load

currents. To select Burst Mode operation, tie the PLLIN/

MODE pin to GND. To select forced continuous operation,

determined by the voltage on the I pin, just as in normal

TH

operation.Inthismode,theefficiencyatlightloadsislower

thaninBurstModeoperation.However,continuousopera-

tion has the advantage of lower output voltage ripple and

less interference to audio circuitry. In forced continuous

mode, the output ripple is independent of load current.

tiethePLLIN/MODEpintoINTV .Toselectpulse-skipping

CC

mode, tie the PLLIN/MODE pin to a DC voltage greater

than 1.2V and less than INTV – 1.3V.

CC

WhenthePLLIN/MODEpinisconnectedforpulse-skipping

mode, the LTC3857-1 operates in PWM pulse-skipping

mode at light loads. In this mode, constant frequency

operation is maintained down to approximately 1% of

designedmaximumoutputcurrent. Atverylightloads, the

current comparator, ICMP, may remain tripped for several

cycles and force the external top MOSFET to stay off for

the same number of cycles (i.e., skipping pulses). The

inductor current is not allowed to reverse (discontinuous

operation). This mode, like forced continuous operation,

exhibits low output ripple as well as low audio noise and

reduced RF interference as compared to Burst Mode

operation. It provides higher low current efficiency than

forced continuous mode, but not nearly as high as Burst

Mode operation.

When a controller is enabled for Burst Mode operation,

the minimum peak current in the inductor is set to ap-

proximately 15% of the maximum sense voltage even

though the voltage on the I pin indicates a lower value.

TH

If the average inductor current is higher than the load

current, the error amplifier, EA, will decrease the voltage

on the I pin. When the I voltage drops below 0.425V,

TH

the internal sleep signal goes high (enabling sleep mode)

and both external MOSFETs are turned off. The I pin is

TH

then disconnected from the output of the EA and parked

at 0.450V.

In sleep mode, much of the internal circuitry is turned off,

reducing the quiescent current that the LTC3857-1 draws.

If one channel is shut down and the other channel is in

sleep mode, the LTC3857-1 draws only 50μA of quiescent

current. Ifbothchannelsareinsleepmode, theLTC3857-1

draws only 65μA of quiescent current. In sleep mode,

the load current is supplied by the output capacitor. As

the output voltage decreases, the EA’s output begins to

Frequency Selection and Phase-Locked Loop

(FREQ and PLLIN/MODE Pins)

Theselectionofswitchingfrequencyisatrade-offbetween

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

rise. When the output voltage drops enough, the I pin

TH

is reconnected to the output of the EA, the sleep signal

goes low, and the controller resumes normal operation

by turning on the top external MOSFET on the next cycle

of the internal oscillator.

The switching frequency of the LTC3857-1’s controllers

can be selected using the FREQ pin.

WhenacontrollerisenabledforBurstModeoperation, the

inductorcurrentisnotallowedtoreverse. Thereversecur-

rentcomparator,IR,turnsoffthebottomexternalMOSFET

just before the inductor current reaches zero, preventing

it from reversing and going negative. Thus, the controller

operates in discontinuous operation.

If the PLLIN/MODE pin is not being driven by an external

clock source, the FREQ pin can be tied to SGND, tied to

INTV_CCorprogrammedthroughanexternalresistor.Tying

FREQtoSGNDselects350kHzwhiletyingFREQtoINTV_CC

selects 535kHz. Placing a resistor between FREQ and

38571fc

12

LTC3857-1

OPERATION ^{(Refer to the Functional Diagram)}

SGND allows the frequency to be programmed between

50kHz and 900kHz.

Power Good (PGOOD1 Pin)

ThePGOOD1pinisconnectedtoanopendrainofaninternal

N-channel MOSFET. The MOSFET turns on and pulls the

A phase-locked loop (PLL) is available on the LTC3857-1

to synchronize the internal oscillator to an external clock

source that is connected to the PLLIN/MODE pin. The

phase detector adjusts the voltage (through an internal

lowpass filter) of the VCO input to align the turn-on of

controller 1’s external top MOSFET to the rising edge of

the synchronizing signal. Thus, the turn-on of controller

2’s external top MOSFET is 180 degrees out of phase to

the rising edge of the external clock source.

PGOOD1 pin low when the corresponding V pin volt-

FB1

age is not within 10% of the 0.8V reference voltage. The

PGOOD1 pin is also pulled low when the corresponding

RUN1 pin is low (shut down). When the V pin voltage

FB1

is within the 10% requirement, the MOSFET is turned

off and the pin is allowed to be pulled up by an external

resistor to a source no greater than 6V.

Foldback Current

The VCO input voltage is prebiased to the operating fre-

quency set by the FREQ pin before the external clock is

applied. If prebiased near the external clock frequency,

the PLL loop only needs to make slight changes to the

VCO input in order to synchronize the rising edge of the

external clock’s to the rising edge of TG1. The ability to

prebias the loop filter allows the PLL to lock-in rapidly

without deviating far from the desired frequency.

When the output voltage falls to less than 70% of its

nominal level, foldback current limiting is activated, pro-

gressively lowering the peak current limit in proportion to

the severity of the overcurrent or short-circuit condition.

Foldback current limiting is disabled during the soft-start

interval (as long as the V voltage is keeping up with the

FB

TRACK/SS voltage).

The typical capture range of the phase-locked loop is from

approximately 55kHz to 1MHz, with a guarantee over all

manufacturingvariationstobebetween75kHzand850kHz.

In other words, the LTC3857-1’s PLL is guaranteed to lock

to an external clock source whose frequency is between

75kHz and 850kHz.

Theory and Benefits of 2-Phase Operation

Why the need for 2-phase operation? Up until the 2-phase

family, constant-frequency dual switching regulators

operated both channels in phase (i.e., single phase

operation). This means that both switches turned on at

the same time, causing current pulses of up to twice the

amplitude of those for one regulator to be drawn from the

input capacitor and battery. These large amplitude current

pulses increased the total RMS current flowing from the

input capacitor, requiring the use of more expensive input

capacitorsandincreasingbothEMIandlossesintheinput

capacitor and battery.

The typical input clock thresholds on the PLLIN/MODE

pin are 1.6V (rising) and 1.1V (falling).

Output Overvoltage Protection

An overvoltage comparator guards against transient over-

shoots as well as other more serious conditions that may

overvoltage the output. When the V pin rises by more

With 2-phase operation, the two channels of the dual

switchingregulatorareoperated180degreesoutofphase.

Thiseffectivelyinterleavesthecurrentpulsesdrawnbythe

switches,greatlyreducingtheoverlaptimewheretheyadd

FB

than 10% above its regulation point of 0.800V, the top

MOSFET is turned off and the bottom MOSFET is turned

on until the overvoltage condition is cleared.

38571fc

13

LTC3857-1

OPERATION ^{(Refer to the Functional Diagram)}

together. The result is a significant reduction in total RMS

input current, which in turn allows less expensive input

capacitors to be used, reduces shielding requirements for

EMI and improves real world operating efficiency.

the RMS input current varies for single phase and 2-phase

operation for 3.3V and 5V regulators over a wide input

voltage range.

It can readily be seen that the advantages of 2-phase op-

eration are not just limited to a narrow operating range,

for most applications is that 2-phase operation will reduce

the input capacitor requirement to that for just one chan-

nel operating at maximum current and 50% duty cycle.

Figure1comparestheinputwaveformsforasingle-phase

dual switching regulator to a 2-phase dual switching

regulator. An actual measurement of the RMS input cur-

rent under these conditions shows that 2-phase operation

dropped the input current from 2.53A

to 1.55A

.

RMS

3.0

While this is an impressive reduction in itself, remember

2

SINGLE PHASE

that the power losses are proportional to I

, meaning

RMS

DUAL CONTROLLER

2.5

2.0

1.5

1.0

0.5

0

thattheactualpowerwastedisreducedbyafactorof2.66.

The reduced input ripple voltage also means less power is

lost in the input power path, which could include batter-

ies, switches, trace/connector resistances and protection

circuitry. Improvements in both conducted and radiated

EMI also directly accrue as a result of the reduced RMS

input current and voltage.

2-PHASE

DUAL CONTROLLER

V

= 5V/3A

O1

O2

= 3.3V/3A

Of course, the improvement afforded by 2-phase opera-

tion is a function of the dual switching regulator’s relative

duty cycles which, in turn, are dependent upon the input

voltage V (Duty Cycle = V /V ). Figure 2 shows how

0

10

20

30

40

INPUT VOLTAGE (V)

38571 F02

Figure 2. RMS Input Current Comparison

IN

OUT IN

5V SWITCH

20V/DIV

3.3V SWITCH

20V/DIV

INPUT CURRENT

5A/DIV

INPUT VOLTAGE

500mV/DIV

38571 F01

I

= 2.53A

I = 1.55A

IN(MEAS) RMS

IN(MEAS)

RMS

Figure 1. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators

Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the 2-Phase Regulator Allows

Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency

38571fc

14

LTC3857-1

APPLICATIONS INFORMATION

The Typical Application on the first page is a basic

LTC3857-1applicationcircuit.LTC3857-1canbeconfigured

to use either DCR (inductor resistance) sensing or low

valueresistorsensing.Thechoicebetweenthetwocurrent

sensing schemes is largely a design trade-off between

cost, power consumption, and accuracy. DCR sensing

is becoming popular because it saves expensive current

sensing resistors and is more power efficient, especially

in high current applications. However, current sensing

resistors provide the most accurate current limits for the

controller. Other external component selection is driven

by the load requirement, and begins with the selection of

programmed current limit unpredictable. If inductor DCR

sensing is used (Figure 4b), resistor R1 should be placed

closetotheswitchingnode,topreventnoisefromcoupling

into sensitive small-signal nodes.

TO SENSE FILTER,

NEXT TO THE CONTROLLER

C

OUT

38571 F03

INDUCTOR OR R

SENSE

Figure 3. Sense Lines Placement with Inductor or Sense Resistor

R

(if R

is used) and inductor value. Next, the

SENSE

V

IN

V

IN

powerMOSFETsandSchottkydiodesareselected. Finally,

input and output capacitors are selected.

INTV

CC

BOOST

TG

+

–

SENSE and SENSE Pins

R

SENSE

SW

V

OUT

+

–

The SENSE and SENSE pins are the inputs to the current

comparators. The common mode voltage range on these

pins is 0V to 28V (abs max), enabling the LTC3857-1 to

regulate output voltages up to a nominal 24V (allowing

margin for tolerances and transients).

LTC3857-1

BG

+

SENSE

PLACE CAPACITOR NEAR

SENSE PINS

–

SENSE

SGND

+

The SENSE pin is high impedance over the full common

38571 F04a

mode range, drawing at most 1μA. This high impedance

allows the current comparators to be used in inductor

DCR sensing.

(4a) Using a Resistor to Sense Current

V

INTV

V

IN

–

The impedance of the SENSE pin changes depending on

CC

–

the common mode voltage. When SENSE is less than

INDUCTOR

DCR

BOOST

TG

INTV – 0.5V, a small current of less than 1μA flows out

CC

L

–

of the pin. When SENSE is above INTV + 0.5V, a higher

SW

V

OUT

CC

LTC3857-1

current (~550μA) flows into the pin. Between INTV

–

CC

BG

0.5V and INTV + 0.5V, the current transitions from the

CC

R1

C1* R2

smaller current to the higher current.

+

SENSE

Filter components mutual to the sense lines should be

placed close to the LTC3857-1, and the sense lines should

run close together to a Kelvin connection underneath the

current sense element (shown in Figure 3). Sensing cur-

rent elsewhere can effectively add parasitic inductance

and capacitance to the current sense element, degrading

the information at the sense terminals and making the

–

SENSE

SGND

38571 F04b

R2

R1 + R2

L

DCR

||

(R1 R2) • C1 =

*PLACE C1 NEAR

SENSE PINS

R

= DCR

SENSE(EQ)

(4b) Using the Inductor DCR to Sense Current

Figure 4. Current Sensing Methods

38571fc

15

LTC3857-1

APPLICATIONS INFORMATION

Low Value Resistor Current Sensing

drop across the external capacitor is equal to the drop

across the inductor DCR multiplied by R2/(R1 + R2). R2

scales the voltage across the sense terminals for appli-

cations where the DCR is greater than the target sense

resistor value. To properly dimension the external filter

components, the DCR of the inductor must be known.

It can be measured using a good RLC meter, but the

DCR tolerance is not always the same and varies with

temperature; consult the manufacturers’ data sheets for

detailed information.

A typical sensing circuit using a discrete resistor is shown

in Figure 4a. R

output current.

is chosen based on the required

SENSE

The current comparator has a maximum threshold

. The current comparator threshold voltage

V

SENSE(MAX)

sets the peak of the inductor current, yielding a maximum

average output current, I

, equal to the peak value less

MAX

half the peak-to-peak ripple current, ΔI . To calculate the

L

sense resistor value, use the equation:

Using the inductor ripple current value from the Induc-

tor Value Calculation section, the target sense resistor

value is:

V

SENSE(MAX)

R

=

SENSE

ΔI

L

I

+

MAX

2

V

SENSE(MAX)

R

=

SENSE(EQUIV)

ΔI

L

When using the controller in very low dropout conditions,

the maximum output current level will be reduced due to

the internal compensation required to meet stability cri-

terion for buck regulators operating at greater than 50%

duty factor. A curve is provided in the Typical Performance

Characteristics section to estimate this reduction in peak

output current depending upon the operating duty factor.

I

+

MAX

2

To ensure that the application will deliver full load current

over the full operating temperature range, choose the

minimum value for the maximum current sense threshold

voltage (V

).

SENSE(MAX)

Next, determine the DCR of the inductor. When provided,

use the manufacturer’s maximum value, usually given at

20°C. Increase this value to account for the temperature

coefficient of copper resistance, which is approximately

Inductor DCR Sensing

For applications requiring the highest possible efficiency

at high load currents, the LTC3857-1 is capable of sensing

the voltage drop across the inductor DCR, as shown in

Figure 4b. The DCR of the inductor represents the small

amount of DC resistance of the copper wire, which can be

lessthan1mꢁfortoday’slowvalue,highcurrentinductors.

In a high current application requiring such an inductor,

power loss through a sense resistor would cost several

points of efficiency compared to inductor DCR sensing.

0.4%/°C. A conservative value for T

is 100°C.

L(MAX)

To scale the maximum inductor DCR to the desired sense

resistor (R ) value, use the divider ratio:

D

R_SENSE(EQUIV)

R_D=

DCR_MAXatT

L(MAX)

C1 is usually selected to be in the range of 0.1μF to 0.47μF.

ThisforcesR1||R2toaround2k, reducingerrorthatmight

If the external R1||R2 • C1 time constant is chosen to

be exactly equal to the L/DCR time constant, the voltage

+

have been caused by the SENSE pin’s 1μA current.

38571fc

16

LTC3857-1

APPLICATIONS INFORMATION

The equivalent resistance R1|| R2 is scaled to the room

temperature inductance and maximum DCR:

Accepting larger values of ΔI allows the use of low in-

L

ductances, but results in higher output voltage ripple and

greater core losses. A reasonable starting point for setting

L

R1|| R2 =

ripple current is ΔI =0.3(I

). The maximum ΔI occurs

L

MAX

DCR at 20°C • C1

(

)

at the maximum input voltage.

The sense resistor values are:

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

R1|| R2

R_D

R1• R_D

1– R_D

R1=

; R2 =

15% of the current limit determined by R

. Lower

SENSE

inductor values (higher ΔI ) will cause this to occur at

The maximum power loss in R1 is related to duty cycle,

and will occur in continuous mode at the maximum input

voltage:

L

lower load currents, which can cause a dip in efficiency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease.

V

_IN(MAX)– V_OUT• V

(

)

OUT

P

LOSS

R1=

R1

Inductor Core Selection

Ensure that R1 has a power rating higher than this value.

If high efficiency is necessary at light loads, consider this

power loss when deciding whether to use DCR sensing or

sense resistors. Light load power loss can be modestly

higher with a DCR network than with a sense resistor, due

totheextraswitchinglossesincurredthroughR1.However,

DCR sensing eliminates a sense resistor, reduces conduc-

tion losses and provides higher efficiency at heavy loads.

Peak efficiency is about the same with either method.

Once the value for L is known, the type of inductor must

be selected. High efficiency converters generally cannot

affordthecorelossfoundinlowcostpowderedironcores,

forcingtheuseofmoreexpensiveferriteormolypermalloy

cores. Actual core loss is independent of core size for a

fixedinductorvalue,butitisverydependentoninductance

value selected. As inductance increases, core losses go

down. Unfortunately, increased inductance requires more

turns of wire and therefore copper losses will increase.

Inductor Value Calculation

Ferrite designs have very low core loss and are preferred

for high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates hard, which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because

of MOSFET gate charge losses. In addition to this basic

trade-off, the effect of inductor value on ripple current and

low current operation must also be considered.

Power MOSFET and Schottky Diode

(Optional) Selection

Theinductorvaluehasadirecteffectonripplecurrent.The

Two external power MOSFETs must be selected for each

controller in the LTC3857-1: one N-channel MOSFET for

the top (main) switch, and one N-channel MOSFET for the

bottom (synchronous) switch.

inductor ripple current, ΔI , decreases with higher induc-

L

tance or higher frequency and increases with higher V :

IN

⎛

⎞

1

V_OUT

ΔI_L=

V_OUT1–

⎜

⎝

⎟

⎠

f L

( )( )

V

IN

38571fc

17

LTC3857-1

APPLICATIONS INFORMATION

Thepeak-to-peakdrivelevelsaresetbytheINTV voltage.

where δ is the temperature dependency of R

DR

and

CC

DS(ON)

This voltage is typically 5.1V during start-up (see EXTV

R

(approximately 2ꢁ) is the effective driver resistance

CC

Pin Connection). Consequently, logic-level threshold

at the MOSFET’s Miller threshold voltage. V

is the

THMIN

MOSFETs must be used in most applications. The only

typical MOSFET minimum threshold voltage.

exception is if low input voltage is expected (V < 4V);

2

IN

GS(TH)

DSS

BothMOSFETshaveI RlosseswhilethetopsideN-channel

equation includes an additional term for transition losses,

then, sub-logic level threshold MOSFETs (V

< 3V)

speci-

should be used. Pay close attention to the BV

which are highest at high input voltages. For V < 20V

IN

fication for the MOSFETs as well; many of the logic-level

MOSFETs are limited to 30V or less.

the high current efficiency generally improves with larger

MOSFETs, while for V > 20V the transition losses rapidly

IN

Selection criteria for the power MOSFETs include the on-

increasetothepointthattheuseofahigherR

device

DS(ON)

resistance, R

, Miller capacitance, C , input

DS(ON) MILLER

withlowerC

actuallyprovideshigherefficiency.The

MILLER

voltage and maximum output current. Miller capacitance,

, can be approximated from the gate charge curve

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

a short-circuit when the synchronous switch is on close

to 100% of the period.

C

MILLER

usually provided on the MOSFET manufacturers’ data

sheet. C is equal to the increase in gate charge

MILLER

along the horizontal axis while the curve is approximately

The term (1+ δ) is generally given for a MOSFET in the

flat divided by the specified change in V . This result is

DS

form of a normalized R

vs Temperature curve, but

DS(ON)

then multiplied by the ratio of the application applied V

DS

δ = 0.005/°C can be used as an approximation for low

to the Gate charge curve specified V . When the IC is

DS

voltage MOSFETs.

operating in continuous mode the duty cycles for the top

and bottom MOSFETs are given by:

The optional Schottky diodes D1 and D2 shown in

Figure 11 conduct during the dead-time between the

conduction of the two power MOSFETs. This prevents

the body diode of the bottom MOSFET from turning on,

storing charge during the dead-time and requiring a

reverse recovery period that could cost as much as 3%

V_OUT

V

IN

Main Switch Duty Cycle =

V − V

IN

OUT

Synchronous Switch Duty Cycle =

V

IN

in efficiency at high V . A 1A to 3A Schottky is generally

IN

a good compromise for both regions of operation due

to the relatively small average current. Larger diodes

result in additional transition losses due to their larger

junction capacitance.

The MOSFET power dissipations at maximum output

current are given by:

V_OUT

V

IN

2

P_MAIN

=

I

1+ δ R

+

(

_MAX) (

)

DS(ON)

C and C

Selection

IN

OUT

I

⎛

⎞

2

MAX

V

IN

R

C

•

(

)

(

)

(

)

DR

MILLER

The selection of C is simplified by the 2-phase architec-

⎜

⎟

⎠

IN

⎝

2

ture and its impact on the worst-case RMS current drawn

throughtheinputnetwork(battery/fuse/capacitor).Itcanbe

shown that the worst-case capacitor RMS current occurs

when only one controller is operating. The controller with

⎡

⎤

1

+

f

( )

⎢

⎣

⎥

⎦

V

_INTVCC– V_THMINV_THMIN

V – V

2

the highest (V )(I ) product needs to be used in the

IN

OUT

OUT OUT

P

SYNC

=

I

1+ δ R

DS(ON)

(

_MAX) (

)

formula shown in Equation 1 to determine the maximum

V

IN

38571fc

18

LTC3857-1

APPLICATIONS INFORMATION

RMS capacitor current requirement. Increasing the out-

put current drawn from the other controller will actually

decrease the input RMS ripple current from its maximum

value. The out-of-phase technique typically reduces the

input capacitor’s RMS ripple current by a factor of 30%

to 70% when compared to a single phase power supply

solution.

1cmofeachotherandshareacommonC (s). Separating

IN

the drains and C may produce undesirable voltage and

IN

current resonances at V .

IN

A small (0.1μF to 1μF) bypass capacitor between the chip

V

pin and ground, placed close to the LTC3857-1, is

IN

also suggested. A 10ꢁ resistor placed between C (C1)

IN

and the V pin provides further isolation between the

two channels.

IN

Incontinuousmode,thesourcecurrentofthetopMOSFET

is a square wave of duty cycle (V )/(V ). To prevent

OUT

IN

The selection of C

is driven by the effective series

OUT

large voltage transients, a low ESR capacitor sized for the

maximum RMS current of one channel must be used. The

maximum RMS capacitor current is given by:

resistance (ESR). Typically, once the ESR requirement

is satisfied, the capacitance is adequate for filtering. The

output ripple (ΔV ) is approximated by:

OUT

I_MAX

V

IN

1/2

C_INRequired I_RMS

≈

⎡ V

_OUT)(

V – V

⎤

)

⎦

(

⎛

⎞

1

IN

OUT

⎣

ΔV_OUT≈ ΔI_LESR +

(1)

⎜

⎝

⎟

⎠

8 • f • C_OUT

This formula has a maximum at V = 2V , where I

IN

OUT

RMS

where f is the operating frequency, C

is the output

OUT

= I /2. This simple worst-case condition is commonly

OUT

capacitance and ΔI is the ripple current in the inductor.

L

usedfordesignbecauseevensignificantdeviationsdonot

offermuchrelief.Notethatcapacitormanufacturers’ripple

current ratings are often based on only 2000 hours of life.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may be paralleled to meet

size or height requirements in the design. Due to the high

operatingfrequencyoftheLTC3857-1, ceramiccapacitors

The output ripple is highest at maximum input voltage

since ΔI increases with input voltage.

L

Setting Output Voltage

The LTC3857-1 output voltages are each set by an exter-

nal feedback resistor divider carefully placed across the

output, as shown in Figure 5. The regulated output voltage

is determined by:

can also be used for C . Always consult the manufacturer

IN

if there is any question.

⎛

⎞

⎟

R_B

R_A⎠

V_OUT= 0.8V 1+

⎜

⎝

The benefit of the LTC3857-1 2-phase operation can be

calculatedbyusingEquation1forthehigherpowercontrol-

ler and then calculating the loss that would have resulted

if both controller channels switched on at the same time.

The total RMS power lost is lower when both controllers

are operating due to the reduced overlap of current pulses

required through the input capacitor’s ESR. This is why

the input capacitor’s requirement calculated above for the

worst-case controller is adequate for the dual controller

design. Also, the input protection fuse resistance, battery

resistance, and PC board trace resistance losses are also

reduced due to the reduced peak currents in a 2-phase

system. The overall benefit of a multiphase design will

only be fully realized when the source impedance of the

power supply/battery is included in the efficiency testing.

The drains of the top MOSFETs should be placed within

To improve the frequency response, a feedforward ca-

pacitor, C , may be used. Great care should be taken to

FF

route the V line away from noise sources, such as the

FB

inductor or the SW line.

V

OUT

R

C

FF

1/2 LTC3857-1

B

A

V

FB

R

38571 F05

Figure 5. Setting Output Voltage

38571fc

19

LTC3857-1

APPLICATIONS INFORMATION

Tracking and Soft-Start (TRACK/SS Pins)

V

X(MASTER)

OUT(SLAVE)

The start-up of each V

is controlled by the voltage on

OUT

the respective TRACK/SS pin. When the voltage on the

TRACK/SS pin is less than the internal 0.8V reference, the

LTC3857-1 regulates the V pin voltage to the voltage on

FB

the TRACK/SS pin instead of 0.8V. The TRACK/SS pin can

be used to program an external soft-start function or to

allow V

to track another supply during start-up.

OUT

38571 F07a

TIME

Soft-start is enabled by simply connecting a capacitor

from the TRACK/SS pin to ground, as shown in Figure 6.

An internal 1μA current source charges the capacitor,

providing a linear ramping voltage at the TRACK/SS pin.

(7a) Coincident Tracking

V

X(MASTER)

OUT(SLAVE)

The LTC3857-1 will regulate the V pin (and hence V

)

FB

OUT

according to the voltage on the TRACK/SS pin, allowing

V

to rise smoothly from 0V to its final regulated value.

OUT

The total soft-start time will be approximately:

0.8V

1μA

t_SS= C_SS

•

38571 F07b

TIME

1/2 LTC3857-1

TRACK/SS

(7b) Ratiometric Tracking

C

SS

SGND

Figure 7. Two Different Modes of Output Voltage Tracking

38571 F06

Figure 6. Using the TRACK/SS Pin to Program Soft-Start

Alternatively, the TRACK/SS pin can be used to track two

(or more) supplies during start-up, as shown qualitatively

in Figures 7a and 7b. To do this, a resistor divider should

V

x OUT

1/2 LTC3857-1

R

B

A

V

FB

be connected from the master supply (V ) to the TRACK/

R

X

SS pin of the slave supply (V ), as shown in Figure 8.

OUT

R

TRACKB

TRACKA

During start-up V

will track V according to the ratio

TRACK/SS

OUT

X

38571 F08

set by the resistor divider:

V_X

R_A

R_TRACKA+ R_TRACKB

R_A+ R_B

=

•

V_OUTR_TRACKA

Figure 8. Using the TRACK/SS Pin for Tracking

For coincident tracking (V

= V during start-up):

X

OUT

R = R

A

TRACKA

TRACKB

R = R

B

38571fc

20

LTC3857-1

APPLICATIONS INFORMATION

INTV Regulators

to regulate the INTV voltage to 5.1V, so while EXTV

is less than 5.1V, the LDO is in dropout and the INTV

CC

The LTC3857-1 features two separate internal P-channel

low dropout linear regulators (LDO) that supply power

voltage is approximately equal to EXTV . When EXTV

CC

is greater than 5.1V, up to an absolute maximum of 14V,

at the INTV pin from either the V supply pin or the

CC

IN

INTV is regulated to 5.1V.

CC

EXTV pin depending on the connection of the EXTV

CC

pin. INTV powers the gate drivers and much of the

Using the EXTV_CCLDO allows the MOSFET driver and

control power to be derived from one of the LTC3857-1’s

switching regulator outputs (4.7V ≤ V_OUT≤ 14V) during

normal operation and from the V_INLDO when the out-

put is out of regulation (e.g., start-up, short-circuit). If

more current is required through the EXTV_CCLDO than

is specified, an external Schottky diode can be added

between the EXTV_CCand INTV_CCpins. In this case, do

not apply more than 6V to the EXTV_CCpin and make sure

that EXTV_CC≤ V_IN.

CC

LTC3857-1’sinternalcircuitry.TheV LDOandtheEXTV

IN

CC

LDO regulate INTV to 5.1V. Each of these can supply a

CC

peak current of 50mA and must be bypassed to ground

with a minimum of 4.7μF ceramic capacitor. No matter

what type of bulk capacitor is used, an additional 1μF

ceramic capacitor placed directly adjacent to the INTV

CC

and PGND pins is highly recommended. Good bypassing

is needed to supply the high transient currents required

by the MOSFET gate drivers and to prevent interaction

between the channels.

Significant efficiency and thermal gains can be realized

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3857-1 to

by powering INTV from the output, since the V cur-

CC

IN

rent resulting from the driver and control currents will be

scaled by a factor of (Duty Cycle)/(Switcher Efficiency).

For 5V to 14V regulator outputs, this means connecting

be exceeded. The INTV current, which is dominated

CC

by the gate charge current, may be supplied by either

the EXTV pin directly to V . Tying the EXTV pin to

CC

OUT

CC

the V LDO or the EXTV LDO. When the voltage on

an 8.5V supply reduces the junction temperature in the

previous example from 125°C to:

IN

CC

the EXTV pin is less than 4.7V, the V LDO is enabled.

CC

IN

Power dissipation for the IC in this case is highest and is

T = 70°C + (15mA)(8.5V)(90°C/W) = 82°C

J

equaltoV •I .Thegatechargecurrentisdependent

IN INTVCC

However, for 3.3V and other low voltage outputs, addi-

on operating frequency as discussed in the Efficiency

Considerations section. The junction temperature can be

estimated by using the equations given in Note 3 of the

Electrical Characteristics. For example, the LTC3857-1

tional circuitry is required to derive INTV power from

CC

the output.

The following list summarizes the four possible connec-

INTV current is limited to less than 15mA from a 40V

CC

tions for EXTV :

CC

supply when not using the EXTV supply at a 70°C

CC

1. EXTV LeftOpen(orGrounded).ThiswillcauseINTV

CC

ambient temperature:

to be powered from the internal 5.1V regulator result-

ing in an efficiency penalty of up to 10% at high input

voltages.

T = 70°C + (15mA)(40V)(90°C/W) = 125°C

J

To prevent the maximum junction temperature from be-

ing exceeded, the input supply current must be checked

while operating in forced continuous mode (PLLIN/MODE

2. EXTV Connected directly to V . This is the normal

CC

OUT

connection for a 5V to 14V regulator and provides the

highest efficiency.

= INTV ) at maximum V .

CC

IN

When the voltage applied to EXTV rises above 4.7V, the

CC

3. EXTV ConnectedtoanExternalsupply. Ifanexternal

CC

V LDO is turned off and the EXTV LDO is enabled. The

IN

CC

supply is available in the 5V to 14V range, it may be

EXTV LDO remains on as long as the voltage applied to

CC

used to power EXTV . Ensure that EXTV < V .

CC

IN

EXTV remains above 4.5V. The EXTV LDO attempts

CC

38571fc

21

LTC3857-1

APPLICATIONS INFORMATION

4. EXTV

Connected to an Output-Derived Boost

Fault Conditions: Current Limit and Current Foldback

CC

Network. For 3.3V and other low voltage regulators,

efficiency gains can still be realized by connecting

TheLTC3857-1includescurrentfoldbacktohelplimitload

current when the output is shorted to ground. If the output

voltage falls below 70% of its nominal output level, then

the maximum sense voltage is progressively lowered to

about half of its maximum selected value. Under short-

circuitconditionswithverylowdutycycles,theLTC3857-1

will begin cycle skipping in order to limit the short-circuit

current. In this situation the bottom MOSFET will be dis-

sipating most of the power but less than in normal opera-

tion. The short-circuit ripple current is determined by the

EXTV to an output-derived voltage that has been

CC

boosted to greater than 4.7V. This can be done with

the capacitive charge pump shown in Figure 9. Ensure

that EXTV < V .

CC

IN

C

IN

BAT85

V

IN

MTOP

MBOT

minimum on-time. t

, of the LTC3857-1 (≈90ns),

ON(MIN)

VN2222LL

TG1

1/2 LTC3857-1

the input voltage and inductor value:

L

R

SENSE

V

L

⎛

⎞

V

OUT

IN

EXTV

SW

CC

ΔI_L(SC)= t_{ON(MIN) ⎜}

⎟

⎠

⎝

C

OUT

D

BG1

The resulting average short-circuit current is:

38571 F09

PGND

1

2

I_SC= 50% •I_LIM(MAX)– ΔI_L(SC)

Figure 9. Capacitive Charge Pump for EXTV_CC

Fault Conditions: Overvoltage Protection (Crowbar)

Topside MOSFET Driver Supply (C , D )

The overvoltage crowbar is designed to blow a system

input fuse when the output voltage of the regulator rises

muchhigherthannominallevels.Thecrowbarcauseshuge

currents to flow, that blow the fuse to protect against a

shorted top MOSFET if the short occurs while the control-

ler is operating.

B

Externalbootstrapcapacitors,C ,connectedtotheBOOST

B

pinssupplythegatedrivevoltagesforthetopsideMOSFETs.

Capacitor C in the Functional Diagram is charged though

B

external diode D from INTV when the SW pin is low.

B

CC

When one of the topside MOSFETs is to be turned on, the

driver places the C voltage across the gate-source of the

A comparator monitors the output for overvoltage condi-

tions. The comparator detects faults greater than 10%

above the nominal output voltage. When this condition

is sensed, the top MOSFET is turned off and the bottom

MOSFET is turned on until the overvoltage condition is

cleared. ThebottomMOSFETremainsoncontinuouslyfor

B

desired MOSFET. This enhances the MOSFET and turns on

the topside switch. The switch node voltage, SW, rises to

V and the BOOST pin follows. With the topside MOSFET

IN

on, the boost voltage is above the input supply: V

=

BOOST

B

V + V

. The value of the boost capacitor, C , needs

IN

INTVCC

to be 100 times that of the total input capacitance of the

aslongastheovervoltageconditionpersists;ifV returns

OUT

topsideMOSFET(s).Thereversebreakdownoftheexternal

Schottky diode must be greater than V

to a safe level, normal operation automatically resumes.

.

IN(MAX)

AshortedtopMOSFETwillresultinahighcurrentcondition

which will open the system fuse. The switching regulator

will regulate properly with a leaky top MOSFET by altering

the duty cycle to accommodate the leakage.

When adjusting the gate drive level, the final arbiter is the

total input current for the regulator. If a change is made

and the input current decreases, then the efficiency has

improved. If there is no change in input current, then there

is no change in efficiency.

38571fc

22

LTC3857-1

APPLICATIONS INFORMATION

Phase-Locked Loop and Frequency Synchronization

1000

900

800

700

600

500

400

300

200

100

0

The LTC3857-1 has an internal phase-locked loop (PLL)

comprised of a phase frequency detector, a lowpass filter,

and a voltage-controlled oscillator (VCO). This allows the

turn-on of the top MOSFET of controller 1 to be locked to

the rising edge of an external clock signal applied to the

PLLIN/MODEpin.Theturn-onofcontroller2’stopMOSFET

is thus 180 degrees out of phase with the external clock.

The phase detector is an edge sensitive digital type that

provides zero degrees phase shift between the external

and internal oscillators. This type of phase detector does

not exhibit false lock to harmonics of the external clock.

15 25 35 45 55 65 75 85 95 105 115 125

FREQ PIN RESISTOR (kꢁ)

38571 F10

Figure 10. Relationship Between Oscillator Frequency

and Resistor Value at the FREQ Pin

If the external clock frequency is greater than the internal

oscillator’sfrequency,f ,thencurrentissourcedcontinu-

OSC

ously from the phase detector output, pulling up the VCO

input.WhentheexternalclockfrequencyislessthanfOSC,

current is sunk continuously, pulling down the VCO input.

If the external and internal frequencies are the same but

exhibit a phase difference, the current sources turn on for

an amount of time corresponding to the phase difference.

The voltage at the VCO input is adjusted until the phase

and frequency of the internal and external oscillators are

identical. At the stable operating point, the phase detector

output is high impedance and the internal filter capacitor,

CLP, holds the voltage at the VCO input.

synchronization frequency. The VCO’s input voltage is

prebiased at a frequency corresponding to the frequency

set by the FREQ pin. Once prebiased, the PLL only needs

to adjust the frequency slightly to achieve phase lock

and synchronization. Although it is not required that the

free-running frequency be near external clock frequency,

doingsowillpreventtheoperatingfrequencyfrompassing

through a large range of frequencies as the PLL locks.

Table 2 summarizes the different states in which the FREQ

pin can be used.

Note that the LTC3857-1 can only be synchronized to an

external clock whose frequency is within range of the

LTC3857-1’s internal VCO, which is nominally 55kHz to

1MHz.Thisisguaranteedtobebetween75kHzand850kHz.

Table 2

FREQ PIN

PLLIN/MODE PIN

DC Voltage

FREQUENCY

350kHz

0V

INTV

DC Voltage

535kHz

CC

Typically,theexternalclock(onthePLLIN/MODEpin)input

highthresholdis1.6V,whiletheinputlowthresholdis1.1V.

Resistor

DC Voltage

50kHz–900kHz

Any of the Above

External Clock

Phase –Locked to

External Clock

Rapid phase locking can be achieved by using the FREQ

pin to set a free-running frequency near the desired

38571fc

23

LTC3857-1

APPLICATIONS INFORMATION

Minimum On-Time Considerations

MOSFET driver and control currents. V current typi-

IN

cally results in a small (<0.1%) loss.

Minimum on-time, t

, is the smallest time dura-

ON(MIN)

tion that the LTC3857-1 is capable of turning on the top

MOSFET. It is determined by internal timing delays and the

gate charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that

2. INTV current is the sum of the MOSFET driver and

CC

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge, dQ, moves

from INTV to ground. The resulting dQ/dt is a current

CC

V_OUT

t_ON(MIN)

<

out of INTV that is typically much larger than the

CC

V

f

_IN( )

control circuit current. In continuous mode, I

GATECHG

= f(Q + Q ), where Q and Q are the gate charges of

T

B

T

B

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

the topside and bottom side MOSFETs.

SupplyingINTV fromanoutput-derivedpowersource

CC

through EXTV will scale the V current required for

CC

IN

thedriverandcontrolcircuitsbyafactorof(DutyCycle)/

Theminimumon-timefortheLTC3857-1isapproximately

95ns. However, as the peak sense voltage decreases the

minimum on-time gradually increases up to about 130ns.

This is of particular concern in forced continuous applica-

tions with low ripple current at light loads. If the duty cycle

drops below the minimum on-time limit in this situation,

a significant amount of cycle skipping can occur with cor-

respondingly larger current and voltage ripple.

(Efficiency). For example, in a 20V to 5V application,

10mAofINTV currentresultsinapproximately2.5mA

CC

of V current. This reduces the midcurrent loss from

IN

10% or more (if the driver was powered directly from

V ) to only a few percent.

IN

2

3. I R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resis-

tor, and input and output capacitor ESR. In continuous

mode the average output current flows through L and

Efficiency Considerations

R

, but is chopped between the topside MOSFET

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

SENSE

andthesynchronousMOSFET.IfthetwoMOSFETshave

approximately the same R

, then the resistance

DS(ON)

of one MOSFET can simply be summed with the resis-

2

tances of L, R

and ESR to obtain I R losses. For

= 30mꢁ, R = 50mꢁ, R

SENSE

DS(ON)

ESR

example, if each R

L

SENSE

= 10mꢁ and R

= 40mꢁ (sum of both input and

%Efficiency = 100% – (L1 + L2 + L3 + ...)

output capacitance losses), then the total resistance

is 130mꢁ. This results in losses ranging from 3% to

13% as the output current increases from 1A to 5A for

a 5V output, or a 4% to 20% loss for a 3.3V output.

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3857-1 circuits: 1) IC V_INcurrent, 2) INTV_CC

regulator current, 3) I²R losses, 4) topside MOSFET

Efficiency varies as the inverse square of V

for the

OUT

sameexternalcomponentsandoutputpowerlevel. The

combined effects of increasingly lower output voltages

andhighercurrentsrequiredbyhighperformancedigital

systemsisnotdoublingbutquadruplingtheimportance

of loss terms in the switching regulator system!

transition losses

.

1. The V current is the DC input supply current given

IN

in the Electrical Characteristics table, which excludes

38571fc

24

LTC3857-1

APPLICATIONS INFORMATION

4. Transition losses apply only to the topside MOSFET(s),

be estimated by examining the rise time at the pin. The

I_THexternal components shown in Figure 13 circuit will

provide an adequate starting point for most applications.

and become significant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

The I series R -C filter sets the dominant pole-zero

TH

C

Transition Loss = (1.7) • V • 2 • I

• C

• f

loop compensation. The values can be modified slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the final PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1μs to 10μs will

IN

O(MAX)

RSS

Other hidden losses such as copper trace and internal

battery resistances can account for an additional 5%

to 10% efficiency degradation in portable systems. It

is very important to include these system level losses

during the design phase. The internal battery and fuse

resistancelossescanbeminimizedbymakingsurethat

C has adequate charge storage and very low ESR at

IN

produce output voltage and I pin waveforms that will

TH

the switching frequency. A 25W supply will typically

require a minimum of 20μF to 40μF of capacitance

having a maximum of 20mꢁ to 50mꢁ of ESR. The

LTC3857-1 2-phase architecture typically halves this

input capacitance requirement over competing solu-

tions.OtherlossesincludingSchottkyconductionlosses

during dead-time and inductor core losses generally

account for less than 2% total additional loss.

give a sense of the overall loop stability without breaking

the feedback loop.

Placing a resistive load and a power MOSFET directly

across the output capacitor and driving the gate with an

appropriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This

Checking Transient Response

is why it is better to look at the I pin signal which is in

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, V_OUTshifts by an

amount equal to ΔI_LOAD(ESR), where ESR is the effective

series resistance of C_OUT. ΔI_LOADalso begins to charge or

discharge C_OUTgenerating the feedback error signal that

forces the regulator to adapt to the current change and

return V_OUTto its steady-state value. During this recovery

time V_OUTcan be monitored for excessive overshoot or

ringing, which would indicate a stability problem. OPTI-

LOOP compensation allows the transient response to be

optimized over a wide range of output capacitance and

ESR values. The availability of the I_THpin not only allows

optimization of control loop behavior, but it also provides

a DC coupled and AC filtered closed-loop response test

point. The DC step, rise time and settling at this test

point truly reflects the closed-loop response. Assuming

apredominantlysecondordersystem,phasemarginand/

or damping factor can be estimated using the percentage

of overshoot seen at this pin. The bandwidth can also

TH

the feedback loop and is the filtered and compensated

control loop response.

The gain of the loop will be increased by increasing R

C

and the bandwidth of the loop will be increased by de-

creasing C . If R is increased by the same factor that C

C

is decreased, the zero frequency will be kept the same,

thereby keeping the phase shift the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loopsystemandwilldemonstratetheactualoverall

supply performance.

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C , causing a rapid drop in V . No regulator can

OUT

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

C

to C

is greater than 1:50, the switch rise time

LOAD

OUT

38571fc

25

LTC3857-1

APPLICATIONS INFORMATION

should be controlled so that the load rise time is limited

ThepowerdissipationonthetopsideMOSFETcanbeeasily

estimated. Choosing a Fairchild FDS6982S dual MOSFET

to approximately 25 • C

. Thus a 10μF capacitor would

LOAD

require a 250μs rise time, limiting the charging current

to about 200mA.

results in: R

= 0.035ꢁ/0.022ꢁ, C

= 215pF. At

DS(ON)

MILLER

maximum input voltage with T(estimated) = 50°C:

3.3V

22V

2

Design Example

P

=

6A ⎡1+ 0.005 50°C – 25°C ⎤

(

)

(

)

(

)

MAIN

⎣

⎦

As a design example for one channel, assume V

=

IN

= 6A,

6A

2

0.035Ω + 22V

2.5Ω 215pF •

)(

(

)

(

)

(

)

12V(nominal), V = 22V (max), V

= 3.3V, I

IN

OUT

MAX

V

= 50mV and f = 350kHz.

SENSE(MAX)

1

⎡

⎤

+

350kHz = 433mW

(

)

Theinductancevalueischosenfirstbasedona30%ripple

current assumption. The highest value of ripple current

occurs at the maximum input voltage. Tie the FREQ pin

to GND, generating 350kHz operation. The minimum

inductance for 30% ripple current is:

⎢

⎣

⎥

⎦

5V – 2.3V 2.3V

A short-circuit to ground will result in a folded back cur-

rent of:

⎛ 95ns 22V ⎞

1

25mV

0.006Ω 2⎝ 3.9μH

(

)

I_SC

=

–

= 3.9A

⎜

⎟

⎠

⎛

⎞

V

OUT

ΔI

=

1–

L(NOM)

⎜

⎟

ƒ • L

V

IN(NOM)

⎝

⎠

with a typical value of R and δ = (0.005/°C)(25°C)

= 0.125. The resulting power dissipated in the bottom

DS(ON)

A 3.9μH inductor will produce 29% ripple current. The

peak inductor current will be the maximum DC value plus

one half the ripple current, or 6.88A. Increasing the ripple

current will also help ensure that the minimum on-time

of 95ns is not violated. The minimum on-time occurs at

MOSFET is:

2

P

SYNC

= 3.9A 1.125 0.022Ω = 376mW

(

) (

)(

)

maximum V :

IN

which is less than under full-load conditions.

V_OUT

3.3V

C is chosen for an RMS current rating of at least 3A at

temperature assuming only this channel is on. C

chosen with an ESR of 0.02ꢁ for low output ripple. The

output ripple in continuous mode will be highest at the

maximum input voltage. The output voltage ripple due to

ESR is approximately:

t_ON(MIN)

=

= 429ns

IN

V_IN(MAX)ƒ 22V 350kHz

(

)

is

OUT

The equivalent R

resistor value can be calculated by

SENSE

using the minimum value for the maximum current sense

threshold (43mV):

43mV

6.88A

V

= R (ΔI ) = 0.02ꢁ(1.75A) = 35mV

ESR L P-P

ORIPPLE

R_SENSE

≤

= 0.006Ω

Choosing 1% resistors: R = 25k and R = 80.6k yields

A

B

an output voltage of 3.33V.

38571fc

26

LTC3857-1

APPLICATIONS INFORMATION

PC Board Layout Checklist

6. Keep the switching nodes (SW1, SW2), top gate nodes

(TG1, TG2), andboostnodes(BOOST1, BOOST2)away

from sensitive small-signal nodes, especially from

the opposites channel’s voltage and current sensing

feedback pins. All of these nodes have very large and

fast moving signals and therefore should be kept on

the output side of the LTC3857-1 and occupy minimum

PC trace area.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layoutdiagramofFigure11.Figure12illustratesthecurrent

waveforms present in the various branches of the 2-phase

synchronousregulatorsoperatinginthecontinuousmode.

Check the following in your layout:

7.Useamodifiedstarground technique:alowimpedance,

large copper area central grounding point on the same

side of the PC board as the input and output capacitors

1. Are the top N-channel MOSFETs MTOP1 and MTOP2

located within 1cm of each other with a common drain

connection at C ? Do not attempt to split the input

IN

with tie-ins for the bottom of the INTV decoupling

CC

decoupling for the two channels as it can cause a large

resonant loop.

capacitor, the bottom of the voltage feedback resistive

divider and the SGND pin of the IC.

2. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return

PC Board Layout Debugging

of C

must return to the combined C

(–) ter-

INTVCC

OUT

Start with one controller on at a time. It is helpful to use

a DC-50MHz current probe to monitor the current in the

inductorwhiletestingthecircuit.Monitortheoutputswitch-

ing node (SW pin) to synchronize the oscilloscope to the

internal oscillator and probe the actual output voltage as

well. Check for proper performance over the operating

voltage and current range expected in the application.

The frequency of operation should be maintained over the

input voltage range down to dropout and until the output

load drops below the low current operation threshold—

typically 15% of the maximum designed current level in

Burst Mode operation.

minals. The path formed by the top N-channel MOSFET,

Schottky diode and the C capacitor should have short

IN

leads and PC trace lengths. The output capacitor (–)

terminals should be connected as close as possible

to the (–) terminals of the input capacitor by placing

the capacitors next to each other and away from the

Schottky loop described above.

3. DotheLTC3857-1V pins’resistivedividersconnectto

FB

the (+) terminals of C ? The resistive divider must be

OUT

connected between the (+) terminal of C

and signal

OUT

ground. The feedback resistor connections should not

be along the high current input feeds from the input

capacitor(s).

The duty cycle percentage should be maintained from

cycle to cycle in a well-designed, low noise PCB imple-

mentation. Variation in the duty cycle at a subharmonic

rate can suggest noise pickup at the current or voltage

sensing inputs or inadequate loop compensation. Over-

compensation of the loop can be used to tame a poor PC

layoutifregulatorbandwidthoptimizationisnotrequired.

Only after each controller is checked for its individual

performance should both controllers be turned on at the

same time. A particularly difficult region of operation is

when one controller channel is nearing its current com-

parator trip point when the other channel is turning on

its top MOSFET. This occurs around 50% duty cycle on

either channel due to the phasing of the internal clocks

and may cause minor duty cycle jitter.

–

+

4. Are the SENSE and SENSE leads routed together with

minimumPCtracespacing?Thefiltercapacitorbetween

+

–

SENSE and SENSE should be as close as possible

to the IC. Ensure accurate current sensing with Kelvin

connections at the SENSE resistor.

5. Is the INTV decoupling capacitor connected close

CC

to the IC, between the INTV and the power ground

CC

pins? This capacitor carries the MOSFET drivers’ cur-

rent peaks. An additional 1μF ceramic capacitor placed

immediatelynexttotheINTV andPGNDpinscanhelp

CC

improve noise performance substantially.

38571fc

27

LTC3857-1

APPLICATIONS INFORMATION

I

TRACK/SS1

PGOOD1

TG1

R

PU1

TH1

V

PULL-UP

V

PGOOD1

FB1

L1

R

SENSE

+

–

V

OUT1

SENSE1

SW1

LTC3857-1

BOOST1

C

B1

M1

M2

D1

BG1

FREQ

R

IN

C

OUT1

V

f

IN

1μF

PLLIN/MODE

RUN1

+

C

CERAMIC

VIN

PGND

GND

RUN2

+

EXTV

CC

C

IN

+

V

IN

C

SGND

INTVCC

–

INTV

SENSE2

OUT2

1μF

CERAMIC

+

BG2

SENSE2

M4

L2

M3

D2

BOOST2

V

FB2

TH2

C

B2

SW2

TG2

I

R

SENSE

V

OUT2

TRACK/SS2

38571 F11

Figure 11. Recommended Printed Circuit Layout Diagram

Reduce V from its nominal level to verify operation of

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

IN

the regulator in dropout. Check the operation of the un-

dervoltage lockout circuit by further lowering V while

IN

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

for inductive coupling between C , Schottky and the top

IN

38571fc

28

LTC3857-1

APPLICATIONS INFORMATION

SW1

L1

R

SENSE1

V

OUT1

D1

C

R

L1

OUT1

V

IN

R

IN

C

IN

SW2

L2

R

SENSE2

V

OUT2

D2

C

R

L2

OUT2

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

3857 F12

Figure 12. Branch Current Waveforms

The output voltage under this improper hookup will still

be maintained but the advantages of current mode control

will not be realized. Compensation of the voltage loop will

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

MOSFET components to the sensitive current and voltage

sensing traces. In addition, investigate common ground

path voltage pickup between these components and the

SGND pin of the IC.

An embarrassing problem, which can be missed in an

otherwise properly working switching regulator, results

when the current sensing leads are hooked up backwards.

38571fc

29

LTC3857-1

TYPICAL APPLICATIONS

R

B1

215k

LTC3857-1

+

C

SENSE1

F1

INTV

CC

C1

1nF

15pF

100k

–

R

A1

SENSE1

PGOOD1

BG1

68.1k

L1

3.3μH

MBOT1

MTOP1

V

FB1

V

3.3V

5A

OUT1

C

150pF

ITH1A

SW1

R

C

SENSE1

6mꢁ

OUT1

B1

BOOST1

TG1

150μF

0.47μF

R

15k

SS1

ITH1

I

TH1

D1

D2

C

820pF

ITH1

C

0.1μF

V

IN

V

IN

9V TO 38V

C

IN

TRACK/SS1

22μF

INTV

CC

C

4.7μF

INT

PGND

PLLIN/MODE

SGND

MTOP2

MBOT2

EXTV

TG2

CC

RUN1

RUN2

FREQ

C

B2

BOOST2

0.47μF

L2

7.2μH

R

SENSE2

8mꢁ

C

0.1μF

SS2

V

8.5V

3A

OUT2

SW2

BG2

TRACK/SS2

C

ITH2

680pF

OUT2

R

27k

150μF

ITH2

I

TH2

C

100pF

C2

ITH2A

V

FB2

R

A2

–

+

SENSE2

44.2k

C

1nF

F2

39pF

SENSE2

R

B2

422k

38571 F12

C

, C

: SANYO 10TPD150M

OUT1 OUT2

D1, D2: CENTRAL SEMI CMDSH-4E

L1: SUMIDA CDEP105-3R2M

L2: SUMIDA CDEP105-7R2M

MTOP1, MTOP2, MBOT1, MBOT2: VISHAY Si7848DP

Figure 13. High Efficiency Dual 3.3V/8.5V Step-Down Converter

38571fc

30

LTC3857-1

TYPICAL APPLICATIONS

High Efficiency Dual 2.5V/3.3V Step-Down Converter

R

B1

144k

LTC3857-1

+

C

SENSE1

INTV

CC

F1

C1

1nF

22pF

100k

–

R

A1

SENSE1

PGOOD1

BG1

68.1k

L1

2.4μH

MBOT1

MTOP1

V

FB1

V

2.5V

5A

OUT1

C

ITH1A

100pF

SW1

R

C

SENSE1

6mꢁ

OUT1

B1

BOOST1

TG1

150μF

0.47μF

R

ITH1

22k

I

TH1

D1

D2

C

820pF

ITH1

C

0.01μF

SS1

V

IN

V

IN

4V TO 38V

C

IN

TRACK/SS1

22μF

INTV

CC

C

INT

4.7μF

PGND

PLLIN/MODE

SGND

MTOP2

MBOT2

EXTV

TG2

CC

RUN1

RUN2

FREQ

C

B2

BOOST2

0.47μF

L2

3.2μH

R

SENSE2

6mꢁ

C

0.01μF

SS2

V

3.3V

5A

OUT2

SW2

BG2

TRACK/SS2

C

ITH2

820pF

OUT2

R

15k

150μF

ITH2

I

TH2

C

150pF

C2

ITH2A

V

FB2

R

A2

–

+

SENSE2

68.1k

C

1nF

F2

15pF

SENSE2

R

B2

215k

38571 TA02

C

, C

: SANYO 4TPE150M

OUT1 OUT2

D1, D2: CENTRAL SEMI CMDSH-4E

L1: SUMIDA CDEP105-2R5

L2: SUMIDA CDEP105-3R2M

MTOP1, MTOP2, MBOT1, MBOT2: VISHAY Si7848DP

38571fc

31

LTC3857-1

TYPICAL APPLICATIONS

High Efficiency Dual 12V/5V Step-Down Converter

R

B1

475k

+

C

SENSE1

INTV

F1

CC

C1

1nF

33pF

100k

–

R

A1

SENSE1

PGOOD1

BG1

34k

L1

8.8μH

MBOT1

MTOP1

V

FB1

V

12V

3A

OUT1

C

ITH1A

100pF

SW1

R

C

SENSE1

9mꢁ

OUT1

B1

BOOST1

TG1

47μF

0.47μF

R

ITH1

10k

I

TH1

D1

D2

C

SS1

0.01μF

LTC3857-1

C

680pF

ITH1

V

IN

V

TRACK/SS1

IN

12.5V TO 38V

C

IN

INTV

CC

C

22μF

INT

4.7μF

PGND

PLLIN/MODE

SGND

MTOP2

MBOT2

EXTV

TG2

CC

RUN1

RUN2

FREQ

R

C

FREQ

B2

BOOST2

60k

0.47μF

L2

4.3μH

R

SENSE2

6mꢁ

C

0.01μF

SS2

V

OUT2

5V

SW2

BG2

TRACK/SS2

5.5A

C

680pF

OUT2

ITH2

R

17k

150μF

ITH2

I

TH2

C

100pF

C2

ITH2A

V

FB2

C

: KEMET T525D476M016E035

: SANYO 10TPD150M

R

OUT1

OUT2

A2

–

+

SENSE2

C

75k

L1: SUMIDA CDEP105-5R7M

L2: SUMIDA CDEP105-4R3M

MTOP1, MTOP2, MBOT1, MBOT2: VISHAY Si7848DP

C

1nF

F2

15pF

SENSE2

R

B2

392k

38571 TA03

38571fc

32

LTC3857-1

TYPICAL APPLICATIONS

High Efficiency Dual 24V/5V Step-Down Converter

R

B1

487k

+

C

SENSE1

INTV

F1

CC

C1

1nF

18pF

100k

–

R

A1

SENSE1

PGOOD1

BG1

16.9k

L1

22μH

MBOT1

MTOP1

V

FB1

V

24V

1A

OUT1

C

100pF

ITH1A

SW1

R

C

SENSE1

OUT1

B1

BOOST1

TG1

25mꢁ

22μF

25V

s2

0.47μF

R

46k

ITH1

I

TH1

D1

D2

C

0.01μF

SS1

CERAMIC

LTC3857-1

C

680pF

ITH1

V

IN

V

TRACK/SS1

IN

28V TO 38V

C

IN

INTV

CC

C

4.7μF

22μF

INT

PGND

PLLIN/MODE

SGND

MTOP2

MBOT2

EXTV

TG2

CC

RUN1

RUN2

FREQ

R

C

FREQ

B2

BOOST2

60k

0.47μF

L2

4.3μH

R

SENSE2

6mꢁ

C

0.01μF

SS2

V

5V

5A

OUT2

SW2

BG2

TRACK/SS2

C

680pF

OUT2

ITH2

R

17k

150μF

ITH2

I

TH2

C

100pF

C2

ITH2A

V

FB2

R

A2

–

+

SENSE2

75k

C

: SANYO 10TPD150M

OUT2

L1: SUMIDA CDR7D43MN

C

1nF

F2

15pF

L2: SUMIDA CDEP105-4R3M

SENSE2

MTOP1, MTOP2, MBOT1, MBOT2: VISHAY Si7848DP

R

B2

392k

38571 TA04

38571fc

33

LTC3857-1

TYPICAL APPLICATIONS

High Efficiency Dual 1V/1.2V Step-Down Converter

R

B1

28.7k

+

C

SENSE1

F1

INTV

CC

C1

1nF

56pF

100k

–

R

A1

SENSE1

PGOOD1

BG1

115k

L1

0.47μH

MBOT1

MTOP1

V

FB1

V

OUT1

C

ITH1A

220pF

1V

SW1

C

R

OUT1 8A

C

SENSE1

B1

BOOST1

TG1

220μF

3.5mꢁ

0.47μF

R

ITH1

3.93k

s2

I

TH1

D1

D2

LTC3857-1

C

ITH1

1000pF

C

SS1

0.01μF

V

IN

V

IN

12V

C

IN

TRACK/SS1

22μF

INTV

CC

C

INT

4.7μF

PGND

PLLIN/MODE

SGND

MTOP2

MBOT2

EXTV

TG2

CC

RUN1

RUN2

FREQ

R

C

FREQ

B2

BOOST2

60k

0.47μF

L2

0.47μH

R

SENSE2

3.5mꢁ

C

0.01μF

SS2

V

OUT2

1.2V

SW2

BG2

TRACK/SS2

C

OUT2 8A

C

1000pF

ITH2

220μF

R

3.43k

ITH2

s2

I

TH2

C

220pF

C2

ITH2A

V

FB2

R

C

, C

: SANYO 2R5TPE220M

A2

OUT1 OUT2

–

+

SENSE2

115k

L1: SUMIDA CDEP105-3R2M

L2: SUMIDA CDEP105-7R2M

MTOP1, MTOP2: RENESAS RJK0305

MBOT1, MBOT2: RENESAS RJK0328

C

1nF

F2

56pF

SENSE2

R

B2

38571 TA05

57.6k

38571fc

34

LTC3857-1

TYPICAL APPLICATIONS

High Efficiency Dual 1V/1.2V Step-Down Converter with Inductor DCR Current Sensing

R

S1

1.18k

B1

28.7k

+

C

SENSE1

F1

INTV

CC

C1

0.1μF

56pF

100k

–

R

A1

PGOOD1

115k

L1

0.47μH

MBOT1

MTOP1

V

BG1

SW1

FB1

V

OUT1

C

ITH1A

200pF

1V

C

OUT1 8A

C

B1

BOOST1

TG1

220μF

0.47μF

R

ITH1

3.93k

s2

I

TH1

D1

D2

LTC3857-1

C

ITH1

1000pF

C

SS1

0.01μF

V

IN

V

IN

12V

C

IN

TRACK/SS1

22μF

INTV

CC

C

INT

4.7μF

PGND

PLLIN/MODE

SGND

MTOP2

MBOT2

EXTV

TG2

CC

RUN1

RUN2

FREQ

R

C

FREQ

B2

BOOST2

65k

0.47μF

L2

0.47μH

C

0.01μF

SS2

V

OUT2

1.2V

SW2

BG2

TRACK/SS2

C

OUT2 8A

C

1000pF

ITH2

220μF

R

3.43k

ITH2

s2

I

TH2

C

220pF

C2

ITH2A

V

FB2

R

A2

–

+

SENSE2

115k

C

, C

: SANYO 2R5TPE220M

OUT1 OUT2

L1, L2: SUMIDA IHL ERR47M06

MTOP1, MTOP2: RENESAS RJK0305

MBOT1, MBOT2: RENESAS RJK0328

C

0.1μF

F2

56pF

SENSE2

R

S2

1.18k

R

B2

57.6k

38571 TA06

38571fc

35

LTC3857-1

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.386 – .393*

(9.804 – 9.982)

.045 p.005

.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 p.0015

.0250 BSC

1

2

3

4

5

6

7

8

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

.015 p .004

.0532 – .0688

(1.35 – 1.75)

s 45o

.004 – .0098

(0.102 – 0.249)

(0.38 p 0.10)

.0075 – .0098

(0.19 – 0.25)

0o – 8o TYP

.016 – .050

(0.406 – 1.270)

.008 – .012

.0250

(0.635)

BSC

GN28 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

38571fc

36

LTC3857-1

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

12/09 Change to Absolute Maximum Ratings

Changes to Electrical Characteristics

Change to Typical Performance Characteristics

Change to Pin Functions

2

3, 4

6

8, 9

Text Changes to Operation Section

Text Changes to Applications Information Section

Change to Table 2

11, 12, 13

21, 22, 23, 26

23

28

38

3, 4

5

Change to Figure 11

Changes to Related Parts

B

C

12/10 Change to Electrical Characteristics

Change to Graph G07

Added Typical Application to back page and updated Related Parts

38

3

01/12 Added V conditions for I specification

FB

Q

Changed V to V in conditions for V specification

4

FB

FB1

PG

Changed 80μA to 65μA in the Light Load Current Operation section

12

15

+

–

Changed 24V to 28V in SENSE and SENSE Pins section

38571fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

37

LTC3857-1

TYPICAL APPLICATION

High Efficiency 2-Phase 12V/150W Step-Down Converter

R

B1

698k

INTV

CC

100k

+

–

C

SENSE1

F1

PGOOD2

C1

1nF

10pF

R

A1

49.9k

PGOOD1

BG1

L1

6μH

MBOT1

MTOP1

V

FB1

V

OUT

C

68pF

ITH1A

12V

SW1

C

22μF

16V

R

OUT1

12.5A

C

SENSE1

5mꢁ

10μF

16V

B1

0.47μF

BOOST1

TG1

R

ITH1

2.94k

I

TH1

D1

D2

LTC38571

C

ITH1

3300pF

C

0.1μF

SS1

V

IN

19V TO 28V

V

IN

C

10μF

50V

IN

TRACK/SS1

10μF

50V

I

INTV

CC

LIM

C

INT

4.7μF

PHSMD

CLKOUT

PLLIN/MODE

SGND

PGND

V

OUT

MTOP2

MBOT2

EXTV

TG2

CC

RUN1

RUN2

FREQ

C

B2

0.47μF

BOOST2

L2

6μH

R

SENSE2

5mꢁ

SW2

BG2

SS2

SS1

C

OUT2

10μF

16V

22μF

16V

I

TH1

TH2

V

FB1

V

FB2

C

, C : SANYO 1670C22M

OUT1 OUT2

–

+

SENSE2

L1: SUMIDA CDEP106-6ROM

C2

1nF

L2: SUMIDA CDEP106-6ROM

MTOP1, MTOP2: INFINEON BSZ097NO4LS

MBOT1, MBOT2: INFINEON BSZ097NO4LS

SENSE2

38571 TA07

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC3859

Low I , Triple Output Buck/Buck-Boost Synchronous Outputs (≥5V) Remain in Regulation Through Cold Crank, 2.5V ≤ V ≤ 38V,

Q

IN

DC/DC Controller

V

Up to 24V, V

Up to 60V, I = 55μA,

OUT(BUCK)

OUT(BOOST) Q

LTC3868/LTC3868-1 Low I , Dual Output 2-Phase Synchronous

Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz,

4V ≤ V ≤ 24V, 0.8V ≤ V ≤ 14V, I = 170μA,

Q

Step-Down DC/DC Controller with 99% Duty Cycle

IN

OUT

Q

LTC3858/LTC3858-1 Low I , Dual Output 2-Phase Synchronous

Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz,

4V ≤ V ≤ 38V, 0.8V ≤ V ≤ 24V, I = 170μA,

Q

Step-Down DC/DC Controller with 99% Duty Cycle

IN

OUT

Q

LTC3890/LTC3890-1 60V, Low I , Dual 2-Phase Synchronous Step-Down Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz,

Q

DC/DC Controller with 99% Duty Cycle

4V ≤ V ≤ 60V, 0.8V ≤ V

≤ 24V, I = 50μA,

OUT Q

IN

LTC3834/LTC3834-1 Low I , Synchronous Step-Down DC/DC Controller

Phase-Lockable Fixed Operating Frequency 140kHz to 650kHz,

4V ≤ V ≤ 36V, 0.8V ≤ V ≤ 10V, I = 30μA,

Q

IN

OUT

Q

LTC3835/LTC3835-1 Low I , Synchronous Step-Down DC/DC Controller

Phase-Lockable Fixed Operating Frequency 140kHz to 650kHz,

4V ≤ V ≤ 36V, 0.8V ≤ V ≤ 10V, I = 80μA,

Q

IN

OUT

Q

LT3845

Low I , High Voltage Synchronous Step-Down

Adjustable Fixed Operating Frequency 100kHz to 500kHz,

4V ≤ V ≤ 60V, 1.23V ≤ V ≤ 36V, I = 120μA, TSSOP-16

Q

DC/DC Controller

IN

OUT

Q

LTC3824

Low I , High Voltage DC/DC Controller, 100%

Selectable Fixed 200kHz to 600kHz Operating Frequency,

4V ≤ V ≤ 60V, 0.8V ≤ V ≤ V , I = 40μA, MSOP-10E

Q

Duty Cycle

IN

OUT

IN Q

38571fc

LT 0112 REV C • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

38

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3857EGN-1#PBF
厂家：	Linear
描述：	LTC3857-1 - Low IQ, Dual, 2-Phase Synchronous Step-Down Controller; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C 开关光电二极管
文件：	总38页 (文件大小：433K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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