LTC3859A [Linear]
60V Low IQ Step-Down DC/DC Controller with 100% Duty Cycle Capability; 60V低IQ降压型DC / DC采用100％占空比能力控制器
| 型号： | LTC3859A |
| 厂家： | 
Linear |
| 描述： | 60V Low IQ Step-Down DC/DC Controller with 100% Duty Cycle Capability |
| 文件： | 总28页 (文件大小：487K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3864
60V Low I Step-Down
Q
DC/DC Controller with
100% Duty Cycle Capability
DESCRIPTION
FEATURES
The LTC®3864 is a robust, high voltage step-down DC/DC
controller optimized for automotive and industrial applica-
tions. It drives a P-channel power MOSFET switch allowing
100% duty cycle operation. The wide input and output volt-
age ranges cover a multitude of applications. This device
has been verified with the failure mode and effects analysis
(FMEA) procedure for operation during failure conditions.
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Wide Operating V Range: 3.5V to 60V
IN
n
Wide V
Range: 0.8V to V
OUT
IN
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Low Operating I = 40µA
Q
Very Low Dropout Operation: 100% Duty Cycle
Strong High Voltage MOSFET Gate Driver
Constant Frequency Current Mode Architecture
Verified FMEA for Adjacent Pin Open/Short
Selectable High Efficiency Burst Mode® Operation or
Pulse-Skipping Mode at Light Loads
The LTC3864 offers excellent light load efficiency, draw-
ing only 40µA quiescent current in a user programmable
Burst Mode operation. Its peak current mode, constant
frequency PWM architecture provides for good control of
switching frequency and output current limit. The switch-
ing frequency can be programmed from 50kHz to 850kHz
with an external resistor and can be synchronized to an
external clock from 75kHz to 750kHz.
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Programmable Fixed Frequency: 50kHz to 850kHz
Phase-Lockable Frequency: 75kHz to 750kHz
Accurate Current Limit
Programmable Soft-Start or Voltage Tracking
Internal Soft-Start Guarantees Smooth Start-Up
Power Good Output Voltage Monitor
Low Shutdown I = 7µA
Available in Small 12-Pin Thermally Enhanced MSOP
and DFN Packages
Q
The LTC3864 offers programmable soft-start or output
tracking. Safety features include overvoltage protection,
overcurrent and short-circuit protection including fre-
quency foldback and a power good output signal.
APPLICATIONS
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The LTC3864 is available in thermally enhanced 12-Pin
MSOP and 3mm × 4mm DFN packages.
L, LT, LTC, LTM, OPTI-LOOP, Linear Technology, Burst Mode and the Linear logo are registered
trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents including 5731694.
Industrial and Automotive Power Supplies
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Telecom Power Supplies
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Distributed Power Systems
TYPICAL APPLICATION
5.2V to 60V Input, 5V/2A Output, 350kHz Step-Down Converter
Efficiency
V
*
IN
100
90
5.2V TO 60V
10µF
0.1µF
Burst Mode
OPERATION
CAP
RUN
V
IN
350kHz
9.09k
25mΩ
PLLIN/MODE
SS
80
70
60
50
SENSE
GATE
PULSE-SKIPPING
LTC3864
3.3nF
10µH
V
5V
2A
*
OUT
ITH
FREQ
100k
422k
47µF
×2
V
V
= 12V
OUT
IN
SGND
= 5V
PGOOD
0.01
0.1
LOAD CURRENT (A)
1
V
FB
PGND
80.6k
3864 TA01b
*V
FOLLOWS V
IN
OUT
WHEN 3.5V ≤ V ≤ 5.2V
IN
3864 TA01a
3864f
1
LTC3864
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Operating Junction Temperature Range (Notes 2, 3)
LTC3864E,I ....................................... –40°C to 125°C
LTC3864H.......................................... –40°C to 150°C
LTC3864MP....................................... –55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
Input Supply Voltage (V )......................... –0.3V to 65V
IN
V -V
IN CAP
Voltage ...................................... –0.3V to 6V
Voltage........................................ –0.3V to 10V
IN SENSE
V -V
RUN Voltage............................................... –0.3V to 65V
PGOOD, PLLIN/MODE Voltages ................... –0.3V to 6V
SS, ITH, FREQ, V Voltages........................ –0.3V to 5V
MSOP Package .................................................300°C
FB
PIN CONFIGURATION
TOP VIEW
TOP VIEW
PLLIN/MODE
FREQ
1
2
3
4
5
6
12 GATE
11
10 SENSE
1
2
3
4
5
6
PLLIN/MODE
FREQ
12 GATE
11
10 SENSE
V
IN
V
IN
SGND
13
SGND
SS
13
PGND
PGND
9
8
7
CAP
RUN
PGOOD
SS
9
8
7
CAP
V
FB
V
FB
RUN
ITH
ITH
PGOOD
MSE PACKAGE
12-LEAD PLASTIC MSOP
DE PACKAGE
T
= 150°C, θ = 40°C/W, θ = 10°C/W
JA JC
EXPOSED PAD (PIN 13) IS PGND, MUST BE SOLDERED TO PCB FOR OPTIMAL
THERMAL PERFORMANCE
JMAX
12-LEAD (4mm × 3mm) PLASTIC DFN
T
JMAX
= 150°C, θ = 43°C/W, θ = 5.5°C/W
JA JC
EXPOSED PAD (PIN 13) IS PGND, MUST BE SOLDERED TO PCB FOR OPTIMAL
THERMAL PERFORMANCE
ORDER INFORMATION
LEAD FREE FINISH
LTC3864EMSE#PBF
LTC3864IMSE#PBF
LTC3864HMSE#PBF
LTC3864MPMSE#PBF
LTC3864EDE#PBF
LTC3864IDE#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
LTC3864EMSE#TRPBF
LTC3864IMSE#TRPBF
LTC3864HMSE#TRPBF
3864
3864
3864
12-Lead Plastic MSOP
12-Lead Plastic MSOP
12-Lead Plastic MSOP
LTC3864MPMSE#TRPBF 3864
12-Lead Plastic MSOP
LTC3864EDE#TRPBF
LTC3864IDE#TRPBF
LTC3864HDE#TRPBF
LTC3864MPDE#TRPBF
3864
3864
3864
3864
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
LTC3864HDE#PBF
LTC3864MPDE#PBF
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3864f
2
LTC3864
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply
V
Input Voltage Operating Range
Undervoltage Lockout
3.5
60
V
IN
l
l
V
UVLO
(V -V ) Ramping Up Threshold
IN CAP
Hysteresis
3.25
3.00
3.50
3.25
0.25
3.8
3.50
V
V
V
IN CAP
(V -V ) Ramping Down Threshold
I
Q
Input DC Supply Current
Pulse-Skipping Mode
PLLIN/MODE = 0V, FREQ = 0V,
FB
0.77
40
7
1.2
60
12
mA
µA
µA
V
= 0.83V (No Load)
Burst Mode Operation
PLLIN/MODE = Open, FREQ = 0V,
= 0.83V (No Load)
V
FB
Shutdown Supply Current
RUN = 0V
Output Sensing
l
V
Regulated Feedback Voltage
V
V
= 1.2V (Note 5)
ITH
0.792
0.800
0.809
0.005
V
REG
∆V
∆V
Feedback Voltage Line Regulation
= 3.8V to 60V (Note 5)
–0.005
%/V
REG
IN
IN
∆V
∆V
Feedback Voltage Load Regulation
V
V
= 0.6V to 1.8V (Note 5)
–0.1
–0.015
0.1
%
REG
ITH
ITH
ITH
g
m(EA)
Error Amplifier Transconductance
Feedback Input Bias Current
= 1.2V, ∆I
=
5µA (Note 5)
1.8
mS
nA
ITH
I
–50
85
–10
50
FB
Current Sensing
l
l
V
Current Limit Threshold (V -V
)
V
V
= 0.77V
95
103
2
mV
µA
ILIM
IN SENSE
FB
I
SENSE Pin Input Current
= V
IN
0.1
SENSE
SENSE
Start-Up and Shutdown
V
V
RUN Pin Enable Threshold
RUN Pin Hysteresis
V
V
Rising
RUN
1.22
375
1.26
150
10
1.32
V
mV
µA
RUN
RUNHYS
I
SS
Soft-Start Pin Charging Current
= 0V
SS
Switching Frequency and Clock Synchronization
f
Programmable Switching Frequency
R
R
R
= 24.9kΩ
= 64.9kΩ
= 105kΩ
105
440
810
kHz
kHz
kHz
FREQ
FREQ
FREQ
505
f
f
f
Low Switching Frequency
High Switching Frequency
Synchronization Frequency
FREQ = 0V
320
485
75
350
535
380
585
750
kHz
kHz
kHz
V
LO
FREQ = Open
HI
l
l
l
SYNC
V
Clock Input High Level into PLLIN/MODE
Clock Input Low Level into PLLIN/MODE
2
CLK(IH)
CLK(LO)
FOLD
V
0.5
V
f
t
Foldback Frequency as Percentage of
Programmable Frequency
V
= 0V, V
= 0
FREQ
18
%
FB
Minimum On-Time
220
ns
ON(MIN)
Gate Driver
l
V
Gate Bias LDO Output Voltage (V -V
)
I
= 0mA
7.6
8.0
0.2
8.5
0.5
V
V
CAP
IN CAP
GATE
V
Gate Bias LDO Dropout Voltage
Gate Bias LDO Line Regulation
Gate Bias LDO Load Regulation
V
= 5V, I
= 15mA
GATE
CAPDROP
IN
∆V
∆V
9V ≤ V ≤ 60V, I = 0mA
GATE
0.002
0.03
%/V
CAP(LINE)
CAP(LOAD)
IN
Load = 0mA to 20mA
–3.5
%
3864f
3
LTC3864
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
Gate High
MIN
TYP
2
MAX
UNITS
Ω
R
UP
DN
Gate Pull-Up Resistance
Gate Pull-Down Resistance
R
Gate Low
0.9
Ω
PGOOD and Overvoltage
V
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
I
= 2mA
= 5V
0.2
0.4
1
V
PGL
PGOOD
I
PG
V
µA
PGOOD
%PGD
V
Ramping Negative with Respect to V
–13
7
–10
2.5
–7
%
%
FB
REG
Hysteresis
V
Ramping Positive with Respect to V
10
2.5
13
%
%
FB
REG
Hysteresis
t
PGOOD Delay
PGOOD Going High to Low
PGOOD Going Low to High
100
100
µs
µs
PGDLY
V
FBOV
V
Overvoltage Lockout Threshold
FB
GATE Going High without Delay,
FB(OV) FB(NOM)
10
%
V
-V
in Percent
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability or permanently damage
the device.
specifications over the –40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with statistical
process controls. The LTC3864I is guaranteed to meet performance
specifications over the –40°C to 125°C operating junction temperature
range, the LTC3864H is guaranteed over the –40°C to 150°C operating
junction temperature range, and the LTC3864MP is guaranteed and tested
over the full –55°C to 150°C operating junction temperature range. High
junction temperatures degrade operating lifetimes; operating lifetime is
derated for junction temperatures greater than 125°C. The maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors.
Note 3: The junction temperature (T in °C) is calculated from the ambient
J
temperature (T in °C) and power dissipation (P in Watts) as follows:
A
D
T = T + (P • θ )
JA
J
A
D
where θ (in °C/W) is the package thermal impedance provided in the Pin
JA
Configuration section for the corresponding package.
Note 5: The LTC3864 is tested in a feedback loop that adjust V to achieve
FB
Note 4: The LTC3864 is tested under pulsed loading conditions such that
a specified error amplifier output voltage (on ITH pin).
T ≈ T . The LTC3864E is guaranteed to meet performance specifications
J
A
from 0°C to 85°C operating junction temperature range. The LTC3864E
3864f
4
LTC3864
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Pulse-Skipping Mode Operation
Waveforms
Burst Mode Operation
Waveforms
Transient Response:
Pulse-Skipping Mode Operation
V
V
I
LOAD
2A/DIV
OUT
OUT
50mV/DIV
50mV/DIV
V
V
SW
SW
10V/DIV
10V/DIV
V
OUT
500mV/DIV
I
L
I
I
L
2A/DIV
L
500mA/DIV
500mA/DIV
3864 G02
3864 G03
2µs/DIV
10µs/DIV
100µs/DIV
V
V
= 12V
V
V
= 12V
V
V
= 12V
OUT
IN
IN
IN
= 5V
= 5V
= 5V
OUT
LOAD
OUT
LOAD
3864 G01
I
= 100mA
I
= 100mA
TRANSIENT = 100mA TO 2A
FIGURE 8 CIRCUIT
FIGURE 8 CIRCUIT
FIGURE 8 CIRCUIT
Transient Response:
Burst Mode Operation
Dropout Behavior (100% Duty
Cycle)
Low VIN Operation
V
IN
2V/DIV
I
LOAD
2A/DIV
V
PROGRAMMED TO 5V,
OUT
V
IN
BUT STARTS UP IN DROPOUT
V
OUT
1V/DIV
SINCE V < 5V
500mV/DIV
V
IN
OUT
2V/DIV
V
OUT
1V/DIV
V
OUT
= V IN DROPOUT
IN
GATE
10V/DIV
I
L
SW
5V/DIV
2A/DIV
3864 G05
3864 G04
3864 G06
50ms/DIV
100µs/DIV
20ms/DIV
V
TRANSIENT: 12V TO 4V
V
V
= 12V
OUT
V
= 0V TO 3.8V
IN
IN
IN
AND BACK TO 12V
= 5V, I
= 5V
THEN BACK TO 0V
V
OUT
= 100mA, FIGURE 8 CIRCUIT
LOAD
TRANSIENT = 100mA TO 2A
FIGURE 8 CIRCUIT
I
= 100mA
LOAD
FIGURE 8 CIRCUIT
Soft Start-Up into a Prebiased
Output
Normal Soft Start-Up
Output Tracking
RUN
5V/DIV
V
IN
5V/DIV
V
PREBIASED
OUT
TO 2.9V
SS
V
OUT
200mV/DIV
1V/DIV
SS
SS
200mV/DIV
200mV/DIV
V
V
OUT
2V/DIV
OUT
1V/DIV
3864 G09
3864 G07
3864 G08
20ms/DIV
= 5V
1ms/DIV
= 5V
OUT
1ms/DIV
= 5V
V
I
= 12V, V
OUT
LOAD
V
= 12V, V
V
I
= 12V, V
OUT
LOAD
IN
IN
IN
= 100mA
FIGURE 8 CIRCUIT
= 0.5mA
FIGURE 8 CIRCUIT
FIGURE 8 CIRCUIT
3864f
5
LTC3864
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Overcurrent Protection
Short-Ciruit Protection
VIN Line Transient Behavior
3.2A
SHORT-
CIRCUIT
TRIGGER
SHORT-CIRCUIT REGION
V
IN
20V/DIV
1A
1A
I
LOAD
V
1A/DIV
OUT
5V/DIV
GATE
20V/DIV
SOFT RECOVERY
FROM SHORT
I
L
1A/DIV
V
OUT
I
L
500mV/DIV
2A/DIV
V
OUT
50mV/DIV
V
DROOPS DUE TO
OUT
REACHING CURRENT LIMIT
3864 G12
3864 G10
3864 G11
20ms/DIV
= 5V
500µs/DIV
= 5V
2ms/DIV
V
V
LOAD
= 12V, SURGE TO 48V
= 5V
= 200mA, FIGURE 8 CIRCUIT
V
= 12V, V
V
= 12V, V
IN OUT
IN
OUT
IN
OUT
FIGURE 8 CIRCUIT
FIGURE 8 CIRCUIT
I
Pulse-Skipping Mode Input
Current Over Input Voltage
(No Load)
Burst Mode Input Current Over
Input Voltage (No Load)
Shutdown Current Over Input
Voltage
950
900
850
800
750
700
25
20
15
10
5
70
65
60
55
50
45
40
35
30
V
I
= 12V, V
= 0A
= 5V
OUT
FIGURE 8 CIRCUIT
V
I
= 12V, V
= 0A
= 5V
OUT
IN
LOAD
IN
LOAD
FIGURE 8 CIRCUIT
FIGURE 8 CIRCUIT
0
0
20
30
(V)
40
50
60
0
20
30
(V)
40
50
60
10
10
0
20
30
(V)
40
50
60
10
V
V
V
IN
IN
IN
3864 G14
3864 G15
3864 G13
Output Regulation Over Input
Voltage
Output Regulation Over Load
Current
Output Regulation Over
Temperature
0.010
0.005
0
1.0
0.8
0.010
0.005
0
V
I
= 12V, V
= 5V
V
I
= 12V, V
= 5V
OUT
V
I
= 5V
IN
OUT
IN
OUT
NORMALIZED AT I
= 1A
= 200mA
= 200mA
LOAD
LOAD
LOAD
LOAD
FIGURE 8 CIRCUIT
V
NORMALIZED TO T = 25°C
OUT A
V
NORMALIZED AT V = 12V
OUT
IN
0.6
FIGURE 8 CIRCUIT
FIGURE 8 CIRCUIT
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.005
–0.010
–0.005
–0.010
Burst Mode OPERATION
PULSE-SKIPPING
Burst Mode OPERATION
PULSE-SKIPPING
Burst Mode OPERATION
PULSE-SKIPPING
–0.5
0.5
1
1.5
2
2.5
–75
25
75
125
175
0
20
30
(V)
40
50
60
0
–25
10
I
(A)
TEMPERATURE (°C)
V
LOAD
IN
3864 G17
3864 G18
3864 G16
3864f
6
LTC3864
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Free Running Frequency Over
Input Voltage
Free Running Frequency Over
Temperature
Frequency Foldback % Over
Feedback Voltage
600
550
500
450
400
350
300
120
100
80
60
40
20
0
600
550
500
450
400
350
300
FREQ = OPEN
FREQ = OPEN
FREQ = 0V
FREQ = 0V
–75
25
75
125
175
0
400
(mV)
600
800
0
20
30
(V)
40
50
60
–25
200
10
TEMPERATURE (°C)
V
V
FB
IN
3864 G20
3864 G21
3864 G19
GATE Bias LDO (VIN - VCAP) Load
Regulation
GATE Bias LDO (VIN - VCAP
Dropout Behavior
)
Current Sense Voltage Over ITH
Voltage
100
90
80
70
60
50
40
30
20
10
0
0.5
0.0
0.1
0.0
V
= 5V
Burst Mode OPERATION
PULSE-SKIPPING
IN
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–0.1
–0.2
–0.3
–0.4
–0.5
–10
0
0.8
1.2
1.6
2
0.4
0
10
(mA)
15
20
5
0
10
(mA)
15
20
5
ITH VOLTAGE (V)
I
I
GATE
GATE
3864 G24
3864 G22
3864 G23
Current Sense Voltage Over
Temperature
SS Pin Pull-Up Current Over
Temperature
RUN Pin Pull-Up Current Over
Temperature
0.65
0.55
0.45
0.35
0.25
100
98
96
94
92
90
14
12
10
8
6
–75
25
75
125
175
–25
–75
25
75
125
175
–75
25
75
125
175
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3864 G27
3864 G25
3864 G26
3864f
7
LTC3864
PIN FUNCTIONS
PLLIN/MODE (Pin 1): External Reference Clock Input
and Burst Mode Enable/Disable. When an external clock
is applied to this pin, the internal phase-locked loop will
synchronize the turn-on edge of the gate drive signal with
the rising edge of the external clock. When no external
clockisapplied,thisinputdeterminestheoperationduring
point. The voltage ranges from 0V to 2.9V, with 0.8V cor-
responding to zero sense voltage (zero current).
PGOOD (Pin 7): Power Good Indicator Output. This open
drain logic output is pulled to ground when the output
voltageisoutsideofa 10%windowaroundtheregulation
point.ThePGOODswitchesstatesonlyaftera100µsdelay.
light loading. Floating this pin selects low I (40μA) Burst
Q
RUN (Pin 8): Digital Run Control Input. A RUN voltage
abovethe1.26Vthresholdenablesnormaloperation,while
a voltage below the threshold shuts down the controller.
An internal 0.4µA current source pulls the RUN pin up to
about 3.3V. The RUN pin can be connected to an external
power supply up to 60V.
Mode operation. Pulling to ground selects pulse-skipping
mode operation.
FREQ (Pin 2): Switching Frequency Set Point Input. The
switching frequency is programmed by an external set-
point resistor R
connected between the FREQ pin and
FREQ
signal ground. An internal 20µA current source creates
a voltage across the external setpoint resistor to set the
internal oscillator frequency. Alternatively, this pin can
be driven directly by a DC voltage to set the oscillator
frequency. Grounding selects a fixed operating frequency
of 350kHz. Floating selects a fixed operating frequency
of 535kHz.
CAP (Pin 9): Gate Driver (–) Supply. A low ESR ceramic
bypass capacitor of at least 0.1µF or 10X the effective
C
of the P-channel power MOSFET, is required
MILLER
from V to this pin to serve as a bypass capacitor for the
IN
internalregulator. Toinsurestablelownoiseoperation, the
bypass capacitor should be placed adjacent to the V and
IN
CAP pins and connected using the same PCB metal layer.
SGND (Pin 3): Ground Reference for Small Signal Analog
Component(SignalGround).Signalgroundshouldbeused
as the common ground for all small signal analog inputs
andcompensationcomponents.Connectsignalgroundto
power ground (ground reference for power components)
only at one point using a single PCB trace.
SENSE (Pin 10): Current Sense Input. A sense resistor
R
from V pin to the SENSE pin sets the maximum
SENSE
IN
current limit. The peak inductor current limit is equal to
95mV/R . For accuracy, it is important that the V
SENSE
IN
pin and the SENSE pin route directly to the current sense
resistor and make a Kelvin (4-wire) connection.
SS (Pin 4): Soft-Start and External Tracking Input. The
LTC3864 regulates the feedback voltage to the smaller of
0.8V or the voltage on the SS pin. An internal 10μA pull-up
current source is connected to this pin. A capacitor to
ground at this pin sets the ramp time to the final regulated
output voltage. Alternatively, another voltage supply con-
nected through a resistor divider to this pin allows the
output to track the other supply during start-up.
V
(Pin 11): Chip Power Supply. A minimum bypass
IN
capacitor of 0.1µF is required from the V pin to power
IN
ground. For best performance use a low ESR ceramic
capacitor placed near the V pin.
IN
GATE (Pin 12): Gate Drive Output for External P-Channel
MOSFET. The gate driver bias supply voltage (V -V
)
IN CAP
is regulated to 8V when V is greater than 8V. The gate
IN
V
(Pin 5): Output Feedback Sense. A resistor divider
driver is disabled when (V -V ) is less than 3.5V (typi-
FB
IN CAP
from the regulated output point to this pin sets the output
cal), 3.8V maximum in startup and 3.25V (typical) 3.5V
maximum in normal operation.
voltage. The LTC3864 will nominally regulate V to the
internal reference value of 0.8V. If V is less than 0.4V, the
FB
FB
PGND(ExposedPadPin13):GroundReferenceforPower
Components(PowerGround).ThePGNDexposedpadmust
be soldered to the circuit board for electrical contact and
for rated thermal performance of the package. Connect
signal ground to power ground only at one point using a
single PCB trace.
switching frequency will linearly decrease and fold back
to about one-fifth of the internal oscillator frequency to
reduce the minimum duty cycle.
ITH (Pin 6): Current Control Threshold and Controller
Compensation Point. This pin is the output of the error
amplifier and the switching regulator’s compensation
3864f
8
LTC3864
FUNCTIONAL DIAGRAM
V
IN
C
IN
UVLO
V
IN
+
–
3.25V
R
SENSE
SENSE
GATE
0.4µA
RUN
RUN
+
–
LOGIC
CONTROL
1.26V
–
DRV
MP
L
Q
V
OUT
S
R
IN
C
Burst Mode
OPERATION
OUT
LDO
C
CAF
CLOCK
PLLIN/MODE
OUT
O.425V
+
–
MODE/CLOCK
DETECT
CAP
V
– 8V
PLL
SYSTEM
IN
D1
ICMP
20µA
–
+
VCO
FREQ
R
FREQ
+
10µA
SS
SGND
+
+
–
0.8V
V
C
OUT
R
SLOPE
COMPENSATION
SS
PGD
EA
(G = 1.8mS)
R
FB2
O.88V
+
–
OV
PGOOD
m
V
FB
DELAY
100µs
+
–
UV
R
FB1
O.72V
PGND
ITH
3864 FD
R
ITH
C
ITH1
3864f
9
LTC3864
OPERATION
Main Control Loop (Refer to Functional Diagram)
Shutdown and Soft-Start
The LTC3864 uses a peak current-mode control architec-
ture to regulate the output in an asynchronous step-down
When the RUN pin is below 0.7V, the controller and most
internalcircuitsaredisabled.Inthismicropowershutdown
state, the LTC3864 draws only 7µA. Releasing the RUN
pin allows a small internal pull up current to pull the RUN
pin above 1.26V and enable the controller. The RUN pin
can be pulled up to an external supply of up to 60V or it
can be driven directly by logic levels.
DC/DC switching regulator. The V input is compared to
FB
an internal reference by a transconductance error ampli-
fier (EA). The internal reference can be either a fixed 0.8V
referenceV orthevoltageinputontheSSpin.Innormal
REF
operation V regulates to the internal 0.8V reference
FB
voltage. In soft-start or tracking mode, when the SS pin
The start-up of the output voltage V
is controlled by
OUT
voltage is less than the internal 0.8V reference voltage,
the voltage on the SS pin. When the voltage on the SS
V
FB
will regulate to the SS pin voltage. The error amplifier
pin is less than the 0.8V internal reference, the V pin is
FB
output connects to the ITH (current [I] threshold [TH])
pin. The voltage level on the ITH pin is then summed with
a slope compensation ramp to create the peak inductor
current set point.
regulated to the voltage on the SS pin. This allows the SS
pin to be used to program a soft-start by connecting an
external capacitor from the SS pin to signal ground. An
internal10µApull-upcurrentchargesthiscapacitor,creat-
ing a voltage ramp on the SS pin. As the SS voltage rises
The peak inductor current is measured through a sense
resistor R
placed across the V and SENSE pins.
from 0V to 0.8V, the output voltage V
from zero to its final value.
rises smoothly
SENSE
IN
OUT
The resultant differential voltage from V to SENSE is
IN
proportionaltotheinductorcurrentandiscomparedtothe
peak inductor current set point. During normal operation
the P-channel power MOSFET is turned on when the clock
leading edge sets the SR latch through the S input. The
P-channel MOSFET is turned off through the SR latch R
Alternatively, the SS pin can be used to cause the start-
up of V to track that of another supply. Typically, this
requires connecting the SS pin to an external resistor
dividerfromtheothersupplytoground. (SeeApplications
Information section.) Under shutdown or UVLO, the SS
pin is pulled to ground and prevented from ramping up.
OUT
input when the differential voltage from V to SENSE is
IN
greater than the peak inductor current set point and the
current comparator, ICMP, trips high.
If the slew rate of the SS pin is greater than 1.2V/ms, the
output will track an internal soft-start ramp instead of the
SS pin. The internal soft-start will guarantee a smooth
start-up of the output under all conditions, including in the
case of a short-circuit recovery where the output voltage
will recover from near ground.
Power CAP and V Undervoltage Lockout (UVLO)
IN
Power for the P-channel MOSFET gate driver is derived
from the CAP pin. The CAP pin is regulated to 8V below
V in order to provide efficient P-channel operation. The
IN
power for the V
supply comes from an internal LDO,
IN
CAP
Light Load Current Operation (Burst Mode Operation
or Pulse-Skipping Mode)
which regulates the V -CAP differential voltage. A mini-
mum capacitance of 0.1µF (low ESR ceramic) is required
The LTC3864 can be enabled to enter high efficiency Burst
Mode operation or pulse-skipping mode at light loads. To
select pulse-skipping operation, tie the PLLIN/MODE pin
to signal ground. To select Burst Mode operation, float
the PLLIN/MODE pin.
between V and CAP to assure stability.
IN
For V ≤ 8V, the LDO will be in dropout and the CAP volt-
IN
age will be at ground, i.e. the V -CAP differential voltage
IN
will equal V . If V -CAP is less than 3.25V (typical), the
IN
IN
LTC3864 enters aUVLO state where theGATE is prevented
In Burst Mode operation, if the V is higher than the refer-
from switching and most internal circuitry is shut down.
FB
ence voltage, the error amplifier will decrease the voltage
In order to exit UVLO, the V -CAP voltage would have to
IN
on the ITH pin. When the ITH voltage drops below 0.425V,
exceed 3.5V (typical).
3864f
10
LTC3864
OPERATION
the internal sleep signal goes high, enabling sleep mode.
The ITH pin is then disconnected from the output of the
error amplifier and held at 0.45V.
Theoscillator’sdefaultfrequencyisbasedontheoperating
frequency set by the FREQ pin. If the oscillator’s default
frequency is near the external clock frequency, only slight
adjustments are needed for the PLL to synchronize the
external P-channel MOSFET’s turn-on edge to the rising
edge of the external clock. This allows the PLL to lock
rapidly without deviating far from the desired frequency.
In sleep mode, much of the internal circuitry is turned
off, reducing the quiescent current to 40µA while the load
current is supplied by the output capacitor. As the output
voltage and hence the feedback voltage decreases, the
error amplifier’s output will rise. When the output voltage
drops enough, the ITH pin is reconnected to the output
of the error amplifier, the sleep signal goes low, and the
controller resumes normal operation by turning on the
external P-MOSFET on the next cycle of the internal oscil-
lator. In Burst Mode operation, the peak inductor current
has to reach at least 25% of current limit for the current
comparator, ICMP, to trip and turn the P-MOSFET back off,
even though the ITH voltage may indicate a lower current
setpoint value.
The PLL is guaranteed from 75kHz to 750kHz. The clock
input levels should be greater than 2V for HI and less
than 0.5V for LO.
Power Good and Fault Protection
The PGOOD pin is an open-drain output. An internal
N-channelMOSFETpullsthePGOODpinlowwhentheV
FB
pinvoltageisoutsidea 10%windowfromthe0.8Vinternal
voltage reference. The PGOOD pin is also pulled low when
the RUN pin is low (shut down). When the V pin voltage
FB
is within the 10% window, the MOSFET is turned off and
the pin is allowed to be pulled up by an external resistor
to a source no greater than 6V. The PGOOD open-drain
output has a 100µs delay before it can transition states.
WhenthePLLIN/MODEpinisconnectedforpulse-skipping
mode, the LTC3864 will skip pulses during light loads. In
thismode,ICMPmayremaintrippedforseveralcyclesand
force the external MOSFET to stay off, thereby skipping
pulses. This mode offers the benefits of smaller output
ripple, lower audible noise, and reduced RF interference,
attheexpenseoflowerefficiencywhencomparedtoBurst
Mode operation.
When the V voltage is above +10% of the regulated
FB
voltage of 0.8V, this is considered as an overvoltage con-
dition and the external P-MOSFET is immediately turned
off and prevented from ever turning on until V returns
FB
below +7.5%.
Frequency Selection and Clock Synchronization
In the event of an output short circuit or overcurrent con-
dition that causes the output voltage to drop significantly
while in current limit, the LTC3864 operating frequency
The switching frequency of the LTC3864 can be selected
using the FREQ pin. If the PLLIN/MODE pin is not being
driven by an external clock source, the FREQ pin can be
tied to signal ground, floated, or programmed through
an external resistor. Tying FREQ to signal ground selects
350kHz, while floating selects 535kHz. Placing a resistor
between FREQ and signal ground allows the frequency to
be programmed between 50kHz and 850kHz.
will fold back. Anytime the output feedback V voltage is
FB
less than 50% of the 0.8V internal reference (i.e., 0.4V),
frequency foldback is active. The frequency will continue
to drop as V drops until reaching a minimum foldback
FB
frequency of about 18% of the setpoint frequency. Fre-
quency foldback is designed, in combination with peak
current limit, to limit current in start-up and short-circuit
conditions.Settingthefoldbackfrequencyasapercentage
ofoperatingfrequencyassuresthatstart-upcharacteristics
scale appropriately with operating frequency.
The phase-locked loop (PLL) on the LTC3864 will syn-
chronize the internal oscillator to an external clock source
when connected to the PLLIN/MODE pin. The PLL forces
the turn-on edge of the external P-channel MOSFET to be
aligned with the rising edge of the synchronizing signal.
3864f
11
LTC3864
APPLICATIONS INFORMATION
The LTC3864 is a current mode, constant frequency PWM
controllerforanasynchronousstep-downDC/DCregulator
withaP-channelpowerMOSFETactingasthemainswitch
and a Schottky power diode acting as the commutating
(catch) diode. The input range extends from 3.5V to 60V.
The output range can be programmed from 0.8V to all the
V
OUT
R
C
FF
LTC3864
FB2
V
FB
R
FB1
3864 F01
way up to V . The LTC3864 can transition from regulation
IN
Figure 1. Setting the Output Voltage
to 100% duty cycle when the input voltage drops below
theprogrammedoutputvoltage.Additionally,theLTC3864
offers Burst Mode operation with 40µA quiescent current,
which delivers outstanding efficiency in light load opera-
tion. The LTC3864 is a low pin count, robust and easy to
use solution in applications which require high efficiency
and operate with widely varying high voltage inputs.
Switching Frequency and Clock Synchronization
The choice of operating frequency is a trade-off between
efficiencyandcomponentsize.Loweringtheoperatingfre-
quencyimprovesefficiencybyreducingMOSFETswitching
losses but requires larger inductance and/or capacitance
to maintain low output ripple voltage. Conversely, raising
the operating frequency degrades efficiency but reduces
component size.
ThetypicalapplicationonthefrontpageisabasicLTC3864
application circuit. The LTC3864 can sense the inductor
current through a high side series sense resistor, R
,
SENSE
placed between V and the source of the external P-
IN
The LTC3864 can free run at a user programmed switch-
ing frequency, or it can synchronize with an external
clock to run at the clock frequency. When the LTC3864
is synchronized, the GATE pin will phase synchronize
with the rising edge of the applied clock in order to turn
the external P-MOSFET on. The switching frequency of
the LTC3864 is programmed with the FREQ pin, and the
external clock is applied at the PLLIN/MODE pin. Table 1
highlights the different states in which the FREQ pin can
be used in conjunction with the PLLIN/MODE pin.
MOSFET. Once the required output voltage and operating
frequency have been determined, external component
selection is driven by load requirements, and begins with
the selection of inductor and R
. Next, the power
SENSE
MOSFET and catch diode are selected. Finally, input and
output capacitors are selected.
Output Voltage Programming
The output voltage is programmed by connecting a
feedback resistor divider from the output to the V pin
FB
Table 1
as shown in Figure 1. The output voltage in steady state
operation is set by the feedback resistors according to
the equation:
FREQ PIN
0V
PLLIN/MODE PIN
DC Voltage
FREQUENCY
350kHz
Floating
DC Voltage
535kHz
Resistor to GND
Any of the Above
DC Voltage
50kHz to 850kHz
R
R
FB2
VOUT = 0.8V • 1+
External Clock
Phase Locked to External
Clock
FB1
Toimprovethetransientresponse,afeedforwardcapacitor
C may be used. Great care should be taken to route the
FF
V
FB
line away from noise sources, such as the inductor
or the GATE signal that drives the external P-MOSFET.
3864f
12
LTC3864
APPLICATIONS INFORMATION
Thefree-runningswitchingfrequencycanbeprogrammed
from50kHzto850kHzbyconnectingaresistorfromFREQ
to signal ground. The resulting switching frequency as a
function of resistance on FREQ pin is shown in Figure 2.
this requires a large inductor. There is a trade-off between
component size, efficiency, and operating frequency.
A reasonable starting point for ripple current is 40% of
I
atnominalV . Thelargestripplecurrentoccurs
OUT(MAX)
IN
atthehighestV .Toguaranteethattheripplecurrentdoes
1000
900
800
700
600
500
400
300
200
100
IN
not exceed a specified maximum, the inductance should
be chosen according to:
VOUT
f • ∆IL(MAX)
VOUT
VIN(MAX)
L =
1–
Once the inductance value has been determined, the type
of inductor must be selected. Core loss is independent of
core size for a given inductor value, but it is very depen-
dent on the inductance selected. As inductance increases,
corelossesdecrease.Unfortunately,increasedinductance
requires more turns of wire and therefore copper losses
will increase.
0
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
3864 F02
Figure 2. Switching Frequency vs Resistor on FREQ
High efficiency converters generally cannot tolerate the
core loss of low cost powdered iron cores, forcing the use
of more expensive ferrite materials. Ferrite designs have
very low core loss and are preferred at high switching
frequencies, so design goals can concentrate on cop-
per loss and preventing saturation. Ferrite core material
saturates hard, which means that inductance collapses
abruptly when the peak design current is exceeded. This
will result in an abrupt increase in inductor ripple current
andoutputvoltageripple.Donotallowthecoretosaturate!
Set the free-running frequency to the desired synchroni-
zation frequency using the FREQ pin so that the internal
oscillatorisprebiasedtoapproximatelythesynchronization
frequency. While it is not required that the free-running
frequency be near the external clock frequency, doing so
will minimize synchronization time.
Inductor Selection
The operating frequency and inductor selection are inter-
relatedinthathigheroperatingfrequenciesallowtheuseof
smaller inductor and capacitor values. A higher frequency
generally results in lower efficiency because of MOSFET
gate charge and transition losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
A variety of inductors are available from manufacturers
such as Sumida, Panasonic, Coiltronics, Coilcraft, Toko,
Vishay, Pulse, and Würth.
Current Sensing and Current Limit Programming
The LTC3864 senses the inductor current through a cur-
Given the desired input and output voltages, the inductor
valueandoperationfrequencydeterminetheripplecurrent:
rent sense resistor, R
, placed across the V and
SENSE
IN
SENSE pins. The voltage across the resistor, V
, is
SENSE
proportional to inductor current and in normal operation
is compared to the peak inductor current setpoint. A
V
f •L
V
VIN
OUT
OUT
∆IL =
1–
current limit condition is detected when V
exceeds
SENSE
95mV. When the current limit threshold is exceeded, the
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and results in lower
output ripple. Highest efficiency operation is obtained at
lowfrequencywithsmallripplecurrent.However,achieving
P-channel MOSFET is immediately turned off by pulling
the GATE voltage to V regardless of the controller input.
IN
3864f
13
LTC3864
APPLICATIONS INFORMATION
The peak inductor current limit is equal to:
draincurrentI
JC(MOSFET)
,andtheMOSFET’sthermalresistance
JA(MOSFET)
D(MAX)
and θ
θ
.
95mV
RSENSE
IL(PEAK)
≅
The gate driver bias voltage V -V
is set by an internal
IN CAP
LDO regulator. In normal operation, the CAP pin will be
regulated to 8V below V . A minimum 0.1µF capacitor
IN
IN
This inductor current limit would translate to an output
current limit based on the inductor ripple:
is required across the V and CAP pins to ensure LDO
stability. If required, additional capacitance can be added
to accommodate higher gate currents without voltage
droop. In shutdown and Burst Mode operation, the CAP
LDO is turned off. In the event of CAP leakage to ground,
the CAP voltage is limited to 9V by a weak internal clamp
95mV ∆IL
ILIMIT
≅
–
RSENSE
2
The SENSE pin is a high impedance input with a maximum
leakage of 2µA. Since the LTC3864 is a peak current
mode controller, noise on the SENSE pin can create pulse
width jitter. Careful attention must be paid to the layout of
from V to CAP. As a result, a minimum 10V V rated
IN
GS
MOSFET is required.
The power dissipated by the P-channel MOSFET when the
LTC3864 is in continuous conduction mode is given by:
R
SENSE
. Toensuretheintegrityofthecurrentsensesignal,
SENSE
V
, the traces from V and SENSE pins should be
IN
2
PMOSFET ≅ D •I
• ρ •R
+
OUT
DS(ON)
τ
short and run together as a differential pair and Kelvin
(4-wire) connected across R
(Figure 3).
I
SENSE
2
OUT
2
V
•
• C
(
•
)
IN
MILLER
V
IN
V
IN
R
R
UP
DN
OPTIONAL
FILTERING
+
• f
R
SENSE
LTC3864
V – V
– V
V
(
)
IN
CAP
MILLER
MILLER
C
F
R
F
where D is duty factor, R
is on-resistance of
SENSE
DS(ON)
P-MOSFET, ρ is temperature coefficient of on-resistance,
t
MP
R
is the pull-down driver resistance specified at 0.9Ω
DN
3864 F03
typical and R is the pull-up driver resistance specified at
UP
2Ω typical. V
is the Miller effective V voltage and
Figure 3. Inductor Current Sensing
MILLER
GS
is taken graphically from the power MOSFET data sheet.
The LTC3864 has internal filtering of the current sense
voltage which should be adequate in most applications.
However, adding a provision for an external filter offers
added flexibility and noise immunity, should it be neces-
sary.Thefiltercanbecreatedbyplacingaresistorfromthe
The power MOSFET input capacitance C is
MILLER
the most important selection criteria for determin-
ing the transition loss term in the P-channel MOSFET
but is not directly specified on MOSFET data sheets.
C
is a combination of several components, but
MILLER
R
resistor to the SENSE pin and a capacitor across
SENSE
it can be derived from the typical gate charge curve
included on most data sheets (Figure 4). The curve is
the V and SENSE pins.
IN
Power MOSFET Selection
S
D
G
MILLER EFFECT
V
SG
+
–
The LTC3864 drives a P-channel power MOSFET that
serves as the main switch for the asynchronous step-
down converter. Important P-channel power MOSFET
parameters include drain-to-source breakdown voltage
V
SD(TEST)
a
b
I
R
LOAD
GATE
Q
IN
C
= (Q – Q )/V
B A SD(TEST)
3864 F04
MILLER
(b)
(a)
V
,thresholdvoltageV
,on-resistanceR
,
BR(DSS)
GS(TH)
DS(ON)
Figure 4. (a) Typical P-MOSFET Gate Charge Characteristics
and (b) Test Set-Up to Generate Gate Charge Curve
gate-to-drainreversetransfercapacitanceC ,maximum
RSS
3864f
14
LTC3864
APPLICATIONS INFORMATION
generated by forcing a constant current out of the gate of a
common-sourceconnectedP-MOSFETthatisloadedwith
a resistor, and then plotting the gate voltage versus time.
The initial slope is the effect of the gate-to-source and
gate-to-drain capacitances. The flat portion of the curve
is the result of the Miller multiplication effect of the drain-
to-gate capacitance as the drain voltage rises across the
resistor load. The Miller charge (the increase in coulombs
on the horizontal axis from a to b while the curve is flat) is
P
P
as a function of average forward current I
.
F(AVG)
DIODE
DIODE
can also be iteratively determined by the two
is a function of both
equations below, where V
,
F(IOUT TJ)
I
and junction temperature T . Note that the thermal
F(AVG)
J
resistance θ
given in the data sheet is typical and
JA(DIODE)
can be highly layout dependent. It is therefore important
to make sure that the Schottky diode has adequate heat
sinking.
T ≅P
•θJA(DIODE)
specified for a given V test voltage, but can be adjusted
J
DIODE
SD
for different V voltages by multiplying by the ratio of
P
≅I
• V
SD
DIODE F(AVG) F(IOUT,TJ)
the adjusted V to the curve specified V value. A way
SD
SD
to estimate the C
term is to take the change in gate
The Schottky diode forward voltage is a function of both
MILLER
charge from points a and b (or the parameter Q on a
GD
I
and T , so several iterations may be required to
F(AVG) J
manufacturer’s data sheet) and dividing it by the specified
satisfy both equations. The Schottky forward voltage V
F
V
SD
test voltage, V
.
SD(TEST)
should be taken from the Schottky diode data sheet curve
showing Instantaneous Forward Voltage. The forward
Q
GD
C
≅
voltage will increase as a function of both T and I
.
F(AVG)
MILLER
J
V
SD(TEST)
The nominal forward voltage will also tend to increase as
the reverse breakdown voltage increases. It is therefore
advantageous to select a Schottky diode appropriate to
the input voltage requirements.
The term with C
accounts for transition loss, which
MILLER
is highest at high input voltages. For V < 20V, the high-
IN
currentefficiencygenerallyimproveswithlargerMOSFETs,
while for V > 20V, the transition losses rapidly increase
IN
C and C
IN
Selection
OUT
to the point that the use of a higher R
device with
DS(ON)
The input capacitance C is required to filter the square
lower C
actually provides higher efficiency.
IN
MILLER
wave current through the P-channel MOSFET. Use a low
Schottky Diode Selection
ESR capacitor sized to handle the maximum RMS current.
WhentheP-MOSFETisturnedoff, apowerSchottkydiode
isrequiredtofunctionasacommutatingdiodetocarrythe
inductor current. The average diode current is therefore
dependent on the P-MOSFET’s duty factor. The worst case
condition for diode conduction is a short-circuit condition
where the Schottky must handle the maximum current
as its duty factor approaches 100% (and the P-channel
MOSFET’s duty factor approaches 0%). The diode there-
fore must be chosen carefully to meet worst case voltage
and current requirements. The equation below describes
the continuous or average forward diode current rating
required, where D is the regulator duty factor.
V
V
V
IN
OUT
I
≅I
•
•
–1
CIN(RMS) OUT(MAX)
V
IN
OUT
The formula has a maximum at V = 2V , where
IN
OUT
I
= I
/2. This simple worst-case condition
CIN(RMS) OUT(MAX)
is commonly used for design because even significant
deviations do not offer much relief. Note that ripple cur-
rent ratings from capacitor manufacturers are often based
on only 2000 hours of life, which makes it advisable to
derate the capacitor.
The selection of C
is primarily determined by the ESR
requiredtominimizevoltagerippleandloadsteptransients.
The ∆V is approximately bounded by:
OUT
I
≅I
• 1–D
(
)
F(AVG) OUT(MAX)
OUT
Once the average forward diode current is calculated,
the power dissipation can be determined. Refer to the
Schottky diode data sheet for the power dissipation
1
∆V
≤ ∆I ESR+
OUT
L
8•f•C
OUT
3864f
15
LTC3864
APPLICATIONS INFORMATION
External Soft-Start and Output Tracking
Since ∆I increases with input voltage, the output ripple
L
is highest at maximum input voltage. Typically, once the
ESR requirement is satisfied, the capacitance is adequate
for filtering and has the necessary RMS current rating.
Start-up characteristics are controlled by the voltage on
the SS pin. When the voltage on the SS pin is less than
the internal 0.8V reference, the LTC3864 regulates the V
FB
pin voltage to the voltage on the SS pin. When the SS pin
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, specialty polymer, aluminum electrolytic
and ceramic capacitors are all available in surface mount
packages. Specialty polymer capacitors offer very low
ESR but have lower specific capacitance than other types.
Tantalumcapacitorshavethehighestspecificcapacitance,
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications provided that
consideration is given to ripple current ratings and long-
termreliability.CeramiccapacitorshaveexcellentlowESR
characteristics but can have a high voltage coefficient and
audible piezoelectric effects.
is greater than the internal 0.8V reference, the V pin
FB
voltage regulates to the 0.8V internal reference. The SS
pin can be used to program an external soft-start function
or to allow V
to track another supply during start-up.
OUT
Soft-start is enabled by connecting a capacitor from
the SS pin to ground. An internal 10µA current source
charges the capacitor, providing a linear ramping voltage
at the SS pin that causes V
to rise smoothly from 0V
OUT
to its final regulated value. The total soft-start time will
be approximately:
0.8V
10µA
t
= C
•
SS
SS
When the LTC3864 is configured to track another supply,
a voltage divider can be used from the tracking supply to
the SS pin to scale the ramp rate appropriately. Two com-
mon implementations of tracking as shown in Figure 5a
are coincident and ratiometric. For coincident tracking,
make the divider ratio from the external supply the same
as the divider ratio for the feedback voltage. Ratiometric
tracking could be achieved by using a different ratio than
the feedback (Figure 5b).
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing. When used as input
capacitors, care must be taken to ensure that ringing from
inrush currents and switching does not pose an overvolt-
age hazard to the power switch and controller. To dampen
inputvoltagetransients,addasmall5μFto40μFaluminum
electrolytic capacitor with an ESR in the range of 0.5Ω to
2Ω. High performance through-hole capacitors may also
be used, but an additional ceramic capacitor in parallel
is recommended to reduce the effect of lead inductance.
Notethatthesoft-startcapacitorchargingcurrentisalways
flowing, producing a small offset error. To minimize this
error,selectthetrackingresistivedividervaluestobesmall
enough to make this offset error negligible.
Discontinuous and Continuous Operation
TheLTC3864operatesindiscontinuousconduction(DCM)
until the load current is high enough for the inductor
current to be positive at the end of the switching cycle.
The output load current at the continuous/discontinuous
Short-Circuit Faults: Current Limit and Foldback
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage.
In the LTC3864, the maximum sense voltage is 95mV,
boundary I
is given by the following equation:
OUT(CDB)
(V – V
)( V
+ V )
IN
OUT
OUT F
I
≅
OUT(CDB)
measured across the inductor sense resistor R
,
SENSE
2• L • f •(V + V )
IN
F
placed across the V and SENSE pins. The output current
IN
limit is approximately:
The continuous/discontinuous boundary is inversely
proportional to the inductor value. Therefore, if required,
95mV ∆I
L
I
≅
–
I
can be reduced by increasing the inductor value.
LIMIT
OUT(CDB)
R
2
SENSE
3864f
16
LTC3864
APPLICATIONS INFORMATION
The current limit must be chosen to ensure that I
Short-Circuit Recovery and Internal Soft-Start
LIMIT(MIN)
> I
under all operating conditions. The minimum
OUT(MAX)
An internal soft-start feature guarantees a maximum posi-
tive output voltage slew rate in all operational cases. In a
short-circuit recovery condition for example, the output
recovery rate is limited by the internal soft-start so that
output voltage overshoot and excessive inductor current
buildup is prevented.
current limit value should be greater than the inductor
current required to produce maximum output power at
worst case efficiency. Worst-case efficiency typically oc-
curs at the highest V .
IN
Short-circuitfaultprotectionisassuredbythecombination
of current limit and frequency foldback. When the output
The internal soft-start voltage and the external SS pin
operate independently. The output will track the lower of
the two voltages. The slew rate of the internal soft-start
voltage is roughly 1.2V/ms, which translates to a total
soft-start time of 650µs. If the slew rate of the SS pin
is greater than 1.2V/ms the output will track the internal
soft-start ramp. To assure robust fault recovery, the
feedback voltage V drops below 0.4V, the operating
FB
frequency f will fold back to a minimum value of 0.18 • f
when V reaches 0V. Both current limit and frequency
FB
foldback are active in all modes of operation. In a short-
circuit fault condition, the output current is first limited by
current limit and then further reduced by folding back the
operating frequency as the short becomes more severe.
EXTERNAL
SUPPLY
EXTERNAL
SUPPLY
V
V
OUT
OUT
3864 F05a
TIME
TIME
Ratiometric Tracking
Coincident Tracking
Figure 5(a). Two Different Modes of Output Tracking
EXT. V
TO SS
V
EXT. V
V
OUT
OUT
R
R
R
R
R1
R
R
FB2
FB1
FB2
FB2
R2
R1+ R2 EXT. V
R2
0.8V
≥
TO V
TO V
FB
TO SS
FB
FB1
FB1
3864 F05b
Coincident Tracking Setup
Ratiometric Tracking Setup
Figure 5(b): Setup for Ratiometric and Coincident Tracking
3864f
17
LTC3864
APPLICATIONS INFORMATION
internal soft-start feature is active in all operational cases.
Ifashort-circuitconditionoccurswhichcausestheoutput
to drop significantly, the internal soft-start will assure a
soft recovery when the fault condition is removed.
guaranteed to operate down to a V of 3.5V over the full
IN
temperature range.
The implications of both the UVLO rising and UVLO falling
specifications must be carefully considered for low V
IN
The internal soft-start assures a clean soft ramp-up from
any fault condition that causes the output to droop, guar-
anteeing a maximum ramp rate in soft-start, short-circuit
fault release, or output recovery from drop out. Figure 6
illustrates how internal soft-start controls the output
ramp-up rate under varying scenarios.
operation. The UVLO threshold with V rising is typi-
IN
cally 3.5V (with a maximum of 3.8V) and UVLO falling is
typically 3.25V (with a maximum of 3.5V). The operating
input voltage range of the LTC3864 is guaranteed to be
3.5V to 60V over temperature, but the initial V ramp
IN
must exceed 3.8V to guarantee start-up.
For example, Figure 7 illustrates LTC3864 operation when
an automotive battery droops during a cold crank condi-
tion. The typical automotive battery is 12V to 14V, which is
more than enough headroom above 3.8V for the LTC3864
to start up. Onboard electronics which are powered by a
DC/DC regulator require a minimum supply voltage for
seamless operation during the cold crank condition, and
the battery may droop close to these minimum supply
requirements during a cold crank. The DC/DC regulator
should not exacerbate the situation by having excessive
dropout between the already suppressed battery voltage
input and the output of the regulator which power these
electronics. As seen in Figure 7, the LTC3864’s 100%
duty cycle capability allows virtually no dropout (only the
V
IN
V
OUT
INTERNAL SOFT-START INDUCED START-UP
(NO EXTERNAL SOFT-START CAPACITOR)
~ 650µs
TIME
(a)
V
OUT
SHORT-CIRCUIT
INTERNAL SOFT-START
INDUCED RECOVERY
TIME
I
• (R
+ R
) drop across the sense resistor
OUT
SENSE
DS(ON)
(b)
andP-MOSFETifthereisasignificantI )fromthebattery
OUT
to the output. The 3.5V guaranteed UVLO point assures
sufficientmarginforcontinuous,uninterruptedoperationin
extreme cold crank battery drooping conditions. However,
additional input capacitance or slower soft start-up time
V
V
IN
V
IN
OUT
DROPOUT
INTERNAL SOFT-START
INDUCED RECOVERY
may be required at low V (e.g. 3.5V to 4.5V) in order to
IN
limit V droop caused by inrush currents, especially if
IN
the battery or input source has a sufficiently large input
TIME
impedance.
(c)
3864 F06
V
BATTERY
Figure 6. Internal Soft-Start (a) Allows Soft Start-Up without
an External Soft-Start Capacitor and Allows Soft Recovery from
(b) a Short-Circuit or (c) a VIN Dropout
12V
5V
V Undervoltage Lockout (UVLO)
IN
V
OUT
LTC3864’s 100% DUTY CYCLE CAPABILITY ALLOWS
TO RIDE V WITHOUT SIGNIFICANT DROP-OUT
The LTC3864 is designed to accommodate applications
requiring widely varying power input voltages from 3.5V
V
OUT
IN
TIME
3864 F07
to 60V. To accommodate the cases where V drops
IN
significantly once in regulation, the LTC3864 is
Figure 7. Typical Automotive Cold Crank
3864f
18
LTC3864
APPLICATIONS INFORMATION
Minimum On-Time Considerations
2. Transition Loss: Transition loss of the P-channel MOS-
FET becomes significant only when operating at high
input voltages (typically 20V or greater.) The P-channel
The minimum on-time, t
, is the smallest time
ON(MIN)
duration that the LTC3864 is capable of turning on the
power MOSFET, and is typically 220ns. It is determined
by internal timing delays and the gate charge required to
turn on the MOSFET. Low-duty-cycle applications may
approach this minimum on-time limit, so care should be
taken to ensure that:
transitionlosses(P
following equation:
)canbedeterminedfromthe
MOSTRL
I
2
OUT
2
P
= V
•
•(C
)•
PMOSTRL
IN
MILLER
R
R
DN
UP
+
• f
V
OUT
(V – V )– V
V
MILLER
t
<
IN
CAP
MILLER
ON(MIN)
V
• f
IN(MAX)
3. Gate Charging Loss: Charging and discharging the gate
of the MOSFET will result in an effective gate charg-
ing current. Each time the P-channel MOSFET gate is
switched from low to high and low again, a packet of
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will skip cycles.
However, the output voltage will continue to regulate.
charge dQ moves from the capacitor across V – V
IN
CAP
Efficiency Considerations
andisthenreplenishedfromgroundbytheinternalV
CAP
regulator. The resulting dQ/dt current is a current out
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
the dominant contributors and therefore where efficiency
improvements can be made. Percent efficiency can be
expressed as:
of V flowing to ground. The total power loss in the
IN
controller including gate charging loss is determined
by the following equation:
P
= V •(I +f•Q
)
CNTRL
IN
Q
G(PMOSFET)
% Efficiency = 100% - (L1+L2+L3+…)
4. Schottky Loss: The Schottky diode loss is most signifi-
cant at low duty factors (high step down ratios). The
critical component is the Schottky forward voltage as
a function of junction temperature and current. The
Schottky power loss is given by the equation below.
where L1, L2, L3, etc., are the individual losses as a per-
centage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources account for most of the losses
in LTC3864 application circuits.
P
≅(1–D)•I
•V
DIODE
OUT F(IOUT,TJ)
2
2
1. I RLoss:I RlossesresultfromtheP-channelMOSFET
resistance,inductorresistance,thecurrentsenseresis-
tor, and input and output capacitor ESR. In continuous
modeoperationtheaverageoutputcurrentflowsthrough
L but is chopped between the P-channel MOSFET and
the bottom side Schottky diode. The following equation
When making adjustments to improve efficiency, the in-
put current is the best indicator of changes in efficiency.
If changes cause the input current to decrease, then the
efficiency has increased. If there is no change in input
current, there is no change in efficiency.
2
may be used to determine the total I R loss:
OPTI-LOOP® Compensation
2
2
2
P
≈(I
+∆I /12)•[ R
+D•(R +R
DS(ON) SENSE
I R
OUT
L
DCR
OPTI-LOOP compensation, through the availability of the
ITH pin, allows the transient response to be optimized for
a wide range of loads and output capacitors. The ITH pin
not only allows optimization of the control loop behavior
2
+ R
)]+∆I / 12 • R
ESR(CIN)
L
ESR(COUT)
3864f
19
LTC3864
APPLICATIONS INFORMATION
butalsoprovidesatestpointforthestep-downregulator’s
DC-coupledandAC-filteredclosed-loopresponse.TheDC
step,risetimeandsettlingatthistestpointtrulyreflectsthe
closed-loop response. Assuming a predominantly second
ordersystem, phase marginand/or dampingfactorcanbe
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at this pin.
of the feedback loop, so this signal cannot be used to
determine phase margin. This is why it is better to look
at the ITH pin signal which is in the feedback loop and
is the filtered and compensated feedback loop response.
ThegainoftheloopincreaseswithR andthebandwidth
ITH
of the loop increases with decreasing C
. If R is
ITH1
ITH
increased by the same factor that C
is decreased, the
ITH1
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
TheITHseriesR -C
filtersetsthedominantpole-zero
ITH ITH1
loop compensation. Additionally, a small capacitor placed
fromtheITHpintosignalground,C ,mayberequiredto
feedbackloop.Inaddition,afeedforwardcapacitor,C ,can
FF
beaddedtoimprovethehighfrequencyresponse,asshown
ITH2
attenuatehighfrequencynoise.Thevaluescanbemodified
to optimize transient response once the final PCB layout
is done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selectedbecausetheirvarioustypesandvaluesdetermine
theloopfeedbackfactorgainandphase. Anoutputcurrent
pulse of 20% to 100% of full load current having a rise
time of 1μs to 10μs will produce output voltage and ITH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The general
goal of OPTI-LOOP compensation is to realize a fast but
stable ITH response with minimal output droop due to
the load step. For a detailed explanation of OPTI-LOOP
compensation, refer to Application Note 76.
in Figure 1. Capacitor C provides phase lead by creating
FF
a high frequency zero with R which improves the phase
FB2
margin. The output voltage settling behavior is related to
thestabilityoftheclosed-loopsystemandwilldemonstrate
overall performance of the step-down regulator.
Insomeapplications,amoreseveretransientcanbecaused
by switching in loads with large (>10μF) input capacitors.
If the switch connecting the load has low resistance and
is driven quickly, then the discharged input capacitors are
effectivelyputinparallelwithC , causingarapiddropin
OUT
V
OUT
. No regulator can deliver enough current to prevent
this problem. The solution is to limit the turn-on speed of
the load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates cur-
rent limiting, short-circuit protection and soft starting.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V
im-
OUT
•ESR,where
Design Example
mediatelyshiftsbyanamountequalto∆I
LOAD
Consider a step-down converter with the following
ESR is the effective series resistance of C . ∆I
also
OUT
LOAD
specifications: V = 5V to 55V, V
= 5V, I = 2A,
beginstochargeordischargeC ,generatingafeedback
IN
OUT
OUT(MAX)
OUT
and f = 350kHz (Figure 8).
error signal used by the regulator to return V
to its
can
OUT
steady-state value. During this recovery time, V
OUT
The output voltage is programmed according to:
be monitored for overshoot or ringing that would indicate
a stability problem.
R
R
FB2
V
= 0.8V • 1+
OUT
FB1
ConnectingaresistiveloadinserieswithapowerMOSFET,
then placing the two directly across the output capacitor
and driving the gate with an appropriate signal generator
is a practical way to produce a realistic load-step condi-
tion. The initial output voltage step resulting from the step
change in output current may not be within the bandwidth
If R
is chosen to be 80.6k, then R
would have to
FB2
FB1
be 422k.
3864f
20
LTC3864
APPLICATIONS INFORMATION
The FREQ pin is tied to signal ground in order to program
the switching frequency to 350kHz. The on-time required
at 55V to generate a 5V output can be calculated as:
Next, set the R
resistor value to ensure that the
SENSE
converter can deliver a maximum output current of 2.0A
with sufficient margin to account for component varia-
tions and worst-case operating conditions. Using a 30%
margin factor:
V
5V
OUT
t
=
=
≈260ns
ON
V •f 55V •350kHz
IN
95mV
R
≅
≈27.5mΩ
SENSE
1.3A
This on-time is larger than LTC3864’s minimum on-time
with sufficient margin to prevent cycle skipping.
1.3• 2A+
2
Next, set the inductor value to give 60% worst-case ripple
Use a more readily available 25mΩ sense resistor.
The current limit is:
at maximum V = 55V.
IN
1–
5V
5V
55V
L =
≈10.8µH
95mV 1.3A
I
≅
–
≈3.15A
350kHz •(0.6•2A)
LIMIT
25mΩ
2
Select 10µH, which is a standard value.
The resulting maximum ripple current is:
Next choose a P-channel MOSFET with the appropri-
ate BV and I rating. In this example, a good choice
DSS
D
is the Fairchild FDMC5614P (BV
= 60V, I = 5.7A,
DSS
= 1.5, C
D
5V
350kHz •10µH
5V
55V
R
θ
= 105mΩ, ρ
= 100pF,
MILLER
1–
∆I =
≈1.3A
DS(ON)
100°C
L
= 60°C/W). The expected power dissipation and the
JA
Efficiency
V
*
IN
5.2V TO 55V
100
+
C
C
12µF
63V
CAP
C
IN2
4.7µF
IN1
0.1µF
R
RUN
100k
Burst Mode
OPERATION
90
CAP
RUN
V
IN
C
VIN
C
R
SENSE
SS
80
70
60
50
MODE/PLLN
SS
0.1µF
25mΩ
0.1µF
PULSE-SKIPPING
SENSE
GATE
C
ITH1
3.3nF
LTC3864
L1
10µH
MP
D1
R
9.53k
ITH
V
5V
2A
*
OUT
ITH
SW
C
100pF
ITH2
R
PGD
100k
V
V
= 12V
OUT
IN
47µF
×2
= 5V
C
FF
47pF
FREQ
0.01
0.1
LOAD CURRENT (A)
1
R
FB2
422k
PGOOD
VFB
SGND
3864 F08b
PGND
R
FB1
80.6k
3864 F08a
C
: NICHICON UPJ1J120MDD
IN1
D1: DIODES INC SBR3U100LP
L1: TOKO 1217AS-H-100M
MP: FAIRCHILD FDMC5614P
*V
FOLLOWS V WHEN 3.5V ≤ V ≤ 5.2V
IN IN
OUT
SEE DROPOUT BEHAVIOR IN TYPICAL PERFORMANCE CHARACTERISTICS
Figure 8. Design Example (5V, 2A 350kHz Step-Down Converter)
3864f
21
LTC3864
APPLICATIONS INFORMATION
resulting junction temperature for the MOSFET can be
A soft-start time of 8ms can be programmed through a
0.1µF capacitor on the SS pin:
calculatedatT =70°C,V
=55VandI
=2A:
A
IN(MAX)
OUT(MAX)
8ms•10µA
5V
55V
2
C
=
= 0.1µF
P
=
(2A) •1.5•105mΩ+
SS
PMOS
0.8V
0.9Ω
8V –3V
2Ω
3V
2
LoopcompensationcomponentsontheITHpinarechosen
based on load step transient behavior (as described under
OPTI-LOOPCompensation)andisoptimizedforstability.A
pull-up resistor is used on the RUN pin for FMEA compli-
ance (see Failure Modes and Effects Analysis).
(55V) •(2A /2)•100pF •
+
•350kHz
≈57mW+90mW =147mW
T = 70°C+147mW•60°C/W ≈80°C
J
The calculations can be repeated for V
= 5V:
IN(MIN)
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3864.
5V
5V
2
P
=
(2A) •1.5•105mΩ+
PMOS
0.9Ω
5.2V –3V 3V
2Ω
2
(5.2V) •100pF •
+
•350kHz
1. Multilayer boards with dedicated ground layers are
preferable for reduced noise and for heat sinking pur-
≈630mW+1mW ≈631mW
T = 70 C+631mW•60 C/ W ≈108 C
poses. Use wide rails and/or entire planes for V , V
IN OUT
°
°
°
J
and GND for good filtering and minimal copper loss. If
a ground layer is used, then it should be immediately
below (and/or above) the routing layer for the power
NextchooseanappropriateSchottkydiodethatwillhandle
the power requirements. The Diodes Inc. SBR3U100LP
train components which consist of C , sense resistor,
IN
Schottkydiodeisselected(V
=0.5V,θ =61°C/W)
F(2A,125°C)
JA
P-MOSFET, Schottky diode, inductor, and C . Flood
OUT
for this application. The power dissipation and junction
unused areas of all layers with copper for better heat
temperature at T = 70°C can be calculated as:
A
sinking.
5V
55V
2. Keep signal and power grounds separate except at the
point where they are shorted together. Short signal and
power ground together only at a single point with a
narrow PCB trace (or single via in a multilayer board).
All power train components should be referenced to
power ground and all small signal components (e.g.,
= 2A • 1–
P
•0.5V ≈909mW
DIODE
°
°
°
T = 70 C+909mW•61 C/W =125 C
J
These power dissipation calculations show that careful
attention to heat sinking will be necessary.
C
, R
, C etc.) should be referenced to signal
ITH1 FREQ SS
ground.
For the input capacitance, a combination of ceramic and
electrolytic capacitors are chosen to handle the maximum
3. Place C , sense resistor, P-MOSFET, inductor, and
IN
RMS current of 1A. C
will be selected based on the
OUT
primary C
capacitors close together in one compact
OUT
ESR that is required to satisfy the output voltage ripple
requirement.Forthisdesign,two47µFceramiccapacitors
are chosen to offer low ripple in both normal operation
and in Burst Mode operation.
area. The junction connecting the drain of P-MOSFET,
cathode of Schottky, and (+) terminal of inductor (this
junction is commonly referred to as switch or phase
node)shouldbecompactbutbelargeenoughtohandle
3864f
22
LTC3864
APPLICATIONS INFORMATION
theinductorcurrentswithoutlargecopperlosses.Place
8. Placesmallsignalcomponentsasclosetotheirrespec-
tive pins as possible. This minimizes the possibility of
PCB noise coupling into these pins. Give priority to
the sense resistor and source of P-channel MOSFET
as close as possible to the (+) plate of C capacitor(s)
IN
that provides the bulk of the AC current (these are
normally the ceramic capacitors), and connect the
anode of the Schottky diode as close as possible to
V , ITH, and R
pins. Use sufficient isolation when
FB
FREQ
routing a clock signal into PLLIN /MODE pin so that the
clock does not couple into sensitive small signal pins.
the (–) terminal of the same C capacitor(s). The high
IN
Failure Mode and Effects Analysis (FMEA)
dI/dt loop formed by C , the MOSFET, and the Schottky
IN
diode should have short leads and PCB trace lengths to
AFMEAstudyontheLTC3864hasbeenconductedthrough
adjacent pin opens and shorts. The device was tested
minimize high frequency EMI and voltage stress from
inductive ringing. The (–) terminal of the primary C
OUT
in a step-down application (Figure 8) from V = 12V to
IN
capacitor(s) which filter the bulk of the inductor ripple
V
= 5V with a current load of 1A on the output. One
OUT
current (these are normally the ceramic capacitors)
group of tests involved the application being monitored
while each pin was disconnected from the PC board
and left open while all other pins remained intact. The
other group of tests involved each pin being shorted to
its adjacent pins while all other pins were connected as
it would be normally in the application. The results are
shown in Table 2.
shouldalsobeconnectedclosetothe(–)terminalofC .
IN
4. Place pins 7 to 12 facing the power train components.
Keep high dV/dt signals on GATE and switch away from
sensitive small signal traces and components.
5. Place the sense resistor close to the (+) terminal of C
IN
and source of P-MOSFET. Use a Kelvin (4-wire) con-
nection across the sense resistor and route the traces
For FMEA compliance, the following design implementa-
tions are recommended:
together as a differential pair into the V and SENSE
IN
pins. An optional RC filter could be placed near the V
IN
• If the RUN pin is being pull-up to a voltage greater than
6V, then it is done so through a pull-up resistor (100k
to 1M) so that the PGOOD pin is not damaged in case
of a RUN to PGOOD short.
and SENSE pins to filter the current sense signal.
6. Place the resistive feedback divider R
as close as
FB1/2
possible to the V pin. The (+) terminal of the feedback
FB
divider should connect to the output regulation point
and the (–) terminal of feedback divider should connect
to signal ground.
• The gate of the external P-MOSFET be pulled through
a resistor (20k to 100k) to the input supply, V so that
IN
the P-MOSFET is guaranteed to turn off in case of a
GATE open.
7. Place the ceramic C
capacitor as close as possible
CAP
to V and CAP pins. This capacitor provides the gate
IN
discharging current for the power P-MOSFET.
3864f
23
LTC3864
APPLICATIONS INFORMATION
Table 2
RECOVERY
WHEN
FAULT IS
FAILURE MODE
None
V
I
I
VIN
f
REMOVED? BEHAVIOR
OUT
OUT
5V
1A
453mA
350kHz
N/A
Normal Operation.
Pin Open
Open Pin 1 (PLLIN/MODE)
Open Pin 2 (FREQ)
Open Pin 3 (GND)
Open Pin 4 (SS)
Open Pin 5 (VFB)
5V
5V
5V
5V
0V
1A
1A
1A
1A
0A
453mA
453mA
453mA
453mA
0.7mA
350kHz
535kHz
350kHz
350kHz
0kHz
OK
OK
OK
OK
OK
Pin already left open in normal application, so no difference.
Frequency jumps to default open value.
Exposed pad still provides GND connection to device.
External soft-start removed, but internal soft-start still available.
Controller stops switching. V internally self biases HI to prevent
FB
switching.
Open Pin 6 (ITH)
5V
5V
5V
5V
0V
1A
1A
1A
1A
0A
507mA
453mA
453mA
453mA
0.7mA
40kHz
350kHz
350kHz
350kHz
0kHz
OK
OK
OK
OK
OK
Output still regulating, but the switching is erratic. Loop not stable.
No PGOOD output, but controller regulates normally.
Controller does not start-up.
Open Pin 7 (PGOOD)
Open Pin 8 (RUN)
Open Pin 9 (CAP)
Open Pin 10 (SENSE)
More jitter during switching, but regulates normally.
SENSE internally prebiases to 0.6V below V . This prevents
IN
controller from switching.
Open Pin 11 (V )
5.4V
1A
0A
597mA
20kHz
OK
V able to bias internally through SENSE. Regulates with high V
IN OUT
IN
ripple.
Open Pin 12 (GATE)
Open Pin 13 (PGND)
Pins Shorted
0V
5V
0.7mA
453mA
0kHz
OK
OK
Gate does not drive external power FET, preventing output regulation.
Pin 3 (GND) still provides GND connection to device.
350kHz
Short Pins 1, 2
5V
5V
0V
1A
1A
0A
453mA
453mA
0.7mA
9mA
350kHz
0kHz
OK
OK
OK
OK
OK
OK
Burst Mode operation disabled, but runs normally as in pulse-skipping
mode.
(PLLIN/MODE and FREQ)
Short Pins 2, 3
(FREQ and GND)
FREQ already shorted to GND, so regulates normally.
Short Pins 3, 4
(GND and SS)
0kHz
SS short to GND prevents device from starting up.
Short Pins 4, 5
(SS and VFB)
1V(DC) 50mA
3V
Erratic
350kHz
350kHz
V
oscillates from 0V to 3V.
OUT
P-P
Short Pins 5, 6
(VFB and ITH)
3.15V 625mA 181mA
Controller loop does not regulate to proper output voltage.
Controller does not start-up.
Short Pins 7, 8
(PGOOD and RUN)
5V
1A
453mA
Short Pins 8, 9
(RUN and CAP)
5V
0V
5V
0V
1A
0A
1A
0A
453mA
181mA
453mA
29mA
350kHz
0kHz
OK
OK
OK
OK
Able to start-up and regulate normally.
Short Pins 9, 10
(CAP and SENSE)
CAP ~ V , which prevents turning on external P-MOSFET.
IN
Short Pins 10, 11
(SENSE and VIN)
50kHz
0kHz
Regulates with high V
ripple.
OUT
Short Pins 11, 12
(VIN and GATE)
Power MOSFET is always kept OFF, preventing regulation.
3864f
24
LTC3864
TYPICAL APPLICATIONS
24V to 60V Input, 24V/1A Output at 750kHz
Efficiency
100
90
80
70
60
50
40
30
V
IN
24V TO 60V
+
C
C
33µF
63V
CAP
IN1
C
IN2
0.1µF
2.2µF
Burst Mode
OPERATION
CAP
RUN
V
IN
C
VIN
R
SENSE
0.1µF
MODE/PLLN
50mΩ
SENSE
GATE
PULSE-SKIPPING
C
ITH1
SS
6.8nF
MP
L1
47µH
R
30.1k
ITH
V
24V
1A
*
LTC3864
ITH
OUT
V
V
= 48V
IN
OUT
C
100pF
ITH2
= 24V
R
10µF
D1
PGD2
768k
0.01
0.1
1
R
97.6k
FREQ
R
LOAD CURRENT (A)
FB2
FREQ
PGOOD
887k
3864 TA02b
SGND
V
FB
PGND
*V
R
R
FB1
30.1k
PGD1
200k
C
: NICHICON UPJ1J100MPD
3864 TA02a
IN1
D1: DIODES INC SBR3U100LP
L1: TOKO 1217AS-H-470M
MP: VISHAY/SILICONIX SI7113DN
FOLLOWS V WHEN 3.5V ≤ V ≤ 24V
OUT
IN
IN
3.5V to 48V Input, 1.8V/4A Output at 100kHz
Efficiency
80
70
60
50
40
30
V
IN
Burst Mode
OPERATION
3.5V TO 48V
+
C
C
33µF
63V
CAP
IN1
C
10µF
×2
IN2
0.1µF
CAP
RUN
V
IN
C
VIN
R
SENSE
C
SS
MODE/PLLN
0.1µF
15mΩ
0.1µF
PULSE-SKIPPING
SENSE
GATE
SS
C
ITH1
L1
10µH
10nF
MP
R
14k
ITH
V
1.8V
4A
LTC3864
OUT
ITH
V
V
= 12V
IN
OUT
C
100pF
= 1.8V
100µF
×2
ITH2
R
D1
PGD
100k
0.01
0.1
1
+
330µF
6.3V
R
LOAD CURRENT (A)
FB2
R
FREQ
24.3k
PGOOD
102k
3864 TA03b
FREQ
V
FB
SGND
R
FB1
PGND
80.6k
3864 TA03a
C
: SANYO 63ME33AX
IN1
D1: VISHAY V10P10
L1: WÜRTH 7447709100
MP: VISHAY/SILICONIX SI7461DP
3864f
25
LTC3864
TYPICAL APPLICATIONS
12V to 58V Input, 12V/2A Output at 535kHz
Efficiency
V
IN
90
80
70
60
50
12V TO 58V
+
C
C
33µF
63V
CAP
IN1
C
Burst Mode
OPERATION
IN2
0.1µF
4.7µF
CAP
RUN
V
IN
C
VIN
R
SENSE
0.1µF
MODE/PLLN
30mΩ
SENSE
GATE
PULSE-SKIPPING
SS
C
ITH1
L1
22µH
MP
3300pF
LTC3864
V
12V
2A
*
R
ITH
11.3k
OUT
ITH
V
V
= 48V
IN
OUT
C
100pF
R
10µF
×2
D1
ITH2
PGD2
= 12V
549k
R
FB2
0.01
0.1
LOAD CURRENT (A)
1
FREQ
PGOOD
845k
3864 TA04b
SGND
V
FB
PGND
R
R
FB1
60.4k
PGD1
402k
3864 TA04a
C
: SANYO 63ME33AX
IN1
D1: DIODES INC SBR3U100LP
L1: TOKO 1217AS-H-220M
MP: VISHAY/SILICONIX SI7465DP
*V
FOLLOWS V WHEN 3.5V ≤ V ≤ 12V
OUT IN IN
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev D)
0.40 0.10
4.00 0.10
(2 SIDES)
R = 0.115
TYP
7
12
0.70 0.05
R = 0.05
TYP
3.30 0.05
1.70 0.05
3.30 0.10
1.70 0.10
3.60 0.05
2.20 0.05
3.00 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PIN 1 NOTCH
R = 0.20 OR
PACKAGE
OUTLINE
0.35 × 45°
CHAMFER
(UE12/DE12) DFN 0806 REV D
6
1
0.25 0.05
0.25 0.05
2.50 REF
0.200 REF
0.75 0.05
0.50 BSC
0.50 BSC
2.50 REF
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3864f
26
LTC3864
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev F)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
(.112 ±.004)
1
6
0.35
REF
1.651 ±0.102
(.065 ±.004)
5.23
(.206)
MIN
1.651 ±0.102
(.065 ±.004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
DETAIL “B”
12
7
0.65
(.0256)
BSC
0.42 ±0.038
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
(.0165 ±.0015)
TYP
0.406 ±0.076
RECOMMENDED SOLDER PAD LAYOUT
(.016 ±.003)
12 11 10 9 8 7
REF
DETAIL “A”
0.254
(.010)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0° – 6° TYP
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
1
2 3 4 5 6
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE12) 0911 REV F
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
3864f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC3864
TYPICAL APPLICATION
3.5V to 38V Input, 3.3V/3A Output at 300kHz
Efficiency
V
IN
90
80
70
60
50
40
3.5V TO 60V
+
C
C
33µF
63V
Burst Mode
OPERATION
CAP
IN1
C
10µF
×2
IN2
0.1µF
CAP
RUN
V
IN
C
VIN
0.1µF
R
C
SENSE
V
3.3V
3A
SS
OUT
MODE/PLLN
SS
20mΩ
0.1µF
SENSE
GATE
47µF
×2
C
ITH1
PULSE-SKIPPING
10nF
L1
6.8µH
MP
R
20k
ITH
LTC3864
ITH
C
100pF
ITH2
V
V
= 12V
OUT
IN
R
D1
PGD
= 3.3V
100k
0.01
0.1
LOAD CURRENT (A)
1
R
FREQ
42.2k
R
FB2
PGOOD
FREQ
634k
3864 TA05b
V
FB
SGND
PGND
R
FB1
200k
3864 TA05a
C
: SANYO 63ME33AX
IN1
D1: VISHAY V15P45S
L1: WÜRTH 7447709100
MP: VISHAY/SILICONIX Si7611DN
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Phase-Lockable Fixed Frequency 50kHz to 900kHz 4V ≤ V ≤ 60V,
LTC3891
60V, Low I , Synchronous Step-Down DC/DC
Controller
Q
IN
0.8V ≤ V
≤ 24V, I = 50µA
OUT Q
LTC3890
LTC3824
LT3845A
60V, Low I , Dual 2-Phase Synchronous
Phase-Lockable Fixed Frequency 50kHz to 900kHz 4V ≤ V ≤ 60V,
IN
Q
Step-Down DC/DC Controller
0.8V ≤ V
≤ 24V, I = 50µA
OUT Q
60V, Low I , Step-Down DC/DC Controller, 100% Selectable Fixed Frequency 200kHz to 600kHz 4V≤ V ≤ 60V,
Q
IN
Duty Cycle
0.8V ≤ V
≤ V , I = 40µA, MSOP-10E
OUT IN Q
60V, Low I , Single Output Step-Down DC/DC
Synchronizable Fixed Frequency 100kHz to 600kHz 4V ≤ V ≤ 60V,
IN
Q
Controller
1.23V ≤ V
≤ 36V, I = 120µA, TSSOP-16
OUT Q
LTC3834/LTC3834-1
LTC3835/LTC3835-1
Low I , Single Output Synchronous Step-Down
Phase-Lockable Fixed Frequency 140kHz to 650kHz, 4V ≤ V ≤ 36V,
IN
Q
DC/DC Controller with 99% Duty Cycle
0.8V ≤ V
≤ 10V, I = 30µA/80µA
OUT Q
LTC3857/LTC3857-1
LTC3858/LTC3858-1
Low I , Dual Output 2-Phase Synchronous
Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 38V,
IN
Q
Step-Down DC/DC Controllers with 99% Duty
Cycle
0.8V ≤ V
≤ 24V, I = 50µA/170µA
OUT Q
LTC3859A
Low I , Triple Output Buck/Buck/Boost
All Outputs Remain in Regulation Through Cold Crank 2.5V ≤ V ≤ 38V,
IN
Q
Synchronous DC/DC Controller
V
Up to 24V, V
Up to 60V, I = 55µA
OUT(BUCKS)
OUT(BOOST) Q
3864f
LT 1012 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
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