LTC3869IGN-2#TRPBF_技术文档

LTC3869/LTC3869-2

Dual, 2-Phase

Synchronous Step-Down

DC/DC Controllers

FEATURES

DESCRIPTION

n

Dual, 180° Phased Controllers Reduce Required

The LTC^®3869 is a high performance dual synchronous

step-down switching regulator controller that drives all

N-channelsynchronouspowerMOSFETstages.Aconstant

frequency current mode architecture allows a phase-

lockable frequency of up to 780kHz. Power loss and noise

due to the ESR of the input capacitors are minimized by

operating the two controller output stages out-of-phase.

OPTI-LOOP^®compensation allows the transient response

to be optimized over a wide range of output capacitance

and ESR values. The LTC3869 features a precision 0.6V

reference and a power good output indicator. A wide 4V

to 38V input supply range encompasses most battery

chemistries. Independent TK/SS pins for each controller

ramp the output voltage during start-up. Current foldback

limitsMOSFETheatdissipationduringshort-circuitcondi-

tions. The MODE/PLLIN pin selects among Burst Mode^®

operation, pulse-skipping mode, or continuous inductor

current mode and allows the IC to be synchronized to an

external clock.

Input Capacitance and Power Supply Induced Noise

n

Accurate Multiphase Current Matching

n

R

SENSE

or DCR Current Sensing

n

0ꢀ.75 0ꢀꢁ6 ꢂutput 6oltage Accuracy

Phase-Lockable Fixed Frequency 270kHz to .80kHz

High Efﬁciency: Up to 95%

Dual N-channel MOSFET Synchronous Drive

Wide V Range: 4V to 38V (40V Max) Operation

IN

Wide V

Range: 0.6V to 12.5V Operation

OUT

Adjustable Soft-Start Current Ramping or Tracking

Foldback Output Current Limiting

Output Overvoltage Protection

Power Good Output Voltage Monitor

5V Low Dropout Regulator

Small 28-Lead QFN and Narrow SSOP Packages

APPLICATIONS

n

Server Systems

n

Telecom Systems

TheLTC3869ispincompatiblewithLTC3850andis available

inbothlowproﬁle28-leadQFNandnarrowSSOPpackages.

L, LT, LTC, LTM, Linear Technology, the Linear logo, OPTI-LOOP, Burst Mode and PolyPhase

n

Industrial and Medical Instruments

n

High Power Battery-Operated Devices

n

DC Power Distribution Systems

are registered trademarks and No R

is a trademark of Linear Technology Corporation. All

SENSE

other trademarks are the property of their respective owners. Protected by U.S. Patents including

5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6580258, 6498466, 6611131.

TYPICAL APPLICATION

High Efﬁciency Dual 76/3ꢀ36 Step-Down Converter

Efﬁciency and Power Loss

100

90

80

70

60

50

40

30

20

10

0

1300

1200

1100

1000

900

V

IN

V

= 12V, V

= 3.3V

= 5V

IN

OUT

7V TO

24V

+

22µF

1µF

4.7µF

V

PGOOD INTV

IN

CC

TG2

TG1

EFFICIENCY

0.1µF

BOOST1

SW1

BOOST2

SW2

3.2µH

2.2µH

800

LTC3869

BG1

BG2

700

f

IN

MODE/PLLIN

PGND

FREQ

500kHz

600

I

LIM

+

POWER LOSS

SENSE1

SENSE2

RUN2

SENSE2

500

RUN1

–

V

OUT1

5V

5A

SENSE1

400

OUT2

0.01

0.1

1

10

3.3V

V

FB1

TH1

FB2

TH2

5A

LOAD CURRENT (A)

147k

90.9k

I

3869 TA01b

470pF

15k

470pF

15k

TK/SS1 SGND TK/SS2

+

20k

56µF

122k

47µF

0.1µF

3869 TA01

3869f

1

LTC3869/LTC3869-2

ABSOLUTE MAXIMUM RATINGS

(Note 1)

Input Supply Voltage: V ........................... 40V to –0.3V

I

, I , V , V Voltages.............. INTV to –0.3V

TH1 TH2 FB1 FB2 CC

IN

Top Side Driver Voltages:

INTV Peak Output Current ................................100mA

CC

BOOST1, BOOST2...................................... 46V to –0.3V

Switch Voltage: SW1, SW2........................... 40V to –5V

Operating Junction Temperature Range

(Note 2)..................................................–40°C to 125°C

Junction Temperature (Note 3) ............................. 125°C

Storage Temperature Range...................–65°C to 150°C

Lead Temperature (Soldering, 10 sec)

INTV , RUN1, RUN2, PGOOD, EXTV ,

CC

BOOST1-SW1, BOOST2-SW2...................... 6V to –0.3V

+

–

+

–

SENSE1 , SENSE2 , SENSE1 ,

SENSE2 Voltages...................................... 13V to –0.3V

GN Package ...................................................... 300°C

MODE/PLLIN, I , TK/SS1, TK/SS2,

LIM

FREQ Voltages ...................................... INTV to –0.3V

CC

PIN CONFIGURATION

TOP VIEW

1

2

FREQ

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RUN1

+

MODE/PLLIN

SW1

SENSE1

–

3

SENSE1

28 27 26 25 24 23

–

4

TG1

V

FB1

SENSE1

TK/SS1

1

2

3

4

5

6

7

8

22

21

20

19

18

17

16

15

BOOST1

BG1

5

BOOST1

BG1

TK/SS1

6

I

TH1

I

V

TH1

IN

7

V

SGND

IN

V

INTV

CC

FB1

SGND

29

8

INTV

CC

I

V

BG2

TH2

FB2

9

BG2

I

TK/SS2

PGND

BOOST2

TG2

TH2

TK/SS2

10

11

12

13

14

PGND

BOOST2

TG2

V

FB2

–

SENSE2

+

9

10 11 12 13 14

UFD PACKAGE

SW2

RUN2

EXTV

PGOOD

CC

GN PACKAGE

28-LEAD PLASTIC SSOP

28-LEAD (4mm × 5mm) PLASTIC QFN

T

= 125°C, θ = 34°C/W,

JMAX

JA

T

= 125°C, θ = 80°C/W

JA

JMAX

EXPOSED PAD (PIN 29) IS SGND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC3869EUFD#PBF

LTC3869IUFD#PBF

LTC3869IGN-2#PBF

TAPE AND REEL

PART MARKING*

3869

PACKAGE DESCRIPTIꢂN

TEMPERATURE RANGE

–40°C to 125°C

LTC3869EUFD#TRPBF

LTC3869IUFD#TRPBF

LTC3869IGN-2#TRPBF

28-Lead (4mm × 5mm) Plastic QFN

28-Lead Narrow Plastic SSOP

3869

–40°C to 125°C

LTC3869GN-2

–40°C to 125°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

3869f

2

LTC3869/LTC3869-2

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

junction temperature range, otherwise speciﬁcations are at T_A= 27°C (Note 2)ꢀ 6_IN= 176, 6_RUN1,2= 76 unless otherwise notedꢀ

SYMBꢂL

PARAMETER

CꢂNDITIꢂNS

MIN

TYP

MAX UNITS

Main Control Loops

V

Input Voltage Range

Output Voltage Range

4

38

V

IN

0.6

12.5

OUT

FB1,2

l

Regulated Feedback Voltage

(Notes 2, 4)

I

Voltage = 1.2V, 0°C to 85°C

Voltage = 1.2V, –40°C to 125°C

0.5955

0.5940

0.600

0.6045

0.6060

V

TH1,2

I

Feedback Current

(Note 4)

= 4.0V to 38V (Note 4)

–15

–50

nA

FB1,2

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

0.002

0.01

%/V

REFLNREG

LOADREG

IN

(Note 4)

Measured in Servo Loop; ∆I Voltage = 1.2V to 0.7V

Measured in Servo Loop; ∆I Voltage = 1.2V to 1.6V

l

0.01

–0.01

0.1

–0.1

%

TH

g

m1,2

Transconductance Ampliﬁer g

I = 1.2V; Sink/Source 5µA; (Note 4)

TH1,2

2

mmho

m

I

Input DC Supply Current

Normal Mode

(Note 5)

IN

RUN1,2

Q

V

= 15V

3

30

mA

µA

Shutdown

= 0V

50

DF

Maximum Duty Factor

Undervoltage Lockout

UVLO Hysteresis

In Dropout

Ramping Down

94

95

3.2

0.6

0.66

1

%

V

MAX

l

UVLO

V

3.0

3.4

INTVCC

V

HYS

l

V

Feedback Overvoltage Lockout

Sense Pins Bias Current

Soft-Start Charge Current

RUN Pin On Threshold

Measured at V

0.64

0.68

2

V

OVL

FB1,2

I

(Each Channel); V

= 3.3V

µA

V

SENSE

SENSE1,2

V

= 0V

TK/SS1,2

1.0

1.1

1.25

1.22

80

1.5

1.35

TK/SS1,2

V

, V

Rising

RUN1,2

RUN1 RUN2

RUN Pin On Hysteresis

mV

RUN1,2(HYS)

SENSE(MAX)

l

Maximum Current Sense Threshold,

0°C to 85°C (Note 2)

V

= 0.5V, V

= 3.3V, I = 0V

25

45

68

30

50

75

35

55

82

mV

FB1,2

SENSE1,2

LIM

= 3.3V, I = Float

LIM

= 3.3V, I = INTV

LIM

CC

l

Maximum Current Sense Threshold,

–40°C to 125°C (Note 2)

V

= 0.5V, V

= 3.3V, I = 0V

23

43

68

40

30

50

75

50

37

57

82

60

mV

FB1,2

SENSE1,2

LIM

= 3.3V, I = Float

LIM

= 3.3V, I = INTV

LIM

= 3.3V, LTC3869IGN-2

V

Channel to Channel Current Sense

I

= Float

2

mV

MISMATCH

LIM

Mismatch Voltage of V

SENSE(MAX)

TG Transition Time:

Rise Time

(Note 8)

TG1, 2 t

C

= 3300pF

25

ns

r

f

LOAD

Fall Time

= 3300pF

BG Transition Time:

Rise Time

(Note 8)

LOAD

BG1, 2 t

C

= 3300pF

25

ns

r

f

Fall Time

TG/BG t

Top Gate Off to Bottom Gate On Delay C

Synchronous Switch-On Delay Time

= 3300pF Each Driver (Note 6)

30

90

ns

1D

LOAD

BG/TG t

Bottom Gate Off to Top Gate On Delay C

Top Switch-On Delay Time

= 3300pF Each Driver (Note 6)

2D

LOAD

t

Minimum On-Time

(Note 7)

ON(MIN)

3869f

3

LTC3869/LTC3869-2

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

junction temperature range, otherwise speciﬁcations are at T_A= 27°C (Note 2)ꢀ 6_IN= 176, 6_RUN1,2= 76 unless otherwise notedꢀ

SYMBꢂL

PARAMETER

CꢂNDITIꢂNS

MIN

TYP

MAX UNITS

INT6 Linear Regulator

CC

INTVCC

V

Internal V Voltage

6V < V < 38V

4.8

5

5.2

2

V

%

CC

IN

INT

INTV Load Regulation

I = 0mA to 20mA

CC

0.5

4.7

200

50

LDO

CC

l

EXTV Switchover Voltage

EXTV Ramping Positive

4.5

V

EXTVCC

LDOHYS

CC

EXTV Hysteresis

mV

CC

EXT

EXTV Voltage Drop

I

= 20mA, V = 5V

EXTVCC

100

LDO

CC

PGꢂꢂD ꢂutput

V

PGOOD Voltage Low

PGOOD Leakage Current

PGOOD Trip Level

= 2mA

= 5V

0.1

0.3

2

V

PGL

PGOOD

I

V

µA

PGOOD

V

with Respect to Set Output Voltage

PG

FB

V

FB

V

FB

Ramping Negative

Ramping Positive

–10

10

%

ꢂscillator and Phase-Locked Loop

f

Nominal Frequency

V

= 1.2V

= 0V

450

210

700

500

250

780

250

10

550

290

850

kHz

kΩ

µA

NOM

LOW

HIGH

FREQ

Lowest Frequency

Highest Frequency

≥ 2.4V

R

MODE/PLLIN Input Resistance

Frequency Setting Current

MODE/PLLIN

FREQ

I

9

11

ꢂn Chip Driver

TG R

BG R

TG Pull-Up R

TG High

TG Low

BG High

BG Low

2.6

1.5

2.4

1.1

Ω

UP

DS(ON)

TG Pull-Down R

DOWN

UP

DS(ON)

BG Pull-Up R

DS(ON)

BG Pull-Down R

DOWN

DS(ON)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: T is calculated from the ambient temperature T and power

J A

dissipation P according to the following formulas:

D

LTC3869UFD: T = T + (P • 34°C/W)

J

A

D

LTC3869GN-2: T = T + (P • 80°C/W)

J

A

D

Note 2: The LTC3869 is tested under pulsed load conditions such that

Note 4: The LTC3869 is tested in a feedback loop that servos V

to a

ITH1,2

T ≈ T . The LTC3869E is guaranteed to meet performance speciﬁcations

speciﬁed voltage and measures the resultant V

.

J

A

FB1,2

from 0°C to 85°C. Speciﬁcations over the –40°C to 125°C operating

junction temperature range are assured by design, characterization

and correlation with statistical process controls. The LTC3869I is

guaranteed to meet performance speciﬁcations over the full –40°C to

125°C operating junction temperature range. The maximum ambient

temperature consistent with these speciﬁcations is determined by speciﬁc

operating conditions in conjunction with board layout, the package thermal

impedence and other environmental factors.

Note 7: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note ꢁ: Delay times are measured using 50% levels.

Note .: The minimum on-time condition is speciﬁed for an inductor

peak-to-peak ripple current ≥40% of I

(see Minimum On-Time

MAX

Considerations in the Applications Information section).

Note 8: Guaranteed by design.

3869f

4

LTC3869/LTC3869-2

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 27°C, unless otherwise notedꢀ

Efﬁciency vs ꢂutput Current

and Mode

Efﬁciency vs ꢂutput Current

and Mode

Full Load Efﬁciency and Power

Loss vs Input 6oltage

90

85

80

75

5

4

3

2

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

1.8V

EFFICIENCY

Burst Mode

OPERATION

Burst Mode

OPERATION

1.2V

DCM

V

= 12V

V

= 12V

IN

OUT

IN

OUT

= 1.8V

= 1.2V

1.8V

POWER LOSS

CCM

1.2V

CIRCUIT OF FIGURE 16

10

INPUT VOLTAGE (V)

CIRCUIT OF FIGURE 16

10 100

CIRCUIT OF FIGURE 16

1 10 100

5

15

20

0.01

0.1

1

0.01

0.1

LOAD CURRENT (A)

3869 G03

3869 G01

3869 G02

Load Step

(Pulse-Skipping Mode)

Load Step

(Burst Mode ꢂperation)

Load Step

(Forced Continuous Mode)

I

LOAD

5A/DIV

300mA TO 5A

I

LOAD

5A/DIV

300mA TO 5A

I

L

I

L

5A/DIV

V

OUT

100mV/DIV

AC-COUPLED

3869 G05

3869 G06

3869 G04

50µs/DIV

V

= 12V

V

= 12V

V

= 12V

IN

OUT

IN

OUT

IN

OUT

= 1.8V

Inductor Current at Light Load

Prebiased ꢂutput at 26

Coincident Tracking

FORCED

CONTINUOUS

MODE

V

OUT

RUN

2V/DIV

5A/DIV

Burst Mode

OPERATION

5A/DIV

V

OUT1

V

FB

500mV/DIV

PULSE-

SKIPPING

MODE

V

OUT2

OUT1

OUT2

TK/SS

500mV/DIV

1V/DIV

5A/DIV

3869 G07

3869 G09

3869 G08

1µs/DIV

5ms/DIV

= 1.8V, 1.5Ω LOAD

= 1.2V, 1Ω LOAD

2ms/DIV

V

LOAD

= 12V

V

= 12V

IN

OUT

V

OUT1

OUT2

= 1.8V

= 3.3V

OUT

I

= 400mA

3869f

5

LTC3869/LTC3869-2

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 27°C, unless otherwise notedꢀ

Tracking Up and Down

with External Ramp

Quiescent Current without EXT6_CC

vs Temperature

INT6_CCLine Regulation

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

TK/SS1

TK/SS2

2V/DIV

V

OUT1

OUT2

V

OUT1

OUT2

500mA/DIV

3869 G10

10ms/DIV

= 1.8V, 1.5Ω LOAD

V

= 12V

IN

OUT1

OUT2

= 1.2V, 1Ω LOAD

–50 –25

0

25

50

75 100 125

0

10

20

30

40

TEMPERATURE (°C)

INPUT VOLTAGE (V)

3869 G11

3869 G12

Maximum Current Sense

Threshold vs Common Mode

6oltage

Current Sense Threshold

vs I_TH6oltage

Maximum Current Sense

Threshold vs Duty Cycle

80

60

80

70

60

50

80

70

60

50

40

30

20

10

0

I

= INTV

CC

LIM

I

= INTV

CC

LIM

I

= INTV

CC

LIM

I

= FLOAT

LIM

40

20

I

= FLOAT

I

= FLOAT

LIM

40

30

I

= GND

LIM

0

–20

–40

I

= GND

I

= GND

LIM

20

10

0

0.5

1

1.5

2

4

6

0

8

10

12

20

40

DUTY CYCLE (%)

80

0

100

60

V

(V)

V

COMMON MODE VOLTAGE (V)

ITH

SENSE

3869 G13

3869 G15

3869 G14

Maximum Current Sense 6oltage

vs Feedback 6oltage (Current

Foldback)

TK/SS Pull-Up Current

vs Temperature

1.6

1.4

1.2

1.0

90

I

= INTV

CC

LIM

80

70

60

50

40

30

20

10

0

I

= FLOAT

LIM

I

= GND

LIM

–50 –25

0

25

50

75 100 125

0.1

0.2

0.3

0

0.4

0.5

0.6

TEMPERATURE (°C)

FEEDBACK VOLTAGE (V)

3869 G17

3869 G16

3869f

6

LTC3869/LTC3869-2

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 27°C, unless otherwise notedꢀ

Shutdown (RUN) Threshold

vs Temperature

Regulated Feedback 6oltage

vs Temperature

ꢂscillator Frequency

vs Temperature

900

1.24

1.22

1.20

1.18

1.16

1.14

1.12

1.10

1.08

604

602

600

598

596

594

592

590

800

ON

V

= INTV

= 1.2V

FREQ

CC

700

600

500

400

300

200

100

0

V

FREQ

V

= GND

FREQ

OFF

50

TEMPERATURE (°C)

100 125

60

TEMPERATURE (°C)

110 125

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

–40 –15

10

35

85

–50 –25

0

25

75

3869 G18

3869 G19

3869 G20

Undervoltage Lockout Threshold

(INT6_CC) vs Temperature

ꢂscillator Frequency

vs Input 6oltage

Shutdown Current

vs Input 6oltage

4.1

3.9

3.7

3.5

3.3

3.1

2.9

2.7

2.5

520

510

500

490

480

60

50

40

30

20

10

0

RISING

FALLING

40

TEMPERATURE (°C)

80 100

–40 –20

0

20

60

5

10

15

20

25

30

35

40

5

10

15

20

25

30

35

40

INPUT VOLTAGE (V)

3869 G21

3869 G22

3869 G23

Shutdown Current

vs Temperature

Quiescent Current

vs Input 6oltage without EXT6_CC

45

40

35

30

25

20

15

10

5

3.8

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

1.8

0

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

5

10

15

20

25

30

35

40

INPUT VOLTAGE (V)

3869 G24

3869 G25

3869f

7

LTC3869/LTC3869-2

PIN FUNCTIONS ^(UFD/GN)

RUN1, RUN2 (Pin 2., Pin 10/Pin 1, Pin 13): Run Control

Inputs. A voltage above 1.2V on either pin turns on the IC.

However, forcing either of these pins below 1.2V causes

theICtoshutdownthecircuitryrequiredforthatparticular

channel. There are 1µA pull-up currents for these pins.

Once the RUN pin raises above 1.2V, an additional 4.5µA

pull-up current is added to the pin.

FREQ (Pin 2ꢁ/Pin 28): There is a precision 10µA current

ﬂowing out of this pin. Connect a resistor to ground set

the controllers’ operating frequency. Alternatively, this pin

can be driven with a DC voltage to vary the frequency of

the internal oscillator.

I

(Pin11/NA):CurrentComparatorSenseVoltageRange

LIM

Inputs. This pin is to be programmed to SGND, FLOAT

or INTV to set the maximum current sense threshold

6

, 6

(Pin 4, Pin 7/Pin 4, Pin 10): Error Ampliﬁer

CC

FB1 FB2

to three different levels for each comparator. The current

limit default value is set to be 50mV for LTC3869GN-2.

Feedback Inputs. These pins receive the remotely sensed

feedback voltages for each channel from external resistive

dividers across the outputs.

EXT6 (Pin 12/Pin 14): External Power Input to an Inter-

CC

nal Switch Connected to INTV . This switch closes and

CC

I

, I

(Pin 3, Pin ꢁ/Pin ꢁ, Pin 8): Current Control

TH1 TH2

supplies the IC power, bypassing the internal low dropout

Thresholds and Error Ampliﬁer Compensation Points.

Each associated channels’ current comparator tripping

regulator, whenever EXTV is higher than 4.7V. Do not

CC

exceed 6V on this pin.

threshold increases with its I control voltage.

TH

6 (Pin 20/Pin 22): Main Input Supply. Decouple this pin

IN

SGND (Pin 29/Pin .): Signal Ground. All small-signal

components and compensation components should con-

nect to this ground, which in turn connects to PGND at

one point. Pin 29 is the exposed pad, only available for

the UFD package. The exposed pad must be soldered to

PCB ground for electrical connection and rated thermal

performance.

to PGND with a capacitor (0.1µF to 1µF).

BꢂꢂST1,BꢂꢂST2(Pin22,Pin1ꢁ/Pin24,Pin18):Boosted

FloatingDriverSupplies.The(+)terminalofthebooststrap

capacitors connect to these pins. These pins swing from

a diode voltage drop below INTV up to V + INTV .

CC

IN

CC

TG1, TG2 (Pin 23, Pin 17/Pin 27, Pin 1.): Top Gate

TK/SS1, TK/SS2 (Pin 2, Pin ./Pin 7, Pin 9): Output Volt-

age Tracking and Soft-Start Inputs. When one particular

channel is conﬁgured to be the master of two channels,

a capacitor to ground at this pin sets the ramp rate for

the master channel’s output voltage. When the channel

Driver Outputs. These are the outputs of ﬂoating drivers

with a voltage swing equal to INTV superimposed on

CC

the switch nodes voltages.

SW1, SW2 (Pin 24, Pin 14/Pin 2ꢁ, Pin 1ꢁ): Switch Node

Connections to Inductors. Voltage swing at these pins

is from a Schottky diode (external) voltage drop below

is conﬁgured to be the slave of two channels, the V

FB

voltage of the master channel is reproduced by a resistor

divider and applied to this pin. Internal soft-start currents

of 1.2µA are charging these pins.

ground to V .

IN

+

SENSE1 , SENSE2 (Pin 28, Pin 9/Pin 2, Pin 12): Current

Sense Comparator Inputs. The (+) inputs to the current

comparators are normally connected to DCR sensing

networks or current sensing resistors.

MꢂDE/PLLIN (Pin 27/Pin 2.): Forced Continuous Mode,

Burst Mode Operation, or Pulse-Skipping Mode Selection

Pin and External Synchronization Input to Phase Detec-

tor Pin. Connect this pin to SGND to force both channels

–

SENSE1 , SENSE2 (Pin 1, Pin 8/Pin 3, Pin 11): Current

Sense Comparator Inputs. The (–) inputs to the current

comparators are connected to the outputs.

in continuous mode of operation. Connect to INTV to

CC

enable pulse-skipping mode of operation. Leave the pin

ﬂoating will enable Burst Mode operation. A clock on

the pin will force the controller into continuous mode of

operation and synchronize the internal oscillator with the

clock on this pin. The PLL compensation components are

integrated inside the IC.

PGND(Pin1./Pin19):PowerGroundPin.Connectthispin

closely to the sources of the bottom N-channel MOSFETs,

the (–) terminal of CV and the (–) terminal of C .

CC

IN

BG1, BG2 (Pin 21, Pin 18/Pin 23, Pin 20): Bottom Gate

Driver Outputs. These pins drive the gates of the bottom

N-channel MOSFETs between PGND and INTV .

CC

3869f

8

LTC3869/LTC3869-2

PIN FUNCTIONS ^(UFD/GN)

INT6 (Pin19/Pin21):Internal5VRegulatorOutput. The

PGꢂꢂD (Pin 13/Pin 17): Power Good Indicator Output.

Open drain logic out that is pulled to ground when either

channel output exceeds 10% regulation windows, after

the internal 20µs power bad mask timer expires.

CC

control circuits are powered from this voltage. Decouple

this pin to PGND with a minimum of 4.7µF low ESR tan-

talum or ceramic capacitor.

FUNCTIONAL BLOCK DIAGRAM

FREQ

MODE/PLLIN

EXTV

V

IN

CC

V

IN

4.7V

+

C

IN

–

+

10µA

F

0.6V

5V

REG

MODE/SYNC

DETECT

INTV

CC

–

+

INTV

CC

F

PLL-SYNC

BOOST

BURSTEN

S

R

OSC

C

B

TG

FCNT

ON

Q

I

M1

SW

L1

SWITCH

LOGIC

AND

ANTI-

SHOOT

THROUGH

V

OUT

3k

+

–

+

D

SENSE

B

I

CMP

REV

–

+

C

OUT

RUN

OV

BG

M2

C

VCC

SLOPE COMPENSATION

I

LIM

PGND

LTC3869UFD

ONLY

PGOOD

INTV

CC

UVLO

+

–

0.54V

R2

R1

SLOPE RECOVERY

ACTIVE CLAMP

1

UV

OV

V

FB

51k

I

THB

+

–

V

SLEEP

IN

0.66V

SS

RUN

+

–

+

SGND

0.6V

REF

EA

+ –

1.2µA

+

–

+

0.5V

1.2V

1µA

0.5V

3869 FD

C

C1

C

SS

I

RUN

TK/SS

TH

R

C

3869f

9

LTC3869/LTC3869-2

OPERATION

Main Control Loop

cycle to allow C to recharge. However, it is recommended

B

that a load be present or the IC operates at low frequency

The LTC3869 is a constant-frequency, current mode step-

down controller with two channels operating 180 degrees

out-of-phase. During normal operation, each top MOSFET

is turned on when the clock for that channel sets the RS

latch, and turned off when the main current comparator,

during the drop-out transition to ensure C is recharged.

B

Shutdown and Start-Up (RUN1, RUN2 and TK/SS1,

TK/SS2 Pins)

The two channels of the LTC3869 can be independently

shut down using the RUN1 and RUN2 pins. Pulling either

of these pins below 1.2V shuts down the main control

loopforthatcontroller. Pullingbothpinslowdisablesboth

I

, resets the RS latch. The peak inductor current at

CMP

which I

resets the RS latch is controlled by the voltage

CMP

TH

on the I pin, which is the output of each error ampli-

ﬁer EA. The V pin receives the voltage feedback signal,

FB

controllersandmostinternalcircuits,includingtheINTV

which is compared to the internal reference voltage by the

CC

regulator. Releasing either RUN pin allows an internal

1µA current to pull up the pin and enable that controller.

Alternatively, the RUN pin may be externally pulled up

or driven directly by logic. Be careful not to exceed the

Absolute Maximum Rating of 6V on this pin.

EA. When the load current increases, it causes a slight

decrease in V relative to the 0.6V reference, which in

FB

turn causes the I voltage to increase until the average

TH

inductor current matches the new load current. After the

top MOSFET has turned off, the bottom MOSFET is turned

on until either the inductor current starts to reverse, as

indicated by the reverse current comparator I , or the

beginning of the next cycle.

The start-up of each controller’s output voltage V

is

OUT

REV

controlled by the voltage on the TK/SS1 and TK/SS2 pins.

When the voltage on the TK/SS pin is less than the 0.6V

internal reference, the LTC3869 regulates the V voltage

FB

INT6 /EXT6 Power

CC

totheTK/SSpinvoltageinsteadofthe0.6Vreference. This

allows the TK/SS pin to be used to program the soft-start

periodbyconnectinganexternalcapacitorfromtheTK/SS

pin to SGND. An internal 1.2µA pull-up current charges

this capacitor, creating a voltage ramp on the TK/SS pin.

As the TK/SS voltage rises linearly from 0V to 0.6V (and

Power for the top and bottom MOSFET drivers and most

otherinternalcircuitryisderivedfromtheINTV pin.When

CC

the EXTV pin is left open or tied to a voltage less than

CC

4.7V,aninternal5VlinearregulatorsuppliesINTV power

CC

from V . If EXTV is taken above 4.7V, the 5V regulator is

IN

CC

turned off and an internal switch is turned on connecting

beyond),theoutputvoltageV risessmoothlyfromzero

OUT

EXTV . Using the EXTV pin allows the INTV power

to its ﬁnal value. Alternatively the TK/SS pin can be used

CC

to be derived from a high efﬁciency external source such

to cause the start-up of V

to “track” that of another

OUT

as one of the LTC3869 switching regulator outputs.

supply. Typically, this requires connecting to the TK/SS

pin an external resistor divider from the other supply to

ground (see the Applications Information section). When

the corresponding RUN pin is pulled low to disable a

Each top MOSFET driver is biased from the ﬂoating boot-

strap capacitor C , which normally recharges during each

B

off cycle through an external diode when the top MOSFET

controller, or when INTV drops below its undervoltage

CC

turns off. If the input voltage V decreases to a voltage

IN

lockout threshold of 3.2V, the TK/SS pin is pulled low by

an internal MOSFET. When in undervoltage lockout, both

controllers are disabled and the external MOSFETs are

held off.

close to V , the loop may enter dropout and attempt to

OUT

turn on the top MOSFET continuously. The dropout detec-

tor detects this and forces the top MOSFET off for about

one-twelfth of the clock period plus 100ns every third

3869f

10

LTC3869/LTC3869-2

OPERATION

Light Load Current ꢂperation (Burst Mode ꢂperation,

remaintrippedforseveralcyclesandforcetheexternaltop

MOSFET to stay off for the same number of cycles (i.e.,

skipping pulses). The inductor current is not allowed to

reverse (discontinuous operation). This mode, like forced

continuousoperation, exhibitslowoutputrippleaswellas

low audio noise and reduced RF interference as compared

to Burst Mode operation. It provides higher low current

efﬁciency than forced continuous mode, but not nearly as

high as Burst Mode operation.

Pulse-Skipping, or Continuous Conduction)

The LTC3869 can be enabled to enter high efﬁciency Burst

Modeoperation,constant-frequencypulse-skippingmode,

or forced continuous conduction mode. To select forced

continuous operation, tie the MODE/PLLIN pin to a DC

voltage below 0.6V (e.g., SGND). To select pulse-skipping

mode of operation, tie the MODE/PLLIN pin to INTV . To

CC

select Burst Mode operation, ﬂoat the MODE/PLLIN pin.

When a controller is enabled for Burst Mode operation,

the peak current in the inductor is set to approximately

one-third of the maximum sense voltage even though the

Single ꢂutput Multiphase ꢂperation

The LTC3869 can be used for single output multiphase

converters by making these connections

voltageontheI pinindicatesalowervalue.Iftheaverage

TH

inductor current is higher than the load current, the error

• Tie all of the I pins together.

TH

ampliﬁer EA will decrease the voltage on the I pin. When

TH

• Tie all of the V pins together.

FB

the I voltage drops below 0.5V, the internal sleep signal

TH

goes high (enabling sleep mode) and the top MOSFET is

turned off immediately, but the bottom MOSFET is turned

off when the inductor current reaches zero.

• Tie all of the TK/SS pins together.

• Tie all of the RUN pins together.

LTC3869 has excellent current matching performance

between channels to ensure that there are equal thermal

stress for both channels.

In sleep mode, the load current is supplied by the output

capacitor. Astheoutputvoltagedecreases, theEA’s output

begins to rise. When the output voltage drops enough, the

sleep signal goes low, and the controller resumes normal

operation by turning on the top external MOSFET on the

next cycle of the internal oscillator. When a controller is

enabled for Burst Mode operation, the inductor current is

not allowed to reverse. The reverse current comparator

Frequency Selection and Phase-Locked Loop

(FREQ and MꢂDE/PLLIN Pins)

Theselectionofswitchingfrequencyisatrade-offbetween

efﬁciency and component size. Low frequency operation

increasesefﬁciencybyreducingMOSFETswitchinglosses,

butrequireslargerinductanceand/orcapacitancetomain-

tain low output ripple voltage. The switching frequency of

theLTC3869controllercanbeselectedusingtheFREQpin.

If the MODE/PLLIN pin is not being driven by an external

clock source, the FREQ pin can be used to program the

controller’s operating frequency from 250kHz to 780kHz.

(I ) turns off the bottom external MOSFET just before

REV

the inductor current reaches zero, preventing it from

reversing and going negative. Thus, the controller oper-

ates in discontinuous operation. In forced continuous

operation, the inductor current is allowed to reverse at

light loads or under large transient conditions. The peak

inductor current is determined by the voltage on the I

TH

pin. In this mode, the efﬁciency at light loads is lower than

in Burst Mode operation. However, continuous mode has

theadvantagesofloweroutputrippleandlessinterference

with audio circuitry.

There is a precision 10µA current ﬂowing out of the FREQ

pin, so the user can program the controller’s switching

frequency with a single resistor to SGND. A curve is

provided later in the application section showing the

relationship between the voltage on the FREQ pin and

switching frequency.

When the MODE/PLLIN pin is connected to INTV , the

CC

LTC3869 operates in PWM pulse-skipping mode at light

loads.Atverylight loads,thecurrentcomparatorI

may

CMP

3869f

11

LTC3869/LTC3869-2

OPERATION

A phase-locked loop (PLL) is integrated on the LTC3869

to synchronize the internal oscillator to an external clock

source that is connected to the MODE/PLLIN pin. The

controller is operating in forced continuous mode when

it is synchronized.

1.2V or when the LTC3869 is in the soft-start or tracking

phase. The PGOOD pin will ﬂag power good immediately

when both V pins are within the 10% of the reference

FB

window. However, there is an internal 20µs power bad

mask when V goes out the 10% window. The PGOOD

FB

pin is allowed to be pulled up by an external resistor to a

ThePLLloopﬁlternetworkisintegratedinsidetheLTC3869.

The phase-locked loop is capable of locking any frequency

withintherangeof250kHzto770kHz.Thefrequencysetting

resistorshouldalwaysbepresenttosetthecontroller’sinitial

switching frequency before locking to the external clock.

source of up to 6V.

ꢂutput ꢂvervoltage Protection

An overvoltage comparator, OV, guards against transient

overshoots (>10%) as well as other more serious condi-

tions that may overvoltage the output. In such cases, the

topMOSFETisturnedoffandthebottomMOSFETisturned

on until the overvoltage condition is cleared.

Power Good (PGꢂꢂD Pin)

When V pin voltage is not within 10% of the 0.6V

FB

reference voltage, the PGOOD pin is pulled low. The

PGOOD pin is also pulled low when the RUN pin is below

3869f

12

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

TheTypicalApplicationontheﬁrstpageisabasicLTC3869

applicationcircuit.LTC3869canbeconﬁguredtouseeither

DCR (inductor resistance) sensing or low value resistor

sensing. The choice between the two current sensing

schemes is largely a design trade-off between cost, power

consumption, and accuracy. DCR sensing is becoming

popular because it saves expensive current sensing resis-

tors and is more power efﬁcient, especially in high current

applications. However, current sensing resistors provide

the most accurate current limits for the controller. Other

externalcomponentselectionisdrivenbytheloadrequire-

Filter components mutual to the sense lines should be

placed close to the LTC3869, and the sense lines should

run close together to a Kelvin connection underneath the

current sense element (shown in Figure 1). Sensing cur-

rent elsewhere can effectively add parasitic inductance

and capacitance to the current sense element, degrading

the information at the sense terminals and making the

programmed current limit unpredictable. If DCR sensing

is used (Figure 2b), sense resistor R1 should be placed

closetotheswitchingnode,topreventnoisefromcoupling

intosensitivesmall-signalnodes. ThecapacitorC1should

be placed close to the IC pins.

ment, and begins with the selection of R

(if R

is

SENSE

used)andinductorvalue.Next,thepowerMOSFETsarese-

lected. Finally, input and output capacitors are selected.

TO SENSE FILTER,

NEXT TO THE CONTROLLER

Current Limit Programming

C

OUT

The I pin is a tri-level logic input which sets the maxi-

LIM

R

3869 F01

SENSE

mum current limit of the controller. When I

is either

LIM

grounded, ﬂoated or tied to INTV , the typical value for

CC

Figure 1ꢀ Sense Lines Placement with Sense Resistor

Low 6alue Resistors Current Sensing

themaximumcurrentsensethresholdwillbe30mV,50mV

or 75mV, respectively.

A typical sensing circuit using a discrete resistor is shown

Which setting should be used? For the best current limit

accuracy, use the 75mV setting. The 30mV setting will

allow for the use of very low DCR inductors or sense

resistors, but at the expense of current limit accuracy.

The 50mV setting is a good balance between the two. For

single output dual phase applications, use the 50mV or

75mV setting for optimal current sharing.

in Figure 2a. R

output current.

is chosen based on the required

SENSE

The current comparator has a maximum threshold

determined by the I setting. The input

V

SENSE(MAX)

LIM

common mode range of the current comparator is 0V to

12.5V. The current comparator threshold sets the peak of

the inductor current, yielding a maximum average output

+

–

SENSE and SENSE Pins

current I

equal to the peak value less half the peak-to-

MAX

+

–

The SENSE and SENSE pins are the inputs to the current

comparators. The common mode input voltage range of

the current comparators is 0V to 12.5V. Both SENSE pins

are high impedance inputs with small base currents of

less than 1µA. When the SENSE pins ramp up from 0V to

1.4V, the small base currents ﬂow out of the SENSE pins.

When the SENSE pins ramp down from 12.5V to 1.1V, the

small base currents ﬂow into the SENSE pins. The high

impedance inputs to the current comparators allow ac-

curate DCR sensing. However, care must be taken not to

ﬂoatthesepinsduringnormaloperation.TheLTC3869GN-2

defaults to 50mV current limit value.

peak ripple current, ∆I . To calculate the sense resistor

L

value, use the equation:

V_SENSE(MAX)

R_SENSE

=

ΔI_L

I_MAX

+

2

BecauseofpossiblePCBnoiseinthecurrentsensingloop,

theACcurrentsensingrippleof∆V =∆I • R also

SENSE

L

SENSE

needs to be checked in the design to get a good signal-to-

noiseratio. Ingeneral, forareasonablygoodPCBlayout, a

10mV ∆V

voltage is recommended as a conservative

SENSE

number to start with, either for R

or DCR sensing

SENSE

applications, for duty cycles less than 40%.

3869f

13

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

For previous generation current mode controllers, the

maximum sense voltage was high enough (e.g., 75mV for

theLTC1628/LTC3728family)thatthevoltagedropacross

the parasitic inductance of the sense resistor represented

a relatively small error. For today’s highest current density

solutions, however, the value of the sense resistor can

be less than 1mΩ and the peak sense voltage can be as

low as 20mV. In addition, inductor ripple currents greater

than 50% with operation up to 1MHz are becoming more

common. Under these conditions the voltage drop across

the sense resistor’s parasitic inductance is no longer neg-

ligible. A typical sensing circuit using a discrete resistor is

showninFigure2a. Inpreviousgenerationsofcontrollers,

a small RC ﬁlter placed near the IC was commonly used to

reducetheeffectsofcapacitiveandinductivenoisecoupled

inthe sense traces on the PCB. A typical ﬁlter consists of

two series 10Ω resistors connected to a parallel 1000pF

capacitor, resulting in a time constant of 20ns.

This same RC ﬁlter, with minor modiﬁcations, can be used

to extract the resistive component of the current sense

signalinthepresenceofparasiticinductance.Forexample,

Figure 3 illustrates the voltage waveform across a 2mΩ

sense resistor with a 2010 footprint for the 1.2V/15A

converter operating at 100% load. The waveform is the

superposition of a purely resistive component and a

purely inductive component. It was measured using two

scope probes and waveform math to obtain a differential

measurement. Based on additional measurements of the

inductor ripple current and the on-time and off-time of

the top switch, the value of the parasitic inductance was

determined to be 0.5nH using the equation:

V

t_ON• t_OFF

ESL(STEP)

ESL =

ΔI_L

t

_ON+ t_OFF

V

IN

V

IN

INTV

CC

BOOST

TG

SENSE RESISTOR

PLUS PARASITIC

INDUCTANCE

INDUCTOR

DCR

BOOST

TG

V

L

SW

OUT

V

R

S

ESL

SW

OUT

LTC3869

BG

C • 2 ≤ ESL/R

F

RF

S

PGND

POLE-ZERO

PGND

R1**

R2

CANCELLATION

+

R

F

SENSE

+

SENSE

C1*

||

C

F

–

SENSE

SGND

3869 F02a

L

R2

R1 + R2

+

FILTER COMPONENTS

PLACED NEAR SENSE PINS

R

= DCR

*PLACE C1 NEAR SENSE , R1 R2 × C1 =

3869 F02b

SENSE(EQ)

DCR

–

SENSE PINS

**PLACE R1 NEXT TO

INDUCTOR

(2a) Using a Resistor to Sense Current

(2b) Using the Inductor DCR to Sense Current

Figure 2ꢀ Two Different Methods of Sensing Current

3869f

14

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

The ﬁlter components need to be placed close to the IC.

The positive and negative sense traces need to be routed

as a differential pair and Kelvin connected to the sense

resistor.

Inductor DCR Sensing

V

ESL(STEP)

For applications requiring the highest possible efﬁciency

at high load currents, the LTC3869 is capable of sensing

the voltage drop across the inductor DCR, as shown in

Figure 2b. The DCR of the inductor represents the small

amount of DC winding resistance of the copper, which

can be less than 1mΩ for today’s low value, high current

inductors. In a high current application requiring such an

inductor, conduction loss through a sense resistor would

costseveralpointsofefﬁciencycomparedtoDCRsensing.

V

SENSE

20mV/DIV

3869 F03

500ns/DIV

Figure 3ꢀ 6oltage Waveform Measured

Directly Across the Sense Resistor

If the external R1||R2 • C1 time constant is chosen to be

exactly equal to the L/DCR time constant, the voltage drop

across the external capacitor is equal to the drop across

theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe

voltage across the sense terminals for applications where

the DCR is greater than the target sense resistor value.

To properly dimension the external ﬁlter components, the

DCR of the inductor must be known. It can be measured

using a good RLC meter, but the DCR tolerance is not

always the same and varies with temperature; consult

the manufacturers’ data sheets for detailed information.

V

SENSE

20mV/DIV

3869 F04

500ns/DIV

Figure 4ꢀ 6oltage Waveform Measured After the

Sense Resistor Filterꢀ C_F= 1000pF, R_F= 100Ω

Using the inductor ripple current value from the Inductor

Value Calculation section, the target sense resistor value is:

If the RC time constant is chosen to be close to the

parasitic inductance divided by the sense resistor (L/R),

the resulting waveform looks resistive again, as shown

in Figure 4. For applications using low maximum sense

voltages, check the sense resistor manufacturer’s data

sheet for information about parasitic inductance. In the

absence of data, measure the voltage drop directly across

the sense resistor to extract the magnitude of the ESL

step and use the equation above to determine the ESL.

However,donotover-ﬁlter.KeeptheRCtimeconstantless

than or equal to the inductor time constant to maintain a

V_SENSE(MAX)

R_SENSE(EQUIV)

=

ΔI_L

I_MAX

+

2

To ensure that the application will deliver full load current

over the full operating temperature range, choose the

minimumvaluefortheMaximumCurrentSenseThreshold

(V

)intheElectricalCharacteristicstable(23mV,

SENSE(MAX)

43mV, or 68mV, depending on the state of the I pin).

LIM

high enough ripple voltage on V

.

RSENSE

Next, determine the DCR of the inductor. Where provided,

use the manufacturer’s maximum value, usually given at

20°C. Increase this value to account for the temperature

coefﬁcient of resistance, which is approximately 0.4%/°C.

The above generally applies to high density/high current

applications where I >10A and low values of inductors

MAX

are used. For applications where I

and C to 1000pF. This will provide a good starting point.

<10A, set R to 10Ω

MAX

F

A conservative value for T

is 100°C.

F

L(MAX)

3869f

15

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

To scale the maximum inductor DCR to the desired sense

resistor value, use the divider ratio:

Slope Compensation and Inductor Peak Current

Slope compensation provides stability in constant-

frequencyarchitecturesbypreventingsubharmonicoscil-

lations at high duty cycles. It is accomplished internally by

addingacompensatingramptotheinductorcurrentsignal

at duty cycles in excess of 40%. Normally, this results in

a reduction of maximum inductor peak current for duty

cycles >40%. However, the LTC3869 uses a scheme that

counteracts this compensating ramp, which allows the

maximum inductor peak current to remain unaffected

throughout all duty cycles.

R_SENSE(EQUIV)

R_D=

DCR_(MAX)at T

L(MAX)

C1 is usually selected to be in the range of 0.047µF to

0.47µF. This forces R1||R2 to around 2kΩ, reducing error

that might have been caused by the SENSE pins’ 1µA

current. T

is the maximum inductor temperature.

L(MAX)

The equivalent resistance R1||R2 is scaled to the room

temperature inductance and maximum DCR:

Inductor 6alue Calculation

L

R1||R2 =

Given the desired input and output voltages, the inductor

value and operating frequency f

inductor’s peak-to-peak ripple current:

(DCR at 20°C) • C1

directly determine the

OSC

The sense resistor values are:

R1||R2

R_D

R1• R_D

1−R_D

⎛

⎞

⎟

⎠

V_OUTV – V

IN

OUT

R1=

; R2 =

I_RIPPLE

=

⎜

⎝

V

f_OSC•L

IN

The maximum power loss in R1 is related to duty cycle,

and will occur in continuous mode at the maximum input

voltage:

Lower ripple current reduces core losses in the inductor,

ESR losses in the output capacitors, and output voltage

ripple. Thus, highest efﬁciency operation is obtained at

low frequency with a small ripple current. Achieving this,

however, requires a large inductor.

V

_IN(MAX)− V_OUT• V

(

)

OUT

P_LOSSR1=

R1

A reasonable starting point is to choose a ripple current

that is about 40% of I

for a duty cycle less than

OUT(MAX)

Ensure that R1 has a power rating higher than this value.

If high efﬁciency is necessary at light loads, consider this

power loss when deciding whether to use DCR sensing or

sense resistors. Light load power loss can be modestly

higher with a DCR network than with a sense resistor, due

totheextraswitchinglossesincurredthroughR1.However,

DCR sensing eliminates a sense resistor, reduces conduc-

tion losses and provides higher efﬁciency at heavy loads.

Peak efﬁciency is about the same with either method.

40%. Note that the largest ripple current occurs at the

highestinputvoltage.Toguaranteethatripplecurrentdoes

not exceed a speciﬁed maximum, the inductor should be

chosen according to:

V – V

f_OSC•I_RIPPLE

V_OUT

IN

OUT

L ≥

•

V

IN

For duty cycles greater than 40%, the 10mV current

sense ripple voltage requirement is relaxed because the

slope compensation signal aids the signal-to-noise ratio

and because a lower limit is placed on the inductor value

to avoid subharmonic oscillations. To ensure stability for

To maintain a good signal to noise ratio for the current

sense signal, use a minimum ∆V

of 10mV for duty

SENSE

cycles less than 40%. For a DCR sensing application, the

actual ripple voltage will be determined by the equation:

V − V

R1• C1 V • f

V_OUT

IN

OUT

ΔV_SENSE

=

IN

OSC

3869f

16

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

duty cycles up to the maximum of 95%, use the following

equation to ﬁnd the minimum inductance.

Selection criteria for the power MOSFETs include the

on-resistance R

, Miller capacitance C

, input

DS(ON)

MILLER

voltage and maximum output current. Miller capacitance,

V_OUT

f_SW•I_LOAD(MAX)

L_MIN

>

• 1.4

C

, can be approximated from the gate charge curve

MILLER

usually provided on the MOSFET manufacturers’ data

sheet. C

is equal to the increase in gate charge

MILLER

where

along the horizontal axis while the curve is approximately

ﬂat divided by the speciﬁed change in V . This result is

L

MIN

is in units of µH

DS

then multiplied by the ratio of the application applied V

DS

f

SW

is in units of MHz

to the gate charge curve speciﬁed V . When the IC is

DS

operating in continuous mode the duty cycles for the top

and bottom MOSFETs are given by:

Inductor Core Selection

Once the inductance value is determined, the type of in-

ductor must be selected. Core loss is independent of core

size for a ﬁxed inductor value, but it is very dependent

on inductance selected. As inductance increases, core

losses go down. Unfortunately, increased inductance

requires more turns of wire and therefore copper losses

will increase.

V_OUT

Main SwitchDuty Cycle =

V

IN

V – V

IN

OUT

Synchronous SwitchDuty Cycle =

V

IN

The MOSFET power dissipations at maximum output

current are given by:

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

V

2

OUT

P

=

I

(

1+ d R

+

) (

)

MAIN

MAX

DS(ON)

V

IN

⎛

⎞

I

2

MAX

V

R

C

•

(

)

⎜

⎟

(

)

(

)

IN

DR

MILLER

⎝

⎠

2

⎡

⎢

⎣

⎤

1

⎥

+

• f

OSC

V

– V

V

⎥

TH(MIN)

TH(MIN) ⎦

INTVCC

Power MꢂSFET and Schottky Diode

(ꢂptional) Selection

V – V

2

IN

OUT

P

=

I

(

1+ d R

DS(ON)

) (

)

MAX

SYNC

Two external power MOSFETs must be selected for each

controller in the LTC3869: one N-channel MOSFET for the

top (main) switch, and one N-channel MOSFET for the

bottom (synchronous) switch.

V

IN

where d is the temperature dependency of R

and

DS(ON)

R

(approximately 2Ω) is the effective driver resistance

DR

at the MOSFET’s Miller threshold voltage. V

is the

TH(MIN)

The peak-to-peak drive levels are set by the INTV

CC

typical MOSFET minimum threshold voltage.

voltage. This voltage is typically 5V during start-up

2

(see EXTV Pin Connection). Consequently, logic-level

BothMOSFETshaveI RlosseswhilethetopsideN-channel

equation includes an additional term for transition losses,

CC

threshold MOSFETs must be used in most applications.

The only exception is if low input voltage is expected (V

which are highest at high input voltages. For V < 20V

IN

GS(TH)

IN

< 5V); then, sub-logic level threshold MOSFETs (V

the high current efﬁciency generally improves with larger

< 3V) should be used. Pay close attention to the BV

MOSFETs, while for V > 20V the transition losses rapidly

DSS

IN

speciﬁcation for the MOSFETs as well; most of the logic

increasetothepointthattheuseofahigherR

device

DS(ON)

level MOSFETs are limited to 30V or less.

with lower C

actually provides higher efﬁciency.

MILLER

3869f

17

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

ThesynchronousMOSFETlossesaregreatestathighinput

voltage when the top switch duty factor is low or during

a short-circuit when the synchronous switch is on close

to 100% of the period.

the controller but by controlling the output ramp voltage

according to the ramp rate on the TK/SS pin. Current

foldback is disabled during this phase to ensure smooth

soft-start or tracking. The soft-start or tracking range is

deﬁned to be the voltage range from 0V to 0.6V on the

TK/SS pin. The total soft-start time can be calculated as:

The term (1 + d) is generally given for a MOSFET in the

form of a normalized R

vs Temperature curve, but

DS(ON)

d = 0.005/°C can be used as an approximation for low

C_SS

t_SOFTSTART= 0.6 •

voltage MOSFETs.

1.2µA

TheoptionalSchottkydiodesconductduringthedeadtime

betweentheconductionofthetwopowerMOSFETs.These

preventthebodydiodesofthebottomMOSFETsfromturn-

ing on, storing charge during the dead time and requiring

a reverse recovery period that could cost as much as 3%

Regardless of the mode selected by the MODE/PLLIN pin,

the regulator will always start in pulse-skipping mode

up to TK/SS = 0.5V. Between TK/SS = 0.5V and 0.54V, it

will operate in forced continuous mode and revert to the

selected mode once TK/SS > 0.54V. The output ripple

is minimized during the 40mV forced continuous mode

window ensuring a clean PGOOD signal.

in efﬁciency at high V . A 1A to 3A Schottky is generally

IN

a good compromise for both regions of operation due to

the relatively small average current. Larger diodes result

in additional transition losses due to their larger junction

capacitance. A Schottky diode in parallel with the bottom

FET may also provide a modest improvement in Burst

Mode efﬁciency.

When the channel is conﬁgured to track another supply,

the feedback voltage of the other supply is duplicated by

a resistor divider and applied to the TK/SS pin. Therefore,

the voltage ramp rate on this pin is determined by the

ramp rate of the other supply’s voltage. Note that the small

soft-start capacitor charging current is always ﬂowing,

producingasmalloffseterror.Tominimizethiserror,select

the tracking resistive divider value to be small enough to

make this error negligible.

Soft-Start and Tracking

The LTC3869 has the ability to either soft-start by itself

with a capacitor or track the output of another channel or

externalsupply.Whenoneparticularchannelisconﬁgured

to soft-start by itself, a capacitor should be connected to

its TK/SS pin. This channel is in the shutdown state if its

RUN pin voltage is below 1.2V. Its TK/SS pin is actively

pulled to ground in this shutdown state.

In order to track down another channel or supply after

the soft-start phase expires, the LTC3869 is forced into

continuous mode of operation as soon as V is below the

FB

undervoltage threshold of 0.54V regardless of the setting

on the MODE/PLLIN pin. However, the LTC3869 should

always be set in force continuous mode tracking down

when there is no load. After TK/SS drops below 0.1V, its

channel will operate in discontinuous mode.

Once the RUN pin voltage is above 1.2V, the channel pow-

ers up. A soft-start current of 1.2µA then starts to charge

its soft-start capacitor. Note that soft-start or tracking is

achieved not by limiting the maximum output current of

3869f

18

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

ꢂutput 6oltage Tracking

To implement the ratiometric tracking in Figure 6b, the

ratio of the V

divider should be exactly the same as

OUT2

The LTC3869 allows the user to program how its output

ramps up and down by means of the TK/SS pins. Through

thesepins, theoutputcanbesetuptoeithercoincidentally

or ratiometrically track another supply’s output, as shown

the master channel’s feedback divider shown in Figure 6b.

By selecting different resistors, the LTC3869 can achieve

different modes of tracking including the two in Figure 5.

So which mode should be programmed? While either

mode in Figure 5 satisﬁes most practical applications,

some tradeoffs exist. The ratiometric mode saves a pair

of resistors, but the coincident mode offers better output

regulation.

in Figure 5. In the following discussions, V

refers to

OUT1

the LTC3869’s output 1 as a master channel and V

OUT2

refers to the LTC3869’s output 2 as a slave channel. In

practice, though, either phase can be used as the master.

To implement the coincident tracking in Figure 5a, con-

nect an additional resistive divider to V

and connect

OUT1

When the master channel’s output experiences dynamic

excursion (under load transient, for example), the slave

channel output will be affected as well. For better output

regulation, use the coincident tracking mode instead of

ratiometric.

its midpoint to the TK/SS pin of the slave channel. The

ratio of this divider should be the same as that of the

slave channel’s feedback divider shown in Figure 6a. In

this tracking mode, V

must be set higher than V

.

OUT1

OUT2

V

OUT1

V

OUT1

V

OUT2

V

OUT2

3869 F08b

TIME

3869 F05a

(5a) Coincident Tracking

(5b) Ratiometric Tracking

Figure 7ꢀ Two Different Modes of ꢂutput 6oltage Tracking

V

OUT1

V

OUT1

V

OUT2

V

OUT2

R3

R4

R1

R2

R3

R4

R3

R4

R1

R2

TO

TK/SS2

TO

FB1

TO

FB2

TO

FB2

TO

TK/SS2

TO

FB1

V

3869 F09

(6a) Coincident Tracking Setup

(6b) Ratiometric Tracking Setup

Figure ꢁꢀ Setup for Coincident and Ratiometric Tracking

3869f

19

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

INT6 Regulators and EXT6

above 4.5V. Using the EXTV allows the MOSFET driver

CC

andcontrolpowertobederivedfromoneoftheLTC3869’s

switching regulator outputs during normal operation and

The LTC3869 features a true PMOS LDO that supplies

power to INTV from the V supply. INTV powers the

CC

IN

CC

from the INTV when the output is out of regulation

CC

gate drivers and much of the LTC3869’s internal circuitry.

ThelinearregulatorregulatesthevoltageattheINTV pin

(e.g., start-up, short-circuit). If more current is required

CC

throughtheEXTV thanisspeciﬁed, anexternalSchottky

CC

to 5V when V is greater than 5.5V. EXTV connects to

IN

CC

diode can be added between the EXTV and INTV pins.

CC

INTV through a P-channel MOSFET and can supply the

CC

Do not apply more than 6V to the EXTV pin and make

CC

needed power when its voltage is higher than 4.7V. Each

of these can supply a peak current of 100mA and must

be bypassed to ground with a minimum of 4.7µF ceramic

capacitor or low ESR electrolytic capacitor. No matter

what type of bulk capacitor is used, an additional 0.1µF

sure that EXTV < V at all times.

CC

IN

Signiﬁcant efﬁciency and thermal gains can be realized by

powering INTV from the output, since the V current

CC

IN

resultingfromthedriverandcontrolcurrentswillbescaled

by a factor of (Duty Cycle)/(Switcher Efﬁciency).

ceramic capacitor placed directly adjacent to the INTV

CC

and PGND pins is highly recommended. Good bypassing

is needed to supply the high transient currents required

by the MOSFET gate drivers and to prevent interaction

between the channels.

Tying the EXTV pin to a 5V supply reduces the junction

CC

temperature in the previous example from 125°C to:

T = 70°C + (42mA)(5V)(34°C/W) = 77°C

J

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3869 to be

However, for 3.3V and other low voltage outputs, addi-

tional circuitry is required to derive INTV power from

CC

the output.

exceeded. The INTV current, which is dominated by the

CC

The following list summarizes the four possible connec-

gatechargecurrent,maybesuppliedbyeitherthe5Vlinear

tions for EXTV :

CC

regulator or EXTV . When the voltage on the EXTV pin

CC

1. EXTV left open (or grounded). This will cause

is less than 4.7V, the linear regulator is enabled. Power

dissipation for the IC in this case is highest and is equal

CC

INTV to be powered from the internal 5V regulator

CC

resulting in an efﬁciency penalty of up to 10% at high

input voltages.

to V • I

. The gate charge current is dependent

IN

INTVCC

on operating frequency as discussed in the Efﬁciency

Considerations section. The junction temperature can be

estimated by using the equations given in Note 3 of the

2. EXTV connected directly to V . This is the

CC

OUT

normal connection for a 5V regulator and provides

the highest efﬁciency.

ElectricalCharacteristics.Forexample,theLTC3869INTV

CC

current is limited to less than 42mA from a 38V supply in

3. EXTV connected to an external supply. If a 5V

the UFD package and not using the EXTV supply:

CC

external supply is available, it may be used to power

T = 70°C + (42mA)(38V)(34°C/W) = 125°C

J

EXTV providing it is compatible with the MOSFET

CC

To prevent the maximum junction temperature from being

exceeded, the input supply current must be checked while

operatingincontinuousconductionmode(MODE/PLLIN=

gate drive requirements.

4. EXTV connected to an output-derived boost net-

CC

work. For 3.3V and other low voltage regulators,

SGND) at maximum V . When the voltage applied to EXT-

IN

efﬁciency gains can still be realized by connecting

V

rises above 4.7V, the INTV linear regulator is turned

CC

EXTV to an output-derived voltage that has been

CC

offandtheEXTV isconnectedtotheINTV .TheEXTV

CC

boosted to greater than 4.7V.

remainsonaslongasthevoltageappliedtoEXTV remains

CC

3869f

20

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

For applications where the main input power is below 5V,

UVLOcomparatorconstantlymonitorstheINTV voltage

CC

tie the V and INTV pins together and tie the combined

to ensure that an adequate gate-drive voltage is present. It

IN

CC

pins to the 5V input with a 1Ω or 2.2Ω resistor as shown

locks out the switching action when INTV is below 3.2V.

CC

in Figure 7 to minimize the voltage drop caused by the

To prevent oscillation when there is a disturbance on the

gate charge current. This will override the INTV linear

INTV , the UVLO comparator has 600mV of precision

CC

regulator and will prevent INTV from dropping too low

hysteresis.

CC

due to the dropout voltage. Make sure the INTV voltage

CC

Another way to detect an undervoltage condition is to

is at or exceeds the R

test voltage for the MOSFET

DS(ON)

monitor the V supply. Because the RUN pins have a

IN

which is typically 4.5V for logic level devices.

precision turn-on reference of 1.2V, one can use a resistor

divider to V to turn on the IC when V is high enough.

IN

An extra 4.5µA of current ﬂows out of the RUN pin once

the RUN pin voltage passes 1.2V. One can program the

hysteresis of the run comparator by adjusting the values

V

IN

LTC3869

INTV

R

VIN

5V

CC

1Ω

CINTV

4.7µF

CC

of the resistive divider. For accurate V undervoltage

+

IN

C

IN

detection, V needs to be higher than 4.5V.

IN

3869 F07

C and C

Selection

Figure .ꢀ Setup for a 76 Input

IN

ꢂUT

The selection of C is simpliﬁed by the 2-phase architec-

IN

Topside MꢂSFET Driver Supply (C , DB)

B

ture and its impact on the worst-case RMS current drawn

throughtheinputnetwork(battery/fuse/capacitor).Itcanbe

shown that the worst-case capacitor RMS current occurs

when only one controller is operating. The controller with

External bootstrap capacitors C connected to the BOOST

B

pinssupplythegatedrivevoltagesforthetopsideMOSFETs.

Capacitor C in the Functional Diagram is charged though

B

external diode DB from INTV when the SW pin is low.

CC

the highest (V )(I ) product needs to be used in the

OUT OUT

When one of the topside MOSFETs is to be turned on,

formula below to determine the maximum RMS capacitor

current requirement. Increasing the output current drawn

from the other controller will actually decrease the input

RMS ripple current from its maximum value. The out-of-

phasetechniquetypicallyreducestheinputcapacitor’sRMS

ripple current by a factor of 30% to 70% when compared

to a single phase power supply solution.

the driver places the C voltage across the gate source

B

of the desired MOSFET. This enhances the MOSFET and

turns on the topside switch. The switch node voltage, SW,

rises to V and the BOOST pin follows. With the topside

IN

MOSFET on, the boost voltage is above the input supply:

V

= V + V

. The value of the boost capacitor

BOOST

IN

INTVCC

C needs to be 100 times that of the total input capa-

B

Incontinuousmode,thesourcecurrentofthetopMOSFET

citance of the topside MOSFET(s). The reverse break-

down of the external Schottky diode must be greater than

is a square wave of duty cycle (V )/(V ). To prevent

OUT

IN

large voltage transients, a low ESR capacitor sized for the

maximum RMS current of one channel must be used. The

maximum RMS capacitor current is given by:

V

. Make sure the diode is a low leakage diode even

IN(MAX)

at hot temperature to prevent leakage current feeding

INTV .Whenadjustingthegatedrivelevel,theﬁnalarbiter

CC

is the total input current for the regulator. If a change is

made and the input current decreases, then the efﬁciency

has improved. If there is no change in input current, then

there is no change in efﬁciency.

I_MAX

1/2

⎡

⎤

C_INRequired I_RMS

≈

V

V – V

IN

OUT

(

_OUT)(

)

⎣

⎦

V

IN

This formula has a maximum at V = 2V , where I

=

IN

OUT

RMS

I

/2.Thissimpleworst-caseconditioniscommonlyused

OUT

Undervoltage Lockout

for design because even signiﬁcant deviations do not of-

fer much relief. Note that capacitor manufacturers’ ripple

The LTC3869 has two functions that help protect the

controller in case of undervoltage conditions. A precision

current ratings are often based on only 2000 hours of life.

3869f

21

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may be paralleled to meet

size or height requirements in the design. Due to the high

operating frequency of the LTC3869, ceramic capacitors

Setting ꢂutput 6oltage

The LTC3869 output voltages are each set by an external

feedback resistive divider carefully placed across the out-

put, as shown in Figure 8. The regulated output voltage

is determined by:

can also be used for C . Always consult the manufacturer

IN

⎛

⎞

⎟

⎠

if there is any question.

R_B

R_A

V_OUT= 0.6V • 1+

⎜

The beneﬁt of the LTC3869 2-phase operation can be

calculated by using the equation above for the higher

power controller and then calculating the loss that would

have resulted if both controller channels switched on at

the same time. The total RMS power lost is lower when

both controllers are operating due to the reduced overlap

of current pulses required through the input capacitor’s

ESR. This is why the input capacitor’s requirement cal-

culated above for the worst-case controller is adequate

for the dual controller design. Also, the input protection

fuse resistance, battery resistance, and PC board trace

resistance losses are also reduced due to the reduced

peak currents in a 2-phase system. The overall beneﬁt of

a multiphase design will only be fully realized when the

source impedance of the power supply/battery is included

in the efﬁciency testing. The sources of the top MOSFETs

should be placed within 1cm of each other and share a

⎝

To improve the frequency response, a feed-forward ca-

pacitor, C , may be used. Great care should be taken to

FF

route the V line away from noise sources, such as the

FB

inductor or the SW line.

V

OUT

R

C

FF

B

1/2 LTC3869

V

FB

R

A

3869 F08

Figure 8ꢀ Setting ꢂutput 6oltage

Fault Conditions: Current Limit and Current Foldback

The LTC3869 includes current foldback to help limit load

current when the output is shorted to ground. If the out-

put falls below 50% of its nominal output level, then the

maximum sense voltage is progressively lowered from its

maximumprogrammedvaluetoone-thirdofthemaximum

value. Foldback current limiting is disabled during the

soft-start or tracking up. Under short-circuit conditions

with very low duty cycles, the LTC3869 will begin cycle

skipping in order to limit the short-circuit current. In this

situation the bottom MOSFET will be dissipating most of

the power but less than in normal operation. The short-

circuit ripple current is determined by the minimum on-

common C (s). Separating the sources and C may pro-

IN

duce undesirable voltage and current resonances at V .

IN

A small (0.1µF to 1µF) bypass capacitor between the chip

V pin and ground, placed close to the LTC3869, is also

IN

suggested. A 2.2Ω to 10Ω resistor placed between C

IN

(C1) and the V pin provides further isolation between

IN

the two channels.

The selection of C

is driven by the effective series

OUT

resistance (ESR). Typically, once the ESR requirement

is satisﬁed, the capacitance is adequate for ﬁltering. The

time t

of the LTC3869 (≈ 90ns), the input voltage

ON(MIN)

output ripple (∆V ) is approximated by:

OUT

and inductor value:

⎛

⎞

⎟

⎠

1

V

IN

ΔV_OUT≈ I_RIPPLEESR+

⎜

ΔI_L(SC)= t_ON(MIN)

•

8fC_OUT

⎝

L

The resulting short-circuit current is:

where f is the operating frequency, C

is the output

OUT

capacitance and I

is the ripple current in the induc-

RIPPLE

1/3 V_SENSE(MAX)

1

I_SC=

– ΔI_L(SC)

tor. The output ripple is highest at maximum input voltage

since I increases with input voltage.

R_SENSE

2

RIPPLE

3869f

22

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

Phase-Locked Loop and Frequency Synchronization

The LTC3869 has a phase-locked loop (PLL) comprised of

900

800

700

600

500

400

300

200

100

0

an internal voltage-controlled oscillator (V ) and a phase

CO

detector. This allows the turn-on of the top MOSFET of

controller 1 to be locked to the rising edge of an external

clock signal applied to the MODE/PLLIN pin. The turn-on

of controller 2’s top MOSFET is thus 180 degrees out-

of-phase with the external clock. The phase detector is

an edge sensitive digital type that provides zero degrees

phase shift between the external and internal oscillators.

This type of phase detector does not exhibit false lock to

harmonics of the external clock.

0

0.5

1

1.5

2

2.5

FREQ PIN VOLTAGE (V)

3869 F09

Figure 9ꢀ Relationship Between ꢂscillator

Frequency and 6oltage at the FREQ Pin

Theoutputofthephasedetectorisapairofcomplementary

current sources that charge or discharge the internal ﬁlter

network. There is a precision 10µA of current ﬂowing out

of FREQ pin. This allows the user to use a single resistor

to SGND to set the switching frequency when no external

clockisappliedtotheMODE/PLLINpin.Theinternalswitch

between FREQ pin and the integrated PLL ﬁlter network

is ON, allowing the ﬁlter network to be pre-charged to the

same voltage potential as the FREQ pin. The relationship

between the voltage on the FREQ pin and the operating

frequency is shown in Figure 9 and speciﬁed in the Electri-

cal Characteristics table. If an external clock is detected on

theMODE/PLLINpin, theinternalswitchmentionedabove

will turn off and isolate the inﬂuence of FREQ pin. Note

that the LTC3869 can only be synchronized to an external

clock whose frequency is within range of the LTC3869’s

2.4V 5V

10µA

R

SET

FREQ

MODE/

PLLIN

DIGITAL

PHASE/

SYNC

EXTERNAL

OSCILLATOR

FREQUENCY

DETECTOR

VCO

3869 F10

Figure 10ꢀ Phase-Locked Loop Block Diagram

Typically, the external clock (on MODE/PLLIN pin)

input high threshold is 1.6V, while the input low threshold

is 1V. It is not recommended to apply the external clock

when IC is in shutdown.

internalV . Thisisguaranteedtobebetween250kHzand

CO

780kHz. A simpliﬁed block diagram is shown in Figure 10.

If the external clock frequency is greater than the internal

oscillator’s frequency, f , then current is sourced con-

OSC

tinuously from the phase detector output, pulling up the

Minimum ꢂn-Time Considerations

ﬁlter network. When the external clock frequency is less

Minimum on-time t

is the smallest time duration

ON(MIN)

than f , current is sunk continuously, pulling down

OSC

that the LTC3869 is capable of turning on the top MOSFET.

It is determined by internal timing delays and the gate

charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that

the ﬁlter network. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

the phase difference. The voltage on the ﬁlter network is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

the ﬁlter capacitor holds the voltage.

V_OUT

t_ON(MIN)

<

V (ƒ)

IN

3869f

23

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

from INTV to ground. The resulting dQ/dt is a cur-

CC

rent out of INTV that is typically much larger than the

CC

control circuit current. In continuous mode, I

GATECHG

= f(Q + Q ), where Q and Q are the gate charges of

T

B

T

B

the topside and bottom side MOSFETs.

The minimum on-time for the LTC3869 is approximately

90ns, with reasonably good PCB layout, minimum 40%

inductor current ripple and at least 10mV – 15mV ripple

on the current sense signal. The minimum on-time can be

affected by PCB switching noise in the voltage and current

loop. As the peak sense voltage decreases the minimum

on-time gradually increases to 130ns. This is of particular

concern in forced continuous applications with low ripple

current at light loads. If the duty cycle drops below the

minimum on-time limit in this situation, a signiﬁcant

amount of cycle skipping can occur with correspondingly

larger current and voltage ripple.

Supplying INTV power through EXTV from an out-

CC

put-derived source will scale the V current required

IN

for the driver and control circuits by a factor of (Duty

Cycle)/(Efﬁciency). Forexample, ina20Vto5Vapplica-

tion, 10mA of INTV current results in approximately

CC

2.5mAofV current.Thisreducesthemid-currentloss

IN

from 10% or more (if the driver was powered directly

from V ) to only a few percent.

IN

2

3. I R losses are predicted from the DC resistances of the

fuse(ifused), MOSFET, inductor, currentsenseresistor.

In continuous mode, the average output current ﬂows

through L and R , but is “chopped” between the

SENSE

Efﬁciency Considerations

topside MOSFET and the synchronous MOSFET. If the

two MOSFETs have approximately the same R

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Percent efﬁciency can

be expressed as:

,

DS(ON)

then the resistance of one MOSFET can simply be

summed with the resistances of L and R

to ob-

SENSE

2

tain I R losses. For example, if each R

= 10mΩ,

DS(ON)

R = 10mΩ, R

= 5mΩ, then the total resistance

L

SENSE

is 25mΩ. This results in losses ranging from 2% to

8% as the output current increases from 3A to 15A for

a 5V output, or a 3% to 12% loss for a 3.3V output.

%Efﬁciency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Efﬁciency varies as the inverse square of V

for the

OUT

sameexternalcomponentsandoutputpowerlevel. The

combined effects of increasingly lower output voltages

andhighercurrentsrequiredbyhighperformancedigital

systemsisnotdoublingbutquadruplingtheimportance

of loss terms in the switching regulator system!

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3869 circuits: 1) IC V current, 2) INTV

IN

CC

2

regulator current, 3) I R losses, 4) Topside MOSFET

transition losses.

4. Transition losses apply only to the topside MOSFET(s),

and become signiﬁcant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

1. The V current is the DC supply current given in

IN

the Electrical Characteristics table, which excludes

MOSFET driver and control currents. V current typi-

IN

cally results in a small (<0.1%) loss.

2

Transition Loss = (1.7) V

I

C

ƒ

IN O(MAX) RSS

2. INTV current is the sum of the MOSFET driver and

CC

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efﬁciency degradation in portable systems. It is very

important to include these “system” level losses during

the design phase. The internal battery and fuse resistance

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge dQ moves

3869f

24

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

losses can be minimized by making sure that C has

The I series R -C ﬁlter sets the dominant pole-zero

TH C C

IN

adequate charge storage and very low ESR at the switch-

ing frequency. A 25W supply will typically require a

minimum of 20µF to 40µF of capacitance having

a maximum of 20mΩ to 50mΩ of ESR. The LTC3869

2-phasearchitecturetypicallyhalvesthisinputcapacitance

requirement over competing solutions. Other losses

including Schottky conduction losses during dead time

and inductor core losses generally account for less than

2% total additional loss.

loop compensation. The values can be modiﬁed slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the ﬁnal PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1µs to 10µs will

produce output voltage and I pin waveforms that will

TH

give a sense of the overall loop stability without break-

ing the feedback loop. Placing a power MOSFET directly

across the output capacitor and driving the gate with an

appropriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This

Modest improvements in Burst Mode efﬁciency may be

realized by using a smaller inductor value, a lower switch-

ingfrequencyorforDCRsensingapplications, makingthe

DCR ﬁlter’s time constant smaller than the L/DCR time

constant for the inductor. A small Schottky diode with a

current rating equal to about 20% of the maximum load

current or less may yield minor improvements, too.

is why it is better to look at the I pin signal which is in

Checking Transient Response

TH

the feedback loop and is the ﬁltered and compensated

control loop response. The gain of the loop will be in-

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

creased by increasing R and the bandwidth of the loop

C

will be increased by decreasing C . If R is increased by

C

load current. When a load step occurs, V

shifts by an

OUT

the same factor that C is decreased, the zero frequency

C

amount equal to ∆I

(ESR), where ESR is the effective

LOAD

will be kept the same, thereby keeping the phase shift the

same in the most critical frequency range of the feedback

loop. The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

the actual overall supply performance.

series resistance of C . ∆I

also begins to charge or

OUT

LOAD

discharge C

generating the feedback error signal that

OUT

forces the regulator to adapt to the current change and

return V to its steady-state value. During this recovery

OUT

time V

can be monitored for excessive overshoot or

OUT

A second, more severe transient is caused by switching

in loads with large (>1µF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

ringing, which would indicate a stability problem. The

availability of the I pin not only allows optimization of

TH

control loop behavior but also provides a DC coupled and

AC ﬁltered closed loop response test point. The DC step,

rise time and settling at this test point truly reﬂects the

closed loop response. Assuming a predominantly second

ordersystem, phasemarginand/or dampingfactorcanbe

estimated using the percentage of overshoot seen at this

pin.Thebandwidthcanalsobeestimatedbyexaminingthe

with C , causing a rapid drop in V . No regulator can

OUT

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

C

to C

is greater than 1:50, the switch rise time

LOAD

OUT

should be controlled so that the load rise time is limited

to approximately 25 • C . Thus a 10µF capacitor would

rise time at the pin. The I external components shown

TH

LOAD

in the Typical Application circuit will provide an adequate

starting point for most applications.

require a 250µs rise time, limiting the charging current

to about 200mA.

3869f

25

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

PC Board Layout Checklist

6. Keep the switching nodes (SW1, SW2), top gate nodes

(TG1, TG2), andboostnodes(BOOST1, BOOST2)away

from sensitive small-signal nodes, especially from the

opposite channel’s voltage and current sensing feed-

back pins. All of these nodes have very large and fast

moving signals and therefore should be kept on the

“output side” of the LTC3869 and occupy minimum

PC trace area. If DCR sensing is used, place the top

resistor (Figure 2b, R1) close to the switching node.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layout diagram of Figure 11. Figure 12 illustrates the

current waveforms present in the various branches of

the 2-phase synchronous regulators operating in the

continuous mode. Check the following in your layout:

1. Are the top N-channel MOSFETs M1 and M3 located

within 1 cm of each other with a common drain con-

7. Use a modiﬁed “star ground” technique: a low imped-

ance, large copper area central grounding point on

the same side of the PC board as the input and output

nection at C ? Do not attempt to split the input de-

IN

coupling for the two channels as it can cause a large

resonant loop.

capacitors with tie-ins for the bottom of the INTV

CC

decouplingcapacitor,thebottomofthevoltagefeedback

2. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return

resistive divider and the SGND pin of the IC.

of C

must return to the combined C

(–) ter-

PC Board Layout Debugging

INTVCC

OUT

minals. The V and I traces should be as short as

FB

TH

Start with one controller at a time. It is helpful to use a

DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switching node (SW pin) to synchronize the oscilloscope

totheinternaloscillatorandprobetheactualoutputvoltage

as well. Check for proper performance over the operating

voltage and current range expected in the application.

The frequency of operation should be maintained over

the input voltage range down to dropout and until the

output load drops below the low current operation

threshold—typically 10% of the maximum designed cur-

rent level in Burst Mode operation.

possible.ThepathformedbythetopN-channelMOSFET,

Schottky diode and the C capacitor should have short

IN

leads and PC trace lengths. The output capacitor (–)

terminals should be connected as close as possible

to the (–) terminals of the input capacitor by placing

the capacitors next to each other and away from the

Schottky loop described above.

3. Do the LTC3869 V pins’ resistive dividers connect to

FB

the (+) terminals of C ? The resistive divider must be

OUT

connected between the (+) terminal of C

and signal

OUT

ground. The feedback resistor connections should not

be along the high current input feeds from the input

capacitor(s).

The duty cycle percentage should be maintained from

cycletocycleinawell-designed,lownoisePCBimplemen-

tation. Variation in the duty cycle at a subharmonic rate

can suggest noise pickup at the current or voltage sensing

inputs or inadequate loop compensation. Overcompensa-

tion of the loop can be used to tame a poor PC layout if

regulatorbandwidthoptimizationisnotrequired.Onlyafter

each controller is checked for its individual performance

should both controllers be turned on at the same time.

A particularly difﬁcult region of operation is when one

controller channel is nearing its current comparator trip

pointwhentheotherchannelisturningonitstopMOSFET.

This occurs around 50% duty cycle on either channel due

to the phasing of the internal clocks and may cause minor

+

–

4. Are the SENSE and SENSE leads routed together with

minimumPCtracespacing?Theﬁltercapacitorbetween

+

–

SENSE and SENSE should be as close as possible

to the IC. Ensure accurate current sensing with Kelvin

connectionsatthesenseresistororinductor,whichever

is used for current sensing.

5. Is the INTV decoupling capacitor connected close to

CC

theIC, betweentheINTV andthepowergroundpins?

CC

ThiscapacitorcarriestheMOSFETdriverscurrentpeaks.

Anadditional1µFceramiccapacitorplacedimmediately

next to the INTV and PGND pins can help improve

CC

noise performance substantially.

duty cycle jitter.

3869f

26

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

R

TK/SS1

PU2

V

PULL-UP

PGOOD

I

PGOOD

TH1

LTC3869

V

FB1

L1

R

SENSE

D1

+

–

V

OUT1

SENSE1

FREQ

TG1

SW1

C

B1

M1

M2

BOOST1

BG1

I

LIM

1µF

CERAMIC

R

IN

f

IN

MODE/PLLIN

RUN1

C

OUT1

V

IN

C

VIN

PGND

RUN2

GND

V

IN

EXTV

CC

C

IN

SGND

C

INTVCC

–

INTV

SENSE2

OUT2

D2

1µF

CERAMIC

+

BG2

SENSE2

M4

M3

BOOST2

V

FB2

TH2

C

B2

SW2

TG2

I

R

SENSE

V

OUT2

TK/SS2

L2

3869 F11

Figure 11ꢀ Recommended Printed Circuit Layout Diagram

3869f

27

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

SW1

L1

R

V

SENSE1

OUT1

D1

C

OUT1

R

L1

V

IN

R

IN

C

IN

SW2

L2

R

V

SENSE2

OUT2

D2

C

OUT2

R

L2

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

3869 F12

Figure 12ꢀ Branch Current Waveforms

3869f

28

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

Reduce V from its nominal level to verify operation

The inductance values are based on a 35% maximum

ripple current assumption (5.25A for each channel). The

highest value of ripple current occurs at the maximum

input voltage:

IN

of the regulator in dropout. Check the operation of the

undervoltage lockout circuit by further lowering V while

IN

monitoring the outputs to verify operation.

⎛

⎞

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

V_OUT

ƒ • ΔI_L(MAX)

V_OUT

V_IN(MAX)

⎜

⎝

⎟

⎠

L =

1−

Channel 1 will require 0.78µH, and channel 2 will require

0.54µH. The Vishay IHLP4040DZ-01, 0.56µH inductor is

chosen for both rails. At the nominal input voltage (12V),

the ripple current will be:

⎛

⎜

⎝

⎞

⎟

⎠

V_OUT

ƒ • L

V_OUT

V

IN(NOM)

ΔI_L(NOM)

=

1−

for inductive coupling between C , Schottky and the top

IN

Channel 1 will have 6.8A (46%) ripple, and channel 2 will

have 4.8A (32%) ripple. The peak inductor current will be

the maximum DC value plus one-half the ripple current,

or 18.4A for channel 1 and 17.4A for channel 2.

MOSFET components to the sensitive current and voltage

sensing traces. In addition, investigate common ground

path voltage pickup between these components and the

SGND pin of the IC.

Theminimumon-timeoccursonchannel2atthemaximum

IN

Design Example

V , and should not be less than 90ns:

As a design example for a two channel high current regu-

V_OUT

_IN(MAX)ƒ 20V(400kHz)

1.2V

t_ON(MIN)

=

= 150ns

lator, assume V = 12V(nominal), V = 20V(maximum),

IN

OUT2

(see Figure 13).

IN

V

= 1.8V, V

= 1.2V, I = 15A, and f = 400kHz

OUT1

MAX1,2

With I

ﬂoating, the equivalent R

resistor value

SENSE

LIM

The regulated output voltages are determined by:

can be calculated by using the minimum value for the

maximum current sense threshold (43mV).

⎛

⎞

⎟

⎠

R_B

R_A

V_OUT= 0.6V • 1+

⎜

V_SENSE(MIN)

⎝

R_SENSE(EQUIV)

=

ΔI_L(NOM)

I_LOAD(MAX)

+

Using 20k 1% resistors from both V nodes to ground,

FB

2

the top feedback resistors are (to the nearest 1% standard

value) 40.2k and 20k.

The equivalent required R

value is 2.4mΩ for chan-

SENSE

nel 1 and 2.5mΩ for channel 2. The DCR of the 0.56µH

inductor is 1.7mΩ typical and 1.8mΩ maximum for a

25°C ambient. At 100°C, the estimated maximum DCR

value is 2.3mΩ. The maximum DCR value is just slightly

The frequency is set by biasing the FREQ pin to 1V (see

Figure 9).

under the equivalent R

values. Therefore, R2 is not

SENSE

required to divide down the signal.

3869f

29

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

V

IN

4.5V TO

82µF 20V

25V

+

10µF

25V

×2

1µF

2.2Ω

4.7µF

D3

D4

V

PGOOD EXTV INTV

CC CC

IN

M1

M2

M3

M4

TG1

TG2

0.1µF

L1

L2

0.56µH

BOOST1

SW1

BOOST2

SW2

0.56µH

LTC3869

BG2

BG1

3.09k

1%

3.09k

1%

MODE/PLLIN

PGND

FREQ

I

LIM

+

SENSE1

SENSE2

0.1µF

–

SENSE1

SENSE2

20k

1%

RUN2

RUN1

40.2k

1%

V

OUT1

1.8V

15A

V

1.2V

15A

OUT2

V

TH1

V

TH2

FB1

FB2

I

1nF

TK/SS1

TK/SS2

SGND

+

150pF

0.1µF

C

OUT1

330µF

OUT2

20k

1%

20k

1%

12.1k

1%

100k

1%

4.99k

1%

330µF

0.1µF

×2

3869 F13

L1, L2: VISHAY IHLP4040DZ-01, 0.56µH

M1, M3: RENESAS RJK0305DPB

M2, M4: RENESAS RJK0330DPB

Figure 13ꢀ High Efﬁciency Dual 400kHz 1ꢀ86/1ꢀ26 Step-Down Converter

95

90

85

80

75

70

5

4

3

2

1

0

V

= 12V

1.8V R

SENSE

IN

MODE = CCM

1.8V DCR SENSE

EFFICIENCY

POWER LOSS

1.2V R

SENSE

1.2V DCR SENSE

0

2

4

6

8

10 12 14 16

LOAD CURRENT (A)

3869 F14

DCR SENSE APP: SEE FIGURE 16

R

APP: SEE FIGURE 19

SENSE

Figure 14ꢀ DCR Sense Efﬁciency vs R_SENSEEfﬁciency

3869f

30

LTC3869/LTC3869-2

APPLICATIONS INFORMATION

For each channel, 0.1µF is selected for C1.

For a 2mΩ sense resistor, a short-circuit to ground will

result in a folded back current of:

L

0.56µH

R1=

=

= 3.11k

⎛

⎜

⎝

⎞

⎟

⎠

1/ 3 50mV

90ns(20V)

0.56µH

1

2

(DCR_MAXat 25°C) • C1 1.8mΩ • 0.1µF

(

)

I_SC

=

–

= 6.7A

0.002Ω

Choose R1 = 3.09k

A Renesas RJK0330DPB, R

= 3.9mΩ, is chosen for

DS(ON)

The power loss in R1 at the maximum input voltage is:

the bottom FET. The resulting power loss is:

(V_IN(MAX)− V_OUT) • V_OUT

P_LOSSR1=

20V – 1.8V

2

P

=

15A •

(

R1

)

SYNC

20V

The resulting power loss for R1 is 11mW for channel 1

and 7mW for channel 2.

⎡

⎤

1+ 0.005 • 75°C – 25°C • 0.0039Ω

(

)

(

)

⎣

⎦

P

= 1W

SYNC

The sum of the sense resistor and DCR is 2.5mΩ (max)

for the R

application whereas the inductor DCR for

C is chosen for an RMS current rating of at least 7.5A at

SENSE

IN

the DCR sense application is 1.8mΩ (max). As a result of

temperature assuming only channel 1 or 2 is on. C

is

OUT

thelowerconductionlossesfromtheswitchnodetoV

the DCR sensing application has higher efﬁciency.

,

chosen with an equivalent ESR of 4.5mΩ for low output

ripple.Theoutputrippleincontinuousmodewillbehighest

at the maximum input voltage. The output voltage ripple

due to ESR is approximately:

OUT

The power dissipation on the topside MOSFET can be

easily estimated. Choosing a Renesas RJK0305DPB

MOSFET results in: R

MILLER

(estimated) = 75°C:

= 13mΩ (max), V

=

V

= R

(∆I ) = 0.0045Ω • 6.8A = 31mV

ESR L P–P

DS(ON)

MILLER

ORIPPLE

2.6V, C

≅ 150pF. At maximum input voltage with T

J

Further reductions in output voltage ripple can be made

by placing a 100µF ceramic across C

.

OUT

1.8V

2

P_MAIN

=

15A 1+(0.005)(75°C – 25°C) •

(

)

[

]

20V

0.013Ω + 20V

⎛

⎞

⎟

⎠

15A

2

2Ω 150pF •

)(

(

) (

)

⎜

(

)

⎝

⎡

⎤

1

+

400kHz

(

⎥

)

⎢

⎣

⎦

5V – 2.6V 2.6V

= 329mW + 288mW

= 617mW

3869f

31

LTC3869/LTC3869-2

TYPICAL APPLICATIONS

S W 1

T G 2

M O D E / P L L I N

S W 2

F R E Q

R U N 1

P G O O D

L I M

I

S E N S E 1

+

–

R U N 2

3869f

32

LTC3869/LTC3869-2

TYPICAL APPLICATIONS

S W 1

T G 2

M O D E / P L L I N

S W 2

F R E Q

R U N 1

P G O O D

L I M

I

S E N S E 1

+

–

R U N 2

3869f

33

LTC3869/LTC3869-2

TYPICAL APPLICATIONS

S W 1

T G 2

M O D E / P L L I N

S W 2

F R E Q

R U N 1

P G O O D

L I M

I

S E N S E 1

+

–

R U N

3869f

34

LTC3869/LTC3869-2

TYPICAL APPLICATIONS

S W 1

T G 2

M O D E / P L L I N

S W 2

F R E Q

R U N 1

P G O O D

L I M

I

S E N S E 1

+

–

R U N

3869f

35

LTC3869/LTC3869-2

TYPICAL APPLICATIONS

S W 1

T G 2

M O D E / P L L I N

S W 2

F R E Q

R U N 1

P G O O D

L I M

I

S E N S E 1

+

–

R U N

3869f

36

LTC3869/LTC3869-2

TYPICAL APPLICATIONS

S W 1

T G 2

M O D E / P L L I N

S W 2

F R E Q

R U N 1

P G O O D

L I M

I

S E N S E 1

+

–

R U N 2

3869f

37

LTC3869/LTC3869-2

PACKAGE DESCRIPTION

UFD Package

28-Lead Plastic QFN (4mm × 7mm)

(Reference LTC DWG # 05-08-1712 Rev B)

0.70 0.05

4.50 0.05

3.10 0.05

2.50 REF

2.65 0.05

3.65 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

3.50 REF

4.10 0.05

5.50 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

R = 0.20 OR 0.35

× 45° CHAMFER

2.50 REF

R = 0.115

TYP

R = 0.05

TYP

0.75 0.05

4.00 0.10

(2 SIDES)

27

28

0.40 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

5.00 0.10

(2 SIDES)

3.50 REF

3.65 0.10

2.65 0.10

(UFD28) QFN 0506 REV B

0.25 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3869f

38

LTC3869/LTC3869-2

PACKAGE DESCRIPTION

GN Package

28-Lead Plastic SSꢂP (Narrow ꢀ170 Inch)

(Reference LTC DWG # 05-08-1641)

.386 – .393*

(9.804 – 9.982)

.045 .005

.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 .0015

.0250 BSC

1

2

3

4

5

6

7

8

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

.015 .004

(0.38 0.10)

.0532 – .0688

(1.35 – 1.75)

× 45°

.004 – .0098

(0.102 – 0.249)

.0075 – .0098

(0.19 – 0.25)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.008 – .012

.0250

(0.635)

BSC

GN28 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

3869f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

39

LTC3869/LTC3869-2

TYPICAL APPLICATIONS

3ꢀ36/7A, 76/7A Converter Using Sense Resistors

V

IN

7V TO

24V

22µF

50V

2.2Ω

1µF

4.7µF

Si4816BDY

M1

Si4816BDY

M2

D3

D4

V

PGOOD INTV

IN

CC

TG1

TG2

0.1µF

L2

2.2µH

L2

3.3µH

BOOST1

SW1

BOOST2

SW2

LTC3869

BG2

BG1

MODE/PLLIN

PGND

FREQ

SENSE2

I

LIM

10Ω

1000pF

10Ω

+

–

+

SENSE1

1000pF

10Ω

8mΩ

–

SENSE1

RUN1

SENSE2

15pF

10pF

RUN2

V

EXTV

V

OUT1

3.3V

5A

CC

V

OUT2

V

5V

FB2

TH2

FB1

147k

1%

5A

90.9k

1%

I

TH1

1000pF

TK/SS1

TK/SS2

SGND

+

20k

1%

100pF

C

10k

1%

20k

1%

C

OUT2

150µF

15k

1%

122k

1%

OUT1

220µF

100pF

0.1µF

3869 TA02

L1: TDK RLF 7030T-2R2M5R4

L2: TDK ULF10045T-3R3N6R9

C

: SANYO 4TPE220MF

OUT1

: SANYO 6TPE150MI

OUT2

RELATED PARTS

PART NUMBER DESCRIPTIꢂN

CꢂMMENTS

Phase-Lockable Fixed 250kHz to 780kHz Frequency,

4V ≤ V ≤ 30V, 0.8V ≤ V ≤ 5.25V

LTC3850/

Dual 2-Phase, High Efﬁciency Synchronous Step-Down DC/DC

Controller, R or DCR Current Sensing and Tracking

LTC3850-1/

LTC3850-2

SENSE

IN

OUT

LTC3860

LTC3855

LTC3890

LTC3856

LTC3853

Dual, Multiphase, Synchronous Step-Down DC/DC Controller with

Differential Ampliﬁer and Tri-State Output Drive

Operates with Power Blocks, DRMOS Devices or External Drivers/

MOSFETs, 3V ≤ V ≤ 24V, t = 20ns

IN

ON(MIN)

Dual, Multiphase, Synchronous Step-Down DC/DC Controller with

Differential Ampliﬁer and DCR Temperature Compensation

Phase-Lockable Fixed Frequency 250kHz to 770kHz,

4.5V ≤ V ≤ 38V, 0.8V ≤ V ≤ 12V

IN

OUT

Dual, High V Low I Synchronous Step-Down DC/DC Controller

PLL Capable Fixed Frequency 50kHz to 900kHz,

4V ≤ V ≤ 60V, 0.8V ≤ V ≤ 24V, I = 50µA

IN

Q

IN

OUT

Q

2-Phase, Single Output Synchronous Step-Down DC/DC Controller

with Differential Ampliﬁer and DCR Temperature Compensation

Phase-Lockable Fixed 250kHz to 770kHz Frequency,

4.5V ≤ V ≤ 38V, 0.8V ≤ V ≤ 5V

IN

OUT

Triple Output, Multiphase Synchronous Step-Down DC/DC Controller, Phase-Lockable Fixed 250kHz to 750kHz Frequency,

or DCR Current Sensing and Tracking 4V ≤ V ≤ 24V, V Up to 13.5V

R

SENSE

IN

OUT3

LTC3851A/

LTC3851A-1

No R

™ Wide V Range Synchronous Step-Down DC/DC

PLL Fixed Frequency 250kHz to 750kHz, 4V ≤ V ≤ 38V,

IN

SENSE

IN

Controller

0.8V ≤ V

≤ 5.25V, MSOP-16E, 3mm × 3mm QFN-16, SSOP-16

OUT

LTC3833

Fast Controlled On-Time, High Frequency Synchronous

Step-Down Controller with Differential Ampliﬁer

Up to 2MHz Operating Frequency, 4V ≤ V ≤ 38V,

IN

0.8V ≤ V

≤ 5.5V, 3mm × 4mm QFN-20, TSSOP-20E

OUT

3869f

LT 0211 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

40

●

 LINEAR TECHNOLOGY CORPORATION 2011

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3869IGN-2#TRPBF
厂家：	Linear
描述：	LTC3869 - Dual, 2-Phase Synchronous Step-Down DC/DC Controllers; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C 控制器
文件：	总40页 (文件大小：2704K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3869IGN-2#TRPBF [Linear]

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