LTC3872EDDB#TR [Linear]
IC SWITCHING CONTROLLER, 650 kHz SWITCHING FREQ-MAX, PDSO8, 3 X 2 MM, PLASTIC, MO-229WECD-1, DFN-8, Switching Regulator or Controller;
| 型号： | LTC3872EDDB#TR |
| 厂家： | 
Linear |
| 描述： | IC SWITCHING CONTROLLER, 650 kHz SWITCHING FREQ-MAX, PDSO8, 3 X 2 MM, PLASTIC, MO-229WECD-1, DFN-8, Switching Regulator or Controller |
| 文件： | 总32页 (文件大小：497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3759
Wide Input Voltage Range
Boost/SEPIC/Inverting
Controller
FEATURES
DESCRIPTION
The LT®3759 is a wide input range, current mode, DC/DC
controller which is capable of regulating either positive or
negative output voltages from a single feedback pin. It can
be configured as a boost, SEPIC or inverting converter.
n
Wide V Range: 1.6V to 42V
IN
n
Positive or Negative Output Voltage Programming
with a Single Feedback Pin
n
PGOOD Output Voltage Status Report
n
Accurate 50mV SENSE Threshold Voltage
The LT3759 drives a low side external N-channel power
MOSFET. An internal LDO regulator draws power from
n
Programmable Soft-Start
n
Programmable Operating Frequency (100kHz to 1MHz)
V or DRIVE to provide up to a 4.75V supply for the gate
IN
with One External Resistor
driver. The fixed frequency, current-mode architecture
results in stable operation over a wide range of supply
and output voltages. The operating frequency of LT3759
can be set over a 100kHz to 1MHz range with an external
resistor, or can be synchronized to an external clock using
the SYNC pin.
n
Synchronizable to an External Clock
n
Low Shutdown Current < 1μA
n
INTV Regulator Supplied from V or DRIVE
CC
IN
n
Programmable Input Undervoltage Lockout with
Hysteresis
APPLICATIONS
The LT3759 features soft-start and frequency foldback
functions to limit inductor current during start-up and
output short-circuit. A window comparator on the FBX pin
reportsviathePGOODpin,providingoutputvoltagestatus
indication. The device is available in a 12-Lead exposed
pad MSOP package.
n
Datacom and Industrial Boost, SEPIC and Inverting
Converters
n
Distributed Power Supplies
n
Portable Electronic Equipment
n
Automotive
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT and No R
are trademarks of Linear Technology Corporation. All other trademarks
SENSE
are the property of their respective owners. Protected by U.S. Patents including 7825665.
TYPICAL APPLICATION
2.5V to 36V Input, 12V Output SEPIC Converter
Excellent for Automotive 12V Post Regulator
Efficiency vs Output Current
4.7μF ×2
V
12V
L1A
OUT
100
V
V
= 12V
IN
IN
2.5V TO
0.5A, 2.5V ≤ V ≤ 8V
IN
2A, 8V < V ≤ 36V
C
4.7μF
×4
36V
IN
IN
95
90
85
80
75
V
105k
118k
IN
C
OUT1
10μF
L1B
EN/UVLO
LT3759
GATE
M1
SENSE
100k
5mΩ
PGOOD
DRIVE
TIE TO GND
IF NOT USED
SYNC
RT
105K
C
+
OUT2
47μF
×4
SS
VC
FBX
41.2k
200kHz
0
0.5
1
1.5
2
2.5
GND INTV
CC
OUTPUT CURRENT (A)
3759 TA01b
0.1μF
7.5k
22nF
15.8K
4.7μF
3759 TA01a
3759fb
1
LT3759
ABSOLUTE MAXIMUM RATINGS
(Note 1)
V ............................................................................42V
RT............................................................................1.5V
SENSE.................................................................... 0.3V
FBX ................................................................. –3V to 3V
Operating Junction Temperature Range (Note 4)
LT3759E/LT3759I .............................. –40°C to 125°C
LT3759H............................................ –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
IN
EN/UVLO (Note 2).....................................................42V
DRIVE .......................................................................42V
PGOOD......................................................................42V
INTV ........................................................................8V
CC
GATE.................................................................. (Note 3)
SYNC ..........................................................................8V
VC, SS.........................................................................3V
PIN CONFIGURATION
TOP VIEW
1
2
3
4
5
6
VC
FBX
SS
12 EN/UVLO
11
10 DRIVE
V
IN
13
GND
RT
SYNC
PGOOD
9
8
7
INTV
GATE
SENSE
CC
MSE PACKAGE
12-LEAD PLASTIC MSOP
θ
JA
= 35°C/W TO 40°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3759EMSE#PBF
LT3759IMSE#PBF
LT3759HMSE#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
12-Lead Plastic MSOP
12-Lead Plastic MSOP
12-Lead Plastic MSOP
TEMPERATURE RANGE
–40°C to 125°C
LT3759EMSE#TRPBF
LT3759IMSE#TRPBF
LT3759HMSE#TRPBF
3759
3759
3759
–40°C to 125°C
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container. Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3759fb
2
LT3759
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, EN/UVLO = 12V, INTVCC = 4.75V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
V
Operating Voltage
1.6
42
V
IN
IN
Shutdown I
EN/UVLO < 0.4V
EN/UVLO = 1.15V
0.1
1
6
μA
μA
Q
V
Operating I
350
450
μA
IN
Q
DRIVE Shutdown Quiescent Current
EN/UVLO < 0.4V
EN/UVLO = 1.15V
0.1
0.1
1
2
μA
μA
DRIVE Quiescent Current (Not Switching)
SENSE Current Limit Threshold
SENSE Input Bias Current
R = 27.4kΩ, DRIVE = 6V
2.0
50
2.5
54
mA
mV
μA
T
l
46
Current Out of Pin
–55
Error Amplifier
l
l
FBX Regulation Voltage (V
)
FBX > 0V
FBX < 0V
1.580
–0.815
1.6
–0.80
1.620
–0.785
V
V
FBX(REG)
FBX Pin Input Current
FBX = 1.6V
FBX = –0.8V
60
120
10
nA
nA
–10
Transconductance g (ΔI /ΔV
)
FBX = V
FBX(REG)
240
5
μs
m
2
FBX
VC Output Impedance
MΩ
FBX Line Regulation [ΔV
/(ΔV • V
)]
1.6V < V < 42V, FBX >0
0.02
0.02
0.05
0.05
%/V
%/V
FBX(REG)
IN
FBX(REG)
IN
1.6V < V < 42V, FBX <0
IN
VC Current Mode Gain (ΔV /ΔV
)
SENSE
5
V/V
μA
VC
VC Source Current
VC Sink Current
FBX = 0V, VC = 1.3V
–13
FBX = 1.7V, VC = 1.3V
FBX = –0.85V, VC = 1.3V
13
10
μA
μA
Oscillator
Switching Frequency
R = 27.4k to GND, V
= 1.6V
= 1.6V
= 1.6V
270
300
100
1000
330
kHz
kHz
kHz
T
FBX
FBX
FBX
R = 86.6k to GND, V
T
R = 6.81k to GND, V
T
R Voltage
FBX = 1.6V, –0.8V
1.2
170
170
V
ns
ns
V
T
GATE Minimum Off-Time
GATE Minimum On-Time
SYNC Input Low
200
200
0.4
l
l
l
SYNC Input High
1.5
V
SS Pull-Up Current
SS = 0V, Current Out of Pin
–14
–10.5
–7
μA
Low Dropout Regulators (DRIVE LDO and V LDO)
IN
l
l
DRIVE LDO Regulation Voltage
DRIVE = 6V
DRIVE = 0V
4.6
3.6
4.75
3.75
60
4.9
3.9
V
V
V
LDO Regulation Voltage
IN
DRIVE LDO Current Limit
LDO Current Limit
INTV = 4V
mA
mA
%
CC
V
DRIVE = 0V, INTV = 3V
60
IN
CC
DRIVE LDO Load Regulation (ΔV
/V
)
0 < I
< 20mA, DRIVE = 6V
–1
–1
–0.6
–0.6
0.03
0.03
190
INTVCC INTVCC
INTVCC
V
LDO Load Regulation (ΔV
/V
)
DRIVE = 0V, 0 < I < 20mA
INTVCC
%
IN
INTVCC INTVCC
DRIVE LDO Line Regulation [ΔV
/(V
• ΔV )] 1.6V < V < 42V, DRIVE = 6V
0.07
0.07
400
%/V
%/V
mV
INTVCC
INTVCC
IN
IN
V
LDO Line Regulation [ΔV
/(V
• ΔV )]
DRIVE = 0V, 5V < V < 42V
IN
IN
INTVCC
INTVCC
IN
l
DRIVE LDO Dropout Voltage (V
– V
)
DRIVE = 4V, I
= 20mA
DRIVE
INTVcc
INTVCC
3759fb
3
LT3759
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, EN/UVLO = 12V, INTVCC = 4.75V, unless otherwise noted.
PARAMETER
LDO Dropout Voltage (V – V
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
)
V
= 3V, DRIVE = 0V,
190
400
mV
IN
IN
INTVcc
IN
I
= 20mA
INTVCC
INTV Undervoltage Lockout Threshold Falling
1.3
22
1.45
1.27
V
CC
INTV Current in Shutdown
EN/UVLO = 0V
μA
CC
Logic
l
EN/UVLO Threshold Voltage Falling
EN/UVLO Rising Hysteresis
EN/UVLO Input Low Voltage
EN/UVLO Pin Bias Current Low
EN/UVLO Pin Bias Current High
FBX Power Good Threshold Voltage
1.17
1.8
1.22
20
V
mV
V
I
< 1ꢀA
0.4
2.6
100
VIN
EN/UVLO = 1.15V
EN/UVLO = 1.30V
2.2
10
μA
nA
FBX > 0V, PGOOD Falling
FBX < 0V, PGOOD Falling
V
V
– 0.08
+ 0.04
V
V
FBX(REG)
FBX(REG)
FBX Overvoltage Threshold
FBX > 0V, PGOOD Rising
FBX < 0V, PGOOD Rising
V
+ 0.12
– 0.06
V
V
FBX(REG)
FBX(REG)
V
PGOOD Output Low (V
)
I
= 250μA
PGOOD
210
300
1
mV
μA
V
OL
PGOOD Leakage Current
INTV Minimum Voltage to Enable PGOOD Function
PGOOD = 42V
l
l
2.4
2.4
2.7
2.7
3.0
3.0
CC
INTV Minimum Voltage to Enable SYNC Function
V
CC
NMOS Gate Drivers
GATE Output Rise Time (T )
C = 3300pF
20
20
ns
ns
V
R
L
GATE Output Fall Time (T )
C = 3300pF
L
F
GATE Output Low (V
)
OL
0.05
GATE Output High (V
)
INTV – 0.05
V
OH
CC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
range are assured by design, characterization and correlation with
statistical process controls. The LT3759I is guaranteed over the full
–40°C to 125°C operating junction temperature range. The LT3759H is
guaranteed over the full –40°C to 150°C operating junction temperature
range. High junction temperatures degrade operating lifetimes. Operating
lifetime is derated at junction temperatures greater than 125°C.
Note 2: For V below 4V, the EN/UVLO pin must not exceed V for proper
IN
IN
operation.
Note 5: The LT3759 is tested in a feedback loop which servos V to the
reference voltages (1.6V and –0.8V) with the VC pin forced to 1.3V.
Note 6: Rise and fall times are measured at 10% and 90% levels.
FBX
Note 3: This pin is for switching purposes. Do not tie directly to a supply.
Note 4: The LT3759E is guaranteed to meet performance specifications
from the 0°C to 125°C operating junction temperature range.
Specifications over the –40°C to 125°C operating junction temperature
3759fb
4
LT3759
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
FBX Positive Regulation Voltage
vs Temperature
FBX Negative Regulation Voltage
vs Temperature
Quiescent Current
vs Temperature
–0.78
–0.79
–0.80
–0.81
–0.82
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.62
1.61
1.60
1.59
1.58
I
Q
(DRIVE)
V
= 12V
IN
DRIVE = 6V
I
(V )
IN
Q
0
25 50 75 100 125
25 50 75 100 125
150
–75 –50 –25
0
150
–75 –50 –25
25 50 75 100 125
150
–75 –50 –25
0
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3759 G02
3759 G03
3759 G01
Dynamic Quiescent Current
vs Switching Frequency
Normalized Switching Frequency
vs FBX Voltage
RT vs Switching Frequency
25
20
15
10
5
100
90
80
70
60
50
40
30
20
10
0
120
100
80
60
40
20
0
C
= 3300pF, DRIVE = 6V
L
I
Q
(DRIVE)
I
(V )
IN
Q
0
800
SWITCHING FREQUENCY (kHz)
100 200 300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
3759 G05
–0.4
0
0.4
0.8
FBX VOLTAGE (V)
1.6
0
200
400
600
1000
0
1.2
–0.8
3759 G04
3759 G06
Switching Frequency
vs Temperature
SENSE Current Limit Threshold
vs Temperature
SENSE Current Limit Threshold
vs Duty Cycle
350
325
300
275
250
53
52
51
50
49
48
47
53
52
51
50
49
48
47
R
T
= 27.4k
25 50 75 100 125
25 50 75 100 125
150
–75 –50 –25
0
150
–75 –50 –25
0
20
40
60
80
100
0
TEMPERATURE (°C)
TEMPERATURE (°C)
DUTY CYCLE (%)
3759 G07
3759 G08
3759 G09
3759fb
5
LT3759
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
EN/UVLO Threshold
vs Temperature
GATE Minimum On- and Off-Times
vs Temperature
EN/UVLO Hysteresis Current
vs Temperature
2.4
2.2
2.0
1.8
1.6
1.27
1.25
1.23
1.21
1.19
1.17
200
190
180
170
160
150
140
130
MINIMUM
OFF TIME
EN/UVLO RISING
EN/UVLO FALLING
MINIMUM
ON TIME
25 50 75 100 125
150
25 50 75 100 125
25 50 75 100 125
150
–75 –50 –25
0
–75 –50 –25
0
150
–75 –50 –25
0
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3759 G12
3759 G10
3759 G11
INTVCC vs Temperature
INTVCC Load Regulation
INTVCC Line Regulation
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
5.0
4.8
4.6
4.4
4.2
4.0
5.0
4.5
4.0
3.5
3.0
DRIVE LDO
DRIVE LDO
DRIVE LDO
V
IN
LDO
V
LDO (DRIVE = 0V)
IN
V
LDO
0
IN
3.8
3.6
5
10
15
20
25
15
35 40 45
25 50 75 100 125
0
5
10
20 25 30
(V)
–75 –50 –25
150
0
INTV LOAD (mA)
TEMPERATURE (°C)
V
IN
CC
3759 G14
3759 G13
3759 G15
INTVCC Dropout Voltage
vs Current, Temperature
Gate Driver Rise and Fall Time
vs CL
Gate Driver Rise and Fall Time
vs INTVCC
400
300
200
100
0
70
60
25
20
15
10
5
V
= 12V
INTV = 4.75V
CC
IN
C = 3300pF
L
RISE TIME
RISE TIME
DRIVE = 4V
50
40
30
20
FALL TIME
150°C
25°C
FALL TIME
–55°C
10
0
0
5
10
15
20
25
3
6
9
12
15
2.5
3
3.5
INTC (V)
4
4.5
5
0
0
2
INTV LOAD (mA)
C
(nF)
CC
L
CC
3759 G16
3759 G17
3759 G18
3759fb
6
LT3759
PIN FUNCTIONS
DRIVE: DRIVE LDO Supply Pin. This pin can be connected
PGOOD: Output Ready Status Pin. An open-collector pull
to either V or a quasi-regulated voltage supply such as
down on PGOOD asserts when INTV is greater than
IN
CC
a DC converter output. This pin must be bypassed with
2.7V and the FBX voltage is within 5% (80mV if V
1.6V or 40mV if V = –0.8V) of the regulation voltage.
=
FBX
a minimum of 1μF capacitor placed close to the pin. Tie
FBX
this pin to V if not used.
IN
RT: SwitchingFrequencyAdjustmentPin.Setthefrequency
using a resistor to GND. Do not leave the RT pin open.
EN/UVLO: Shutdown and Undervoltage Detect Pin. An
accurate 1.22V (nominal) falling threshold with externally
programmable hysteresis detects when power is okay to
enable switching. Rising hysteresis is generated by the
external resistor divider and an accurate internal 2.2ꢀA
pull-down current. An undervoltage condition resets soft-
start. Tie to 0.4V, or less, to disable the device and reduce
SENSE: The Current Sense Input for the Control Loop.
Kelvin connect this pin to the positive terminal of the
switch current sense resistor in the source of the N-FET.
The negative terminal of the current sense resistor should
be connected to GND plane close to the IC.
SS: Soft-Start Pin. This pin modulates compensation pin
voltage (VC) clamp. The soft-start interval is set with an
external capacitor. The pin has a 10μA (typical) pull-up
current source to an internal 2.5V rail. The soft-start pin
is reset to GND by an EN/UVLO undervoltage condition,
V quiescent current below 1ꢀA.
IN
FBX: Voltage Regulation Feedback Pin for Positive or
Negative Outputs. Connect this pin to a resistor divider
between the output and GND. FBX is the input of two error
amplifiers—one configured to regulate a positive output;
the other, a negative output. Depending upon topology
selected, switching causes the output to ramp positive or
negative. The appropriate amplifier takes control while the
other becomes inactive. Additionally FBX is input for two
window comparators that indicate through the PGOOD
pin when the output is within 5% of the regulation volt-
ages. FBX also modulates the switching frequency during
start-up and fault conditions when FBX is close to GND.
an INTV undervoltage condition or an internal thermal
CC
lockout.
SYNC:FrequencySynchronizationPin.Usedtosynchronize
the internal oscillator to an outside clock. If this feature is
used,anR resistorshouldbechosentoprogramaswitch-
T
ing frequency 20% slower than SYNC pulse frequency.
Tie the SYNC pin to GND if this feature is not used. This
signal is ignored during FB frequency foldback or when
INTV is less than 2.7V.
CC
GATE: N-Channel FET Gate Driver Output. Switches
VC: Error Amplifier Compensation Pin. Used to stabilize
the voltage loop with an external RC network.
between INTV and GND. Driven to GND when IC is shut
CC
down, during thermal lockout or when INTV is below
CC
undervoltage threshold.
V : Supply Pin for Internal Leads and the V LDO
IN
IN
Regulator of INTV . Must be locally bypassed with a
GND: Exposed Pad. Solder the exposed pad directly to
ground plane.
CC
minimum of 1μF capacitor placed close to this pin.
INTV : Regulated Supply for Internal Loads and Gate
CC
Driver. Regulated to 4.75V if powered from DRIVE or
regulated to 3.75V if powered from V . The INTV pin
IN
CC
must be bypassed with a minimum of 4.7μF capacitor
placed close to the pin.
3759fb
7
LT3759
BLOCK DIAGRAM
L1
C
DC
L2
D1
V
OUT
V
IN
+
R4
R3
C
IN
R2
R1
C
OUT1
+
t
FBX
C
OUT2
12
11
10
DRIVE
EN/UVLO
V
IN
A10
+
I
S1
2.5V
2μA
1.22V
–
2.5V
BANDGAP
REFERENCE
I
S3
CURRENT
LIMIT
CURRENT
LIMIT
I
INTERNAL BIAS
GENERATOR
S2
BG
VC
10μA
BG_LOW
UVLO
1
V
LDO
DRIVE LDO
IN
Q3
INTERNAL BIAS
INTV
C
VCC
C
C2
CC
G4
9
8
R
C
A8
+
C
C1
1.2V
A11
1.72V
–
+
TSD
~165˚C
–
G6
SR1
S
A12
V
–
GATE
C
DRIVER
–
+
G2
A7
R
Q
G5
M1
+
–0.86V
Q2
PWM
1.6V
+
–
COMPARATOR
50mV
–
+
A1
A6
FBX
SLOPE
V
ISENSE
2
6
FBX
SENSE
GND
+
–
RAMP
7
+
–
A2
A5
–0.8V
R
SENSE
RAMP
GENERATOR
PGOOD
13
Q4
G8
A15
+
2.7V
100kHz ~ 1MHz
OSCILLATOR
–
A13
A14
1.52V
–
+
–
+
G7
1.25V
A3
G1
–
+
–0.76V
FREQ
FOLDBACK
1.25V
+
+
FREQUENCY
FOLDBACK
A4
Q1
–
FREQ
PROG
SS
SYNC
RT
3
5
4
3759 F01
C
SS
R
T
Figure 1. LT3759 Block Diagram Working as a SEPIC Converter
3759fb
8
LT3759
APPLICATIONS INFORMATION
Main Control Loop
An overvoltage comparator A11 (with 40mV hysteresis)
senses when the FBX pin voltage exceeds the positive
regulated voltage (1.6V) by 7.5% and turns off M1.
Similarly, an overvoltage comparator A12 (with 20mV
hysteresis) senses when the FBX pin voltage exceeds the
negative regulated voltage (–0.8V) by 7.5% and turns
off M1. Both reset pulses are sent to the main RS latch
(SR1) through G6 and G5. The external power MOSFET
switch M1 is actively held off for the duration of an output
overvoltage condition.
The LT3759 uses a fixed frequency, current mode control
scheme to provide excellent line and load regulation.
OperationcanbebestunderstoodbyreferringtotheBlock
Diagram in Figure 1.
ThestartofeachoscillatorcyclesetstheSRlatch(SR1)and
turns on the external power MOSFET switch M1 through
driver G2. The switch current flows through the external
current sensing resistor R
and generates a voltage
SENSE
proportional to the switch current. This current sense
voltage V (amplified by A5) is added to a stabilizing
Programming Turn-On and Turn-Off Thresholds with
EN/UVLO Pin
ISENSE
slope compensation ramp and the resulting sum (SLOPE)
isfedintothepositiveterminalofthePWMcomparatorA7.
When SLOPE exceeds the level at the negative input of A7
(VC pin), SR1 is reset, turning off the power switch. The
level at the negative input of A7 is set by the error amplifier
A1 (or A2) and is an amplified version of the difference
between the feedback voltage (FBX pin) and the reference
voltage (1.6V or –0.8V, depending on the configuration).
In this manner, the error amplifier sets the correct peak
switch current level to keep the output in regulation.
The EN/UVLO pin controls whether the LT3759 is enabled
or is in shutdown state. A micropower 1.22V reference, a
comparator A10 and controllable current source I allow
S1
theusertoaccuratelyprogramthesupplyvoltageatwhich
the IC turns on and off. The falling value can be accurately
set by the resistor dividers R3 and R4. When EN/UVLO
is above 0.7V, and below the 1.22V threshold, the small
pull-down current source I (typical 2μA) is active.
S1
The purpose of this current is to allow the user to program
therisinghysteresis.TheBlockDiagramofthecomparator
and the external resistors is shown in Figure 1. The typical
falling threshold voltage and rising threshold voltage can
be calculated by the following equations:
TheLT3759hasaswitchcurrentlimitfunction.Thecurrent
sense voltage is input to the current limit comparator A6.
If the SENSE pin voltage is higher than the sense current
SENSE(MAX)
SR1 and turn off M1 immediately.
limit threshold V
(50mV, typical), A6 will reset
(R3+R4)
The LT3759 is capable of generating either positive or nega-
tiveoutputvoltagewithasingleFBXpin.Itcanbeconfigured
as a boost or SEPIC converter to generate positive output
voltage, or as an inverting converter to generate negative
output voltage. When configured as a SEPIC converter, as
showninFigure1,theFBXpinispulleduptotheinternalbias
voltage of 1.6V by a voltage divider (R1 and R2) connected
VVIN(FALLING) = 1.22 •
R4
VVIN(RISING) = 2μA • R3+ V
IN(FALLING)
For applications where the EN/UVLO pin is only used as
a logic input, the EN/UVLO pin can be connected directly
to the input voltage V for always-on operation.
IN
from V
to GND. Comparator A2 becomes inactive and
OUT
comparator A1 performs the inverting amplification from
FBXtoVC.WhentheLT3759isinaninvertingconfiguration,
the FBX pin is pulled down to –0.8V by a voltage divider
INTV Low Dropout Voltage Regulators
CC
The LT3759 features two internal low dropout (LDO) volt-
age regulators (V LDO and DRIVE LDO) powered from
IN
connected from V
to GND. Comparator A1 becomes
OUT
differentsupplies(V andDRIVErespectively).BothLDO’s
IN
inactive and comparator A2 performs the noninverting
amplification from FBX to VC.
regulate the internal INTV supply which powers the gate
CC
driver and the internal loads, as shown in Figure 1. Both
TheLT3759hasovervoltageprotectionfunctionstoprotect
the converter from excessive output voltage overshoot
during start-up or recovery from a short-circuit condition.
regulatorsaredesignedsothatcurrentdoesnotflowfrom
INTV to the LDO input under a reverse bias condition.
CC
DRIVE LDO regulates the INTV to 4.75V, while V LDO
CC
IN
3759fb
9
LT3759
APPLICATIONS INFORMATION
regulates the INTV to 3.75V. V LDO is turned off when
cern when a large power MOSFET is being driven at a
CC
IN
the INTV voltage is greater than 3.75V (typical). Both
high frequency and the V voltage is high. It is important
CC
IN
LDO’s can be turned off if the INTV pin is driven by a
to limit the power dissipation with proper selection of a
MOSFET and/or an operating frequency so the LT3759
doesnotexceeditsmaximumjunctiontemperaturerating.
CC
supply of 4.75V or higher but less than 8V (the INTV
CC
maximum voltage rating is 8V). A table of the LDO sup-
ply and output voltage combination is shown in Table 1.
The junction temperature T can be estimated using the
J
following equations:
Table 1. LDO’s Supply and Output Voltage Combination (Assuming
That the LDO Dropout Voltage is 0.15V)
TJ = TA +P • θJA
IC
SUPPLY VOLTAGES
DRIVE
LDO OUTPUT
INTV
LDO STATUS
(Note 7)
V
IN
CC
T = ambient temperature
A
V
≤ 3.9V
V
V
< V
= V
V
V
– 0.15V
– 0.15V
#1 Is ON
#1 #2 are ON
#2 Is ON
IN
DRIVE
DRIVE
IN
IN
IN
IN
θ
= junction-to-ambient thermal resistance
JA
P = IC power consumption = V • (I + I )
DRIVE
V
< V
< 4.9V
V
– 0.15V
DRIVE
IN
DRIVE
IC
IN
Q
4.9V ≤ V
≤ 42V
4.75V
#2 Is ON
DRIVE
(Assume the DRIVE pin is connected to V Supply)
IN
3.9V < V ≤ 42V
V
DRIVE
V
DRIVE
< 3.9V
3.75V
3.75V
#1 Is ON
IN
I = V operation I = 1.8mA
Q
IN
Q
= 3.9V
< 4.9V
#1 #2 are ON
#2 Is ON
3.9V < V
V
– 0.15V
DRIVE
I
= average gate drive current = f • Q
G
DRIVE
DRIVE
4.9V ≤ V
≤ 42V
4.75V
#2 Is ON
DRIVE
f = switching frequency
Q = power MOSFET total gate charge
Note 7: #1 is V LDO and #2 is DRIVE LDO
IN
G
The DRIVE pin provides flexibility to power the gate driver
and the internal loads from a supply that is available only
when the switcher is enabled and running. If not used, the
The LT3759 uses packages with an exposed pad for en-
hanced thermal conduction. With proper soldering to the
exposed pad on the underside of the package and a full
copper plane underneath the device, thermal resistance
DRIVE pin should be tied to V .
IN
(θ ) will be about 40°C/W for the MSE package.
JA
The INTV pin must be bypassed to ground immediately
CC
adjacenttotheINTV pinwithaminimumof4.7μFceramic
The LT3759 has an internal INTV
I
current limit
CC
CC DRIVE
capacitor. Good bypassing is necessary to supply the high
function to protect the IC from excessive on-chip power
dissipation. If I reaches the current limit, INTV
transient currents required by the MOSFET gate driver.
DRIVE
CC
voltage will fall and may trigger the soft-start.
If a low input voltage operation is expected (V is 3V or
IN
less),lowthresholdMOSFETsshouldbeused.TheLT3759
contains an undervoltage lockout comparator A8 for the
internal INTV supply. The INTV undervoltage (UV)
There is a trade-off between the operating frequency and
the size of the power MOSFET (Q ) in order to maintain
G
a reliable IC junction temperature. Prior to lowering the
operating frequency, however, be sure to check with
power MOSFET manufacturers for their most recent low
CC
CC
threshold is 1.3V (typical), with 100mV hysteresis, to
ensurethattheMOSFETshavesufficientgatedrivevoltage
before turning on. The logic circuitry within the LT3759
Q , low R
devices. Power MOSFET manufacturing
G
DS(ON)
is also powered from the internal INTV supply. When
technologies are continually improving, with newer and
CC
INTV is below the UV threshold, the GATE pin will be
betterperformancedevicesbeingintroducedalmostyearly.
CC
forcedtoGNDandthesoft-startoperationwillbetriggered.
Operating Frequency and Synchronization
In an actual application, most of the IC supply current is
used to drive the gate capacitance of the power MOSFET.
The on-chip power dissipation can be a significant con-
The choice of operating frequency may be determined
by on-chip power dissipation, otherwise it is a trade-off
between efficiency and component size. Low frequency
3759fb
10
LT3759
APPLICATIONS INFORMATION
operation improves efficiency by reducing gate drive cur-
rent and MOSFET and diode switching losses. However,
lowerfrequencyoperationrequiresaphysicallylargerloop
inductor. Switching frequency also has implications for
loopcompensation.TheLT3759usesaconstant-frequency
architecture that can be programmed over a 100kHz to
1MHz range with a single external resistor from the RT pin
to ground, as shown in Figure 1. The RT pin must have
an external resistor to GND for proper operation of the
The minimum on-time and minimum off-time and the
switching frequency define the minimum and maximum
switching duty cycles a converter is able to generate:
Minimum duty cycle = minimum on-time • frequency
Maximum duty cycle = 1 – (minimum off-time • frequency)
Programming the Output Voltage
The output voltage (V ) is set by a resistor divider, as
OUT
shown in Figure 1. The positive V
are set by the following equations:
and negative V
OUT
OUT
LT3759. A table for selecting the value of R for a given
T
operating frequency is shown in Table 2.
Table 2. Timing Resistor (RT) Value
⎛
⎞
⎟
⎠
R2
R1
VOUT(POSITIVE) = 1.6V • 1+
⎜
OSCILLATOR FREQUENCY (kHz)
R (kΩ)
T
⎝
⎛
100
200
300
400
500
600
700
800
900
1000
86.6
41.2
27.4
21.0
16.5
13.7
11.5
9.76
8.45
6.81
⎞
⎟
⎠
R2
R1
VOUT(NEGATIVE) = –0.8V • 1+
⎜
⎝
The resistors R1 and R2 are typically chosen so that the
error caused by the current flowing into the FBX pin dur-
ing normal operation is less than 1% (this translates to a
maximum value of R1 at about 158k).
Soft-Start
The LT3759 contains several features to limit peak switch
currents and output voltage (V ) overshoot during
OUT
TheswitchingfrequencyoftheLT3759canbesynchronized
to the positive edge of an external clock source. By provid-
ing a digital clock signal into the SYNC pin, the LT3759 will
operateattheSYNCclockfrequency.Ifthisfeatureisused,
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
High peak switch currents during start-up may occur in
an R resistor should be chosen to program a switching
T
switching regulators. Since V
is far from its final value,
OUT
frequency 20% slower than SYNC pulse frequency. The
SYNCpulseshouldhaveaminimumpulsewidthof200ns.
Tie the SYNC pin to GND if this feature is not used.
the feedback loop is saturated and the regulator tries to
chargetheoutputcapacitorasquicklyaspossible,resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.
Duty Cycle Consideration
Switching duty cycle is a key variable defining converter
operation.Assuch,itslimitsmustbeconsidered.Minimum
on-time is the smallest time duration that the LT3759 is
capable of turning on the power MOSFET. This time is
generally about 170ns (typical) (see Minimum On-Time
in the Electrical Characteristics table). In each switching
cycle, the LT3759 keeps the power switch off for at least
170ns (typical) (see Minimum Off-Time in the Electrical
Characteristics table).
LT3759 addresses this mechanism with the SS pin. As
shown in Figure 1, the SS pin reduces the power MOSFET
current by pulling down the VC pin through Q2. In this
waytheSSallowstheoutputcapacitortochargegradually
toward its final value while limiting the start-up peak
currents.
3759fb
11
LT3759
APPLICATIONS INFORMATION
Besides start-up, soft-start can also be triggered by
Loop Compensation
INTV undervoltagelockoutand/orthermallockout,which
CC
Loop compensation determines the stability and transient
performance. The LT3759 uses current mode control to
regulate the output which simplifies loop compensation.
Theoptimumvaluesdependontheconvertertopology,the
componentvaluesandtheoperatingconditions(including
the input voltage, load current, etc.). To compensate the
feedback loop of the LT3759, a series resistor-capacitor
network is usually connected from the VC pin to GND.
Figure 1 shows the typical VC compensation network. For
most applications, the capacitor should be in the range of
470pF to 22nF, and the resistor should be in the range of
5k to 50k. A small capacitor is often connected in paral-
lel with the RC compensation network to attenuate the
VC voltage ripple induced from the output voltage ripple
through the internal error amplifier. The parallel capacitor
usually ranges in value from 10pF to 100pF. A practical
approach to design the compensation network is to start
with one of the circuits in this data sheet that is similar
to your application, and tune the compensation network
to optimize the performance. Stability should then be
checked across all operating conditions, including load
current, input voltage and temperature.
causes the LT3759 to stop switching immediately. The SS
pin will be discharged by Q3. When all faults are cleared
and the SS pin has been discharged below 0.2V, a 10μA
current source I starts charging the SS pin, initiating a
S2
soft-start operation.
The soft-start interval is set by the soft-start capacitor
selection according to the equation:
1.25V
10μA
TSS = CSS
•
FBX Frequency Foldback
When V is very low during start-up or a short-circuit
OUT
fault on the output, the switching regulator must operate
at low duty cycles to maintain the power switch current
within the current limit range, since the inductor current
decayrateisverylowduringswitchofftime.Theminimum
on-timelimitationmaypreventtheswitcherfromattaining
a sufficiently low duty cycle at the programmed switch-
ing frequency. So, the switch current will keep increasing
through each switch cycle, exceeding the programmed
current limit. To prevent the switch peak currents from
exceeding the programmed value, the LT3759 contains
a frequency foldback function to reduce the switching
frequency when the FBX voltage is low (see the Normal-
ized Switching Frequency vs FBX graph in the Typical
Performance Characteristics section).
SENSE Pin Programming
For control and protection, the LT3759 measures the
powerMOSFETcurrentbyusingasenseresistor(R
)
SENSE
between GND and the MOSFET source. Figure 2 shows a
typicalwave-formofthesensevoltage(V )acrossthe
SENSE
sense resistor. It is important to use Kelvin traces between
Some frequency foldback waveforms are shown in the
TypicalApplicationssection.Thefrequencyfoldbackfunc-
the SENSE pin and R
close as possible to the GND terminal of the R
proper operation.
, and to place the IC GND as
SENSE
for
SENSE
tion prevents I from exceeding the programmed limits
L
because of the minimum on-time.
Duringfrequencyfoldback,externalclocksynchronization
is disabled to allow the frequency reducing operation to
function properly.
V
SENSE
χ
• V
SENSE(MAX)
ΔV
=
SENSE
V
V
SENSE(PEAK)
SENSE(MAX)
Thermal Lockout
t
DT
S
If the LT3759 die temperature reaches 165°C (typical),
the part will go into thermal lockout. The power switch
will be turned off. A soft-start operation will be triggered.
The part will be enabled again when the die temperature
has dropped by 5°C (nominal).
T
S
3759 F02
Figure 2. The Sense Voltage During a Switching Cycle
3759fb
12
LT3759
APPLICATIONS INFORMATION
Due to the current limit function of the SENSE pin, R
shouldbeselectedtoguaranteethatthepeakcurrentsense
trace, the sense resistor, the diode, and the MOSFET. The
100ns timing interval is adequate for most of the LT3759
applications. In the applications that have very large and
long ringing on the current sense signal, a small RC filter
can be added to filter out the excess ringing. Figure 4
shows the RC filter on SENSE pin. It is usually sufficient
SENSE
voltage V
during steady state normal opera-
SENSE(PEAK)
tion is lower than the SENSE current limit threshold (see
the Electrical Characteristics table). Given a 20% margin,
V
issettobe40mV.Then,themaximumswitch
SENSE(PEAK)
ripple current percentage can be calculated using the fol-
to choose 22Ω for R and 2.2nF to 10nF for C . Keep
FLT
FLT
lowing equation:
R
resistance low. Remember that there is 50μA (typi-
FLT’s
cal) flowing out of the SENSE pin. Adding R will affect
FLT
DVSENSE
40mV - 0.5• DVSENSE
the SENSE current limit threshold:
c =
VSENSE _ILIM = 50mV −50μA •RFLT
χ
is used in subsequent design examples to calculate
inductorvalue.ΔV istheripplevoltageacrossR
.
SENSE
SENSE
The LT3759 has internal slope compensation to stabilize
the control loop against sub-harmonic oscillation. When
the LT3759 operates at a high duty cycle in continuous
M
1
GATE
LT3759
GND
R
FLT
SENSE
conduction mode, the SENSE voltage ripple ΔV
(re-
SENSE
C
FLT
fer to Figure 2) needs to be limited to ensure the internal
slope compensation is sufficient to stabilize the control
R
SENSE
loop. Figure 3 shows the maximum allowed ΔV
over
3759 F04
SENSE
the duty cycle. It is recommended to check and ensure
Figure 4. The RC Filter on SENSE pin
ΔV
is below the curve at the highest duty cycle.
SENSE
60
50
40
30
20
10
0
APPLICATION CIRCUITS
The LT3759 can be configured as different topologies.
The design procedure for component selection differs
somewhat between these topologies. The first topology
to be analyzed will be the boost converter, followed by the
flyback SEPIC and inverting converters.
Boost Converter: Switch Duty Cycle and Frequency
The LT3759 can be configured as a boost converter for
the applications where the converter output voltage is
higher than the input voltage. Remember that boost con-
verters are not short-circuit protected. Under a shorted
output condition, the inductor current is limited only by
the input supply capability. For applications requiring a
step-up converter that is short-circuit protected, please
refer to the Applications Information section covering
SEPIC converters.
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY CYCLE
1
3759 F03
Figure 3. The Maximum Allowed SENSE Voltage Ripple vs
Duty Cycle
TheLT3759switchingcontrollerincorporates100nstiming
interval to blank the ringing on the current sense signal
immediately after M1 is turned on. This ringing is caused
by the parasitic inductance and capacitance of the PCB
3759fb
13
LT3759
APPLICATIONS INFORMATION
The selection of switching frequency is the starting point.
The maximum frequency that can be used is based on the
maximum duty cycle. The conversion ratio as a function
of duty cycle is:
converter will approach voltage mode). Accepting larger
values of ΔI provides fast transient response and allows
L
the use of low inductances, but results in higher input
current ripple and greater core losses. It is recommended
χ
that falls within the range of 0.2 to 0.6.
VOUT
V
IN
1
1−D
=
The peak and RMS inductor current are:
⎛
⎝
⎞
⎟
⎠
χ
2
IL(PEAK) = IL(MAX) • 1+
⎜
in continuous conduction mode (CCM). The equations
that follow assume CCM operation.
χ2
12
For a boost converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
IL(RMS) = IL(MAX) • 1+
voltage (V ) and the input voltage (V ). The maximum
OUT
duty cycle (D
minimum input voltage:
IN
TheinductorusedwiththeLT3759shouldhaveasaturation
current rating appropriate to the maximum switch current
) occurs when the converter has the
MAX
selectedwiththeR
resistor.Chooseaninductorvalue
SENSE
VOUT − V
based on operating frequency, input and output voltage
to provide a current mode ramp on SENSE during the
switch on-time of approximately 10mV magnitude. The
following equation is useful to estimate the inductor value
for continuous conduction mode operation:
IN(MIN)
DMAX
=
VOUT
The alternative to CCM, discontinuous conduction mode
(DCM) is not limited by duty cycle to provide high con-
version ratios at a given frequency. The price one pays
is reduced efficiency and substantially higher switching
current.
RSENSE • V
L =
IN(MIN) • DMAX
0.01V • fOSC
Boost Converter: Inductor and Sense Resistor Selection
Set the sense voltage at I
SENSE current limit threshold with a 20% margin. The
sense resistor value can then be calculated to be:
to be the minimum of the
L(PEAK)
For the boost topology, the maximum average inductor
current is:
40mV
IL(PEAK)
1
RSENSE
=
IL(MAX) = IO(MAX)
•
1−DMAX
Then, the ripple current can be calculated by:
Boost Converter: Power MOSFET Selection
1
DIL = c •IL(MAX) = c •IO(MAX)
•
Important parameters for the power MOSFET include the
1-DMAX
drain-source voltage rating (V ), the threshold voltage
DS
(V
), the on-resistance (R
), the gate to source
GD
GS(TH)
DS(ON)
χ
The constant in the preceding equation represents the
percentage peak-to-peak ripple current in the inductor,
and gate to drain charges (Q and Q ), the maximum
GS
drain current (I
tances (R and R ).
) and the MOSFET’s thermal resis-
D(MAX)
relative to I
.
L(MAX)
θJC
θJA
Theinductorripplecurrenthasadirecteffectonthechoice
The power MOSFET will see full output voltage, plus a
diode forward voltage, and any additional ringing across
its drain-to-source during its off-time. It is recommended
of inductor value. Choosing smaller values of ΔI requires
L
large inductances and reduces the current loop gain (the
3759fb
14
LT3759
APPLICATIONS INFORMATION
to choose a MOSFET whose BV
is higher than V
It is recommended that the peak repetitive reverse voltage
DSS
OUT
by a safety margin (a 10V safety margin is usually
rating V
is higher than V
by a safety margin (a 10V
RRM
OUT
sufficient).
safety margin is usually sufficient).
The power dissipated by the MOSFET in a boost
The power dissipated by the diode is:
converter is:
D
PD = IO(MAX) • VD
P
FET = I2L(MAX) •RDS(ON)
•
MAX
and the diode junction temperature is:
f
1A
+V2
•
C
IL(MAX) •
RSS
•
OUT
TJ
T P R
• •
A D θJA
=
The first term in the preceding equation represents the
conductionlossesinthedevices, andthesecondterm, the
The R to be used in this equation normally includes the
θJC
θJA
R
for the device plus the thermal resistance from the
switching loss. C
is the reverse transfer capacitance,
RSS
boardtotheambienttemperatureintheenclosure.T must
J
which is usually specified in the MOSFET characteristics.
notexceedthediodemaximumjunctiontemperaturerating.
For maximum efficiency, R and C should be
DS(ON)
RSS
Boost Converter: Output Capacitor Selection
minimized. From a known power dissipated in the power
MOSFET, its junction temperature can be obtained using
the following equation:
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct output
capacitors for a given output ripple voltage. The effect of
thesethreeparameters(ESR,ESLandbulkC)ontheoutput
voltage ripple waveform for a typical boost converter is
illustrated in Figure 5.
TJ
T
P θ
•
FET JA
=
•
A
= TA +PFET •(θJC +θCA)
T must not exceed the MOSFET maximum junction
J
temperature rating. It is recommended to measure the
MOSFETtemperatureinsteadystatetoensurethatabsolute
maximum ratings are not exceeded.
The choice of component(s) begins with the maximum
t
t
OFF
ON
)V
COUT
Boost Converter: Output Diode Selection
V
OUT
(AC)
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desirable. The
peak reverse voltage that the diode must withstand is
equal to the regulator output voltage plus any additional
ringing across its anode-to-cathode during the on-time.
The average forward current in normal operation is equal
to the output current, and the peak current is equal to:
)V
ESR
3759 F05
Figure 5. The Output Ripple Waveform of a Boost Converter
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step ΔV
and charging/discharging
⎛
⎞
χ
ESR
ID(PEAK) = IL(PEAK) = 1+ •I
⎜
⎟
L(MAX)
ΔV
. For the purpose of simplicity, we will choose
COUT
⎝
⎠
2
2% for the maximum output ripple, to be divided equally
between ΔV
and ΔV
. This percentage ripple will
ESR
COUT
3759fb
15
LT3759
APPLICATIONS INFORMATION
FLYBACK CONVERTER APPLICATIONS
change, depending on the requirements of the applica-
tion, and the following equations can easily be modified.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the fol-
lowing equation:
TheLT3759canbeconfiguredasaflybackconverterforthe
applications where the converters have multiple outputs,
high output voltages or isolated outputs. Figure 6 shows
a simplified flyback converter.
0.01• VOUT
ID(PEAK)
The flyback converter has a very low parts count for mul-
tipleoutputs, andwithprudentselectionofturnsratio, can
have high output/input voltage conversion ratios with a
desirable duty cycle. However, it has low efficiency due to
thehighpeakcurrents,highpeakvoltagesandconsequent
power loss. The flyback converter is commonly used for
an output power of less than 50W.
ESRCOUT
≤
For the bulk C component, which also contributes 1% to
the total ripple:
IO(MAX)
COUT
≥
0.01• VOUT • f
The flyback converter can be designed to operate either
in continuous or discontinuous mode. Compared to con-
tinuous mode, discontinuous mode has the advantage of
smaller transformer inductances and easy loop compen-
sation, and the disadvantage of higher peak-to-average
current and lower efficiency. In the high output voltage
applications, the flyback converters can be designed
to operate in discontinuous mode to avoid using large
transformers.
Theoutputcapacitorinaboostregulatorexperienceshigh
RMSripplecurrents, asshowninFigure5. TheRMSripple
current rating of the output capacitor can be determined
using the following equation:
DMAX
1−DMAX
IRMS(COUT) ≥IO(MAX)
•
Multiple capacitors are often paralleled to meet ESR
requirements. Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering and has
therequiredRMScurrentrating.Additionalceramiccapaci-
tors in parallel are commonly used to reduce the effect of
parasiticinductanceintheoutputcapacitor,whichreduces
high frequency switching noise on the converter output.
SUGGESTED
D
RCD SNUBBER
N :N
P
S
V
IN
–
SN
+
+
+
+
V
C
I
D
C
R
IN
SN
SN
C
L
L
S
OUT
P
–
D
SN
I
SW
Boost Converter: Input Capacitor Selection
LT3759
GATE
+
V
–
M
R
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input, and the input current wave-
form is continuous. The input voltage source impedance
determines the size of the input capacitor, which is typi-
cally in the range of 10μF to 100μF. A low ESR capacitor
is recommended, although it is not as critical as for the
output capacitor.
DS
SENSE
SENSE
GND
3759 F06
Figure 6. A Simplified Flyback Converter
The RMS input capacitor ripple current for a boost
converter is:
IRMS(CIN) = 0.3• DIL
3759fb
16
LT3759
APPLICATIONS INFORMATION
Flyback Converter: Switch Duty Cycle and Turns Ratio
Accordingtotheprecedingequations,theuserhasrelative
freedom in selecting the switch duty cycle or turns ratio to
suit a given application. The selections of the duty cycle
and the turns ratio are somewhat iterative processes, due
to the number of variables involved. The user can choose
either a duty cycle or a turns ratio as the start point. The
following trade-offs should be considered when select-
ing the switch duty cycle or turns ratio, to optimize the
converter performance. A higher duty cycle affects the
flyback converter in the following aspects:
The flyback converter conversion ratio in the continuous
mode operation is:
VOUT NS
D
=
•
V
NP 1−D
IN
where N /N is the second to primary turns ratio.
S
P
Figure 7 shows the waveforms of the flyback converter
in discontinuous mode operation. During each switching
period T , three subintervals occur: DT , D2T , D3T .
• Lower MOSFET RMS current I
, but higher
SW(RMS)
S
S
S
S
During DT , M is on, and D is reverse-biased. During
MOSFET V peak voltage
S
DS
D2T , M is off, and L is conducting current. Both L and
S
S
P
• Lower diode peak reverse voltage, but higher diode
RMS current I
L currents are zero during D3T .
S
S
D(RMS)
The flyback converter conversion ratio in the discontinu-
ous mode operation is:
• Higher transformer turns ratio (N /N )
P
S
The choice,
VOUT NS
D
=
•
D
D+D2
1
3
V
IN
NP D2
=
(for discontinuous mode operation with a given D3) gives
the power MOSFET the lowest power stress (the product
of RMS current and peak voltage). However, in the high
output voltage applications, a higher duty cycle may be
adopted to limit the large peak reverse voltage of the
diode. The choice,
V
DS
I
SW
D
D+D2
2
3
=
I
SW(MAX)
(for discontinuous mode operation with a given D3) gives
the diode the lowest power stress (the product of RMS
current and peak voltage). An extreme high or low duty
cycleresultsinhighpowerstressontheMOSFETordiode,
and reduces efficiency. It is recommended to choose a
duty cycle, D, between 20% and 80%.
I
D
I
D(MAX)
DT
D2T
D3T
S
t
S
S
T
S
3759 F07
Figure 7. Waveforms of the Flyback Converter in
Discontinuous Mode Operation
3759fb
17
LT3759
APPLICATIONS INFORMATION
Flyback Converter: Transformer Design for
Discontinuous Mode Operation
The primary and second inductor values of the flyback
converter transformer can be determined using the fol-
lowing equations:
Thetransformerdesignfordiscontinuousmodeofopera-
tion is chosen as presented here. According to Figure 7,
D2MAX • V2IN(MIN) • η
LP =
the minimum D3 (D3 ) occurs when the converter
MIN
2 •POUT(MAX) • f
OSC
has the minimum V and the maximum output power
IN
MIN
(P ). Choose D3
to be equal to or higher than 10%
OUT
D22 •(VOUT + VD)
to guarantee the converter is always in discontinuous
modeoperation(choosinghigherD3allowstheuseoflow
inductances, but results in a higher switch peak current).
LS =
2 •IOUT(MAX) • f
OSC
The primary to second turns ratio is:
The user can choose a D
as the start point. Then, the
MAX
NP
NS
LP
LS
maximum average primary currents can be calculated by
the following equation:
=
POUT(MAX)
ILP(MAX) =ISW(MAX)
=
Flyback Converter: Snubber Design
DMAX • VIN(MIN) • η
Transformer leakage inductance (on either the primary or
secondary) causes a voltage spike to occur after the MOS-
FET turn-off. This is increasingly prominent at higher load
currents, where more stored energy must be dissipated.
In some cases a snubber circuit will be required to avoid
overvoltagebreakdownattheMOSFET’sdrainnode.There
are different snubber circuits, and Application Note 19 is
a good reference on snubber design. An RCD snubber is
shown in Figure 6.
where η is the converter efficiency.
If the flyback converter has multiple outputs, P
is the sum of all the output power.
OUT(MAX)
The maximum average secondary current is:
IOUT(MAX)
ILS(MAX) =ID(MAX)
=
D2
where:
D2 = 1 – D
– D3
The snubber resistor value (R ) can be calculated by the
MAX
SN
following equation:
the primary and secondary RMS currents are:
NP
NS
DMAX
V2SN − VSN • VOUT
•
ILP(RMS) = 2 •ILP(MAX)
•
•
RSN = 2 •
3
I2SW(PEAK) •LLK • f
OSC
D2
3
ILS(RMS) = 2 •ILS(MAX)
where V is the snubber capacitor voltage. A smaller
SN
V
results in a larger snubber loss. A reasonable V is
SN
SN
According to Figure 7, the primary and secondary peak
currents are:
2 to 2.5 times of:
VOUT •NP
NS
I
I
= I
= I
= 2 • I
SW(PEAK) LP(MAX)
LP(PEAK)
LS(PEAK)
= 2 • I
D(PEAK)
LS(MAX)
3759fb
18
LT3759
APPLICATIONS INFORMATION
L istheleakageinductanceoftheprimarywinding,which
The first term in this equation represents the conduction
losses in the device, and the second term, the switching
LK
is usually specified in the transformer characteristics. L
LK
canbeobtainedbymeasuringtheprimaryinductancewith
loss. C
is the reverse transfer capacitance, which is
RSS
the secondary windings shorted. The snubber capacitor
usually specified in the MOSFET characteristics.
value(C )canbedeterminedusingthefollowingequation:
CN
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
equation:
VSN
CCN
=
ΔVSN •RCN • fOSC
T = T + P • θ = T + P • (θ + θ )
J
A
FET
JA
A
FET
JC
CA
where ΔV is the voltage ripple across C . A reasonable
SN
CN
T must not exceed the MOSFET maximum junction
ΔV is 5% to 10% of V . The reverse voltage rating of
J
SN
SN
temperature rating. It is recommended to measure the
MOSFETtemperatureinsteadystatetoensurethatabsolute
maximum ratings are not exceeded.
D
should be higher than the sum of V and V
.
SN
SN
IN(MAX)
Flyback Converter: Sense Resistor Selection
In a flyback converter, when the power switch is turned
on, the current flowing through the sense resistor
SENSE
Flyback Converter: Output Diode Selection
The output diode in a flyback converter is subject to large
RMS current and peak reverse voltage stresses. A fast
switching diode with a low forward drop and a low reverse
leakage is desired. Schottky diodes are recommended if
the output voltage is below 100V.
(I
) is:
I
= I
LP
SENSE
Set the sense voltage at I
to be the minimum of
LP(PEAK)
the SENSE current limit threshold with a 20% margin. The
sense resistor value can then be calculated to be:
Approximate the required peak repetitive reverse voltage
40mV
ILP(PEAK)
rating V
using:
RRM
RSENSE
=
NS
VRRM
>
• VIN(MAX) + VOUT
NP
The power dissipated by the diode is:
P = I • V
Flyback Converter: Power MOSFET Selection
Fortheflybackconfiguration, theMOSFETisselectedwith
a V rating high enough to handle the maximum V , the
D
O(MAX)
D
DC
IN
reflected secondary voltage and the voltage spike due to
and the diode junction temperature is:
T = T + P • R
theleakageinductance.ApproximatetherequiredMOSFET
J
A
D
θJA
V
rating using:
DC
The R to be used in this equation normally includes the
θJC
θJA
BV
> V
DS(PEAK)
DSS
R
for the device, plus the thermal resistance from the
where:
boardtotheambienttemperatureintheenclosure.T must
J
notexceedthediodemaximumjunctiontemperaturerating.
VDS(PEAK) = VIN(MAX) + VSN
Flyback Converter: Output Capacitor Selection
The power dissipated by the MOSFET in a flyback con-
verter is:
The output capacitor of the flyback converter has a similar
operation condition as that of the boost converter. Refer to
the Boost Converter: Output Capacitor Selection section
2
2
P
= I
• R
+ 2 • V
• I
•
FET
M(RMS)
DS(ON)
DS(PEAK) L(MAX)
C
• f /1A
RSS OSC
for the calculation of C
and ESR
.
OUT
COUT
3759fb
19
LT3759
APPLICATIONS INFORMATION
The RMS ripple current rating of the output capacitors
in discontinuous operation can be determined using the
following equation:
Themaximumdutycycle(D )occurswhentheconverter
MAX
has the minimum input voltage:
VOUT + VD
DMAX
=
4−(3 •D2)
IRMS(COUT),DISCONTINUOUS ≥ IO(MAX)
•
VIN(MIN) + VOUT + VD
3 •D2
SEPIC Converter: Inductor and Sense Resistor
Selection
Flyback Converter: Input Capacitor Selection
The input capacitor in a flyback converter is subject to
a large RMS current due to the discontinuous primary
current. To prevent large voltage transients, use a low
ESR input capacitor sized for the maximum RMS current.
The RMS ripple current rating of the input capacitors in
discontinuous operation can be determined using the
following equation:
As shown in Figure 1, the SEPIC converter contains two
inductors:L1andL2.L1andL2canbeindependent,butcan
also be wound on the same core, since identical voltages
are applied to L1 and L2 throughout the switching cycle.
For the SEPIC topology, the current through L1 is the
converter input current. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average inductor currents of L1 and L2 are:
POUT(MAX)
IN(MIN)•η
V
4−(3 •D
)
MAX
IRMS(CIN),DISCONTINUOUS
≥
•
3 •DMAX
DMAX
IL1(MAX) = IIN(MAX) = I
O(MAX) 1–DMAX
SEPIC CONVERTER APPLICATIONS
IL2(MAX) = IO(MAX)
The LT3759 can be configured as a SEPIC (single-ended
primary inductance converter), as shown in Figure 1. This
topology allows for the input to be higher, equal, or lower
than the desired output voltage. The conversion ratio as
a function of duty cycle is:
In a SEPIC converter, the switch current is equal to I
+
L1
I
when the power switch is on, therefore, the maximum
L2
average switch current is defined as:
ISW(MAX) = IL1(MAX) +IL2(MAX)
VOUT + VD
D
1−D
1
=
= IO(MAX)
•
V
IN
1–DMAX
In continuous conduction mode (CCM).
and the peak switch current is:
In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.
⎛
⎝
⎞
⎟
⎠
χ
2
1
ISW(PEAK) = 1+
• I
•
⎜
O(MAX)
1–DMAX
χ
The constant in the preceding equations represents the
percentage peak-to-peak ripple current in the switch, rela-
SEPIC Converter: Switch Duty Cycle and Frequency
For a SEPIC converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
tive to I
, as shown in Figure 8. Then, the switch
SW(MAX)
ripple current ΔI can be calculated by:
SW
voltage (V ), the input voltage (V ) and diode forward
OUT
IN
DISW = c • ISW(MAX)
voltage (V ).
D
3759fb
20
LT3759
APPLICATIONS INFORMATION
The inductor ripple currents ΔI and ΔI are identical:
BymakingL1=L2,andwindingthemonthesamecore,the
value of inductance in the preceding equation is replaced
by 2L, due to mutual inductance:
L1
L2
DIL1= DIL2 = 0.5• DISW
V
IN(MIN)
I
SW
L =
• DMAX
H
= ꢀzꢀI
SW(MAX)
)I
SW
DISW • fOSC
SENSE • V
R
IN(MIN)
I
SW(MAX)
=
• DMAX
0.01V • fOSC
t
DT
S
In a SEPIC converter, when the power switch is turned on,
T
S
3759 F08
the current flowing through the sense resistor (I
the switch current.
) is
SENSE
Figure 8. The Switch Current Waveform of a SEPIC Converter
Set the sense voltage at I
to be minimum of
SENSE(PEAK)
the SENSE current limit threshold with a 20% margin. The
sense resistor value can then be calculated to be:
The inductor ripple current has a direct effect on the
choice of the inductor value. Choosing smaller values of
L
40mV
ISW(PEAK)
ΔI requires large inductances and reduces the current
RSENSE
=
loop gain (the converter will approach voltage mode).
Accepting larger values of ΔI allows the use of low in-
L
ductances, but results in higher input current ripple and
SEPIC Converter: Power MOSFET Selection
χ
greater core losses. It is recommended that falls in the
For the SEPIC configuration, choose a MOSFET with a
range of 0.2 to 0.4.
V
rating higher than the sum of the output voltage and
DC
Choose an inductor value based on operating frequency,
input and output voltage to provide a current mode ramp
on SENSE during the switch on-time of approximately
10mV magnitude. The inductor value (L1 and L2 are
independent) of the SEPIC converter can be determined
using the following equation:
input voltage by a safety margin (a 10V safety margin is
usually sufficient).
ThepowerdissipatedbytheMOSFETinaSEPICconverter
is:
P
FET
= I2SW(MAX) • RDS(ON) • DMAX
V
+ (VIN(MIN) + VOUT)2 • ISW(MAX)
IN(MIN)
L1= L2 =
• DMAX
0.5• DISW • fOSC
SENSE • V
IN(MIN)
fOSC
R
•CRSS
•
=
•DMAX
1A
0.5•0.01V • fOSC
The first term in this equation represents the conduction
losses in the device, and the second term, the switching
For most SEPIC applications, the equal inductor values
will fall in the range of 1μH to 100μH.
loss. C
is the reverse transfer capacitance, which is
RSS
usually specified in the MOSFET characteristics.
3759fb
21
LT3759
APPLICATIONS INFORMATION
For maximum efficiency, R
and C
should be
SEPIC Converter: Selecting the DC Coupling Capacitor
DS(ON)
RSS
minimized. From a known power dissipated in the power
MOSFET, its junction temperature can be obtained using
the following equation:
The DC voltage rating of the DC coupling capacitor (C ,
DC
as shown in Figure 1) should be rated for the maximum
input voltage:
T = T + P • θ
JA
J
A
FET
CDC ≥ V
IN(MAX)
= T +P • (θ + θ
)
CA
A
FET
JC
C
has nearly a rectangular current waveform. During
DC
T must not exceed the MOSFET maximum junction
the switch off-time, the current through C is I , while
J
DC IN
temperature rating. It is recommended to measure the
MOSFETtemperatureinsteadystatetoensurethatabsolute
maximum ratings are not exceeded.
approximately –I flows during the on-time. The RMS
O
rating of the coupling capacitor is determined by the fol-
lowing equation:
VOUT + VD
SEPIC Converter: Output Diode Selection
IRMS(CDC) ≥ IO(MAX)
•
V
IN(MIN)
To maximize efficiency, a fast switching diode with a low
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
the output current, and the peak current is equal to:
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for C .
DC
INVERTING CONVERTER APPLICATIONS
⎛
⎝
⎞
⎟
⎠
χ
2
1
ID(PEAK) = 1+
• I
O(MAX)
•
⎜
1−DMAX
TheLT3759canbeconfiguredasadual-inductorinverting
topology, as shown in Figure 9. The V
to V ratio is:
OUT
IN
It is recommended that the peak repetitive reverse voltage
rating V is higher than V by a safety
margin (a 10V safety margin is usually sufficient).
VOUT – VD
D
1−D
V
OUT + IN(MAX)
RRM
=
V
IN
The power dissipated by the diode is:
In continuous conduction mode (CCM).
P = IO(MAX) • VD
D
C
+
DC
L1
L2
–
V
IN
and the diode junction temperature is:
+
–
C
IN
C
OUT
TJ = TA +PD • R
JA
θ
+
LT3759
GATE
D1
V
OUT
M1
R
The R used in this equation normally includes the R
θJA
θJC
for the device, plus the thermal resistance from the board,
SENSE
to the ambient temperature in the enclosure. T must not
J
SENSE
+
exceed the diode maximum junction temperature rating.
GND
3759 F09
SEPIC Converter: Output and Input Capacitor Selection
Figure 9. A Simplified Inverting Converter
The selections of the output and input capacitors of the
SEPICconverteraresimilartothoseoftheboostconverter.
Please refer to the Boost Converter, Output Capacitor
Selection and Boost Converter, Input Capacitor Selection
sections.
3759fb
22
LT3759
APPLICATIONS INFORMATION
Inverting Converter: Switch Duty Cycle and Frequency
Inverting Converter: Selecting the DC Coupling
Capacitor
For an inverting converter operating in CCM, the duty
cycle of the main switch can be calculated based on the
The DC voltage rating of the DC coupling capacitor (C ,
DC
as shown in Figure 9) should be larger than the maximum
negativeoutputvoltage(V )andtheinputvoltage(V ).
OUT
IN
input voltage minus the output voltage (negative voltage):
Themaximumdutycycle(D )occurswhentheconverter
MAX
has the minimum input voltage:
VCDC > VIN(MAX) – VOUT
VOUT – VD
DMAX
=
C
has nearly a rectangular current waveform. During
DC
VOUT – VD – V
IN(MIN)
the switch off-time, the current through C is I , while
DC
IN
approximately –I flows during the on-time. The RMS
O
Inverting Converter: Inductor, Sense Resistor, Power
MOSFET, Output Diode and Input Capacitor Selections
rating of the coupling capacitor is determined by the fol-
lowing equation:
The selections of the inductor, sense resistor, power
MOSFET, output diode and input capacitor of an inverting
converteraresimilartothoseoftheSEPICconverter.Please
refer to the corresponding SEPIC converter sections.
DMAX
1–DMAX
IRMS(CDC) >IO(MAX)
•
A low ESR and ESL, X5R or X7R ceramic capacitor works
Inverting Converter: Output Capacitor Selection
well for C .
DC
The inverting converter requires much smaller output
capacitors than those of the boost and SEPIC converters
for similar output ripples. This is due to the fact that, in
the inverting converter, the inductor L2 is in series with the
output, and the ripple current flowing through the output
capacitors are continuous. The output ripple voltage is
produced by the ripple current of L2 flowing through the
ESR and bulk capacitance of the output capacitor:
Board Layout
The high speed operation of the LT3759 demands careful
attention to board layout and component placement. The
exposed pad of the package is the only GND terminal of
the IC, and is important for thermal management of the
IC. Therefore, it is crucial to achieve a good electrical and
thermal contact between the exposed pad and the ground
plane of the board. For the LT3759 to deliver its full output
power, it is imperative that a good thermal path be pro-
vided to dissipate the heat generated within the package.
It is recommended that multiple vias in the printed circuit
board be used to conduct heat away from the IC and into
a copper plane with as much area as possible.
⎞
⎠
⎛
⎝
1
ΔVOUT(P−P) = ΔIL2 s ESRCOUT
+
8sfOSC sCOUT
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
To prevent radiation and high frequency resonance prob-
lems, proper layout of the components connected to the
IC is essential, especially the power paths with higher di/
dt. The following high di/dt loops of different topologies
should be kept as tight as possible to reduce inductive
ringing:
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output volt-
age ripple.
The RMS ripple current rating of the output capacitor
needs to be greater than:
• In boost configuration, the high di/dt loop contains the
outputcapacitor,thesensingresistor,thepowerMOSFET
and the Schottky diode.
IRMS(COUT) >0.3• DIL2
3759fb
23
LT3759
APPLICATIONS INFORMATION
ringing, which can exceed the maximum specified voltage
rating of the MOSFET. If this ringing cannot be avoided,
and exceeds the maximum rating of the device, either
choose a higher voltage device or specify an avalancher-
ated power MOSFET.
• In flyback configuration, the high di/dt primary loop
contains the input capacitor, the primary winding, the
power MOSFET and sensing resistor. The high di/dt
secondary loop contains the output capacitor, the sec-
ondary winding and the output diode.
Thesmall-signalcomponentsshouldbeplacedawayfrom
highfrequencyswitchingnodes.Foroptimumloadregula-
tion and true remote sensing, the top of the output voltage
sensing resistor divider should connect independently to
thetopoftheoutputcapacitor(Kelvinconnection),staying
away from any high dV/dt traces. Place the divider resis-
tors near the LT3759 in order to keep the high impedance
FBX node short.
• In SEPIC configuration, the high di/dt loop contains
the power MOSFET, sense resistor, output capacitor,
Schottky diode and the coupling capacitor.
• In inverting configuration, the high di/dt loop contains
power MOSFET, sense resistor, Schottky diode and the
coupling capacitor.
Check the stress on the power MOSFET by measuring its
drain-to-sourcevoltagedirectlyacrossthedeviceterminals
(reference the ground of a single scope probe directly to
the source pad on the PC board). Beware of inductive
Figure 10 shows the suggested layout of 1.8V to 3.3V
input, 5V/2A Output Boost Converter.
VIAS TO GROUND
PLANE
R4
R3
VIAS TO V
V
IN
C
C
C1
C2
IN
R
C
L1
12
11
10
9
R1
R2
C
1
2
3
4
5
6
LT3759
SS
C
DRIVE
R
C
VCC
T
8
13
R
7
PGOOD
1
8
7
6
5
2
3
4
M1
R
S
GND
D1
C
C
C
OUT1
IN
OUT2
V
V
OUT
IN
3759 F10
Figure 10. The Suggested Boost Converter Layout
3759fb
24
LT3759
TYPICAL APPLICATIONS
1.8V to 3.3V Input, 5V/2A Output Boost Converter
V
IN
1.8V TO 3.3V
C
IN
R5
10k
R3
59k
L1
2.2μH
47μF
6.3V
X5R
V
DRIVE
PGOOD
IN
D1
EN/UVLO
V
OUT
5V
2A
R4
124k
LT3759
SYNC
RT
GATE
M1
R2
34k
1%
SENSE
SS
VC
FBX
R
27.4k
T
GND INTV
CC
C
OUT2
300kHz
R1
15.8k
1%
R
5mΩ
0.5W
S
100μF
6.3V
X5R
×3
C
R
7.5k
C
C
VCC
C2
C
4.7μF
100pF
C
0.1μF
10V
X5R
SS
C1
22nF
3759 TA02a
M1: VISHAY Si414DJ
L1: TOKO FDA1055-2R2M
D1: VISHAY 6CWQ06FN
Efficiency vs Output Current
Load Step Response at VIN = 2.5V
100
90
80
70
60
50
40
30
20
10
0
V
OUT
500mV/DIV
(AC)
V
= 3.3V
IN
1.6A
V
= 1.8V
IN
I
OUT
1A/DIV
0.4A
3759 TA02c
10
0.001
0.01
0.1
1
500μs/DIV
OUTPUT CURRENT (A)
3759 TA02b
3759fb
25
LT3759
TYPICAL APPLICATIONS
8V to 16V Input, 24V/2A Output Boost Converter
V
IN
8V TO 16V
C
IN
L1
10μH
R5
100k
R3
200k
22μF
25V
V
DRIVE
PGOOD
IN
X5R
D1
EN/UVLO
V
OUT
24V
2A
R4
43.2k
LT3759
SYNC
RT
GATE
M1
R2
226k
1%
SENSE
C
OUT1
+
33μF
35V
×2
SS
VC
FBX
R
T
GND INTV
CC
27.4k
C
OUT2
300kHz
R1
16.2k
1%
R
S
22μF
25V
X5R
5mΩ
0.5W
C
R
C
C2
C
20k
VCC
4.7μF
10V
100pF
C
SS
C
C1
X5R
0.1μF
10nF
3759 TA03a
M1: VISHAY SILICONIX Si4840 BDY
L1: WÜRTH ELEKTRONIK 7443321000
D1: VISHAY 6CWQ06FN
Efficiency vs Output Current
Load Step Response at VIN = 12V
100
90
80
70
60
50
40
30
20
10
0
V
OUT
V
= 16V
500mV/DIV
IN
(AC)
V
= 8V
IN
1.6A
I
OUT
1A/DIV
0.4A
3759 TA03c
10
0.001
0.01
0.1
1
500μs/DIV
OUTPUT CURRENT (A)
3759 TA03b
3759fb
26
LT3759
TYPICAL APPLICATIONS
1.8V to 5V Input, 3.3V/3A Output SEPIC Converter
V
IN
1.8V TO 5V
L1A
C
47μF
10V
I
C
4.7μF
IN
10k
L1A
DC
59k
V
DRIVE
PGOOD
IN
10V, X5R, ×2
D1
EN/UVLO
V
OUT
3.3V
2A, 1.8V ≤ V ≤ 3V
V
SW
124k
IN
LT3759
3A, 3V < V ≤ 5V
IN
SYNC
RT
GATE
M1
16.9k
1%
I
L1B
SENSE
L1B
0.004Ω
1W
SS
VC
FBX
27.4k
300kHz
GND INTV
CC
C
OUT
100μF
6.3V
X5R
×3
15.8k
1%
0.1μF
3.01k
22nF
4.7μF
10V
X5R
3759 TA04a
M1: VISHAY Si7858BDP
L1A, L1B: COILTRONICS DRQ127-4R7
D1: VISHAY 6CWQ06FN
Efficiency vs Output Current
Load Step Response at VIN = 2.5V
100
90
80
70
60
50
40
30
20
10
0
V
= 2.5V
IN
V
OUT
500mV/DIV
(AC)
2.5A
I
OUT
1A/DIV
0.5A
3759 TA04c
10
500μs/DIV
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
3759 TA04b
3759fb
27
LT3759
TYPICAL APPLICATIONS
2.5V to 36V Input, 12V/1A Output SEPIC Converter
(Automotive 12V Regulator)
V
IN
2.5V TO 36V
C
IN
L1A
I
L1A
C
100k
DC
4.7μF
50V
×4
105k
118k
V
DRIVE
PGOOD
IN
4.7μF
50V, X5R, ×2
V
12V
D1
OUT
EN/UVLO
V
SW
0.5A, 2.5V ≤ V ≤ 8V
IN
LT3759
2A, 8V < V ≤ 36V
IN
SYNC
RT
GATE
M1
105k
1%
I
L1B
SENSE
L1B
0.005Ω
0.5W
C
OUT1
+
47μF
20V
×4
SS
VC
FBX
41.2k
200kHz
GND INTV
CC
C
OUT2
15.8k
1%
10μF
25V
X5R
0.1μF
7.5k
22nF
4.7μF
10V
X5R
3759 TA05a
M1: VISHAY SILICONIX Si7460DP
L1A, L1B: COILTRONICS DRQ127-150
D1: VISHAY 6CWQ06FN
Efficiency vs Output Current
Load Step Response at VIN = 12V
100
V
= 12V
IN
95
90
85
80
75
V
OUT
500mV/DIV
(AC)
1.6A
I
OUT
1A/DIV
0.4A
3759 TA05c
2
500μs/DIV
0
0.5
1
1.5
2.5
OUTPUT CURRENT (A)
3759 TA05b
Frequency Foldback Waveforms When Output Short-Circuits
V
OUT
10V/DIV
V
SW
20V/DIV
I
L1A + L1B
5A/DIV
3759 TA05d
20μs/DIV
3759fb
28
LT3759
TYPICAL APPLICATIONS
5V to 15V Input, –5V/3A Output Inverting Converter
V
IN
5V TO 15V
C
IN
47μF
16V
L1A
3.3μH
R2
105k
C
4.7μF
25V, X5R, ×2
DC
100k
V
DRIVE
PGOOD
IN
L1B
3.3μH
X5R
EN/UVLO
V
OUT
–5V
3A, 5V ≤ V ≤ 10V
R1
45.3k
IN
LT3759
4A, 10V < V ≤ 15V
IN
SYNC
RT
GATE
M1
84.5k
15.8k
SENSE
D1
5mΩ
0.5W
SS
VC
FBX
27.4k
300kHz
GND INTV
CC
C
OUT
47μF
6.3V, X5R
×4
9.1k
10nF
C
VCC
4.7μF
10V
X5R
0.1μF
3759 TA06a
M1: VISHAY SILICONIX Si7848BDP
L1A, L1B: COILTRONICS DRQ127-3R3
D1: VISHAY 6CWQ03FN
Efficiency vs Output Current
Load Step Response at VIN = 10V
100
90
80
70
60
50
40
30
20
10
0
V
= 5V
IN
V
OUT
V
= 15V
IN
500mV/DIV
(AC)
4A
I
OUT
2A/DIV
0.5A
3759 TA06c
10
0.001
0.01
0.1
1
500μs/DIV
OUTPUT CURRENT (A)
3759 TA06b
Frequency Foldback Waveforms When Output Short-Circuits
V
OUT
5V/DIV
V
SW
10V/DIV
I
L1A + L1B
5A/DIV
3759 TA06d
20μs/DIV
3759fb
29
LT3759
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev F)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 t0.102
2.845 t0.102
(.112 t.004)
0.889 t0.127
(.035 t.005)
(.112 t.004)
1
6
0.35
REF
1.651 t0.102
(.065 t.004)
5.23
(.206)
MIN
1.651 t0.102
(.065 t.004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
DETAIL “B”
12
7
0.65
(.0256)
BSC
0.42 t0.038
4.039 t0.102
(.159 t.004)
(NOTE 3)
(.0165 t.0015)
TYP
0.406 t0.076
RECOMMENDED SOLDER PAD LAYOUT
(.016 t.003)
12 11 10 9 8 7
REF
DETAIL “A”
0.254
(.010)
3.00 t0.102
(.118 t.004)
(NOTE 4)
0s – 6s TYP
4.90 t0.152
(.193 t.006)
GAUGE PLANE
0.53 t0.152
(.021 t.006)
1
2 3 4 5 6
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.1016 t0.0508
(.004 t.002)
MSOP (MSE12) 0911 REV F
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
3759fb
30
LT3759
REVISION HISTORY
REV
DATE DESCRIPTION
PAGE NUMBER
A
12/11 SS Pull-Up Current MIN and TYP values updated and INTV Current in Shutdown TYP value updated in Electrical
3, 4
CC
Characteristics table.
Revised Typical Application drawing TA02a
25
B
4/12
Revised Typical Applications Schematic TA01a
Added UN/UVLO Rising Spec
1
4
3759fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LT3759
TYPICAL APPLICATION
1.8V to 5V Input, –5V/2A Output Inverting Converter
L1A, 3.3μH
1:1
V
IN
1.8V TO 5V
C
IN
μF
C
DC
59k
V
47
IN
4.7μF ×2
25V, X5R
L1B
3.3μH
10V
X5R
EN/UVLO
V
OUT
124k
100k
–5V
1A, 1.8V ≤ V ≤ 2.5V
2A, 2.5V < V ≤ 5V
LT3759
IN
IN
GATE
M1
PGOOD
D2
D1
SENSE
TIE TO GND
IF NOT USED
5mΩ
0.5W
SYNC
M1: VISHAY SILICONIX Si74116DY
L1A, L1B: COILTRONICS DRQ127-3R3
D1: VISHAY 6CWQ03FN
DRIVE
FBX
1μF
16V
X5R
D2: PHILIPS PMEG2005EJ
84.5k
15.8k
RT
SS
VC
27.4k
300kHz
GND INTV
CC
C
OUT
C
4.7μF
10V
X5R
VCC
100μF
6.3V, X5R
×2
9.1k
10nF
0.1μF
3759 TA07a
Efficiency vs Output Current
100
95
90
85
80
75
70
V
= 2.5V
IN
V
= 5V
IN
2
2.5
0
0.5
1
1.5
OUTPUT CURRENT (A)
3759 TA07b
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT3757
Boost, Flyback, SEPIC and Inverting
Controller
2.9V ≤ V ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable Operation
IN
Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages
LT3758
LT3957
LT3958
LTC3872
Boost, Flyback, SEPIC and Inverting
Controller
5.5V ≤ V ≤ 100V, Current Mode Control, 100kHz to 1MHz Programmable Operation
IN
Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages
Boost, Flyback, SEPIC and Inverting
Converter with 5A, 40V Switch
3V ≤ V ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable Operation
IN
Frequency, 5mm × 6mm QFN Package
Boost, Flyback, SEPIC and Inverting
Converter with 3.3A, 84V Switch
5V ≤ V ≤ 80V, Current Mode Control, 100kHz to 1MHz Programmable Operation
IN
Frequency, 5mm × 6mm QFN Package
No R
Boost Controller
2.75V ≤ V ≤ 9.8V, TSOT-23 and 2mm × 3mm DFN-8
IN
SENSE
3759fb
LT 0412 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
●
●
© LINEAR TECHNOLOGY CORPORATION 2011
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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