LTC3880/_技术文档

LTC3838-1

Dual, Fast, Accurate

Step-Down DC/DC Controller with

Dual Differential Output Sensing

DESCRIPTION

FEATURES

Wide V Range: 4.5V to 38V, V : 0.6V to 5.5V

The LTC^®3838-1 is a dual-channel, PolyPhase^®syn-

chronousstep-downDC/DCswitchingregulatorcontroller.

Two independent channels drive all N-channel power

MOSFETs. The controlled on-time, valley current mode

control architecture allows for not only fast response to

transientswithoutclockdelay,butalsoconstantfrequency

switching at steady load condition. Its proprietary load-

release transient detection feature (DTR) significantly

reduces overshoot at low output voltages.

n

IN

OUT

n

Two Independent Channels: Dual/Single Output

Output Voltage Regulation Accuracy: 0.6ꢀ7

(V ) and 0.ꢀ57 (V

OUT1

) Over Temperature

OUT2

n

Differential Remote Output Sensing: Up to 500mV

(V ) and 200mV (V ) Ground Deviations

OUT1

OUT2

n

Controlled On-Time, Valley Current Mode Control

FastLoadTransientResponseWithoutClockDelay

DetectTransientRelease(DTR)ReducesV

Overshoot

Frequency Programmable from 200kHz to 2MHz,

Synchronizable to External Clock

OUT

Aprecisioninternalreferenceenablesaccuratedifferential

output regulation. The dual channels can either provide

two independent output voltages, or be combined into

multiphase single-output configuration.

n

t

= 30ns, t

= 90ns

ON(MIN)

OFF(MIN)

R

SENSE

or Inductor DCR Current Sensing

Theswitchingfrequencycanbeprogrammedfrom200kHz

to2MHzwithanexternalresistorandcanbesynchronizedto

anexternalclock.Very lowt andt timesallowfornear

Overvoltage Protection and Current Limit Foldback

Power Good Output Voltage Monitor

Output Voltage Tracking and Adjustable Soft Start-Up

Thermally Enhanced 38-Pin (5mm × 7mm) QFN Package

ON

OFF

0%andnear100%dutycycles,respectively.Voltagetrack-

ingsoftstart-upandmultiplesafetyfeaturesareprovided.

APPLICATIONS

See Table 1 for a comparison of LTC3838, LTC3838-1 and

LTC3838-2.

L, LT, LTC, LTM, PolyPhase, OPTI-LOOP, Linear Technology and the Linear logo are registered

trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks

are the property of their respective owners. Protected by U.S. Patents, including 5481178,

5847554, 6580258, 6304066, 6476589, 6774611.

n

Distributed Power Systems; Power Supply for ASIC

n

Computing, Data Storage, Communication Systems

Low Voltage, High Current, and/or High Step-Down Ratio

n

Converters That Demand Tight Load Transient Regulation

TYPICAL APPLICATION

1.2V/1.5V, 15A, 350kHz Step-Down Converter (Refer to Figure 16 for Complete Design)

V

IN

Efficiency/Power Loss

4.5V TO 38V

2.5

2.0

1.5

1.0

0.5

0

–

+

–

+

100

90

80

70

60

50

40

SENSE1

SENSE2

INTV

FORCED CONTINUOUS MODE

DISCONTINUOUS MODE

V

IN

CC

TG1

TG2

LTC3838-1

SW1

SW2

0.56µH

15k

V

1.5V

15A

V

OUT2

OUT1

1.2V

15A

EFFICIENCY

BOOST1

BOOST2

POWER

LOSS

0.1µF

10k

+

DRV

CC2

DRV

CC1

330µF

×2

330µF

×2

BG1

BG2

10k/ 10k

15k

4.7µF

10k

EXTV

CC

PGND

V

= 12V

IN

OUT

+

–

= 1.2V

V

OUTSENSE1

DFB2

–

V

OUTSENSE1

DFB2

0.1

1

10

TRACK/SS1 TRACK/SS2

LOAD CURRENT (A)

ITH1

ITH2

38381 TA01b

115k

RT

SGND

MODE_PLLIN

CLKOUT

V

PHASMD

RUN2

RNG

RUN1

38381 TA01a

38381f

1

For more information www.linear.com3838-1

LTC3838-1

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

V Voltage................................................. –0.3V to 40V

IN

BOOST1, BOOST2 Voltages ....................... –0.3V to 46V

SW1, SW2 Voltages ...................................... –5V to 40V

INTV , DRV , DRV , EXTV , PGOOD1,

38 37 36 35 34 33 32

+

CC

CC1

CC2

CC

V

1

2

3

4

5

6

7

8

9

31 TG2

30 SW2

DFB2

PGOOD2, RUN1, RUN2, (BOOST1-SW1),

V

RNG

ITH2

BG2

DRV

29

28

(BOOST2-SW2), MODE/PLLIN Voltages ...... –0.3V to 6V

+

–

TRACK/SS2

MODE/PLLIN

CLKOUT

SGND

CC2

SENSE1 , SENSE2 ,SENSE1 , SENSE2

27 EXTV

CC

Voltages....................................................... –0.6V to 6V

INTV

26

+

39

PGND

V

Voltage ............... –0.6V to (INTV + 0.3V)

OUTSENSE1

CC

25 PGND

24

–

+

Voltage.....................–0.6V to V

OUTSENSE1

RT

V

IN

TRACK/SS1, TRACK/SS2 Voltages .............. –0.3V to 5V

PHASMD

23 DRV

22 BG1

CC1

+

–

DTR1, DTR2, PHASMD, RT, V , V

, V

,

ITH1 10

RNG DFB2

DFB2

TRACK/SS1 11

+

21 SW1

20

ITH1, ITH2 Voltages ................–0.3V to (INTV + 0.3V)

CC

V

12

TG1

OUTSENSE1

Operating Junction Temperature Range

13 14 15 16 17 18 19

(Notes 2, 3, 4)........................................ –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

UHF PACKAGE

38-LEAD (5mm × 7mm) PLASTIC QFN

= 125°C, θ = 34°C/W

T

JMAX

JA

EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC3838EUHF-1#PBF

LTC3838IUHF-1#PBF

TAPE AND REEL

LTC3838EUHF-1#TRPBF 38381

LTC3838IUHF-1#TRPBF 38381

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

38-Lead (5mm × 7mm) Plastic QFN

–40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping

container. Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

Table 1. Comparison of LTC3838 Options

PART NUMBER

DESCRIPTION

LTC3838

0.67% Differential Output Regulation on Channel 1

1% Output Regulation on Channel 2

Separate-Per-Channel Continuous 30mV to 100mV Current Sense Range Controls

LTC3838-1

LTC3838-2

0.67% and 0.75%, Both Differential Output Regulation on Channel 1 and 2

Single-Pin 30mV/60mV Current Sense Range Control

0.67% Differential Output Regulation with Internal Reference on Channel 1

4mV Differential Output Regulation with External Reference Voltage on Channel 2

Fixed 30mV Current Sense Range

38381f

2

For more information www.linear.com/3838-1

LTC3838-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V unless otherwise noted (Note 3).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loops

V

Input Voltage Operating Range

4.5

0.6

38

V

IN

Regulated Output Voltage Operating Range

V

Regulated Differentially with

5.5

OUT1,2

OUT1

–

Respect to V

, V

Regulated

OUTSENSE1

OUT2

–

Differentially with Respect to V

DFB2

I

Q

Input DC Supply Current

Both Channels Enabled

Only One Channel Enabled

Shutdown Supply Current

MODE/PLLIN = 0V, No Load

3

2

15

mA

µA

RUN1 or RUN2 (But Not Both) = 0V

RUN1 = RUN2 = 0V

–

V

FB1

Regulated Feedback Voltage on Channel 1

ITH1 = 1.2V, V

= 0V (Note 5)

OUTSENSE1

+

–

(V

– V

)

T = 25°C

0.5985 0.6

0.6015

0.604

0.606

V

OUTSENSE1

A

l

T = 0°C to 85°C

0.596

0.594

0.6

A

T = –40°C to 125°C

A

Regulated Feedback Voltage on Channel 1 Over

Line, Load and Common Mode

V

= 4.5V to 38V, ITH1 = 0.5V to 1.9V,

IN

–

–0.5V < V

< 0.5V (Note 5)

OUTSENSE1

l

T = 0°C to 85°C

0.594

0.591

0.6

0.606

0.609

V

A

T = –40°C to 125°C

A

–

–0.2V < V

< 0.2V

OUTSENSE1

l

T = 0°C to 85°C

0.5955 0.6

0.594

0.6045

0.606

V

A

T = –40°C to 125°C

0.6

A

–

V

Regulated Feedback Voltage on Channel 2

ITH2 = 1.2V, V

= 0V (Note 5)

FB2

DFB2

+

–

(2 • V

– V

)

T = 25°C

0.598

0.6

0.602

0.6045

0.606

V

DFB2

A

l

T = 0°C to 85°C

T = –40°C to 125°C

0.5955 0.6

0.594 0.6

Regulated Feedback Voltage on Channel 2 Over

Line, Load and Common Mode

V

= 4.5V to 38V, ITH2 = 0.5V to 1.9V,

IN

–

–0.2V < V

< 0.2V (Note 5)

DFB2

l

T = 0°C to 85°C

0.5955 0.6

0.6045

0.606

V

A

T = –40°C to 125°C

0.594

0.6

A

+

–

+

–

I

V

Input Bias Current

V

= 0.6V, V

= 0V

0

25

–50

25

nA

µA

nA

µA

mS

ns

VOUTSENSE1

OUTSENSE1

–

+

= 0.6V, V

–25

0

VOUTSENSE1

OUTSENSE1

+

OUTSENSE1

+

OUTSENSE1

+

–

Input Bias Current

= 0.3V, V

= 0V

VDFB2

DFB2

–

+

–

= 0V

–6

1.7

30

90

–12

VDFB2

g

Error Amplifier Transconductance (∆I

Minimum Top Gate On-Time

/∆V

) ITH = 1.2V (Note 5)

m(EA)1,2

TH1,2

FB1,2

t

V

= 38V, V

= 0.6V, R = 20k (Note 6)

ON(MIN)1,2

OFF(MIN)1,2

IN

OUT

T

Minimum Top Gate Off-Time

(Note 6)

ns

Current Sensing

–

l

V

Maximum Valley Current Sense Threshold

(V

V

RNG

V

RNG

= 0V, V = 0.57V, V

= 2.5V

24

54

30

61

36

69

mV

SENSE(MAX)1,2

FB

SENSE

+

–

– V

)

= INTV , V = 0.57V, V

= 2.5V

SENSE1,2

CC FB

SENSE

–

V

Minimum Valley Current Sense Threshold

V

= 0V, V = 0.63V, V

= 2.5V

–15

–30

mV

SENSE(MIN)1,2

RNG

FB

SENSE

+

–

(V

– V

)

= INTV , V = 0.63V, V

= 2.5V

SENSE1,2

CC FB

SENSE

(Forced Continuous Mode)

+

I

SENSE1,2 Pins Input Bias Current

V

= 0.6V

= 5V

5

1

50

2

nA

µA

SENSE1,2

SENSE

–

SENSE1,2 Pins Input Bias Current (Internal 500k

Resistor to SGND)

V

= 0.6V

= 5V

1.2

10

µA

SENSE1,2

SENSE

38381f

3

For more information www.linear.com3838-1

LTC3838-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V unless otherwise noted (Note 3).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Start-Up and Shutdown

l

V

RUN Pin On Threshold

V

Rising

1.1

1.2

100

1.2

5

1.3

V

mV

µA

RUN1,2

RUN Pin On Hysteresis

Falling from On Threshold

I

RUN Pin Pull-Up Current When Off

RUN Pin Pull-Up Current Hysteresis

RUN1,2 = SGND

= I

RUN1,2

I

– I

RUN1,2(OFF)

µA

RUN1,2(HYS)

RUN1,2(ON)

l

UVLO

INTV Undervoltage Lockout

INTV Falling

3.3

3.7

4.2

V

CC

INTV Rising

4.5

CC

I

Soft-Start Pull-Up Current

0V < TRACK/SS1,2 < 0.6V

1

µA

TRACK/SS1,2

Frequency and Clock Synchronization

f

Clock Output Frequency

(Steady-State Switching Frequency)

R = 205k

200

500

2000

kHz

T

R = 80.6k

450

550

T

R = 18.2k

T

Channel 2 Phase (Relative to Channel 1)

CLKOUT Phase (Relative to Channel 1)

PHASMD = SGND

180

240

Deg

PHASMD = Floating

PHASMD = INTV

CC

PHASMD = SGND

60

90

120

Deg

PHASMD = Floating

PHASMD = INTV

CC

V

Clock Input High Level Into MODE/PLLIN

Clock Input Low Level Into MODE/PLLIN

MODE/PLLIN Input DC Resistance

2

V

PLLIN(H)

0.5

PLLIN(L)

R

With Respect to SGND

600

kΩ

MODE/PLLIN

Gate Drivers

R

TG Driver Pull-Up On Resistance

TG High

TG Low

BG High

BG Low

(Note 6)

2.5

1.2

2.5

0.8

20

Ω

TG(UP)1,2

TG Driver Pull-Down On Resistance

BG Driver Pull-Up On Resistance

TG(DOWN)1,2

BG(UP)1,2

Ω

BG Driver Pull-Down On Resistance

Top Gate Off to Bottom Gate On Delay Time

Bottom Gate Off to Top Gate On Delay Time

Ω

BG(DOWN)1,2

D(TG/BG)1,2

D(BG/TG)1,2

t

ns

15

Internal V Regulator

CC

V

Internally Regulated DRV

Voltage

6V < V < 38V

5.0

4.4

5.3

–1.5

4.6

5.6

–3

V

%

DRVCC1

EXTVCC

CC1

IN

DRV

Load Regulation

I

= 0mA to –100mA

CC1

DRVCC1

V

EXTV Switchover Voltage

EXTV Rising

4.8

V

CC

EXTV Switchover Hysteresis

200

mV

CC

EXTV to DRV

Voltage Drop

V

= 5V, I

= –100mA

CC

CC2

EXTVCC

DRVCC2

PGood Output

OV

UV

PGOOD Overvoltage Threshold

PGOOD Undervoltage Threshold

PGOOD Threshold Hysteresis

PGOOD Low Voltage

V

Rising from Regulated Voltage

Falling from Regulated Voltage

Returning to Regulated Voltage

= 2mA

5

7.5

–7.5

2.5

10

%

V

FB1,2

–5

–10

FB1,2

V

I

0.1

0.3

PGOOD(L)1,2

PGOOD

t

Delay from V Fault (OV/UV) to PGOOD Falling

50

20

µs

D(PGOOD)1,2

FB

Delay from V Good (OV/UV Cleared) to PGOOD

FB

Rising

38381f

4

For more information www.linear.com/3838-1

LTC3838-1

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. The maximum

rated junction temperature will be exceeded when this protection is active.

Continuous operation above the specified absolute maximum operating

junction temperature may impair device reliability or permanently damage

the device.

Note 2: The junction temperature (T , in °C) is calculated from the ambient

J

temperature (T , in °C) and power dissipation (P , in Watts) according to

A

D

the formula:

T = T + (P • θ )

JA

Note 5: The LTC3838-1 is tested in a feedback loop that adjusts voltages

+

on the V

and V

pins to achieve specified error amplifier

OUTSENSE1

DFB2

J

A

D

output voltages (ITH1,2).

where θ (in °C/W) is the package thermal impedance.

JA

In order to simplify the total system error computation, the regulated

voltage is defined in one combined specification which includes the effects

of line, load and common mode variation. The combined regulated voltage

specification is tested by independently varying line, load, and common

mode, which by design do not significantly affect one another. For any

combination of line, load, and common mode variation, the regulated

voltage should be within the limits specified that are tested in production

to the following conditions:

Note 3: The LTC3838-1 is tested under pulsed load conditions such that T

J

≈ T . The LTC3838E-1 is guaranteed to meet specifications over the 0°C to

A

85°C operating junction temperature range. Specifications over the –40°C

to 125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3838I-1 is guaranteed to meet specifications over the –40°C to 125°C

operating junction temperature range . Note that the maximum ambient

temperature consistent with these specifications is determined by specific

operating conditions in conjunction with board layout, the rated package

thermal impedance and other environmental factors.

–

Line: V = 4.5V to 38V, ITH = 1.2V, V

= 0V, V

= 0V

DFB2

IN

OUTSENSE1

–

Load: V = 15V, ITH = 0.5V to 1.9V, V

= 0V

IN

OUTSENSE1

DFB2

–

Common Mode: V = 15V, ITH = 1.2V, V

= 0.5V, 0.2V,

IN

OUTSENSE1

–

V

DFB2

= 0.2V

Note 6: Delay times are measured with top gate (TG) and bottom gate

(BG) driving minimum load, and using 50% levels.

38381f

5

For more information www.linear.com3838-1

LTC3838-1

TYPICAL PERFORMANCE CHARACTERISTICS

Transient Response

(Forced Continuous Mode)

Load Step

(Forced Continuous Mode)

Load Release

(Forced Continuous Mode)

I

LOAD

I

LOAD

10A/DIV

V

OUT

50mV/DIV

AC-COUPLED

I

L

I

L

10A/DIV

38381 G02

38381 G01

38381 G03

5µs/DIV

50µs/DIV

5µs/DIV

LOAD STEP = 0A TO 15A

LOAD TRANSIENT = 0A TO 15A TO 0A

LOAD RELEASE = 15A TO 0A

V

= 12V

V

= 12V

V

= 12V

IN

OUT

IN

OUT

IN

OUT

= 1.2V

FIGURE 17 CIRCUIT, CHANNEL 1

Transient Response

(Discontinuous Mode)

Load Step

(Discontinuous Mode)

Load Release

(Discontinuous Mode)

I

LOAD

10A/DIV

V

OUT

V

OUT

50mV/DIV

AC-COUPLED

I

L

I

L

10A/DIV

38381 G06

38381 G04

38381 G05

5µs/DIV

50µs/DIV

5µs/DIV

LOAD RELEASE = 15A TO 500mA

LOAD TRANSIENT = 500mA TO 15A TO 500mA

LOAD STEP = 500mA TO 15A

V

= 12V

V

= 12V

V

= 12V

IN

OUT

IN

OUT

IN

OUT

= 1.2V

FIGURE 17 CIRCUIT, CHANNEL 1

Load Release with Detect Transient (DTR)

Feature Enabled

Load Release with Detect Transient (DTR)

Feature Disabled

SW

3V/DIV

SW

3V/DIV

V

OUT

V

OUT

50mV/DIV

AC-COUPLED

ITH

1V/DIV

I

L

10A/DIV

38381 G07

38381 G08

5µs/DIV

LOAD RELEASE = 15A TO 5A

V

IN

V

OUT

= 5V

V

= 5V

IN

OUT

= 0.6V

FIGURE 17 CIRCUIT, CHANNEL 1 MODIFIED:

= 0Ω, C = 120pF, C = 0pF,

FIGURE 17 CIRCUIT, CHANNEL 1 MODIFIED:

R

= 0Ω, C

= 120pF, C

= 0pF,

FB2

ITH1

ITH2

FB2

ITH1/2

CONNECTION FROM R

ITH1

ITH2

FROM DTR1 PIN: R

= 46.4k TO SGND, R

= 42.2k TO INTV

CC

= 46.4k TO SGND//42.2k TO INTV

,

ITH1

ITH2

CC

SHADING OBTAINED WITH INFINITE PERSISTENCE ON

OSCILLOSCOPE WAVEFORMS

AND C

TO DTR1 PIN REMOVED.

ITH1/2

ITH1

DTR1 PIN TIED TO INTV

CC

38381f

6

For more information www.linear.com/3838-1

LTC3838-1

TYPICAL PERFORMANCE CHARACTERISTICS

Soft Start-Up Into

Prebiased Output

Regular Soft Start-Up

Output Tracking

RUN1

5V/DIV

RUN1

5V/DIV

TRACK/SS1

200mV/DIV

TRACK/SS1

200mV/DIV

V

OUT

500mV/DIV

V

OUT

TRACK/SS1

200mV/DIV

500mV/DIV

V

OUT

500mV/DIV

38381 G09

38381 G12

38381 G15

38381 G10

38381 G11

C

V

= 10nF

= 12V

OUT

1ms/DIV

C

V

= 10nF

= 12V

1ms/DIV

V

= 12V

10ms/DIV

SS

IN

SS

IN

OUT

= 1.2V

FORCED CONTINUOUS MODE

FIGURE 17 CIRCUIT, CHANNEL 1

OUT

FORCED CONTINUOUS MODE

FIGURE 17 CIRCUIT, CHANNEL 1

PRE-BIASED TO 0.75V

FIGURE 17 CIRCUIT, CHANNEL 1

Overcurrent Protection

Short-Circuit Protection

Overvoltage Protection

SHORT-

CIRCUIT

TRIGGER

I

L

I

10A/DIV

L

5A/DIV

OVERVOLTAGE CREATED BY APPLYING

V

OUT

A CHARGED CAPACITOR TO V

OUT

V

OUT

FULL CURRENT LIMIT

1V/DIV

100mV/DIV

WHEN V

HIGHER

CURRENT LIMIT STARTS TO FOLD BACK AS

OUT

AC-COUPLED

V

DROPS BELOW HALF OF REGULATED

THAN HALF OF REGULATED

OUT

I

C

L

OUT

V

BG1

5V/DIV

OUT

10A/DIV

RECHARGE

100mV/DIV

AC-COUPLED

38381 G13

38381 G14

V

I

= 12V

= 1.2V

= 0A

500µs/DIV

V

= 12V

= 1.2V

5ms/DIV

V

= 12V

= 1.2V

20µs/DIV

BG STAYS ON UNTIL

IS PULLED

IN

OUT

LOAD

IN

OUT

IN

OUT

FORCED CONTINUOUS MODE

CURRENT LIMIT = 17A

FORCED CONTINUOUS

MODE

V

OUT

FIGURE 17 CIRCUIT, CHANNEL 1

BELOW OVERVOLTAGE

THRESHOLD

OVERLOAD = 7.5A TO 17.5A

FIGURE 17 CIRCUIT, CHANNEL 1

I

= 0A

LOAD

FIGURE 17 CIRCUIT, CHANNEL 1

Phase Relationship:

PHASMD = Ground

Phase Relationship:

PHASMD = Float

Phase Relationship:

PHASMD = INTV_CC

PLLIN

5V/DIV

PLLIN

5V/DIV

PLLIN

5V/DIV

SW1

10V/DIV

SW1

10V/DIV

SW1

10V/DIV

0°

SW2

10V/DIV

SW2

10V/DIV

SW2

10V/DIV

180°

240°

CLKOUT

5V/DIV

CLKOUT

5V/DIV

CLKOUT

5V/DIV

60°

90°

120°

38381 G16

38381 G17

500ns/DIV

FIGURE 21 CIRCUIT

V

= 12V

= 5V, V

V

= 12V

= 5V, V

V

= 12V

= 5V, V

IN

OUT1

IN

OUT1

IN

OUT1

= 3.3V

OUT2

LOAD = 0A

MODE/PLLIN = 333kHz EXTERNAL CLOCK

LOAD = 0A

MODE/PLLIN = 333kHz EXTERNAL CLOCK

LOAD = 0A

MODE/PLLIN = 333kHz EXTERNAL CLOCK

38381f

7

For more information www.linear.com3838-1

LTC3838-1

TYPICAL PERFORMANCE CHARACTERISTICS

Output Regulation

vs Input Voltage

Output Regulation

vs Load Current

Output Regulation

vs Temperature

0.2

0.1

0.6

0.4

0.2

0.1

0

V

= 15V

V

I

= 15V

= 0.6V

= 0A

V

I

= 0.6V

= 5A

IN

OUT

= 0.6V

OUT

LOAD

NORMALIZED AT I

= 4A

V

NORMALIZED AT V = 15V

LOAD

OUT

IN

V

NORMALIZED AT T = 25°C

OUT

A

0.2

0

–0.2

–0.4

–0.6

–0.1

–0.2

0

2

4

6

8

10

75 100

125 150

–50 –25

0

25 50

0

5

10 15 20 25 30 35 40

TEMPERATURE (°C)

V

(V)

I

(A)

IN

LOAD

38381 G19

38381 G20

38381 G18

CLKOUT/Switching Frequency

vs Input Voltage

Error Amplifier Transconductance

vs Temperature

CLKOUT/Switching Frequency

vs Temperature

1.80

1.75

1.70

1.65

1.60

1.55

1.50

2

1

2

1

V

= 15V, V

= 0.6V

IN

OUT

I

= 0A

LOAD

f = 500kHz

FREQUENCY NORMALIZED AT T = 25°C

A

0

–1

V

= 0.6V

= 5A

OUT

I

LOAD

f = 500kHz

FREQUENCY NORMALIZED AT V = 15V

IN

–2

75 100

–50 –25

0

25 50

125 150

0

5

10 15 20 25 30 35 40

(V)

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

V

IN

38381 G27

38381 G21

38381 G23

t_ON(MIN)and t_OFF(MIN)

vs Voltage on V_INPin

t_ON(MIN)and t_OFF(MIN)

vs Switching Frequency

t_ON(MIN)and t_OFF(MIN)

vs V_OUT(Voltage on SENSE^–Pin)

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

t

OFF(MIN)

t

ON(MIN)

t

ON(MIN)

V

R

= 0.6V

V

= 38V

V

= 38V

OUT

T

IN

T

IN

OUT

ADJUSTED FOR f

= 2MHz

R

ADJUSTED FOR f

= 2MHz

4

= 0.6V

CLKOUT

0

5

15 20 25 30 35 40

(V)

0

1

3

–

5

6

10

200

500

1100 1400 1700 2000

2

800

V

(V)

CLKOUT/SWITCHING FREQUENCY (kHz)

IN

SENSE

38381 G25

38381 G24

38381 G26

38381f

8

For more information www.linear.com/3838-1

LTC3838-1

TYPICAL PERFORMANCE CHARACTERISTICS

Maximum Current Sense Voltage

vs Voltage on SENSE^–Pin

Current Sense Voltage

vs ITH Voltage

Maximum Current Sense Voltage

vs Temperature

120

100

80

120

100

80

60

40

20

0

120

100

80

60

40

20

0

FORCED CONTINUOUS MODE

60

V

= INTV

CC

40

V

= INTV

CC

RNG

20

0

V

= SGND

V

RNG

= SGND

RNG

–20

–40

V

= INTV

CC

RNG

= SGND

–60

75 100

–50 –25

0

25 50

125 150

–0.5

1.5

2.5

3.5

4.5

5.5

0

0.4

0.8

1.2

2.4

0.5

1.6

2

–

TEMPERATURE (°C)

SENSE PIN VOLTAGE (V)

ITH VOLTAGE (V)

38381 G29

38381 G22

38381 G28

RUN Pin Thresholds

vs Temperature

RUN Pull-Up Currents

vs Temperature

TRACK/SS Pull-Up Currents

vs Temperature

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

8

7

6

5

4

3

2

1

0

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

SWITCHING REGION

RUN PIN ABOVE 1.2V

SWITCHING THRESHOLD

STAND-BY REGION

SHUTDOWN REGION

RUN PIN BELOW 1.2V

SWITCHING THRESHOLD

50 75

25

TEMPERATURE (°C)

50 75

25

TEMPERATURE (°C)

50 75

TEMPERATURE (°C)

–50 –25

0

100 125 150

–50 –25

0

100 125 150

–50 –25

0

25

100 125 150

38381 G30

38381 G31

38381 G32

INTV_CCUndervoltage Lockout

Thresholds vs Temperature

Shutdown Current Into V_INPin

vs Voltage on V_INPin

Quiescent Current Into V_INPin

vs Temperature

3.5

40

35

30

25

20

15

10

5

4.5

4.3

4.1

3.9

3.7

3.5

3.3

UVLO RELEASE

(INTV RISING)

CC

3.0

2.5

BOTH CHANNELS ON

CHANNEL 1 ON ONLY OR

CHANNEL 2 ON ONLY

2.0

1.5

1.0

UVLO LOCK

(INTV FALLING)

CC

130°C

25°C

–45°C

0

20 25

(V)

75 100

0

5

10 15

30 35 40

–50

25 50

75

–50 –25

0

25 50

125 150

–25

0

100 125

150

TEMPERATURE (°C)

V

TEMPERATURE (°C)

IN

38381 G34

38381 G33

38381 G35

38381f

9

For more information www.linear.com3838-1

LTC3838-1

PIN FUNCTIONS

+

V

(Pin 1): Differential Feedback Amplifier (+) Input

PHASMD(Pin9):PhaseSelectorInput.Thispindetermines

the relative phases of channels and the CLKOUT signal.

With zero phase being defined as the rising edge of TG1:

Pulling this pin to SGND locks TG2 to 180°, and CLKOUT

DFB2

of Channel 2. As shown in the Functional Diagram, con-

nect this pin to a 3-resistor feedback divider network,

which is composed of R

thenegativeandpositiveterminalsofV

and R

from this pin to

OUT2

DFB1

DFB2

respectively,

to 60°. Connecting this pin to INTV locks TG2 to 240°

CC

and a third resistor from this pin to local SGND. The

third resistor must have a value equal to R //R

and CLKOUT to 120°. Floating this pin locks TG2 to 180°

and CLKOUT to 90°.

DFB1 DFB2

for accurate differential regulation. With the 3-resistor

ITH1,ITH2(Pin10,Pin3):CurrentControlThreshold.This

pin is the output of the error amplifier and the switching

regulator’s compensation point. The current comparator

threshold increases with this control voltage. The voltage

ranges from 0V to 2.4V, with 0.8V corresponding to zero

sense voltage (zero inductor valley current).

feedbackdividernetwork,theLTC3838-1willregulatethe

differentialoutputV

to0.6V• (R

+R

)/R

.

OUT2

DFB1

DFB2

DFB1

V

(Pin2):CurrentSenseVoltageRangeInput.Themaxi-

RNG

+

–

mumsensevoltagebetweenSENSE1,2 andSENSE1,2 of

either channel, V , is 30mV if V is tied to

SGND, and 60mV if V

SENSE(MAX)1,2

RNG

is tied to INTV .

RNG

CC

TRACK/SS1,TRACK/SS2(Pin11,Pin4):ExternalTracking

MODE/PLLIN (Pin 5): Operation Mode Selection or Exter-

and Soft-Start Input. The LTC3838-1 regulates differen-

+

–

nal Clock Synchronization Input. When this pin is tied to

tial feedback voltages (V

– V

) and

OUTSENSE1

+

–

INTV ,forcedcontinuousmodeoperationisselected.Ty-

(2 • V

– V

) to the smaller of 0.6V or the volt-

CC

DFB2

ingthispintoSGNDallowsdiscontinuousmodeoperation.

Whenanexternalclockisappliedatthispin,bothchannels

operateinforcedcontinuousmodeandsynchronizetothe

external clock. This pin has an internal 600k pull-down

resistor to SGND.

age on the TRACK/SS1,2 pins respectively. An internal

1µA temperature-independent pull-up current source is

connected to each TRACK/SS pin. A capacitor to ground

at this pin sets the ramp time to the final regulated output

voltage. Alternatively, another voltage supply connected

to this pin allows the output to track the other supply

during start-up.

CLKOUT (Pin 6): Clock Output of Internal Clock Genera-

tor. Its output level swings between INTV and SGND.

CC

+

If clock input is present at the MODE/PLLIN pin, it will

be synchronized to the input clock, with phase set by the

PHASMD pin. If no clock is present at MODE/PLLIN, its

frequency will be set by the RT pin. To synchronize other

controllers,itcanbeconnectedtotheirMODE/PLLINpins.

V

(Pin 12): Differential Output Sense Amplifier

OUTSENSE1

(+) Input of Channel 1. Connect this pin to a feedback

resistor divider between the positive and negative output

capacitor terminals of V

as shown in the Functional

OUT1

Diagram. In normal operation, the LTC3838-1 will at-

tempt to regulate the differential output voltage V

OUT1

SGND (Pin ꢀ): Signal Ground. All small-signal analog and

compensation components should be connected to this

ground. Connect SGND to the exposed pad and PGND pin

using a single PCB trace.

to 0.6V divided by the feedback resistor divider ratio, i.e,

0.6V • (R + R )/R .

FB1

FB2

FB1

+

Shorting the V

pin to INTV will disable

CC

OUTSENSE1

channel 1’s error amplifier, and internally connect ITH1

to ITH2. (As a result, TRACK/SS1 is no longer functional

and PGOOD1 is always pulling low.) By doing so, this

RT (Pin 8): Clock Generator Frequency Programming Pin.

Connect an external resistor from RT to SGND to program

the switching frequency between 200kHz and 2MHz. An

external clock applied to MODE/PLLIN should be within

30% of this programmed frequency to ensure frequency

lock.WhentheRT pinisfloating,thefrequencyisinternally

set to be slightly under 200kHz.

part can function as a dual phase, single V

step-down

OUT

controller, and the two channels use a single channel 2

error amplifier for the ITH output and compensation.

38381f

10

For more information www.linear.com/3838-1

LTC3838-1

PIN FUNCTIONS

–

V

(Pin 13): Differential Output Sense Amplifier

RUN1, RUN2 (Pin 1ꢀ, Pin 34): Run Control Inputs. An

internal proportional-to-absolute-temperature (PTAT)

pull-up current source (~1.2µA at 25°C) is constantly

connected to this pin. Taking both RUN1 and RUN2 pins

below a threshold voltage (~0.8V at 25°C) shuts down all

bias of INTV and DRV and places the LTC3838-1 into

micropower shutdown mode. Allowing either RUN pin to

rise above this threshold would turn on the internal bias

supply and the circuitry for the particular channel. When

a RUN pin rises above 1.2V, its corresponding channel’s

TG and BG drivers are turned on and an additional 5µA

temperature-independent pull-up current is connected

internally to the RUN pin. Either RUN pin can sink up to

50µA, or be forced no higher than 6V.

OUTSENSE1

(–) Input of Channel 1. Connect this pin to the negative

terminal of the output load capacitor of V

.

OUT1

+

SENSE1 , SENSE2 (Pin 14, Pin 3ꢀ): Differential Current

Sense Comparator (+) Inputs. The ITH pin voltage and

+

–

CC

controlled offsets between the SENSE and SENSE pins

set the current trip threshold. The comparator can be used

for R

sensing or inductor DCR sensing. For R

SENSE

+

sensing, Kelvin (4-wire) connect the SENSE pin to the

+

(+) terminal of R

. For DCR sensing, tie the SENSE

SENSE

pins to the connection between the DCR sense capacitor

and sense resistor tied across the inductor.

–

SENSE1 ,SENSE2 (Pin15,Pin36):DifferentialCurrent

SenseComparator(–)Input.Thecomparatorcanbeused

PGOOD1,PGOOD2(Pin18,Pin33):PowerGoodIndicator

Outputs. This open-drain logic output is pulled to ground

when the output voltage goes out of a 7.5% window

around the regulation point, after a 50µs power-bad-

masking delay. Returning to the regulation point, there is

a delay of around 20µs to power good, and a hysteresis

of around 2.5% (or 15mV on the same scale as the 0.6V

for R

sensing or inductor DCR sensing. For R

SENSE

–

sensing,Kelvin(4-wire)connecttheSENSE pintothe(–)

terminal of R

totheDCRsensecapacitortiedtotheinductorV

–

. For DCR sensing, tie the SENSE pin

SENSE

node

OUT

connection. These pins also function as output voltage

sense pins for the top MOSFET on-time adjustment. The

impedance looking into these pins is different from the

reference and internal feedback voltages, V

sides of the voltage window.

) on both

FB1,2

+

SENSE pins because there is an additional 500k internal

–

resistor from each of the SENSE pins to SGND.

BOOST1, BOOST2 (Pin 19, Pin 32): Boosted Floating

DTR1, DTR2 (Pin 16, Pin 35): Detect Load-Release Tran-

sient for Overshoot Reduction. When load current sud-

denly drops, if voltage on this DTR pin drops below half

Supplies for Top MOSFET Drivers. The (+) terminal of the

bootstrap capacitor, C , connects to this pin. The BOOST

B

pins swing by a V between a diode drop below DRV ,

IN

CC

of INTV , the bottom gate (BG) could turn off, allowing

CC

or (V

– V ) and (V + V

– V ).

DRVCC D

DRVCC

D

IN

the inductor current to drop to zero faster, thus reducing

the V

overshoot. (Refer to Load-Release Transient

TG1, TG2 (Pin 20, Pin 31): Top Gate Driver Outputs. The

OUT

DetectionintheApplicationsInformationsectionformore

TGpinsdrivethegatesofthetopN-channelpowerMOSFET

details.) An internal 2.5μA current source pulls this pin

with a voltage swing of V

between SW and BOOST.

DRVCC

toward INTV . To disable the DTR feature, simply tie the

CC

DTR pin to INTV .

CC

38381f

11

For more information www.linear.com3838-1

LTC3838-1

PIN FUNCTIONS

SW1, SW2 (Pin 21, Pin 30): Switch Node Connection to

PGND (Pin 25, Exposed Pad Pin 39): Power Ground.

Connect this pin as close as practical to the source of the

bottom N-channel power MOSFET, the (–) terminal of

Inductors. Voltage swings are from a diode voltage below

ground to V . The (–) terminal of the bootstrap capacitor,

IN

C , connects to this node.

B

C

and the (–) terminal of C . Connect the exposed

DRVCC IN

pad and PGND pin to SGND pin using a single PCB trace

under the IC. The exposed pad must be soldered to the

circuit board for electrical and rated thermal performance.

BG1, BG2 (Pin 22, Pin 29): Bottom Gate Driver Outputs.

TheBGpinsdrivethegatesofthebottomN-channelpower

MOSFET between PGND and DRV .

CC

INTV (Pin 26): Supply Input for Internal Circuitry (Not

CC

DRV , DRV

(Pin 23, Pin 28): Supplies of Bottom

CC1

CC2

IncludingGateDrivers).NormallypoweredfromtheDRV

CC

Gate Drivers. DRV is also the output of an internal 5.3V

pins through a decoupling RC filter to SGND (typically

regulator. DRV is also the output of the EXTV switch.

CC2

CC

2Ω and 1µF).

Normally the two DRV pins are shorted together on the

CC

PCB, and decoupled to PGND with a minimum of 4.7µF

EXTV (Pin 2ꢀ): External Power Input. When EXTV

CC CC

ceramic capacitor, C

.

exceedstheswitchovervoltage(typically4.6V),aninternal

switch connects this pin to DRV and shuts down the

DRVCC

CC2

V

IN

(Pin 24): Input Voltage Supply. The supply voltage

internal regulator so that INTV and gate drivers draw

CC

canrangefrom4.5Vto38V. Forincreasednoiseimmunity

decouple this pin to SGND with an RC filter. Voltage at

this pin is also used to adjust top gate on-time, therefore

it is recommended to tie this pin to the main power input

supply through an RC filter.

power from EXTV . The V pin still needs to be powered

CC

IN

up but draws minimum current.

–

V

(Pin 38): Differential Feedback Amplifier (–) Input

DFB2

of Channel 2. Connect this pin to the negative terminal of

the output load capacitor of V

.

OUT2

38381f

12

For more information www.linear.com/3838-1

LTC3838-1

FUNCTIONAL DIAGRAM

V

IN

EN LDO

OUT SD

1-2µA

PTAT

5µA

+

–

4.2V

UVLO

BOOST

TG

DRV

C

B

RUN

D

B

+

TG

M

T

R

SENSE

L

SW

EN_DRV

+

V

OUT

1.2V

–

DRV

CC

EXTV

CC

+

–

+

~4.6V

INTV

~0.8V

CC

–

LOGIC

CONTROL

C

OUT

INTVCC

DRV

CC2

CC1

–

SENSE

START

STOP

V

250k

IN

ONE-SHOT

TIMER

C

DRVCC

BG DRV

250k

BG

M

B

FORCED

ON-TIME

ADJUST

CONTINUOUS

MODE

PGND

–

OUT

V

MODE/PLLIN

PHASE

DETECTOR

MODE/CLK

DETECT

I

REV

CMP

+

–

CLK1

CLK2

+

–

RT

SENSE

CLOCK PLL/

GENERATOR

TO CHANNEL 2

R

T

CLKOUT

1µA

EA

TRACK/SS

+

INTV

CC

g

C

SS

m

0.6V V

REFERENCE

+

–

0.555V

R

–

PGD

UV

OV

PGOOD

+

V

OUTSENSE1

+

REMOTE OUTPUT

SENSING

V

(CHANNEL 1)

FB1

DIFFAMP

(A = 1)

DELAY

(CHANNEL 1)

+

R

FB2

–

FB1

–

V

OUT1

+

–

V

OUT1

0.645V

+

R

//R

DFB1 DFB2

V

DFB2

+

–

V

(CHANNEL 2)

FB2

REMOTE OUTPUT

SENSING

(CHANNEL 2)

–

R

DFB1

DFB2

+

V

OUT2

V

OUT2

50k

–

INTV

CC

LOAD

1/2 INTV

DTR

+

–

RELEASE

CC

DETECTION

TO LOGIC

CONTROL

DUPLICATE DASHED

LINE BOX FOR

CHANNEL 2

V

RNG

I

TH

38381 FD

INTV

CC

INTV

CC

C

ITH1

R

ITH2

C

ITH2

OPT

R

ITH1

38381f

13

For more information www.linear.com3838-1

LTC3838-1

OPERATION ^{(Refer to Functional Diagram)}

Main Control Loop

The LTC3838-1 features a detect transient (DTR) pin to

detect“load-release”,oratransientwheretheloadcurrent

suddenly drops, by monitoring the first derivative of the

ITHvoltage.Whendetected,thebottomgate(BG)isturned

off and inductor current flows through the body diode in

the bottom MOSFET, allowing the SW node voltage to

dropbelowPGNDbythebodydiode’sforward-conduction

voltage. This creates a more negative differential voltage

The LTC3838-1 is a controlled on-time, valley current

mode step-downDC/DC dualcontroller with two channels

operating out of phase. Each channel drives both main

and synchronous N-channel MOSFETs. The two channels

can be either configured to two independently regulated

outputs, or combined into a single output.

ThetopMOSFETisturnedonforatimeintervaldetermined

by a one-shot timer. The duration of the one-shot timer is

controlled to maintain a fixed switching frequency. As the

top MOSFET is turned off, the bottom MOSFET is turned

on after a small delay. The delay, or dead time, is to avoid

both top and bottom MOSFETs being on at the same time,

(V – V ) across the inductor, allowing the inductor

SW

OUT

current to drop faster to zero, thus creating less overshoot

onV . SeeLoad-ReleaseTransientDetectioninApplica-

OUT

tions Information for details.

Differential Output Sensing

causing shoot-through current from V directly to power

IN

Bothchannelsofthisdualcontrollerhavedifferentialoutput

voltage sensing. The output voltage is resistively divided

externally to create a feedback voltage for the controller.

As shown in the Functional Diagram, channel 1 uses an

external 2-resistor voltage divider, and an internal unity-

gain difference amplifier (DIFFAMP) that converts the dif-

ferentialfeedbacksignaltoasingle-endedinternalfeedback

ground. The next switching cycle is initiated when the cur-

rent comparator, I

, senses that inductor current falls

CMP

below the trip level set by voltages at the ITH and V

RNG

pins. The bottom MOSFET is turned off immediately and

the top MOSFET on again, restarting the one-shot timer

and repeating the cycle. In order to avoid shoot-through

current, there is also a small dead-time delay before the

top MOSFET turns on. At this moment, the inductor cur-

rent hits its “valley” and starts to rise again.

+

–

voltage V = V

– V

with respect to

FB1

OUTSENSE1

+

–

SGND.Withtheexternalresistordivider,V

–V

=

OUT1

V

• (R +R )/R .Channel2hasauniquefeedback

FB1

FB1 FB2 FB1

+

–

Inductor current is determined by sensing the voltage

amplifier that produces V

= 2 • V

– V

. Its

FB2

DFB2

+

–

between SENSE and SENSE , either by using an explicit

resistorconnectedinserieswiththeinductororbyimplicitly

sensing the inductor’s DC resistive (DCR) voltage drop

through an RC filter connected across the inductor. The

external feedback network requires a third resistor tied

to local ground (SGND). The third resistor must have a

value equal to the parallel value of the two voltage divider

+

–

resistors R

and R

DFB2

so that V

DFB1

– V

=

DFB1

DFB2

)/R

OUT2

trip level of the current comparator, I

, is proportional

V

• (R

+ R

.

CMP

FB2

DFB1

to the voltage at the ITH pin, with a zero-current threshold

corresponding to an ITH voltage of around 0.8V.

Both channels adjust outputs through system feedback

loops so that these internally-generated single-ended

The error amplifier (EA) adjusts this ITH voltage by

comparing the feedback signal to the internal reference

voltage. Output voltage is regulated so that the feedback

voltageisequaltotheinternalreference.Iftheloadcurrent

increases/decreases, it causes a momentary drop/rise in

the differential feedback voltage relative to the reference.

The EA then moves ITH voltage, or inductor valley current

setpoint, higher/lower until the average inductor current

again matches the load current, so that the output voltage

comes back to the regulated voltage.

feedback voltages (V

in the Functional Diagram)

FB1,2

are equal to the internal 0.6V reference voltages when in

regulation. Therefore, the differential V is regulated

OUT1

to 0.6V • (R + R )/R , and the differential V is

FB1

FB2

FB1

+ R

OUT2

. Such schemes

regulated to 0.6V • (R

)/R

DFB1

DFB2

DFB1

eliminate any ground offsets between local ground and

remoteoutputground, resultinginamoreaccurateoutput

voltage. Channel1allowsremoteoutputgroundtodeviate

as much as 500mV, and channel 2 allows as much as

200mV, with respect to local ground (SGND).

38381f

14

For more information www.linear.com/3838-1

LTC3838-1

OPERATION ^{(Refer to Functional Diagram)}

DRV /EXTV /INTV Power

the corresponding channel’s internal circuitry off INTV

CC

will be biased up when either or both RUN pins are pulled

up above the 0.8V threshold, either by the internal pull-up

current or driven directly by an external voltage source

such as a logic gate output.

DRV

are the power for the bottom MOSFET drivers.

CC1,2

Normally the two DRV pins are shorted together on

CC

the PCB, and decoupled to PGND with a minimum 4.7µF

ceramic capacitor, C

. The top MOSFET drivers are

DRVCC

biased from the floating bootstrap capacitors (C

)

A channel of the LTC3838-1 will not start switching until

the RUN pin of the respective channel is pulled up to 1.2V.

When a RUN pin rises above 1.2V, the corresponding

channel’s TG and BG drivers are enabled, and TRACK/

SS released. An additional 5µA temperature-independent

pull-up current is connected internally to the channel’s

respective RUN pin. To turn off TG, BG and the additional

5µA pull-up current, RUN needs to be pulled down be-

low 1.2V by about 100mV. These built-in current and

voltagehysteresespreventfalsejitteryturn-onandturn-off

due to noise. These features on the RUN pins allow input

undervoltage lockout (UVLO) to be set up using external

B1,2

whicharerechargedduringeachcyclethroughanexternal

Schottky diode when the top MOSFET turns off and the

SW pin swings down.

The DRV can be powered two ways: an internal low-

CC

dropout (LDO) linear voltage regulator that is powered

from V and can output 5.3V to DRV . Alternatively,

IN

CC1

an internal EXTV switch (with on-resistance of around

CC

2Ω) can short the EXTV pin to DRV

.

CC

CC2

If the EXTV pin is below the EXTV switchover voltage

CC

(typically 4.6V with 200mV hysteresis, see the Electrical

Characteristics Table), then the internal 5.3V LDO is en-

voltage dividers from V .

IN

abled.IftheEXTV pinistiedtoanexternalvoltagesource

CC

The start-up of a channel’s output voltage (V ) is

OUT

greaterthanthisEXTV switchovervoltage, thentheLDO

CC

controlled by the voltage on its TRACK/SS pin. When the

is shut down and the internal EXTV switch shorts the

CC

voltage on the TRACK/SS pin is less than the 0.6V inter-

EXTV pin to the DRV

pin. In this case, DRV and

CC

CC2

CC

nal reference, the feedback voltage (V ) is regulated to

FB

INTV draw power from the external voltage source,

the TRACK/SS voltage instead of the 0.6V reference. The

TRACK/SS pin can be used to program the output voltage

soft-start ramp-up time by connecting an external capaci-

tor from a TRACK/SS pin to signal ground. An internal

temperature-independent1µApull-upcurrentchargesthis

capacitor, creating a voltage ramp on the TRACK/SS pin.

As the TRACK/SS voltage rises from ground to 0.6V, the

which helps to increase overall efficiency and decrease

internal self heating from power dissipated in the LDO. If

the output voltage of the converter itself is above the up-

per switchover voltage limit (4.8V), it can provide power

for EXTV . The V pin still needs to be powered up but

now draws minimum current.

CC

IN

Power for most internal control circuitry other than gate

driversisderivedfromtheINTV pin.INTV canbepow-

ered from the combined DRV pins through an external

RC filter to SGND to filter out noises due to switching.

switching starts, and V

ramps up smoothly to its final

OUT

valueandthefeedbackvoltageto0.6V.TRACK/SSwillkeep

rising beyond 0.6V, until being clamped to around 3.7V.

CC

Upon enabling the RUN pin, if V

is prebiased at a

OUT

level above zero, the top gate (TG) will remain off and

stays prebiased. Once TRACK/SS rises above the

Shutdown and Start-Up

V

OUT

EachoftheRUN1andRUN2pinshasaninternalproportion-

al-to-absolute-temperature(PTAT)currentsource(around

1.2µA at 25°C) to pull up the pins. Taking both RUN1 and

RUN2pinsbelowacertainthresholdvoltage(around0.8V

prebiased feedback level, and TG starts switching, V

OUT

will be regulated according to TRACK/SS or the reference,

whichever is lower.

Alternatively, the TRACK/SS pin can be used to track an

external supply like in a master slave configuration. Typi-

cally, this requires connecting a resistor divider from the

master supply to the TRACK/SS pin (see the Applications

at 25°C) shuts down all bias of INTV and DRV and

CC

places the LTC3838-1 into micropower shutdown mode

with a minimum I at the V pin. The LTC3838-1’s DRV

CC

Q

IN

(through the internal 5.3V LDO regulator or EXTV ) and

CC

Information section).

38381f

15

For more information www.linear.com3838-1

LTC3838-1

OPERATION ^{(Refer to Functional Diagram)}

TRACK/SS is pulled low internally when the correspond-

In an overvoltage (OV) condition, M is turned off and M

T B

ing channel’s RUN pin is pulled below the 1.2V threshold

isturnedonimmediatelywithoutdelayandheldonuntilthe

overvoltage condition clears. This happens regardless of

any other condition as long as the RUN pin is enabled. For

(hysteresis applies), or when INTV or either of the

CC

DRV

pins drop below their respective undervoltage

CC1,2

lockout (UVLO) thresholds.

example, uponenablingtheRUN1pin, ifV

isprebiased

OUT

at more than 7.5% above the programmed regulated volt-

Light Load Current Operation

age, the OV stays triggered and BG forced on until V

pulled a ~2.5% hysteresis below the 7.5% OV threshold.

is

OUT

If the MODE/PLLIN pin is tied to INTV or an external

CC

clock is applied to MODE/PLLIN, the LTC3838-1 will be

forced to operate in continuous mode. With load current

less than one-half of the full load peak-to-peak ripple, the

inductor current valley can drop to zero or become nega-

tive. This allows constant-frequency operation but at the

cost of low efficiency at light loads.

Foldback current limiting is provided if the output is below

one-half of the regulated voltage, such as being shorted

to ground. As the feedback approaches 0V, the internal

clamp voltage for the ITH pin drops from 2.4V to around

1.3V, which reduces the inductor valley current level to

about30%ofitsmaximumvalue.Foldbackcurrentlimiting

is disabled at start-up.

If the MODE/PLLIN pin is left open or connected to signal

ground,thechannelwilltransitionintodiscontinuousmode

Frequency Selection and External Clock

Synchronization

operation,whereacurrentreversalcomparator(I )shuts

REV

off the bottom MOSFET (M ) as the inductor current ap-

B

proaches zero, thus preventing negative inductor current

and improving light-load efficiency. In this mode, both

switches can remain off for extended periods of time. As

the output capacitor discharges by load current and the

output voltage droops lower, EA will eventually move the

ITH voltage above the zero current level (0.8V) to initiate

another switching cycle.

An internal oscillator (clock generator) provides phase-

interleaved internal clock signals for individual channels

to lock up to. The switching frequency and phase of each

switching channel is independently controlled by adjust-

ing the top MOSFET turn-on time (on-time) through the

one-shot timer. This is achieved by sensing the phase

relationship between a top MOSFET turn-on signal and

its internal reference clock through a phase detector,

and the time interval of the one-shot timer is adjusted on

a cycle-by-cycle basis, so that the rising edge of the top

MOSFET turn-on is always trying to synchronize to the

internal reference clock signal for the respective channel.

Power Good and Fault Protection

Each PGOOD pin is connected to an internal open-drain

N-channelMOSFET. Anexternalresistororcurrentsource

can be used to pull this pin up to 6V (e.g., V

or

OUT1,2

DRV ). Overvoltage or undervoltage comparators (OV,

Thefrequencyoftheinternaloscillatorcanbeprogrammed

CC

UV) turn on the MOSFET and pull the PGOOD pin low

when the feedback voltage is outside the 7.5% window

of the reference voltage. The PGOOD pin is also pulled low

when the channel’s RUN pin is below the 1.2V threshold

(hysteresis applies), or in undervoltage lockout (UVLO).

from 200kHz to 2MHz by connecting a resistor, R , from

T

theRT pintosignalground(SGND).TheRT pinisregulated

to 1.2V internally.

For applications with stringent frequency or interference

requirements, an external clock source connected to the

MODE/PLLIN pin can be used to synchronize the internal

clock signals through a clock phase-locked loop (Clock

PLL).TheLTC3838-1operatesinforcedcontinuousmode

of operation when it is synchronized to the external clock.

The external clock frequency has to be within 30% of the

internal oscillator frequency for successful synchroniza-

tion. The clock input levels should be no less than 2V for

38381f

When the feedback voltage is within the 7.5% window,

the open-drain NMOS is turned off and the pin is pulled

up by the external source. The PGOOD pin will indicate

power good immediately after the feedback is within the

window. But when a feedback voltage of a channel goes

out of the window, there is an internal 50µs delay before

its PGOOD is pulled low.

16

For more information www.linear.com/3838-1

LTC3838-1

OPERATION ^{(Refer to Functional Diagram)}

“high” and no greater than 0.5V for “low”. The MODE/

PLLIN pin has an internal 600k pull-down resistor.

Single-Output PolyPhase Configurations

To use LTC3838-1 for a 2-phase single output step-down

+

controller: Tie the V

pin to INTV , which will

OUTSENSE1

CC

Multichip Operations

disable channel 1’s error amplifier and internally connect

ITH2 to ITH1. Tie the compensation R-C components

to the ITH2 pin. The ITH1 pin can be either left open or

shorted to ITH2 externally. The TRACK/SS1 and PGOOD1

pins become defunct and can be left open. Note that the

RUN1 and RUN2, as well as DTR1 and DTR2 pins still

functionforthetwochannelsindividually,thereforeshould

be shorted externally for single-output applications. Set

PHASMD to SGND or FLOAT so that the two channels are

180° out-of-phase. Efficiency losses may be substantially

reduced because the peak current drawn from the input

capacitor is effectively divided by the number of phases

used and power loss is proportional to the RMS current

squared. A 2-phase implementation can reduce the input

path power loss by up to 75%.

The PHASMD pin determines the relative phases between

the internal reference clock signals for the two channels

as well as the CLKOUT signal, as shown in Table 2. The

phases tabulated are relative to zero degree (0°) being

defined as the rising edge of the internal reference clock

signal of channel 1. The CLKOUT signal can be used to

synchronizeadditionalpowerstagesinamultiphasepower

supplysolutionfeedingeitherasinglehighcurrentoutput,

or separate outputs.

The system can be configured for up to 12-phase opera-

tion with a multichip solution. Typical configurations are

shown in Table 3 to interleave the phases of the channels.

Table 2

PHASMD

Channel 1

Channel 2

CLKOUT

SGND

0°

FLOAT

0°

INTV

CC

To makeasingle-outputconverterofthreeormorephases,

additionalLTC3838-1ICscanbeused.Thefirstchipshould

be tied the same way as the 2-phase above. If only one

more channel of an additional LTC3838-1 is needed, use

channel 2 for the additional phase:

0°

180°

60°

180°

90°

240°

120°

Table 3

• Tie the ITH2 pin to the ITH2 pin of the first chip

• Tie the RUN2 pin to the RUN pins of the first chip

NUMBER OF

PHASES

NUMBER OF

LTC3838-1

PIN CONNECTIONS

[PIN NAME (CHIP NUMBER)]

2

3

1

2

PHASMD(1) = FLOAT or SGND

+

• Tie the V

pin to the V

pin of the first chip

PHASMD(1) = INTV

MODE/PLLIN(2) = CLKOUT(1)

DFB2

CC

–

4

6

2

3

PHASMD(1) = FLOAT

PHASMD(2) = FLOAT or SGND

MODE/PLLIN(2) = CLKOUT(1)

• Tie the TRACK/SS2 pin to the TRACK/SS2 pin of the

first chip

PHASMD(1) = SGND

PHASMD(2) = SGND

MODE/PLLIN(2) = CLKOUT(1)

PHASMD(3) = FLOAT or SGND

MODE/PLLIN(3) = CLKOUT(2)

If both channels are needed, the additional LTC3838-1

chip should be tied the same way as the first LTC3838-1

chip to disable the second channel 1’s EA:

12

6

PHASMD(1) = SGND

PHASMD(2) = SGND

+

• Tie the V

pin to the chip’s own INTV

CC

OUTSENSE1

MODE/PLLIN(2) = CLKOUT(1)

PHASMD(3) = FLOAT

• Tie the ITH2 pin to the ITH2 pin of the first chip

• Tie the RUN pins to the RUN pins of the first chip

MODE/PLLIN(3) = CLKOUT(2)

PHASMD(4) = SGND

MODE/PLLIN(4) = CLKOUT(3)

PHASMD(5) = SGND

+

• Tie the V

pin to the V

pin of the first chip

DFB2

MODE/PLLIN(5) = CLKOUT(4)

PHASMD(6) = FLOAT or SGND

MODE/PLLIN(6) = CLKOUT(5)

–

• Tie the TRACK/SS2 pin to the TRACK/SS2 pin of the

first chip

38381f

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For more information www.linear.com3838-1

LTC3838-1

APPLICATIONS INFORMATION

Once the required output voltage and operating frequency

have been determined, external component selection is

driven by load requirement, and begins with the selec-

tion of inductors and current sense method (either sense

The maximum output voltages on both channels can be

set up to 5.5V, as limited by the maximum voltage that

can be applied on the SENSE pins. For example, if V

OUT1

is programmed to 5.5V and the output ground reference

is sitting at 0.5V with respect to SGND, then the absolute

value of the output will be 6V with respect to SGND, which

is the absolute maximum voltage that can be applied on

the SENSE pins.

resistors R

or inductor DCR sensing). Next, power

SENSE

MOSFETs are selected. Finally, input and output capaci-

tors are selected.

Output Voltage Programming

+

TheV

andV

arehighimpedancepinswith

OUTSENSE1

DFB2

As shown in Figure 1, external resistor dividers are used

from the regulated outputs to their respective ground

references to program the output voltages. On chan-

noinputbiascurrentotherthanleakageinthenArange.The

–

V

pin has about 25µA of current flowing out of

DFB2

OUTSENSE1

–

thepin.TheV

pinhasabout6μAflowingoutofthepin.

+

nel 1, the resistive divider is tapped by the V

OUTSENSE1

Differentialoutputsensingallowsformoreaccurateoutput

regulation in high power distributed systems having large

line losses. Figure 2 illustrates the potential variations in

the power and ground lines due to parasitic elements.

The variations may be exacerbated in multi-application

systems with shared ground planes. Without differential

outputsensing, these variations directly reflect as an error

intheregulatedoutputvoltage.TheLTC3838-1differential

output sensing can correct for up to 500mV of common-

mode deviation in the output’s power and ground lines on

channel 1, and 200mV on channel 2.

pin, and the ground reference is remotely sensed by the

–

V

pin; this voltage is sensed differentially. On

OUTSENSE1

channel 2, add a 3rd resistor with value equal to the two

voltage-divider resistors in parallel (or simply add two

parallel resistors equal to each of the two voltage divider

resistors). By regulating the tapped (differential) feedback

voltagestotheinternalreference0.6V,theresultingoutput

voltages are:

+

–

V

– V

= 0.6V • (1 + R

/R

)

OUT1

DFB2 FB1

and

+

–

The LTC3838-1’s differential output sensing schemes are

distinct from conventional schemes where the regulated

output and its ground reference are directly sensed with

a difference amplifier whose output is then divided down

with an external resistor divider and fed into the error

amplifier input. This conventional scheme is limited by

the common mode input range of the difference amplifier

and typically limits differential sensing to the lower range

of output voltages.

V

– V

= 0.6V • (1 + R

/R

)

OUT2

DFB2 FB1

The minimum (differential) V

reference 0.6V. To program V

is limited to the internal

OUT1

= 0.6V, remove R

OUT1

FB1

(effectively R = ∞), and/or short out R (effectively

FB1

FB2

R

=0).To programV

=0.6V,R canberemoved,

DFB1 DFB2

FB2

OUT2

DFB1

and the R

= R

//R uses the same value as

DFB1

DFB3

R

, as effectively R

= ∞.

DFB2

TO PROGRꢁM

V

= 0.6V,

OUT2

REMOVE R

+

V

OUT2

ꢁND

DFB2

+

DFB1

= R

V

OUT1

C

USE R

DFB3

LTC3838-1

R

FB2

DFB2

+

C

OUT2

V

OUT1

OUTSENSE1

DFB2

FB1

DFB1

–

V

OUTSENSE1

–

V

OUT1

R

=

OUT2

DFB3

//R

DFB1 DFB2

REMOTELY-SENSED

POWER GROUND 1,

±±00ꢀV MꢁA ꢂv SGND

REMOTELY-SENSED

POWER GROUND 2,

±200ꢀV MꢁA ꢂv SGND

SGND

38381 F01

Figure 1. Setting Output Voltage

38381f

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For more information www.linear.com/3838-1

LTC3838-1

APPLICATIONS INFORMATION

+

C

IN

V

C

IN

–

POWER TRACE

PARASITICS

M

T

L

LTC3838-1

+

V

DROP(PWR)

M

B

–

V

OUTSENSE1

I

LOAD

OUT

I

R

FB1

LOAD

FB2

GROUND TRACE

PARASITICS

V

DROP(GND)

OTHER CURRENTS

FLOWING IN

SHARED GROUND

PLANE

38381 F02

Figure 2. Differential Output Sensing Used to Correct Line Loss Variations

in a High Power Distributed System with a Shared Ground Plane

The switching frequency of the LTC3838-1 can be pro-

grammed from 200kHz to 2MHz by connecting a resistor

from the RT pin to signal ground. The value of this resistor

can be chosen according to the following formula:

The LTC3838-1 allows for seamless differential output

sensingbysensingtheresistivelydividedfeedbackvoltage

differentially. This allows for differential sensing in the full

output range from 0.6V to 5.5V. Channel 1’s difference

amplifier (DIFFAMP) has a bandwidth of around 8MHz,

and channel 2’s feedback amplifier has a bandwidth of

around 4MHz, both high enough so as to not affect main

loop compensation and transient behavior.

41550

R kΩ =

– 2.2

[

]

T

f kHz

[

]

The overall controller system, including the clock PLL

and switching channels, has a synchronization range of

no less than 30% around this programmed frequency.

Therefore, during external clock synchronization be sure

thattheexternalclockfrequencyiswithinthis 30%range

of the RT programmed frequency. It is advisable that the

RT programmed frequency be equal the external clock

for maximum synchronization margin. Refer to the Phase

and Frequency Synchronization section for more details.

To avoid noise coupling into the feedback voltages, the

+

resistordividersshouldbeplacedclosetotheV

OUTSENSE1

–

+

–

and V

, or V

and V

pins. Remote

OUTSENSE1

DFB2

output and ground traces should be routed together

as a differential pair to the remote output. For best ac-

curacy, these traces to the remote output and ground

should be connected as close as possible to the desired

regulation point.

Switching Frequency Programming

Inductor Value Calculation

The choice of operating frequency is a trade-off between

efficiencyandcomponentsize.Loweringtheoperatingfre-

quencyimprovesefficiencybyreducingMOSFETswitching

losses but requires larger inductance and/or capacitance

to maintain low output ripple voltage. Conversely, raising

the operating frequency degrades efficiency but reduces

component size.

The operating frequency and inductor selection are inter-

relatedinthathigheroperatingfrequenciesallowtheuseof

smaller inductor and capacitor values. A higher frequency

generally results in lower efficiency because of MOSFET

gate charge losses. In addition to this basic trade-off, the

effect of inductor value on ripple current and low current

operation must also be considered.

38381f

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For more information www.linear.com3838-1

LTC3838-1

APPLICATIONS INFORMATION

The inductor value has a direct effect on ripple current.

very significant. Be sure to check with the manufacturer

on the frequency characteristics of the core material.

The inductor ripple current ∆I decreases with higher

L

inductance or frequency and increases with higher V :

IN

Current Sense Pins

















V_OUT

f •L

V_OUT

∆I =

1–



Inductor current is sensed through voltage between

L





V

+

–

IN

SENSE andSENSE pins,theinputsoftheinternalcurrent

comparators. Care must be taken not to float these pins

Accepting larger values of ∆I allows the use of low induc-

L

+

during normal operation. The SENSE pins are quasi-high

tances, but results in higher output voltage ripple, higher

+

impedance inputs. There is no bias current into a SENSE

ESRlossesintheoutputcapacitor,andgreatercorelosses.

–

pin when its corresponding channel’s SENSE pin ramps

A reasonable starting point for setting ripple current is ∆I

L

up from below 1.1V and stays below 1.4V. But there is a

= 0.4 • I

. The maximum ∆I occurs at the maximum

MAX

L

+

small (~1μA) current flowing into a SENSE pin when its

input voltage. To guarantee that ripple current does not

exceed a specified maximum, the inductance should be

chosen according to:

–

corresponding SENSE pin ramps down from 1.4V and

–

staysabove1.1V.SuchcurrentsalsoexistonSENSE pins.

–

But in addition, each SENSE pin has an internal 500k









resistor to SGND. The resulted current (V /500k) will

OUT

V_OUT

f • ∆I_L(MAX)

V_OUT



–



L =

1–

dominate the total current flowing into the SENSE pins.

_IN(MAX)

V







+

–

SENSE and SENSE pin currents have to be taken into

account when designing either R

current sensing.

or DCR inductor

SENSE

Inductor Core Selection

Once the value for L is known, the type of inductor must

be selected. The two basic types are iron powder and fer-

rite. The iron powder types have a soft saturation curve

which means they do not saturate hard like ferrites do.

However, iron powder type inductors have higher core

losses. Ferrite designs have very low core loss and are

preferred at high switching frequencies, so design goals

canconcentrateoncopperlossandpreventingsaturation.

Current Limit Programming

The current sense comparators’ maximum trip voltage

+

–

between SENSE and SENSE (or V

), when ITH

SENSE(MAX)

is clamped at its maximum 2.4V, is set by the V

pin.

RNG

Connecting V

typical; connecting V

at 60mV typical.

to SGND sets the V

at 30mV

RNG

SENSE(MAX)

to INTV sets the V

RNG

CC

SENSE(MAX)

The valley current mode control loop does not allow the

inductorcurrentvalleytoexceedV .Butnotethat

Core loss is independent of core size for a fixed inductor

value, but it is very dependent on inductance selected. As

inductanceincreases,corelossesgodown.Unfortunately,

increased inductance requires more turns of wire and

therefore copper losses will increase.

SENSE(MAX)

the peak inductor current is higher than this valley current

limitbytheamountoftheinductorripplecurrent.Alsowhen

calculating the peak current limit, allow sufficient margin

to account for the tolerance of V

as given in the

SENSE(MAX)

Ferrite core material saturates hard, which means that in-

ductance collapses abruptly when the peak design current

is exceeded. This results an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

Electrical Characteristics table, and variations in values of

external components (such as the inductor), as well as

the range of the input voltage (since ripple current ∆I is

L

a function of input voltage).

Eitherthelowvalueseriescurrentsensingresistor(R

)

SENSE

A variety of inductors designed for high current, low

voltage applications are available from manufacturers

such as Sumida, Panasonic, Coiltronics, Coilcraft, Toko,

Vishay, Pulse and Würth. In designs of higher switching

frequency, especially in the MHz range, core loss can be

or the DC resistance of the inductor (DCR) can be used

to monitor the inductor current. The choice between the

two current sensing schemes is largely a design trade-

off among accuracy, power consumption, and cost. The

38381f

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For more information www.linear.com/3838-1

LTC3838-1

APPLICATIONS INFORMATION

R

SENSE

method offers more precise control of the current

sense voltage, V

, set by the V

pin, and

SENSE(MAX)

maximum inductor ripple current ∆I

RNG

, the value of

limit but the resistor will dissipate loss. The DCR method

saves the cost of the sense resistors and may offer bet-

ter efficiency, especially in high current applications, but

tolerance and the variation over temperature in the DCR

value usually requires larger design margins.

L(MAX)

R

can be chosen as:

SENSE

V_SENSE(MAX)

R_SENSE

=

∆I_L(MAX)

I_OUT(MAX)

–

2

R

SENSE

Inductor Current Sensing

Conversely, given R

and I

, V

(set

SENSE

OUT(MAX) SENSE(MAX)

The LTC3838-1 can be configured to sense the inductor

currentsthrougheithercurrentsensingresistors(R

or inductor DC resistance (DCR). The current sensing

resistors provide the most accurate current limits for the

controller.

by the V

pin) can be determined from the above equa-

RNG

)

SENSE

tion. To ensure the maximum output current, sufficient

margin should be built in the calculations to account for

variations of the ICs under different operating conditions

and tolerances of external components.

AtypicalR

inductorcurrentsensingschemeisshown

SENSE

Because of possible PCB noise in the current sensing

in Figure 3a. The filter components (R , C ) need to be

F

loop, the current sensing voltage ripple ∆V

= ∆I •

SENSE

L

placed close to the IC. The positive and negative sense

traces need to be routed as a differential pair close to-

getherandKelvin(4-wire)connectedunderneaththesense

resistor,asshowninFigure3b.Sensingcurrentelsewhere

caneffectivelyaddparasiticinductancetothecurrentsense

element, degrading the information at the sense terminals

and making the programmed current limit unpredictable.

R

SENSE

also needs to be checked in the design to get a

good signal-to-noise ratio. In general, for a reasonably

is recommended as

good PCB layout, 10mV of ∆V

SENSE

a conservative number to start with, either for R

Inductor DCR sensing applications.

or

SENSE

For today’s highest current density solutions the value

of the sense resistor can be less than 1mΩ and the

peak sense voltage can be as low as 20mV. In addition,

inductor ripple currents greater than 50% with operation

up to 2MHz are becoming more common. Under these

conditions, the voltage drop across the sense resistor’s

parasitic inductance becomes more relevant. A small RC

filter placed near the IC has been traditionally used to re-

duce the effects of capacitive and inductive noise coupled

in the sense traces on the PCB. A typical filter consists of

two series 10Ω resistors connected to a parallel 1000pF

capacitor, resulting in a time constant of 20ns.

R

is chosen based on the required maximum output

SENSE

current.Giventhemaximumcurrent,I

,maximum

OUT(MAX)

R

RESISTOR

SENSE

AND

PARASITIC INDUCTANCE

R

ESL

V

OUT

LTC3838-1

SENSE

C • 2R ≤ ESL/R

F

S

POLE-ZERO

R

F

CANCELLATION

+

–

C

F

38381 F03a

SENSE

This same RC filter, with minor modifications, can be

used to extract the resistive component of the current

sense signal in the presence of parasitic inductance.

For example, Figure 4a illustrates the voltage waveform

across a 2mΩ sense resistor with a 2010 footprint for a

1.2V/15Aconverteroperatingat100%load.Thewaveform

is the superposition of a purely resistive component and a

purely inductive component. It was measured using two

scope probes and waveform math to obtain a differential

measurement. Based on additional measurements of the

FILTER COMPONENTS

PLACED NEAR SENSE PINS

Figure 3a. R_SENSECurrent Sensing

TO SENSE FILTER,

NEXT TO THE CONTROLLER

C

OUT

38381 F03b

R

SENSE

Figure 3b. Sense Lines Placement with Sense Resistor

inductor ripple current and the on-time and off-time of

38381f

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LTC3838-1

APPLICATIONS INFORMATION

the top switch, the value of the parasitic inductance was

determined to be 0.5nH using the equation:

–

Note that the SENSE1 and SENSE2 pins are also used

for sensing the output voltage for the adjustment of top

gate on time, t . For this purpose, there is an additional

ON

V

t_ON• t_OFF

t_ON+ t_OFF

ESL(STEP)

–

internal 500k resistor from each SENSE pin to SGND,

ESL =

•

∆I_L

therefore there is an impedance mismatch with their cor-

+

responding SENSE pins. The voltage drop across the

where V

is the voltage step caused by the ESL

ESL(STEP)

R causes an offset in sense voltage. For example, with

F

and shown in Figure 4a, and t and t are top MOSFET

–

ON

OFF

R = 100Ω, at V

= V

= 5V, the sense-voltage

F

OUT

SENSE(OFFSET)

SENSE

on-time and off-time respectively. If the RC time constant

ischosentobeclosetotheparasiticinductancedividedby

the sense resistor (L/R), the resulting waveform looks re-

sistiveagain,asshowninFigure4b.Forapplicationsusing

offset V

• R /500k = 1mV. Such

SENSE F

small offset may seem harmless for current limit, but

could be significant for current reversal detection (I ),

REV

causingexcessnegativeinductorcurrentatdiscontinuous

low V

, check the sense resistor manufacturer’s

SENSE(MAX)

mode. Also, at V

= 30mV, a mere 1mV offset

SENSE(MAX)

data sheet for information about parasitic inductance. In

the absence of data, measure the voltage drop directly

across the sense resistor to extract the magnitude of the

ESLstepandusetheequationabovetodeterminetheESL.

However, donotoverfilter. KeeptheRCtimeconstantless

than or equal to the inductor time constant to maintain a

will cause a significant shift of zero-current ITH voltage

by (2.4V – 0.8V) • 1mV/30mV = 53mV. Too much shift

maynotallowtheoutputvoltagetoreturntoitsregulated

value after the output is shorted due to ITH foldback.

Therefore, when a larger filter resistor R value is used,

F

it is recommended to use an external 500k resistor from

high enough ripple voltage on V

.

+

RSENSE

each SENSE pin to SGND, to balance the internal 500k

–

resistor at its corresponding SENSE pin.

The previous discussion generally applies to high density/

high current applications where I

> 10A and low

OUT(MAX)

inductorvaluesareused.ForapplicationswhereI

OUT(MAX)

V

SENSE

< 10A, set R to 10Ω and C to 1000pF. This will provide

20mV/DIV

F

V

ESL(STEP)

a good starting point.

The filter components need to be placed close to the IC.

The positive and negative sense traces need to be routed

as a differential pair and Kelvin (4-wire) connected to the

sense resistor.

38381 F04a

500ns/DIV

Figure 4a. Voltage Waveform Measured

Directly Across the Sense Resistor

DCR Inductor Current Sensing

For applications requiring higher efficiency at high load

currents, the LTC3838-1 is capable of sensing the volt-

age drop across the inductor DCR, as shown in Figure 5.

The DCR of the inductor represents the small amount of

DC winding resistance, which can be less than 1mΩ for

today’s low value, high current inductors.

V

SENSE

20mV/DIV

In a high current application requiring such an inductor,

conductionlossthroughasenseresistorwouldcostseveral

points of efficiency compared to DCR sensing.

38381 F04b

500ns/DIV

Figure 4b. Voltage Waveform Measured After the

Sense Resistor Filter. C_F= 1000pF, R_F= 100Ω

The inductor DCR is sensed by connecting an RC filter

across the inductor. This filter typically consists of one or

38381f

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LTC3838-1

APPLICATIONS INFORMATION

IfV

iswithinthemaximumsensevoltage(30mV

SENSE(MAX)

INDUCTOR

or 60mV typical) of the LTC3838-1 as set by the V

pin,

RNG

L

DCR

then the RC filter only needs R1. If V

then R2 may be used to scale down the maximum sense

voltage so that it falls within range.

is higher,

V

OUT

SENSE(MAX)

C

OUT

L/DCR = (R1||R2) C1

R1

LTC3838-1

SENSE

+

–

The maximum power loss in R1 is related to duty cycle,

and will occur in continuous mode at the maximum input

voltage:

R2

(OPT)

C1

38381 F05

SENSE

C1 NEAR SENSE PINS

V

_IN(MAX)– V_OUT• V

(

)

OUT

P_LOSSR1 =

( )

Figure 5. DCR Current Sensing

R1

tworesistors(R1andR2)andonecapacitor(C1)asshown

in Figure 5. If the external (R1||R2) • C1 time constant is

chosen to be exactly equal to the L/DCR time constant, the

voltage drop across the external capacitor is equal to the

voltage drop across the inductor DCR multiplied by R2/

(R1 + R2). Therefore, R2 may be used to scale the voltage

across the sense terminals when the DCR is greater than

the target sense resistance. C1 is usually selected in the

range of 0.01µF to 0.47µF. This forces R1||R2 to around

2k to 4k, reducing error that might have been caused by

the SENSE pins’ input bias currents.

Ensure that R1 has a power rating higher than this value.

If high efficiency is necessary at light loads, consider this

power loss when deciding whether to use DCR sensing or

R

sensing. Light load power loss can be modestly

SENSE

higher with a DCR network than with a sense resistor due

to the extra switching losses incurred through R1. How-

ever, DCR sensing eliminates a sense resistor, reduces

conduction losses and provides higher efficiency at heavy

loads.Peakefficiencyisaboutthesamewitheithermethod.

To maintain a good signal-to-noise ratio for the current

sense signal, start with a ∆V

of 10mV. For a DCR

SENSE

Resistor R1 should be placed close to the switching node,

to prevent noise from coupling into sensitive small-signal

nodes. Capacitor C1 should be placed close to the IC pins.

sensing application, the actual ripple voltage will be de-

termined by:

V – V

R1•C1

V_OUT

IN

OUT

∆V_SENSE

=

•

The first step in designing DCR current sensing is to

determine the DCR of the inductor. Where provided, use

themanufacturer’smaximumvalue,usuallygivenat25°C.

Increase this value to account for the temperature coef-

ficient of resistance, which is approximately 0.4%/°C. A

V • f

IN

Power MOSFET Selection

Two external N-channel power MOSFETs must be selected

for each channel of the LTC3838-1 controller: one for the

top (main) switch and one for the bottom (synchronous)

conservative value for inductor temperature T is 100°C.

L

TheDCRoftheinductorcanalsobemeasuredusingagood

RLC meter, but the DCR tolerance is not always the same

and varies with temperature; consult the manufacturers’

data sheets for detailed information.

switch. The gate drive levels are set by the DRV voltage.

CC

This voltage is typically 5.3V. Pay close attention to the

BV

specification for the MOSFETs as well; most of the

DSS

logic-level MOSFETs are limited to 30V or less.

From the DCR value, V

is easily calculated as:

SENSE(MAX)

Selection criteria for the power MOSFETs include the on-

V_SENSE(MAX)= DCR_MAX(25°C)

resistance, R , Miller capacitance, C , input

DS(ON) MILLER





– 25°C

)

voltage and maximum output current. Miller capacitance,

, can be approximated from the gate charge curve

• 1+ 0.4% T

(

L(MAX)





C

MILLER









∆I_L

2

usually provided on the MOSFET manufacturers’ data

• I

–



 ^OUT(MAX)

sheet. C

isequaltotheincreaseingatechargealong

MILLER

the horizontal axis while the curve is approximately flat

38381f

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APPLICATIONS INFORMATION

(ortheparameterQ ifspecifiedonamanufacturer’sdata

whereT isestimatedjunctiontemperatureoftheMOSFET

J

GD

sheet), divided by the specified V test voltage:

and T is ambient temperature.

DS

A

Q_GD

V_DS(TEST)

C Selection

C_MILLER

≅

IN

In continuous mode, the source current of the top

N-channel MOSFET is a square wave of duty cycle V

/

OUT

When the IC is operating in continuous mode, the duty

cycles for the top and bottom MOSFETs are given by:

V . To prevent large voltage transients, a low ESR input

IN

capacitor sized for the maximum RMS current must be

used. The worst-case RMS current occurs by assuming

a single-phase application. The maximum RMS capacitor

current is given by:

V_OUT

D_TOP

=

V

IN

V_OUT

D_BOT= 1–

V

V_OUT

V

IN

V_OUT

IN

I_RMS≅ I_OUT(MAX)

•

– 1

V

IN

The MOSFET power dissipations at maximum output

current are given by:

This formula has a maximum at V_IN= 2V_OUT, where

I_RMS= I_OUT(MAX)/2. This simple worst-case condition

is commonly used for design because even significant

deviations do not offer much relief. Note that capacitor

manufacturers’ ripple current ratings are often based on

only 2000 hours of life. This makes it advisable to further

derate the capacitor or to choose a capacitor rated at a

highertemperaturethanrequired.Severalcapacitorsmay

also be paralleled to meet size or height requirements in

the design. Due to the high operating frequency of the

LTC3838-1, additional ceramic capacitors should also be

used in parallel for C_INclose to the IC and power switches

to bypass the high frequency switching noises. Typically

multipleX5RorX7Rceramiccapacitorsareputinparallel

with either conductive-polymer or aluminum-electrolytic

types of bulk capacitors. Because of its low ESR, the

ceramic capacitors will take most of the RMS ripple cur-

rent.Vendorsdonotconsistentlyspecifytheripplecurrent

rating for ceramics, but ceramics could also fail due to

excessiveripplecurrent.Alwaysconsultthemanufacturer

if there is any question.

P_TOP= D_TOP•I_OUT(MAX)²•R_DS(ON)(MAX)1+ δ + V

2

(

)

IN

















I_OUT(MAX)

R_TG(UP)

R_TG(DOWN)

•

•C

+

• f

_MILLER





2

V

_DRVCC– V_MILLER

V_MILLER



2

P

BOT

= D

• I

• R

• (1 + δ )

BOT OUT(MAX) DS(ON)(MAX)

whereδ isthetemperaturedependencyofR

,R

DS(ON) TG(UP)

is the TG pull-up resistance, and R

is the TG pull-

TG(DOWN)

down resistance. V

is the Miller effect V voltage

MILLER

GS

and is taken graphically from the MOSFET’s data sheet.

2

BothMOSFETshaveI RlosseswhilethetopsideN-channel

equation includes an additional term for transition losses,

which are highest at high input voltages. For V < 20V,

IN

the high current efficiency generally improves with larger

MOSFETs, whileforV >20V, thetransitionlossesrapidly

IN

increasetothepointthattheuseofahigherR

device

DS(ON)

withlowerC

actuallyprovideshigherefficiency.The

MILLER

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

short-circuit when the synchronous switch is on close to

100% of the period.

Figure6representsasimplifiedcircuitmodelforcalculat-

ing the ripple currents in each of these capacitors. The

input inductance (L_IN) between the input source and the

inputoftheconverterwillaffecttheripplecurrentthrough

the capacitors. A lower input inductance will result in less

ripple current through the input capacitors since more

ripple current will now be flowing out of the input source.

The term (1 + δ) is generally given for a MOSFET in the

form of a normalized R

vs temperature curve in the

DS(ON)

power MOSFET data sheet. For low voltage MOSFETs,

0.5% per degree (°C) can be used to estimate δ as an

approximation of percentage change of R

:

DS(ON)

δ = 0.005/°C • (T – T )

J

A

38381f

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LTC3838-1

APPLICATIONS INFORMATION

L

IN

1µH

showstheinputcapacitorRMSripplecurrentsnormalized

against the DC output currents with respect to the duty

cycle. This graph can be used to estimate the maximum

RMS capacitor current for a multiple-phase application,

assuming the channels are identical and their phases are

fully interleaved.

ESR

(BULK)

(CERAMIC)

+

V

I

PULSE(PHASE2)

ESL

IN

PULSE(PHASE1)

(BULK)

(CERAMIC)

–

+

C

IN(CERAMIC)

IN(BULK)

38381 F06

Figure 7 shows that the use of more phases will reducethe

ripple current through the input capacitors due to ripple

current cancellation. However, since LTC3838-1 is only

truly phase-interleavedatsteady state, transient RMS cur-

rents could be higher than the curves for the designated

number of phase. Therefore, it is advisable to choose

capacitors by taking account the specific load situations

of the applications. It is always the safest to choose input

capacitors’ RMS current rating closer to the worst case of

a single-phase application discussed above, calculated by

assuming the loss that would have resulted if controller

channels switched on at the same time.

Figure 6. Circuit Model for Input Capacitor

Ripple Current Simulation

For simulations with this model, look at the ripple current

during steady-state for the case where one phase is fully

loaded and the other was not loaded. This will in general

be the worst case for ripple current since the ripple cur-

rentfromonephasewillnotbecancelledbyripplecurrent

from the other phase.

Note that the bulk capacitor also has to be chosen for

RMS rating with ample margin beyond its RMS current

persimulationwiththecircuitmodelprovided.Foralower

V_INrange, a conductive-polymer type (such as Sanyo

OS-CON) can be used for its higher ripple current rating

and lower ESR. For a wide V_INrange that also require

highervoltagerating,aluminum-electrolyticcapacitorsare

more attractive since it can provide a larger capacitance

for more damping. An aluminum-electrolytic capacitor

with a ripple current rating that is high enough to handle

all of the ripple current by itself will be very large. But

when in parallel with ceramics, an aluminum-electrolytic

capacitor will take a much smaller portion of the RMS

ripple current due to its high ESR. However, it is crucial

that the ripple current through the aluminum-electrolytic

capacitor should not exceed its rating since this will

produce significant heat, which will cause the electrolyte

inside the capacitor to dry over time and its capacitance

to go down and ESR to go up.

0.6

0.5

1-PHASE

0.4

2-PHASE

3-PHASE

4-PHASE

0.3

6-PHASE

0.2

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

IN

O

38381 F07

Figure ꢀ. Normalized RMS Input Ripple Current

However,itisgenerallynotneededtosizetheinputcapaci-

tor for such worst-case conditions where on-times of the

phases coincide all the time. During a load step event, the

overlap of on-time will only occur for a small percentage

of time, especially when duty cycles are low. A transient

event where the switch nodes align for several cycles at

a time should not damage the capacitor. In most applica-

tions, sizing the input capacitors for 100% steady-state

load should be adequate. For example, a microprocessor

load may cause frequent overlap of the on-times, which

makes the ripple current higher, but the load current may

The benefit of PolyPhase operation is reduced RMS cur-

rents and therefore less power loss on the input capaci-

tors. Also, the input protection fuse resistance, battery

resistance, and PC board trace resistance losses are also

reduced due to the reduced peak currents in a PolyPhase

system. The details of a close form equation can be found

in Application Note 77 High Efficiency, High Density, Poly-

Phase Converters for High Current Applications. Figure 7

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LTC3838-1

APPLICATIONS INFORMATION

rarely be at 100% of I

. Using the worst-case load

compensated for by using capacitors of very low ESR to

maintain the ripple voltage.

OUT(MAX)

current should already have margin built in for transient

conditions.

Multiple capacitors placed in parallel may be needed to

meet the ESR and RMS current handling requirements.

Dry tantalum, special polymer, aluminum electrolytic and

ceramiccapacitorsareallavailableinsurfacemountpack-

ages. Special polymer capacitors offer very low ESR but

havelowercapacitancedensitythanothertypes.Tantalum

capacitors have the highest capacitance density but it is

important to only use types that have been surge tested

foruseinswitchingpowersupplies.Aluminumelectrolytic

capacitors have significantly higher ESR, but can be used

in cost-sensitive applications provided that consideration

is given to ripple current ratings and long-term reliability.

The V sources of the top MOSFETs should be placed

IN

close to each other and share common C (s). Separating

IN

the sources and C may produce undesirable voltage and

IN

current resonances at V .

IN

A small (0.1µF to 1µF) bypass capacitor between the IC’s

V pin and ground, placed close to the IC, is suggested.

IN

A 2.2Ω to 10Ω resistor placed between C and the V

IN

pin is also recommended as it provides further isolation

from switching noise of the two channels.

C

Selection

OUT

CeramiccapacitorshaveexcellentlowESRcharacteristics

but can have a high voltage coefficient and audible piezo-

electriceffects.ThehighQofceramiccapacitorswithtrace

inductance can also lead to significant ringing. Whenused

asinputcapacitors,caremustbetakentoensurethatring-

ing from inrush currents and switching does not pose an

overvoltage hazard to the power switches and controller.

The selection of output capacitance C

is primarily

OUT

determined by the effective series resistance, ESR, to

minimize voltage ripple. The output voltage ripple ∆V

in continuous mode is determined by:

,

OUT









1

∆V_OUT≤ ∆I R

+

_L

ESR

8 • f •C_OUT



Forhighswitchingfrequencies,reducingoutputrippleand

betterEMIfilteringmayrequiresmallvaluecapacitorsthat

have low ESL (and correspondingly higher self-resonant

frequencies) to be placed in parallel with larger value

capacitors that have higher ESL. This will ensure good

noise and EMI filtering in the entire frequency spectrum

of interest. Even though ceramic capacitors generally

have good high frequency performance, small ceramic

capacitors may still have to be parallel connected with

large ones to optimize performance.

where f is operating frequency, and ∆I is ripple current

L

in the inductor. The output ripple is highest at maximum

input voltage since ∆I increases with input voltage. Typi-

L

cally, once the ESR requirement for C

has been met,

OUT

the RMS current rating generally far exceeds that required

from ripple current.

In multiphase single-output applications, it is advisable to

considerripplerequirementsatspecificloadconditions.At

steady state, the LTC3838-1’s individual phases are inter-

leaved, and their ripples cancel each other at the output,

High performance through-hole capacitors may also be

used, but an additional ceramic capacitor in parallel is

recommendedtoreducetheeffectoftheirleadinductance.

Rememberalsotoplacehighfrequencydecouplingcapaci-

tors as close as possible to the power pins of the load.

so ripple on C

is reduced. During transient, when the

OUT

phases are not fully interleaved, the ripple cancellation

may not be as effective. While the worst-case ∆I is the

sum of the ∆I s of individual phases aligned during a

L

fast transient, such ripple tends to counteract the effect

of load transient itself and lasts for only a short time. For

example, during sudden load current increase, the phases

align to ramp up the total inductor current to quickly pull

Top MOSFET Driver Supply (C , D )

B

An external bootstrap capacitor, C , connected to the

B

BOOST pin supplies the gate drive voltage for the topside

the V

up from the droop.

OUT

MOSFET. ThiscapacitorischargedthroughdiodeD from

B

The choice of using smaller output capacitance increases

the ripple voltage due to the discharging term but can be

DRV whentheswitchnodeislow.WhenthetopMOSFET

CC

38381f

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turns on, the switch node rises to V and the BOOST pin

an internal switch. This switch remains on as long as the

IN

rises to approximately V + INTV . The boost capacitor

voltage applied to EXTV remains above the hysteresis

IN

CC

needs to store approximately 100 times the gate charge

required by the top MOSFET. In most applications a 0.1µF

to 0.47µF, X5R or X7R dielectric capacitor is adequate. It

is recommended that the BOOST capacitor be no larger

(around 200mV) below the switchover voltage. Using

EXTV allows the MOSFET driver and control power

CC

to be derived from the LTC3838-1’s switching regulator

output V

during normal operation and from the LDO

OUT

than 10% of the DRV capacitor, C

, to ensure that

when the output is out of regulation (e.g., start up, short

circuit). If more current is required through the EXTV

CC

DRVCC

the C

can supply the upper MOSFET gate charge

DRVCC

CC

and BOOST capacitor under all operating conditions. Vari-

able frequency in response to load steps offers superior

transient performance but requires higher instantaneous

gate drive. Gate charge demands are greatest in high

frequency low duty factor applications under high load

steps and at start-up.

than is specified, an external Schottky diode can be added

between the EXTV and DRV pins. Do not apply more

CC

than 6V to the EXTV pin and make sure that EXTV is

CC

less than V .

IN

Significant efficiency and thermal gains can be realized

by powering DRV from the switching converter output,

CC

since the V current resulting from the driver and control

IN

DRV Regulator and EXTV Power

CC

currentswillbescaledbyafactorof(DutyCycle)/(Switcher

TheLTC3838-1featuresaPMOSlowdropout(LDO)linear

Efficiency).

regulatorthatsuppliespowertoDRV fromtheV supply.

CC

IN

Tying the EXTV pin to a 5V supply reduces the junction

CC

The LDO regulates its output at the DRV

pin to 5.3V.

CC1

temperature in the previous example from 125°C to:

The LDO can supply a maximum current of 100mA and

must be bypassed to ground with a minimum of 4.7µF

ceramic capacitor. Good bypassing is needed to supply

the high transient currents required by the MOSFET gate

drivers and to minimize interaction between the channels.

T = 70°C + (42mA)(5V)(34°C/W) = 77°C

J

However, for 3.3V and other low voltage outputs, ad-

ditional circuitry is required to derive DRV power from

CC

the converter output.

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3838-1 to

be exceeded, especially if the LDO is active and provides

The following list summarizes the four possible connec-

tions for EXTV :

CC

1. EXTV left open (or grounded). This will cause INTV

CC

to be powered from the internal 5.3V LDO resulting

in an efficiency penalty of up to 10% at high input

voltages.

DRV . Power dissipation for the IC in this case is highest

CC

andisapproximatelyequaltoV • I

.Thegatecharge

IN DRVCC

current is dependent on operating frequency as discussed

intheEfficiencyConsiderationssection. Thejunctiontem-

perature can be estimated by using the equation given in

Note 2 of the Electrical Characteristics. For example, when

2. EXTV connecteddirectlytoswitchingconverteroutput

CC

V

OUT

ishigherthantheswitchovervoltage’shigherlimit

(4.8V). This provides the highest efficiency.

using the LDO, LTC3838-1’s DRV current is limited to

CC

3. EXTV connected to an external supply. If a 4.8V or

CC

less than 42mA from a 38V supply at T = 70°C:

A

greater external supply is available, it may be used to

T = 70°C + (42mA)(38V)(34°C/W) = 125°C

J

power EXTV providing that the external supply is

CC

sufficient for MOSFET gate drive requirements.

To prevent the maximum junction temperature from being

exceeded, the input supply current must be checked while

4. EXTV connected to anoutput-derived boost network.

CC

operatingincontinuousconductionmodeatmaximumV .

IN

For 3.3V and other low voltage converters, efficiency

gains can still be realized by connecting EXTV to an

When the voltage applied to the EXTV pin rises above

CC

output-derivedvoltagethathasbeenboostedtogreater

the switchover voltage (typically 4.6V), the V LDO is

IN

than 4.8V.

turnedoffandtheEXTV isconnectedtoDRV pinwith

CC

CC2

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Forapplicationswherethemaininputpowerneverexceeds

pins are pulled below the ~0.8V threshold, the part will

5.3V, tie the DRV

and DRV

pins to the V input

shut down all bias of INTV and DRV and be put in

CC1

CC2

IN

CC

through a small resistor, (such as 1Ω to 2Ω) as shown

in Figure 8 to minimize the voltage drop caused by the

gate charge current. This will override the LDO and will

micropower shutdown mode.

The RUN pins’ bias currents depend on the RUN voltages.

The bias current changes should be taken into account

when designing the external voltage divider UVLO circuit.

An internal proportional-to-absolute-temperature (PTAT)

pull-up current source (~1.2µA at 25°C) is constantlycon-

nected to this pin. When a RUN pin rises above 1.2V, the

corresponding channel’s TG and BG drives are turned on

and an additional 5µA temperature-independent pull-up

current is connected internally to the RUN pin. Pulling the

RUN pin to fall below 1.2V by more than an 80mV hyster-

esis turns off TG and BG of the corresponding channel,

and the additional 5µA pull-up current is disconnected.

prevent DRV from dropping too low due to the dropout

CC

voltage.MakesuretheDRV voltageexceedstheR

CC

DS(ON)

test voltage for the external MOSFET which is typically at

4.5V for logic-level devices.

LTC3838-1

DRV

CC2

CC1

R

DRVCC

V

IN

C

DRVCC

IN

As voltage on a RUN pin increases, typically beyond 3V,

its bias current will start to reverse direction and flow into

the RUN pin. Keep in mind that neither of the RUN pins

can sink more than 50µA; Even if a RUN pin may slightly

exceed 6V when sinking 50µA, a RUN pin should never

be forced to higher than 6V by a low impedance voltage

source to prevent faulty conditions.

38381 F08

Figure 8. Setup for V_IN≤ 5.3V

Input Undervoltage Lockout (UVLO)

The LTC3838-1 has two functions that help protect the

controller in case of input undervoltage conditions. An

Soft-Start and Tracking

internalUVLOcomparatorconstantlymonitorstheINTV

The LTC3838-1 has the ability to either soft-start by itself

with a capacitor or track the output of another channel or

an external supply. Note that the soft-start and tracking

features are achieved not by limiting the maximum output

currentofthecontroller,butbycontrollingtheoutputramp

voltage according to the ramp rate on the TRACK/SS pin.

CC

and DRV voltages to ensure that adequate voltages are

CC

present. The comparator enables internal UVLO signal,

whichlocksouttheswitchingactionofbothchannels,until

theINTV andDR

pinsareallabovetheirrespective

CC

VCC1,2

UVLO thresholds. The rising threshold (to release UVLO)

of the INTV is typically 4.2V, with 0.5V falling hysteresis

CC

When a channel is configured to soft-start by itself, a ca-

pacitor should be connected to its TRACK/SS pin. TRACK/

SS is pulled low until the RUN pin voltage exceeds 1.2V

and UVLO is released, at which point an internal current

(tore-enableUVLO).TheUVLOthresholdsforDR

are

VCC1,2

lower than that of INTV but higher than typical threshold

CC

voltagesofpowerMOSFETs, topreventthemfromturning

on without sufficient gate drive voltages.

of 1µA charges the soft-start capacitor, C , connected

SS

Generally for V > 6V, a UVLO can be set through moni-

to the TRACK/SS pin. Current-limit foldback is disabled

during this phase to ensure smooth soft-start or track-

ing. The soft-start or tracking range is defined to be the

voltage range from 0V to 0.6V on the TRACK/SS pin. The

total soft-start time can be calculated as:

IN

toring the V supply by using external voltage dividers

IN

at the RUN pins from V to SGND. To design the volt-

IN

age divider, note that both RUN pins have two levels

of threshold voltages. The precision gate-drive-enable

threshold voltage of 1.2V can be used to set a V to turn

IN

C_SS(µF)

on a channel’s switching. If resistor dividers are used on

t_SS(SEC)= 0.6(V)•

1(µA)

both RUN pins, when V is low enough and both RUN

IN

38381f

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LTC3838-1

APPLICATIONS INFORMATION

When one particular channel is configured to track an

external supply, a voltage divider can be used from the

external supply to the TRACK/SS pin to scale the ramp

rate appropriately. Two common implementations are co-

incidentaltrackingandratiometrictracking.Forcoincident

tracking, make the divider ratio from the external supply

the same as the divider ratio for the differential feedback

voltage. Ratiometric tracking could be achieved by using

a different ratio than the differential feedback.

By selecting different resistors, the LTC3838-1 can

achieve different modes of tracking including the two in

Figure 9. To implement the coincident tracking, connect

an additional resistive divider to V

and connect its

OUT1

midpoint to the TRACK/SS pin of the slave channel. The

ratio of this divider should be the same as that of the slave

channel’s feedback divider shown in Figure 9b. In this

tracking mode, V

must be set higher than V . To

OUT2

OUT1

implement the ratiometric tracking as shown in Figure 9,

the additional divider should be of the same ratio as the

master channel’s feedback divider.

Note that the 1µA soft-start capacitor charging current is

still flowing, producing a small offset error. To minimize

this error, select the tracking resistive divider values to be

small enough to make this offset error negligible.

Under the ratiometric mode, when the master channel’s

output experiences dynamic excursion (under load tran-

sient,forexample),theslavechanneloutputwillbeaffected

as well. For better output regulation, use the coincident

tracking mode instead of ratiometric, or use the additional

divider with a ratio of somewhere between coincident and

ratiometric tracking modes.

The LTC3838-1 allows the user to program how its two

channels’ outputs track each other ramping up or down.

Inthefollowingdiscussions,V

referstotheLTC3838-

OUT1

1’s output 1 as a master channel and V

refers to the

OUT2

LTC3838-1’s output 2 as a slave channel. In practice

though, either channel can be used as the master.

V

OUT1

V

OUT2

38381 F09a

TIME

Coincident Tracking

Ratiometric Tracking

Figure 9a. Two Different Modes of Output Tracking

+

V

OUT1

V

OUT1

OUT2

R

DFB2

FB2(1)

DFB2

DFB1

FB2(1)

FB1(1)

TO

V

TO

V

TO

DFB2

TO

DFB2

+

–

+

–

+

TRACK/SS2

V

OUTSENSE1

R

//R

DFB1 DFB2

//R

FB1(1)

DFB1

DFB1 DFB2

TO

–

V

OUTSENSE1

DFB2

–

SGND

V

OUT2

SGND

V

OUT2

SGND

OUT1

Coincident Tracking Setup

Ratiometric Tracking Setup

38381 F09b

Figure 9b. Setup for Coincident and Ratiometric Tracking

38381f

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LTC3838-1

APPLICATIONS INFORMATION

Phase and Frequency Synchronization

errors. The goal is to set the on-time programmed by V ,

IN

V

and R close to the steady-state on-time so that the

OUT

T

For applications that require better control of EMI and

switching noise or have special synchronization needs,

the LTC3838-1 can synchronize the turn-on of the top

MOSFET to an external clock signal applied to the MODE/

PLLIN pin. The applied clock signal needs to be within

30% of the RT programmed frequency to ensure proper

frequency and phase lock. The clock signal levels should

systemwillhavesufficientrangetocorrectforcomponent

andoperatingconditionvariations,ortosynchronizetothe

external clock. Note that there is an internal 500k resistor

–

+

on each SENSE pin to SGND, but not on the SENSE pin.

During dynamic transient conditions either in the line

voltage or load current (e.g., load step or release), the top

switch will turn on more or less frequently in response to

achieve faster transient response. This is the benefit of

the LTC3838-1’s controlled on-time, valley current mode

architecture. However, this process may understandably

lose phase and even frequency lock momentarily. For

relatively slow changes, phase and frequency lock can

still be maintained. For large load current steps with fast

slew rates, phase lock will be lost until the system returns

back to a steady-state condition (see Figure 10). It may

take up to several hundred microseconds to fully resume

the phase lock, but the frequency lock generally recovers

quickly, long before phase lock does.

generally comply to V

> 2V and V

< 0.5V.

PLLIN(H)

PLLIN(L)

The MODE/PLLIN pin has an internal 600k pull-down

resistor to ensure discontinuous current mode operation

if the pin is left open.

The LTC3838-1 uses the voltages on V and V

as well

OUT

IN

as R to adjust the top gate on-time in order to maintain

T

phase and frequency lock for wide ranges of V , V

IN OUT

and R -programmed switching frequency f:

T

V_OUT

t_ON

≈

V • f

IN

As the on-time is a function of the switching regulator’s

For light load conditions, the phase and frequency syn-

chronization depends on the MODE/PLLIN pin setting. If

the externalclock is applied, synchronization willbe active

and switching in continuous mode. If MODE/PLLIN is tied

–

output voltage, this output is measured by the SENSE pin

–

to set the required on-time. The SENSE pin is tied to the

regulator’s local output point to the IC for most applica-

tions, as the remotely regulated output point could be

significantly different from the local output point due to

linelosses,andlocaloutputversuslocalgroundistypically

to INTV , it will operate in forced continuous mode at

CC

the R -programmed frequency. If the MODE/PLLIN pin is

T

tiedtoSGND,theLTC3838-1willoperateindiscontinuous

mode at light load and switch into continuous conduction

the V

required for the calculation of t .

OUT

ON

However, there could be circumstances where this V

attheR programmedfrequencyasloadincreases.TheTG

OUT

T

programmed on-time differs significantly different from

the on-time required in order to maintain frequency

and phase lock. For example, lower efficiencies in the

switching regulator can cause the required on-time to be

substantially higher than the internally set on-time (see

on-time during discontinuous conduction is intentionally

slightlyextended(approximately1.2timesthecontinuous

conduction on-time as calculated from V , V

and f) to

IN OUT

create hysteresis at the load-current boundary of continu-

ous/discontinuous conduction.

Efficiency Considerations). If a regulated V

is relatively

OUT

Ifanapplicationrequiresverylow(approachingminimum)

on-time, the system may not be able to maintain its full

frequency synchronization range. Getting closer to mini-

mumon-time, itmayevenlosephase/frequencylockatno

load or light load conditions, under which the SW on-time

is effectively longer than TG on-time due to TG/BG dead

times. This is discussed further under Minimum On-Time,

Minimum Off-Time and Dropout Operation.

low, proportionally there could be significant error caused

by the difference between the local ground and remote

ground, due to other currents flowing through the shared

ground plane.

If necessary, the R resistor value, voltage on the V pin,

T

IN

or even the common mode voltage of the SENSE pins may

be programmed externally to correct for such systematic

38381f

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For more information www.linear.com/3838-1

LTC3838-1

APPLICATIONS INFORMATION

I

LOAD

CLOCK

INPUT

PHASE AND

FREQUENCY

LOCKED

PHASE AND

FREQUENCY

LOCK LOST

DUE TO FAST

LOAD STEP

FREQUENCY

RESTORED

QUICKLY

PHASE LOCK

RESUMED

PHASE AND

FREQUENCY

LOCK LOST

DUE TO FAST

LOAD STEP

FREQUENCY

RESTORED

QUICKLY

SW

V

OUT

38381 F10

Figure 10. Phase and Frequency Locking Behavior During Transient Conditions

Minimum On-Time, Minimum Off-Time

and Dropout Operation

Figure 11. During the dead time from BG turn-off to TG

turn-on,theinductorcurrentflowsinthereversedirection,

charging the SW node high before the TG actually turns

on. The reverse current is typically small, causing a slow

rising edge. On the falling edge, after the top FET turns off

and before the bottom FET turns on, the SW node lingers

high for a longer duration due to a smaller peak inductor

current available in light load to pull the SW node low. As

a result of the sluggish SW node rising and falling edges,

the effective on-time is extended and not fully controlled

by the TG on-time. Closer to minimum on-time, this may

cause some phase jitter to appear at light load. As load

currentincrease,theedgesbecomesharper,andthephase

locking behavior improves.

Theminimumon-timeisthesmallestdurationthatLTC3838-

1’s TG (top gate) pin can be in high or “on” state. It has

dependency on the operating conditions of the switching

regulator, and is a function of voltages on the V and

IN

T

V

pins, as well as the value of external resistor R . As

OUT

shown by the t

curves in the Typical Performance

ON(MIN)

Characteristics section, a minimum on-time of 30ns can

–

be achieved when V , sensed by the SENSE pin, is at

OUT

its minimum regulated value of 0.6V or lower, while V is

IN

OUT

tied to its maximum value of 38V. For larger values of V

,

smallervaluesofV ,and/orlargervalueofR (i.e.,lowerf),

IN

T

the minimum achievable on-time will be longer. The valley

mode control architecture allows low on-time, making the

LTC3838-1 suitable for high step-down ratio applications.

Incontinuousmodeoperation, theminimumon-timelimit

imposes a minimum duty cycle of:

The effective on-time, as determined by the SW node

pulse width, can be different from this TG on-time, as it

also depends on external components, as well as loading

conditionsoftheswitchingregulator.Oneofthefactorsthat

contributestothisdiscrepancyisthecharacteristicsofthe

power MOSFETs. For example, if the top power MOSFET’s

turn-on delay is much smaller than the turn-off delay,

the effective on-time will be longer than the TG on-time,

limiting the effective minimum on-time to a larger value.

D

= f • t

MIN

ON(MIN)

where t

is the effective minimum on-time for the

ON(MIN)

switching regulator. As the equation shows, reducing the

operating frequency will alleviate the minimum duty cycle

constraint. If the minimum on-time that LTC3838-1 can

provide is longer than the on-time required by the duty

cycle to maintain the switching frequency, the switching

frequency will have to decrease to maintain the duty cycle,

but the output voltage will still remain in regulation. This is

generally more preferable to skipping cycles and causing

larger ripple at the output, which is typically seen in fixed

frequency switching regulators.

Light-load operation, in forced continuous mode, will

further elongate the effective on-time due to the dead

times between the “on” states of TG and BG, as shown in

38381f

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For more information www.linear.com3838-1

LTC3838-1

APPLICATIONS INFORMATION

TG-SW

the dead-time delays from TG off to BG on and from BG

off to TG on. The minimum off-time that the LTC3838-1

can achieve is 90ns.

(V OF TOP

GS

MOSFET)

DEAD-TIME

DELAYS

BG

(V OF

GS

BOTTOM

MOSFET)

Theeffectiveminimumoff-timeoftheswitchingregulator,

or the shortest period of time that the SW node can stay

low,canbedifferentfromthisminimumoff-time.Themain

factor impacting the effective minimum off-time is the top

and bottom power MOSFETs’ electrical characteristics,

such as Qg and turn-on/off delays. These characteristics

can either extend or shorten the SW nodes’ effective

minimum off-time. Large size (high Qg) power MOSFETs

generally tend to increase the effective minimum off-time

due to longer gate charging and discharging times. On

the other hand, imbalances in turn-on and turn-off delays

could reduce the effective minimum off-time.

I

L

0

NEGATIVE

INDUCTOR

CURRENT

IN FCM

V

IN

SW

DURING BG-TG DEAD TIME,

DURING TG-BG DEAD TIME,

THE RATE OF SW NODE DISCHARGE

WILL DEPEND ON THE CAPACITANCE

ON THE SW NODE AND INDUCTOR

CURRENT MAGNITUDE

NEGATIVE INDUCTOR CURRENT

WILL FLOW THROUGH TOP MOSFET’S

BODY DIODE TO PRECHARGE SW NODE

+

V

I

L

IN

–

The minimum off-time limit imposes a maximum duty

cycle of:

L

SW

D

MAX

= 1 – f • t

OFF(MIN)

I

L

where t

is the effective minimum off-time of the

OFF(MIN)

TOTAL CAPACITANCE

switchingregulator.Reducingtheoperatingfrequencycan

alleviate the maximum duty cycle constraint.

ON THE SW NODE

38381 F11

Figure 11. Light Loading On-Time Extension for Forced

Continuous Mode Operation

If the maximum duty cycle is reached, due to a drooping

input voltage for example, the output will drop out of

regulation.Theminimuminputvoltagetoavoiddropoutis:

The t

curves in the Typical Performance Charac-

ON(MIN)

teristics are measured with minimum load on TG and

BG, at extreme cases of V = 38V, and/or V = 0.6V,

V_OUT

D_MAX

V

=

IN

OUT

IN(MIN)

and/or programmed f = 2MHz (i.e., R = 18k). In applica-

T

tions with different V , V

and/or f, the t

that

IN OUT

ON(MIN)

At the onset of drop-out, there is a region of V of about

IN

canbeachievedwillgenerallybelarger. Also, toguarantee

frequencyandphaselockingatlightload,sufficientmargin

500mV that generates two discrete off-times, one being

the minimum off time and the other being an off-time that

is about 40ns to 60ns longer than the minimum off-time.

This secondary off-time is due to the extra delay in trip-

ping the internal current comparator. The two off-times

average out to the required duty cycle to keep the output in

regulation. There may be higher SW node jitter, apparent

especially when synchronized to an external clock, but the

output voltage ripple remains relatively small.

needs to be added to account for the dead times (t

D(TG/BG)

+ t

in the Electrical Characteristics).

D(TG/BG)

Forapplicationsthatrequirerelativelylowon-time, proper

cautionhastobetakenwhenchoosingthepowerMOSFET.

If the gate of the MOSFET is not able to fully turn on due

to insufficient on-time, there could be significant heat dis-

sipation and efficiency loss as a result of larger R

.

DS(ON)

This may even cause early failure of the power MOSFET.

Fault Conditions: Current Limiting and Overvoltage

The minimum off-time is the smallest duration of time

that the TG pin can be turned low and then immediately

turnedbackhigh.Thisminimumoff-timeincludesthetime

to turn on the BG (bottom gate) and turn it back off, plus

The maximum inductor current is inherently limited in a

currentmodecontrollerbythemaximumsensevoltage.In

the LTC3838-1, the maximum sense voltage is controlled

38381f

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LTC3838-1

APPLICATIONS INFORMATION

by the voltage on the V

pin. With valley current mode

Assuming a predominantly 2nd order system, phase

margin and/or damping factor can be estimated using the

percentage of overshoot seen at this pin.

RNG

control, the maximum sense voltage and the sense re-

sistance determine the maximum allowed inductor valley

current. The corresponding output current limit is:

The external series R -C

filter at the ITH pin sets the

ITH ITH1

V_SENSE(MAX)

dominant pole-zero loop compensation. The values can

1

2

I_LIMIT

=

+ • ∆I_L

be adjusted to optimize transient response once the final

PCBlayoutisdoneandtheparticularoutputcapacitortype

and value have been determined. The output capacitors

need to be selected first because their various types and

values determine the loop feedback factor gain and phase.

R_SENSE

The current limit value should be checked to ensure that

> I . The current limit value should

I

LIMIT(MIN)

OUT(MAX)

be greater than the inductor current required to produce

maximum output power at the worst-case efficiency.

An additional small capacitor, C , can be placed from

ITH2

the ITH pin to SGND to attenuate high frequency noise.

Note this C contributes an additional pole in the loop

gain therefore can affect system stability if too large. It

should be chosen so that the added pole is higher than

the loop bandwidth by a significant margin.

Worst-case efficiency typically occurs at the highest V

IN

and highest ambient temperature. It is important to check

ITH2

for consistency between the assumed MOSFET junction

temperatures and the resulting value of I

the MOSFET switches.

which heats

LIMIT

The regulator loop response can also be checked by

looking at the load transient response. An output current

pulse of 20% to 100% of full-load current having a rise

time of 1µs to 10µs will produce V_OUTand ITH voltage

transient-responsewaveformsthatcangiveasenseofthe

overall loop stability without breaking the feedback loop.

For a detailed explanation of OPTI-LOOP compensation,

refer to Application Note 76.

To further limit current in the event of a short circuit to

ground,theLTC3838-1includesfoldbackcurrentlimiting.

If the output falls by more than 50%, the maximum sense

voltage is progressively lowered, to about one-fourth of

its full value as the feedback voltage reaches 0V.

A feedback voltage exceeding 7.5% of the regulated target

of 0.6V is considered as overvoltage (OV). In such an OV

condition, the top MOSFET is immediately turned off and

the bottom MOSFET is turned on indefinitely until the OV

conditionisremoved,i.e.,thefeedbackvoltagefallingback

below the 7.5% threshold by more than the hysteresis of

around 2.5% typical. Current limiting is not active during

an OV. If the OV persists, and the BG turns on for a longer

time, the current through the inductor and the bottom

MOSFET may exceed their maximum ratings, sacrificing

themselves to protect the load.

Switching regulators take several cycles to respond to

a step in load current. When a load step occurs, V

OUT

• ESR,

immediately shifts by an amount equal to ∆I

LOAD

whereESRistheeffectiveseriesresistanceofC .∆I

OUT

LOAD

also begins to charge or discharge C , generating a

OUT

feedback error signal used by the regulator to return V

to its steady-state value. During this recovery time, V

OUT

can be monitored for overshoot or ringing that would

indicate a stability problem.

OPTI-LOOP^®Compensation

ConnectingaresistiveloadinserieswithapowerMOSFET,

then placing the two directly across the output capacitor

and driving the gate with an appropriate signal generator

is a practical way to produce a realistic load step condi-

tion. The initial output voltage step resulting from the step

change in load current may not be within the bandwidth

of the feedback loop, so it cannot be used to determine

phasemargin.Theoutputvoltagesettlingbehaviorismore

OPTI-LOOP compensation, through the availability of the

ITH pin, allows the transient response to be optimized for

a wide range of loads and output capacitors. The ITH pin

not only allows optimization of the control-loop behavior

butalsoprovidesaDC-coupledandAC-filteredclosed-loop

response test point. The DC step, rise time and settling

at this test point truly reflects the closed-loop response.

38381f

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LTC3838-1

APPLICATIONS INFORMATION

relatedtothestabilityoftheclosed-loopsystem.However,

itisbettertolookatthefilteredandcompensatedfeedback

loop response at the ITH pin.

load current change. The excess inductor current charges

up the output capacitor, which causes overshoot at V

.

OUT

If the bottom MOSFET could be turned off during the load-

release transient, the inductor current would flow through

the body diode of the bottom MOSFET, and the equation

can be modified to include the bottom MOSFET body

The gain of the loop increases with the R and the band-

ITH

width of the loop increases with decreasing C

. If R

ITH1

is decreased,

ITH

is increased by the same factor that C

ITH1

the zero frequency will be kept the same, thereby keeping

the phase the same in the most critical frequency range

of the feedback loop. In addition, a feedforward capacitor,

diode drop to become V = –(V

+ V ). Obviously the

L

OUT BD

benefit increases as the output voltage gets lower, since

V

BD

would increase the sum significantly, compared to a

C ,canbeaddedtoimprovethehighfrequencyresponse,

single V

only.

OUT

FF

as used in the typical application at the last page of this

Theload-releaseovershootatV causestheerrorampli-

OUT

data sheet. Feedback capacitor C provides phase lead by

FF

fieroutput,ITH,todropquickly.ITHvoltageisproportional

to the inductor current setpoint. A load transient will

result in a quick change of this load current setpoint, i.e.,

a negative spike of the first derivative of the ITH voltage.

creating a high frequency zero with R which improves

FB2

the phase margin.

A more severe transient can be caused by switching in

loadswithlargesupplybypasscapacitors.Thedischarged

bypass capacitors of the load are effectively put in parallel

The LTC3838-1 uses a detect transient (DTR) pin to

monitor the first derivative of the ITH voltage, and detect

the load-release transient. Referring to the Functional

Diagram, the DTR pin is the input of a DTR comparator,

and the internal reference voltage for the DTR comparator

with the converter’s C , causing a rapid drop in V

.

OUT

No regulator can deliver current quick enough to prevent

this sudden step change in output voltage, if the switch

connecting the C

to the load has low resistance and is

OUT

is half of INTV . To use this pin for transient detection,

CC

driven quickly. The solution is to limit the turn-on speed

of the load switch driver. Hot Swap™ controllers are de-

signedspecificallyforthispurposeandusuallyincorporate

current limiting, short-circuit protection and soft starting.

ITH compensation needs an additional R resistor tied

ITH

to INTV , and connects the junction point of ITH com-

CC

pensation components C

, R

ITH1 ITH1

and R

to the DTR

ITH2

pin as shown in the Functional Diagram. The DTR pin is

now proportional to the first derivative of the inductor

Load-Release Transient Detection

current setpoint, through the highpass filter of C

and

ITH1

Astheoutputvoltagerequirementofstep-downswitching

(R

//R

).

ITH1 ITH2

regulators becomes lower, V to V

step-down ratio

IN

OUT

The two R resistors establish a voltage divider from

ITH

increases, and load transients become faster, a major

INTV to SGND, and bias the DC voltage on DTR pin (at

CC

challenge is to limit the overshoot in V

load current drop, or “load-release” transient.

during a fast

OUT

steady-state load or ITH voltage) slightly above half of

INTV . Compensation performance will be identical by

CC

Inductor current slew rate di /dt = V /L is proportional

using the same C

and make R

//R

equal the

L

ITH1

ITH1 ITH2

to voltage across the inductor V = V – V . When

R

ITH

as used in conventional single resistor OPTI-LOOP

L

SW

OUT

the top MOSFET is turned on, V = V – V , inductor

compensation.ThiswillalsoprovidetheR-Ctimeconstant

needed for the DTR duration. The DTR sensitivity can be

adjusted by the DC bias voltage difference between DTR

L

IN

OUT

current ramps up. When bottom MOSFET turns on, V =

L

V

– V

= –V , inductor current ramps down. At

SW

OUT OUT

very low V , the low differential voltage, V , across the

and half INTV . This difference could be set as low as

OUT

L

CC

inductor during the ramp down makes the slew rate of the

inductor current much slower than needed to follow the

200mV, as long as the ITH ripple voltage with DC load

current does not trigger the DTR.

38381f

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LTC3838-1

APPLICATIONS INFORMATION

Note the internal 2.5µA pull-up current from the DTR pin

will generate an additional offset on top of the resistor

divider itself, making the total difference between the DC

present), even if DTR is still below half INTV . This is

CC

to allow the inductor current to go negative to quickly

pull down the V

overshoot. Of course, if the MODE/

OUT

bias voltage on the DTR pin and half INTV :

PLLIN pin is set to discontinuous mode (i.e., tied to

SGND), BG will stay off as inductor current reverse, as

it would with the DTR feature disabled.

CC





R

ITH1

+ R

V

– 0.5V

=

– 0.5 • 5.3V





DTR

INTVCC

(R

)





ITH1 ITH2

Also, if V

gets higher than the OV window (7.5%

OUT

+ 2.5µA • R

//R

)

(

ITH1

ITH2

typical), the DTR function is defeated and BG will turn

on regardless. Therefore, in order for the DTR feature

As illustrated in Figure 12, when load current suddenly

to reduce V

overshoot effectively,sufficient output

OUT

drops,V overshoots,andITHdropsquickly.Thevoltage

OUT

capacitance needs to be used in the application so that

OV is not triggered with the amount of load step desired

to have its overshoot suppressed.

on the DTR pin will also drop quickly, since it is coupled

to the ITH pin through a capacitor. If the load transient

is fast enough that the DTR voltage drops below half of

Experimenting with a 0.6V output application (modified

INTV , a load release event is detected. The bottom gate

CC

from the design example circuit by setting V

to 0.6V

(BG) will be turned off, so that the inductor current flows

through the body diode in the bottom MOSFET. This al-

lows the SW node to drop below PGND by a voltage of

a forward-conducted silicon diode. This creates a more

OUT

and ITH compensation adjusted accordingly) shows this

detecttransientfeaturesignificantlyreducestheovershoot

peak voltage, as well as time to resume regulation during

load release steps (see application examples in Typical

Performance Characteristics).

negative differential voltage (V

– V ) across the

SW

OUT

inductor, allowing the inductor current to drop at a faster

rate to zero, therefore creating less overshoot on V

.

OUT

Note that it is expected that this DTR feature will cause

additional loss on the bottom MOSFET, due to its body

diode conduction. The bottom MOSFET temperature may

be higher with a load of frequent and large load steps. This

is an important design consideration. Experiments on the

demo board show a 20°C increase when a continuous

100% to 50% load step pulse train with 50% duty cycle

and 100kHz frequency is applied to the output.

The DTR comparator output is overridden by reverse

inductor current detection (I ) and overvoltage (OV)

REV

+

condition.ThismeansBGwillbeturnedoffwhenSENSE

–

is higher than SENSE (i.e., inductor current is posi-

tive), as long as the OV condition is not present. When

inductor current drops to zero and starts to reverse, BG

will turn back on in forced continuous mode (e.g., the

MODE/PLLIN pin tied to INTV , or an input clock is

CC

SW

5V/DIV

SW

5V/DIV

BG

BG REMAINS ON

5V/DIV

DURING THE LOAD

DTR

1V/DIV

RELEASE EVENT

ITH

1V/DIV

BG TURNS BACK ON, INDUCTOR

CURRENT (I ) GOES NEGATIVE

L

I

L

I

L

10A/DIV

38381 F12

DTR DETECTS LOAD

5µs/DIV

RELEASE, TURNS OFF BG

FOR FASTER INDUCTOR

LOAD RELEASE = 15A TO 0A

V

IN

V

OUT

= 5V

V

= 5V

IN

OUT

CURRENT (I ) DECAY

= 0.6V

L

(12a) DTR Enabled

(12b) DTR Disabled

Figure 12. Comparison of V_OUTOvershoot with Detect Transient (DTR) Feature Enabled and Disabled

38381f

35

For more information www.linear.com3838-1

LTC3838-1

APPLICATIONS INFORMATION

If not needed, this DTR feature can be disabled by tying

3. DRV current. This is the sum of the MOSFET driver

CC

the DTR pin to INTV , or simply leave the DTR pin open

and INTV control currents. The MOSFET driver cur-

CC

so that an internal 2.5µA current source will pull itself up

rents result from switching the gate capacitance of the

power MOSFETs. Each time a MOSFET gate is switched

from low to high to low again, a packet of charge dQ

to INTV .

CC

Efficiency Considerations

moves from DRV to ground. The resulting dQ/dt is a

CC

current out of DRV that is typically much larger than

CC

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percentage efficiency

can be expressed as:

the controller I current. In continuous mode,

Q

I

= f • (Qg

+ Qg ),

(BOT)

GATECHG

(TOP)

where Qg

and Qg

are the gate charges of the

(TOP)

(BOT)

top and bottom MOSFETs, respectively.

SupplyingDRV powerthroughEXTV couldincrease

CC

%Efficiency = 100% – (L1% + L2% + L3% + ...)

efficiency by several percent, especially for high V

IN

where L1%, L2%, etc. are the individual losses as a per-

centage of input power. Although all dissipative elements

in the circuit produce power losses, several main sources

usually account for most of the losses:

applications. Connecting EXTV to an output-derived

CC

source will scale the V current required for the driver

IN

and controller circuits by a factor of (Duty Cycle)/(Ef-

ficiency). Forexample, ina20Vto5Vapplication, 10mA

2

of DRV current results in approximately 2.5mA of V

CC

IN

1. I R loss. These arise from the DC resistances of the

current. This reduces the mid-current loss from 10%

MOSFETs,inductor,currentsenseresistorandisthema-

jority of power loss at high output currents. In continu-

ous mode the average output current flows though the

inductor L, but is chopped between the top and bottom

MOSFETs. If the two MOSFETs have approximately the

or more (if the driver was powered directly from V )

IN

to only a few percent.

4. C loss. The input capacitor filters large square-wave

IN

input current drawn by the regulator into an averaged

DC current from the supply. The capacitor itself has

a zero average DC current, but square-wave-like AC

current flows through it. Therefore the input capacitor

must have a very low ESR to minimize the RMS current

loss on ESR. It must also have sufficient capacitance

to filter out the AC component of the input current to

prevent additional RMS losses in upstream cabling,

fusesorbatteries.TheLTC3838-1’s2-phasearchitecture

improves the ESR loss.

same R

, then the resistance of one MOSFET can

DS(ON)

simply be summed with the inductor’s DC resistances

2

(DCR) and the board traces to obtain the I R loss. For

example,ifeachR

=8mΩ,R =5mΩ,andR

DS(ON)

L SENSE

= 2mΩ the loss will range from 15mW to 1.5W as the

outputcurrentvariesfrom1Ato10A.Thisresultsinloss

from 0.3% to 3% a 5V output, or 1% to 10% for a 1.5V

output. Efficiency varies as the inverse square of V

OUT

for the same external components and output power

level. The combined effects of lower output voltages

and higher currents load demands greater importance

of this loss term in the switching regulator system.

“Hidden” copper trace, fuse and battery resistance, even

at DC current, can cause a significant amount of efficiency

degradation, so it is important to consider them during

2. Transition loss. This loss mostly arises from the brief

amount of time the top MOSFET spends in the satura-

tion (Miller) region during switch node transitions. It

depends upon the input voltage, load current, driver

strength and MOSFET capacitance, among other fac-

tors, and can be significant at higher input voltages or

higher switching frequencies.

the design phase. Other losses, which include the C

OUT

ESR loss, bottom MOSFET’s body diode reverse-recovery

loss, and inductor core loss generally account for less

than 2% additional loss.

Power losses in the switching regulator will reflect as

a higher than ideal duty cycle, or a longer on-time for a

38381f

36

For more information www.linear.com/3838-1

LTC3838-1

APPLICATIONS INFORMATION

constant frequency. This efficiency accounted on-time

can be calculated as:

Set the inductor value to give 40% ripple current at maxi-

mum V using the adjusted operating frequency:

IN



















t

≈ t

/Efficiency

1.2V

24V

ON

ON(IDEAL)

L =

1–

= 0.54µH

350kHz • 40% •15A

Whenmakingadjustmentstoimproveefficiency,theinput

current is the best indicator of changes in efficiency. If

you make a change and the input current decreases, then

the efficiency has increased.

Select 0.56µH which is the nearest standard value.

The resulting maximum ripple current is:

















1.2V

350kHz • 0.56µH

1.2V

24V

Design Example

∆I =

1–

= 5.8A









L

Consider a channel of step-down converter from V

4.5V to 26V to V

f = 350kHz (see Figure 13, channel 1).

=

IN

= 1.2V, with I

= 15A, and

OUT

OUT(MAX)

Often in a high power application, DCR current sensing is

preferred over R in order to maximize efficiency. In

SENSE

order to determine the DCR filter values, first the inductor

manufacturerhastobechosen.Forthisdesign,theVishay

IHLP-4040DZ-01 model is chosen with a value of 0.56µH

Theregulatedoutputvoltageofchannel1isdeterminedby:





R



^FB2

V_OUT1= 0.6V • 1+

R

_FB1

and a DCR

=1.8mΩ. This implies that:



MAX

V

= 1.8mΩ • [1 + (100°C – 25°C) • 0.4%/°C]

• (15A – 5.8A/2) = 28mV

SENSE(MAX)

Using a 10k resistor for R , R is also 10k.

FB1 FB2

Channel 2 requires an additional resistor to SGND (see

Output Voltage Programming section). The value of

the additional resistor is equal to the parallel of the two

feedback resistors. If such an exact resistor value is not

available, simply use two additional resistors in parallel

for the best accuracy.

The maximum sense voltage, V

, is within the

SENSE(MAX)

range that LTC3838-1 can handle without any additional

scaling. Therefore, the DCRfiltercan use a simple RC filter

across the inductor. If the C is chosen to be 0.1µF, then

the R can be calculated as:

L

0.56µH

The frequency is programmed by:

R_DCR

=

= 3.1kΩ

DCR •C_DCR1.8mΩ • 0.1µF

41550

f kHz

41550

350

R kΩ =

– 2.2 =

– 2.2 ≈ 116.5

[

]

T

Connect V

to SGND to set the V

to 30mV

[

]

RGN

SENSE(MAX)

typical while using an additional resistor in the DCR filter,

Use the nearest 1% resistor standard value of 115k.

Theminimumon-timeoccursformaximumV .Usingthe

asdiscussedinDCRInductorCurrentSensing,toscalethe

V

downbyacomfortablemarginbelowthelower

SENSE(MAX)

limit of the LTC3838-1’s own V

IN

specification,

SENSE(MAX)

t

curvesintheTypicalPerformanceCharacteristics

ON(MIN)

so that the maximum output current can be guaranteed.

asreferences, makesurethatthet

atmaximumV

ON(MIN)

IN

is greater than that the LTC3838-1 can achieve, and allow

In this design example, a 3.57k and 15k resistor divider

is used. The previously calculated V

sufficient margin to account for the extension of effective

is scaled

SENSE(MAX)

on-time at light load due to the dead times (t

down from 28mV to 22.6mV, which is close to the lower

limit of LTC3838-1’s V specification. Note the

D(TG/BG) +

t

in the Electrical Characteristics). The minimum

D(TG/BG)

on-time for this application is:

SENSE(MAX)

= 3.57k//15k = 2.9k, slightly lower than

the 3.1k calculated above for a matched R -C

equivalent R

DCR

and

DCR DCR

V_OUT

1.2V

t_ON(MIN)

=

= 143ns

L-DCRnetwork.Theresultedmismatchallowsforaslightly

higher ripple in V

V

_IN(MAX)• f 24V • 350kHz

.

SENSE

38381f

37

For more information www.linear.com3838-1

LTC3838-1

APPLICATIONS INFORMATION

V

IN

4.5V TO 26V

C

+

IN2

C

IN1

10µF

2.2Ω

220µF

×3

LTC3838-1

–

1µF

V

IN

–

SENSE1

SENSE2

15k

0.1µF

15k

+

SENSE1

SENSE2

0.1µF

BOOST1

TG1

BOOST2

TG2

3.57k

L2

MT1

MB1

MT2

MB2

L1

0.56µH

DB1

DB2

0.56µH

V

1.5V

15A

OUT1

1.2V

15A

OUT2

SW1

SW2

2.2Ω

DRV

CC1

DRV

CC2

EXTV

C

+

C

+

C

OUT3

OUT1

OUT2

OUT4

INTV

CC

100µF

330µF

100µF

1µF

4.7µF

×2

BG1

BG2

PGND

10k

15k

+

–

+

V

OUTSENSE1

DFB2

10k//15k

SGND

10k

–

V

OUTSENSE1

DFB2

100k

22pF

100k

22pF

PGOOD1

0.01µF

PGOOD2

PGOOD1

PGOOD2

0.01µF

C

: PANASONIC EEEFK1V221P

IN1

IN2

TRACK/SS1 TRACK/SS2

: TAIYO YUDEN GMK325BJ106MN-T

, C

: SANYO 2R5TPE330M9

: MURATA GRM31CR60J107ME39L

OUT2 OUT4

, C

ITH1

ITH2

OUT1 OUT3

220pF

115k

220pF

DB1, DB2: CENTRAL SEMI CMDSH-4ETR

L1, L2: VISHAY IHLP4040DZERR56M01

MT1, MT2: RENESAS RJK0305DPB

MB1, MB2: RENESAS RJK0330DPB

90.9k

82.5k

DTR1

DTR2

38381 F13a

V

RNG

PHASMD

MODE/PLLIN

CLKOUT

RT

SGND

RUN1

RUN2

100

3.0

2.5

2.0

1.5

1.0

0.5

0

100

3.0

FORCED CONTINUOUS MODE

DISCONTINUOUS MODE

FORCED CONTINUOUS MODE

DISCONTINUOUS MODE

90

80

70

60

50

40

90

80

70

60

50

40

2.5

2.0

1.5

1.0

0.5

0

EFFICIENCY

POWER

LOSS

POWER

LOSS

V

OUT

= 12V

V

IN

V

OUT

= 12V

IN

V

= 1.2V

= 1.5V

0.1

1

10

0.1

1

10

LOAD CURRENT (A)

38381 F13b

38381 F13c

Figure 13. Design Example: 4.5V to 26V Input, 1.2V/15A and 1.5V/15A Dual Outputs,

350kHz, DCR Sense, DTR Enabled, Step-Down Converter

38381f

38

For more information www.linear.com/3838-1

LTC3838-1

APPLICATIONS INFORMATION

Remember to check the maximum possible peak inductor

aluminum-electrolytic bulk capacitor for stability. For

10µF 1210 X5R ceramic capacitors, try to keep the ripple

current less than 3A RMS through each device. The bulk

capacitor is chosen for RMS rating per simulation with

the circuit model provided.

current, considering the upper spec limit of V

SENSE(MAX)

at lowest operating temperature, as well

and the DCR

(MIN)

as the maximum ∆I , is not going to saturate the inductor

L

or exceed the rating of power MOSFETs:

V

_SENSE(MAX)(UpperSpecLimit)

The output capacitor C

is chosen for a low ESR of

OUT

I_L(PEAK)

=

+ ∆I_L(MAX)

4.5mΩtominimizeoutputvoltagechangesduetoinductor

ripple current and load steps. The output voltage ripple

is given as:





1+ T – 25°C • 0.4% / °C



MIN

DCR

_MIN

(

)

For the external N-channel MOSFETs, Renesas

RJK0305DBP (R = 13mΩ max, C

=

MILLER

DS(ON)

∆V

= ∆I

• ESR = 5.85A • 4.5mΩ = 26mV

OUT(RIPPLE)

L(MAX)

150pF, V = 4.5V, θ = 40°C/W, T = 150°C)

GS

JA

J(MAX)

However, a 10A load step will cause an output change

of up to:

is chosen for the top MOSFET (main switch). RJK-

0330DBP (R = 3.9mΩ max, V = 4.5V, θ

=

JA

DS(ON)

GS

40°C/W, T

= 150°C) is chosen for the bottom

J(MAX)

∆V

= ∆I

• ESR = 10A • 4.5mΩ = 45mV

OUT(STEP)

LOAD

MOSFET (synchronous switch). The power dissipation

for each MOSFET can be calculated for V = 24V and

typical T = 125°C:

Optional2× 100µFceramicoutputcapacitorsareincluded

to minimize the effect of ESR and ESL in the output ripple

and to improve load step response.

IN

J













1.2V

24V

2





P_TOP

=

15A 13mΩ 1+ 0.4% 125°C – 25°C

( ) (

)



(

)



The ITH compensation resistor R of 40k and a C of

ITH

220pF are chosen empirically for fast transient response,



²















15A

2

2.5Ω

5.3V – 3V 3V

1.2Ω

+ 24V

150pF

(

+

350kHz

andanadditionalC =22pFisaddeddirectlyfromITHpin

(

)

(

)







ITH2

toSGND, torolloffthesystemgainatswitchingfrequency

= 0.54W

and attenuate high frequency noise. For less aggressive













24V – 1.2V

24V

2

transient response but more stability, lower-valued R





ITH

P_BOT

=

15A 3.9mΩ 1+ 0.4% 125°C – 25°C

(

) (

)

(

)





and higher-valued C and C

can be used (such as

ITH

ITH2

= 1.2W

the various combinations used in Figures 16, 17, 18, 19,

20), which typically results in lower bandwidth but more

phase margin.

The resulted junction temperatures at an ambient tem-

perature T = 75°C are:

A

To set up the detect transient (DTR) feature, pick resis-

tors for an equivalent R = R

40k chosen. Here, 1% resistors R

T

= 75°C + (0.54W)(40°C/W) = 97°C

= 75°C + (1.2W)(40°C/W) = 123°C

J(TOP)

J(BOT)

//R close to the

ITH

ITH1 ITH2

= 90.9k (low side)

ITH1

and R

= 82.5k (high side) are used, which yields an

ITH

ITH2

These numbers show that careful attention should be paid

to proper heat sinking when operating at higher ambient

temperatures.

equivalentR of43.2k,andaDC-biasthresholdof236mV

typical above one-half of INTV (including the 2.5µA

CC

pull-up current from the DTR pin, see the Load-Release

Select the C capacitors to give ample capacitance and

IN

Transient Detection section). Note that even though the

RMS ripple current rating. Consider worst-case duty

cycles per Figure 6: If operated at steady-state with SW

nodes fully interleaved, the two channels would gener-

ate not more than 7.5A RMS at full load. In this design

example, 3 × 10µF 35V X5R ceramic capacitors are put

in parallel to take the RMS ripple current, with a 220µF

accuracy of the equivalent compensation resistance R

ITH

is not as important, always use 1% or better resistors for

the resistor divider from INTV to SGND to guarantee the

CC

relative accuracy of this DC-bias threshold. To disable the

DTR feature, simply use a single R resistor to SGND,

ITH

and tie the DTR pin to INTV .

CC

38381f

39

For more information www.linear.com3838-1

LTC3838-1

APPLICATIONS INFORMATION

PCB Layout Checklist

• The top N-channel MOSFETs of the two channels have

to be located within a short distance from (preferably

<1cm) each other with a common drain connection at

The printed circuit board layout is illustrated graphically

in Figure 14. Figure 15 illustrates the current waveforms

present in the various branches of 2-phase synchronous

regulators operating in continuous mode. Use the follow-

ing checklist to ensure proper operation:

C . Do not attempt to split the input decoupling for the

IN

two channels as it can result in a large resonant loop.

• Connect the input capacitor(s), C , close to the power

IN

MOSFETs.ThiscapacitorprovidestheMOSFETtransient

spike current. Connect the drain of the top MOSFET as

close as possible to the (+) plate of the ceramic portion

• Amultilayerprintedcircuitboardwithdedicatedground

planes is generally preferred to reduce noise coupling

and improve heat sinking. The ground plane layer

should be immediately next to the routing layer for the

power components, e.g., MOSFETs, inductors, sense

resistors, input and output capacitors etc.

of input capacitors C . Connect the source of the bot-

IN

tom MOSFET as close as possible to the (–) terminal

of the same ceramic C capacitor(s). These ceramic

IN

capacitor(s) bypass the high di/dt current locally, and

both top and bottom MOSFET should have short PCB

trace lengths to minimize high frequency EMI and

prevent MOSFET voltage stress from inductive ringing.

• Keep SGND and PGND separate. Upon finishing the

layout, connect SGND and PGND together with a single

PCBtraceunderneaththeICfromtheSGNDpinthrough

the exposed PGND pad to the PGND pin.

• The path formed by the top and bottom N-channel

• All power train components should be referenced to

MOSFETs, and the C capacitors should have short

IN

PGND; all components connected to noise-sensitive

leads and PCB trace. The (–) terminal of output capaci-

pins, e.g., ITH, RT, TRACK/SS and V , should return

tors should be connected close to the (–) terminal of

RNG

to the SGND pin. Keep PGND ample, but SGND area

compact.Useamodified“starground”technique:alow

impedance, large copper area central PCB point on the

same side of the as the input and output capacitors.

C , but away from the loop described above. This is to

IN

achieve an effect of Kelvin (4-wire) connection to the

input ground so that the “chopped” switching current

will not flow through the path between the input ground

andtheoutputground,andcausecommonmodeoutput

voltage ripple.

• Placepowercomponents,suchasC ,C ,MOSFETs,

IN OUT

D and inductors, in one compact area. Use wide but

B

shortest possible traces for high current paths (e.g.,

• Several smaller sized ceramic output capacitors, C

,

OUT

V , V , PGND etc.) to this area to minimize copper

can be placed close to the sense resistors and before

the rest bulk output capacitors.

IN OUT

loss.

+

–

• Keep the switch nodes (SW1,2), top gates (TG1,2) and

boost nodes (BOOST1,2) away from noise-sensitive

small-signal nodes, especially from the opposite chan-

nel’s voltage and current sensing feedback pins. These

nodes have very large and fast moving signals and

therefore should be kept on the “output side” of the

LTC3838-1 (power-related pins are toward the right

hand side of the IC), and occupy minimum PC trace

area. Usecompactswitchnode(SW)planestoimprove

cooling of the MOSFETs and to keep EMI down. If DCR

sensing is used, place the top filter resistor (R1 only in

Figure 5) close to the switch node.

• ThefiltercapacitorbetweentheSENSE andSENSE pins

should always be as close as possible to these pins.

Ensure accurate current sensing with Kelvin (4-wire)

connections to the soldering pads from underneath

the sense resistors or inductor. A pair of sense traces

should be routed together with minimum spacing.

R

, if used, should be connected to the inductor

on the noiseless output side, and its filter resistors

SENSE

+

–

close to the SENSE /SENSE pins. For DCR sensing,

however, filter resistor should be placed close to the

+

–

inductor, and away from the SENSE /SENSE pins, as

its terminal is the SW node.

38381f

40

For more information www.linear.com/3838-1

LTC3838-1

APPLICATIONS INFORMATION

C

R

DFB1

B2

–

+

–

L2

V

R

DFB2 SENSE2 SENSE2 DTR2 RUN2 PGOOD2 BOOST2

+

SENSE2

DFB2

TG2

SW2

BG2

V

OUT2

DFB2

R

//R

DFB1 DFB2

R

V

D

ITH2(2)

RNG

B2

MT2

C

ITH1(2)

DRV

EXTV

MB2

CC2

R

ITH1(2)

LTC3838-1

ITH2

CC

R

INTVCC

C

ITH2(2)

INTV

CC

CERAMIC

C

INTVCC

TRACK/SS2

C

OUT2

C

SS2

MODE/PLLIN

CLKOUT

SGND

PGND

LOCALIZED

SGND TRACE

V

C

PGND

IN

VIN

+

RT

C

V

IN

CERAMIC

IN

R

T

R

VIN

PHASMD

C

DRVCC

C

ITH2(1)

OUT1

DRV

CC1

R

ITH1(1)

D

B1

ITH1

MT1

R

ITH2(1)

MB1

C

ITH1(1)

BG1

SW1

TG1

TRACK/SS1

+

R

SENSE1

V

OUT1

C

SS1

R

FB2(1)

L1

V

OUTSENSE1

C

–

+

–

B1

V

SENSE1 SENSE1 DTR1 RUN1 PGOOD1 BOOST1

OUTSENSE1

R

FB1(1)

38381 F14

BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH

Figure 14. Recommended PCB Layout Diagram

• Place the resistor feedback dividers close to the

• Keepsmall-signalcomponentsconnectednoise-sensi-

+

–

+

–

+

V

and V

pins for channel 1,

tivepins(giveprioritytoSENSE /SENSE ,V

/

OUTSENSE1

+

–

+

–

or V

and V

pins for channel 2, so that the

V

, V

/V

, RT, ITH, V

pins) on

DFB2

OUTSENSE1

DFB2

RNG

feedback voltage tapped from the resistor divider will

not be disturbed by noise sources. Route remote sense

PCB traces (use a pair of wires closely together for

differential sensing) directly to the terminals of output

capacitors for best output regulation.

the left hand side of the IC as close to their respective

pinsaspossible. Thisminimizes thepossibilityofnoise

couplingintothesepins.IftheLTC3838-1canbeplaced

on the bottom side of a multilayer board, use ground

planes to isolate from the major power components on

the top side of the board, and prevent noise coupling

to noise sensitive components on the bottom side.

• Place decoupling capacitors C

next to the ITH and

ITH2

SGND pins with short, direct trace connections.

38381f

41

For more information www.linear.com3838-1

LTC3838-1

APPLICATIONS INFORMATION

L2

R

SENSE2

V

OUT2

SW2

C

OUT2

R

L2

V

IN

R

IN

C

IN

L1

R

SENSE1

V

OUT1

SW1

C

OUT1

R

L1

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

38381 F15

Figure 15. Branch Current Waveforms

• Use sufficient isolation when routing a clock signal into

the MODE/PLLIN pin or out of the CLKOUT pin, so that

the clock does not couple into sensitive pins.

• Filter the V input to the LTC3838-1 with an RC filter.

IN

Place the filter capacitor close to the V pin.

IN

• If vias have to be used, use immediate vias to connect

componentstotheSGNDandPGNDplanesofLTC3838-1.

Use multiple large vias for power components.

• PlacetheceramicdecouplingcapacitorC

between

INTVCC

the INTV pin and SGND and as close as possible to

CC

the IC.

• Floodallunusedareasonalllayerswithcopper.Flooding

with copper will reduce the temperature rise of power

components. ConnectthecopperareastoDCrailsonly,

e.g., PGND.

• Place the ceramic decoupling capacitor C

close

DRVCC

to the IC, between the combined DRV

PGND.

pins and

CC1,2

38381f

42

For more information www.linear.com/3838-1

LTC3838-1

APPLICATIONS INFORMATION

PCB Layout Debugging

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins.

Only after each controller is checked for its individual

performance should both controllers be turned on at the

same time. It is helpful to use a current probe to monitor

thecurrentintheinductorwhiletestingthecircuit.Monitor

the output switching node (SW pin) to synchronize the

oscilloscope to the internal oscillator output CLKOUT, or

external clock if used. Probe the actual output voltage as

well. Check for proper performance over the operating

voltage and current range expected in the application.

Thecapacitorplacedacrossthecurrentsensingpinsneeds

to be placed immediately adjacent to the pins of the IC.

This capacitor helps to minimize the effects of differential

noise injection due to high frequency capacitive coupling.

The frequency of operation should be maintained over

the input voltage range. The phase should be maintained

from cycle to cycle in a well designed, low noise PCB

implementation. Variation in the phase of SW node pulse

can suggest noise pickup at the current or voltage sensing

inputs or inadequate loop compensation. Overcompensa-

tion of the loop can be used to tame a poor PCB layout if

regulator bandwidth optimization is not required.

If problems are encountered with high current output

loadingatlowerinputvoltages,lookforinductivecoupling

between C , top and bottom MOSFET components to the

IN

sensitive current and voltage sensing traces.

Inaddition,investigatecommongroundpathvoltagepickup

between these components and the SGND pin of the IC.

High Switching Frequency Operation

Pay special attention to the region of operation when one

controller channel is turning on (right after its current

comparator trip point) while the other channel is turning

off its top MOSFET at the end of its on-time. This may

cause minor phase-lock jitter at either channel due to

noise coupling.

At high switching frequencies there may be an increased

sensitivity to noise. Special care may need to be taken to

prevent cycle-by-cycle instability and/or phase-lock jitter.

First, carefullyfollowtherecommendedlayouttechniques

toreducecouplingfromthehighswitchingvoltage/current

traces. Additionally, use low ESR and low impedance X5R

or X7R ceramic input capacitors: up to 5μF per Ampere of

load current may be needed. If necessary, increase ripple

sense voltage by increasing sense resistance value and

Reduce V from its nominal level to verify operation of

IN

the regulator in dropout. Check the operation of the un-

dervoltage lockout circuit by further lowering V while

IN

V

setting, to improve noise immunity.

monitoring the outputs to verify operation.

RNG

38381f

43

For more information www.linear.com3838-1

LTC3838-1

TYPICAL APPLICATIONS

V

IN

4.5V TO 38V

C

+

IN2

C

IN1

10µF

2.2Ω

100µF

×3

1µF

LTC3838-1

–

V

IN

–

SENSE1

SENSE2

15k

0.1µF

15k

+

SENSE1

SENSE2

0.1µF

BOOST1

TG1

BOOST2

TG2

3.57k

L2

MT1

MB1

MT2

MB2

L1

0.56µH

DB1

DB2

0.56µH

V

1.5V

15A

OUT1

1.2V

15A

OUT2

SW1

SW2

2.2Ω

DRV

CC1

DRV

CC2

EXTV

C

+

C

+

C

OUT3

OUT1

OUT2

OUT4

INTV

CC

100µF

330µF

100µF

1µF

4.7µF

×2

BG1

BG2

PGND

10k

15k

+

–

V

DFB2

OUTSENSE1

10k//15k

SGND

10k

–

V

OUTSENSE1

DFB2

100k

22pF

PGOOD1

0.01µF

PGOOD2

PGOOD1

PGOOD2

0.01µF

220pF

C

: NICHICON UCJ1H101MCL1GS

: MURATA GRM32ER71H106K

IN1

IN2

TRACK/SS1 TRACK/SS2

22pF

20k

, C

: SANYO 2R5TPE330M9

OUT2 OUT4

, C

ITH1

ITH2

: MURATA GRM31CR60J107ME39L

OUT1 OUT3

220pF

115k

DB1, DB2: DIODES INC. SDM10K45

L1, L2: TOKO FDA1055-R56M

20k

MT1, MT2: INFINEON BSC093N04LSG

MB1, MB2: INFINEON BSC035N04LSG

DTR1

DTR2

38381 F16a

V

RNG

PHASMD

MODE/PLLIN

CLKOUT

RT

SGND

RUN1

RUN2

100

3.0

2.5

2.0

1.5

1.0

0.5

0

100

FORCED CONTINUOUS MODE

DISCONTINUOUS MODE

FORCED CONTINUOUS MODE

DISCONTINUOUS MODE

90

80

70

60

50

40

2.5

2.0

1.5

1.0

0.5

0

90

80

70

60

50

40

EFFICIENCY

POWER

LOSS

POWER

LOSS

V

= 12V

IN

OUT

V

IN

V

OUT

= 12V

= 1.2V

= 1.5V

0.1

1

10

0.1

1

10

LOAD CURRENT (A)

38381 F16c

38381 F16b

Figure 16. 4.5V to 38V Input, 1.2V/15A and 1.5V/15A Dual Output, 350kHz, DCR Sense, Step-Down Converter

38381f

44

For more information www.linear.com/3838-1

LTC3838-1

TYPICAL APPLICATIONS

V

IN

6V TO 26V

C

+

IN2

C

IN1

220µF

10µF

2.2Ω

×3

LTC3838-1

–

1µF

1nF

V

IN

100Ω

–

SENSE1

SENSE2

1nF

+

SENSE1

SENSE2

0.1µF

2.2Ω

0.1µF

BOOST1

TG1

BOOST2

TG2

MT1

MB1

MT2

MB2

L1

0.47µH

L2

0.47µH

R

S2

S1

0.002Ω

DB1

DB2

V

1.5V

12A

0.002Ω

OUT1

1.2V

12A

OUT2

SW1

SW2

DRV

CC1

DRV

CC2

C

+

C

OUT2

330µF

+

C

OUT1

OUT3

OUT4

INTV

EXTV

CC

100µF

330µF

100µF

1µF

4.7µF

×2

BG1

BG2

PGND

15k

10k

+

–

V

DFB2

OUTSENSE1

10k//15k

SGND

10k

–

V

OUTSENSE1

DFB2

100k

PGOOD1

0.01µF

PGOOD2

0.01µF

PGOOD1

PGOOD2

C

: PANASONIC EEEFK1V221P

IN1

IN2

TRACK/SS1 TRACK/SS2

: TAIYO YUDEN GMK325BJ106MN-T

22pF

, C

: MURATA GRM31CR60J107ME39L

: SANYO 2R5TPE330M9

OUT1 OUT4

, C

ITH1

ITH2

OUT2 OUT3

220pF

115k

220pF

DB1, DB2: CENTRAL SEMI CMDSH-4ETR

L1, L2: WÜRTH 7443330047

MT1, MT2: RENESAS RJK0305DPB

MB1, MB2: RENESAS RJK0330DPB

39.2k

30.1k

DTR1

DTR2

38381 F17a

V

RNG

PHASMD

MODE/PLLIN

CLKOUT

RT

SGND

RUN1

RUN2

Channel 1 Loop Gain

Channel 2 Loop Gain

90

60

50

40

30

20

10

0

60

75

50

40

60

PHASE

45

30

PHASE

30

20

15

10

GAIN

0

–10

–15

–30

–45

–10

–20

–30

–15

–30

–45

–20

–30

10

100

1000

10

100

1000

FREQUENCY (kHz)

38381 F17b

38381 F17c

Bode plots taken with OMICRON Lab Bode 100 Vector Network Analyzer.

Figure 1ꢀ. 4.5V to 26V Input, 1.2V/15A and 1.5V/15A Dual Output, 350kHz, R_SENSE, Step-Down Converter

38381f

45

For more information www.linear.com3838-1

LTC3838-1

TYPICAL APPLICATIONS

V

IN

4.5V TO 14V

C

+

IN2

C

IN1

22µF

2.2Ω

180µF

×4

LTC3838-1

–

1µF

1nF

V

IN

100Ω

–

SENSE1

SENSE2

1nF

+

SENSE1

SENSE2

0.1µF

2.2Ω

0.1µF

BOOST1

TG1

BOOST2

TG2

M1

M2

R

L1

0.47µH

L2

0.47µH

S1

S2

0.0015Ω

DB1

DB2

0.0015Ω

V

1.5V

20A

OUT1

1.2V

20A

OUT2

SW1

SW2

DRV

CC1

DRV

CC2

EXTV

C

+

C

+

OUT3

C

OUT1

OUT2

OUT4

INTV

CC

100µF

330µF

100µF

1µF

4.7µF

×2

BG1

BG2

15k

PGND

+

V

DFB2

+

–

V

OUTSENSE1

10k//15k

SGND

100k

10k

–

V

OUTSENSE1

DFB2

100k

PGOOD1

0.01µF

PGOOD2

0.01µF

PGOOD1

TRACK/SS1 TRACK/SS2

PGOOD2

C

: SANYO 16SVP180MX

IN1

IN2

47pF

: MURATA GRM32ER61C226KE20L

ITH1

ITH2

, C

: MURATA GRM31CR60J107ME39L

: SANYO 2R5TPE330M9

OUT1 OUT4

, C

470pF

137k

470pF

OUT2 OUT3

23.2k

DB1, DB2: CENTRAL SEMI CMDSH-4ETR

L1, L2: WÜRTH 7443330047

M1, M2: INFINEON BSC0911ND

DTR1

DTR2

38381 F18

V

RNG

PHASMD

MODE/PLLIN

CLKOUT

RT

SGND

RUN1

RUN2

4

3

2

1

100

90

80

70

60

10

8

100

90

80

70

60

V

= 12V FCM

= 12V DCM

V

= 5V FCM

= 5V DCM

IN

6

4

LOSS

2

LOSS

0

0.1

V

1

10

100

0.1

1

10

100

LOAD CURRENT (A)

= 12V

V

= 5V

= 12V

IN

38381 F18b

38381 F18c

V

OUT

Figure 18. 4.5V to 14V Input, 1.2V/20A and 1.5V/20A Dual Output, 300kHz, R_SENSE, Step-Down Converter

38381f

46

For more information www.linear.com/3838-1

LTC3838-1

TYPICAL APPLICATIONS

5V TO 5.5V EXTERNAL

V

IN

3.3V TO 14V

C

+

IN2

C

IN1

22µF

2.2Ω

180µF

×4

LTC3838-1

–

1µF

1nF

V

IN

100Ω

–

SENSE1

SENSE2

1nF

+

SENSE1

SENSE2

0.1µF

2.2Ω

0.1µF

BOOST1

TG1

BOOST2

TG2

M1

M2

R

L1

0.47µH

L2

0.47µH

S1

S2

DB1

DB2

0.0015Ω

V

0.9V

20A

OUT1

1.2V

20A

OUT2

SW1

SW2

DRV

CC1

DRV

CC2

C

+

C

+

OUT3

C

OUT1

OUT2

OUT4

INTV

EXTV

CC

100µF

330µF

100µF

1µF

4.7µF

×2

BG1

BG2

10k

PGND

+

V

DFB2

+

–

V

OUTSENSE1

10k

20k//10k

SGND

20k

10k

–

V

OUTSENSE1

DFB2

100k

PGOOD1

0.01µF

PGOOD2

0.01µF

PGOOD1

TRACK/SS1 TRACK/SS2

PGOOD2

C

: SANYO 16SVP180MX

IN1

IN2

47pF

: MURATA GRM32ER61C226KE20L

, C

: MURATA GRM31CR60J107ME39L

: SANYO 2R5TPE330M9

ITH1

ITH2

OUT1 OUT4

, C

470pF

137k

470pF

OUT2 OUT3

23.2k

17.4k

DB1, DB2: CENTRAL SEMI CMDSH-4ETR

L1, L2: WÜRTH 7443330047

M1, M2: INFINEON BSC0911ND

DTR1

DTR2

38381 F19

V

RNG

PHASMD

MODE/PLLIN

CLKOUT

RT

SGND

RUN1

RUN2

Note: When operating with the power V supply below 5.5V, this applicatoin requires the 5V to 5.5V external supply

IN

to be present at EXTV in order to maintain DRV , INTV and V pin voltages needed for the IC to function

CC

IN

properly. The EXTV supply is optional when the power V supply is at or above 5.5V.

CC

IN

Power input voltage range of this application cannot be generalized for other frequency and/or output voltage. Each

application that needs a power input voltage different from the V pin voltage shall be tested individually for margin

IN

of range in which the switching nodes (SW1, SW2) phase-lock to the clock output (CLKOUT).

Figure 19. 3.3V to 14V Power Input, 1.2V/20A and 0.9V/20A Dual Output, 300kHz, R_SENSE, Step-Down Converter

(with Externally-Available 5V to 5.5V Supply)

38381f

47

For more information www.linear.com3838-1

LTC3838-1

TYPICAL APPLICATIONS

V

IN

4.5V TO 14V

C

+

IN2

C

IN1

22µF

2.2Ω

180µF

×4

1µF

LTC3838-1

–

V

IN

–

SENSE1

SENSE2

0.1µF

16.2k

4.02k

16.2k

4.02k

+

SENSE1

SENSE2

0.1µF

2.2Ω

BOOST1

TG1

BOOST2

TG2

MT2

MB2

MT1

MB1

L1

0.4µH

L2

0.4µH

DB1

DB2

V

1.2V

50A

OUT

SW1

SW2

DRV

CC2

CC1

+

C

OUT4

OUT1

OUT2

OUT3

INTV

EXTV

CC

100µF

330µF

100µF

1µF

4.7µF

×2

BG1

BG2

+

PGND

V

20k

+

–

V

DFB2

OUTSENSE1

10k

20k

SGND

100k

–

V

OUTSENSE1

DFB2

PGOOD

PGOOD1

PGOOD2

0.01µF

TRACK/SS1 TRACK/SS2

47pF

ITH1

ITH2

470pF

47.5k

41.2k

DTR1

DTR2

V

RT

SGND

RUN1

PHASMD

C

: SANYO 16SVP180MX

RNG

IN1

IN2

137k

: MURATA GRM32ER61C226KE20L

MODE/PLLIN

CLKOUT

RUN2

, C

: MURATA GRM31CR60J107ME39L

: SANYO 2R5TPE330M9

OUT1 OUT4

, C

OUT2 OUT3

DB1, DB2: CENTRAL SEMI CMDSH-4ETR

L1, L2: VISHAY IHLP5050FDERR40M01

MT1, MT2: INFINEON BSC050NE2LS

MB1, MB2: INFINEON BSC010NE2LS

38381 F20a

10

8

100

FORCED CONTINUOUS MODE

DISCONTINUOUS MODE

8

6

4

2

0

90

80

70

60

50

6

80

POWER

LOSS

POWER

LOSS

EFFICIENCY

4

70

60

50

2

0

0.1

V

1

10

0.1

V

1

LOAD CURRENT (A)

10

LOAD CURRENT (A)

= 12V

= 1.2V

= 5V

= 1.2V

IN

OUT

IN

OUT

38381 F20b

38381 F20c

Figure 20. 4.5V to 14V Input, 1.2V/50A 2-Phase Single Output, 300kHz, DCR Sense, DTR Enabled, Step-Down Converter

38381f

48

For more information www.linear.com/3838-1

LTC3838-1

TYPICAL APPLICATIONS

V

IN

6.5V TO 34V

C

+

IN2

C

IN1

220µF

10µF

2.2Ω

×3

LTC3838-1

–

1µF

1nF

V

IN

20Ω

–

SENSE1

SENSE2

1nF

+

SENSE1

SENSE2

0.1µF

2.2Ω

0.1µF

BOOST1

TG1

BOOST2

TG2

MT1

MB1

MT2

MB2

L1

2.2µH

L2

1.3µH

R

S1

0.002Ω

S2

DB1

DB2

V

3.3V

12A

0.002Ω

OUT1

OUT2

5V

SW1

SW2

12A

DRV

CC1

DRV

CC2

EXTV

+

C

OUT2

150µF

V

INTV

C

OUT1

CC

OUT3

OUT4

100µF

OUT1

100µF

330µF

1µF

4.7µF

×2

BG1

BG2

PGND

45.3k

73.2k

+

–

V

DFB2

OUTSENSE1

10k//45.3k

SGND

10k

–

V

OUTSENSE1

DFB2

100k

PGOOD1

0.01µF

PGOOD2

0.01µF

C

: PANASONIC EEEFK1V221P

PGOOD1

PGOOD2

IN1

IN2

: TAIYO YUDEN GMK325BJ106MN-T

, C : MURATA GRM31CR60J107ME39L

OUT1 OUT4

TRACK/SS1 TRACK/SS2

: SANYO 6TPE150MIC2

22pF

OUT2

OUT3

: SANYO 4TPD330M

ITH1

ITH2

DB1, DB2: DIODES INC. SDM10K45

L1: WÜRTH 7443320220

L2: WÜRTH 7443551130

220pF

53.6k

45.3k

MT1, MT2: INFINEON BSC093N04LSG

MB1, MB2: INFINEON BSC035N04LSG

DTR1

DTR2

38381 F21a

V

RNG

137k

PHASMD

MODE/PLLIN

CLKOUT

RT

SGND

RUN1

RUN2

100

90

80

70

60

50

40

3.0

100

3.0

2.5

2.0

2.5

2.0

1.5

1.0

0.5

0

90

80

70

60

50

40

EFFICIENCY

1.5

1.0

0.5

0

POWER

LOSS

POWER

LOSS

V

= 12V

V

= 12V

IN

OUT

IN

OUT

= 5V

= 3.3V

0.1

1

LOAD CURRENT (A)

10

38381 F21b

0.1

1

10

38381 F21c

LOAD CURRENT (A)

FORCED CONTINUOUS MODE

DISCONTINUOUS MODE

FORCED CONTINUOUS MODE

DISCONTINUOUS MODE

Figure 21. 6.5V to 34V Input, 5V/12A and 3.3V/12A Dual Output, 300kHz, R_SENSE, 5V Output Tied to EXTV_CC, Step-Down Converter

38381f

49

For more information www.linear.com3838-1

LTC3838-1

TYPICAL APPLICATIONS

V

IN

4.5V TO 14V

C

+

IN2

C

IN1

180µF

22µF

2.2Ω

×4

LTC3838-1

–

1µF

1nF

V

IN

10Ω

–

SENSE1

SENSE2

1nF

+

SENSE1

SENSE2

0.1µF

BOOST1

TG1

BOOST2

TG2

MT1

MB1

MT2

MB2

L1

0.3µH

L2

0.3µH

R

S2

S1

DB1

DB2

V

3.3V

25A

0.004Ω

OUT

SW1

SW2

2.2Ω

DRV

CC1

DRV

CC2

EXTV

C

OUT1

100µF

INTV

C

CC

OUT2

100µF

1µF

4.7µF

×3

BG1

BG2

PGND

45.3k

+

–

V

DFB2

OUTSENSE1

10k//45.3k

SGND

10k

–

DFB2

V

OUTSENSE1

100k

PGOOD

0.01µF

PGOOD1

PGOOD2

TRACK/SS1 TRACK/SS2

100pF

51.1k

ITH1

ITH2

DTR1

DTR2

V

RNG

18.7k

PHASMD

MODE/PLLIN

CLKOUT

RT

C

: SANYO 165VP180MX

: MURATA GRM32ER61C226KE20L

, C : MURATA GRM31CR60J107ME39L

IN1

IN2

SGND

C

OUT1 OUT2

RUN1

RUN2

DB1, DB2: CENTRAL CMDSH-3

L1, L2: WÜRTH 7443340030

MT1, MT2: INFINEON BSC050NE2LS

MB1, MB2: INFINEON BSC032NE2LS

38381 F22a

2.5

100

90

80

70

60

50

100

90

80

70

60

50

FORCED CONTINUOUS MODE

DISCONTINUOUS MODE

FORCED CONTINUOUS MODE

DISCONTINUOUS MODE

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

EFFICIENCY

POWER

LOSS

EFFICIENCY

POWER

LOSS

0.01

0.1

= 12V LOAD CURRENT (A)

1

0.01

0.1

1

V

= 12V LOAD CURRENT (A)

IN

OUT

IN

OUT

= 5V

= 3.3V

38381 F22b

38381 F22c

EXTV TIED TO V

EXTV TIED TO 5V BIAS SUPPLY

CC

OUT

EFFICIENCY MEASUREMENTS INCLUDE POWER

FROM THE 5V BIAS SUPPLY

Figure 22. 4.5V to 14V Input, 3.3V/25A Output, 2MHz, R_SENSE, Step-Down Converter

38381f

50

For more information www.linear.com/3838-1

LTC3838-1

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UHF Package

38-Lead Plastic QFN (5mm × 7mm)

(Reference LTC DWG # 05-08-ꢀ70ꢀ Rev C)

0.70 0.05

5.50 0.05

5.ꢀ5 0.05

4.ꢀ0 0.05

3.ꢀ5 0.05

3.00 REF

PACKAGE

OUTLINE

0.25 0.05

0.50 BSC

5.5 REF

6.ꢀ0 0.05

7.50 0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN ꢀ NOTCH

R = 0.30 TYP OR

0.35 × 45° CHAM

0.75 0.05

0.00 – 0.05

3.00 REF

5.00 0.ꢀ0

37 38

0.40 0.ꢀ0

PIN ꢀ

TOP MARK

ꢀ

2

(SEE NOTE 6)

5.ꢀ5 0.ꢀ0

5.50 REF

7.00 0.ꢀ0

3.ꢀ5 0.ꢀ0

(UH) QFN REF C ꢀꢀ07

0.200 REF 0.25 0.05

0.50 BSC

R = 0.ꢀ25

TYP

R = 0.ꢀ0

TYP

BOTTOM VIEW—EXPOSED PAD

NOTE:

ꢀ. DRAWING CONFORMS TO JEDEC PACKAGE

OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3. ALL DIMENSIONS ARE IN MILLIMETERS

38381f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

51

For more information www.linear.com3838-1

LTC3838-1

TYPICAL APPLICATION

7V to 14V Input, 5V/7A and 3.3V/7A Dual Output, 2MHz, R_SENSE, Step-Down Converter with EXTV_CCTied to 5V Output

V

IN

7V TO 14V

C

+

IN2

C

IN1

39µF

10µF

2.2Ω

×3

LTC3838-1

–

1µF

1nF

V

IN

10Ω

–

SENSE1

SENSE2

1nF

+

SENSE1

SENSE2

0.1µF

BOOST1

TG1

BOOST2

TG2

MT2

MB2

MT1

MB1

L1

0.8µH

L2

0.8µH

R

S1

0.008Ω

S2

0.008Ω

DB1

DB2

V

3.3V

7A

OUT1

5V

7A

OUT2

SW1

SW2

2.2Ω

DRV

CC1

DRV

CC2

EXTV

C

OUT2

OUT1

V

INTV

OUT1

CC

47µF

1µF

4.7µF

×2

BG1

BG2

PGND

45.3k

73.2k

+

–

V

DFB2

OUTSENSE1

10k//45.3k

10k

C

FF1

47pF

FF2

SGND

150pF

–

V

OUTSENSE1

DFB2

100k

PGOOD1

0.01µF

PGOOD2

0.01µF

PGOOD1

PGOOD2

TRACK/SS1 TRACK/SS2

22pF

C

: SANYO 16SVP39M

IN1

IN2

ITH1

ITH2

: MURATA GRM32DR61E106K

330pF

18.7k

330pF

, C

: TAIYO YUDEN LMK325BJ476MM-T

OUT1 OUT2

24.9k

35.7k

DB1, DB2: CENTRAL CMDSH-3

L1, L2: COILCRAFT XAL5030-801MEB

MT1, MB1, MT2, MB2: VISHAY Si7114ADN

DTR1

DTR2

38381 TA02

V

RNG

PHASMD

MODE/PLLIN

CLKOUT

RT

SGND

RUN1

RUN2

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

200kHz to 2MHz Operating Frequency, 4.5V ≤ V ≤ 38V,

LTC3833

Fast Controlled On-Time, High Frequency Synchronous

Step-Down Controller with Diff Amp

IN

0.6V ≤ V

≤ 5.5V, 3mm × 4mm QFN-20, TSSOP-20

OUT

LTC3838/LTC3838-2 Dual or Single Output, Controlled On-Time, Synchronous Step- 200kHz to 2MHz Operating Frequency, 4.5V ≤ V ≤ 38V,

IN

Down Controller with Diff Amp(s), Internal/External Reference 0.6V/0.4V ≤ V

≤ 5.5V, 5mm × 7mm QFN-38, TSSOP-38

OUT

LTC3839

Single Output, 2-Channel Fast Controlled On-Time

Synchronous Step-Down Controller with Diff Amp

200kHz to 2MHz Operating Frequency, 4.5V ≤ V ≤ 38V,

IN

0.6V ≤ V

≤ 5.5V, 5mm × 5mm QFN-32

OUT

2

LTC3880/LTC3880-1 Dual Output PolyPhase Step-Down DC/DC Controller with

Digital Power System Management

I C/PMBus Interface with EEPROM and 16-Bit ADC,

V

IN

Up to 24V, 0.5V ≤ V

≤ 5.5V, Analog Control Loop

OUT

LTC3869/LTC3869-2 Dual Output, 2-Phase Synchronous Step-Down DC/DC

Controller, with Accurate Current Sharing

PLL Fixed 250kHz to 750kHz Frequency, 4V ≤ V ≤ 38V,

IN

OUT3

V

Up to 12.5V

LTC3855

Dual Output, 2-phase, Synchronous Step-Down DC/DC

PLL Fixed Frequency 250kHz to 770kHz, 4.5V ≤ V ≤ 38V,

IN

Controller with Diff Amp and DCR Temperature Compensation 0.8V ≤ V

≤ 12V

OUT

LTC3856

Single Output 2-Channel Synchronous Step-Down DC/DC

Controller with Diff Amp and Up to 12-Phase Operation

PLL Fixed 250kHz to 770kHz Frequency, 4.5V ≤ V ≤ 38V,

IN

0.8V ≤ V

≤ 5V

OUT

LTC3861/LTC3861-1 Dual, Multiphase, Synchronous Step-Down DC/DC Controller

with Diff Amp and Three-State Output Drive

Operates with Power Blocks, DRMOS Devices or External Drivers/

MOSFETs, 3V ≤ V ≤ 24V, t = 20ns

IN

ON(MIN)

LTC3850/LTC3850-1 Dual Output, 2-Phase Synchronous Step-Down DC/DC

PLL Fixed 250kHz to 780kHz Frequency, 4V ≤ V ≤ 30V,

IN

LTC3850-2

Controller, R

or DCR Current Sensing

0.8V ≤ V

≤ 5.25V

OUT

SENSE

38381f

LT 0213 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

52

For more information www.linear.com/3838-1

(408)432-1900 FAX: (408) 434-0507 www.linear.com/3838-1

●

 LINEAR TECHNOLOGY CORPORATION 2013


型号：	LTC3880/
厂家：	Linear
描述：	Dual, Fast, Accurate Step-Down DC/DC Controller with Dual Differential Output Sensing 双通道，快速，准确的降压型DC / DC ，带有双差分输出检测器
文件：	总52页 (文件大小：5344K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3880/ [Linear]

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