LTC3880EUJ-1#PBF [Linear]
LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C;型号: | LTC3880EUJ-1#PBF |
厂家: | Linear |
描述: | LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C 开关 |
文件: | 总116页 (文件大小:985K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3880/LTC3880-1
Dual Output PolyPhase
Step-Down DC/DC Controller with
Digital Power System Management
DescripTion
FeaTures
2
The LTC®3880/LTC3880-1 are dual, PolyPhase DC/DC
n
PMBus/I C Compliant Serial Interface
– Telemetry Read Back includes V , I , V , I
,
synchronous step-down switching regulator controllers
IN IN OUT OUT
2
Temperature and Faults
with an I C-based PMBus compliant serial interface.
– Programmable Voltage, Current Limit, Digital
Soft-Start/Stop, Sequencing, Margining, OV/UV
and Frequency Synchronization (250kHz to 1MHz)
0ꢀ5ꢁ Output Voltage Accuracy over Temperature
Integrated 16-Bit ADC
The controllers use a constant frequency, current mode
architecture that is supported by LTpowerPlay™ software
development tool with graphical user interface (GUI).
n
n
n
n
Switching frequency, output voltage, and device address
canbeprogrammedusingexternalconfigurationresistors.
Additionally, parameters can be set via the digital interface
or stored in EEPROM. Voltage, current, internal/external
temperature and fault status can be read back through
the bus interface.
Internal EEPROM and Fault Logging
Integrated Powerful N-Channel MOSFET Gate Drivers
Power Conversion
n
Wide V Range: 4.5V to 24V
OUT
Analog Current Mode Control Loop
Supports Power-Up Into Pre-Biased Load
IN
n
n
n
n
n
V
Range: 0.5V to 5.4V (4V on V
)
OUT0
The LTC3880/LTC3880-1 can be configured for Burst
Mode® operation, discontinuous (pulse-skipping) mode
or continuous inductor current mode. The LTC3880 incor-
porates a 5V linear regulator while the LTC3880-1 uses an
external 5V supply for minimum power loss.
Accurate PolyPhase® Current Sharing for Up to 6 Phases
Available in a 40-Pin (6mm × 6mm) QFN Package
applicaTions
L, LT, LTC, LTM, PolyPhase, Burst Mode, µModule, Linear Technology and the Linear logo are
registered trademarks and No R
and LTpowerPlay are trademarks of Linear Technology
SENSE
Corporation. All other trademarks are the property of their respective owners. Protected by
U.S. Patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 5408150,
7420359. Licensed under U.S. Patent 7000125 and other related patents worldwide.
n
High Current Distributed Power Systems
Telecom, Datacom and Storage Systems
n
n
Intelligent Energy Efficient Power Regulation
Typical applicaTion
V
IN
1µF
10µF
Efficiency and Power Loss
vs Load Current
V
INTV
IN
CC
TG0
TG1
0.1µF
0.1µF
100
90
80
70
60
50
40
30
20
10
0
6
5
4
3
2
1
0
LTC3880
V
V
= 12V
IN
OUT
BOOST0 BOOST1
= 1.8V
1.0µH
0.56µH
V
1.8V
20A
V
OUT1
OUT0
3.3V
15A
SW0
BG0
SW1
BG1
2.15k
0.2µF
1.74k
0.2µF
PGND
+
–
+
SENSE1
–
I
I
V
V
I
I
SENSEO
+
SENSEO
SENSE1
530µF
+
–
V
SENSEO
SENSEO
TSNS0
SENSE1
TSNS1
+
10nF
10nF
530µF
2200pF
2200pF
6.04k
4.99k
I
I
TH1
THO
0.01
0.1
1
10
100
SDA
SCL
ALERT
RUN0
RUN1
GPIO0
GPIO1
FAULT MANAGEMENT
LOAD CURRENT (A)
SOME DETAILS OMITTED
FOR CLARITY
PMBus
INTERFACE
3880 TA01b
V
V
DD33
DD25
SHARE_CLK
SYNC
WP
1µF
1µF
TO/FROM
OTHER LTC DEVICES
WRITE PROTECT
SGND
3880 TA01a
3880fc
1
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
Table oF conTenTs
Featuresꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1
Applications ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1
Typical Application ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1
Descriptionꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1
Table of Contents ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 2
Absolute Maximum Ratingsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 4
Pin Configuration ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 4
Order Informationꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 4
Electrical Characteristicsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 5
Typical Performance Characteristics ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ10
Pin Functionsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ13
Block Diagramꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ15
Operationꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ16
Overview................................................................. 16
Main Control Loop.................................................. 16
EEPROM ................................................................. 17
Power Up and Initialization ..................................... 17
Soft-Start................................................................ 18
Sequencing............................................................. 19
Voltage-Based Sequencing..................................... 19
Shutdown ............................................................... 19
Light Load Current Operation .................................20
Switching Frequency and Phase.............................20
Output Voltage Sensing ..........................................21
Current Sensing......................................................21
Load Sharing ..........................................................22
External/Internal Temperature Sense......................22
RCONFIG (Resistor Configuration) Pins..................23
Fault Detection and Handling..................................23
CRC Failure ........................................................24
Serial Interface .......................................................25
Communication Failure ......................................25
Device Addressing..................................................25
Responses to Timing Faults....................................26
Responses to V OV Faults....................................27
IN
Responses to OT/UT Faults.....................................27
Overtemperature Fault Response—Internal ......27
Overtemperature and Undertemperature
Fault Response—Externals ...............................27
Responses to External Faults .................................27
Bus Timeout Failure................................................28
2
Similarity Between PMBus, SMBus and I C
2-Wire Interface......................................................28
PMBus Serial Digital Interface................................28
PMBus Command Summary ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ32
PMBus Commands.................................................32
*Data Format..........................................................37
Applications Information ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ38
Current Limit Programming....................................38
+
–
I
and I
Pins.........................................38
SENSE
SENSE
Low Value Resistor Current Sensing.......................39
Inductor DCR Current Sensing................................40
Slope Compensation and Inductor Peak Current .... 41
Inductor Value Calculation ...................................... 41
Inductor Core Selection ..........................................42
Power MOSFET and Schottky Diode (Optional)
Selection.................................................................42
Variable Delay Time, Soft-Start and Output Voltage
Ramping .................................................................43
Digital Servo Mode.................................................44
Soft Off (Sequenced Off)........................................44
INTV Regulator....................................................45
CC
Topside MOSFET Driver Supply (C , D ) ................46
B
B
Undervoltage Lockout.............................................46
C and C Selection ...........................................46
IN
OUT
Fault Conditions......................................................47
Open-Drain Pins .....................................................48
Phase-Locked Loop and Frequency
Synchronization......................................................48
Minimum On-Time Considerations..........................49
Responses to V
and I
Faults ........................25
OUT
OUT
Output Overvoltage Fault Response ...................26
Output Undervoltage Response .........................26
Peak Output Overcurrent Fault Response...........26
3880fc
2
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
Table oF conTenTs
RCONFIG (External Resistor
Temperature............................................................76
External Temperature Calibration........................76
External Temperature Limits...............................77
Timing ....................................................................78
Timing—On Sequence/Ramp.............................78
Timing—Off Sequence/Ramp ............................79
Precondition for Restart .....................................79
Fault Response .......................................................80
Fault Responses All Faults..................................80
Fault Responses Input Voltage ...........................80
Fault Responses Output Voltage.........................81
Fault Responses Output Current.........................84
Fault Responses IC Temperature ........................85
Fault Responses External Temperature...............86
Fault Sharing...........................................................87
Fault Sharing Propagation ..................................87
Fault Sharing Response......................................89
Scratchpad .............................................................89
Identification...........................................................90
Fault Warning and Status........................................91
Telemetry................................................................98
NVM Memory Commands .................................... 101
Store/Restore ................................................... 101
Fault Logging.................................................... 102
Block Memory Write/Read................................ 108
Typical Applicationsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 109
Package Description ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 114
Revision History ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 115
Typical Application ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 116
Related Partsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 116
Configuration Pins).................................................49
Voltage Selection................................................49
Frequency and Phase Selection Using
RCONFIG ............................................................50
Address Selection Using RCONFIG..................... 51
Efficiency Considerations .......................................52
Checking Transient Response.................................53
PC Board Layout Checklist .....................................54
PC Board Layout Debugging...................................56
Design Example......................................................57
2
Connecting the USB to the I C/SMBus/PMBus
Controller to the LTC3880 In System......................59
LTpowerPlay: An Interactive GUI for
Digital Power ..........................................................60
PMBus Communication and Command
Processing..............................................................61
PMBus Command Details ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ63
Addressing and Write Protect.................................63
General Configuration Registers.............................65
On/Off/Margin ........................................................66
PWM Config ...........................................................68
Voltage....................................................................70
Input Voltage and Limits.....................................70
Output Voltage and Limits..................................71
Current.................................................................... 74
Input Current Calibration ................................... 74
Output Current Calibration ................................. 74
Input Current ...................................................... 74
Output Current....................................................75
3880fc
3
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
absoluTe maximum raTings (Note 1)
V Voltage................................................. –0.3V to 28V
FREQ_CFG, V
, V
,
IN
OUTn_CFG TRIMn_CFG
............................................ –0.3V to 2.75V
Topside Driver Voltages
ASEL, V
DD25
–
BOOST1, BOOST0.................................. –0.3V to 34V
Switch Voltage (SW1, SW0).......................... –5V to 28V
V
, GPIO0, GPIO1, TSNS0, TSNS1, V
,
DD33
SENSE0
SHARE_CLK, WP, SYNC, ITHn ................. –0.3V to 3.6V
EXTV , INTV , (BOOST1 – SW1),
INTV Peak Output Current................................100mA
CC
CC
CC
(BOOST0 – SW0)......................................... –0.3V to 6V
Operating Junction Temperature Range
+
V
, V
, I , I .......... –0.3V to 6V
(Note 2).................................................. –40°C to 125°C
Storage Temperature Range .................. –40°C to 125°C
SENSE0
SENSE1 SENSE0n SENSE1n
RUN0, RUN1, SDA, SCL, ALERT ................ –0.3V to 5.5V
pin conFiguraTion
LTC3880
LTC3880-1
TOP VIEW
TOP VIEW
40 39 38 37 36 35 34 33 32 31
+
40 39 38 37 36 35 34 33 32 31
+
V
V
I
1
2
3
4
5
6
7
8
9
30
29
28
27
26
25
V
V
I
1
2
3
4
5
6
7
8
9
30
29
28
27
26
25
TG1
TG1
SENSE0
SENSE0
SENSE1
SENSE0
SENSE0
SENSE1
–
+
–
–
+
–
SW1
TSNS1
SW1
TSNS1
I
I
V
V
SENSE1
I
SENSE1
I
SENSE1
SENSE1
I
I
TH0
+
TH0
+
TH1
TH1
41
SGND
41
SGND
I
I
I
I
V
V
SENSE0
SENSE0
DD33
DD33
–
–
24 SHARE_CLK
24 SHARE_CLK
SENSE0
SENSE0
SYNC
SCL
23
22
21
SYNC
SCL
23
22
21
WP
WP
V
V
V
V
DD25
DD25
SDA 10
SDA 10
TRIM1_CFG
TRIM1_CFG
11 12 13 14 15 16 17 18 19 20
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
T
= 125°C, θ = 33°C/W, θ = 2.5°C/W
T
= 125°C, θ = 33°C/W, θ = 2.5°C/W
JMAX
JA
JC
JMAX JA JC
EXPOSED PAD (PIN 41) IS SGND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 41) IS SGND, MUST BE SOLDERED TO PCB
orDer inFormaTion
LEAD FREE FINISH
LTC3880EUJ#PBF
LTC3880IUJ#PBF
LTC3880EUJ-1#PBF
LTC3880IUJ-1#PBF
TAPE AND REEL
PART MARKING*
LTC3880UJ
PACKAGE DESCRIPTION
JUNCTION TEMPERATURE RANGE
–40°C to 105°C
LTC3880EUJ#TRPBF
LTC3880IUJ#TRPBF
LTC3880EUJ-1#TRPBF
LTC3880IUJ-1#TRPBF
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
LTC3880UJ
–40°C to 125°C
LTC3880UJ-1
LTC3880UJ-1
–40°C to 105°C
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3880fc
4
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°Cꢀ (Note 2) VIN = 12V, VRUN0,1 = 3ꢀ3V, fSYNC = 500kHz (externally
driven) unless otherwise specifiedꢀ
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage
l
V
Input Voltage Range
(Note 12)
(Note 14)
4.5
24
V
IN
I
Input Voltage Supply Current
Normal Operation
Q
V
V
= 3.3V, No Caps on TG and BG
= 0V
25
20
mA
mA
RUN0,1
RUN0,1
V
Undervoltage Lockout Threshold
V
V
/V
Falling
/V Rising
INTVCC EXTVCC
3.7
3.95
V
V
UVLO
INTVCC EXTVCC
when V > 4.3V
IN
t
Initialization Time
Time from V Applied Until the TON_DELAY
145
ms
INIT
IN
Timer Starts
Control Loop
l
l
V
V
V
V
Full-Scale Voltage Range 0
Set Point Accuracy (0.6V to 5V)
Resolution
VOUT_COMMAND(1) = 5.500V (Note 9)
5.4
5.6
0.5
V
%
OUT1R0
OUT1R1
OUT0R0
OUT0R1
–0.5
12
Bits
mV
LSB Step Size
1.375
l
l
Full-Scale Voltage Range 1
Set Point Accuracy (0.6V to 2.5V)
Resolution
VOUT_COMMAND(1) = 2.75V (Note 9)
VOUT_COMMAND(0) = 4.095V (Note 9)
VOUT_COMMAND(0) = 2.75V (Note 9)
2.7
–0.5
2.8
0.5
V
%
Bits
mV
12
0.6875
LSB Step Size
l
l
Full-Scale Voltage Range 0
Set Point Accuracy (0.6V to 4.096V)
Resolution
4.0
–0.5
4.2
0.5
V
%
Bits
mV
12
1.375
LSB Step Size
l
l
Full-Scale Voltage Range 1
Set Point Accuracy (0.6V to 2.5V)
Resolution
2.7
–0.5
2.8
0.5
V
%
Bits
mV
12
0.6875
LSB Step Size
l
V
V
Line Regulation
Load Regulation
6V < V < 24V
0.02
%/V
LINEREG
IN
l
l
0.01
–0.01
0.1
–0.1
%
%
∆V = 1.35V – 0.7V
LOADREG
ITH
∆V = 1.35V – 2.0V
ITH
g
Error Amplifier g
Input Current
I =1.22V
TH0,1
3
1
mmho
µA
m0,1
m
l
I
V
= 5.5V
ISENSE
3
ISENSE0,1
V
V
V
V
V
Input Resistance to Ground
Input Resistance to Ground
0V ≤ V ≤ 5.5V
41
37
3
kΩ
SENSERIN0
SENSERIN1
IlLIMIT
SENSE
SENSE
PIN
0V ≤ V ≤ 5.5V
kΩ
PIN
Resolution
bits
l
l
V
Hi Range
Lo Range
68
44
75
50
82
56
mV
mV
ILIMMAX
V
Hi Range
Lo Range
37.5
25
mV
mV
ILMMIN
Gate Drivers
TG0,1
r
f
TG Transition Time:
Rise Time
Fall Time
(Note 4)
t
t
C
C
= 3300pF
= 3300pF
30
30
ns
ns
LOAD
LOAD
BG0,1
r
f
BG Transition Time:
Rise Time
Fall Time
(Note 4)
t
t
C
C
= 3300pF
= 3300pF
30
30
ns
ns
LOAD
LOAD
TG/BG t
BG/TG t
Top Gate Off to Bottom Gate On Delay Time
Bottom Gate Off to Top Gate On Delay Time
Minimum On-Time
(Note 4) C
(Note 4) C
= 3300pF Each Driver
= 3300pF Each Driver
30
30
90
ns
ns
1D
2D
LOAD
LOAD
t
ns
ON(MIN)
3880fc
5
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
The l denotes the specifications which apply over the specified operating
elecTrical characTerisTics
junction temperature range, otherwise specifications are at TA = 25°Cꢀ (Note 2) VIN = 12V, VRUN0,1 = 3ꢀ3V, fSYNC = 500kHz (externally
driven) unless otherwise specifiedꢀ
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
OV/UV Output Voltage Supervisor Channel 0
N
Resolution
8
Bits
V
V0
V0
V0
V0
V0
V0
Voltage Monitoring Range
Voltage Monitoring Range
Threshold Programming Step
Threshold Programming Step
Range Value = 0
Range Value = 1
Range Value = 0
Range Value = 1
Range Value = 0
Range Value = 1
1
4.096
2.7
RANGE0
RANGE1
OUSTP0
OUSTP1
THACC0
0.5
V
22
11
mV
mV
%
l
l
Threshold Accuracy 2V < V
Threshold Accuracy 1V < V
< 4V
2
2
OUT0
OUT0
< 2.5V
%
THACC1
t
t
OV Comparator to GPIO Low Time
UV Comparator to GPIO Low Time
V
V
= 10% of Threshold
= 10% of Threshold
35
100
µs
µs
PROPOV0
PROPUV0
OD
OD
OV/UV Output Voltage Supervisor Channel 1
N
Resolution
8
bits
V
V1
V1
V1
V1
V1
V1
Voltage Range
Range Value = 0
Range Value = 1
Range Value = 0
Range Value = 1
Range Value = 0
Range Value = 1
1
5.5
2.7
RANGE0
RANGE1
OUSTP0
OUSTP1
THACC0
Voltage Range
0.5
V
Step Size
22
11
mV
mV
%
Step Size
l
l
Threshold Accuracy 2V < V
Threshold Accuracy 1V < V
< 5V
2
2
OUT1
< 2.5V
%
THACC1
OUT1
t
t
OV Comparator to GPIO Low Time
UV Comparator to GPIO Low Time
V
V
= 10% of Threshold
= 10% of Threshold
35
100
µs
µs
PROPOV1
PROPUV1
OD
OD
V
Voltage Supervisor
IN
N
Resolution
8
bits
V
V
V
V
V
Full-Scale Voltage
Step Size
4.5
20
INRANGE
INSTP
82
mV
%
l
l
Threshold Accuracy 9.0V < V < 20V
2.5
5
INTHACC
INTHACC\M
PROPVIN
IN
Threshold Accuracy 4.5V < V ≤ 9V
%
IN
t
Comparator Response Time
(VIN_ON and VIN_OFF)
V
= 10% of Threshold
100
µs
OD
Output Voltage Readback
N
Resolution
LSB Step Size
16
244
Bits
µV
V
V
V
Full-Scale Voltage
(Note 10) V
= 0V (Note 8)
RUNn
8
V
%
OFS
l
Total Unadjusted Error
Zero-Code Offset Voltage
Conversion Time
(Note 8) V
> 0.6V
OUTn
0.5
OUT_TUE
OS
500
µV
ms
t
(Note 6)
100
CONVERT
3880fc
6
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°Cꢀ (Note 2) VIN = 12V, VRUN0,1 = 3ꢀ3V, fSYNC = 500kHz (externally
driven) unless otherwise specifiedꢀ
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Voltage Readback
IN
N
Resolution
(Note 5)
10
Bits
V
V
V
Full-Scale Voltage
Total Unadjusted Error
(Note 11)
38.91
IFS
V
> 4.5V (Note 8)
VIN
0.5
2
%
%
IN_TUE
l
t
Conversion Time
(Note 6)
100
ms
CONVERT
Output Current Readback
N
Resolution
LSB Step Size
(Note 5)
10
15.625
31.25
62.5
Bits
µV
µV
µV
µV
+
–
0V ≤ |V
– V
| < 16mV
ISENSE
ISENSE
+
–
16mV ≤ |V
32mV ≤ |V
– V
| < 32mV
ISENSE
ISENSE
ISENSE
ISENSE
ISENSE
ISENSE
+
–
– V
| < 63.9mV
+
–
63.9mV ≤ |V
– V
| < 127.9mV
125
I
I
Full-Scale Current
(Note 7) R
(Note 8) V
= 1mΩ
128
A
%
FS
ISENSE
ISENSE
l
Total Unadjusted Error
Zero-Code Offset Voltage
Conversion Time
> 6mV (Note 15)
1
OUT_TUE
V
28
µV
ms
OS
t
(Note 6)
100
10
CONVERT
Input Current and Duty Cycle Readback
D_RES
D_TUE
Resolution
Bits
%
Total Unadjusted Error
Update Rate
16.3% Duty Cycle
(Note 6)
–3
3
3
t
100
0.25
ms
CONVERT
Temperature Readback (T0, T1, T2)
T
Resolution
°C
°C
RES_T
l
T0,1_TUE
T2_TUE
External TSNS TUE
Internal TSNS TUE
Update Rate
∆V
= 72mV (Note 8)
TSNS
V
= 0.0V, f
= 0kHz (Note 8)
SYNC
1
°C
RUN0,1
t
(Note 6)
120
ms
CONVERT_T
INTV Regulator
CC
l
l
V
V
V
V
Internal V Voltage No Load (LTC3380)
6V < V < 24V
4.8
3.2
5
5.2
2
V
INTVCC
CC
IN
INTV Load Regulation (LTC3380)
I = 0mA to 50mA
CC
0.5
%
LDO_INT
CC
Regulator
DD33
Internal V
Voltage
4.5V < V /V
INTVCC EXTVCC
3.3
70
3.40
V
mA
V
DD33
DD33
I
V
V
V
Current Limit
V
DD33
= GND
LIM(VDD33)
DD33
DD33
DD33
V
V
V
V
Overvoltage Threshold
Undervoltage Threshold
3.5
3.1
DD33_OV
DD33_UV
V
Regulator
DD25
l
Internal V
Voltage
2.25
2.5
50
2.75
V
DD25
DD25
I
V
Current Limit
DD25
V
DD25
= GND
mA
LIM(VDD25)
3880fc
7
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°Cꢀ (Note 2) VIN = 12V, VRUN0,1 = 3ꢀ3V, fSYNC = 500kHz (externally
driven) unless otherwise specifiedꢀ
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillator and Phase-Locked Loop
l
f
Oscillator Frequency Accuracy
SYNC Input Threshold
250kHz < f
< 1MHz Measured Falling
SYNC
7.5
%
OSC
Edge-to-Falling Edge of SYNC with SWITCH_
FREQUENCY = 250.0.and 1000.0
V
V
V
V
Falling
Rising
1
V
V
TH,SYNC
CLKIN
CLKIN
1.5
l
SYNC Low Output Voltage
I
= 3mA
LOAD
0.2
0.4
5
V
OL,SYNC
I
SYNC Leakage Current in Slave Mode
0V ≤ V ≤ 3.6V
µA
LEAKSYNC
PIN
SYNC to Ch0 Phase Relationship Based on
the Falling Edge of Sync and Rising Edge of
TG0
MFR_PWM_CONFIG_LTC3880[2:0] = 0, 2, 3
MFR_PWM_CONFIG_LTC3880[2:0] = 5
MFR_PWM_CONFIG_LTC3880[2:0] = 1
MFR_PWM_CONFIG_LTC3880[2:0] = 4, 6
0
Deg
Deg
Deg
Deg
θSYNC-θ0
60
90
120
SYNC to Ch1 Phase Relationship Based on
the Falling Edge of Sync and Rising Edge of
TG1
MFR_PWM_CONFIG_LTC3880[2:0] = 3
MFR_PWM_CONFIG_LTC3880[2:0] = 0
MFR_PWM_CONFIG_LTC3880[2:0] = 2, 4, 5
MFR_PWM_CONFIG_LTC3880[2:0] = 1
MFR_PWM_CONFIG_LTC3880[2:0] = 6
120
180
240
270
300
Deg
Deg
Deg
Deg
Deg
θSYNC-θ1
EEPROM Characteristics
l
Endurance
(Note 13)
0°C < T < 85°C During EEPROM Write
10,000
10
Cycles
J
Operations
l
l
Retention
(Note 13)
T < T
J
Years
ms
JMAX
Mass_Write Mass Write Operation Time
STORE_USER_ALL, 0°C < TJ < 85°C During
EEPROM Write Operations
440
4100
2.0
Digital Inputs SCL, SDA, RUN0, RUN1, GPIO0, GPIO1
l
l
V
V
V
C
Input High Threshold Voltage
Input Low Threshold Voltage
Input Hysteresis
SCL, SDA, RUN0, RUN1, GPIO0, GPIO1
SCL, SDA, RUN0, RUN1, GPIO0, GPIO1
SCL, SDA
V
V
IH
1.4
IL
0.08
10
V
HYST
PIN
Input Capacitance
10
pF
Digital Input WP
Input Pull-Up Current
I
WP
µA
V
PUWP
Open-Drain Outputs SCL, SDA, GPIO0, GPIO1, ALERT, RUN0, RUN1, SHARE_CLK
Output Low Voltage = 3mA
Digital Inputs SHARE_CLK, WP
l
V
I
0.4
1.8
OL
SINK
l
l
V
V
Input High Threshold Voltage
Input Low Threshold Voltage
1.5
1
V
V
IH
IL
0.6
Leakage Current SDA, SCL, ALERT, RUN0, RUN1
Input Leakage Current
Leakage Current GPIO0, GPIO1
Input Leakage Current
l
l
I
0V ≤ V ≤ 5.5V
5
2
µA
µA
OL
PIN
I
0V ≤ V < 3.6V
GL
PIN
3880fc
8
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°Cꢀ (Note 2) VIN = 12V, VRUN0,1 = 3ꢀ3V, fSYNC = 500kHz (externally
driven) unless otherwise specifiedꢀ
SYMBOL
Digital Filtering of GPIO0, GPIO1
Input Digital Filtering GPIO
Digital Filtering of RUN0, RUN1
Input Digital Filtering RUN
PMBus Interface Timing Characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
3
µs
FLTG
I
10
µs
FLTG
l
l
l
f
t
t
Serial Bus Operating Frequency
10
1.3
0.6
400
kHz
µs
SMB
Bus Free Time Between Stop and Start
BUF
Hold time After Repeated Start Condition.
After this Period, the First Clock is Generated
µs
HD,STA
l
l
t
t
t
Repeated Start Condition Setup Time
Stop Condition Setup Time
0.6
0.6
µs
µs
SU,STA
SU,STO
HD,DAT
Data Hold Time
Receiving Data
Transmitting Data
l
l
0
0.3
µs
µs
0.9
t
t
Data Setup Time
Receiving Data
SU,DAT
l
0.1
µs
Stuck PMBus Timer Non-Block Reads
Stuck PMBus Timer Block Reads
Measured from the Last PMBus Start Event
32
150
ms
ms
TIMEOUT_SMB
l
l
t
t
Serial Clock Low Period
Serial Clock High Period
1.3
0.6
10000
µs
µs
LOW
HIGH
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 6: The data conversion is done in round robin fashion. All inputs
signals are continuously converted for a typical latency of 100ms.
Note 7: The IOUT_CAL_GAIN = 1.0mΩ and MFR_IOUT_CAL_GAIN_TC =
0.0. Value as read from READ_IOUT in amperes.
Note 2: The LTC3880/LTC3880-1 are tested under pulsed load conditions
Note 8: Part tested with PWM disabled. Evaluation in application
demonstrates capability. TUE (%) = ADC Gain Error (%) + 100 • [Zero
Code Offset + ADC Linearity Error]/Actual Value.
such that T ≈ T . The LTC3880E/LTC3880E-1 are guaranteed to meet
J
A
performance specifications from 0°C to 85°C. Specifications over the
–40°C to 105°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3880I/LTC388I-1 are guaranteed over the full –40°C to 125°C
Note 9: All V
commands assume the ADC is used to auto-zero the
OUT
output to achieve the stated accuracy. LTC3880 is tested in a feedback loop
that servos V to a specified value.
OUT
operating junction temperature range. T is calculated from the ambient
J
Note 10: The maximum V
voltage is 5.5V.
OUT
temperature T and power dissipation P according to the following
A
D
Note 11: The maximum V voltage is 28V.
IN
formula:
T = T + (P • θ )
JA
Note 12: When V < 6V, INTV must be tied to V .
IN
CC
IN
J
A
D
Note 13: EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls. The
minimum retention specification applies for devices whose EEPROM
has been cycled less than the minimum endurance specification. The
RESTORE_USER_ALL command (NVM read) is valid over the entire
operating junction temperature range.
The maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 5: The data format in PMBus is 5 bits exponent (signed) and 11 bits
mantissa (signed). This limits the output resolution to 10 bits though the
internal ADC is 16 bits and the calculations use 32-bit words.
Note 14: The LTC3880-1 quiescent current (I ) equals the I of V plus
Q
Q
IN
the I of EXTV
.
CC
Q
Note 15: Guaranteed with a common mode voltage (V ) between 0V and
OUT
5.5V.
3880fc
9
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
Typical perFormance characTerisTics
Efficiency vs Load Current,
OUT = 3ꢀ3V (LTC3880)
Efficiency and Power Loss
vs Input Voltage (LTC3880)
Efficiency vs Load Current,
OUT = 1ꢀ8V (LTC3880)
V
V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
91.0
90.5
2500
2400
2300
2200
2100
2000
1900
1800
V
= 1.8V
= 10A
OUT
OUT
I
90.0
89.5
V
f
= 12V
V
f
= 12V
IN
SW
IN
SW
= 370kHz
= 364kHz
89.0
88.5
88.0
L = 0.56µH
L = 0.56µH
DCR = 1.8m
DCR = 1.8m
CCM
DCM
BM
CCM
DCM
BM
10
100
1000
10000
100000
5
7
9
11
13
15
10
100
1000
10000
100000
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
3880 G02
3880 G01
3880 G03
Load Step
(Burst Mode Operation)
Load Step
(Forced Continuous Mode)
Load Step
(Pulse-Skipping Mode)
I
I
I
LOAD
5A/DIV
LOAD
LOAD
5A/DIV
5A/DIV
INDUCTOR
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
V
V
V
OUT
OUT
OUT
100mV/DIV
100mV/DIV
100mV/DIV
AC-COUPLED
AC-COUPLED
AC-COUPLED
3880 G04
3880 G05
3880 G06
V
V
= 12V
50µs/DIV
V
V
= 12V
50µs/DIV
V
V
= 12V
50µs/DIV
IN
OUT
IN
OUT
IN
OUT
= 1.8V
= 1.8V
= 1.8V
0.3A TO 5A STEP
0.3A TO 5A STEP
0.3A TO 5A STEP
Inductor Current at Light Load
Start-Up into a Pre-Biased Load
Soft-Start Ramp
FORCED
RUN
2V/DIV
RUN
CONTINUOUS
MODE
2V/DIV
2A/DIV
V
OUT
1V/DIV
V
OUT
Burst Mode
OPERATION
2A/DIV
1V/DIV
PULSE-SKIPPING
MODE
3880 G09
3880 G08
t
= 10ms
= 5ms
5ms/DIV
t
t
= 10ms
= 5ms
5ms/DIV
RISE
RISE
DELAY
2A/DIV
t
DELAY
3880 G07
V
V
LOAD
= 12V
1µs/DIV
IN
= 1.8V
OUT
I
= 100µA
3880fc
10
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
Typical perFormance characTerisTics
Current Sense Threshold
Maximum Current Sense Threshold
vs Duty Cycle, VOUT = 0V
Soft-Off Ramp
vs ITH Voltage (Low Range)
55
60
50
40
30
50mV SENSE CONDITION
54
RUN
2V/DIV
53
52
51
50
49
48
47
46
45
V
OUT
1V/DIV
20
10
3880 G10
t
t
= 5ms
DELAY
5ms/DIV
FALL
0
–10
–20
= 10ms
V
V
50mV
25mV
SENSE
SENSE
0.5
1
2
0
30
50
70
90
0
2.5
1.5
(V)
DUTY CYCLE (%)
V
ITH
3880 G12
3880 G11
Maximum Current Sense Threshold
vs Common Mode Voltage
Regulated Output
vs Temperature
SHARE_CLK Frequency
vs Temperature
0.5025
0.5020
0.5015
0.5010
0.5005
0.5000
0.4995
0.4990
0.4985
0.4980
0.4975
55
54
53
52
51
50
49
48
47
46
45
110
105
100
95
50mV SENSE CONDITION
90
0
1
3
4
5
6
–50
70 90
–50 –30 –10 10 30 50 70 90 110
TEMPERATURE (°C)
2
–30 –10 10
30
TEMPERATURE (°C)
50
110
COMMON MODE VOLTAGE (V)
3880 G13
3880 G14
3880 G15
SHARE-CLK Frequency vs VIN
Quiescent Current vs Temperature
VOUT Measurement vs VOUT
0.40
0.30
0.20
0.10
0
30
25
20
15
101.0
100.5
100.0
99.5
–0.10
–0.20
–0.30
–0.40
99.0
6
8
10 12 14 16 18 20 22 24 26 28
(V)
0.5
1
1.5
2
2.5
V
3
3.5
(V)
4
4.5
5
5.5
–50 –30 –10 10 30 50 70 90 110
TEMPERATURE (°C)
V
IN
OUT
3880 G16
3880 G18
3880 G17
3880fc
11
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
Typical perFormance characTerisTics
VOUT Command INL
VOUT Command DNL
INTVCC Line Regulation
5.25
5.00
4.75
2.0
1.5
0.3
0.2
1.0
0.5
0.1
0
4.50
4.25
4.00
3.75
3.50
0
–0.5
–1.0
–0.1
–0.2
–0.3
10
15
(V)
25
5
20
0.5
1
1.5
2
2.5
V
3
3.5
(V)
4
4.5
5
5.5
0.5
1
1.5
2
2.5
V
3
3.5
(V)
4
4.5
5
5.5
V
OUT
OUT
IN
3880 G21
3880 G19
3880 G20
V
OUT OV Threshold
VOUT OV Threshold
vs Temperature (2V Target)
VOUT OV Threshold
vs Temperature (4V Target)
vs Temperature (1V Target)
4.04
4.03
4.02
4.01
4.00
3.99
3.98
3.97
3.96
1.010
1.005
1.000
0.995
2.03
2.02
2.01
2.00
1.99
1.98
1.97
0.990
75 100
TEMPERATURE (°C)
–50 –25
0
25 50
125 150
–50 –30 –10 10 30 50 70 90 110
TEMPERATURE (°C)
75 100
TEMPERATURE (°C)
–50 –25
0
25 50
125 150
3880 G24
3880 G22
3880 G23
Temperature Error
vs Temperature
IOUT Error vs IOUT Room
Temperature
IIN Measurement Error vs IIN
1.0
0.8
2
0
8
6
0.6
4
–2
0.4
2
0.2
–4
–6
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–2
–4
–6
–8
–8
–10
–12
10
OUTPUT CURRENT (A)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
(A)
–45 –25 –5 15 35 55 75 95 115
ACTUAL TEMPERATURE (°C)
0
5
15
20
I
IN
3880 G25
3880 G26
3880 G27
3880fc
12
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
Typical perFormance characTerisTics
DC Output Current Matching in a
2-Phase System (LTC3880)
Dynamic Current Sharing During a
Load Transient in a 4-Phase System
Dynamic Current Sharing During a
Load Transient in a 4-Phase System
25
20
15
CURRENT
5A/DIV
CURRENT
10
10
0
5A/DIV
0
10
5
3880 G29
3880 G30
5µs/DIV
5µs/DIV
CHAN 0
CHAN 1
0
20
TOTAL CURRENT (A)
0
5
10 15
25 30 35 40
3880 G28
pin FuncTions
+
V
(Pin 1): Channel 0 Positive Voltage Sense
(Pin 2): Channel 0 Negative Voltage Sense
(Pin 5/Pin 26 ): Current Control Threshold and
SCL (Pin 9): Serial Bus Clock Input. Open-drain output,
can hold the output low if clock stretching is enabled. A
pull-up resistor to 3.3V is required in the application.
SENSE0
Input.
–
V
SENSE0
Input.
SDA (Pin 10): Serial Bus Data Input and Output. A pull-up
resistor to 3.3V is required in the application.
I
/I
TH0 TH1
Error Amplifier Compensation Nodes. Each associated
ALERT (Pin 11): Open-Drain Digital Output. Connect the
SMBALERT signal to this pin. A pull-up resistor to 3.3V
is required in the application.
channel’scurrentcomparatortrippingthresholdincreases
with its I voltage.
TH
+
+
I
/I
(Pins6/Pin3):CurrentSenseCompara-
GPIO0/GPIO1 (Pin 12/Pin 13): Digital Programmable
General Purpose Inputs and Outputs. Open-drain output.
A pull-up resistor to 3.3V is required in the application.
SENSE0 SENSE1
tor Inputs. The (+) inputs to the current comparators are
normally connected to DCR sensing networks or current
sensing resistors.
RUN0/RUN1(Pin14/Pin15):EnableRunInput.Logichigh
on these pins enables the controller. Open-drain output
holds the pin low until the LTC3880 is out of reset. A pull-
up resistor to 3.3V is required in the application.
–
–
I
/I
(Pin7/Pin4):CurrentSenseComparator
SENSE0 SENSE1
Inputs. The (–) inputs are connected to the low side of the
current sense element.
SYNC (Pin 8): External Clock Synchronization Input and
Open-Drain Output Pin. If an external clock is present at
this pin, the switching frequency will be synchronized to
the external clock. If clock master mode is enabled, this
pin will pull low at the switching frequency with a 500ns
pulse to ground. A resistor pull up to 3.3V is required in
the application if the LTC3880 is the master.
ASEL (Pin 16): Serial Bus Address Configuration Input.
Connect a 1% resistor divider between the chip V
DD25
ASEL and SGND in order to select the 4LSBs of the se-
rial bus interface address. A resistor divider on ASEL is
recommended if there are more than 1 LTC3880 on the
sameboardtoassuretheusercanindependentlyprogram
each IC. If the pin is left open, the IC will use the value
programmed in the NVM. Minimize capacitance when the
pin is open to assure accurate detection of the pin state.
3880fc
13
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pin FuncTions
FREQ_CFG (Pin 17): Frequency or Phase Set/Select Pin.
Connect a 1% resistor divider between the chip V
FREQ_CFGandSGNDinordertoselectswitchingfrequency
or phase. If the pin is left open, the IC will use the value
programmed in the NVM. Minimize capacitance when the
pin is open to assure accurate detection of the pin state.
INTV (Pin 33) LTC3880: Internal Regulator 5V Out-
CC
put. The control circuits are powered from this voltage.
Decouple this pin to PGND with a minimum of 4.7µF low
ESR tantalum or ceramic capacitor.
DD25
EXTV (Pin 33) LTC3880-1: External Regulator 5V
CC
input. The control circuits are powered from this voltage.
Decouple this pin to PGND with a minimum of 4.7µF low
ESR tantalum or ceramic capacitor.
V
/V
(Pin 18/Pin 19): Output Voltage
OUT0_CFG OUT1_CFG
Select Pin. Connect a 1% resistor divider between the
chipV n_CFGandSGNDinordertoselectoutput
V
DD25 OUT
PGND(Pin34):PowerGroundPin.Connectthispinclosely
voltage.ThisvoltagecanbeadjustedwiththeV
n_CFG
TRIM
to the sources of the bottom N-channel MOSFETs, the (–)
pins. If the pin is left open, the IC will use the value pro-
grammed in the NVM. Minimize capacitance when the
pin is open to assure accurate detection of the pin state.
terminal of C
and the (–) terminal of C .
VCC
IN
V
(Pin 35): Main Input Supply. Decouple this pin to
IN
PGND with a capacitor (0.1µF to 1µF). For applications
V
/V
(Pin 20/Pin 21): Voltage Trim
TRIM0_CFG TRIM1_CFG
where the main input power is 5V, tie the V and INTV
pins together.
IN
CC
Select Pin. Connect a 1% resistor divider between the
chip V n_CFG and SGND in order to adjust
V
DD25 TRIM
BG0/BG1 (Pin 36/Pin 32): Bottom Gate Driver Outputs.
the output voltage set point. The V
n_CFG settings
TRIM
These pins drive the gates of the bottom N-Channel
in conjunction with the V n_CFG setting adjusts the
OUT
MOSFETs between PGND and INTV .
voltage set point. If the pin is left open, the IC will either
CC
not modify the V n_CFG setting or use NVM. Minimize
OUT
BOOST0/BOOST1(Pin37/Pin31):BoostedFloatingDriver
Supplies. The (+) terminal of the booststrap capacitors
connect to these pins. These pins swing from a diode
voltage drop below INTV up to V + INTV .
capacitance when the pin is open to assure accurate de-
tection of the pin state.
V
DD25
(Pin 22): Internally Generated 2.5V power Supply
CC
IN
CC
Output Pin. Bypass this pin to SGND with a low ESR 1µF
capacitor. Do not load this pin with external current except
for the 1% resistor dividers required for the configura-
tion pins.
TG0/TG1 (Pin 38/Pin 30): Top Gate Driver Outputs. These
aretheoutputsoffloatingdriverswithavoltageswingequal
to INTV superimposed on the switch node voltages.
CC
SW0/ SW1 (Pin 39/Pin 29): Switch Node Connections to
WP (Pin 23): Write Protect Pin Active High. An internal
Inductors. Voltage swings at the pins are from a Schottky
10µA current source pulls the pin to V . If WP is high,
DD33
the PMBus writes are restricted.
diode (external) voltage drop below ground to V .
IN
TSNS0/TSNS1 (Pin 40/Pin 28): Channel 0,1 External
DiodeTemperatureSense. Connecttotheanodeofadiode
connected PNP transistor and star connect the cathode
to SGND in order to sense remote temperature. If exter-
nal temperature sense elements are not installed, short
pin to ground and set the UT_FAULT_LIMIT to –275°C,
IOUT_CAL_GAINsettozeroandtheUT_FAULT_RESPONSE
to ignore.
SHARE_CLK (Pin 24): Share Clock, Bidirectional Open-
Drain Clock Sharing Pin. Nominally 100kHz. Used to
synchronize thetimingbetweenmultipleLTC3880s.Tieall
SHARE_CLK pins together. All LTC3880s will synchronize
to the fastest clock. A pull-up resistor to 3.3V is required.
V
DD33
(Pin 25): Internally Generated 3.3V Power Supply
Output Pin. Bypass this pin to SGND with a low ESR 1µF
capacitor. Do not load this pin with external current except
for the pull-up resistors required for GPIOn, SCLK, SYNC
and possibly RUNn, ALERT, SDA and SCL.
SGND (Exposed Pad Pin 41): Signal Ground. All small-
signal and compensation components should connect to
this ground, which in turn connects to PGND at one point.
V
(Pin 27): Channel 1 Voltage Sense Input. This
SENSE1
input voltage is referenced to the SGND pin.
3880fc
14
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
block Diagram (One of two channels (CH0) shown)
V
IN
35
V
IN
+
V
ON/OFF
19R
38R
R
IN
C
IN
5V REG
LTC3880
ONLY
+
–
R
INTV /EXTV (LTC3880-1)
CC
CC
33
8-BIT V
DAC
IN
INTV /EXTV
CC
CC
SGND
V
DD33
25
3.3V
SUBREG
V
DD33
BOOST0
S
R
PWM_CLOCK
37
Q
TG0
C
D
B
I
I
REV
3k
CMP
–
+
M1
38
FCNT
+
–
SW0
ON
UV
39
+
SWITCH
LOGIC
I
I
SENSE0
6
B
REV
UVLO
SS
AND
ANTI-
SHOOT-
THROUGH
–
SENSE0
7
V
OUT0
I
RANGE SELECT
HI: 1:1
LO: 1:1.5
+
LIM
C
RUN
OV
OUT
BG0
36
M2
C
VCC
34
SLOPE
PGND
COMPENSATION
+
–
–
+
NO DIFF AMP ON CH1
R
R
+
–
+
INTV
UVLO
CC
1
–
+
+
–
V
V
SENSE0
16-BIT
ADC
–
+
–
8:1
+
–
+
AO
I
I
V
SENSE1
SENSE1
ACTIVE
CLAMP
I
DAC
LIM
(3 BITS)
MUX
–
+
SENSE0
2
1
R
R
SENSE1
71.1k
I
–
+
TH0
5
PWM0
PWM1
–
+
2µA
30µA
41
SGND
–
R
C
+
C
C1
TSNS0
40
BURST
EA
UV
OV
TMUX
–
–
–
–
+
+
+
+
V
STBY
9R
2R
SGND
0.56V
SGND
1.22V
REF
12-BIT
SET POINT
DAC
8-BIT
UV
DAC
8-BIT
OV
DAC
SGND
PHASE DET
8
SYNC
M3
SGND
V
CO
PWM
CLOCK
PHASE SELECTOR
CLOCK DIVIDER
V
DD33
V
DD25
V
V
DD33
2.5V
22
V
DD25
WP
SCL
23
SUBREG
SLAVE
MISO
DD33
COMPARE
PMBus
INTERFACE
(400kHz
9
SDA
10
11
COMPATIBLE)
18
19
20
21
V
V
V
V
OUT0_CFG
OUT1_CFG
TRIM0_CFG
TRIM1_CFG
CLK MOSI
MASTER
MAIN
CONTROL
OSC
(32MHz)
ALERT
3
SINC
UVLO
RUN0
14
CONFIG
DETECT
RUN1 15
CHANNEL
TIMING
MANAGEMENT
PROGRAM
ROM
17 FREQ_CFG
16 ASEL
RAM
EEPROM
GPIO0
GPIO1
12
13
3880 F01
SHARE_CLK 24
Figure 1ꢀ Block Diagram
3880fc
15
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
operaTion
OVERVIEW
n
n
n
n
n
n
Average Output Current
Average PWM Duty Cycle
Average Output Voltage
Average Input Voltage
Average Input Current
The LTC3880 is a dual channel/dual phase, constant fre-
quency, analog current mode controller for DC/DC step-
down applications with a digital interface. The LTC3880
digitalinterfaceiscompatiblewithPMBuswhichsupports
bus speeds of up to 400kHz. A typical application circuit
is shown on the first page of this data sheet.
Configurable, Latched and Unlatched Individual Fault
and Warning Status
Major features include:
n
Programmable Output Voltage
IndividualchannelsareaccessedthroughthePMBususing
the PAGE command, i.e., PAGE 0 or 1.
n
n
n
n
n
n
n
Programmable Input Voltage Comparator
Programmable Current Limit
Fault reporting and shutdown behavior are fully configu-
rable. Two individual GPIO outputs are provided (GPIO0,
GPIO1), both of which can be masked independently. A
dedicatedpinforALERTisprovided. Theshutdownopera-
tionalsoallowsallfaultstobeindividuallymaskedandcan
beoperatedineitherunlatched(hiccup)orlatchedmodes.
Programmable Switching Frequency
Programmable OV and UV Comparators
Programmable On and Off Delay Times
Programmable Output Rise/Fall Times
Individual status commands enable fault reporting over
the serial bus to identify the specific fault event. Fault or
warning detection includes the following:
Phase-LockedLoopforSynchronous,PolyphaseOpera-
tion (2, 3, 4 or 6 Phases)
n
Input and Output Voltage/Current, Temperature and
Duty Cycle Telemetry
n
n
n
n
n
n
Output Undervoltage/Overvoltage
Input Undervoltage/Overvoltage
Input and Output Overcurrent
Internal Overtemperature
n
n
n
n
Fully Differential Load Sense
Integrated Gate Drivers
Non-Volatile Configuration Memory
External Overtemperature
Optional External Configuration Resistors for Key
Operating Parameters
Communication, Memory or Logic (CML) Fault
n
Optional Time-Base Interconnect for Synchronization
Between Multiple Controllers
MAIN CONTROL LOOP
The LTC3880 is a constant frequency, current mode step-
down controller containing two channels operating with
various user-defined relative phasing. During normal
operation each top MOSFET is turned on when the clock
for that channel sets the RS latch, and turned off when
n
n
n
n
Fault Logging
WP Pin to Protect Internal Configuration
StandaloneOperationAfterUserFactoryConfiguration
PMBus, 400kHz Compliant Interface
the main current comparator, I
, resets the RS latch.
CMP
The peak inductor current at which I
resets the RS
TH
CMP
The PMBus interface provides access to important power
management data during system operation including:
latch is controlled by the voltage on the I pin which is
the output of each error amplifier, EA. The EA negative
n
Internal Controller Temperature
terminal is equal to the V
voltage divided by 5.5
SENSE
n
(2.75 if range = 1). The positive terminal of the EA is
External System Temperature via Optional Diode Sense
Elements
connectedtotheoutputofa12-bitDACwithvaluesranging
3880fc
16
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
operaTion
from 0V to 1.024V. The output voltage, through feedback
of the EA, will be regulated to 5.5 times the DAC output
(2.75 times if range = 1). The DAC value is calculated by
the part to synthesize the users desired output voltage.
The output voltage is programmed by the user either
with the resistor configuration pins detailed in Tables 12
It is recommended that the EEPROM not be written
when the die temperature is greater than 85°C. If the die
temperature exceeds 130°C, the LTC3880 will disable all
EEPROM write operations. All EEPROM write operations
will be re-enabled when the die temperature drops below
125°C. (The controller will also disable when the die
temperature exceeds the internal overtemperature fault
limit 160°C with a 10°C hysteresis)
and 13 or by the V
command (either from NVM or
OUT
by PMBus command). Refer to the PMBus command
section of the data sheet or the PMBus specification for
more details. The output voltage can be modified by the
user at any time with a PMBus VOUT_COMMAND. This
command will typically have a latency less than 10ms.
The user is encouraged to reference the PMBus Power
SystemManagementProtocolSpecificationtounderstand
how to program the LTC3880. This specification can be
found at http://www.pmbus.org/specs.html.
The degradation in EEPROM retention for temperatures
>125°C can be approximated by calculating the dimen-
sionless acceleration factor using the following equation:
Ea
k
1
1
•
–
AF = e
T
USE +273 TSTRESS+273
where:
AF = acceleration factor
Continuing the basic operation description, the current
mode controller will turn off the top gate when the peak
Ea = activation energy = 1.4eV
current is reached. If the load current increases, V
SENSE
–5
K = 8.617 • 10 eV/°K
will slightly droop with respect to the DAC reference.
T
T
= 125°C specified junction temperature
USE
This causes the I voltage to increase until the average
TH
inductor current matches the new load current. After the
top MOSFET has turned off, the bottom MOSFET is turned
on. In continuous conduction mode, the bottom MOSFET
stays on until the end of the switching cycle.
= actual junction temperature in °C
STRESS
Example: Calculate the effect on retention when operating
at a junction temperature of 135°C for 10 hours.
T
T
= 130°C
STRESS
EEPROM
= 125°C
[(1.4/8.617 • 10–5) • (1/398 – 1/403)]
USE
The LTC3880 contains internal EEPROM (nonvolatile
memory) to store configuration settings and fault log
information. EEPROM endurance retention and mass
write operation time are specified in the Electrical Char-
acteristics and Absolute Maximum Ratings sections.
AF= e
= 1.66
The equivalent operating time at 125°C = 16.6 hours.
Thus the overall retention of the EEPROM was degraded
by 16.6 hours as a result of operating at a junction tem-
peratureof130°Cfor10hours.Theeffectoftheoverstress
is negligible when compared to the overall EEPROM
retention rating of 87,600 hours at a maximum junction
temperature of 125°C.
Write operations above T = 85°C are possible although
J
the Electrical Characteristics are not guaranteed and the
EEPROM will be degraded. Read operations performed at
temperatures between 85°C and 125°C will not degrade
the EEPROM. Writing to the EEPROM above 85°C will
result in a degradation of retention characteristics. The
faultloggingfunction,whichisusefulindebuggingsystem
problemsthatmayoccurathightemperatures,onlywrites
tofaultlogEEPROMlocations.Ifoccasionalwritestothese
registers occur above 85°C, the slight degradation in the
data retention characteristics of the fault log will not take
away from the usefulness of the function.
POWER UP AND INITIALIꢂATION
The LTC3880 is designed to provide standalone supply
sequencing and controlled turn-on and turn-off opera-
tion. It operates from a single input supply (4.5V to 24V)
while three on-chip linear regulators generate internal
3880fc
17
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
operaTion
2.5V, 3.3V and 5V. If V is below 6V, the INTV and V
multiple LTC3880s are used in an application, they all hold
their respective run pins low until all devices initialize and
IN
IN
CC
IN
pins must be tied together. The controller configuration
is initialized by an internal threshold based UVLO where
V exceeds the VIN_ON threshold for every device. The
V must be approximately 4V and the 5V, 3.3V and 2.5V
SHARE_CLK pin assures all the devices connected to the
IN
linear regulators must be within approximately 20% of
signalusethesametimebase.TheSHARE_CLKpinisheld
the regulated values. The LTC3880-1 does not have an
low until the part has initialized after V is applied. The
IN
internal 5V linear regulators. The EXTV pin is driven by
LTC3880canbesettoturnoff(orremainoff)ifSHARE_CLK
is low (set bit 2 of MFR_CHAN_CONFIG_LTC3880 to a 1).
This allows the user to assure synchronization across
numerous LTC ICs even if the RUN pins can not be con-
nected together due to board constraints. In general, if
the user cares about synchronization between chips it is
best to connect all the respective RUN pins together and
to connect all the respective SHARE_CLK pins together.
This assures all chips begin sequencing at the same time
and use the same time base.
CC
an external regulator to improve efficiency of the circuit
and minimize power on the LTC3880. The EXTV pin
CC
must exceed approximately 4V before the internal UVLO
is exceeded. To minimize application power, the EXTV
pin can be supplied by a switching regulator.
CC
During initialization, the external configuration resistors
are identified and/or contents of the NVM are read into
the controller’s commands. The GPIOn pins are in high
impedance (Hi-Z) mode. The TGn, BGn and RUNn pins
are held low. The LTC3880 will use the contents of Tables
12 to 15 to determine the resistor defined parameters.
See the Resistor Configuration section for more detail.
The resistor configuration pins only control some of the
preset values of the controller. The remaining values are
programmed in NVM either at the factory or by the user.
After the RUN pin releases and prior to entering a constant
output voltage regulation state, the LTC3880 performs a
monotonic initial ramp or “soft-start”. Soft-start is per-
formedbyactivelyregulatingtheloadvoltagewhiledigitally
ramping the target voltage from 0V to the commanded
voltageset-point.OncetheLTC3880iscommandedtoturn
on, (after power up and initialization) the controller waits
for the user specified turn-on delay (TON_DELAY) prior
to initiating this output voltage ramp. The rise time of the
voltage ramp can be programmed using the TON_RISE
commandtominimizeinrushcurrentsassociatedwiththe
start-up voltage ramp. The soft-start feature is disabled
by setting the value of TON_RISE to any value less than
0.25ms. The LTC3880 PWM always uses discontinuous
mode during the TON_RISE operation. In discontinuous
mode, the bottom gate is turned off as soon as reverse
current is detected in the inductor. This will allow the
regulator to start up into a pre-biased load. When the
TON_MAX_FAULT_LIMIT is reached, the part transi-
tions to continuous mode or burst, if so programmed. If
TON_MAX_FAULT_LIMIT is set to zero, there is no time
limit and the part transitions to the desired conduction
If the configuration resistors are not inserted or if the
ignore RCONFIG bit is asserted (bit 6 of the MFR_
CONFIG_ALL_LTC3880 configuration command), the
LTC3880 will use only the contents of NVM to determine
the DC/DC characteristics. The ASEL value read at power-
up or reset is always respected unless the pin is open.
The ASEL will use the MSB from NVM and the LSB from
the detected threshold. See the Applications Information
section for more detail.
After the part has initialized, an additional comparator
monitors V . The VIN_ON threshold must be exceeded
IN
before the output power sequencing can begin. After V
IN
is initially applied, the part will typically require 130ms to
initialize and begin the TON_DELAY timer. The readback of
voltages and currents may require an additional 100ms.
mode after TON_RISE completes and V
has exceeded
OUT
the VOUT_UV_FAULT_LIMIT and IOUT_OC is not pres-
ent. Setting TON_MAX_FAULT_LIMIT to a value of 0 is
not recommended. This described method of start-up
sequencing is time based.
SOFT-START
The part must enter the run state prior to soft-start.
The run pins are released by the LTC3880 after the part
initializes and V is greater than the VIN_ON threshold. If
IN
3880fc
18
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
operaTion
SEQUENCING
the UV threshold and the GPIO pin releasing This can be
implementedacrossmultipleLTC3880s.TheVOUT_UVUF
The default mode for sequencing the outputs on and off is
time based. Each output is enabled after waiting TON_DE-
LAY amount of time following either a RUN pin going high,
has a 250µs filter. If the V
voltage bounces around the
OUT
UV threshold for a long period of time it is possible for
the GPIO output to toggle more than once. To minimize
this problem, set the TON_RISE time under 100ms. If a
fault in the string of rails is detected, only the faulted rail
and downstream rails will fault off. The rails in the string
of devices in front of the faulted rail will remain on unless
commanded off.
a PMBus command to turn on or the V rising above a
IN
preprogrammed voltage. Off sequencing is handled in a
similar way. To assure proper sequencing, make sure all
ICs connect the SHARE_CLK pin together and RUN pins
together. IftheRUNpinscannotbeconnectedtogetherfor
some reason, set bit 2 of MFR_CHAN_CONFIG_LTC3880
to a 1. This bit requires the SHARE_CLK pin to be clocking
beforethepowersupplyoutputcanstart.WhentheRUNpin
ispulledlow,theLTC3880willholdthepinlowfortheMFR_
RESTART_DELAY. The minimum MFR_RESTART_DELAY
isTOFF_DELAY+TOFF_FALL+136ms.Thisdelayassures
proper sequencing of all rails. The LTC3880 calculates
this delay internally and will not process a shorter delay.
However, a longer commanded MFR_RESTART_DELAY
will be used by the part. The maximum allowed value is
65.52 seconds.
SHUTDOWN
The LTC3880 supports two shutdown modes. The first
mode is closed-loop shutdown response, with user-
defined turn-off delay (TOFF_DELAY) and ramp down
rate (TOFF_FALL). The controller will maintain the mode
of operation for TOFF_FALL. In discontinuous conduction
mode, the controller will not draw current from the load
and the fall time will be set by the output capacitance and
load current.
The other shutdown mode occurs in response to a fault
condition or loss of SHARE_CLK (if bit 2 of MFR_CHAN_
VOLTAGE-BASED SEQUENCING
The GPIOn pins can be asserted when the UV threshold is
exceeded for each output. It is possible to feed the GPIO
pin from one output into the RUN pin of the next output
in the sequence. To use the GPIOn pin for voltage based
sequencing, set bit 12 of the MFR_GPIOn_PROPAGATE
command = 1. Bit 12 is the VOUT_UVUF which is the
unfiltered VOUT_UV comparator. Using the unfiltered
VOUT_UVfaultlimitisrecommendedbecausethereislittle
appreciable time delay between the comparator crossing
CONFIG_LTC3880 is set to a 1) or V falling below the
IN
VIN_OFF threshold or GPIO pulled low externally (if the
MFR_GPIO_RESPONSE is set to inhibit). Under these
conditions the power stage is disabled in order to stop
the transfer of energy to the load as quickly as possible.
The shutdown state can be entered from the soft-start or
active regulation states either through user intervention
(deasserting RUNn or the PMBus OPERATION command)
or in response to a detected fault or an external fault via
the bidirectional GPIOn pins, or loss of SHARE_CLK (if
bit 2 of MFR_CHAN_CONFIG_LTC3880 is set to a 1) or
Voltage Based Sequencing by Cascading GPIOs into RUN Pins
GPIO0 = V
RUN 0
RUN 1
OUT0_UVUF
OUT1_UVUF
START
V falling below the VIN_OFF threshold.
IN
LTC3880
GPIO1 = V
In hiccup mode, the controller responds to a fault by
shutting down and entering the inactive state for a
programmable delay time (MFR_RETRY_DELAY). This
delay minimizes the duty cycle associated with autono-
mous retries if the fault that caused the shutdown disap-
pears once the output is disabled. The retry delay time
is determined by the longer of the MFR_RETRY_DELAY
command or the time required for the regulated output
to decay below 12.5% of the programmed value. If
3880fc
RUN 0
RUN 1
GPIO0 = V
GPIO1 = V
OUT0_UVUF
LTC3880
OUT1_UVUF
3880 F02
TO NEXT CHANNEL
IN THE SEQUENCE
Figure 2ꢀ Event (Voltage) Based Sequencing
19
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
operaTion
multiple outputs are controlled by the same GPIO pin,
the decay time of the faulted output determines the retry
delay. If the natural decay time of the output is too long,
it is possible to remove the voltage requirement of the
MFR_RETRY_DELAY command by asserting bit 0 of
MFR_CHAN_CONFIG_LTC3880. Alternatively, the con-
troller can be configured so that it remains latched-off
following a fault and clearing requires user intervention
such as toggling RUNn or commanding the part OFF
then ON.
mode exhibits lower output ripple and less interference
with audio circuitry. Forced continuous conduction mode
may result in reverse inductor current, which can cause
the input supply to boost. The VIN_OV_FAULT_LIMIT can
detectthisandturnofftheoffendingchannel.However,this
fault is based on an ADC read and can take up to 100ms
to detect. If there is a concern about the input supply
boosting, keep the part in discontinuous conduction or
Burst Mode operation.
If the part is set to Burst Mode operation, as the inductor
average current increases, the controller will automati-
cally modify the operation from Burst Mode operation,
to discontinuous mode to continuous mode.
LIGHT LOAD CURRENT OPERATION
The LTC3880 has three modes of operation including high
efficiency Burst Mode operation, discontinuous conduc-
tion mode or forced continuous conduction mode. Mode
selection is done using the MFR_PWM_MODE_LTC3880
command (discontinuous conduction is always the start-
upmode, forcedcontinuousisthedefaultrunningmode).
SWITCHING FREQUENCY AND PHASE
The switching frequency of the LTC3880’s controller can
be established with internal clock references or with an
external time-base. The LTC3880 can be configured for an
externalclockinputthroughtheprogrammedvalueinNVM,
In Burst Mode operation the peak current in the inductor
is set to approximately one-third of the maximum sense
a PMBus command or setting the R
resistor of the
BOTTOM
to open. The PMBus
voltage even though the voltage on the I pin indicates a
FREQ_CFG pin to 0Ω and the R
TH
TOP
lower value. If the average inductor current is higher than
command FREQUENCY_SWITCH is set to external clock.
TheMFR_PWM_CONFIG_LTC3880commanddetermines
the relative phasing. Using the RCONFIG input, channel 0
and channel 1 have a relative phasing of 0° and 180° with
respect to the falling edge of SYNC. The master should
be selected to be out of phase with the slave. Both RUN
pins must be low or both channels commanded off before
theFREQUENCYandMFR_PWM_CONFIG_LTC3880com-
mands can be written to the LTC3880. The relative phas-
ing of all devices in a PolyPhase rail should be optimally
phased. The relative phasing of each rail is 360/n where
n is the number of phases in the rail.
the load current, the error amplifier, EA, will decrease the
voltage on the I pin. When the I voltage drops below
TH
TH
approximately 0.5V, the internal Burst Mode operation as-
serts and both external MOSFETS are turned off. In Burst
Mode operation, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA output
begins to rise. When the output voltage drops sufficiently,
Burst Mode operation is deasserted, and the controller
resumes normal operation by turning on the top external
MOSFET on the next PWM cycle.
If a controller is enabled for Burst Mode operation, the
inductor current is not allowed to reverse. The reverse
currentcomparator,I ,turnsoffthebottomgateexternal
If the LTC3880 is configured as the oscillator output on
SYNC,theswitchingfrequencysourcecanbeselectedwith
either external configuration resistors or through serial
busprogramming.TheFREQ_CFGconfigurationresistor
pin can be used to select the FREQUENCY_SWITCH
and MFR_PWM_CONFIG_LTC3880 values as outlined
in Table 14. Otherwise, the FREQUENCY_SWITCH and
MFR_PWM_CONFIG_LTC3880PMBuscommandscanbe
used to select PWM switching frequency and the PWM
channel phase relationship. The phase and frequency
3880fc
REV
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus, the
controllercanoperateindiscontinuousoperation.Inforced
continuousoperation,theinductorcurrentisallowedtore-
verseatlightloadsorunderlargetransientconditions.The
peak inductor current is determined solely by the voltage
on the I pin. In this mode, the efficiency at light loads is
TH
lower than in Burst Mode operation. However, continuous
20
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
operaTion
relationships are completely independent of each other
providing the numerous application options for the user.
If the LTC3880 is configured to drive the SYNC pin using
theprogrammedFREQUENCY_SWITCHcommandvalue,
the SYNC pin will pull low at the desired clock rate with
500ns low pulse. Care must be taken in the application to
assure the capacitance on SYNC is minimized to assure
the pull-up resistor versus the capacitor load has a low
enough time constant for the application. In addition,
a phase-locked loop (PLL) is available to synchronize
the internal oscillator to an external clock source that is
connected to the SYNC pin. All phase relationships are
between the falling edge of SYNC and the rising edge
of the LTC3880 TG outputs. Multiple LTC3880s can be
synchronized in order to realize PolyPhase arrays.
limitations of the internal amplifier for V
, the maxi-
SENSE0
mum allowed differential sense voltage is 4.096V.
CURRENT SENSING
For DCR current sense applications, a resistor in series
with a capacitor is placed across the inductor. In this
configuration, the resistor is tied to the FET side of the
inductor while the capacitor is tied to the load side of the
inductor as shown in Figure 3. If the RC values are cho-
sen such that the RC time constant matches the inductor
time constant (L/DCR, where DCR is the inductor series
resistance), theresultantvoltage(V )appearingacross
DCR
the capacitor will equal the voltage across the inductor
series resistance and thus represent the current flowing
through the inductor. The RC calculations are based on
the room temperature DCR of the inductor.
OUTPUT VOLTAGE SENSING
The RC time constant should remain constant, as a func-
tionoftemperature.Thisassuresthetransientresponseof
the circuit is the same regardless of the temperature. The
DCR of the inductor has a large temperature coefficient,
approximately 3900ppm/°C. The temperature coefficient
of the inductor must be written to the MFR_IOUT_CAL_
GAIN_TC register. The external temperature is sensed
The channel 0 differential amplifier allows remote, dif-
ferential sensing of the load voltage with V
pins.
SENSE0n
) is referenced to SGND.
The channel 1 sense pin (V
SENSE1
ThetelemetryADCisfullydifferentialandmakesmeasure-
ments of channels 0 and 1 output voltages at the V
SENSE0n
and V
/SGND pins, respectively. Due to head room
SENSE1
LTC3880 + POWER STAGE
I
I
TH0
TH1
+
–
10k 4.99k 10k 10k 10k
I
I
V
V
SENSE0
SENSE0
GPIO0
+
–
RUN
RUN0
RUN1
ALERT
GPIO1
SYNC
SHARE_CLK
V
SENSE0
SENSE0
ALERT
GPIO
SYNC
+
–
I
I
SHARE_CLK
SENSE1
SENSE1
DD33
1µF
V
SENSE1
SGND
PGND
1/2 LTC3880 + POWER STAGE
I
TH0
DD33
V
1µF
+
–
I
I
RUN0
SENSE0
SENSE0
ALERT
GPIO1
SYNC
SHARE_CLK
+
–
V
V
SENSE0
SENSE0
LOAD
SGND
PGND
NOTE: SOME CONNECTORS
AND COMPONENTS OMITTED
FOR CLARITY
3880 F03
Figure 3ꢀ Load Sharing Connections for 3-Phase Operation
3880fc
21
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
operaTion
near the inductor and used to modify the internal current
parallelwiththediodeconnectedPNP.Twodifferentcurrents
are applied to the diode (nominally 2µA and 32µA) and the
limit circuit to maintain an essentially constant current
+
limit with temperature. In this application, the I
temperatureiscalculatedfromthe∆V measurement.The
SENSEn
BE
pin is connected to the FET side of the capacitor while the
external transistor temperature is digitized by the telem-
etry ADC, and the value is returned by the PMBus READ_
TEMPERATURE_1 (Chn)command.
–
I
pin is placed on the load side of the capacitor.
SENSEn
The current sensed from the input is then given by the
expression V /DCR. V is digitized by the LTC3880’s
DCR
DCR
TheREAD_TEMPERATURE_2commandreturnsthejunc-
tion temperature of the LTC3880 using an on-chip diode.
The slope of the external temperature sensor can be
modified with the temperature slope coefficient stored in
MFR_TEMP_1_GAIN. Typical PNPs require temperature
slopeadjustmentsslightlylessthan 1.TheMMBT3906has
a recommended value in this command of approximately
MFR_TEMP_1_GAIN = 0.991 based on the ideality factor
of 1.01. Simply invert the ideality factor to calculate the
MFR_TEMP_1_GAIN. Different manufacturers and differ-
ent lots may have different ideality factors. Consult with
the manufacturer to set this value.
telemetry ADC with an input range of 128mV, a noise
floor of 7µV , and a peak-peak noise of approximately
RMS
46.5µV. TheLTC3880computestheinductorcurrentusing
the DCR value stored in the IOUT_CAL_GAIN command
and the temperature coefficient stored in command
MFR_IOUT_CAL_GAIN_TC. The resulting current value
is returned by the READ_IOUT command.
LOAD SHARING
Multiple LTC3880’s can be arrayed in order to provide a
balanced load-share solution by bussing the necessary
pins. Figure 3 illustrates the shared connections required
for load sharing.
Theoffsetoftheexternaltemperaturesensecanbeadjusted
byMFR_TEMP_1_OFFSET.Avalueof0inthisregistersets
the temperature offset to –273.15°C.
The frequency must only be programmed on one of the
LTC3880s. The other(s) must be programmed to External
Clock.
If the PNP cannot be placed in direct contact with the
inductor, the slope or offset can be increased to account
for temperature mismatches. If the user is adjusting the
slope,theinterceptpointisatabsolutezero,–273.15°C,so
small adjustments in slope can change the apparent mea-
sured temperature significantly. Another way to artificially
increase the slope of the temperature term is to increase
the MFR_IOUT_CAL_GAIN_TC term. This will modify the
temperature slope with respect to room temperature.
EXTERNAL/INTERNAL TEMPERATURE SENSE
Externaltemperaturecanbebestmeasuredusingaremote
diode-connected PNP transistor such as the MMBT3906.
TheemittershouldbeconnectedtotheTSNSnpinwhilethe
base and collector terminals of the PNP transistor should
be returned to the LTC3880’s SGND pin, preferably using a
starconnection.Itispossibletoconnectthecollectorofthe
PNPtothesourceofthebottomMOSFET.Thismayoptimize
boardlayoutallowingthePNPcloserproximitytothepower
FETs.ThebaseofthePNPmuststillbetiedtosignalground.
Forbestnoiseimmunity,theconnectionsshouldberouted
differentially and a 10nF capacitor should be placed in
TSNS
LTC3880
SGND
10nF
MMBT3906
SGND
3880 F04
Figure 4ꢀ Temperature Sense Circuit
3880fc
22
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
operaTion
RCONFIG (RESISTOR CONFIGURATION) PINS
up, bit 3 of the MFR_CONFIG_ALL_LTC3880 command
must be asserted. If the SYNC pin is connected between
multiple ICs only one of the ICs can be the oscillator, all
other ICs must be configured to external clock.
There are six input pins utilizing 1% resistor dividers be-
tweenV
andSGNDtoselectkeyoperatingparameters.
DD25
The pins are ASEL, FREQ_CFG, V
, V
,
OUT0_CFG OUT1_CFG
. If pins are floated, the value
V
and V
The ASEL pin settings are described in Table 15. This
pin selects the bottom 4 bits of the slave address for the
LTC3880. The 3 most significant bits are retrieved from
the NVM MFR_ADDRESS command. If the pin is floating,
the 7-bit value stored in NVM MFR_ADDRESS command
is used to determine the slave address. For more detail,
refer to Table 15a.
TRIM0_CFG
TRIM1_CFG
stored in the corresponding NVM command is used. If
bit 6 of the MFR_CONFIG_ALL_LTC3880 configuration
command is asserted in NVM, the resistor inputs are
ignored upon power-up except for ASEL which is always
respected. The resistor configuration pins are only mea-
sured during a power-up reset or after an MFR_RESET
command is executed.
Note: Per the PMBus specification, pin programmed
parameters can be overridden by commands from the
digital interface with the exception of ASEL which is
always honored. Do not set any part address to 0x5A or
0x5B because these are global addresses and all parts
will respond to them.
The V
and V
pin settings are described in
OUTn_CFG
TRIMn
Tables 12 and 13. These pins select the output voltages
for the LTC3880’s analog PWM controllers. If both pins
are open, the VOUT_COMMAND command is loaded from
NVM to determine the output voltage.
The following parameters are set as a percentage of the
outputvoltageiftheRCONFIGpinsareusedtodetermined
output voltage:
FAULT DETECTION AND HANDLING
A variety of fault and warning reporting and handling
mechanisms are available. Fault and warning detection
capabilities include:
n
n
n
n
n
n
n
n
n
VOUT_OV_FAULT_LIMIT.................................... +10%
VOUT_OV_WARN.............................................. +7.5%
VOUT_MAX....................................................... +7.5%
VOUT_MARGIN_HI..............................................+5%
POWER_GOOD_ON .............................................–7%
POWER_GOOD_OFF............................................–8%
VOUT_MARGIN_LO.............................................–5%
VOUT_UV_WARN..............................................–6.5%
VOUT_UV_FAULT_LIMIT......................................–7%
n
Input OV/FAULT Protection and UV Warning
n
Average Input OC Warn
n
n
n
n
n
n
Output OV/UV Fault and Warn Protection
Output OC Fault and Warn Protection
Internal and External Overtemperature Fault Protection
External Undertemperature Fault and Warn Protection
CML Fault (Communication, Memory or Logic)
TheFREQ_CFGpinsettingsaredescribedinTable14. This
pinselectstheswitchingfrequencyandphaserelationships
betweenthetwochannelsandSYNCpin.Tosynchronizeto
an external clock, the part must be put into external clock
mode (FREQ_CFG pin shorted to ground). If no external
clock is supplied, the part will clock at the lowest free-
running frequency of the internal PWM oscillator. This low
clock rate will increase the ripple current of the inductor
possibly producing undesirable operation. If the external
SYNC signal is missing or misbehaving, a “PLL Lock Sta-
tus” fault will be indicated in the STATUS_MFR_SPECIFIC
command. If the user does not wish to see the PLL_FAULT
even if there is not a valid synchronization signal at power
External Fault Detection via the Bidirectional GPIOn
Pins.
In addition, the LTC3880 can map any combination of fault
indicatorstotheirrespectiveGPIOn pinusingthepropagate
GPIOn response commands, MFR_GPIO_PROPAGATE_
LTC3880. Typical usage of a GPIO pin is as a driver for an
externalcrowbardevice,overtemperaturealert,overvoltage
alert or as an interrupt to cause a microcontroller to poll
the fault commands. Alternatively, the GPIOn pins can be
3880fc
23
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
operaTion
used as inputs to detect external faults downstream of
the controller that require an immediate response. The
GPIO0and/orGPIO1pinscanalsobeconfiguredaspower
good outputs. Power good indicates the controller output
is above the power good threshold. At power-up the pin
will initially be three-state. If it is necessary to have the
desired polarity on the pin at power-up in this configura-
tion, attach a Schottky diode between the RUN pin of the
propagated power good signal and the GPIO pin. The
Cathode must be attached to RUN and the Anode to the
GPIO pin. If the GPIO pin is set to a power good status, the
MFR_GPIO_RESPONSE must be ignore otherwise there
is a latched off condition with the controller.
Channel-to-channel fault dependencies can be created by
connecting GPIOn pins together. In the event of an internal
fault, one or more of the channels is configured to pull
the bussed GPIOn pins low. The other channels are then
configured to shut down when the GPIOn pins are pulled
low. For autonomous group retry, the faulted channel
is configured to let go of the GPIOn pin(s) after a retry
interval, assuming the original fault has cleared. All the
channels in the group then begin a soft-start sequence.
If the fault response is LATCH_OFF, the GPIO pin remains
asserted low until either the RUN pin is toggled OFF/ON or
the part is commanded OFF/ON. The toggling of the RUN
either by the pin or OFF/ON command will clear faults as-
sociated with the channel. If it is desired to have all faults
cleared when either RUN pin is toggled, set bit 0 of MFR_
CONFIG_ALL_LTC3880 to a 1.
As described in the Soft-Start section, it is possible to
control start-up through concatenated events. If GPIOn
is used to drive the RUN pin of another controller, the
unfiltered VOUT_UV fault limit should be mapped to the
GPIO pin.
The status of all faults and warnings is summarized in the
STATUS_WORD and STATUS_BYTE commands.
Any fault or warning event will cause the ALERT pin to
assert low. The pin will remain asserted low until the
CLEAR_FAULTScommandisissued, thefaultbitiswritten
to a 1 or bias power is cycled or a MFR_RESET command
isissued.ChannelspecificfaultsareclearediftheRUNpins
are toggled OFF/ON or the part is commanded OFF/ON via
PMBus. If bit 0 of MFR_CONFIG_ALL_LTC3880 is set to
a 1, toggling the RUN pins OFF/ON clears all faults. The
MFR_GPIO_PROPAGATE_LTC3880commanddetermines
if the GPIO pins are pulled low when a fault is detected;
however, the ALERT pin is always pulled low if a fault or
warning is detected and the status bits are updated.
Additional fault detection and handling capabilities are:
CRC Failure
TheintegrityoftheNVMmemoryischeckedafterapower-
onreset.ACRCfailurewillpreventthecontrollerfromleav-
ingtheinactivestate. IfaCRCfailureoccurs, theCMLbitis
setintheSTATUS_BYTEandSTATUS_WORDcommands,
the appropriate bit is set in the STATUS_MFR_SPECIFIC
command, and the ALERT pin will be pulled low. NVM
repair can be attempted by writing the desired configura-
tion to the controller and executing a STORE_USER_ALL
command followed by a CLEAR_FAULTS command.
Output and input fault event handling is controlled by the
correspondingfault response byteas specifiedinTables 5
to 9. Shutdown recovery from these types of faults can
either be autonomous or latched. For autonomous re-
covery, the faults are not latched, so if the fault condition
is not present after the retry interval has elapsed, a new
soft-start is attempted. If the fault persists, the controller
will continue to retry. The retry interval is specified by the
MFR_RETRY_DELAY command and prevents damage to
the regulator components by repetitive power cycling,
assuming the fault condition itself is not immediately
destructive. The MFR_RETRY_DELAY must be greater
than 120ms. It can not exceed 83.88 seconds.
The LTC3880 manufacturing section of the NVM is mir-
rored. The LTC3880 has the ability to operate if either
one of the two sections of the manufacturing section
of the NVM configuration becomes corrupted. If a
discrepancy is detected, the “NVM CRC Fault” in the
STATUS_MFR_SPECIFIC command is set. If this bit re-
mainssetafterbeingclearedbyissuingaCLEAR_FAULTS
or writing a 1 to this bit, an irrecoverable internal fault has
occurred. The user is cautioned to disable both output
powersupplyrailsassociatedwiththisspecificpart.There
are no provisions for field repairing unrecoverable NVM
faults in the manufacturing section.
3880fc
24
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
operaTion
SERIAL INTERFACE
Device addressing provides the standard means of the
PMBus master communicating with a single instance
of an LTC3880. The value of the device address is set
by a combination of the ASEL configuration pin and the
MFR_ADDRESS command. When this addressing means
isused, thePAGEcommanddeterminesthechannelbeing
acted upon. Device addressing can be disabled by writing
a value of 0x80 to the MFR_ADDRESS.
The LTC3880 serial interface is a PMBus compliant slave
device and can operate at any frequency between 10kHz
and 400kHz. The address is configurable using either the
NVMoranexternalresistordivider.InadditiontheLTC3880
always responds to the global broadcast address of 0x5A
(7 bit) or 0x5B (7 bit). Address 0x5A is not paged and
is performed on both channels. 0x5B respects the page
command. Because address 0x5A does not support page,
it can not be used for any paged reading commands.
Channel addressing provides a means for the PMBus
master addressing a single channel of the LTC3880
without using the PAGE command. The value assigned
to the paged MFR_CHANNEL_ADDRESS determines the
specific channel the user wishes to act upon. Example: If
MFR_CHANNEL_ADDRESS for page 0 is set to 0x57 and
the MFR_CHANNEL_ADDRESS for page 1 is set to 0x54,
theusercanaddresschannel0ofthedevicebyperforming
PMBus device commands using address 0x57 (7 bit). The
user can address channel 1 of the device by performing
PMBusdevicecommandsusingaddress0x54(7bit).This
eliminatestheuserfromfirstassigningthePAGEcommand
and then the command to be acted upon.
Theserialinterfacesupportsthefollowingprotocolsdefined
in the PMBus specifications: 1) send command, 2) write
byte, 3) write word, 4) group, 5) read byte, 6) read word
and 7) read block. All read operations will return a valid
PECifthePMBusmasterrequestsit.IfthePEC_REQUIRED
bit is set in the MFR_CONFIG_ALL_LTC3880 command,
the PMBus write operations will not be acted upon until
a valid PEC has been received by the LTC3880.
Communication Failure
PEC write errors (if PEC_REQUIRED is active), attempts
to access unsupported commands, or writing invalid data
to supported commands will result in a CML fault. The
CML bit is set in the STATUS_BYTE and STATUS_WORD
commands, the appropriate bit is set in the STATUS_CML
command, and the ALERT pin is pulled low.
Rail addressing provides a means for the PMBus master
addressingasetofchannelsconnectedtothesameoutput
rail, simultaneously. This is similar to global addressing,
however, thePMBusaddresscanbedynamicallyassigned
by using the MFR_RAIL_ADDRESS command. The MFR_
-
RAIL_ADDRESS is paged, so channels can be indepen
dentlyassignedtoaspecificrail.Itisrecommendedthatrail
addressingshouldbelimitedtocommandwriteoperations.
DEVICE ADDRESSING
The LTC3880 offers five different types of addressing over
the PMBus interface, specifically: 1) global, 2) device, 3)
channel, 4) rail addressing and 5) alert response address
(ARA).
All five means of PMBus addressing require the user to
employdisciplinedplanningtoavoidaddressingconflicts.
RESPONSES TO V
AND I
FAULTS
OUT
OUT
GlobaladdressingprovidesameansofthePMBusmasterto
addressallLTC3880devicesonthebus.TheLTC3880global
address is fixed 0x5A (7 bit) or 0xB4 (8 bit) and cannot be
disabled. Commands sent to the global address act the
sameasifPAGEissettoavalueof0xFF.Commandssentare
writtentobothchannelssimultaneously.Globalcommand
0x5B (7 bit) or 0xB6 (8 bit) is paged and allows channel
specific command of all LTC3880 devices on the bus.
V
OVandUVconditionsaremonitoredbycomparators.
OUT
The OV and UV limits are set in three ways.
n
n
n
As a Percentage of the V
figuration Pins
if Using the Resistor Con-
OUT
In NVM if Either Programmed at the Factory or Through
the GUI
By PMBus Command
3880fc
25
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
operaTion
The I and I
overcurrent monitors are performed by
Output Undervoltage Response
IN
OUT
ADC readings and calculations. Thus these values are
based on average currents and can have a time latency of
The response to an undervoltage comparator output can
be either:
up to 100ms. The I
calculation accounts for the sense
OUT
n
Ignore
resistor and the temperature coefficient of the resistor.
The input current is equal to the sum of output current
times the respective channel duty cycle plus the input
offset current for each channel. If this calculated input
current exceed the IN_OC_WARN_LIMIT the ALERT pin
is pulled low and the IIN_OC_WARN bit is asserted in the
STATUS_INPUT register.
n
Shut Down Immediately—Latch Off
n
ShutDownImmediately—RetryIndefinitelyattheTime
Interval Specified in MFR_RETRY_DELAY
The UV responses can be deglitched. See Table 6.
Peak Output Overcurrent Fault Response
The digital processor within the LTC3880 provides the
ability to ignore the fault, shut down and latch off or shut
down and retry indefinitely (hiccup). The retry interval
is set in MFR_RETRY_DELAY and can be from 120ms
to 83.88 seconds in 1ms increments. The shutdown for
OV/UV and OC can be done immediately or after a user
selectable deglitch time.
Due to the current mode control algorithm, peak output
current across the inductor is always limited on a cycle by
cycle basis. The value of the peak current limit is specified
in sense voltage in the EC table. The current limit circuit
operatesbylimitingtheI maximumvoltage.IfDCRsens-
TH
ing is used, the I maximum voltage has a temperature
TH
dependency directly proportional to the TC of the DCR
of the inductor. The LTC3880 automatically monitors the
external temperature sensors and modifies the maximum
Output Overvoltage Fault Response
A programmable overvoltage comparator (OV) guards
against transient overshoots as well as long-term over-
voltages at the output. In such cases, the top MOSFET is
turned off and the bottom MOSFET is turned on until the
overvoltage condition is cleared regardless of the PMBus
VOUT_OV_FAULT_RESPONSEcommandbytevalue. This
hardware level fault response delay is typically 2µs from
the overvoltage condition to BG asserted high. Using the
VOUT_OV_FAULT_RESPONSE command, the user can
select any of the following behaviors:
allowed I to compensate for this term.
TH
The overcurrent fault processing circuitry can execute the
following behaviors:
n
Current Limit Indefinitely
n
Shut Down Immediately—Latch Off
n
ShutDownImmediately—RetryIndefinitelyattheTime
Interval Specified in MFR_RETRY_DELAY
Theovercurrentresponsescanbedeglitchedinincrements
of (0-7) • 16ms. See Table 7
n
OV Pull-Down Only (OV cannot be ignored)
n
Shut Down (Stop Switching) Immediately—Latch Off
RESPONSES TO TIMING FAULTS
n
ShutDownImmediately—RetryIndefinitelyattheTime
TON_MAX_FAULT_LIMIT is the time allowed for V
to
OUT
Interval Specified in MFR_RETRY_DELAY
rise and settle at start-up. The TON_MAX_FAULT_LIMIT
condition is predicated upon detection of the VOUT_UV_
FAULT_LIMIT as the output is undergoing a SOFT_START
sequence. The TON_MAX_FAULT_LIMIT time is started
Either the Latch Off or Retry fault responses can be de-
glitched in increments of (0-7) • 10µs. See Table 5.
3880fc
26
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
operaTion
after TON_DELAY has been reached and a SOFT_START
sequence is started. The resolution of the TON_MAX_
FAULT_LIMIT is 10µs. If the VOUT_UV_FAULT_LIMIT is
not reached within the TON_MAX_FAULT_LIMIT time,
the response of this fault is determined by the value of
the TON_MAX_FAULT_RESPONSE command value. This
response may be one of the following:
Overtemperature and Undertemperature
Fault Response—Externals
Two external temperature sensors can be used to sense
criticalcircuitelementslikeinductorsandpowerMOSFETs.
The OT_FAULT_RESPONSE and UT_FAULT_RESPOSE
commandsareusedtodeterminetheappropriateresponse
to an overtemperature and undertemperature condition,
respectively. If no external sense elements are used
(not recommended) set the UT_FAULT_RESPONSE to
ignore and set the UT_FAULT_LIMIT to –275°C.
n
Ignore
n
Shut Down (Stop Switching) Immediately—Latch Off
n
ShutDownImmediately—RetryIndefinitelyattheTime
Interval Specified in MFR_RETRY_DELAY
The fault responses are:
n
Ignore
This fault response is not deglitched. A value of 0 in
TON_MAX_FAULT_LIMIT means the fault is ignored. The
TON_MAX_FAULT_LIMIT should be set longer than the
TON_RISE time. It is recommended TON_MAX_FAULT_
LIMIT always be set to a non-zero value, otherwise the
outputmaynevercomeupandnoflagwillbesettotheuser.
n
n
Shut Down Immediately—Latch Off
ShutDownImmediately—RetryIndefinitelyattheTime
Interval Specified in MFR_RETRY_DELAY
See Table 9.
See Table 9.
RESPONSES TO EXTERNAL FAULTS
RESPONSES TO V OV FAULTS
When either GPIOn pin is pulled low, the OTHER bit is set
intheSTATUS_WORDcommand,theappropriatebitisset
in the STATUS_MFR_SPECIFC command, and the ALERT
pinispulledlow.Responsesarenotdeglitched.Eachchan-
nel can be configured to ignore or shut down then retry
in response to its GPIOn pin going low by modifying the
MFR_GPIO_RESPONSE command. To avoid the ALERT
pin asserting low when GPIO is pulled low, assert bit 1 of
MFR_CHAN_CONFIG_LTC3880.
IN
V overvoltage is measured with the MUX’d ADC; there-
IN
fore, the response is naturally deglitched by the 100ms
typical response time of the ADC. The fault responses are:
n
Ignore
n
Shut Down Immediately—Latch Off
n
ShutDownImmediately—RetryIndefinitelyattheTime
Interval Specified in MFR_RETRY_DELAY
FAULT LOGGING
See Table 9.
The LTC3880 has fault logging capability. Data is logged
into memory in the order shown in Table 11. The data to
be stored in the fault log is being continuously stored in
internal volatile memory. When a fault event occurs, the
recording into internal volatile memory is halted, the fault
log information is available from the MFR_FAULT_LOG
command, and the contents of the internal memory are
copied into NVM. Fault logging is allowed at temperatures
above 85°C; however, retention of 10 years is not guaran-
teed. When the die temperature exceeds 130°C the fault
logging is delayed until the die temperature drops below
120°C. After the fault condition that created the fault log
RESPONSES TO OT/UT FAULTS
Overtemperature Fault Response—Internal
An internal temperature sensor protects against NVM
damage.Above85°C,nowritestoNVMarerecommended.
Above 130°C, the part disables the NVM and does not
re-enable until the temperature has dropped to 120°C.
Temperature is measured by the ADC. Internal tempera-
ture faults cannot be ignored. Internal temperature limits
cannot be adjusted by the user.
See Table 9.
event has been removed, clear the fault before the fault
3880fc
27
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
operaTion
log data is erased, or else the part will immediately issue
another fault log.
bytecommandsbecausePMBus/SMBusprovidetime-outs
to prevent bus hangs and optional packet error checking
(PEC) to ensure data integrity. In general, a master device
When the LTC3880 powers-up, it checks the NVM for
a valid fault log. If a valid fault log exists in NVM, the
“ValidFaultLog”bitintheSTATUS_MFR_SPECIFICcom-
mand will be set and an ALERT event will be generated.
Also, fault logging will be blocked until the LTC3880 has
received a MFR_FAULT_LOG_CLEAR command before
fault logging will be re-enabled.
2
that can be configured for I C communication can be
used for PMBus communication with little or no change
to hardware or firmware. Repeat start (restart) is not
2
supported by all I C controllers but is required for SMBus/
2
PMBus reads. If a general purpose I C controller is used,
check that repeat start is supported.
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification
Part 1 Revision 1.1: Paragraph 5: Transport.
TheinformationisstoredinEEPROMintheeventofanyfault
that disables the controller on either channel. An external
GPIOn pulling low will not trigger a fault logging event.
For a description of the differences between SMBus and
2
I C, refer to System Management Bus (SMBus) Speci-
BUS TIMEOUT FAILURE
fication Version 2.0: Appendix B—Differences Between
2
TheLTC3880implementsatimeoutfeaturetoavoidhanging
theserialinterface.Thedatapackettimerbeginsatthefirst
START event before the device address write byte. Data
packet information must be completed within 25ms or
the LTC3880 will three-state the bus and ignore the given
data packet. Data packet information includes the device
address byte write, command byte, repeat start event
(if a read operation), device address byte read (if a read
operation), all data bytes and the PEC byte if applicable.
SMBus and I C.
PMBUS SERIAL DIGITAL INTERFACE
TheLTC3880communicateswithahost(master)usingthe
standardPMBusserialbusinterface.TheTimingDiagram,
Figure 5, shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines.
TheLTC3880allowslongerPMBustimeoutsforblockread
data packets. This timeout is proportional to the length
of the block read. The additional block read timeout ap-
plies primarily to the MFR_FAULT_LOG command. In no
circumstances will the timeout period be less than the
TheLTC3880isaslavedevice.Themastercancommunicate
with the LTC3880 using the following formats:
n
Master transmitter, slave receiver
n
Master receiver, slave transmitter
t
specification of 32ms (typical).
TIMEOUT_SMB
The following PMBus protocols are supported:
The user is encouraged to use as high a clock rate as
possibletomaintainefficientdatapackettransferbetween
all devices sharing the serial bus interface. The LTC3880
supports the full PMBus frequency range from 10kHz to
400kHz.
n
Write Byte, Write Word, Send Byte
n
Read Byte, Read Word, Block Read
n
Alert Response Address
Figures 7-16 illustrate the aforementioned PMBus proto-
cols. All transactions supportPEC(parity error check)and
GCP(groupcommandprotocol).TheBlockReadsupports
255 bytes of returned data. For this reason, the PMBus
timeout may be extended when reading the fault log.
2
SIMILARITY BETWEEN PMBUS, SMBUS AND I C
2-WIRE INTERFACE
The PMBus 2-wire interface is an incremental extension
2
of the SMBus. SMBus is built upon I C with some minor
differences in timing, DC parameters and protocol. The
Figure 6 is a key to the protocol diagrams in this section.
PEC is optional.
2
PMBus/SMBusprotocolsaremorerobustthansimpleI C
3880fc
28
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
operaTion
SDA
t
r
t
SU(DAT)
t
t
SP
t
HD(SDA)
r
t
t
t
t
f
BUF
f
LOW
SCL
t
t
t
SU(STO)
HD(STA)
SU(STA)
t
t
HIGH
HD(DAT)
3880 F05
START
CONDITION
REPEATED START
CONDITION
STOP
START
CONDITION CONDITION
Figure 5ꢀ Timing Diagram
1
7
1
1
A
x
8
1
A
x
1
A value shown below a field in the following figures is a
mandatory value for that field.
S
SLAVE ADDRESS Wr
DATA BYTE
P
S
START CONDITION
The data formats implemented by PMBus are:
Sr
REPEATED START CONDITION
n
Rd READ (BIT VALUE OF 1)
Wr WRITE (BIT VALUE OF 0)
Master transmitter transmits to slave receiver. The
transfer direction in this case is not changed.
x
SHOWN UNDER A FIELD INDICATES THAT THAT
FIELD IS REQUIRED TO HAVE THE VALUE OF x
n
Master reads slave immediately after the first byte. At
A
ACKNOWLEDGE (THIS BIT POSITION MAY BE 0
FOR AN ACK OR 1 FOR A NACK)
the moment of the first acknowledgment (provided by
the slave receiver) the master transmitter becomes a
master receiver and the slave receiver becomes a slave
transmitter.
P
STOP CONDITION
PEC PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
...
CONTINUATION OF PROTOCOL
3880 F06
n
Combined format. During a change of direction within
a transfer, the master repeats both a start condition and
the slave address but with the R/W bit reversed. In this
case, the master receiver terminates the transfer by
generating a NACK on the last byte of the transfer and
a STOP condition.
Figure 6ꢀ PMBus Packet Protocol Diagram Element Key
Examples of these formats are shown in Figures 7-16.
3880fc
29
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
operaTion
Table 1ꢀ Data Format Terminology
PMBus
FOR MORE DETAIL REFER TO
THE DATA FORMAT SECTION
OF TABLE 2
TERMINOLOGY FOR: SPECS,
GUI, APPLICATION NOTES
ABBREVIATIONS FOR
SUMMARY COMMAND TABLE
TERMINOLOGY
MEANING
Linear
Linear
Linear_5s_11s
Linear_16u
L11
L16
Page 35
Page 35
Linear (for Voltage
Related Commands)
Linear
Direct
Direct-Manufacturer
Customized
DirectMfr
CF
Page 35
Hex
Hex
ASCII
Reg
I16
ASC
Reg
ASCII
Register Fields
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE
A
P
3880 F07
Figure 7ꢀ Write Byte Protocol
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
3880 F08
Figure 8ꢀ Write Word Protocol
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE
A
PEC
A
P
3880 F09
Figure 9ꢀ Write Byte Protocol with PEC
1
7
1
1
8
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
3880 F10
Figure 10ꢀ Write Word Protocol with PEC
3880fc
30
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
operaTion
1
7
1
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
P
3880 F11
Figure 11ꢀ Send Byte Protocol
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
PEC
A
P
3880 F12
Figure 12ꢀ Send Byte Protocol with PEC
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
3880 F13
Figure 13ꢀ Read Word Protocol
1
7
1
1
8
1
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
3880 F14
Figure 14ꢀ Read Word Protocol with PEC
1
7
1
1
8
1
1
7
1
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE
A
P
3880 F15
Figure 15ꢀ Read Byte Protocol
1
7
1
1
8
1
1
7
1
1
8
1
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE
A
PEC
A
P
3880 F16
Figure 16ꢀ Read Byte Protocol with PEC
Refer to Figure 6 for a legend.
Handshaking features are included to ensure robust
system communication. Please refer to the PMBus Com-
munication and Command Processing subsection of the
Applications Information section for further details.
3880fc
31
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD summary
PMBUS COMMANDS
implicitlynotsupportedbythemanufacturer.Attemptingto
access non-supported or reserved commands may result
in a CML command fault event. All output voltage settings
ThefollowingtableslistsupportedPMBuscommandsand
manufacturerspecificcommands.Acompletedescription
of these commands can be found in the “PMBus Power
System Mgt Protocol Specification – Part II – Revision
1.1”. Usersareencouragedtoreferencethisspecification.
Exceptions or manufacturer specific implementations
are listed below in Table 2. Floating point values listed
in the “DEFAULT VALUE” column are either Linear 16-bit
Signed (PMBus Section 8.3.1) or Linear_5s_11s (PMBus
Section 7.1)format,whicheverisappropriateforthecom-
mand. All commands from 0xD0 through 0xFF not listed
in this table are implicitly reserved by the manufacturer.
Users should avoid blind writes within this range of com-
mands to avoid undesired operation of the part. All com-
mands from 0x00 through 0xCF not listed in this table are
and measurements are based on the VOUT_MODE setting
–12
of 0x14. This translates to an exponent of 2
.
If PMBus commands are received faster than they are be-
ing processed, the part may become too busy to handle
new commands. In these circumstances the part follows
the protocols defined in the PMBus Specification v1.1,
Part II, Section 10.8.7, to communicate that it is busy.
The part includes handshaking features to eliminate busy
errors and simplify error handling software while ensur-
ing robust communication and system behavior. Please
refer to the subsection titled PMBus Communication and
Command Processing in the Applications Information
section for further details.
Table 2ꢀ Summary (Note: The Data Format abbreviations are detailed at the end of this tableꢀ)
CMD
DATA
DEFAULT
VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
PAGE
0x00 Channel or page currently selected for any
command that supports paging.
R/W Byte
N
Y
Y
Reg
Reg
Reg
0x00
0x80
0x1E
63
67
66
OPERATION
0x01 Operating mode control. On/off, margin high and R/W Byte
margin low.
Y
Y
ON_OFF_CONFIG
0x02 RUN pin and PMBus bus on/off command
configuration.
R/W Byte
CLEAR_FAULTS
0x03 Clear any fault bits that have been set.
Send Byte
R/W Byte
N
N
NA
91
63
WRITE_PROTECT
0x10 Level of protection provided by the device
against accidental changes.
Reg
Y
0x00
STORE_USER_ALL
RESTORE_USER_ALL
CAPABILITY
0x15 Store user operating memory to EEPROM.
Send Byte
N
N
N
NA
NA
101
101
90
0x16 Restore user operating memory from EEPROM. Send Byte
0x19 Summary of PMBus optional communication
protocols supported by this device.
R Byte
Reg
Reg
L16
L16
0xB0
–12
–12
VOUT_MODE
VOUT_COMMAND
VOUT_MAX
0x20 Output voltage format and exponent (2 ).
R Byte
Y
Y
Y
2
71
72
0x14
0x21 Nominal output voltage set point.
R/W Word
R/W Word
V
V
Y
Y
1.0
0x1000
0x24 Upper limit on the commanded output voltage
including VOUT_MARGIN_HIGH.
4.096 ch0 71
0x4189
5.5 ch1
0x5800
VOUT_MARGIN_HIGH
VOUT_MARGIN_LOW
0x25 Margin high output voltage set point. Must be
greater than VOUT_COMMAND.
R/W Word
R/W Word
R/W Word
Y
Y
Y
L16
L16
L11
V
V
Y
Y
Y
1.05
72
72
78
0x10CD
0x26 Margin low output voltage set point. Must be
less than VOUT_COMMAND.
0.95
0x0F33
VOUT_TRANSITION_RATE 0X27 Rate the output changes when VOUT
commanded to a new value.
V/ms
0.25
AA00
3880fc
32
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD summary
CMD
DATA
DEFAULT
VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
FREQUENCY_SWITCH
0x33 Switching frequency of the controller.
R/W Word
N
N
N
Y
L11
L11
L11
L11
kHz
Y
Y
Y
Y
350
69
70
70
74
0xFABC
VIN_ON
0x35 Input voltage at which the unit should start
power conversion.
R/W Word
R/W Word
V
6.5
0xCB40
VIN_OFF
0x36 Input voltage at which the unit should stop
power conversion.
V
6.0
0xCB00
IOUT_CAL_GAIN
0x38 The ratio of the voltage at the current sense pins R/W Word
to the sensed current. For devices using a fixed
current sense resistor, it is the resistance value
in mΩ.
mΩ
1.8
0xBB9A
VOUT_OV_FAULT_LIMIT
0x40 Output overvoltage fault limit.
R/W Word
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
N
N
Y
L16
Reg
L16
L16
L16
Reg
L11
Reg
L11
L11
Reg
L11
L11
Reg
L11
Reg
L11
L11
L16
V
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
1.1
71
81
72
73
73
82
75
84
76
77
86
77
77
86
70
80
70
75
73
0x119A
VOUT_OV_FAULT_
RESPONSE
0x41 Action to be taken by the device when an output R/W Byte
overvoltage fault is detected.
0xB8
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
VOUT_UV_FAULT_LIMIT
0x42 Output overvoltage warning limit.
0x43 Output undervoltage warning limit.
0x44 Output undervoltage fault limit.
R/W Word
R/W Word
R/W Word
V
V
V
1.075
0x1133
0.925
0x0ECD
0.9
0x0E66
VOUT_UV_FAULT_
RESPONSE
0x45 Action to be taken by the device when an output R/W Byte
undervoltage fault is detected.
0xB8
IOUT_OC_FAULT_LIMIT
0x46 Output overcurrent fault limit.
R/W Word
A
29.75
0xDBB8
IOUT_OC_FAULT_
RESPONSE
0x47 Action to be taken by the device when an output R/W Byte
overcurrent fault is detected.
0x00
IOUT_OC_WARN_LIMIT
0x4A Output overcurrent warning limit.
R/W Word
A
C
20.0
0xDA80
OT_FAULT_LIMIT
0x4F External overtemperature fault limit.
R/W Word
100.0
0xEB20
OT_FAULT_RESPONSE
OT_WARN_LIMIT
0x50 Action to be taken by the device when an external R/W Byte
overtemperature fault is detected,
0xB8
0x51 External overtemperature warning limit.
R/W Word
C
C
85.0
0xEAA8
UT_FAULT_LIMIT
0x53 External undertemperature fault limit.
R/W Word
–40.0
0xE580
UT_FAULT_RESPONSE
VIN_OV_FAULT_LIMIT
0x54 Action to be taken by the device when an external R/W Byte
undertemperature fault is detected.
0xB8
0x55 Input supply overvoltage fault limit.
R/W Word
R/W Byte
R/W Word
R/W Word
R/W Word
V
15.5
0xD3E0
VIN_OV_FAULT_
RESPONSE
0x56 Action to be taken by the device when an input
overvoltage fault is detected.
0x80
VIN_UV_WARN_LIMIT
IIN_OC_WARN_LIMIT
POWER_GOOD_ON
0x58 Input supply undervoltage warning limit.
V
A
V
6.3
0xCB26
0x5D Input supply overcurrent warning limit.
10.0
0xD280
0x5E Output voltage at or above which a power good
should be asserted.
0.93
0x0EE1
3880fc
33
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD summary
CMD
DATA
DEFAULT
VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
POWER_GOOD_OFF
0x5F Output voltage at or below which a power good
should be de-asserted.
R/W Word
Y
Y
Y
L16
L11
L11
V
Y
Y
Y
0.92
73
78
78
0x0EB8
TON_DELAY
TON_RISE
0x60 Time from RUN and/or Operation on to output
rail turn-on.
R/W Word
ms
ms
0.0
0x8000
0x61 Time from when the output starts to rise until the R/W Word
output voltage reaches the VOUT commanded
value.
8.0
0xD200
TON_MAX_FAULT_LIMIT
0x62 Maximum time from V
on for VOUT to
R/W Word
Y
Y
Y
Y
Y
L11
Reg
L11
L11
L11
ms
Y
Y
Y
Y
Y
10.00
78
83
79
79
79
OUT_EN
cross the VOUT_UV_FAULT_LIMIT.
0xD280
TON_MAX_FAULT_
RESPONSE
0x63 Action to be taken by the device when a
TON_MAX_FAULT event is detected.
R/W Byte
0xB8
TOFF_DELAY
0x64 Time from RUN and/or Operation off to the start R/W Word
of TOFF_FALL ramp.
ms
ms
ms
0.0
0x8000
TOFF_FALL
0x65 Time from when the output starts to fall until the R/W Word
output reaches zero volts.
8.00
0xD200
TOFF_MAX_WARN_LIMIT 0x66 Maximum allowed time, after TOFF_FALL
completed, for the unit to decay below 12.5%.
R/W Word
150
0xF258
STATUS_BYTE
0x78 One byte summary of the unit’s fault condition.
0x79 Two byte summary of the unit’s fault condition.
0x7A Output voltage fault and warning status.
0x7B Output current fault and warning status.
0x7C Input supply fault and warning status.
R/W Byte
R/W Word
R/W Byte
R/W Byte
R/W Byte
Y
Y
Y
Y
N
Y
Reg
Reg
Reg
Reg
Reg
Reg
NA
NA
NA
NA
NA
NA
92
92
93
93
94
94
STATUS_WORD
STATUS_VOUT
STATUS_IOUT
STATUS_INPUT
STATUS_TEMPERATURE
0x7D External temperature fault and warning status for R/W Byte
READ_TEMERATURE_1.
STATUS_CML
0x7E Communication and memory fault and warning
status.
R/W Byte
N
Reg
NA
95
STATUS_MFR_SPECIFIC
READ_VIN
0x80 Manufacturer specific fault and state information. R/W Byte
Y
N
N
Y
Y
Y
Reg
L11
L11
L16
L11
L11
NA
NA
NA
NA
NA
NA
95
98
98
98
99
99
0x88 Measured input supply voltage.
0x89 Measured input supply current.
0x8B Measured output voltage.
0x8C Measured output current.
R Word
R Word
R Word
R Word
R Word
V
A
V
A
C
READ_IIN
READ_VOUT
READ_IOUT
READ_TEMPERATURE_1
0x8D External diode junction temperature. This is the
value used for all temperature related processing,
including IOUT_CAL_GAIN.
READ_TEMPERATURE_2
0x8E Internal junction temperature. Does not affect
any other registers.
R Word
N
L11
C
NA
99
READ_DUTY_CYCLE
READ_POUT
0x94 Duty cycle of the top gate control signal.
0x96 Measured output power.
R Word
R Word
R Byte
Y
Y
N
L11
L11
Reg
%
W
NA
NA
99
99
90
PMBUS_REVISION
0x98 PMBus revision supported by this device.
Current revision is 1.1.
0x11
MFR_ID
0x99 The manufacturer ID of the LTC3880 in ASCII.
0x9A Manufacturer part number in ASCII.
0x9E Serial number of this specific unit.
0xA5 Maximum allowed output voltage.
R String
R String
R Block
R Word
N
N
N
Y
ASC
ASC
CF
LTC
LTC3880
NA
90
90
90
MFR_MODEL
MFR_SERIAL
MFR_VOUT_MAX
L16
V
4.096 CH0 73
5.5 CH1
USER_DATA_00
0xB0 OEM RESERVED. Typically used for part
serialization.
R/W Word
N
Reg
Y
NA
89
3880fc
34
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD summary
CMD
DATA
DEFAULT
COMMAND NAME
USER_DATA_01
USER_DATA_02
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
VALUE PAGE
0xB1 Manufacturer reserved for LTpowerPlay.
R/W Word
R/W Word
Y
N
Reg
Reg
Y
Y
NA
NA
89
89
0xB2 OEM RESERVED. Typically used for part
serialization
USER_DATA_03
USER_DATA_04
MFR_EE_UNLOCK
0xB3 A NVM word available for the user.
0xB4 A NVM word available for the user.
R/W Word
R/W Word
R/W Byte
Y
N
N
Reg
Reg
Reg
Y
Y
0x0000
0x0000
NA
89
89
0xBD Unlock user EEPROM for access by MFR_EE_
ERASE and MFR_EE_DATA commands.
108
MFR_EE_ERASE
MFR_EE_DATA
0xBE Initialize user EEPROM for bulk programming by R/W Byte
MFR_EE_DATA.
N
N
Reg
Reg
NA
NA
108
108
0xBF Data transferred to and from EEPROM using
sequential PMBus word reads or writes.
Supports bulk programming.
R/W Word
MFR_CHAN_CONFIG_
LTC3880
0xD0 Configuration bits that are channel specific.
R/W Byte
Y
N
Y
Y
Y
N
Y
Y
Y
Y
Y
N
Y
Reg
Reg
Reg
Reg
Reg
Reg
L11
Reg
L11
L11
L16
L11
L11
Y
Y
Y
Y
Y
0x1F
0x09
0x2993
0xC2
0xC0
0xC0
NA
65
65
MFR_CONFIG_ALL_
LTC3880
0xD1 Configuration bits that are common to all pages. R/W Byte
MFR_GPIO_PROPAGATE_ 0xD2 Configuration that determines which faults are
LTC3880
R/W Word
R/W Byte
R/W Byte
R Byte
87
propagated to the GPIO pins.
MFR_PWM_MODE_
LTC3880
0xD4 Configuration for the PWM engine of each
channel.
68
MFR_GPIO_RESPONSE
0xD5 Action to be taken by the device when the GPIO
89
pin is externally asserted low.
MFR_OT_FAULT_
RESPONSE
0xD6 Action to be taken by the device when an internal
overtemperature fault is detected.
85
MFR_IOUT_PEAK
0xD7 Report the maximum measured value of
READ_IOUT since last MFR_CLEAR_PEAKS.
R Word
A
100
64
MFR_CHANNEL_
ADDRESS
0xD8 Address to the PAGE activated channel.
R/W Byte
R/W Word
R/W Word
R Word
Y
Y
Y
0x80
MFR_RETRY_DELAY
MFR_RESTART_DELAY
MFR_VOUT_PEAK
MFR_VIN_PEAK
0xDB Retry interval during FAULT retry mode.
ms
ms
V
350
0xFABC
80
0xDC Minimum time the RUN pin is held low by the
LTC3880.
500
0xFBE8
80
0xDD Maximum measured value of READ_VOUT since
last MFR_CLEAR_PEAKS.
NA
NA
NA
100
100
100
0xDE Maximum measured value of READ_VIN since
last MFR_CLEAR_PEAKS.
R Word
V
MFR_TEMPERATURE_1_ 0xDF Maximum measured value of external
PEAK
R Word
C
Temperature (READ_TEMPERATURE_1)
since last MFR_CLEAR_PEAKS.
MFR_CLEAR_PEAKS
MFR_PADS
0xE3 Clears all peak values.
Send Byte
R Word
N
N
N
N
Y
NA
NA
91
97
64
90
74
0xE5 Digital status of the I/O pads.
Reg
Reg
Reg
L11
2
MFR_ADDRESS
MFR_SPECIAL_ID
MFR_IIN_OFFSET
0xE6 Sets the 7-bit I C address byte.
R/W Byte
R Word
Y
Y
0x4F
0x40X
0xE7 Manufacturer code representing the LTC3880
0xE9 Coefficient used to add to the input current to
account for the IQ of the part.
R/W Word
A
0.050
0X9333
MFR_FAULT_LOG_STORE 0xEA Command a transfer of the fault log from RAM to Send Byte
EEPROM. This causes the part to behave as if a
N
NA
102
channel has faulted off.
3880fc
35
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD summary
CMD
DATA
DEFAULT
VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
MFR_FAULT_LOG_CLEAR 0xEC Initialize the EEPROM block reserved for fault
Send Byte
N
NA
107
logging and clear any previous fault logging
locks.
MFR_READ_IIN
0xED Measured input current per channel
R Word
R Block
Y
N
L11
Reg
A
NA
NA
99
MFR_FAULT_LOG
0xEE Fault log data bytes. This sequentially retrieved
data is used to assemble a complete fault log.
Y
102
MFR_COMMON
0xEF Manufacturer status bits that are common across R Byte
multiple LTC chips.
N
N
N
N
Y
Y
Y
Y
N
Reg
NA
NA
97
101
100
68
MFR_COMPARE_USER_
ALL
0xF0 Compares current command contents with NVM. Send Byte
MFR_TEMPERATURE_2_
PEAK
0xF4 Peak internal die temperature since last MFR_
CLEAR_PEAKS.
R Word
R/W Byte
R/W Word
L11
Reg
CF
C
NA
MFR_PWM_CONFIG_
LTC3880
0xF5 Set numerous parameters for the DC/DC
controller including phasing.
Y
Y
Y
Y
Y
0x10
MFR_IOUT_CAL_GAIN_TC 0xF6 Temperature coefficient of the current sensing
element.
3900
0x0F3C
74
MFR_TEMP_1_GAIN
MFR_TEMP_1_OFFSET
MFR_RAIL_ADDRESS
MFR_RESET
0xF8 Sets the slope of the external temperature sensor. R/W Word
CF
1.0
0x4000
76
0xF9 Sets the offset of the external temperature
sensor with respect to –273.1°C
R/W Word
R/W Byte
Send Byte
L11
Reg
C
0.0
0x8000
76
0xFA Common address for PolyPhase outputs to
adjust common parameters.
0x80
64
0xFD Commanded reset without requiring a power
down.
NA
67
Note 1: Commands indicated with Y indicate that these commands are
stored and restored using the STORE_USER_ALL and RESTORE_USER_
ALL commands, respectively.
Note 4: Some of the unpublished commands are read-only and will
generate a CML bit 6 fault if written.
Note 5: Writing to commands not published in this table is not permitted.
Note 2: Commands with a default value of NA indicate “not applicable”.
Commands with a default value of FS indicate “factory set on a per part
basis”.
Note 3: The LTC3880 contains additional commands not listed in this
table. Reading these commands is harmless to the operation of the IC;
however, the contents and meaning of these commands can change
without notice.
Note 6: The user should not assume compatibility of commands
between different parts based upon command names. Always refer to
the manufacturer’s data sheet for each part for a complete definition of a
command’s function.
LTC has made every reasonable attempt to keep command functionality
compatible between parts; however, differences may occur to address
product requirements.
3880fc
36
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD summary
*DATA FORMAT
L11 Linear_5s_11s
PMBus data field b[15:0]
N
Value = Y • 2
where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit
two’s complement integer
Example:
For b[15:0] = 0x9807 = ‘b10011_000_0000_0111
–13
–6
Value = 7 • 2 = 854 • 10
From “PMBus Spec Part II: Paragraph 7.1”
L16 Linear_16u
PMBus data field b[15:0]
N
Value = Y • 2
where Y = b[15:0] is an unsigned integer and N = Vout_mode_parameter is a 5-bit two’s
complement exponent that is hardwired to –12 decimal
Example:
For b[15:0] = 0x4C00 = ‘b0100_1100_0000_0000
–12
Value = 19456 • 2 = 4.75
From “PMBus Spec Part II: Paragraph 8.2”
Reg Register
PMBus data field b[15:0] or b[7:0].
Bit field meaning is defined in detailed PMBus Command Register Description.
I16 Integer Word
PMBus data field b[15:0]
Value = Y
where Y = b[15:0] is a 16 bit unsigned integer
Example:
For b[15:0] = 0x9807 = ‘b1001_1000_0000_0111
Value = 38919 (decimal)
CF Custom Format
ASC ASCII Format
Value is defined in detailed PMBus Command Register Description.
This is often an unsigned or two’s complement integer scaled by an MFR specific
constant.
A variable length string of text characters conforming to ISO/IEC 8859-1 standard.
3880fc
37
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
TheTypicalApplicationonthebackpageisabasicLTC3880
application circuit. The LTC3880 can be configured to use
either DCR (inductor resistance) sensing or low value
resistor sensing. The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. The LTC3880 can nominally
account for the temperature dependency of the DCR sens-
ing element. The accuracy of the current reading and cur-
rent limit are typically limited by the accuracy of the DCR
resistor (accounted for in the IOUT_CAL_GAIN parameter
of the LTC3880). Thus current sensing resistors provide
the most accurate current sense and limiting for the ap-
plication. Other external component selection is driven
by the load requirement, and begins with the selection of
inductors or sense resistors, but at the expense of cur-
rent limit accuracy. Keep in mind this operation is on a
cycle-by-cycle basis and is only a function of the peak in-
ductor current. The average inductor current is monitored
by the ADC converter and can provide a warning if too
much average output current is detected. The overcurrent
fault is detected when the ITH voltage hits the maximum
value. The digital processor within the LTC3880 provides
theabilitytoeitherignorethefault, shutdownandlatchoff
or shut down and retry indefinitely (hiccup). Refer to the
overcurrentportionoftheOperationsectionformoredetail.
+
–
I
AND I
PINS
SENSE
SENSE
+
–
The I
and I
pins are the inputs to the current
SENSE
SENSE
comparatorsandtheA/D.Thecommonmodeinputvoltage
range of the current comparators is 0V to 5.5V. Both the
SENSE pins are high impedance inputs with small base
R
SENSE
(if R
is used) and inductor value. Next, the
SENSE
currents typically less than 1µA. When the I
pins
SENSE
power MOSFETs are selected. Then the input and output
capacitorsareselected.Finallythecurrentlimitisselected.
All of these components and ranges are required to be
determinedpriortocalculatingtheexternalcompensation
components. The current limit range is required because
the two ranges (25mV to 50mV vs 37.5mV to 70mV) have
different EA gains set with bit 7 of the MFR_PWM_MODE_
LTC3880 command. The voltage RANGE bit also modifies
the loop gain and impacts the compensation network set
with bits 5, 6 of MFR_PWM_CONFIG_LTC3880. All other
programmable parameters do not affect the loop gain,
allowing parameters to be modified without impact to the
transient response to load.
ramp up from 0V to 1.4V, the small base currents flow
out of the SENSE pins. When the I pins are greater
SENSE
than 1.4V, the base currents flow into the I
pins. The
SENSE
high impedance inputs to the current comparators allow
accurate DCR sensing. Do not to float these pins during
normal operation.
Filter components mutual to the I
lines should be
SENSE
placed close to the IC. The positive and negative traces
should be routed differentially and Kelvin connected to
the current sense element, see Figure 17. A non-Kelvin
connection elsewhere can add parasitic inductance and
capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. In a PolyPhase
system,poorplacementofthesensingelementwillresultin
sub-optimalcurrentsharingbetweenpowerstages.IfDCR
sensing is used (Figure 18a), sense resistor R1 should be
placed close to the switching node to prevent noise from
CURRENT LIMIT PROGRAMMING
TheLTC3880hastworangesofcurrentlimitprogramming
and a total of eight levels within each range. Refer to the
IOUT_OC_FAULT_LIMITsectionofthePMBuscommands.
Within each range the error amp gain is fixed, resulting in
constant loop gain. The LTC3880 will account for the DCR
oftheinductorandautomaticallyupdatethecurrentlimitas
the inductor temperature changes. The temperature coef-
ficient of the DCR is stored in the MFR_IOUT_TC register.
TO SENSE FILTER,
NEXT TO THE CONTROLLER
C
OUT
INDUCTOR OR R
3880 F17
SENSE
For the best current limit accuracy, use the 75mV setting.
The 25mV setting will allow for the use of very low DCR
Figure 17ꢀ Optimal Sense Line Placement
3880fc
38
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
coupling into sensitive small-signal nodes. The capacitor
C1 should be placed close to the IC pins. This impedance
difference can result in loss of accuracy in the current
reading of the ADC. The current reading accuracy can be
improved by matching the impedance of the two pins. To
The current comparator has a maximum threshold
V
determined by the I
setting. The input
SENSE(MAX)
LIMIT
common mode range of the current comparator is 0V to
5.5V (if V is greater than 6V). The current comparator
IN
threshold sets the peak of the inductor current, yielding
accomplish this add a series resistor between V
SENSE
be placed in parallel with this resistor. If the peak voltage
is <75mV at room temperature, R2 is not required.
and
a maximum average output current I
equal to the
OUT
MAX
–
I
equal to R1. A capacitor of 1µF or greater should
peak value less half the peak-to-peak ripple current ∆I .
L
To calculate the sense resistor value, use the equation:
VSENSE(MAX)
RSENSE
=
∆IL
IMAX
+
LOW VALUE RESISTOR CURRENT SENSING
2
A typical sensing circuit using a discrete resistor is shown
Due to possible PCB noise in the current sensing loop, the
also
in Figure 18b. R
output current.
is chosen based on the required
SENSE
AC current sensing ripple of ∆V
= ∆I • R
L SENSE
SENSE
needs to be checked in the design to get a good signal-to-
noise ratio. In general, for a reasonably good PCB layout,
V
IN
V
IN
INTV
CC
a 15mV minimum ∆V
voltage is recommended as
SENSE
a conservative number to start with, either for R
DCR sensing applications.
or
BOOST
TG
SENSE
INDUCTOR
L
DCR
SW
V
OUT
For previous generation current mode controllers, the
maximum sense voltage was high enough (e.g., 75mV for
theLTC1628/LTC3728family)thatthevoltagedropacross
the parasitic inductance of the sense resistor represented
a relatively small error. In the new highest current density
solutions; however, the value of the sense resistor can be
lessthan1mΩandthepeaksensevoltagecanbelessthan
20mV.Inaddition,inductorripplecurrentsgreaterthan50%
with operation up to 1MHz are becoming more common.
Under these conditions, the voltage drop across the sense
resistor’s parasitic inductance is no longer negligible. A
typical sensing circuit using a discrete resistor is shown in
Figure 18b. In previous generations of controllers, a small
RC filter placed near the IC was commonly used to reduce
the effects of the capacitive and inductive noise coupled
in the sense traces on the PCB. A typical filter consists of
two series 100Ω resistors connected to a parallel 1000pF
capacitor, resulting in a time constant of 200ns.
LTC3880
BG
PGND
C2 >1µF
R1
+
I
I
SENSE
C1* R2
R3
–
SENSE
SGND
OPTIONAL
3880 F18a
R2
2 • L
DCR
[(R1 + R3)||R2] • C1 =
IOUT_CAL_GAIN = DCR •
R3 = R1
R1 + R2 + R3
+
–
*PLACE C1 NEAR SENSE , SENSE PINS
Figure 18aꢀ Inductor DCR Current Sense Circuit
V
IN
V
IN
INTV
CC
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
BOOST
TG
R
ESL
SW
S
V
OUT
LTC3880
BG
C • 2R ≤ ESL/R
F
F
S
POLE-ZERO
PGND
CANCELLATION
R
R
F
F
This same RC filter with minor modifications, can be
used to extract the resistive component of the current
sense signal in the presence of parasitic inductance. For
example,Figure19illustratesthevoltagewaveformacross
a 2mΩ resistor with a 2010 footprint. The waveform is
the superposition of a purely resistive component and a
3880fc
+
I
I
SENSE
C
F
–
SENSE
SGND
FILTER COMPONENTS
PLACED NEAR SENSE PINS
3880 F018b
Figure 18bꢀ Resistor Current Sense Circuit
39
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
purely inductive component. It was measured using two
scope probes and waveform math to obtain a differential
measurement. Based on additional measurements of the
inductor ripple current and the on-time and off-time of
the top switch, the value of the parasitic inductance was
determined to be 0.5nH using the equation:
INDUCTOR DCR CURRENT SENSING
For applications requiring the highest possible efficiency
at high load currents, the LTC3880 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 18a. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such an
inductor, conduction loss through a sense resistor would
cost a few points of efficiency compared to DCR sensing.
VESL(STEP)
tON • tOFF
tON + tOFF
ESL =
•
(1)
∆IL
If the RC time constant is chosen to be close to the para-
sitic inductance divided by the sense resistor (L/R), the
resultantwaveformlooksresistive, asshowninFigure 20.
For applications using low maximum sense voltages,
check the sense resistor manufacturer’s data sheet for
information about parasitic inductance. In the absence
of data, measure the voltage drop directly across the
sense resistor to extract the magnitude of the ESL step
and use Equation 1 to determine the ESL. However, do
not overfilter the signal. Keep the RC time constant less
than or equal to the inductor time constant to maintain a
Iftheexternal(R1+R3)||R2•C1timeconstantischosento
be exactly equal to the 2 • L/DCR time constant, assuming
R1=R3, the voltage drop across the external capacitor is
equal to the drop across the inductor DCR multiplied by
R2/(R1+R2+R3). R2 scales the voltage across the sense
terminals for applications where the DCR is greater than
the target sense resistor value. The DCR value is entered
as the IOUT_CAL_GAIN in mΩ unless R2 is required. If R2
isused,IOUT_CAL_GAIN=DCR•R2/(R1+R2+R3).Ifthere
is no need to attenuate the signal, R2 can be removed. To
properlydimensiontheexternalfiltercomponents,theDCR
of the inductor must be known. It can be measured using
a good RLC meter, but the DCR tolerance is not always the
sameandvarieswithtemperature.Consultthemanufactur-
ers’ data sheets for detailed information. The LTC3880 will
account for temperature variation if the correct parameter
is entered into the MFR_IOUT_CAL_GAIN_TC register.
Typically the resistance has a 3900ppm/°C coefficient.
sufficient ripple voltage on V
for optimal operation
RSENSE
of the current loop controller.
V
SENSE
20mV/DIV
V
ESL(STEP)
C2 can be optimized for a flat frequency response, assum-
ing R1 = R3 by the following equation
3880 F19
500ns/DIV
2
C2 = [2R1 • R2 • C1–L/DCR • (2R1+R2)]/R1
Figure 19ꢀ Voltage Measured Directly Across RSENSE
Using the inductor ripple current value from the inductor
Value Calculation section, the target sense resistor value
is:
VSENSE(MAX)
RSENSE(EQUIV)
=
∆IL
V
SENSE
IMAX
+
20mV/DIV
2
To ensure that the application will deliver full load current
over the full operating temperature range, be sure to pick
3880 F20
the optimum I
value accounting for errors in the DCR
500ns/DIV
LIMIT
versus the MFR_IOUT_CAL_GAIN parameter entered.
Figure 20ꢀ Voltage Measured After the RSENSE Filter
3880fc
40
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given
at 20°C. Increase this value to account for errors in the
temperature sensing element of 3°C to 5°C and any
additional errors associated with the proximity of the
temperature sensor element to the inductor.
mode will improve the converter efficiency at light loads
regardless of the current sensing method.
To maintain a good signal-to-noise ratio for the current
sense signal, use a minimum ∆V
of 10mV to 15mV.
For a DCR sensing application, the actual ripple voltage
will be determined by the equation:
SENSE
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
V – VOUT
R1•C1
VOUT
IN
∆VSENSE
=
•
V • fOSC
IN
RSENSE(EQUIV)
RD=
DCR(MAXERROR) at TL(MAX)
SLOPE COMPENSATION AND INDUCTOR PEAK
CURRENT
C1 is usually selected to be in the range of 0.047µF to
4.7µF. This forces R1||R2 to be approximately 2k. This
resistance minimizes errors caused by the SENSE pin
leakage currents. Adding optional elements R3 and C2
shown in Figure 18a will minimize offset errors associated
with these leakage currents.
Slope compensation provides stability in constant
frequency current mode architectures by preventing
sub-harmonic oscillations at high duty cycles. This is
accomplished internally by adding a compensation ramp
to the inductor current signal at duty cycles in excess of
35%. TheLTC3880usesapatentedcurrentlimittechnique
that counteracts the compensating ramp. This allows the
maximum inductor peak current to remain unaffected
throughout all duty cycles.
The equivalent resistance (R1+R3)||R2 is scaled to the
room temperature inductance and maximum DCR:
2•L
(R1+R3)||R2=
DCR at 20°C •C1
(
)
INDUCTOR VALUE CALCULATION
The sense resistor values are:
Given the desired input and output voltages, the inductor
R1||R2
RD
R1•RD
1–RD
value and operating frequency, f , directly determine
OSC
R1=R3; R1=
; R2=
the inductor peak-to-peak ripple current:
The maximum power loss in R1 is related to the duty
cycle, and will occur in continuous mode at the maximum
input voltage:
VOUT V – V
(
)
IN
OUT
IRIPPLE
=
V • fOSC •L
IN
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highestefficiencyoperationisobtainedatthe
lowest frequency with a small ripple current. Achieving
this, however, requires a large inductor.
V
IN(MAX) – VOUT • V
(
)
OUT
PLOSSR1=
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor
due to the extra switching losses incurred through R1.
However, DCR sensing eliminates a sense resistor, reduc-
ing conduction losses and provides higher efficiency at
heavy loads. Peak efficiency is about the same with either
method.SelectingBurstModeoperationordiscontinuous
A reasonable starting point is to choose a ripple current
that is about 40% of I
. Note that the largest ripple
OUT(MAX)
current occurs at the highest input voltage. To guarantee
that the ripple current does not exceed a specified maxi-
mum, the inductor should be chosen according to:
VOUT V – V
(
)
IN
OUT
L ≥
V • fOSC •IRIPPLE
IN
3880fc
41
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
INDUCTOR CORE SELECTION
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Once the inductor value is determined, the type of induc-
tor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance. As the inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses increase.
VOUT
Main Switch Duty Cycle=
V
IN
V – VOUT
IN
Synchronous Switch Duty Cycle=
V
IN
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core materials saturate hard, which means that the induc-
tance collapse abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
The MOSFET power dissipations at maximum output
current are given by:
VOUT
2
PMAIN
=
I
1+δ R
+
)
(
)
(
)
MAX
DS(ON)
V
IN
I
2 MAX
V
R
DR )(
C
•
(
)
(
IN
MILLER
2
1
1
+
• f
OSC
V
INTVCC – VTH(MIN) VTH(MIN)
POWER MOSFET AND SCHOTTKY DIODE (OPTIONAL)
SELECTION
Two external power MOSFETs must be selected for each
controller in the LTC3880: one N-channel MOSFET for the
top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
V – VOUT
2
IN
PSYNC
=
I
(
1+δ R
DS(ON)
(
)
)
MAX
V
IN
where d is the temperature dependency of R
and
DS(ON)
R
(approximately 2Ω) is the effective driver resistance
DR
The peak-to-peak drive levels are set by the INTV volt-
CC
at the MOSFET’s Miller threshold voltage. V
typical MOSFET minimum threshold voltage.
is the
TH(MIN)
age. This voltage is typically 5V. Consequently, logic-level
threshold MOSFETs must be used in most applications.
2
BothMOSFETshaveI RlosseswhilethetopsideN-channel
equation includes an additional term for transition losses,
The only exception is if low input voltage is expected (V
IN
< 5V); then, sub-logic level threshold MOSFETs (V
GS(TH)
which are highest at high input voltages. For V < 20V
< 3V) should be used. Pay close attention to the BV
IN
DSS
the high current efficiency generally improves with larger
specification for the MOSFETs as well; most of the logic-
MOSFETs, while for V > 20V the transition losses rapidly
level MOSFETs are limited to 30V or less.
IN
increasetothepointthattheuseofahigherR
device
DS(ON)
Selection criteria for the power MOSFETs include the on-
withlowerC
actuallyprovideshigherefficiency.The
MILLER
resistance, R
, Miller capacitance, C
, input
MILLER
DS(ON)
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
voltage and maximum output current. Miller capacitance,
, can be approximated from the gate charge curve
C
MILLER
usually provided on the MOSFET manufacturers’ data
sheet. C
is equal to the increase in gate charge
MILLER
The term (1 + d) is generally given for a MOSFET in the
along the horizontal axis while the curve is approximately
form of a normalized R
vs Temperature curve, but
flat divided by the specified change in V . This result is
DS(ON)
DS
d = 0.005/°C can be used as an approximation for low
then multiplied by the ratio of the application applied V
DS
voltage MOSFETs.
to the gate charge curve specified V . When the IC is
DS
3880fc
42
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
TheoptionalSchottkydiodesconductduringthedeadtime
betweentheconductionofthetwopowerMOSFETs.These
preventthebodydiodesofthebottomMOSFETsfromturn-
ing on, storing charge during the dead time and requiring
a reverse recovery period that could cost as much as 3%
TON_RISE to any value less than 0.250ms. The LTC3880
will perform the necessary math internally to assure the
voltage ramp is controlled to the desired slope. However,
thevoltageslopecannotbeanyfasterthanthefundamental
limits of the power stage. The shorter TON_RISE time is
set, the more jagged the TON_RISE ramp will appear. The
number of steps in the ramp is equal to TON_RISE/0.1ms.
in efficiency at high V . A 1A to 3A Schottky is generally
IN
a good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
The LTC3880 PWM will always use discontinuous mode
during the TON_RISE operation. In discontinuous mode,
the bottom gate is turned off as soon as reverse current
is detected in the inductor. This will allow the regulator to
start up into a pre-biased load.
VARIABLE DELAY TIME, SOFT-START AND OUTPUT
VOLTAGE RAMPING
There is no tracking feature in the LTC3880; how-
ever, two outputs can be given the same TON_RISE and
TON_DELAYtimestoeffectivelyrampupatthesametime.
Because the RUN pins are released at the same time and
both units use the same time base, the outputs will track
very closely. If the circuit is in a PolyPhase configuration,
all timing parameters must be the same.
The LTC3880 must enter the run state prior to soft-start.
The RUN pins are released after the part initializes and V
IN
isgreaterthantheVIN_ONthreshold.IfmultipleLTC3880s
are used in an application, they should be configured to
share the same RUN pins. They all hold their respective
RUN pins low until all devices initialize and V exceeds
IN
the VIN_ON threshold for all devices. The SHARE_CLK
pin assures all the devices connected to the signal use
the same time base.
Thedescribedmethodofstart-upsequencingistimebased.
For concatenated events it is possible to control the RUN
pinbasedontheGPIOpinofadifferentcontroller.TheGPIO
pincanbeconfiguredtoreleasewhentheoutputvoltageof
the converter is greater than the VOUT_UV_FAULT_LIMIT.
After the RUN pin releases, the controller waits for the
user-specified turn-on delay (TON_DELAY) prior to ini-
tiating an output voltage ramp. Multiple LTC3880s and
other LTC parts can be configured to start with variable
delay times. To work correctly, all devices use the same
timing clock (SHARE_CLK) and all devices must share
the RUN pin. This allows the relative delay of all parts to
be synchronized. The actual variation in the delay will be
dependent on the highest clock rate of the devices con-
nected to the SHARE_CLK pin (all Linear Technology ICs
are configured to allow the fastest SHARE_CLK signal to
control the timing of all devices). The SHARE_CLK signal
can be 10% in frequency, thus the actual time delays will
have some variance.
It is recommended to use the unfiltered V
UV fault limit
OUT
because there is little appreciable time delay between the
converter crossing the UV threshold and the GPIO pin
releasing. The unfiltered output can be enabled using the
MFR_GPIO_PROPAGATE_VOUT_UVUFcommand.(Refer
to the MFR section of the PMBus commands in this docu-
ment).Theunfilteredsignalmayhavesomeglitchingasthe
V
signaltransitionsthroughthecomparatorthreshold.
OUT
A small internal digital filter of 250µs has been added to
minimize this problem. To minimize the risk of GPIO pins
glitching, make the TON_RISE times less than 100ms. If
unwantedtransitionsstilloccuronGPIO,placeacapacitor
to ground on the GPIO pin to filter the waveform. The RC
time-constant of the filter should be set sufficiently fast to
assure no appreciable delay is incurred. A value of 300µs
to 500µs will provide some additional filtering without
significantly delaying the trigger event.
Soft-startisperformedbyactivelyregulatingtheloadvolt-
agewhiledigitallyrampingthetargetvoltagefrom0Vtothe
commanded voltage set point. The rise time of the voltage
ramp can be programmed using the TON_RISE command
to minimize inrush currents associated with the start-up
voltage ramp. The soft-start feature is disabled by setting
3880fc
43
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
DIGITAL SERVO MODE
If the TON_MAX_FAULT_IMIT is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSE is not set
to ignore 0X00, the servo begins:
For maximum accuracy in the regulated output voltage,
enable the digital servo loop by asserting bit 6 of the
MFR_PWM_MODE_LTC3880 command. In digital servo
mode,theLTC3880willadjusttheregulatedoutputvoltage
basedontheADCvoltagereading. Every100msthedigital
servoloopwillsteptheLSBoftheDAC(nominally1.375mV
or 0.6875mV depending on the voltage range bit) until the
outputisatthecorrectADCreading.Atpower-upthismode
engages after TON_MAX_FAULT_LIMIT unless the limit is
set to 0 (infinite). If the TON_MAX_FAULT_LIMIT is set to
0 (infinite), the servo begins after TON_RISE is complete
and VOUT has exceeded the VOUT_UV_FAULT_LIMIT and
IOUT_OC is not present. This same point in time is when
theoutputchangesfromdiscontinuoustotheprogrammed
mode as indicated in MFR_PWM_MODE_LTC3880 bits 0
and1. RefertoFigure21fordetailsontheVOUTwaveform
under time based sequencing.
1. After the TON_RISE sequence is complete;
2. After the TON_MAX_FAULT_LIMIT time has expired
and both VOUT_UV_FAULT and IOUT_OC_FAULT are
not present.
The maximum rise time is limited to 1.3 seconds.
In a PolyPhase configuration it is recommended only one
of the control loops have the digital servo mode enabled.
Thiswillassurethevariousloopsdonotworkagainsteach
other due to slight differences in the reference circuits.
SOFT OFF (SEQUENCED OFF)
In addition to a controlled start-up, the LTC3880 also sup-
portscontrolledturn-off.TheTOFF_DELAYandTOFF_FALL
functionsareshowninFigure22.TOFF_FALLisprocessed
when the RUN pin goes low or if the part is commanded
off. If the part faults off or GPIO is pulled low externally
and the part is programmed to respond to this, the output
will three-state rather than exhibiting a controlled ramp.
The output will decay as a function of the load.
RUN
DIGITAL SERVO
MODE ENABLED
FINAL OUTPUT
VOLTAGE REACHED
TON_MAX_FAULT_LIMIT
VOUT_UV_FAULT_LIMIT
DAC VOLTAGE
ERROR (NOT
TO SCALE)
TIME DELAY OF
200ms - 400ms
The output voltage will operate as shown in Figure 22 so
long as the part is in forced continuous mode and the
TOFF_FALL time is sufficiently slow that the power stage
can achieve the desired slope. The TOFF_FALL time can
only be met if the power stage and controller can sink
sufficient current to assure the output is a zero volts by
V
OUT
3880 F21
TIME
TON_RISE
TON_DELAY
Figure 21ꢀ Timing Controlled VOUT Rise
RUN
If the TON_MAX_FAULT_LIMIT is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSE is set to
ignore 0x00, the servo begins:
V
OUT
1. After the TON_RISE sequence is complete
2. AftertheTON_MAX_FAULT_LIMITtimeisreached;and
3880 F22
TIME
TOFF_DELAY
TOFF_FALL
3. After the VOUT_UV_FAULT_LIMIT has been exceed or
the IOUT_OC_FAULT_LIMIT is not longer active.
Figure 22ꢀ TOFF_DELAY and TOFF_FALL
3880fc
44
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
the end of the fall time interval. If the TOFF_FALL time is
set shorter than the time required to discharge the load
capacitance, the output will not reach the desired zero volt
state. At the end of TOFF_FALL, the controller will cease
INTVCC current is limited to less than 69mA from a 24V
supply:
T = 70°C + 69mA • 24V • 33°C/W = 125°C
J
To prevent the maximum junction temperature from being
exceeded, a LTC3880-1 can be used. In the LTC3880-1,
to sink current and V
will decay at the natural rate
OUT
determined by the load impedance. If the controller is in
discontinuous mode, the controller will not pull negative
current and the output will be pulled low by the load, not
the power stage. The maximum fail time is limited to 1.3
seconds. The shorter TOFF_FALL time is set, the more
jagged the TOFF_FALL ramp will appear. The number of
steps in the ramp is equal to TOFF_FALL/0.1ms.
the INTV linear regulator is disabled and approximately
CC
2mA of current is supplied internally from V . Significant
IN
system efficiency and thermal gains can be realized by
powering the EXTV pin from a switching 5V regulator.
CC
The V current resulting from the gate driver and control
IN
circuitry will be scaled by a factor of:
VEXTVCC
1
INTV REGULATOR
CC
V
Efficiency
IN
The LTC3880 features an NPN linear regulator that sup-
Tying the EXTV pin to a 5V supply (LTC3880-1 only)
CC
plies power to INTV from the V supply. INTV powers
CC
DD33
IN
CC
reduces the junction temperature in the previous example
the gate drivers, V
and much of the LTC3880 internal
from125°C to:
circuitry. The linear regulator produces the voltage at the
INTV pin to nominally 5V when V is greater than 6.5V.
T = 70°C + 69mA • 5V • 33°C/W + 2mA • 24V • 33°C/W
J
CC
IN
Theregulatorcansupplyapeakcurrentof100mAandmust
be bypassed to ground with a minimum of 1µF ceramic
capacitororlowESRelectrolyticcapacitor.Nomatterwhat
type of bulk capacitor is used, an additional 0.1µF ceramic
= 83°C
Do not tie INTV on the LTC3880 to an external supply
CC
because INTV will attempt to pull the external supply
CC
high and hit current limit, significantly increasing the die
capacitorplaceddirectlyadjacenttotheINTV andPGND
CC
temperature.
pinsishighlyrecommended.Goodbypassingisneededto
supplythehightransientcurrentsrequiredbytheMOSFET
gate drivers and to prevent interaction between the chan-
nels. The NPN linear regulator on the LTC3880-1 is not
present and an external 5V supply is needed.
ForapplicationswhereV is5V,tietheV andINTV pins
IN
IN
CC
together and tie the combined pins to the 5V input with a
1Ωor2.2ΩresistorasshowninFigure23.Tominimizethe
voltage drop caused by the gate charge current a low ESR
capacitor must be connected to the V /INTV (EXTV )
IN
CC
CC
CC
CC
High input voltage application in which large MOSFETs
pins. This configuration will override the INTV (EXTV )
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3880 to be
exceeded. The INTVCC current, of which a large percent-
age is due to the gate charge current, may be supplied by
either the internal 5V linear regulator or from an external
5V regulator on the LTC3880-1. If the LTC3880 is used
with the internal regulator activated, the power through
the IC is equal to VIN • IINTVCC. The gate charge current
is dependent on operating frequency as discussed in the
Efficiency Considerations section. The junction tempera-
ture can be estimated by using the equations in Note 2 of
the Electrical Characteristics. For example, the LTC3880
linear regulator and will prevent INTV (EXTV ) from
CC
CC
CC
dropping too low. Make sure the INTV (EXTV ) voltage
CC
exceedstheR
testvoltagefortheMOSFETswhichis
DS(ON)
V
IN
LTC3880
LTC3880-1
R
VIN
1Ω
INTV /EXTV
5V
CC
CC
+
C
INTVCC
4.7µF
C
IN
3880 F23
Figure 23ꢀ Setup for a 5V Input
3880fc
45
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
typically 4.5V for logic level devices. The UVLO on INTV
UNDERVOLTAGE LOCKOUT
CC
(EXTV ) is set to approximately 4V. Both a LTC3880 and
CC
The LTC3880 is initialized by an internal threshold-based
LTC3880-1 are valid for this configuration.
UVLO where V must be approximately 4V and INTV /
IN
CC
EXTV , V
, V
must be within approximately 20%
CC DD33 DD25
TOPSIDE MOSFET DRIVER SUPPLY (C , D )
of the regulated values. In addition, V
must be within
B
B
DD33
approximately 7% of the targeted value before the RUN
pin is released. After the part has initialized, an additional
External bootstrap capacitors C connected to the BOOST
B
pinssupplythegatedrivevoltagesforthetopsideMOSFETs.
comparator monitors V . The VIN_ON threshold must
IN
Capacitor C in the Block Diagram is charged though
B
be exceeded before the power sequencing can begin.
external diode D from INTV when the SW pin is low.
B
CC
When V drops below the VIN_OFF threshold, the RUN
IN
When one of the topside MOSFETs is to be turned on,
pins will be pulled low and V must increase above the
IN
the driver places the C voltage across the gate source
B
VIN_ON threshold before the controller will restart. The
normalstart-upsequencewillbeallowedaftertheVIN_ON
threshold is crossed.
of the desired MOSFET. This enhances the MOSFET and
turns on the topside switch. The switch node voltage, SW,
rises to V and the BOOST pin follows. With the topside
IN
MOSFET on, the boost voltage is above the input supply:
It is possible to program the contents of the NVM in the
V
B
= V + V
. The value of the boost capacitor
application if the V
supply is externally driven. This
BOOST
IN
INTVCC
DD33
C needs to be 100 times that of the total input capa-
will activate the digital portion of the LTC3880 without
engaging the high voltage sections. PMBus communica-
citance of the topside MOSFET(s). The reverse break-
down of the external Schottky diode must be greater
tions are valid in this supply configuration. If V has not
IN
than V
. When adjusting the gate drive level, the
IN(MAX)
been applied to the LTC3880, bit 3 (NVM Not Initialized)
in MFR_COMMON will be asserted low. If this condition is
detected,thepartwillonlyrespondtoaddresses5Aand5B.
To initialize the part issue the following set of commands:
global address 0x5B command 0xBD data 0x2B followed
by global address 5B command 0xBD and data 0xC4. The
part will now respond to the correct address. Configure
thepartasdesiredthenissueaSTORE_USER_ALL. When
final arbiter is the total input current for the regulator. If
a change is made and the input current decreases, then
the efficiency has improved. If there is no change in input
current, then there is no change in efficiency.
PWM jitter has been observed in some designs operating
at higher V /V
ratios. This jitter does not substantially
IN OUT
affect the circuit accuracy. Referring to Figure 24, PWM
jitter can be removed by inserting a series resistor with a
value of 1Ω to 5Ω between the cathode of the diode and
the BOOSTn pin. A resistor case size of 0603 or larger is
recommended to reduce ESL and achieve the best results.
V is applied a MFR_RESET command must be issued to
IN
allow the PWM to be enabled and valid ADC conversions
to be read.
C AND C
SELECTION
IN
OUT
V
IN
V
IN
The selection of C is simplified by the 2-phase architec-
IN
ture and its impact on the worst-case RMS current drawn
throughtheinputnetwork(battery/fuse/capacitor).Itcanbe
shown that the worst-case capacitor RMS current occurs
when only one controller is operating. The controller with
BOOST
TGATE
0.2µF
LTC3880
LTC3880-1
SW
INTV
CC
the highest (V )(I ) product needs to be used in the
OUT OUT
10µF
formula below to determine the maximum RMS capacitor
current requirement. Increasing the output current drawn
from the other controller will actually decrease the input
RMS ripple current from its maximum value. The out-of-
phasetechniquetypicallyreducestheinputcapacitor’sRMS
3880fc
BGATE
PGND
3880 F24
Figure 24ꢀ Boost Circuit to Minimize PWM Jitter
46
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
ripple current by a factor of 30% to 70% when compared
to a single phase power supply solution.
A small (0.1µF to 1µF) bypass capacitor between the chip
IN
V pin and ground, placed close to the LTC3880, is also
suggested. A 2.2Ω – 10Ω resistor placed between C
IN
Incontinuousmode,thesourcecurrentofthetopMOSFET
(C1) and the V pin provides further isolation between
IN
is a square wave of duty cycle (V )/(V ). To prevent
OUT
IN
the two channels.
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
The selection of C
is driven by the effective series
OUT
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
1/2
IMAX
output ripple (∆V ) is approximated by:
CIN Required IRMS
≈
V
OUT )(
V – V
IN OUT
(
)
OUT
V
IN
1
∆VOUT ≈IRIPPLE ESR+
This formula has a maximum at V = 2V , where
IN
OUT
8fC
OUT
I
= I /2. This simple worst-case condition is com-
RMS
OUT
monlyusedfordesignbecauseevensignificantdeviations
donotoffermuchrelief.Notethatcapacitormanufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capaci-
tor, or to choose a capacitor rated at a higher temperature
thanrequired.Severalcapacitorsmaybeparalleledtomeet
size or height requirements in the design. Due to the high
operating frequency of the LTC3880, ceramic capacitors
where f is the operating frequency, C
is the output
OUT
capacitance and I
is the ripple current in the induc-
RIPPLE
tor. The output ripple is highest at maximum input voltage
since I increases with input voltage.
RIPPLE
FAULT CONDITIONS
The LTC3880 GPIOn pins are configurable to indicate a
variety of faults including OV/UV, OC, OT, timing faults,
peak overcurrent faults. In addition the GPIOn pins can
be pulled low by external sources indicating a fault in
some other portion of the system. The fault response is
configurable and allow the following options:
can also be used for C . Always consult the manufacturer
IN
if there is any question.
The benefit of the LTC3880 2-phase operation can be
calculated by using the equation above for the higher
power controller and then calculating the loss that would
have resulted if both controller channels switched on at
the same time. The total RMS power lost is lower when
both controllers are operating due to the reduced overlap
of current pulses required through the input capacitor’s
ESR. This is why the input capacitor’s requirement cal-
culated above for the worst-case controller is adequate
for the dual controller design. Also, the input protection
fuse resistance, battery resistance, and PC board trace
resistance losses are also reduced due to the reduced
peak currents in a 2-phase system. The overall benefit
of a multiphase design will only be fully realized when
the source impedance of the power supply/battery is
included in the efficiency testing. The sources of the top
MOSFETs should be placed within 1cm of each other and
share a common CIN(s). Separating the sources and CIN
mayproduceundesirablevoltageandcurrentresonances
at VIN.
n
Ignore
n
Shut Down Immediately—Latch Off
n
ShutDownImmediately—RetryIndefinitelyattheTime
Interval Specified in MFR_RETRY_DELAY
Refer to the PMBus section of the data sheet and the
PMBus specification for more details.
The OV response is automatic and virtually immediate. If
an OV is detected, TG goes low and BG is asserted.
Fault logging is available on the LTC3880. The fault log-
ging is configurable to automatically store data when a
fault occurs that causes the unit to fault off. The header
portion of the fault logging table contains peak values. It
is possible to read these values at any time. This data will
be useful while troubleshooting the fault.
3880fc
47
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
If the LTC3880 internal temperature is in excess of 85°C,
the write into the NVM is not recommended. The data will
still be held in RAM, unless the 3.3V supply UVLO thresh-
old is reached. If the die temperature exceeds 130°C all
NVM communication is disabled until the die temperature
drops below 120°C.
long it takes for the desired signal to reach approximately
63% of the output value. This is one time constant.
The SYNC pin has an on-chip pull-down transistor with the
output held low for nominally 500ns. If the internal oscil-
lator is set for 500kHz and the load is 100pF and a 3x time
constant is required, the resistor calculation is as follows:
2µs–500ns
3•100pF
OPEN-DRAIN PINS
RPULLUP
=
= 5k
The LTC3880 has the following open-drain pins:
The closest 1% resistor is 4.99k.
3.3V Pins
If timing errors are occurring or if the SYNC frequency is
notasfastasdesired,monitorthewaveformanddetermine
if the RC time constant is too long for the application. If
possible reduce the parasitic capacitance. If not reduce
the pull up resistor sufficiently to assure proper timing.
The SHARE_CLK pull-up resistor has a similar equation
with a period of 10µs and a pull-down time of 1µs. The
RC time constant should be approximately 3µs or faster.
1. GPIOn
2. SYNC
3. SHARE_CLK
5V Pins(5V pinsoperate correctly whenpulled to 3.3V.)
1. RUNn
2. ALERT
3. SCL
4. SDA
PHASE-LOCKED LOOP AND FREQUENCY
SYNCHRONIꢂATION
All the above pins have on-chip pull-down transistors
that can sink 3mA at 0.4V. The low threshold on the pins
is 1.4V; thus, plenty of margin on the digital signals with
3mA of current. For 3.3V pins, 3mA of current is a 1.1k
resistor. Unless there are transient speed issues associ-
ated with the RC time constant of the resistor pull-up and
parasitic capacitance to ground, a 10k resistor or larger
is generally recommended.
The LTC3880 has a phase-locked loop (PLL) comprised of
aninternalvoltage-controlledoscillator(VCO)andaphase
detector. The PLL is locked to the falling edge of the SYNC
pin. The phase relationship between channel 0, channel 1
and the falling edge of SYNC is controlled by the lower 3
bits of the MFR_PWM_CONFIG_LTC3880 command. For
PolyPhase applications, it is recommended all the phases
be spaced evenly. Thus for a 2-phase system the signals
should be 180° out of phase and a 4-phase system should
be spaced 90°.
For high speed signals such as the SDA, SCL and SYNC,
a lower value resistor may be required. The RC time con-
stant should be set to 1/3 to 1/5 the required rise time
to avoid timing issues. For a 100pF load and a 400kHz
PMBus communication rate, the rise time must be less
than 300ns. The resistor pull-up on the SDA and SCL pins
with the time constant set to 1/3 the rise tme:
The phase detector is an edge-sensitive digital type that
provides a known phase shift between the external and
internal oscillators. This type of phase detector does not
exhibit false lock to harmonics of the external clock.
tRISE
3•100pF
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the internal
filter network. The PLL lock range is guaranteed between
250kHzand1MHz.Nominalpartswillhavearangebeyond
this; however, operation to a wider frequency range is not
guaranteed.
RPULLUP
=
=1k
The closest 1% resistor value is 1k. Be careful to minimize
parasitic capacitance on the SDA and SCL pins to avoid
communication problems. To estimate the loading
capacitance,monitorthesignalinquestionandmeasurehow
3880fc
48
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
The PLL has a lock detection circuit. If the PLL should
lose lock during operation, bit 4 of the STATUS_MFR_
SPECIFIC command is asserted and the ALERT pin is
pulled low. The fault can be cleared by writing a 1 to the
bit. If the user does not wish to see the PLL_FAULT, even
if a synchronization clock is not available at power up,
bit 3 of the MFR_CONFIG_ALL_LTC3880 command must
be asserted.
inductor current ripple and at least 10mV – 15mV ripple
on the current sense signal. The minimum on-time can be
affected by PCB switching noise in the voltage and cur-
rent loop. As the peak current sense voltage decreases,
the minimum on-time gradually increases to 130ns. This
is of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle
drops below the minimum on-time limit in this situation,
a significant amount of cycle skipping can occur with cor-
respondingly larger current and voltage ripple.
If the SYNC signal is not clocking in the application, the
PLL will run at the lowest free running frequency of the
VCO. This will be well below the intended PWM frequency
of the application and may cause undesirable operation
of the converter.
RCONFIG (EXTERNAL RESISTOR
CONFIGURATION PINS)
The LTC3880 default NVM is programmed to respect the
RCONFIG pins. If a user wishes the output voltage, PWM
frequency and phasing and the address to be set without
programmingthepartorpurchasingspeciallyprogrammed
parts, the RCONFIG pins can be used to establish these
parameters. The RCONFIG pins all require a resistor di-
vider between the VDD25 and SGND of the LTC3880. The
RCONFIG pins are only monitored at initial power up and
during a reset so modifying their values perhaps using an
A/D after the part is powered will have no effect. 1% resis-
tors or better must be used to assure proper operation.
Noisy clock signals should not be routed near these pins.
If the PWM signal appears to be running at too high a
frequency, monitor the SYNC pin. Extra transitions on
the falling edge will result in the PLL trying to lock on to
noise versus the intended signal. Review routing of digital
control signals and minimize crosstalk to the SYNC signal
to avoid this problem. Multiple LTC3880s are required to
share the SYNC pin in PolyPhase configurations, for other
configurations it is optional. If the SYNC pin is shared be-
tween LTC3880s, only one LTC3880 can be programmed
with a frequency output. All the other LTC3880s must be
programmed to external clock.
MINIMUM ON-TIME CONSIDERATIONS
Voltage Selection
Minimum on-time, t , is the smallest time duration
ON(MIN)
When an output voltage is set using the RCONFIG pins on
VOUTn_CFG and VTRIMn_CFG, the following parameters
are set as a percentage of the output voltage:
that the LTC3880 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
• VOUT_OV_FAULT_LIMIT
• VOUT_OV_WARN
• VOUT_MAX
+10%
+7.5%
+7.5%
+5%
VOUT
tON(MIN)
<
V • fOSC
IN
• VOUT_MARGIN_HI
• POWER_GOOD_ON
• POWER_GOOD_OFF
• VOUT_MARGIN_LO
• VOUT_UV_WARN
• VOUT_UV_FAULT_LIMIT
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
–7%
–8%
–5%
–6.5%
–7%
The minimum on-time for the LTC3880 is approximately
90ns, with reasonably good PCB layout, minimum 30%
3880fc
49
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
Refer to Tables 12 and 13 to set the output voltage using
RCONFIG pins VOUTn_CFG and VTRIMn_CFG. RTOP is
connected between VDD25 and the pin and RBOTTOM is
connected between the pin and SGND. 1% resistors must
be used to assure proper operation.
Open
0
0.5
Table 13ꢀ VTRIMn_CFG
V
(mV)
V
(V)
TRIM
OUT
CHANGE TO
IF V
HAS
OUT
R
TOP
(kΩ)
R
(kΩ)
V VOLTAGE
SET
10kΩ/23ꢀ3kΩ
BOTTOM
The output voltage set point is equal to:
0 or Open
10
Open
23.2
15.8
20.5
17.4
17.8
15
0
99
V
= VOUTn_CFG + VTRIMn_CFG
SETPOINT
10
86.625
74.25
Forexample,iftheVOUTn_CFGpinhasR equalto24.9k
TOP
16.2
16.2
20
and R
TOP
equal to 4.32k, and VTRIMn_CFG is set with
BOTTOM
not inserted and R
61.875
49.5
R
equal to0Ω:
BOTTOM
20
37.125
24.75
5.5
5.25
5
V
= 1.1V – 0.099V or 1.001V
SETPOINT
20
12.7
11
If odd values of output voltage are required from 0.5V
to 3.3V, use only the VOUTn_CFG resistor divider, the
20
12.375
–12.375
–24.75
–37.125
–49.5
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
11.3
9.09
7.32
5.76
4.32
3.57
1.96
0
4.75
4.5
V
pin can be open or shorted to V
. If the output
TOP
TRIM
DD25
set point is 5V, the VOUTn_CFG must have R
equal to
4.25
4
10k and R
have R equal to 20k and R
equal to 23.2k and VTRIMn_CFG must
BOTTOM
equal to 11k. If VOUT
TOP
BOTTOM
–61.875
–74.25
–86.625
–99
3.75
3.63
3.5
is 2.5 volts or lower, low range is used. The maximum
voltage command on channel 0 is 4.096 volts including
VOUT_OV_FAULT,VOUT_OV_WARN,VOUT_MARGIN_HI
and VOUT.
3.46
Table 12ꢀ VOUTn_CFG
Frequency and Phase Selection Using RCONFIG
R
TOP
(kΩ)
R
(kΩ)
V
(V)
OUT
BOTTOM
The frequency and phase commands are linked if they
are set using the RCONFIG pins. If PMBus commands
are used the two parameters are independent. The SYNC
pins must be shared in PolyPhase configurations where
multiple LTC3880s are used to produce the output. If the
configuration is not PolyPhase the SYNC pins do not
have to be shared. If the SYNC pins are shared between
LTC3880s only one SYNC pin can be set as a frequency
output, all other SYNC pins must be set to External Clock.
0 or Open
10
Open
23.2
15.8
20.5
17.4
17.8
15
NVM
See VTRIM
3.3
10
16.2
16.2
20
3.1
2.9
2.7
20
2.5
20
12.7
11
2.3
20
2.1
Forexampleina4-phaseconfigurationclockedat425kHz,
one of the LTC3880s must be set to the desired frequency
and phase and the other LTC3880 must be set to External
24.9
24.9
24.9
24.9
24.9
30.1
30.1
11.3
9.09
7.32
5.76
4.32
3.57
1.96
1.9
1.7
1.5
1.3
1.1
0.9
0.7
3880fc
50
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
Table 14ꢀ FREQ_CFG (Phase Based on Falling Edge of SYNC)
RTOP (kΩ)
0 or Open
10
RBOTTOM (kΩ)
Open
23.2
15.8
20.5
17.4
17.8
15
FREQUENCY (kHz)
DESCRIPTION
NVM
θ
SYNC TO θ0
NVM
0
θ
SYNC TO θ1
NVM
180
NVM
250
2-Phase
3-Phase
4-Phase
2-Phase
3-Phase
4-Phase
2-Phase
3-Phase
4-Phase
2-Phase
3-Phase
4-Phase
2-Phase
3-Phase
4-Phase
2-Phase
10
250
120
90
0
240
16.2
16.2
20
250
270
425
180
425
120
90
0
240
20
425
270
20
12.7
11
500
180
20
500
120
90
0
240
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
11.3
9.09
7.32
5.76
4.32
3.57
1.96
0
500
270
575
180
575
120
90
0
240
575
270
650
180
650
120
90
0
240
650
270
External Clock
180
Clock. All phasing is with respect to the falling edge of
SYNC.
achieved using the FREQ_CFG pin.
Address Selection Using RCONFIG
LTC3880 Chip 1 set the frequency to 425kHz with 90° and
270° phase shift:
The LTC3880 address is selected using a combination of
the address stored in NVM and the ASEL pin. The MSB
of ASEL is the MSB in the NVM and the LSB is the ASEL
value. This allows 16 different LTC3880s on a single board
with one programmed address in NVM.
R
TOP
= 20kΩ and R
= 15kΩ
BOTTOM
LTC3880 Chip 2 set the frequency to External Clock with
0° and 180° phase shift:
R
= open and R
= 0Ω
If the address stored in NVM is 0x4F, then the part address
can be set from 0x40 to 0x4F using ASEL. (The standard
default address is 0x4F). Do not set any part address to
0x5A or 0x5B because these are global addresses and all
parts will respond to them.
TOP
BOTTOM
Frequencies of 350kHz, 750kHz and 1000kHz can only be
set using NVM programming. If a 6-phase configuration
is desired, NVM programming will give optimal phasing.
All other configurations in frequency and phasing can be
To choose address 0x40 R
is open and
TOP
R
= 0Ω
BOTTOM
To choose address 0x45 R
= 7.32k
= 24.9k and
TOP
R
BOTTOM
3880fc
51
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
To choose address 0x4E R
BOTTOM
= 10.0k and
30.1
1.96
0
xyz_0001
xyz_0000
1
0
TOP
R
= 15.8k
Open
Table 15ꢀ ASEL
(kΩ)
EFFICIENCY CONSIDERATIONS
R
TOP
R
(kΩ)
BOTTOM
SLAVE ADDRESS
NVM
LSB HEX
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
0 or Open
10
Open
23.2
15.8
20.5
17.4
17.8
15
xyz_1111
xyz_1110
xyz_1101
xyz_1100
xyz_1011
xyz_1010
xyz_1001
xyz_1000
xyz_0111
xyz_0110
xyz_0101
xyz_0100
xyz_0011
xyz_0010
F
E
D
C
B
A
9
8
7
6
5
4
3
2
10
16.2
16.2
20
20
%Efficiency = 100% – (L1 + L2 + L3 + ...)
20
12.7
11
where L1, L2, etc. are the individual losses as a percent-
age of input power.
20
24.9
24.9
24.9
24.9
24.9
30.1
11.3
9.09
7.32
5.76
4.32
3.57
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3880 circuits: 1) IC V current, 2) INTV
IN
CC
2
regulator current, 3) I R losses, 4) Topside MOSFET
transition losses.
Table 15A1ꢀ LTC3880 MFR_ADDRESS Command Examples
Expressing Both 7- or 8-Bit Addressing
1. The V current is the DC supply current given in
IN
the Electrical Characteristics table, which excludes
HEX DEVICE
ADDRESS
MOSFET driver and control currents. V current typi-
IN
BIT BIT BIT BIT BIT BIT BIT BIT
DESCRIPTION 7 BIT 8 BIT
7
0
0
0
0
0
1
6
1
1
1
1
1
0
5
0
0
0
1
1
0
4
1
1
0
0
0
0
3
1
1
1
0
0
0
2
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
1
0
R/W
0
cally results in a small (<0.1%) loss.
4
Rail
0x5A 0xB4
0x5B 0xB6
0x4F 0x9E
0x60 0xC0
0x61 0xC2
2. INTV current is the sum of the MOSFET driver and
CC
4
Global
0
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
Default
0
Example 1
0
Example 2
0
2,3,5
Disabled
0
from INTV to ground. The resulting dQ/dt is a cur-
CC
Note 1: This table can be applied to the MFR_CHANNEL_ADDRESS,
and MFR_RAIL_ADDRESS commands as well as the MFR_ADDRESS
command.
rent out of INTV that is typically much larger than the
CC
control circuit current. In continuous mode, I
GATECHG
Note 2: A disabled value in one command does not disable the device, nor
does it disable the Global address.
= f(Q + Q ), where Q and Q are the gate charges of
T
B
T
B
the topside and bottom side MOSFETs.
Note 3: A disabled value in one command does not inhibit the device from
responding to device addresses specified in other commands.
On the LTC3880-1, supplying EXTV from an output-
CC
Note 4: It is not recommended to write the value 0x00, 0x0C (7 bit),
or 0x5A or 0x5B(7 bit) to the MFR_ADDRESS, MFR_CHANNEL_
ADDRESS or the MFR_RAIL_ADDRESS commands.
derived source will scale the V current required for
IN
the driver and control circuits by a factor of:
Note 5: To disable the address enter 0x80 in the MFR_ADDRESS
command. The 0x80 is greater than the 7-bit address field, disabling
the address.
VEXTVCC
1
V
Efficiency
IN
Forexample,ina20Vto5Vapplication,10mAofINTV
CC
current results in approximately 2.5mA of V current.
IN
3880fc
52
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
This reduces the mid-current loss from 10% or more
and inductor core losses generally account for less than
2% total additional loss.
(if the driver was powered directly from V ) to only a
IN
few percent.
2
CHECKING TRANSIENT RESPONSE
3. I R losses are predicted from the DC resistances of the
fuse(ifused), MOSFET, inductor, currentsenseresistor.
In continuous mode, the average output current flows
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
through L and R
, but is “chopped” between the
SENSE
topside MOSFET and the synchronous MOSFET. If the
two MOSFETs have approximately the same R
load current. When a load step occurs, V
shifts by an
OUT
,
DS(ON)
amount equal to ∆I
(ESR), where ESR is the effective
LOAD
then the resistance of one MOSFET can simply be
series resistance of C . ∆I
also begins to charge or
OUT
LOAD
summed with the resistances of L and R
to ob-
SENSE
discharge C
generating the feedback error signal that
OUT
2
tain I R losses. For example, if each R
= 10mΩ,
DS(ON)
forces the regulator to adapt to the current change and
return V to its steady-state value. During this recov-
R = 10mΩ, R
= 5mΩ, then the total resistance
L
SENSE
OUT
is 25mΩ. This results in losses ranging from 2% to
8% as the output current increases from 3A to 15A for
a 5V output, or a 3% to 12% loss for a 3.3V output.
ery time V
can be monitored for excessive overshoot
OUT
or ringing, which would indicate a stability problem.
The availability of the I pin not only allows optimization
TH
Efficiency varies as the inverse square of V
for the
OUT
of control loop behavior but also provides a DC-coupled
and AC-filtered closed-loop response test point. The DC
step, rise time and settling at this test point truly reflects
the closed loop response. Assuming a predominantly
second order system, phase margin and/or damping fac-
tor can be estimated using the percentage of overshoot
seen at this pin. The bandwidth can also be estimated
sameexternalcomponentsandoutputpowerlevel. The
combined effects of increasingly lower output voltages
andhighercurrentsrequiredbyhighperformancedigital
systemsisnotdoublingbutquadruplingtheimportance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
by examining the rise time at the pin. The I external
TH
components shown in the Typical Application circuit will
provide an adequate starting point for most applications.
The only two programmable parameters that affect loop
gain are the voltage range, bits 5 and 6 of the MFR_PWM_
CONFIG_LTC3880 command and the current range, bit 7
of the MFR_PWM_MODE_LTC3880 command. Be sure to
establishthesesettingspriortocompensationcalculation.
2
Transition Loss = (1.7) V
I
C
f
IN O(MAX) RSS
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
The I series R -C filter sets the dominant pole-zero
TH
C
C
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the
loop gain and phase. An output current pulse of 20%
losses can be minimized by making sure that C has
IN
adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a
minimum of 20µF to 40µF of capacitance having
a maximum of 20mΩ to 50mΩ of ESR. The LTC3880
2-phasearchitecturetypicallyhalvesthisinputcapacitance
requirement over competing solutions. Other losses
including Schottky conduction losses during dead time
3880fc
53
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
to 80% of full-load current having a rise time of 1µs to
require a 250µs rise time, limiting the charging current
to about 200mA.
10µs will produce output voltage and I pin waveforms
TH
that will give a sense of the overall loop stability without
breakingthefeedbackloop. PlacingapowerMOSFETwith
a resistor to ground directly across the output capacitor
and driving the gate with an appropriate signal generator
is a practical way to produce to a load step. The MOSFET
PC BOARD LAYOUT CHECKLIST
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 25. Figure 26 illustrates the
current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
+ R
will produce output currents approximately
SERIES
equal to V /R
. R
values from 0.1Ω to 2Ω
OUT SERIES SERIES
are valid depending on the current limit settings and the
programmed output voltage. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
1. Are the top N-channel MOSFETs M1 and M2 located
within 1 cm of each other with a common drain con-
is why it is better to look at the I pin signal which is in
nection at C ? Do not attempt to split the input de-
TH
IN
the feedback loop and is the filtered and compensated
control loop response. The gain of the loop will be in-
coupling for the two channels as it can cause a large
resonant loop.
creased by increasing R and the bandwidth of the loop
C
2. Are the signal and power grounds kept separate? The
combinedICsignalgroundpinandthegroundreturnof
will be increased by decreasing C . If R is increased by
C
C
the same factor that C is decreased, the zero frequency
C
C
mustreturntothecombinedC (–)terminals.
INTVCC
OUT
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
The I traces should be as short as possible. The path
TH
formed by the top N-channel MOSFET, Schottky diode
and the C capacitor should have short leads and PC
IN
tracelengths.Theoutputcapacitor(–)terminalsshould
be connected as close as possible to the (–) terminals
of the input capacitor by placing the capacitors next to
each other and away from the Schottky loop described
above.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with C , causing a rapid drop in V . No regulator can
OUT
OUT
3. Does the LTC3880 V
lines equal V ? V
is
SENSE
OUT
OUT0
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
differential. V
should reference the SGND (Pin 41)
OUT1
to the Load 1 ground.
+
–
4. Are the I
and I
leads routed together with
SENSE
SENSE
C
to C
is greater than 1:50, the switch rise time
LOAD
OUT
minimumPCtracespacing?Thefiltercapacitorbetween
should be controlled so that the load rise time is limited
+
–
I
and I
should be as close as possible to
SENSE
SENSE
to approximately 25 • C
. Thus a 10µF capacitor would
LOAD
3880fc
54
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
I
TH1
V
I
SENSE1
L1
R
SENSE1
D1
+
V
TG1
SW1
OUT1
SENSE1
SENSE1
–
I
C
B1
M1
M2
BOOST1
BG1
LTC3880
1µF
CERAMIC
f
IN
SYNC
RUN0
RUN1
SGND
C
C
OUT1
V
IN
R
IN
C
VIN
PGND
V
GND
IN
C
IN
C
INTVCC
–
+
INTV
I
CC
SENSE0
OUT2
D2
1µF
CERAMIC
BG0
I
SENSE0
M4
M3
+
BOOST0
V
SENSE0
C
B0
SW0
TG0
I
TH0
R
SENSE0
–
V
V
SENSE0
OUT0
L0
3880 F25
Figure 25ꢀ Recommended Printed Circuit Layout Diagram
SW1
L1
R
SENSE1
V
OUT1
D1
C
R
L1
OUT1
V
IN
R
IN
C
IN
SW0
L0
R
SENSE0
V
OUT0
D0
C
R
L0
OUT0
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
3880 F26
Figure 26ꢀ Branch Current Waveforms
3880fc
55
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
the IC. Ensure accurate current sensing with Kelvin
connectionsatthesenseresistororinductor,whichever
is used for current sensing.
output load drops below the low current operation
threshold—typically 10% of the maximum designed cur-
rent level in Burst Mode operation.
5. Is the INTV decoupling capacitor connected close to
The duty cycle percentage should be maintained from
cycletocycleinawell-designed,lownoisePCBimplemen-
tation. Variation in the duty cycle at a subharmonic rate
can suggest noise pickup at the current or voltage sensing
inputs or inadequate loop compensation. Overcompensa-
tion of the loop can be used to tame a poor PC layout if
regulatorbandwidthoptimizationisnotrequired.Onlyafter
each controller is checked for its individual performance
should both controllers be turned on at the same time.
A particularly difficult region of operation is when one
controller channel is nearing its current comparator trip
pointwhentheotherchannelisturningonitstopMOSFET.
This occurs around 50% duty cycle on either channel due
to the phasing of the internal clocks and may cause minor
duty cycle jitter.
CC
theIC, betweentheINTV andthepowergroundpins?
CC
ThiscapacitorcarriestheMOSFETdriverscurrentpeaks.
Anadditional1µFceramiccapacitorplacedimmediately
next to the INTV and PGND pins can help improve
CC
noise performance substantially.
6. Keep the switching nodes (SW1, SW0), top gate nodes
(TG1, TG0), andboostnodes(BOOST1, BOOST0)away
from sensitive small-signal nodes, especially from the
opposite channel’s voltage and current sensing feed-
back pins. All of these nodes have very large and fast
moving signals and therefore should be kept on the
“output side” of the LTC3880 and occupy minimum
PC trace area. If DCR sensing is used, place the top
resistor (Figure 18a, R1) close to the switching node.
Reduce V from its nominal level to verify operation
IN
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering V while
IN
monitoring the outputs to verify operation.
capacitors with tie-ins for the bottom of the INTV
CC
decouplingcapacitor,thebottomofthevoltagefeedback
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
resistive divider and the SGND pin of the IC.
PC BOARD LAYOUT DEBUGGING
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
totheinternaloscillatorandprobetheactualoutputvoltage
as well. Check for proper performance over the operating
voltage and current range expected in the application.
The frequency of operation should be maintained over
the input voltage range down to dropout and until the
for inductive coupling between C , Schottky and the top
IN
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
3880fc
56
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
V
IN
6V TO 24V
22µF
1µF
10µF
D1
D2
V
INTV
IN
CC
M1
M3
TG0
TG1
M2
M4
0.1µF
0.1µF
L0
L1
BOOST0
SW0
BOOST1
SW1
1.0µH
0.56µH
BG0
SYNC
SDA
SCL
BG1
4.99k
10k
10k
10k
10k
10k
10k
10k
10k
2.0k
1µF
1.58k
1µF
PGND
V
DD25
LTC3880
V
10k
24.9k
11.3k
10k
20k
ALERT
OUT0_CFG
15.8k
23.2k
12.7k
V
V
GPIO0
TRIM0_CFG
DD33
GPIO1
V
OUT1_CFG
V
SHARE_CLK
RUN0
TRIM1_CFG
ASEL
RUN1
WP
FREQ_CFG
TSNS0
+
TSNS1
+
I
I
I
SENSEO
SENSE1
2.0k
1.58k
0.22µF
0.22µF
220pF
–
–
I
V
V
V
V
1.8V
15A
SENSEO
SENSE1
OUT0
3.3V
15A
OUT1
+
V
SENSEO
SENSEO
SENSE1
–
I
V
I
TH1
THO
+
+
4700pF
4.99k
2200pF
4.99k
SGND
V
DD33
DD25
530µF
530µF
10nF
220pF
1µF
1µF
10nF
L0, L1: VISHAY IHLP-4040DZ-11 1µH, 0.56µH
M1, M2: INFINEON BSC050N03LS
M3, M4: INFINEON BSC010NE2LSI
3880 F27
Figure 27ꢀ High Efficiency Dual 500kHz 3ꢀ3V/1ꢀ8V Step-Down Converter
The regulated output is established by the VOUT_
COMMAND stored in NVM or placing the following resis-
tor divider between VDD25 the RCONFIG pin and SGND:
path voltage pickup between these components and the
SGND pin of the IC.
DESIGN EXAMPLE
1. VOUT0_CFG, R
= 10k, R
= 15.8k
TOP
BOTTOM
As a design example for a two channel medium current
2. VTRIM0_CFG, Open
3. VOUT1_CFG, R = 24.9k, R
regulator,assumeV =12Vnominal,V =20Vmaximum,
IN
IN
= 11.3k
BOTTOM
TOP
V
= 3.3V, V
= 1.8V, I = 15A and f = 500kHz
OUT0
OUT1
MAX0,1
4. VTRIM1_CFG, R
= Open, R
= 0Ω
(see Figure 27).
TOP
BOTTOM
The frequency and phase are set by NVM or by setting
3880fc
57
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
the resistor divider between VDD25 FREQ_CFG and SGND
VOUT
1.8V
• f 20V 500kHz
tON(MIN)
=
=
=180ns
with R
= 20k and R
= 12.7k. The address is set
TOP
BOTTOM
V
(
)
IN(MAX)
to XF where X is the MSB stored in NVM.
The following parameters are set as a percentage of the
output voltage if the resistor configuration pins are used
to determined output voltage:
The Vishay IHLP4040DZ-11 1µH (2.3mΩ DCR
at 25°C)
TYP
channel0andtheVishayIHLP4040DZ-110.56µH(1.61mΩ
DCR at 25°C) channel 1 are chosen.
TYP
n
VOUT_OV_FAULT_LIMIT.................................... +10%
Assuming the temperature measurement of the inductor
n
VOUT_OV_WARN.............................................. +7.5%
temperatureisaccurateandC1issetto0.2µF, R isinfinite
D
n
VOUT_MAX....................................................... +7.5%
and removed from the equations.
n
VOUT_MARGIN_HI..............................................+5%
L
1µH
n
POWER_GOOD_ON .............................................–7%
R0=
=
= 2k
DCR at 25°C •C1 2.3mΩ•0.22µF
n
POWER_GOOD_OFF............................................–8%
n
VOUT_MARGIN_LO.............................................–5%
The maximum power loss in R0 is related to the duty
cycle, and will occur in continuous mode at the maximum
input voltage:
n
VOUT_UV_WARN..............................................–6.5%
n
VOUT_UV_FAULT_LIMIT......................................–7%
All other user defined parameters must be programmed
into the NVM. The GUI can be utilized to quickly set up
the part with the desired operating parameters.
V
IN(MAX) – VOUT • V
(
)
OUT
PLOSSR0=
R1
20–3.3 •3.3
The inductance values are based on a 35% maximum
ripple current assumption (5.25A for each channel). The
highest value of ripple current occurs at the maximum
input voltage:
(
)
=
= 27.55mW
2k
The respective values for channel 1 are R1 = 2k, R2 is
open and P R1 = 20.73mW.
LOSS
VOUT
f • ∆IL(MAX)
VOUT
The current limit will be set 20% higher than the peak
value to assure variation in components and noise in the
system do not limit the average current.
L =
1–
V
IN(MAX)
Channel 0 will require 1.05µH and channel 1 will require
0.624µH. Theneareststandardvaluesare1µHand0.68µH
respectively. At the nominal input the ripple will be:
V
= I
• R
= 17.39A • 2.5mΩ = 43mV
DCR(MAX)
ILIMIT
PEAK
TheclosestV
settingis42.9mVor46.4mV.Thevalues
ILIMIT
are entered with the IOUT_OC_FAULT_LIMIT command.
Based on expected variation and measurement in the lab
across the sense capacitor the user can determine the
VOUT
f •L
VOUT
∆IL(NOM)
=
1–
V
IN(NOM)
optimal setting. For channel 1 the V
The closest value Iis 28.6mV.
value is 28.6mV.
ILIMT
Channel 0 will have 4.79A (32%) ripple, and channel 1 will
have 5.5A (30%) ripple. The peak inductor current will be
the maximum DC value plus one-half the ripple current
or 17.39A for channel 0 and 17.75A for channel 1. The
minimum on time occurs on channel 1 at the maximum
The power dissipation on the top side MOSFET can be
easilyestimated.ChooseaRENESASRJK0305DPBtopside
MOSFET. R
= 10mΩ, C
= 75pF. At maximum
DS(ON)
MILLER
input voltage with T estimated = 50°C and a bottom side
MOSFET a RENESAS RJK0330DPB, R = 3mΩ:
V , and should not be less than 90ns:
IN
DS(ON)
3880fc
58
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
at temperature assuming only channel 0 or 1 is on. C
OUT
3.3V
20V
2
PMAIN
=
• 17.39 •1+ 0.005 50°C–25°C
(
)
(
)
(
)
is chosen with an ESR of 0.006Ω for low output ripple.
The output ripple in continuous mode will be highest at
the maximum input voltage. The output voltage ripple
due to ESR is
1
1
2
• 0.006Ω+ 20V 8.695A •
+
(
) (
)
5–2.3 2.3
75pF 500kHz = 0.386W
)(
(
)
V
= R(∆I ) = 0.006Ω • 5.5A = 33mV.
ORIPPLE
L
The loss in the bottom side MOSFET is:
2
CONNECTING THE USB TO THE I C/SMBus/PMBus
CONTROLLER TO THE LTC3880 IN SYSTEM
20V –3.3V
(
)
2
PSYNC
=
• 17.39A •
(
)
2
20V
The LTC USB to I C/SMBus/PMBus controller can be
interfacedtotheLTC3880ontheuser’sboardforprogram-
ming, telemetry and system debug. The controller, when
usedinconjunctionwithLTpowerPlay,providesapowerful
way to debug an entire power system. Faults are quickly
diagnosed using telemetry, fault status registers and the
fault log. The final configuration can be quickly developed
and stored to the LTC3880 EEPROM.
1+ 0.005 50°C–25°C •0.001Ω
(
)
(
)
= 0.312W
2
Both MOSFETS have I R losses while the P
equation
MAIN
includes an additional term for transition losses, which
are highest at high input voltages.
C is chosen for an RMS current rating of:
IN
Figure 28 illustrates the application schematic for pow-
ering, programming and communication with one or
more LTC3880s via the LTC I2C/SMBus/PMBus controller
regardless of whether or not system power is present. If
1/2
17.39
20
= 6.5A
CIN Required IRMS
=
3.3 • 20–3.3
) (
(
)
V
IN
LTC
CONTROLLER
HEADER
100k
100k
V
V
IN
ISOLATED 3.3V
V
DD33
DD25
TP0101K
SDA
SCL
1µF
1µF
LTC3880
10k
10k
SDA
SCL
WP SGND
TO LTC DC1613
2
USB TO I C/SMBus/PMBus
CONTROLLER
V
V
IN
V
DD33
DD25
TP0101K
1µF
1µF
LTC3880
SDA
SCL
WP SGND
VGS MAX ON THE TP0101K IS 8V IF V > 16V
IN
CHANGE THE RESISTOR DIVIDER ON THE PFET GATE
3880 F28
Figure 28ꢀ LTC Controller Connection
3880fc
59
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
system power is not present the dongle will power the
LTC3880 through the VDD33 supply pin. To initialize the
part when VIN is not applied and the VDD33 pin is pow-
ered use global address 5B command 0xBD data 0x2B
followed by address 5B command 0xBD data 0xC4. The
part can now be communicated with, and the project file
updated.TowritetheupdatedprojectfiletotheNVMissue
a STORE_USER_ALL command. When VIN is applied,
a MFR_RESET must be issued to allow the PWM to be
enabled and valid ADCs to be read.
tion in the absence of system power. If VIN is applied the
dongle will not supply the LTC3880s on the board. It is
recommendedtheRUNpinsbeheldlowtoavoidproviding
power to the load until the part is fully configured.
2
The LTC controller I C connections are optoisolated from
the PC USB. The 3.3V from the controller and the LTC3880
V
pin must be driven to each LTC3880 with a separate
DD33
PFET. If V is not applied, the V
pins can be in parallel
IN
DD33
because the on-chip LDO is off. The controller 3.3V cur-
rent limit is 100mA but typical V currents are under
DD33
Becauseofthecontrollerslimitedcurrentsourcingcapabil-
ity, only the LTC3880s, their associated pull-up resistors
15mA. The V
does back drive the INTV /EXTV pin.
DD33 CC CC
Normally this is not an issue if V is open.
IN
2
and the I C pull-up resistors should be powered from the
2
ORed 3.3V supply. In addition any device sharing the I C
LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL
POWER
bus connections with the LTC3880 should not have body
diodes between the SDA/SCL pins and their respective
LTpowerPlay is a powerful Windows-based development
V
DD
node because this will interfere with bus communica-
Figure 29
3880fc
60
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
Two distinct parallel blocks manage command buffering
and command processing (fetch, convert, and execute)
to ensure the last data written to any command is never
lost. Command data buffering handles incoming PMBus
writes by storing the command data to the Write Com-
mandDataBufferandmarkingthesecommandsforfuture
processing. The internal processor runs in parallel and
handles the sometimes slower task of fetching, convert-
ing and executing commands marked for processing.
environment that supports Linear Technology digital
power ICs including the LTC3880. The software supports
a variety of different tasks. LTpowerPlay can be used to
evaluate Linear Technology ICs by connecting to a demo
board or the user application. LTpowerPlay can also be
used in an offline mode (with no hardware present) in
order to build multiple IC configuration files that can be
saved and re-loaded at a later time. LTpowerPlay provides
unprecedenteddiagnosticanddebugfeatures.Itbecomes
a valuable diagnostic tool during board bring-up to pro-
gram or tweak the power system or to diagnose power
issues when bring up rails. LTpowerPlay utilizes Linear
Some computationally intensive commands (e.g., timing
parameters, temperatures, voltages and currents) have
internalprocessorexecutiontimesthatmaybelongrelative
toPMBustiming.Ifthepartisbusyprocessingacommand,
and new command(s) arrive, execution may be delayed
or processed in a different order than received. The part
indicateswheninternalcalculationsareinprocessviabit5
of MFR_COMMON (‘calculations not pending’). When the
part is busy calculating, bit 5 is cleared. When this bit is
set, the part is ready for another command. An example
polling loop is provided in Figure 30 which ensures that
commands are processed in order while simplifying error
handling routines.
2
Technology’s USB-to-I C/SMBus/PMBus controller to
communication with one of the many potential targets
including the DC1590B-A/B demo board, the DC1709A
socketed programming board, or a customer target
system. The software also provides an automatic update
feature to keep the revisions current with the latest set of
device drivers and documentation. A great deal of context
sensitive help is available with LTpowerPlay along with
severaltutorialdemos.Completeinformationisavailableat
http://www.linear.com/ltpowerplay.
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on part configuration it may either
NACK the command or return all ones (0xFF) for reads. It
may also generate a BUSY fault and ALERT notification,
or stretch the SCL clock low. For more information refer
to PMBus Specification v1.1, Part II, Section 10.8.7 and
SMBusv2.0section4.3.3.Clockstretchingcanbeenabled
by asserting bit 1 of MFR_CONFIG_ALL_LTC3880. Clock
stretching will only occur if enabled and the bus com-
munication speed exceeds 100kHz.
PMBus COMMUNICATION AND COMMAND
PROCESSING
The LTC3880/LTC3880-1 have a one deep buffer to hold
the last data written for each supported command prior
to processing as shown in Figure 30; Write Command
Data Processing. When the part receives a new command
from the bus, it copies the data into the Write Command
Data Buffer, indicates to the internal processor that this
command data needs to be fetched, and converts the
command to its internal format so that it can be executed.
CMD
WRITE COMMAND
DATA BUFFER
PMBus busy protocols are well accepted standards, but
can make writing system level software somewhat com-
plex. The part provides three ‘hand shaking’ status bits
which reduce complexity while enabling robust system
level communication.
PMBus
WRITE
DECODER
INTERNAL
PAGE
0x00
0x21
PROCESSOR
•
•
•
CMDS
FETCH,
CONVERT
DATA
AND
EXECUTE
DATA
MUX
VOUT_COMMAND
•
•
•
The three hand shaking status bits are in the MFR_
COMMON register. When the part is busy executing an
internal operation, it will clear bit 6 of MFR_COMMON
(‘chip not busy’). When the part is busy specifically be-
0xFD
MFR_RESET
x1
S
R
CALCULATIONS
PENDING
3880 F30
cause it is in a transitional VOUT state (margining hi/lo,
Figure 30ꢀ Write Command Data Processing
3880fc
61
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
applicaTions inFormaTion
power off/on, moving to a new output voltage set point,
etc.) it will clear bit 4 of MFR_COMMON (‘output not in
transition’).Wheninternalcalculationsareinprocess,the
part will clear bit 5 of MFR_COMMON (‘calculations not
pending’). These three status bits can be polled with a
PMBus read byte of the MFR_COMMON register until all
three bits are set. A command immediately following the
status bits being set will be accepted without NACKing or
It is recommended that all command writes (write byte,
write word, etc.) be preceded with a polling loop to avoid
the extra complexity of dealing with busy behavior and
unwanted ALERTB notification. A simple way to achieve
thisistocreateaSAFE_WRITE_BYTE()andSAFE_WRITE_
WORD()subroutine.Theabovepollingmechanismallows
your software to remain clean and simple while robustly
communicating with the part. For a detailed discussion
of these topics and other special cases please refer to
the application note section located at www.linear.com/
designtools/app_notes.
// wait until bits 6, 5, and 4 of MFR_COMMON are all set
do
{
mfrCommonValue = PMBUS_READ_BYTE(0xEF);
partReady = (mfrCommonValue & 0x68) == 0x68;
}while(!partReady)
When communicating using bus speeds at or below
100kHz, the polling mechanism shown here provides a
simplesolutionthatensuresrobustcommunicationwithout
clock stretching. At bus speeds in excess of 100kHz, it is
strongly recommended that the part be configured to en-
able clock stretching. This requires a PMBus master that
supports clock stretching. System software that detects
and properly recovers from the standard PMBus NACK/
BUSYfaultsasdescribedinthePMBusSpecificationv1.1,
Part II, Section 10.8.7 is required to communicate above
100kHz without clock stretching.
// now the part is ready to receive the next command
PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_COMMAND to 2V
Figure 31ꢀ Example of a Command Write of VOUT_COMMAND
generating a BUSY fault/ALERT notification. The part can
NACK commands for other reasons, however, as required
by the PMBus spec (for instance, an invalid command or
data). An example of a robust command write algorithm
fortheVOUT_COMMANDregisterisprovidedinFigure31.
3880fc
62
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
ADDRESSING AND WRITE PROTECT
CMD
DATA
PAGED FORMAT
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
UNITS
NVM
PAGE
0x00 Channel or page currently selected for any
command that supports paging.
R/W Byte
N
Reg
Reg
0x00
WRITE_PROTECT
0x10 Level of protection provided by the device
against accidental changes.
R/W Byte
N
Y
0x00
2
MFR_ADDRESS
0xE6 Sets the 7-bit I C address byte.
R/W Byte
R/W Byte
N
Y
Y
Reg
Reg
Reg
Y
Y
Y
0x4F
0x80
0x80
MFR_CHANNEL_ADDRESS
MFR_RAIL_ADDRESS
0xD8 Address to the PAGE activated channel
0xFA Common address for PolyPhase outputs to R/W Byte
adjust common parameters.
PAGE
The page command provides the ability to configure, control and monitor both outputs through only one physical ad-
dress. Each PAGE contains the Operating Memory for each output.
Pages 0x00 and 0x01 correspond to channel 0 and channel 1, respectively, in this device.
Setting the page to 0xFF means that the commands are to applied to both outputs. Performing READ commands with
PAGE set to 0xFF will return the same value as PAGE 0. When PAGE is set to 0xFF there are no restrictions on R/W
commands.
This command has one data byte.
WRITE_PROTECT
The WRITE_PROTECT command is used to control writing to the LTC3880 device. This command does not indicate the
status of the WP pin which is defined in the MFR_COMMON command. The WP pin takes precedence over the value
of this command unless the WRITE_PROTECT command is more stringent.
BYTE MEANING
0x80 Disable all writes except to the WRITE_PROTECT, PAGE_MFR_
EE_UNLOCK and STORE_USER_ALL command
0x40 Disable all writes except to the WRITE_PROTECT, PAGE,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, STORE_USER_ALL,
OPERATION and CLEAR_FAULTS command. ndividual fault
bits can be cleared by writing a 1 to the respective bits in the
STATUS registers.
0x20 Disable all writes except to the WRITE_PROTECT, OPERATION,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, CLEAR_FAULTS,
PAGE, ON_OFF_CONFIG, VOUT_COMMAND and STORE_USER_
ALL. Individual fault bits can be cleared by writing a 1 to the
respective bits in the STATUS registers.
0x10 Reserved, must be 0
0x08 Reserved, must be 0
0x04 Reserved, must be 0
0x02 Reserved, must be 0
0x01 Reserved, must be 0
Enable writes to all commands when WRITE_PROTECT is set to 0x00.
This command has one data byte.
3880fc
63
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
If WP pin is high, PAGE, OPERATION, MFR_CLEAR_PEAKS, MFR_EE_UNLOCK and CLEAR_FAULTS commands are
supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS registers.
MFR_ADDRESS
The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device.
Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B,
cannot be deactivated. If RCONFIG is set to ignore, the ASEL pin is still used to determine the LSB of the channel ad-
dress. If the ASEL pin is open, the LTC3880 will use the address value stored in NVM.
This command has one data byte.
MFR_CHANNEL_ADDRESS
The MFR_CHANNEL_ADDRESS command enables direct device address access to the PAGE activated channel. The
value of this command should be unique on the PMBus and should not be the same as another channel or device.
If this command is not set to 0x80, a status condition specific to this channel will result in the Alert Response Address
(ARA) value to be equal to the value of the MFR_CHANNEL_ADDRESS command.
Setting this command to a value of 0x80 disables channel device addressing for the channel.
This command has one data byte.
MFR_RAIL_ADDRESS
The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value
of this command should be common to all devices attached to a single power supply rail.
The user should only perform command writes to this address. If a read is performed from this address and the rail
devices do not respond with EXACTLY the same value, the LTC3880 will detect bus contention and set a CML com-
munications fault.
Setting this command to a value of 0x80 disables rail device addressing for the channel.
This command has one data byte.
3880fc
64
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
GENERAL CONFIGURATION REGISTERS
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
MFR_CHAN_CONFIG_LTC3880
MFR_CONFIG_ALL_LTC3880
0xD0
0xD1
Configuration bits that are channel specific. R/W Byte
Y
N
Reg
Reg
Y
Y
0x1F
0x09
Configuration bits that are common to all
pages.
R/W Byte
MFR_CHAN_CONFIG_LTC3880
General purpose configuration command common to multiple LTC products.
BIT MEANING
7
6
5
4
3
Reserved
Reserved
Reserved
Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF
Short Cycle. When asserted the output will immediate off if commanded ON while waiting for TOFF_DELAY or TOFF_FALL. TOFF_MIN of 120mS
is honored then the part will command ON.
2
1
SHARE_CLOCK control, if SHARE_CLOCK is held low, the output is disabled
No GPIO ALERT, ALERT is not pulled low if GPIO is pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are propagated
on GPIO
0
Disables the VOUT decay value requirement for MFR_RETRY_TIME processing. When this bit is set to a 0, the output must decay to less than
12.5% of the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from high to low
to high.
This command has one data byte.
MFR_CONFIG_ALL_LTC3880
General purpose configuration command common to multiple LTC products
BIT MEANING
7
6
5
4
3
2
Enable Fault Logging
Ignore Resistor Configuration Pins
Reserved, set to 1
Reserved
Mask PLL Unlock Fault
A valid PEC required for PMBus writes to be accepted. If this bit is not
set, the part will accept commands with invalid PEC.
1
0
Enable the use of PMBus clock stretching
Enables a low to high transition on either RUN pin to issue a
CLEAR_FAULTS command
This command has one data byte.
3880fc
65
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
ON/OFF/MARGIN
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
ON_OFF_CONFIG
OPERATION
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
0x02 RUN pin and PMBus bus on/off command configuration.
R/W Byte
R/W Byte
Y
Y
Reg
Reg
Y
Y
0x1E
0x80
0x01 Operating mode control. On/off, margin high and margin
low.
MFR_RESET
0xFD Commanded reset without requiring a power-down.
Send Byte
N
NA
ON_OFF_CONFIG
The ON_OFF_CONFIG command configures the combination of RUNn pin input and serial bus commands needed to
turn the unit on and off. This includes how the unit responds when power is applied.
The only bits allowed to be changed are as follows:
3: Controls how the unit responds to commands received via the serial bus
0: RUN pin action when commanding the unit to turn off. If bit 0 is set to one, the part will stop transferring power to
the output stage as fast as possible. This will have the effect of the load discharging the output capacitor. Setting
bit 0 to a zero will cause the regulator to use the programmed turn-off delay and fall times. If the part is in continu-
ous mode, the programmed turn-off response may pull the output to zero volts considerably faster than removing
power immediately from the load.
Changing the value of bits 4, 2 or 1, will generate a CML fault.
This command has one data byte.
Table 3ꢀ ON_OFF_CONFIG Detailed Register Information
ON_OFF_CONFIG Data Contents
BITS(S) SYMBOL
OPERATION
b[7:5] Reserved
Don’t care. Always returns 0.
b[3] On_off_config_use_pmbus
Controls how the unit responds to commands received via the serial bus.
0: Unit ignores the Operation command b[7:6].
1: Unit responds to Operation command b[7:6]. The unit also requires the RUNn pin to be asserted for the
unit to start.
b[0] On_off_config_control_fast_off RUNn pin turn off action when commanding the unit to turn off.
0: Use the programmed TOFF_DELAY.
1: Turn off the output and stop transferring energy as quickly as possible. The device does not sink current
in order to decrease the output voltage fall time.
Note: A high on the RUN pin is always required to start power conversion. Power conversion will always stop with a low on RUN.
3880fc
66
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
OPERATION
The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUNn pins. It
is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOLTAGEs. The unit stays in
the commanded operating mode until a subsequent OPERATION command or change in the state of the RUNn pin
instructs the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next RESET
or POWER_ON cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed to
MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE.
Margin High (Ignore Faults) and Margin Low (Ignore Faults) operations are not supported by the LTC3880.
The part defaults to the ON state.
This command has one data byte.
Table 4ꢀ OPERATION Command Detail Register OPERATION Data Contents
When On_Off_Config_Use_PMBus Enables Operation_Control
SYMBOL
BITS
Action
Value
Turn off immediately
Turn on
0x00
0x80
0x98
0xA8
0x40
FUNCTION Margin Low
Margin High
Sequence off
OPERATION Data Contents When On_Off_Config is Configured Such That
OPERATION Command Is Not Used to Command Channel On or Off
SYMBOL
BITS
Action
Value
Output at Nominal
0x80
0x98
0xA8
FUNCTION Margin Low
Margin High
Note: Attempts to write a reserved value will cause a CML fault.
MFR_RESET
This command provides a means by which the user can perform a reset of the LTC3880.
This write-only command has no data bytes.
3880fc
67
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
PWM CONFIG
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM VALUE
MFR_PWM_MODE_
LTC3880
0xD4
0xF5
0x33
Configuration for the PWM engine of each channel
R/W Byte
Y
N
N
Reg
Reg
L11
Y
Y
Y
0xC2
0x10
MFR_PWM_CONFIG_
LTC3880
Set numerous parameters for the DC/DC controller
including phasing.
R/W Byte
FREQUENCY_SWITCH
Switching frequency of the controller
R/W Word
kHz
350
0xFABC
MFR_PWM_MODE_LTC3880
TheMFR_PWM_MODE_LTC3880commandallowstheusertoprogramthePWMcontrollertouseBurstModeoperation,
discontinuous (pulse-skipping mode), or forced continuous conduction mode.
BIT
MEANING
7
Use High Range of I
LIMIT
0 – Low Current Range
1 – High Current Range
6
5
4
3
2
Enable Servo Mode
Reserved
Reserved
Reserved
Reserved
Bit[1:0] Mode
00b
01b
10b
Discontinuous
Burst Mode Operation
Forced Continuous
Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of this
command.
Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command.
Changing this bit value changes the PWM loop gain and compensation. Changing this bit value whenever an output is
active may have detrimental system results.
Bit [6] The LTC3880 will not servo while the part is OFF, ramping on or ramping off. When set to a one, the output servo
is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC
and the VOUT_COMMAND (or the appropriate margined value).
This command has one data byte.
MFR_PWM_CONFIG_LTC3880
The MFR_PWM_CONFIG_LTC3880 command sets the switching frequency phase offset with respect to the falling edge
of the SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or
the part must be commanded off. If the part is in the RUN state and this command is written, the command will be
ignored and a BUSY fault will be asserted. Bits 5 and 6 of this command affect the loop gain of the respective channels
which may require modifications to the external compensation network.
3880fc
68
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
BIT
MEANING
7
Reserved, set to 0.
6
If V
RANGE = 1, the maximum output voltage
OUT0
for V0 is 2.75V. If RANGE = 0, the maximum output
voltage for V0 is 4.096V.
5
4
If V
RANGE = 1, the maximum output voltage
OUT1
for V1 is 2.75V. If RANGE = 0, the maximum output
voltage for V1 is 5.5V.
Share Clock Enable : If this bit is 1, the
SHARE_CLK pin will not be released until
V
> VIN_ON. The SHARE_CLK pin will be
IN
pulled low when V < VIN_OFF. If this bit is 0, the
IN
SHARE_CLK pin will not be pulled low when VIN <
VIN_OFF except for the initial application of VIN.
3
BIT [2:0]
000b
001b
010b
011b
100b
101b
110b
Reserved
CHANNEL 0 (DEGREES) CHANNEL 1 (DEGREES)
0
90
0
180
270
240
120
240
240
300
0
120
60
120
This command has one data byte.
FREQUENCY_SWITCH
The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of a PMBus device.
Supported Frequencies:
VALUE [15:0]
0x0000
0xF3E8
RESULTING FREQUENCY (TYP)
External Oscillator
250kHz
0xFABC
0xFB52
0xFBE8
0x023F
350kHz
425kHz
500kHz
575kHz
0x028A
0x02EE
0x03E8
650kHz
750kHz
1000kHz
The part must be in the OFF state to process this command. Either the RUN pins must be low or the part must be
commanded off. If the part is in the RUN state and this command is written, the command will be ignored and a BUSY
fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be
detected as the PLL locks onto the new frequency.
This command has two data bytes and is formatted in Linear_5s_11s format.
3880fc
69
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
VOLTAGE
Input Voltage and Limits
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM VALUE
VIN_OV_FAULT_ LIMIT
0x55
0x58
0x35
0x36
Input supply overvoltage fault limit.
R/W Word
N
N
N
N
L11
L11
L11
L11
V
V
V
V
Y
Y
Y
Y
15.5
0xD3E0
VIN_UV_WARN_LIMIT
VIN_ON
Input supply undervoltage warning limit.
R/W Word
R/W Word
R/W Word
6.3
0xCB26
Input voltage at which the unit should start power
conversion.
6.5
0xCB40
VIN_OFF
Input voltage at which the unit should stop power
conversion.
6.0
0xCB00
VIN_OV_FAULT_LIMIT
The VIN_OV_FAULT_LIMIT command sets the value of the measured input voltage, in volts, that causes an input
overvoltage fault. The fault is detected with the A/D converter resulting in latency up to 100ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
VIN_UV_WARN_LIMIT
The VIN_UV_WARN_LIMIT command sets the value of the input voltage that causes an input undervoltage warning.
The warning is detected with the A/D converter resulting in latency up to 100ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
VIN_ON
The VIN_ON command sets the input voltage, in volts, at which the unit should start power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
VIN_OFF
The VIN_OFF command sets the input voltage, in volts, at which the unit should stop power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
3880fc
70
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
Output Voltage and Limits
DATA
DEFAULT
VALUE
2
0x14
4.096 Ch0
0x4189
5.5 Ch1
0x5800
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
R Byte
PAGED FORMAT UNITS NVM
Y
–12
–2
VOUT_MODE
0x20
Output voltage format and exponent (2 ).
Reg
L16
VOUT_MAX
0x24
Upper limit on the commanded output voltage R/W Word
including VOUT_MARGIN_HIGH.
Y
V
Y
VOUT_OV_FAULT_ LIMIT
VOUT_OV_WARN_ LIMIT
VOUT_MARGIN_HIGH
VOUT_COMMAND
0x40
0x42
0x25
0x21
0x26
0x43
0x44
0x5E
0x5F
0xA5
Output overvoltage fault limit.
R/W Word
R/W Word
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
L16
L16
L16
L16
L16
L16
L16
L16
L16
L16
V
V
V
V
V
V
V
V
V
V
Y
Y
Y
Y
Y
Y
Y
Y
Y
1.1
0x119A
Output overvoltage warning limit.
1.075
0x1133
1.05
0x10CD
1.0
0x1000
0.95
0x0F33
0.925
0x0ECD
0.9
0x0E66
0.93
0x0EE1
0.92
0x0EB8
Margin high output voltage set point. Must be R/W Word
greater than VOUT_COMMAND.
Nominal output voltage set point.
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R Word
VOUT_MARGIN_LOW
VOUT_UV_WARN_ LIMIT
VOUT_UV_FAULT_ LIMIT
POWER_GOOD_ON
Margin low output voltage set point. Must be
less than VOUT_COMMAND.
Output undervoltage warning limit.
Output undervoltage fault limit.
Output voltage at or above which a power
good should be asserted.
Output voltage at or below which a power
good should be de-asserted.
Maximum allowed voltage command
including VOUT_OV_FAULT_LIMIT.
POWER_GOOD_OFF
MFR_VOUT_MAX
4.096 Ch0
5.5 Ch1
VOUT_MODE
The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode
(only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write
commands.
This read-only command has one data byte
VOUT_MAX
The VOUT_MAX command sets an upper limit on the output voltage, including VOUT_MARGIN_HIGH, the unit can
command regardless of any other commands or combinations.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_OV_FAULT_LIMIT
The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured at the sense pins, in volts, which
causes an output overvoltage fault.
If the VOUT_OV_FAULT_LIMIT is modified and the switcher is active, allow 10ms after the command is modified to
assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and 6 of
3880fc
71
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
MFR_COMMON. Either bit is low if the part is busy. If this wait time is not met, and the VOUT_COMMAND is modified
above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable behavior and
possible damage to the switcher.
If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN, the GPIO pin will not assert if VOUT_OV_FAULT is propa-
gated. The LTC3880 will pull the TG low and assert the BG bit as soon as the overvoltage condition is detected.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_OV_WARN_LIMIT
The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured at the sense pins, in volts, which
causes an output voltage high warning. The READ_VOUT value will be used to determine if this limit has been exceeded.
In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin
This condition is detected by the ADC so the response time may be up to 100ms.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_MARGIN_HIGH
The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in volts,
when the OPERATION command is set to “Margin High”. The value must be greater than VOUT_COMMAND.
ThiscommandwillnotbeactedonduringTON_RISEandTOFF_FALLoutputsequencing.TheVOUT_TRANSITION_RATE
will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_COMMAND
The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts.
ThiscommandwillnotbeactedonduringTON_RISEandTOFF_FALLoutputsequencing.TheVOUT_TRANSITION_RATE
will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_MARGIN_LOW
The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts,
when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND.
ThiscommandwillnotbeactedonduringTON_RISEandTOFF_FALLoutputsequencing.TheVOUT_TRANSITION_RATE
will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
3880fc
72
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
VOUT_UV_WARN_LIMIT
The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured at the sense pins, in volts,
which causes an output voltage low warning.
In response to the VOUT_UV_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin
This condition is detected by the ADC so the response time may be up to 100ms.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_UV_FAULT_LIMIT
The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured at the sense pins, in volts,
which causes an output undervoltage fault.
This command has two data bytes and is formatted in Linear_16u format.
POWER_GOOD_ON
The POWER_GOOD_ON command sets the output voltage at which the POWER_GOOD signal should be asserted.
POWER_GOOD_ON is detected with an A/D read resulting in latency of up to 100ms.
This command has two data bytes and is formatted in Linear_16u format.
POWER_GOOD_OFF
The POWER_GOOD_OFF command sets the output voltage at which the POWER_GOOD signal should be negated.
POWER_GOOD_OFF is detected with an A/D read resulting in latency of up to 100ms. At initial power up the output of
this pin will be high even though the state should be low. If the proper state at power-up is required, place a Schottky
diode between RUN and GPIO. The Anode must be tied to GPIO and the Cathode to RUN.
ThePOWER_GOOD_ONstatusismaskedfrominitiatinganALERT. ThePOWER_GOODstatusbitintheSTATUS_WORD
command is always reflective of VOUT wrt. the POWER_GOOD threshold.
This command has two data bytes and is formatted in Linear_16u format.
MFR_VOUT_MAX
The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel including VOUT_OV_
FAULT_LIMIT. If the output voltages are set to high range (Bits 5 and 6 of MFR_PWM_CONFIG_LTC3880 set to a 0)
MFR_VOUT_MAX for channel 0 is 4.096V and MFR_VOUT_MAX for channel 1 is 5.5V. If the output voltages are set to
low range (Bits 5 and 6 of MFR_PWM_CONFIG_LTC3880 set to a 1) the MFR_VOUT_MAX for both channels is 2.75V.
Entering VOUT_COMMAND values greater than this will result in a CML fault and the output voltage setting will be
clamped to the maximum level.
This read-only command has 2 data bytes and is formatted in Linear_16u format.
3880fc
73
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
CURRENT
Input Current Calibration
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0xE9 Coefficient used to add to the input current to
account for the IQ of the part.
TYPE
PAGED FORMAT
UNITS
NVM
MFR_IIN_OFFSET
R/W
Word
Y
L11
A
Y
0.050
0x9333
MFR_IIN_OFFSET
The MFR_IIN_OFFSET command allows the user to set an input current representing the quiescent current of each
channel. For accurate results at low output current, the part should be in continuous conduction mode.
This command has 2 data bytes and is formatted in Linear_5s_11s format.
Output Current Calibration
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
IOUT_CAL_GAIN
0x38 The ratio of the voltage at the current sense pins R/W Word
to the sensed current. For devices using a fixed
current sense resistor, it is the resistance value
in mΩ.
Y
L11
mΩ
Y
1.8
0xBB9A
MFR_IOUT_CAL_GAIN_TC
0xF6 Temperature coefficient of the current sensing
element.
R/W Word
Y
CF
Y
3900
0x0F3C
IOUT_CAL_GAIN
The IOUT_CAL_GAIN command is used to set the resistance value of the current sense resistor in milliohms. (see
also MFR_IOUT_CAL_GAIN_TC).
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_IOUT_CAL_GAIN_TC
TheMFR_IOUT_CAL_GAIN_TCcommandallowstheusertoprogramthetemperaturecoefficientoftheIOUT_CAL_GAIN
sense resistor or inductor DCR in ppm/°C.
This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 •
–6
10 . Nominal temperature is 27°C. The IOUT_CAL_GAIN is multiplied by:
[1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1-27)]. DCR sensing will have a typical value of 3900.
The IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including: READ_IOUT, READ_IIN,
IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT.
Input Current
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0x5D Input overcurrent warning limit.
TYPE
PAGED FORMAT UNITS
NVM
IIN_OC_WARN_LIMIT
R/W Word
N
L11
A
Y
10.0
0xD280
3880fc
74
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
IIN_OC_WARN_LIMIT
The IIN_OC_WARN_LIMIT command sets the value of the input current, in amperes, that causes a warning indicating
the input current is high. The READ_IIN value will be used to determine if this limit has been exceeded.
In response to the IIN_OC_WARN_LIMIT being exceeded, the device:
• Sets the OTHER bit in the STATUS_BYTE
• Sets the INPUT bit in the upper byte of the STATUS_WORD
• Sets the IIN Overcurrent Warning bit in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin
This condition is detected by the ADC so the response time may be up to 100ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
Output Current
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
IOUT_OC_FAULT_LIMIT
0x46
Output overcurrent fault limit.
R/W Word
Y
L11
L11
A
Y
29.75
0xDBB8
IOUT_OC_WARN_LIMIT
0x4A
Output overcurrent warning limit.
R/W Word
Y
A
Y
20.0
0xDA80
IOUT_OC_FAULT_LIMIT
The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in amperes. When the controller
is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The programmed overcurrent
fault limit value is rounded up to the nearest one of the following set of discrete values:
25mV/IOUT_CAL_GAIN
28.6mV/IOUT_CAL_GAIN
32.1mV/IOUT_CAL_GAIN
35.7mV/IOUT_CAL_GAIN
39.3mV/IOUT_CAL_GAIN
42.9mV/IOUT_CAL_GAIN
46.4mV/IOUT_CAL_GAIN
50mV/IOUT_CAL_GAIN
37.5mV/IOUT_CAL_GAIN
42.9mV/IOUT_CAL_GAIN
48.2mV/IOUT_CAL_GAIN
53.6mV/IOUT_CAL_GAIN
58.9mV/IOUT_CAL_GAIN
64.3mV/IOUT_CAL_GAIN
69.6mV/IOUT_CAL_GAIN
75mV/IOUT_CAL_GAIN
Low Range (1.5x Nominal Loop Gain)
MFR_PWM_MODE_LTC3880 [7]=0
High Range (Nominal Loop Gain)
MFR_PWM_MODE_LTC3880 [7]=1
Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output
3880fc
75
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation:
IOUT_OC_FAULT_LIMIT = IOUT_CAL_GAIN • (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)).
The LTpowerPlay GUI automatically convert the voltages to currents.
The I
range is set with bit 7 of the MFR_PWM_MODE_LTC3880 command.
OUT
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
This command has two data bytes and is formatted in Linear_5s_11s format.
IOUT_OC_WARN_LIMIT
This command sets the value of the output current that causes an output overcurrent warning in amperes. The
READ_IOUT value will be used to determine if this limit has been exceeded.
In response to the IOUT_OC_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin
This condition is detected by the ADC so the response time may be up to 100ms.
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
This command has two data bytes and is formatted in Linear_5s_11s format
TEMPERATURE
External Temperature Calibration
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM VALUE
MFR_TEMP_1_GAIN
0xF8
Sets the slope of the external temperature
R/W Word
Y
Y
CF
Y
Y
1
sensor.
0x4000
MFR_TEMP_1_OFFSET
0xF9
Sets the offset of the external temperature
sensor with respect to –273.1°C.
R/W Word
L11
C
0
0x8000
MFR_TEMP_1_GAIN
TheMFR_TEMP_1_GAINcommandwillmodifytheslopeoftheexternaltemperaturesensortoaccountfornon-idealities
in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in 16-bit 2’s complement integer. N = 8192 to 32767. The effective
–14
adjustment is N • 2 . The nominal value is 1.
MFR_TEMP_1_OFFSET
The MFR_TEMP_1_OFFSET command will modify the offset of the external temperature sensor to account for non-
idealities in the element and errors associated with the remote sensing of the temperature in the inductor.
3880fc
76
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
This command has two data bytes and is formatted in Linear_5s_11s format. The part starts the calculation with a
value of –273.15 so the default adjustment value is zero.
External Temperature Limits
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
OT_FAULT_LIMIT
0x4F
0x51
0x53
External overtemperature fault limit.
R/W Word
Y
Y
Y
L11
L11
L11
C
C
C
Y
Y
Y
100.0
0xEB20
OT_WARN_LIMIT
UT_FAULT_LIMIT
External overtemperature warning limit.
External undertemperature fault limit.
R/W Word
R/W Word
85.0
0xEAA8
–40.0
0xE580
OT_FAULT_LIMIT
The OT_FAULT_LIMIT command sets the value of the external sense temperature, in degrees Celsius, which causes an
overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.
This condition is detected by the ADC so the response time may be up to 100ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
OT_WARN_LIMIT
The OT_WARN_LIMIT command sets the value of the external sense temperature, in degrees Celsius, which causes an
overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.
In response to the OT_WARN_LIMIT being exceeded, the device:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin.
This condition is detected by the ADC so the response time may be up to 100ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
UT_FAULT_LIMIT
The UT_FAULT_LIMIT command sets the value of the external sense temperature, in degrees Celsius, which causes
an undertemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been
exceeded.
Note: If the temp sensors are not installed, the UT_FAULT_LIMIT can be set to –275°C and UT_FAULT_LIMIT response
set to ignore to avoid ALERT being asserted.
This condition is detected by the ADC so the response time may be up to 100ms.
Values of greater than 0.1V/ms and less than or equal to 1V/ms are recommended. If a transition rate out of this range
is desired, contact the factory for more information.
This command has two data bytes and is formatted in Linear_5s_11s format.
3880fc
77
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
TIMING
Timing—On Sequence/Ramp
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
TON_DELAY
0x60
Time from RUN and/or Operation on to output R/W Word
rail turn-on.
Y
L11
L11
ms
Y
0.0
0x8000
TON_RISE
0x61
Time from when the output starts to rise
until the output voltage reaches the VOUT
commanded value.
R/W Word
Y
ms
Y
8.0
0xD200
TON_MAX_FAULT_LIMIT
VOUT_TRANSITION_RATE
0x62
0x27
Maximum time from V
on for VOUT to R/W Word
Y
Y
L11
L11
ms
Y
Y
10.0
OUT_EN
cross the VOUT_UV_FAULT_LIMIT.
0xD280
Rate the output changes when VOUT
commanded to a new value.
R/W Word
V/ms
0.25
0xAA00
TON_DELAY
The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output
voltage starts to rise. Values from 0ms to 83 seconds are valid.
This command has two data bytes and is formatted in Linear_5s_11s format.
TON_RISE
The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output
enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during
TON_RISE events. If TON_RISE is less than 0.25ms, the LTC3880 digital slope will be bypassed. The output voltage
transition will be controlled by the analog performance of the PWM switcher. The maximum allowed slope is 4V/ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
TON_MAX_FAULT_LIMIT
The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power up
the output without reaching the output undervoltage fault limit.
A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely.
The maximum limit is 83 seconds.
This command has two data bytes and is formatted in Linear_5s_11s format.
VOUT_TRANSITION_RATE
When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the
output voltage to change this command set the rate in V/ms at which the output voltage changes. This commanded
rate of change does not apply when the unit is commanded on or off.
Values of greater than 0.1V/ms are recommended.
This command has two data bytes and is formatted in Linear_5s_11s format.
3880fc
78
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
Timing—Off Sequence/Ramp
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
TOFF_DELAY
0x64
0x65
0x66
Time from RUN and/or Operation off to the start R/W Word
of TOFF_FALL ramp.
Time from when the output starts to fall until the R/W Word
output reaches zero volts.
Y
Y
Y
L11
L11
L11
ms
ms
ms
Y
Y
Y
0.0
0x8000
TOFF_FALL
8.0
0xD200
150
0xF258
TOFF_MAX_WARN_LIMIT
Maximum allowed time, after TOFF_FALL
completed, for the unit to decay below 12.5%.
R/W Word
TOFF_DELAY
The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output
voltage starts to fall. Values from 0 to 83 seconds are valid.
This command is excluded from fault events.
This command has two data bytes and is formatted in Linear_5s_11s format.
TOFF_FALL
The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output volt-
age is commanded to zero. It is the ramp time of the V
DAC. When the V
DAC is zero, the part will three-state.
OUT
OUT
The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part
to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate.
The minimum supported fall time is 0.25ms. A value less than 0.25ms will result in a 0.25ms ramp. The maximum fall
time is 1.3 seconds. The maximum allowed slope is 4V/ms.
In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by
the output capacitance and load current.
This command has two data bytes and is formatted in Linear_5s_11s format.
TOFF_MAX_WARN_LIMIT
The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to turn off
the output until a warning is asserted. The output is considered off when the V
voltage is less than 12.5% of the
OUT
programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete. TOFF_MAX_WARN is not
enabled in VOUT_DECAY is disabled.
A data value of 0ms means that there is no limit and that the unit can attempt to turn off the output voltage indefinitely.
Other than 0, values from 120ms to 524 seconds are valid.
This command has two data bytes and is formatted in Linear_5s_11s format.
Precondition for Restart
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0xDC Delay from actual RUN active edge to virtual
RUN active edge.
TYPE
PAGED FORMAT UNITS
NVM
MFR_RESTART_ DELAY
R/W Word
Y
L11
ms
Y
500
0xFBE8
3880fc
79
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
MFR_RESTART_DELAY
This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length
of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms.
Note: The restart delay is different than the retry delay. The restart delay pulls run low for the specified time, after which
a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_FALL
+ 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time, set
the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_
RESTART_DELAY after the RUN pin is pulled high if the output decay bit 1 is enabled in MFR_CHAN_CONFIG_LTC3880
and the output takes a long time to decay below 12.5% of the programmed value.
This command has two data bytes and is formatted in Linear_5s_11s format.
FAULT RESPONSE
Fault Responses All Faults
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0xDB Retry interval during FAULT retry mode.
TYPE
PAGED FORMAT UNITS NVM
MFR_RETRY_ DELAY
R/W Word
Y
L11
ms
Y
350
0xFABC
MFR_RETRY_DELAY
This command sets the time in milliseconds between restarts if the fault response is to retry the controller at specified
intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has
been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 10µs increments.
Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required
for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is
too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of
MFR_CHAN_CONFIG_LTC3880.
This command has two data bytes and is formatted in Linear_5s_11s format.
Fault Responses Input Voltage
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0x56 Action to be taken by the device when an
input supply overvoltage fault is detected.
TYPE
PAGED FORMAT UNITS NVM
VIN_OV_FAULT_RESPONSE
R/W Byte
Y
Reg
Y
0x80
VIN_OV_FAULT_RESPONSE
The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input overvolt-
age fault. The data byte is in the format given in Table 9.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Set the INPUT bit in the upper byte of the STATUS_WORD
3880fc
80
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
• Sets the VIN Overvoltage Fault bit in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin
This command has one data byte.
Fault Responses Output Voltage
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
VOUT_OV_FAULT_RESPONSE
0x41
0x45
0x63
Action to be taken by the device when an
R/W Byte
Y
Y
Y
Reg
Reg
Reg
Y
Y
Y
0xB8
0xB8
0xB8
output overvoltage fault is detected.
VOUT_UV_FAULT_RESPONSE
Action to be taken by the device when an
output undervoltage fault is detected.
R/W Byte
R/W Byte
TON_MAX_FAULT_
RESPONSE
Action to be taken by the device when a
TON_MAX_FAULT event is detected.
VOUT_OV_FAULT_RESPONSE
The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overvoltage fault. The data byte is in the format given in Table 5.
The device also:
• Sets the VOUT_OV bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin
The only value recognized for this command are:
0x80–The device shuts down (disables the output) and the unit does not attempt to retry. The output remains disabled
until the fault is cleared (PMBus, Part II, Section 10.7).
0xB8–The device shuts down (disables the output) and device attempts retry continuously, without limitation, until
it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault
condition causes the unit to shut down.
0x4n The device shuts down and the unit does not attempt to retry. The output remains disabled until the part is com-
manded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN.
The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
0x78+n The device shuts down and the unit attempts to retry continuously until either the fault condition is cleared
or the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or
removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
Any other value will result in a CML fault and the write will be ignored.
This command has one data byte.
3880fc
81
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
Table 5ꢀ VOUT_OV_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
Part performs OV pull down only (i.e., turns off the top
MOSFET and turns on lower MOSFET while V
VOUT_OV_FAULT)
is >
OUT
For all values of bits [7:6], the LTC3880:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin
01
The PMBus device continues operation for the delay time
specified by bits [2:0] and the delay time unit specified for that
particular fault. If the fault condition is still present at the end of
the delay time, the unit responds as programmed in the Retry
Setting (bits [5:3]).
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
10
11
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
• The output is commanded through the RUNn pin, the
OPERATION command, or the combined action of the RUNn pin
and OPERATION command, to turn off and then to turn back on,
or
Not supported. Writing this value will generate a CML fault.
• Bias power is removed and reapplied to the LTC3880.
Retry Setting
5:3
2:0
000-110 The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
111
The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUNn pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
Delay Time
XXX
The delay time in 10µs increments. This delay time determines
how long the controller continues operating after a fault is
detected. Only valid for deglitched off state
VOUT_UV_FAULT_RESPONSE
The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
undervoltage fault. The data byte is in the format given in Table 6.
The device also:
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT undervoltage fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin
The UV fault and warn are masked until the following criteria are achieved:
1) The TON_MAX_FAULT_LIMIT has been reached
2) The TON_DELAY sequence has completed
3) The TON_RISE sequence has completed
4) The VOUT_UV_FAULT_LIMIT threshold has been reached
5) The IOUT_OC_FAULT_LIMIT is not present
The UV fault and warn are masked whenever the channel is not active.
The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing.
This command has one data byte.
3880fc
82
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
Table 6ꢀ VOUT_UV_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
The PMBus device continues operation without interruption.
(Ignores the fault functionally)
For all values of bits [7:6], the LTC3880:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin
01
The PMBus device continues operation for the delay time
specified by bits [2:0] and the delay time unit specified for
that particular fault. If the fault condition is still present at the
end of the delay time, the unit responds as programmed in the
Retry Setting (bits [5:3]).
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command
10
11
The device shuts down (disables the output) and responds
according to the retry setting in bits [5:3].
• The output is commanded through the RUNn pin, the
OPERATION command, or the combined action of the RUNn pin
and OPERATION command, to turn off and then to turn back on,
or
Not supported. Writing this value will generate a CML fault.
• Bias power is removed and reapplied to the LTC3880
Retry Setting
5:3
2:0
000-110 The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
111
The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUNn pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
Delay Time
XXX
The delay time in 10µs increments. This delay time determines
how long the controller continues operating after a fault is
detected. Only valid for deglitched off state.
TON_MAX_FAULT_RESPONSE
The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX
fault. The data byte is in the format given in Table 9.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and
• Notifies the host by asserting ALERT pin
• A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0.
This command has one data byte.
3880fc
83
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
Fault Responses Output Current
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0x47 Action to be taken by the device when an
output overcurrent fault is detected.
TYPE
PAGED FORMAT UNITS NVM
IOUT_OC_FAULT_RESPONSE
R/W Byte
Y
Reg
Y
0x00
IOUT_OC_FAULT_RESPONSE
The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overcurrent fault. The data byte is in the format given in Table 7.
The device also:
• Sets the IOUT_OC bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin
This command has one data byte.
Table 7ꢀ IOUT_OC_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
The LTC3880 continues to operate indefinitely while maintaining
the output current at the value set by IOUT_OC_FAULT_LIMIT
without regard to the output voltage (known as constant-
current or brick-wall limiting).
For all values of bits [7:6], the LTC3880:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin
01
10
Not supported.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
The LTC3880 continues to operate, maintaining the output
current at the value set by IOUT_OC_FAULT_LIMIT without
regard to the output voltage, for the delay time set by bits [2:0].
If the device is still operating in current limit at the end of the
delay time, the device responds as programmed by the Retry
Setting in bits [5:3].
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUNn pin, the
OPERATION command, or the combined action of the RUNn pin
and OPERATION command, to turn off and then to turn back on,
or
11
The LTC3880 shuts down immediately and responds as
programmed by the Retry Setting in bits [5:3].
• Bias power is removed and reapplied to the LTC3880.
Retry Setting
5:3
2:0
000-110 The unit does not attempt to restart. The output remains
disabled until the fault is cleared by cycling the RUNn pin or
removing bias power.
111
The device attempts to restart continuously, without limitation,
until it is commanded OFF (by the RUNn pin or OPERATION
command or both), bias power is removed, or another fault
condition causes the unit to shut down. Note: The retry interval
is set by the MFR_RETRY_DELAY command.
Delay Time
XXX
The number of delay time units in 16ms increments. This
delay time is used to determine the amount of time a unit is
to continue operating after a fault is detected before shutting
down. Only valid for deglitched off state.
3880fc
84
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
Fault Responses IC Temperature
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0xD6 Action to be taken by the device when an
internal overtemperature fault is detected
TYPE
PAGED FORMAT UNITS NVM
MFR_OT_FAULT_RESPONSE
R Byte
N
Reg
0xC0
MFR_OT_FAULT_RESPONSE
The MFR_OT_FAULT_RESPONSE command byte instructs the device on what action to take in response to an internal
overtemperature fault. The data byte is in the format given in Table 8.
The LTC3880 also:
• Sets the MFR bit in the STATUS_WORD, and
• Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command
• Notifies the host by asserting ALERT pin
This command has one data byte.
Table 8ꢀ Data Byte Contents MFR_OT_FAULT_RESPONSE
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
01
10
Not supported. Writing this value will generate a CML fault.
For all values of bits [7:6], the LTC3880:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin
Not supported. Writing this value will generate a CML fault
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11
The device’s output is disabled while the fault is present.
Operation resumes and the output is enabled when the fault
condition no longer exists.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUNn pin, the
OPERATION command, or the combined action of the RUNn pin
and OPERATION command, to turn off and then to turn back on,
or
• Bias power is removed and reapplied to the LTC3880
Retry Setting
5:3
2:0
000
The unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001-111 Not supported. Writing this value will generate CML fault.
XXX Not supported. Value ignored
Delay Time
3880fc
85
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
Fault Responses External Temperature
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
OT_FAULT_ RESPONSE
0x50
Action to be taken by the device when an external R/W Byte
overtemperature fault is detected,
Y
Reg
Reg
Y
0xB8
UT_FAULT_ RESPONSE
0x54
Action to be taken by the device when an external R/W Byte
undertemperature fault is detected.
Y
Y
0xB8
OT_FAULT_RESPONSE
The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an external overtem-
perature fault on the external temp sensors. The data byte is in the format given in Table 9.
The device also:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin
This condition is detected by the ADC so the response time may be up to 100ms.
This command has one data byte.
UT_FAULT_RESPONSE
The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an external undertem-
perature fault on the external temp sensors. The data byte is in the format given in Table 9.
The device also:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin
This condition is detected by the ADC so the response time may be up to 100ms.
This command has one data byte.
3880fc
86
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
Table 9ꢀ Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE,
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
01
10
The PMBus device continues operation without interruption.
Not supported. Writing this value will generate a CML fault.
For all values of bits [7:6], the LTC3880:
• Sets the corresponding fault bit in the status commands, and
• Notifies the host by asserting ALERT pin
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11
Not supported. Writing this value will generate a CML fault.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUNn pin, the
OPERATION command, or the combined action of the RUNn pin
and OPERATION command, to turn off and then to turn back on,
or
• Bias power is removed and reapplied to the LTC3880
Retry Setting
5:3
2:0
000-110 The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
111
The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUNn pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
Delay Time
XXX
Not supported. Values ignored
FAULT SHARING
Fault Sharing Propagation
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
MFR_GPIO_
PROPAGATE_LTC3880
0xD2
Configuration that determines which faults are
propagated to the GPIO pins.
R/W Word
Y
Reg
Y
0x2993
MFR_GPIO_PROPAGATE_LTC3880
The MFR_GPIO_PROPAGATE_LTC3880 command enables the faults that can cause the GPIOn pin to assert low. The
command is formatted as shown in Table 10. Faults can only be propagated to the GPIO if they are programmed to
respond to faults.
This command has two data bytes.
Table 10: GPIOn Propagate Fault Configuration
The GPIO0 and GPIO1 pins are designed to provide electrical notification of selected events to the user. Some of these events are common to both output
channels. Others are specific to an output channel. They can also be used to share faults between channels.
BIT(S)
SYMBOL
OPERATION
B[15]
VOUT disabled while not decayed.
This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG_LTC3880 is a
zero. If the channel is turned off, by toggling the RUN pin or commanding the part OFF, and then
the RUN is reasserted or the part is commanded back on before the output has decayed, VOUT
will not restart until the 12.5% decay is honored. The GPIO pin is asserted during this condition if
bit 15 is asserted.
3880fc
87
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
BIT(S)
SYMBOL
OPERATION
B[14]
Mfr_gpio_propagate_short_CMD_cycle 0: No action
1: Asserts low if commanded off then on before the output has sequenced off. Re-asserts high
120ms after sequence off.
b[13]
b[12]
Mfr_gpio_propagate_ton_max_fault
0: No action if a TON_MAX_FAULT fault is asserted
1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted
GPIO0 is associated with page 0 TON_MAX_FAULT faults
GPIO1 is associated with page 1 TON_MAX_FAULT faults
Unfiltered VOUT_UV_FAULT_LIMIT comparator output
GPIO0 is associated with channel 0
Mfr_gpio0_propagate_vout_uvuf,
Mfr_gpio1_propagate_vout_uvuf
GPIO1 is associated with channel 1
b[11]
b[10]
Mfr_gpio0_propagate_int_ot,
Mfr_gpio1_propagate_int_ot
Mfr_pwrgd1_en (Note 1)
0: No action if the MFR_OT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted
0: No action if channel 1 POWER_GOOD is not true
1: Associated output will be asserted low if channel 1 POWER_GOOD is not true
If this bit is asserted, the GPIO_FAULT_RESPONSE must be ignore. If the GPIO_FAULT_
RESPONSE is not set to ignore, the part will latch off and never be able to start.
b[9]
b[8]
Mfr_pwrgd0_en (Note 1)
0: No action if channel 0 POWER_GOOD is not true
1: Associated output will be asserted low if channel 0 POWER_GOOD is not true
If this bit is asserted, the GPIO_FAULT_RESPONSE must be ignore. If the GPIO_FAULT_
RESPONSE is not set to ignore, the part will latch off and never be able to start.
Mfr_gpio0_propagate_ut,
Mfr_gpio1_propagate_ut
0: No action if the UT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted
GPIO0 is associated with page 0 UT faults
GPIO1 is associated with page 1 UT faults
b[7]
Mfr_gpio0_propagate_ot,
Mfr_gpio1_propagate_ot
0: No action if the OT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted
GPIO0 is associated with page 0 OT faults
GPIO1 is associated with page 1 OT faults
b[6]
b[5]
b[4]
Reserved
Reserved
Mfr_gpio0_propagate_input_ov,
Mfr_gpio1_propagate_input_ov
Reserved
0: No action if the VIN_OV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted
b[3]
b[2]
Mfr_gpio0_propagate_iout_oc,
Mfr_gpio1_propagate_iout_oc
0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted
GPIO0 is associated with page 0 OC faults
GPIO1 is associated with page 1 OC faults
b[1]
b[0]
Mfr_gpio0_propagate_vout_uv,
Mfr_gpio1_propagate_vout_uv
0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted
GPIO0 is associated with page 0 UV faults
GPIO1 is associated with page 1 UV faults
Mfr_gpio0_propagate_vout_ov,
Mfr_gpio1_propagate_vout_ov
0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted
GPIO0 is associated with page 0 OV faults
GPIO1 is associated with page 1 OV faults
Note 1: The PWRGD status is designed as an indicator and not to be used for power supply sequencing.
3880fc
88
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
Fault Sharing Response
DATA
PAGED FORMAT UNITS NVM VALUE
Reg 0xC0
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
MFR_GPIO_RESPONSE
0xD5
Action to be taken by the device when the GPIO pin R/W Byte
Y
Y
is asserted low.
MFR_GPIO_RESPONSE
This command determines the controller’s response to the GPIOn pin being pulled low by an external source.
VALUE
0xC0
0x00
MEANING
GPIO_INHIBIT The LTC3880 will three-state the output in response to the GPIO pin pulled low.
GPIO_IGNORE The LTC3880 continues operation without interruption.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the MFR bit in the STATUS_WORD
• Sets the GPIOB bit in the STATUS_MFR_SPECIFIC command, and
• Notifies the host by asserting ALERT pin. The ALERT pin pulled low can be disabled by setting bit[1] of MFR_CHAN_
CFG_LTC3880.
This command has one data byte.
SCRATCHPAD
DATA
DEFAULT
COMMAND NAME
USER_DATA_00
USER_DATA_01
USER_DATA_02
USER_DATA_03
USER_DATA_04
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM VALUE
0xB0
0xB1
0xB2
0xB3
0xB4
OEM reserved. Typically used for part serialization.
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
N
Y
N
Y
N
Reg
Reg
Reg
Reg
Reg
Y
Y
Y
Y
Y
NA
NA
Manufacturer reserved for LTpowerPlay.
OEM reserved. Typically used for part serialization.
A NVM word available for the user.
NA
0x0000
0x0000
A NVM word available for the user.
USER_DATA_00 through USER_DATA_04
These commands are non-volatile memory locations for customer storage. The customer has the option to write any
value to the USER_DATA_nn at any time. However, the LTpowerPlay software and contract manufacturers use some of
these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable
inventory control and incompatibility with these products.
These commands have 2 data bytes and are in register format.
3880fc
89
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
IDENTIFICATION
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
PMBUS_REVISION
0x98
PMBus revision supported by this device. Current revision R Byte
is 1.1.
N
Reg
Reg
0x11
CAPABILITY
0x19
Summary of PMBus optional communication protocols
supported by this device.
R Byte
N
0xB0
MFR_ID
0x99
0x9A
0x9E
0xE7
The manufacturer ID of the LTC3880 in ASCII.
Manufacturer part number in ASCII.
R String
R String
R Block
R Word
N
N
N
N
ASC
ASC
CF
LTC
LTC3880
NA
MFR_MODEL
MFR_SERIAL
MFR_SPECIAL_ID
Serial number of this specific unit in ASCII.
Manufacturer code representing the LTC3880.
Reg
0x40X
PMBus_REVISION
The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTC3880
is PMBus Version 1.1 compliant in both Part I and Part II.
This read-only command has one data byte.
CAPABILITY
This command provides a way for a host system to determine some key capabilities of a PMBus device.
The LTC3880 supports packet error checking, 400kHz bus speeds, and ALERT pin.
This read-only command has one data byte.
MFR_ID
The MFR_ID command indicates the manufacturer ID of the LTC3880 using ASCII characters.
This read-only command is in block format.
MFR_MODEL
The MFR_MODEL command indicates the manufacturer’s part number of the LTC3880 using ASCII characters.
This read-only command is in block format.
MFR_SERIAL
The MFR_SERIAL command contains up to 9 bytes of custom formatted data used to uniquely identify the LTC3880
configuration.
This read-only command is in block format.
MFR_SPECIAL_ID
The 16-bit word representing the part name. 0x402 denotes the part is an LTC3880, X is adjustable by the manufacturer.
This read-only command has 2 data bytes.
3880fc
90
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
FAULT WARNING AND STATUS
DEFAULT
COMMAND NAME
CLEAR_FAULTS
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
VALUE
0x03
0xE3
0x78
0x79
0x7A
0x7B
0x7C
0x7D
Clear any fault bits that have been set.
Clears all peaks values.
Send Byte
Send Byte
N
N
NA
MFR_CLEAR_PEAKS
STATUS_BYTE
NA
One byte summary of the unit’s fault condition. R/W Byte
Two byte summary of the unit’s fault condition. R/W Word
Y
Y
Y
Y
N
Y
Reg
Reg
Reg
Reg
Reg
Reg
NA
STATUS_WORD
STATUS_VOUT
NA
Output voltage fault and warning status.
Output current fault and warning status.
Input supply fault and warning status.
R/W Byte
R/W Byte
R/W Byte
R/W Byte
NA
STATUS_IOUT
NA
STATUS_INPUT
NA
STATUS_ TEMPERATURE
External temperature fault and warning status
for READ_TEMERATURE_1.
NA
STATUS_CML
0x7E
0x80
Communication and memory fault and
warning status.
R/W Byte
R/W Byte
N
Y
Reg
Reg
NA
NA
STATUS_MFR_ SPECIFIC
Manufacturer specific fault and state
information.
MFR_PADS
0xE5
0xEF
Digital status of the I/O pads.
R Word
R Byte
N
N
Reg
Reg
NA
NA
MFR_COMMON
Manufacturer status bits that are common
across multiple LTC chips.
CLEAR_FAULTS
The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all
status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output
if the device is asserting the ALERT pin signal.
The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut down
for a fault condition are restarted when:
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin
and OPERATION command, to turn off and then to turn back on, or
• MFR_RESET command is issued.
• Bias power is removed and reapplied to the integrated circuit
If the fault is still present when the bit is cleared, the fault bit will remain set and the host notified by asserting the
ALERT pin pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault occurs within that time frame it may be
cleared before the status register is set.
This write-only command has no data bytes.
MFR_CLEAR_PEAKS
The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. A reset will initiate this command.
This write-only command has no data bytes.
3880fc
91
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
STATUS_BYTE
The STATUS_BYTE command returns a one-byte summary of the most critical faults.
STATUS_BYTE Message Contents:
BIT
7*
6
STATUS BIT NAME
MEANING
BUSY
OFF
A fault was declared because the LTC3880 was unable to respond.
This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not
being enabled.
5
4
VOUT_OV
IOUT_OC
VIN_UV
An output overvoltage fault has occurred.
An output overcurrent fault has occurred.
Not supported (LTC3880 returns 0).
3
2
TEMPERATURE
CML
A temperature fault or warning has occurred.
A communications, memory or logic fault has occurred.
1
0*
NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
STATUS_WORD
The STATUS_WORD command returns a two-byte summary of the channel’s fault condition. The low byte of the STA-
TUS_WORD is typically the same as the STATUS_BYTE command: However, if a fault occurs at the exact right time, the
read value can have a bit set in the lower byte with no corresponding bits set in the upper byte. An immediate second
read of STATUS_WORD will have the corresponding bits in the upper byte set.
STATUS_WORD High Byte Message Contents:
BIT
15
14
13
12
11
10
9
STATUS BIT NAME
MEANING
V
An output voltage fault or warning has occurred.
An output current fault or warning has occurred.
An input voltage fault or warning has occurred.
A fault or warning specific to the LTC3880 has occurred.
The POWER_GOOD state is false if this bit is set.
Not supported (LTC3880 returns 0).
OUT
OUT
I
INPUT
MFR_SPECIFIC
POWER_GOOD#
FANS
OTHER
Not supported (LTC3880 returns 0).
8
UNKNOWN
Not supported (LTC3880 returns 0).
Any supported fault bit in this command will initiate an ALERT event.
This command has two data bytes.
3880fc
92
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
STATUS_VOUT
The STATUS_VOUT commands returns one byte of V
status information.
OUT
STATUS_VOUT Message Contents:
BIT
7
MEANING
V
OUT
V
OUT
V
OUT
V
OUT
overvoltage fault.
6
overvoltage warning.
undervoltage warning.
undervoltage fault.
5
4
3
VOUT_MAX warning.
2
TON_MAX fault.
1
TOFF_MAX warning.
0
Not supported by the LTC3880 (returns 0).
ALERT can be asserted if any of bits[7:1] are set. These may be cleared by writing a 1 to their bit position in STATUS_VOUT, in lieu of a CLEAR_FAULTS
command.
This command has one data byte.
STATUS_IOUT
The STATUS_IOUT commands returns one byte of I
status information.
OUT
STATUS_IOUT Message Contents:
BIT
7
MEANING
overcurrent fault.
I
OUT
6
Not supported (LTC3880 returns 0).
I overcurrent warning.
OUT
5
4:0
Not supported (LTC3880 returns 0).
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_IOUT, in lieu of a
CLEAR_FAULTS command.
This command has one data byte.
3880fc
93
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
STATUS_INPUT
The STATUS_INPUT commands returns one byte of V (VINSNS) status information.
IN
STATUS_INPUT Message Contents:
BIT
7
MEANING
overvoltage fault.
V
IN
6
Not supported (LTC3880 returns 0).
V undervoltage warning.
IN
5
4
Not supported (LTC3880 returns 0).
3
Unit off for insufficient V .
IN
2
Not supported (LTC3880 returns 0).
Input over current warning.
1
0
Not supported (LTC3880 returns 0)
ALERT can be asserted if bit 7 is set. Bit 7 may be cleared by writing it to a 1, in lieu of a CLEAR_FAULTS command.
This command has one data byte.
STATUS_TEMPERATURE
The STATUS_TEMPERATURE commands returns one byte of sensed external temperature status information.
STATUS_TEMPERATURE Message Contents:
BIT
7
MEANING
External overtemperature fault.
External overtemperature warning.
Not supported (LTC3880 returns 0).
External undertemperature fault.
Not supported (LTC3880 returns 0).
6
5
4
3:0
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_TEMPERATURE, in lieu
of a CLEAR_FAULTS command.
This command has one data byte.
3880fc
94
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
STATUS_CML
TheSTATUS_CMLcommandsreturnsonebyteofstatusinformationonreceivedcommands,internalmemoryandlogic.
STATUS_CML Message Contents:
BIT
7
MEANING
Invalid or unsupported command received.
Invalid or unsupported data received.
Packet error check failed.
Memory fault detected.
6
5
4
3
Processor fault detected.
2
Reserved (LTC3880 returns 0).
Other communication fault.
Other memory or logic fault.
1
0
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_CML, in lieu of a
CLEAR_FAULTS command.
This command has one data byte.
STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information.
Each channel has a copy of the same information. Only bit 0 is page specific.
The format for this byte is:
BIT MEANING
7
6
5
4
3
2
0
Internal Temperature Fault Limit Exceeded.
Internal Temperature Warn Limit Exceeded.
NVM CRC Fault.
PLL is Unlocked
Fault Log Present
V
DD33
UV or OV Fault
GPIO Pin Asserted Low by External Device (paged)
If any of these bits are set, the MFR bit in the STATUS_WORD will be set.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command. Exception: The fault log present bit can only be cleared
by issuing the MFR_FAULT_LOG_CLEAR command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
3880fc
95
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
Summary of the Status Registers
STATUS_VOUT
VOUT_OV Fault
VOUT_OV Warning
VOUT_UV Warning
VOUT_UV Fault
VOUT_MAX Warning
TON_MAX_FAULT
TOFF_MAX Warning
Reserved
STATUS_WORD
STATUS_INPUT
VIN_OV Fault
Reserved
VIN_UV Warning
Reserved
Reserved
Reserved
IIN_OC Warning
Reserved
(Upper Byte)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
VOUT
IOUT/POUT
INPUT
MFR
POWER_GOOD#
Reserved
Reserved
Unknown
STATUS_IOUT
STATUS_MFR_SPECIFIC
STATUS_BYTE
Also is the Lower Byte of
STATUS_WORD
7
6
5
4
3
2
1
0
IOUT_OC Fault
IOUT_OC Fault with LV Shutdown
IOUT_OC Warning
Reserved
Reserved
Reserved
7
6
5
4
3
2
1
0
INTERNAL TEMP FAULT
INTERNAL TEMP WARN
NVM CRC ERROR
PLL UNLOCKED
FAULT LOG PRESENT
VDD33 OV/UV
7
6
5
4
3
2
1
0
BUSY
OFF
VOUT_OV
IOUT_OC
Reserved
Reserved
Reserved
Reserved
GPIO PIN ASSERTED LOW EXTERNALLY
TEMPERATURE
CML
NONE OF THE ABOVE
3880 F28
STATUS_TEMPERATURE
7
6
5
4
3
2
1
0
OT Fault
OT Warning
Reserved
UT Fault
Reserved
Reserved
Reserved
Reserved
MFR_COMMON
STATUS_CML
7
6
5
4
3
2
1
0
CHIP NOT DRIVING ALERT LOW
CHIP NOT BUSY
CALCULATIONS NOT PENDING
OUTPUT NOT IN TRANSITION
NVM INITIALIZED
Reserved
SHARE_CLK_LOW
WP PIN
7
6
5
4
3
2
1
0
Invalid/Unsupported Command
Invalid/Unsupported Data
Packet Error Check Failed
Memory Fault Detected
Processor Fault Detected
Reserved
Other Communication Fault
Other Memory or Logic Fault
3880fc
96
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
MFR_PADS
This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit
assignments of this command are as follows:
BIT ASSIGNED DIGITAL PIN
15
14
V
DD33
V
DD33
OV Fault
UV Fault
13 Reserved
12 Reserved
11 ADC Values Invalid, Occurs
During Start-Up
10 Device Driving ALERT Low
9
8
7
6
5
4
3
2
1
0
PowerGood1
PowerGood0
Device Driving RUN1 Low
Device Driving RUN0 Low
RUN1
RUN0
Device Driving GPIO1 Low
Device Driving GPIO0 Low
GPIO1
GPIO0
A 1 indicates the condition is true.
This read-only command has two data bytes.
MFR_COMMON
The MFR_COMMON command contains bits that are common to all LTC digital power and telemetry products.
BIT
7
MEANING
CHIP NOT DRIVING ALERT LOW
CHIP NOT BUSY
6
5
CALCULATIONS NOT PENDING
OUTPUT NOT IN TRANSITION
NVM Initialized
4
3
2
Reserved
1
SHARE_CLK Timeout
WP Pin Status
0
This read-only command has one data byte.
3880fc
97
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
TELEMETRY
CMD
DEFAULT
COMMAND NAME
READ_VIN
CODE DESCRIPTION
TYPE PAGED FORMAT UNITS NVM VALUE
0x88 Measured input supply voltage.
0x8B Measured output voltage.
0x89 Calculated input supply current.
0xED Calculated input current per channel.
0x8C Measured output current.
R Word
R Word
R Word
R Word
R Word
N
Y
N
Y
Y
Y
L11
L16
L11
L11
L11
L11
V
V
A
A
A
C
NA
NA
NA
NA
NA
NA
READ_VOUT
READ_IIN
MFR_READ_IIN
READ_IOUT
READ_TEMPERATURE_1
0x8D External diode junction temperature. This is the value R Word
used for all temperature related processing, including
IOUT_CAL_GAIN.
READ_TEMPERATURE_2
0x8E Internal junction temperature. Does not affect any
other registers.
R Word
N
L11
C
NA
READ_DUTY_CYCLE
READ_POUT
0x94 Duty cycle of the top gate control signal.
0x96 Calculated output power.
R Word
R Word
Y
Y
Y
L11
L11
L16
%
W
V
NA
NA
NA
MFR_VOUT_PEAK
0xDD Maximum measured value of READ_VOUT since last R Word
MFR_CLEAR_PEAKS.
MFR_VIN_PEAK
0xDE Maximum measured value of READ_VIN since last
MFR_CLEAR_PEAKS.
R Word
N
Y
L11
L11
V
C
NA
NA
MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of external Temperature
R Word
(READ_TEMPERATURE_1) since last MFR_CLEAR_
PEAKS.
MFR_TEMPERATURE_2_PEAK 0xF4 Maximum measured value of external Temperature
R Word
N
Y
L11
L11
C
A
NA
NA
(READ_TEMPERATURE_2) since last MFR_CLEAR_
PEAKS.
MFR_IOUT_PEAK
0xD7 Report the maximum measured value of READ_IOUT R Word
since last MFR_CLEAR_PEAKS.
READ_VIN
The READ_VIN command returns the measured input voltage, in volts.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_VOUT
The READ_VOUT command returns the measured output voltage in the same format as set by the VOUT_MODE
command.
This read-only command has two data bytes and is formatted in Linear_16u format.
READ_IIN
The READ_IIN command returns the input current in Amperes. Note: Input current is calculated from READ_IOUT
current and the READ_DUTY_CYCLE value from both outputs plus the MFR_IIN_OFFSET. For accurate values at low
currents the part must be in continuous conduction mode. The greatest source of error if DCR sensing is used, is the
accuracy of the inductor parasitic DC resistance (DCR) at room temperature IOUT_CAL_GAIN.
READ_IIN = MFR_READ_IIN_
+ MFR_READ_IIN_
PAGE1
PAGE0
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
3880fc
98
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
MFR_READ_IIN
The MFR_READ_IIN command is a paged reading of the input current that applies the paged MFR_IIN_OFFSET
parameter. This calculation is similar to READ_IIN except the paged values are used.
MFR_READ_IIN = MFR_IIN_OFFSET + (IOUT • DUTYCYCLE)
This command has 2 data bytes and is formatted in Linear_5s_11s format.
READ_IOUT
The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of:
a) the differential voltage measured across the I
b) the IOUT_CAL_GAIN value
pins
SENSE
c) the MFR_IOUT_CAL_GAIN_TC value, and
d) READ_TEMPERATURE_1 value
e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_TEMPERATURE_1
The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the external sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_TEMPERATURE_2
The READ_TEMPERATURE_2 command returns the temperature, in degrees Celsius, of the internal sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_DUTY_CYCLE
The READ_DUTY_CYCLE command returns the duty cycle of controller, in percent.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_POUT
The READ_POUT command is a paged reading of the DC/DC converter output power in Watts. The POUT is calculated
based on the most recent correlated output voltage and current readings.
This command has 2 data bytes and is formatted in Linear_5s_11s format.
3880fc
99
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
MFR_VOUT_PEAK
The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_16u format.
MFR_VIN_PEAK
The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_1_PEAK
The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_1 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_2_PEAK
The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_2 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_IOUT_PEAK
The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
3880fc
100
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
NVM MEMORY COMMANDS
Store/Restore
CMD
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
STORE_USER_ALL
0x15
0x16
0xF0
Store user operating memory to EEPROM.
Restore user operating memory from EEPROM.
Send Byte
Send Byte
N
N
N
NA
RESTORE_USER_ALL
MFR_COMPARE_USER_ALL
NA
Compares current command contents with NVM. Send Byte
NA
STORE_USER_ALL
The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating
Memory to the matching locations in the non-volatile User NVM memory.
Executing this command if the die temperature exceeds 85°C is not recommended and the data retention of 10 years
cannot be guaranteed. If the die temperature exceeds 130°C, the STORE_USER_ALL command is disabled. The com-
mand is re-enabled when the IC temperature drops below 125°C.
Communication with the LTC3880 and programming of the NVM can be initiated when VDD33 is available and VIN
is not applied. To enable the part in this state, using global address 0x5B write 0x2B followed by 0xC4. The part
can now be communicated with, and the project file updated. To write the updated project file to the NVM issue a
STORE_USER_ALL command. When VIN is applied, a MFR_RESET must be issued to allow the PWM to be enabled
and valid ADCs to be read.
This write-only command has no data bytes.
RESTORE_USER_ALL
The RESTORE_USER_ALL command instructs the PMBus device to copy the contents of the non-volatile User memory
to the matching locations in the Operating Memory. The values in the Operating Memory are overwritten by the value
retrieved from the User commands. When a RESTORE_USER_ALL command is issued, the RUN pins and SHARE_CLK
pin are asserted low until the restore is complete. The RUN pins and SHARE_CLK pin are then released. The run pins
are held low for the MFR_RESTART_DELAY. The RESTORE_USER_ALL command will place the value of all commands
stored in NVM into the RAM ignoring the pin-strapped resistor configuration pins including ASEL. The MFR_RESET
command is recommended to be used instead of RESTORE_USER_ALL because the MFR_RESET command always
honors the ASEL pins and will honor the pin-strapped RCONFIG pins if the part is programmed to respect them.
RESTORE_USER_ALL. RESTORE_USER_ALL commands are disabled if the die exceeds 130°C and are not re-enabled
until the die temperature drops below 125°C.
This write-only command has no data bytes.
MFR_COMPARE_USER_ALL
The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with
what is stored in non-volatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated.
This write-only command has no data bytes.
3880fc
101
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
Fault Logging
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM VALUE
MFR_FAULT_LOG
0xEE
Fault log data bytes. This sequentially retrieved
data is used to assemble a complete fault log.
R Block
N
N
CF
Y
NA
NA
MFR_FAULT_LOG_ STORE
MFR_FAULT_LOG_CLEAR
0xEA
Command a transfer of the fault log from RAM to Send Byte
EEPROM. This causes the part to behave as if a
channel has faulted off.
0xEC
Initialize the EEPROM block reserved for fault
logging and clear any previous fault logging
locks.
Send Byte
N
NA
MFR_FAULT_LOG
The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occurrence
since the last MFR_FAULT_LOG_CLEAR command was last written. The contents of this command are stored in non-
volatile memory, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this command
are listed in Table 11. If the user accesses the MFR_FAULT_LOG command and no fault log is present, the command
will return a data length of 0. If a fault log is present, the MFR_FAUTL_LOG will always return a block of data 147
bytes long. If a fault occurs within the first second of applying power, some of the earlier pages in the fault log may
not contain valid data. When a fault occurs and Fault Log is enabled, a header section and the last 6 ADC events are
stored in NVM. If the Fault Log is read before a reset occurs, the most recent event is in location N (the first location).
If the part resets or V is lost, the event may appear in any one of the 6 cyclical data locations.
IN
NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock.
This read-only command is in block format.
MFR_FAULT_LOG_STORE
The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to NVM just as if a fault event
occurred. This command will generate a MFR_SPECIFIC fault if the “Enable Fault Logging” bit is set in the MFR_
CONFIG_ALL_LTC3880 command.
If the die temperature exceeds 130°C, the MFR_FAULT_LOG_STORE command is disabled until the IC temperature
drops below 125°C.
Up-Time Counter is in the Fault Log header. The counter is the time since the last reset in 200µs increments. This is
a 48-bit binary counter.
This write-only command has no data bytes.
3880fc
102
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
Table 11ꢀ Fault Logging
This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.
Data Format Definitions
LIN 11 = PMBus = Rev 1.1, Part 2, section 7.1
LIN 16 = PMBus Rev 1.1, Part 2, section 8. Mantissa portion only
BYTE = 8 bits interpreted per definition of this command
DATA
FORMAT BYTE NUM BLOCK READ COMMAND
DATA
BITS
Block Length
BYTE
147
The MFR_FAULT_LOG command is a fixed length of 147 bytes
The block length will be zero if a data log event has not been captured
HEADER INFORMATION
Position_Fault
BYTE
BYTE
0
Indicates the fault that caused the fault log to be activated.
MFR_REAL_TIME
[7:0}
[15:8}
[23:16]
[31:24]
[39:32]
[47:40]
[15:8]
[7:0]
1
48-bit binary counter. The value is the time since the last reset in 200µs
increments.
BYTE
2
BYTE
3
BYTE
4
BYTE
5
BYTE
6
MFR_VOUT_PEAK (PAGE 0)
MFR_VOUT_PEAK (PAGE 1)
MFR_IOUT_PEAK (PAGE 0)
MFR_IOUT_PEAK (PAGE 1)
MFR_VIN_PEAK
LIN 16
LIN 16
LIN 16
LIN 16
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
7
Peak READ_VOUT page 0 since last MFR_CLEAR_PEAKS.
Peak READ_VOUT page 1 since last MFR_CLEAR_PEAKS.
Peak READ_IOUT page 0 since last MFR_CLEAR_PEAKS.
Peak READ_IOUT page 1 since last MFR_CLEAR_PEAKS.
Peak READ_VIN since last MFR_CLEAR_PEAKS.
8
[15:8]
[7:0]
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
READ_TEMPERATURE_1 (PAGE 0)
[15:8]
[7:0]
External temperature sensor 0 during last event
READ_TEMPERATURE_1 (PAGE 1)
READ_TEMPERATURE_2
[15:8]
[7:0]
External temperature sensor 1 during last event
[15:8]
[7:0]
Internal temperature sensor during last event
MFR_TEMPERATURE1_PEAK (PAGE 0)
MFR_TEMPERATURE1_PEAK (PAGE 1)
[15:8]
[7:0]
Peak READ_TEMPERATURE_1 page 0 since MFR_CLEAR_PEAKS.
Peak READ_TEMPERATURE_1 page 1 since MFR_CLEAR_PEAKS.
[15:8]
[7:0]
3880fc
103
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
CYCLICAL DATA
EVENT n
Event “n” represents one complete cycle of ADC reads through the MUX
at time of fault. Example: If the fault occurs when the ADC is processing
step 15, it will continue to take readings through step 25 and then store
the header and all 6 event pages to EEPROM
(Data at Which Fault Occurred; Most Recent Data)
READ_VOUT (PAGE 0)
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
[15:8]
[7:0]
LIN 16
LIN 16
LIN 16
LIN 16
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
READ_IIN
[15:8]
[7:0]
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
BYTE
[15:8]
[7:0]
WORD
WORD
WORD
WORD
BYTE
STATUS_WORD (PAGE 1)
[15:8]
[7:0]
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
BYTE
3880fc
104
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
EVENT n-1
(data measured before fault was detected)
READ_VOUT (PAGE 0)
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
[15:8]
[7:0]
LIN 16
LIN 16
LIN 16
LIN 16
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
READ_IIN
[15:8]
[7:0]
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
BYTE
[15:8]
[7:0]
WORD
WORD
WORD
WORD
BYTE
STATUS_WORD (PAGE 1)
[15:8]
[7:0]
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
BYTE
*
*
*
3880fc
105
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
EVENT n-5
(Oldest Recorded Data)
READ_VOUT (PAGE 0)
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
[15:8]
[7:0]
LIN 16
LIN 16
LIN 16
LIN 16
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
READ_IIN
[15:8]
[7:0]
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
BYTE
[15:8]
[7:0]
WORD
WORD
WORD
WORD
BYTE
STATUS_WORD (PAGE 1)
[15:8]
[7:0]
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
BYTE
3880fc
106
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
Table 11a: Explanation of Position_Fault Values
POSITION_FAULT VALUE
SOURCE OF FAULT LOG
0xFF
0x00
0x01
0x02
0x03
0x05
0x06
0x07
0x0A
0x10
0x11
0x12
0x13
0x15
0x16
0x17
0x1A
MFR_FAULT_LOG_STORE
TON_MAX_FAULT Channel 0
VOUT_OV_FAULT Channel 0
VOUT_UV_FAULT Channel 0
IOUT_OC_FAULT Channel 0
OT_FAULT Channel 0
UT_FAULT Channel 0
VIN_OV_FAULT Channel 0
MFR_OT_FAULT Channel 0
TON_MAX_FAULT Channel 1
VOUT_OV_FAULT Channel 1
VOUT_UV_FAULT Channel 1
IOUT_OC_FAULT Channel 1
OT_FAULT Channel 1
UT_FAULT Channel 1
VIN_OV_FAULT Channel 1
MFR_OT_FAULT Channel 1
MFR_FAULT_LOG_CLEAR
The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the
STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear.
This write-only command is send bytes.
3880fc
107
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
pmbꢀꢁ commanD DeTails
Block Memory Write/Read
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM VALUE
MFR_EE_UNLOCK
0xBD
0xBE
0xBF
Unlock user EEPROM for access by MFR_EE_ERASE and
MFR_EE_DATA commands.
R/W Byte
N
N
N
Reg
Reg
Reg
NA
NA
NA
MFR_EE_ERASE
MFR_EE_DATA
Initialize user EEPROM for bulk programming by MFR_EE_ R/W Byte
DATA.
Data transferred to and from EEPROM using sequential
PMBus word reads or writes. Supports bulk programming.
R/W
Word
All the NVM commands are disabled if the die temperature exceeds 130°C. NVM commands are re-enabled when the
die temperature drops below 125°C.
MFR_EE_UNLOCK
Multiple writes to MFR_EE_UNLOCK with the appropriate unlock keys are used to enable MFR_EE_ERASE and MFR_
EE_DATA access and configure PEC.
Communication with the LTC3880 and programming of the NVM can be initiated when VDD33 is applied and VIN is
not. To enable the part in this state, use global address 0x5B command 0xBD data 0x2B followed by address 0x5B
command 0xBD data 0xC4. When VIN is applied, a MFR_RESET must be issued to allow the PWM to be enabled and
valid ADCs to be read.
Writing 0x2B followed by 0xD4 clears PEC, resets the EEPROM address pointer and unlocks the part for EEPROM
erase and data command writes.
Writing 0x2B followed by 0xD5 sets the PEC, resets the EEPROM address pointer and unlocks the part for EEPROM
erase and data command writes.
Writing 0x2B followed by 0x91 and 0xE4 clears PEC, resets the EEPROM address pointer and unlocks the part for
EEPROM data reads of all locations.
Writing 0x2B followed by 0x91 and 0xE5 sets PEC, resets the EEPROM address pointer and unlocks the part for
EEPROM data reads of all locations.
MFR_EE_ERASE
A single write after the appropriate unlock key erases the EEPROM allowing subsequent data writes. This register may
be read to indicate if an EEPROM access is in progress.
A value of 0x2B will erase the EEPROM. If the part is busy writing or erasing the EEPROM a non-zero value will be
returned.
MFR_EE_DATA
Sequential writes or reads perform block loads or restores from the EEPROM. Successive MFR_EE_DATA word writes
will enter the EEPROM until it is full. Extra writes will lock the part. The first write is to the lowest address. The first
read returns the 16 bit EEPROM packing revision ID. The second read returns the number of 16 bit words available.
Subsequent reads return EEPROM data starting with the lowest address.
3880fc
108
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
Typical applicaTions
High Efficiency Dual 500kHz 5V/3.3V Step-Down Converter with Sense Resistors
V
IN
6V TO 24V
22µF
1µF
10µF
M1
M2
D1
D2
V
INTV
IN
CC
TG0
TG1
0.1µF
0.1µF
L1
2.2µH
L0
2.2µH
BOOST0
SW0
BOOST1
SW1
0.005Ω
0.005Ω
BG0
BG1
LTC3880
4.99k
PGND
SYNC
SDA
SCL
V
DD25
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
20k
16.2k
20k
V
ALERT
OUT0_CFG
15.8k
23.2k
11k
20.5k
12.7k
V
V
GPIO0
TRIM0_CFG
DD33
GPIO1
V
OUT1_CFG
V
SHARE_CLK
RUN0
TRIM1_CFG
ASEL
RUN1
WP
FREQ_CFG
TSNS0
+
TSNS1
+
I
I
I
SENSEO
SENSE1
100Ω
100Ω
100Ω
100Ω
1000pF
1000pF
–
–
I
V
V
V
V
5V
5A
SENSEO
SENSE1
OUT0
3.3V
5A
OUT1
+
V
SENSEO
SENSEO
SENSE1
–
I
V
I
TH1
THO
+
+
4700pF
4.99k
4700pF
4.99k
SGND
V
DD33
DD25
530µF
530µF
10nF
220pF
220pF
1µF
1µF
10nF
L0, L1: VISHAY IHLP-2525CZ01 2.2µH
M1, M2: VISHAY Si4816BDY
3880 TA03
3880fc
109
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
Typical applicaTions
High Efficiency 350kHz 2-Phase 1.5V Dual Step-Down Converter with External VCC and Sense Resistors
V
IN
6V TO 24V
5V
CC
22µF
1µF
10µF
D1
D2
V
EXTV
IN
CC
M1
TG0
TG1
M2
M4
0.1µF
0.1µF
L0
L1
0.42µH
BOOST0
SW0
BOOST1
SW1
0.42µH
0.0015Ω
0.0015Ω
M3
BG0
BG1
4.99k
PGND
SYNC
SDA
V
DD25
10k
10k
10k
LTC3880-1
SCL
24.9k
20k
V
ALERT
OUT0_CFG
7.32k
17.8k
V
V
DD33
GPIO0
TRIM0_CFG
10k
10k
GPIO1
V
OUT1_CFG
V
SHARE_CLK
RUN0
TRIM1_CFG
ASEL
10k
RUN1
WP
FREQ_CFG
TSNS0
+
TSNS1
+
I
I
I
SENSEO
SENSE1
100Ω
100Ω
100Ω
100Ω
1000pF
1000pF
–
–
I
V
V
V
SENSEO
SENSE1
OUT1
1.5V
40A
+
V
SENSEO
SENSEO
SENSE1
–
I
V
I
TH1
THO
+
+
4700pF
2.55k
SGND
V
DD33
DD25
530µF
530µF
10nF
220pF
1µF
1µF
10nF
3880 TA04
L0, L1: VITEC 59PR9875 0.42µH
M1, M2: INFINEON BSC050N03LS
M3, M4: INFINEON BSC010NE2LSI
3880fc
110
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
Typical applicaTions
High Efficiency 425kHz 1V Step-Down Dual Phase Converter with Power Blocks
V
IN
7V TO 13.2V
22µF
10µF
1µF
7V
GATE DRIVE
V
INTV
IN
CC
V
V
IN
PWMH
IN
V
OUT
TG0
TG1
V
PWMH
OUT
–
+
+
–
P1
P2
–
+
CS
CS
CS
CS
BOOST0
SW0
BOOST1
SW1
V
V
GATE
GATE
1µF
1µF
+
–
TEMP
TEMP
TEMP PWML
GND
PWML TEMP
GND
BG0
SYNC
SDA
SCL
BG1
4.99k
10k
PGND
V
LTC3880
DD25
10k
10k
24.9k
20k
16.2k
ALERT
V
OUT0_CFG
V
DD33
GPIO0
10k
10k
4.32k
17.8k
17.4k
V
TRIM0_CFG
GPIO1
V
SHARE_CLK
RUN0
OUT1_CFG
V
TRIM1_CFG
10k
ASEL
RUN1
WP
FREQ_CFG
TSNS0
+
TSNS1
+
I
I
SENSEO
SENSE1
1µF
1µF
0.22µF
0.22µF
1.2k
1.2k
–
–
I
V
V
I
V
V
1.0V
60A
SENSEO
SENSE1
OUT1
+
SENSEO
SENSEO
SENSE1
–
I
V
I
TH1
THO
+
+
4700pF
2.55k
SGND
V
DD33
DD25
530µF
530µF
220pF
1µF
1µF
3880 TA05
P1, P2: VRA001-4C3G ACBEL POWER BLOCK
3880fc
111
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
Typical applicaTions
3880fc
112
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
Typical applicaTions
3880fc
113
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-ꢀ728 Rev Ø)
0.70 0.05
6.50 0.05
5.ꢀ0 0.05
4.42 0.05
4.50 0.05
(4 SIDES)
4.42 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 0.05
R = 0.ꢀꢀ5
TYP
6.00 0.ꢀ0
(4 SIDES)
R = 0.ꢀ0
TYP
39 40
0.40 0.ꢀ0
PIN ꢀ TOP MARK
(SEE NOTE 6)
ꢀ
2
PIN ꢀ NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
4.42 0.ꢀ0
4.50 REF
(4-SIDES)
4.42 0.ꢀ0
(UJ40) QFN REV Ø 0406
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
BOTTOM VIEW—EXPOSED PAD
ꢀ. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE TOP AND BOTTOM OF PACKAGE
3880fc
114
For more information www.linear.com/LTC3880
LTC3880/LTC3880-1
revision hisTory
REV
DATE
10/11 Added I-grade, all sections updated
11/13 Amended upper limit of I
DESCRIPTION
PAGE NUMBER
A
1-112
B
5
SENSE0/1
Amended parametric errors and typical values
Amended Pin Function errors
6
13
Amended 2nd left paragraph under Operation
Amended 3rd left paragraph under Operation
Amended commands on Table 2
17
23
31
Amended formula on Figure 18a
38
Amended component on Figure 27
Amended Scratchpad table
56
88
89
Amended Identification table
Amended PMBus Command Details table
Amended components on Typical Application page
100
106
C
05/14 Added Initialization Time
5
Reduced readback time
Edit equations
Throughout
40, 57, 58
56, 106, 108,
109
Changed schematic MOSFET part numbers
Edit VOUT_MAX description
31
33
Edit MFR_VOUT_MAX description
Added STATUS Message content
90, 91, 92, 93
3880fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
115
LTC3880/LTC3880-1
Typical applicaTion
High Efficiency Dual 425kHz 2.5V/1.8V Step-Down Converter
V
IN
6V TO 24V
22µF
1µF
10µF
D1
D2
V
INTV
IN
CC
M1
M3
TG0
TG1
M2
M4
0.1µF
0.1µF
L0
L1
BOOST0
SW0
BOOST1
SW1
1.0µH
0.56µH
BG0
SYNC
SDA
SCL
BG1
4.99k
2.0k
1µF
1.58k
1µF
PGND
V
DD25
10k
10k
10k
10k
10k
10k
10k
10k
LTC3880
V
20k
15k
24.9k
11.3k
10k
16.2k
17.4k
ALERT
OUT0_CFG
15.8k
V
V
GPIO0
TRIM0_CFG
DD33
GPIO1
V
OUT1_CFG
V
SHARE_CLK
RUN0
TRIM1_CFG
ASEL
RUN1
WP
FREQ_CFG
TSNS0
+
TSNS1
+
I
I
I
SENSEO
SENSE1
2.0k
1.58k
0.22µF
0.22µF
–
–
I
V
V
V
V
1.8V
20A
SENSEO
SENSE1
OUT0
2.5V
20A
OUT1
+
V
SENSEO
SENSEO
SENSE1
–
I
V
I
TH1
THO
+
+
2200pF
6.04k
2200pF
4.99k
SGND
V
DD33
DD25
530µF
530µF
10nF
220pF
220pF
10nF
1µF
1µF
L0, L1: VISHAY IHLP-4040DZ-11 1µH, 0.56µH
M1, M2: INFINEON BSC050N03LS
M3, M4: INFINEON BSC010NE2LS
3880 TA02
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
Up to 24V, 0.5V ≤ V
LTC3883/LTC3883-1 Single Output PolyPhase Step-Down Controller with Input Current
Sense and Digital Power Sytem Management
V
≤ 5.4V, Analog CM Control Loop,
OUT
IN
2
I C/PMBus Interface with EEPROM and 16-Bit ADC
LTC2977
Octal, PMBus Compliant Power-Supply Monitor, Supervisor,
Sequencer and Margin Controller
Fault Logging to Internal EEPROM Monitors Eight Output
Channels and One Input Voltage
LTC3850/LTC3850-2 Dual 2-Phase, Synchronous Step-Down DC/DC Controller, R
or DCR Current Sensing and Tracking
PLL Fixed 250kHz to 780kHz Frequency, 4V ≤ V ≤ 30V,
IN
SENSE
0.8V ≤ V
≤ 5.25V
OUT
LTC3855
LTC3869
LTC3861
LTC3833
LTC3856
LTC3870
LTC3890
LTM®4676
Dual, Multiphase, Synchronous Step-Down DC/DC Controller with PLL Fixed Frequency 250kHz to 770kHz, 4.5V ≤ V ≤ 38V,
IN
Diff Amp and DCR Temperature Compensation
0.8V ≤ V
≤ 12V
OUT
Dual 2-Phase, Synchronous Step-Down DC/DC Controller, with
Excellent Current Balance when Paralleled
PLL Fixed Frequency 250kHz to 770kHz, 4V ≤ V ≤ 38V,
IN
0.6V ≤ V
≤ 12.5V
OUT
Dual, Multiphase, Synchronous Step-Down DC/DC Controller with Operates with Power Blocks, DRMOS Devices or External
Diff Amp and Three-State Output Drive
MOSFETs 3V ≤ V ≤ 24V, t
= 20ns
ON(MIN)
IN
Fast Accurate Synchronous Step-Down DC/DC Controller
Controlled On-time, Synchronizable, 4.5V ≤ V ≤ 38V,
IN
0.6V ≤ V
≤ 5.25V
OUT
2-Phase, Single Output Synchronous Step-Down DC/DC Controller PLL Fixed 250kHz to 770kHz Frequency, 4.5V ≤ V ≤ 38V,
IN
with Diff Amp and DCR Temp Compensation
0.6V ≤ V
≤ 5.25V
OUT
PolyPhase Step-Down Slave Controller for the LTC3880/LTC3883
with Digital Power System Management
LTC3880/LTC3883 Extender, 4.5V ≤ V ≤ 60V, PLL 100kHz to
IN
1MHz Frequency, 4mm × 5mm QFN-28
60V, Low I , Dual Output 2-Phase Synchronous Step-Down
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V,
Q
IN
DC/DC Controller
0.8V ≤ V
≤ 24V, 5mm × 5mm QFN-32
OUT
Dual 13A or Single 26A µModule® Power Supply with Digital
Power Sytem Management
4.5V ≤ V ≤ 26V, 0.5V ≤ V
≤ 5.4V,
IN
OUT
16mm × 16mm × 5.01mm BGA
This product has a license from PowerOne, Inc. related to digital power technology as set forth in U.S. Patent 7000125 and other related patents owned by PowerOne, Inc.
This license does not extend to standalone power supply products.
3880fc
LT 0514 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
116
●
●
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3880
LINEAR TECHNOLOGY CORPORATION 2011
相关型号:
LTC3880EUJ-1#TRPBF
LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
Linear
LTC3880IUJ#PBF
LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
Linear
LTC3880IUJ#PBF
Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management
ADI
LTC3880IUJ#TRPBF
LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
Linear
LTC3880IUJ-1#PBF
LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
Linear
LTC3880IUJ-1#TRPBF
LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
Linear
LTC3880_15
Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management
Linear
©2020 ICPDF网 联系我们和版权申明