LTC3882EUJ-1#PBF [Linear]
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| 型号： | LTC3882EUJ-1#PBF |
| 厂家： | 
Linear |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3882-1
Dual Output PolyPhase
Step-Down DC/DC Voltage Mode Controller
with Digital Power System Management
FeaTures
DescripTion
2
The LTC®3882-1 is a dual, PolyPhase DC/DC synchronous
step-down switching regulator controller with PMBus
compliant serial interface. It uses a constant frequency,
leading-edge modulation, voltage mode architecture for
excellent transient response and output regulation. Each
PWM channel can produce output voltages from 0.5V to
5.25Vusingawiderangeof3.3Vcompatiblepowerstages,
including power blocks, DrMOS or discrete FET drivers.
Up to four LTC3882-1 devices can operate in parallel for
2-, 3-, 4-, 6- or 8-phase operation.
n
PMBus/I C Compliant Serial Interface
– Monitor Voltage, Current, Temperature and Faults
– Program Voltage, Soft-Start/Stop, Sequencing,
Margining, AVP and UV/OV/OC Limits
n
n
n
3V ≤ VINSNS ≤ 38V, 0.5V ≤ V
0.5ꢀ Output Voltage Error
≤ 5.25V
OUT
Programmable PWM Frequency or External Clock
Synchronization from 250kHz to 1.25MHz
Accurate PolyPhase® Current Sharing
Internal EEPROM with Fault Logging
IC Supply Range: 3V to 13.2V
Resistor or Inductor DCR Current Sensing
Power Good Output Voltage Monitor
Optional Resistor Programming for Key Parameters
40-Pin (6mm × 6mm) QFN Package
n
n
n
n
n
n
n
System configuration and monitoring is supported by the
LTpowerPlay™softwaretool.TheLTC3882-1serialinterface
can read back input voltage, output voltage and current,
temperatureandfaultstatus.Mostoperatingparameterscan
be set via the digital interface or stored in internal EEPROM
foruseatpowerup. Switchingfrequencyandphase, output
voltage and device address can also be set using external
configuration resistors.
applicaTions
n
High Current Distributed Power Systems
n
Servers, Network and Storage Equipment
L, LT, LTC, LTM, Linear Technology,the Linear logo and PolyPhase are registered trademarks
and LTpowerPlay is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 5396245, 5859606,
6144194, 6937178, 7420359 and 7000125.
n
Intelligent Energy Efficient Power Regulation
PWM ENABLE
OUTPUT
TG/BG
HW WRITE
DEDICATED
DIFFERENTIAL
SENSE
Typical applicaTion
CONTROL PROTECT PGOOD OUTPUT
V
OUT
LTC3882
•
•
•
V
Only
OUT0
LTC3882-1
•
V
& V
OUT0 OUT1
V
IN
7V TO 13.2V
+
V
VINSNS
V
CC
SENSE0
FB0
V
FDMF5820DC
PWM
IN
LTC3882-1
Load Step Transient Current Sharing
(Using FDMF5820DC DrMOS)
V
SDA
OUT
1V
70A
SW
SCL
COMP0
COMP1
PWM0
TSNS0
TO/FROM
MCU
ALERT
RUN0
RUN1
GND
I
OUT
10A/DIV
PGOOD0
FAULT0
+
SENSE0
–
I
I
SENSE0
+
TO/FROM
EXTERNAL DEVICES
PGOOD1
FAULT1
V
I
SENSE1
–
SENSE1
+
SYNC
FDMF5820DC
PWM
I
V
SENSE1
IN
SHARE_CLK
I
I
AVG0
AVG1
SW
PWM1
TSNS1
I
, I
L0 L1
10A/DIV
I
AVG_GND
GND
–
SENSE0
–
V
V
38821 TA01b
50µs/DIV
SENSE1
GND
38821 TA01a
INDUCTORS: COOPER FP1007R1-R22
SOME DETAILS OMITTED FOR CLARITY
38821f
1
For more information www.linear.com/LTC3882-1
LTC3882-1
Table oF conTenTs
Features..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Absolute Maximum Ratings.............................. 4
Order Information.......................................... 4
Pin Configuration .......................................... 4
Electrical Characteristics................................. 5
Typical Performance Characteristics ................... 9
Pin Functions..............................................13
Block Diagram.............................................15
Test Circuit.................................................16
Timing Diagram...........................................16
Operation...................................................16
Overview ............................................................ 16
Main Control Loop.............................................. 17
Power-Up and Initialization................................. 19
Soft-Start ...........................................................20
Time-Based Output Sequencing .........................20
Output Ramping Control.....................................20
Voltage-Based Output Sequencing .....................20
Minimum Output Disable Times .........................21
Output Short Cycle.............................................21
Light Load Current Operation .............................21
Switching Frequency and Phase.........................21
PolyPhase Load Sharing.....................................22
Active Voltage Positioning..................................22
Input Supply Monitoring.....................................22
Output Voltage Sensing and Monitoring.............22
Output Current Sensing and Monitoring.............22
External and Internal Temperature Sense...........23
Resistor Configuration Pins................................23
Internal EEPROM with CRC ................................24
Fault Detection....................................................24
Input Supply Faults.............................................24
Serial Communication Errors..............................36
PMBus Command Summary ............................37
PMBus Commands.............................................37
Data Formats......................................................37
Applications Information ................................42
Efficiency Considerations ...................................42
PWM Frequency and Inductor Selection.............42
Power MOSFET Selection...................................43
MOSFET Driver Selection ...................................44
Using PWM Protocols ........................................44
C Selection.......................................................44
IN
OUT
C
Selection....................................................45
Feedback Loop Compensation............................46
PCB Layout Considerations................................47
Output Current Sensing......................................48
Output Voltage Sensing......................................50
Soft-Start and Stop ............................................ 51
Time-Based Output Sequencing and Ramping ... 51
Voltage-Based Output Sequencing .....................52
Using Output Voltage Servo ...............................54
Using AVP ..........................................................54
PWM Frequency Synchronization.......................55
PolyPhase Operation and Load Sharing .............56
External Temperature Sense...............................60
Resistor Configuration Pins................................60
Internal Regulator Outputs .................................62
IC Junction Temperature.....................................62
Derating EEPROM Retention at Temperature......63
Configuring Open-Drain Pins..............................63
PMBus Communication and Command Processing64
Status and Fault Log Management.....................65
LTpowerPlay – An Interactive Digital Power GUI 65
Interfacing to the DC1613...................................66
Design Example..................................................66
PMBus COMMAND DETAILS.............................70
Addressing and Write Protect.................................70
PAGE ..................................................................70
PAGE_PLUS_WRITE ..........................................70
PAGE_PLUS_READ............................................71
WRITE_PROTECT...............................................71
MFR_ADDRESS .................................................72
MFR_RAIL_ADDRESS .......................................72
General Device Configuration .................................72
PMBUS_REVISION.............................................72
CAPABILITY........................................................72
MFR_CONFIG_ALL_LTC3882-1 .........................73
On, Off and Margin Control.....................................73
ON_OFF_CONFIG................................................73
OPERATION........................................................ 74
Hardwired PWM Response to V
Faults .........24
OUT
Power Good Indication (Master).........................25
Power Good Indication (Slave) ...........................25
Hardwired PWM Response to I
Faults ............... 25
OUT
Hardwired PWM Response to Temperature Faults.. 25
Hardwired PWM Response to Timing Faults ......26
External Faults....................................................26
Fault Handling.....................................................26
Status Registers and ALERT Masking.................26
FAULT Pin I/O......................................................28
Fault Logging......................................................28
Factory Default Operation...................................31
Serial Interface ...................................................32
Serial Bus Addressing ........................................32
Serial Bus Timeout .............................................36
MFR_RESET....................................................... 74
38821f
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For more information www.linear.com/LTC3882-1
LTC3882-1
Table oF conTenTs
PWM Configuration ................................................75
FREQUENCY_SWITCH........................................75
MFR_PWM_CONFIG_LTC3882-1.......................76
MFR_CHAN_CONFIG_LTC3882-1 ......................77
MFR_PWM_MODE_LTC3882-1 .........................78
Input Voltage and Limits.........................................79
VIN_ON ..............................................................79
VIN_OFF .............................................................79
VIN_OV_FAULT_LIMIT........................................79
VIN_UV_WARN_LIMIT .......................................79
Output Voltage and Limits ......................................80
VOUT_MODE ......................................................80
VOUT_COMMAND..............................................80
MFR_VOUT_MAX ...............................................80
VOUT_MAX ........................................................81
MFR_VOUT_AVP ................................................81
VOUT_MARGIN_HIGH........................................81
VOUT_MARGIN_LOW.........................................81
VOUT_OV_FAULT_LIMIT ....................................81
VOUT_OV_WARN_LIMIT....................................82
VOUT_UV_WARN_LIMIT....................................82
VOUT_UV_FAULT_LIMIT ....................................82
Output Current and Limits ......................................83
IOUT_CAL_GAIN ................................................83
MFR_IOUT_CAL_GAIN_TC.................................83
IOUT_OC_FAULT_LIMIT .....................................83
IOUT_OC_WARN_LIMIT.....................................83
Output Timing, Delays, and Ramping .....................84
MFR_RESTART_DELAY......................................84
TON_DELAY .......................................................84
TON_RISE ..........................................................84
TON_MAX_FAULT_LIMIT...................................85
VOUT_TRANSITION_RATE .................................85
TOFF_DELAY ......................................................85
TOFF_FALL .........................................................85
TOFF_MAX_WARN_LIMIT..................................85
External Temperature and Limits............................86
MFR_TEMP_1_GAIN ...........................................86
MFR_TEMP_1_OFFSET.......................................86
OT_FAULT_LIMIT................................................86
OT_WARN_LIMIT ...............................................86
UT_FAULT_LIMIT................................................87
Status Reporting.....................................................87
STATUS_BYTE....................................................87
STATUS_WORD..................................................88
STATUS_VOUT ...................................................88
STATUS_IOUT ....................................................89
STATUS_INPUT..................................................89
STATUS_TEMPERATURE....................................89
STATUS_CML .....................................................90
STATUS_MFR_SPECIFIC....................................90
MFR_PADS_LTC3882-1 .....................................91
MFR_COMMON..................................................91
CLEAR_FAULTS..................................................92
Telemetry................................................................92
READ_VIN ..........................................................92
MFR_VIN_PEAK .................................................93
READ_VOUT.......................................................93
MFR_VOUT_PEAK ..............................................93
READ_IOUT........................................................93
MFR_IOUT_PEAK...............................................93
READ_POUT.......................................................93
READ_TEMPERATURE_1 ...................................94
MFR_TEMPERATURE_1_PEAK ..........................94
READ_TEMPERATURE_2...................................94
MFR_TEMPERATURE_2_PEAK..........................94
READ_DUTY_CYCLE ..........................................94
READ_FREQUENCY............................................94
MFR_CLEAR_PEAKS .........................................94
Fault Response and Communication.......................95
VIN_OV_FAULT_RESPONSE...............................95
VOUT_OV_FAULT_RESPONSE............................96
VOUT_UV_FAULT_RESPONSE............................96
IOUT_OC_FAULT_RESPONSE.............................97
OT_FAULT_RESPONSE.......................................98
UT_FAULT_RESPONSE.......................................98
MFR_OT_FAULT_RESPONSE .............................98
TON_MAX_FAULT_RESPONSE..........................99
MFR_RETRY_DELAY..........................................99
SMBALERT_MASK ...........................................100
MFR_FAULT_PROPAGATE_LTC3882-1 ............ 101
MFR_FAULT_RESPONSE.................................. 101
EEPROM User Access........................................... 102
MFR_FAULT_LOG............................................. 102
MFR_FAULT_LOG_CLEAR................................ 102
STORE_USER_ALL .......................................... 103
RESTORE_USER_ALL...................................... 103
MFR_COMPARE_USER_ALL ........................... 103
MFR_FAULT_LOG_STORE ............................... 103
MFR_EE_xxxx.................................................. 103
USER_DATA_0x ............................................... 103
Unit Identification .................................................104
MFR_ID ............................................................104
MFR_MODEL....................................................104
MFR_SERIAL....................................................104
Typical Applications.................................... 105
Package Description ................................... 107
Typical Application ..................................... 108
Related Parts............................................ 108
38821f
3
For more information www.linear.com/LTC3882-1
LTC3882-1
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
V
CC
Supply Voltage .................................... –0.3V to 15V
VINSNS Voltage ......................................... –0.3V to 40V
–
V
V
...................................................... –0.3V to 1V
SENSEn
40 39 38 37 36 35 34 33 32 31
+
+
–
, I
, I
........................ –0.3V to 6V
SENSEn SENSEn SENSEn
COMP0
TSNS0
TSNS1
VINSNS
1
2
3
4
5
6
7
8
9
30
29
28
I
AVG1
FBn, COMPn, TSNSn, I
, I
...... –0.3V to 3.6V
AVG_GND AVGn
FB1
SYNC, FAULTn, PGOODn, SHARE_CLK........–0.3V to 3.6V
SCL, SDA, RUNn, ALERT........................... –0.3V to 5.5V
ASELn, VOUTn_CFG, FREQ_CFG,
COMP1
27 PGOOD1
26 PWM1
41
GND
I
AVG_GND
PGOOD0
PWM0
SYNC
SCL
25
24
23
22
21
V
V
CC
PHAS_CFG.............................................. –0.3V to 2.75V
DD33
PWMn, V
DD33
.................................................. (Note 13)
............................................................... (Note 14)
DD25
SHARE_CLK
V
V
DD25
Operating Junction Temperature
SDA 10
PHAS_CFG
(Notes 2, 3).......................................... –40°C to 125°C*
Storage Temperature Range ................ –65°C to 125°C*
11 12 13 14 15 16 17 18 19 20
*See Derating EEPROM Retention at Temperature in the
ApplicationsInformationsectionforjunctiontemperatures
in excess of 125°C.
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
T
= 125°C, θ = 33°C/W , θ = 2.5°C/W
JA JC
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
JMAX
orDer inForMaTion
LEAD FREE FINISH
LTC3882EUJ-1#PBF
LTC3882IUJ-1#PBF
TAPE AND REEL
PART MARKING*
LTC3882UJ-1
LTC3882UJ-1
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3882EUJ-1#TRPBF
LTC3882IUJ-1#TRPBF
–40°C to 125°C
–40°C to 125°C
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
38821f
4
For more information www.linear.com/LTC3882-1
LTC3882-1
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
–
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VCC = 5V, VSENSE0+ = VSENSE1+ = 1.8V, VSENSE0
VSENSE1– = IAVG_GND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified.
=
SYMBOL
IC Supply
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
V
V
V
V
V
Voltage Range
V
V
V
= Internal LDO
4.5
3
13.8
3.6
3
V
V
CC
CC
DD33
l
l
Voltage Range
= V
(Note 6)
DD33
DD33_EXT
UVLO
DD33
CC
Undervoltage Lockout Threshold
Rising
Hysteresis
V
mV
DD33
42
32
70
I
t
IC Operating Current
mA
ms
Q
Controller Initialization Time
Delay from RESTORE_USER_ALL, MFR_RESET or
INIT
V
> V
Until TON_DELAY Can Begin
UVLO
DD33
V
Linear Regulator
DD33
DD33
DD33
V
V
Regulator Output Voltage
Current Limit
V
≥ 4.5V
CC
3.2
3.3
3.4
V
DD33
DD33
I
V
V
DD33
V
DD33
= 2.8V
= 0V
85
40
mA
mA
V
Linear Regulator
DD25
DD25
DD25
V
V
V
Regulator Output Voltage
Current Limit
2.25
3
2.5
95
2.75
38
V
DD25
DD25
I
mA
PWM Control Loops
VINSNS
V
IN
Sense Voltage Range
V
R
VINSNS Input Resistance
Range 0 Maximum V
278
kΩ
VINSNS
OUT_R0
V
5.25
0.2
V
%
OUT
Range 0 Set Point Error (Note 7)
0.6V ≤ V
0.6V ≤ V
≤ 5V
OUT
OUT
l
l
≤ 5V
–0.5
–0.5
0.5
0.5
%
Range 0 Set Point Resolution
1.375
mV
V
Range 1 Maximum V
2.65
0.2
V
%
OUT_R1
VSENSE
OUT
Range 1 Set Point Error (Note 7)
0.6V ≤ V
0.6V ≤ V
≤ 2.5V
≤ 2.5V
OUT
OUT
%
Range 1 Set Point Resolution
0.6875
mV
+
–
I
V
V
Input Current
V
SENSE
V
SENSE
= 5.5V
= 0V
235
–335
µA
µA
SENSE
V
Line Regulation, No Output Servo
4.5V ≤ V ≤ 13.2V (See Test Circuit)
–0.02
0.02
–96
%/V
mV
LINEREG
CC
CC
l
AVP
AVP ∆V
AVP = 10%, VOUT_COMMAND = 1.8V,
–118 –108
OUT
I
Differential Step 3mV to 12mV
SENSE
with IOUT_OC_WARN_LIMIT = 15mV
A
Error Amplifier Open-Loop Voltage Gain
Error Amplifier Slew Rate
87
9.5
30
dB
V/µs
MHz
V(OL)
SR
f
I
Error Amplifier Bandwidth
(Note 12)
0dB
Error Amplifier Output Current
Sourcing
Sinking
–2.6
34
mA
mA
COMP
+
l
l
R
Resistance Between V
and FB
Range 0
Range 1
52
37
67
49
83
61
kΩ
kΩ
VSFB
SENSE
V
I
I
I
Differential Input Range
Input Current
70
0.1
175
mV
µA
ISENSE
SENSE
SENSE
I
I
0V ≤ V ≤ 5.5V
–1
1
ISENSE
PIN
Current Sense Offset
Referred to I
Inputs
Inputs
µV
µV
AVG_VOS
AVG
SENSE
l
–600
650
V
SIOS
Slave Current Sharing Offset
SYNC Frequency Error
Referred to I
300
µV
µV
SENSE
l
l
–800
–10
700
10
f
250kHz ≤ f
≤ 1.25MHz
SYNC
%
38821f
5
SYNC
For more information www.linear.com/LTC3882-1
LTC3882-1
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
–
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VCC = 5V, VSENSE0+ = VSENSE1+ = 1.8V, VSENSE0
VSENSE1– = IAVG_GND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified.
=
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
Input Voltage Supervisor
l
V
Input ON/OFF Threshold Error
15V ≤ V
≤ 35V
IN_ON
–2
2
%
ON_TOL
N
VON
Input ON/OFF Threshold Resolution
143
mV
Output Voltage Supervisors
V
V
Range 0 Maximum Threshold
Range 0 Error
5.5
11
V
%
UVOV_R0
l
l
2V ≤ V
1V ≤ V
≤ 5V (Falling for UV and Rising for OV)
≤ 2.5V (Falling for UV and Rising for OV)
–1
–1
1
OUT
OUT
Range 0 Threshold Resolution
Range 0 Threshold Hysteresis
mV
mV
54
Range 1 Maximum Threshold
Range 1 Error
Range 1 Threshold Resolution
Range 1 Threshold Hysteresis
2.75
5.5
V
%
mV
mV
UVOV_R1
1
27
Output Current Supervisors
+
+
+
–
–
–
l
l
l
V
Output Current Limit Tolerance
SENSE
15mV < I
30mV < I
50mV < I
– I
– I
– I
≤ 30mV
≤ 50mV
≤ 70mV
–1.7
–2.5
–5.2
1.7
2.5
5.2
mV
mV
mV
ILIM_TOL
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
+
–
I
– I
SENSE
+
–
N
lLIM
I
– I
Threshold Resolution
1LSB
0.4
10
mV
SENSE
SENSE
ADC Readback Telemetry (Note 8)
N
VINSNS Readback Resolution
(Note 9)
Bits
VIN
V
VINSNS Total Unadjusted Readback Error 4.5V ≤ VINSNS ≤ 38V
0.5
2
%
%
IN_TUE
l
N
PWM Duty Cycle Resolution
(Note 9)
PWM Duty Cycle = 12.5%
10
Bits
%
DC
DC
PWM Duty Cycle Total Unadjusted
Readback Error
–2
2
TUE
N
V
V
Readback Resolution
244
0.2
µV
VOUT
OUT
OUT
V
Total Unadjusted Readback Error
0.6V ≤ V
≤ 5.5V, Constant Load
%
%
OUT_TUE
OUT
l
–0.5
0.5
N
I
Readback Resolution
(Note 9)
0mV ≤ |I
10
15.625
31.25
62.5
Bits
µV
µV
µV
µV
ISENSE
OUT
+
–
LSB Step Size (at I
)
– I
| < 16mV
SENSE
SENSE
16mV ≤ |I
32mV ≤ |I
SENSE
+
–
– I
| < 32mV
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
+
–
– I
| < 63.9mV
+
–
63.9mV ≤ |I
– I
| ≤ 70mV
125
+
–
l
I
I
I
I
Total Unadjusted Readback Error
Zero-Code Offset Voltage
|I
– I
| ≥ 6mV, 0V ≤ V ≤ 5.5V
OUT
–1
1
%
µV
°C
SENSE_TUE
OUT
OUT
SENSE
SENSE
32
SENSE_OS
N
TEMP
Temperature Resolution
0.25
T
External Temperature Total Unadjusted
Readback Error
TSNS0, TSNS1 ≤ 1.85V (Note 10)
MFR_PWM_MODE_LTC3882-1[6] = 0
MFR_PWM_MODE_LTC3882-1[6] = 1
EXT_TUE
l
l
–3
–7
3
7
°C
°C
T
Internal Temperature Total Unadjusted
Readback Error
Internal Diode (Note 10)
1
°C
INT_TUE
t
Update Rate
(Note 11)
100
ms
CONVERT
Internal EEPROM (Notes 4, 6)
Endurance
Retention
Number of Write Operations
Stored Data Retention
0°C ≤ T ≤ 85°C During All Write Operations
10,000
10
Cycles
Years
s
J
T ≤ 125°C
J
Mass Write Time STORE_USER_ALL Execution Duration
0°C ≤ T ≤ 85°C During All Write Operations
0.2
2
J
38821f
6
For more information www.linear.com/LTC3882-1
LTC3882-1
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
–
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VCC = 5V, VSENSE0+ = VSENSE1+ = 1.8V, VSENSE0
VSENSE1– = IAVG_GND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified.
=
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
Digital Inputs (SCL, SDA, RUNn, FAULTn, SYNC, SHARE_CLOCK)
l
l
V
V
Input High Voltage
Input Low Voltage
SCL, SDA, RUN0, RUN1, FAULT0, FAULT1
2.0
1.8
V
V
IH
SYNC, SHARE_CLK
l
l
SCL, SDA, RUN0, RUN1, FAULT0, FAULT1
SYNC, SHARE_CLK
1.4
0.6
V
V
IL
V
C
Input Hysteresis
Input Capacitance
SCL, SDA
80
mV
pF
HYST
IN
SCL, SDA, RUN0, RUN1, FAULT0, FAULT1, SYNC,
SHARE_CLK (Note 12)
10
t
Input Digital Filter Delay
FAULT0, FAULT1
RUN0, RUN1
3
10
µs
µs
FILT
Digital Outputs (SCL, SDA, RUNn, FAULTn, SYNC, SHARE_CLOCK, ALERT, PWMn, PGOODn)
l
V
Output Low Voltage
I
= 3mA; SDA, SCL, RUN0, RUN1, FAULT0,
SINK
0.2
0.4
0.3
V
OL
FAULT1, SYNC, SHARE_CLK, ALERT,
l
l
I
= 2mA; PWMn, PGOODn
V
V
SINK
V
PWMn Output High Voltage
I
= 2mA
2.7
OH
SOURCE
I
Output Leakage Current
0V ≤ PWM0, PWM1, PGOOD0, PGOOD1 ≤ V
–1
–5
1
5
µA
µA
LKG
DD33
0V ≤ FAULT0, FAULT1, SYNC, SHARE_CLK ≤ 3.6V
0V ≤ RUN0, RUN1 ≤ 5.5V
l
0V ≤ SCL, SDA, ALERT ≤ 5.5V
–5
5
µA
ns
ns
t
t
PWMn Output Rise Time
PWMn Output Fall Time
C
C
= 30pF, 10% to 90%
= 30pF, 90% to 10%
5
4
RO
LOAD
LOAD
FO
Serial Bus Timing
l
l
l
f
t
t
Serial Bus Operating Frequency
10
1.3
0.6
400
kHz
µs
SMB
Bus Free Time Between Stop and Start
BUF
Hold Time After (Repeated) Start
Condition. After This Period, the First
Clock Is Generated
µs
HD,STA
l
l
t
t
t
Repeated Start Condition Setup Time
Stop Condition Setup Time
0.6
0.6
µs
µs
SU,STA
SU,STO
HD,DAT
Data Hold Time:
Receiving Data
Transmitting Data
l
l
0
0.3
ns
µs
0.9
l
l
l
l
t
t
t
t
Input Data Setup Time
Clock Low Timeout
100
25
ns
ms
µs
SU,DAT
TIMEOUT
LOW
35
Serial Clock Low Period
Serial Clock High Period
1.3
0.6
10000
µs
HIGH
38821f
7
For more information www.linear.com/LTC3882-1
LTC3882-1
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Note 6: Minimum EEPROM endurance, retention and mass write time
Note 2: The LTC3882-1 is tested under pulsed load conditions such that
specifications apply when writing data with 3.15V ≤ V
EEPROM read commands are valid over the entire specified V
operating range.
≤ 3.45V.
DD33
DD33
T ≈ T . The LTC3882-1E is guaranteed to meet performance specifications
J
A
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3882-1I is guaranteed
over the full –40°C to 125°C operating junction temperature range.
Note 7: Specified V
error with AVP = 0% requires servo mode to be
OUT
set with MFR_PWM_MODE_LTC3882-1 command bit 6. Performance is
guaranteed by testing the LTC3882-1 in a feedback loop that servos V
to a specified value.
Note 8: ADC tested with PWMs disabled. Comparable capability
demonstrated by in-circuit evaluations. Total Unadjusted Error includes all
gain and linearity errors, as well as offsets.
OUT
Junction temperature T is calculated in °C from the ambient temperature
J
T and power dissipation P according to the formula:
A
D
T = T + (P • θ )
JA
J
A
D
where θ is the package thermal impedance. Note that the maximum
JA
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors. Refer to the
Applications Information section.
Note 9: Internal 32-bit calculations using 16-bit ADC results are limited to
10-bit resolution by PMBus Linear 11-bit data format.
Note 10: Limits guaranteed by TSNS voltage and current measurements
during test, including ADC readback.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: EEPROM endurance, retention and mass write times are
guaranteed by design, characterization and correlation with statistical
process controls. Minimum retention applies only for devices cycled less
than the minimum endurance specification. EEPROM read commands
(e.g. RESTORE_USER_ALL) are valid over the entire specified operating
junction temperature range.
Note 11: Data conversion is done in round robin fashion. All inputs signals
are continuously scanned in sequence resulting in a typical conversion
latency of 100ms.
Note 12: Guaranteed by design.
Note 13: Do not apply a voltage or current source directly to these pins.
They should only be connected to passive RC loads, otherwise permanent
damage may occur.
Note 14: Do not apply a voltage source to this pin unless shorted to V
.
CC
See Electrical Characteristics for applicable limits beyond which permanent
damage may occur.
38821f
8
For more information www.linear.com/LTC3882-1
LTC3882-1
Typical perForMance characTerisTics
LTC3882-1 1.0V Regulated Output
vs Temperature
Typical LTC3882-1 Output Voltage
Distribution at 0°C
Typical LTC3882-1 Output Voltage
Distribution at 105°C
1.001
1.0005
1.0
1000
900
800
700
600
500
400
300
200
100
0
1200
1000
800
600
400
200
0
1078 UNITS
VOUT_COMMAND = 1.0V
DIGITAL SERVO
V
= 12V
1094 UNITS
IN
VOUT_COMMAND = 1.0V
DIGITAL SERVO ENGAGED
VOUT_COMMAND = 1.0V
DIGITAL SERVO
ENGAGED
ENGAGED
I
= 6.5A
OUT
0.9995
0.999
0.9985
–5
15
35
55
(°C)
75
95
–1.25 –1 –0.75–0.5–0.25 0 0.25 0.5 0.75
ERROR (mV)
1
1.25
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
T
V
V
OUT
ERROR (mV)
A
OUT
38821 G01
38821 G01a
38821 G02
Efficiency and Loss vs Load
(2-Phase Using FDMF5820DC
DRMOS)
Efficiency vs Load Current
(1-Phase Using D12S1R880A
Power Block)
Efficiency vs Load Current
(3-Phase Using D12S1R845A
Power Block)
92
91
90
89
88
87
86
85
84
83
82
81
80
13
95
90
85
80
75
94
92
90
88
86
84
82
80
V
= 12V
V
V
= 12V
IN
IN
OUT
= 1.5V
11
9
7
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
5
V
V
= 12V
= 1V
3
IN
OUT
SYNC = 500kHz
1
0
10 20 30 40 50 60 70 80
0
10
20
30
40
0
10
20
30
40
50
60
70
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
38821 G03
38821 G04
38821 G05
Typical Distribution of Slave
IOUT Offset (Not Including DCR
Mismatch)
Typical Distribution of Slave
Typical Distribution of Slave
IOUT Offset (Not Including DCR
Mismatch)
IOUT Offset (Not Including DCR
Mismatch)
4000
3500
3000
2500
2000
1500
1000
500
3500
3000
2500
2000
1500
1000
500
4500
4000
3500
3000
2500
2000
1500
1000
500
9595 UNITS
FROM 3 LOTS
8593 UNITS
FROM 3 LOTS
11783 UNITS
FROM 3 LOTS
T
T
= –40°C
= –22°C
T
= 38°C
T = 121°C
A
J
J
J
CHO MASTER
CHO MASTER
CHO MASTER
0
0
0
–400–300–200–100
0
100 200 300 400
–400–300–200–100
0
100 200 300 400
–300–200–100
CH1 I OFFSET TO IDEAL (µV)
SENSE
38821 G08
0
100 200 300 400 500
CH1 I
OFFSET TO IDEAL (µV)
CH1 I
OFFSET TO IDEAL (µV)
SENSE
SENSE
38821 G06
38821 G07
38821f
9
For more information www.linear.com/LTC3882-1
LTC3882-1
Typical perForMance characTerisTics
3-Phase DC Output Current
Sharing (Using D12S1R845A
Power Block
Load Step Transient Current
Sharing (Using FDMF6707B
DrMOS)
Load Dump Transient Current
Sharing (Using FDMF6707B
DrMOS)
20
18
16
14
12
10
8
CHANNEL 1
CHANNEL 2
CHANNEL 3
I
I
OUT
OUT
20A/DIV
20A/DIV
V
OUT
V
20mV/DIV
OUT
20mV/DIV
I
, I
I
, I
L1 L2
L1 L2
10A/DIV
10A/DIV
6
38821 G10
38821 G11
4
V
V
= 1V
5µs/DIV
V
V
= 1V
5µs/DIV
OUT
IN
OUT
IN
= 12V
= 12V
2
SYNC = 500kHz
L = 320nH
SYNC = 500kHz
L = 320nH
0
0
10 20 30 40 50 60 70 80
TOTAL RAIL CURRENT (A)
38821 G09
Efficiency and Power Loss vs
Input Voltage
(1-Phase Using LTC4449)
1-Phase Single Cycle Response
(Using D12S1R860A Power Block
with COUT = 6 × 100µF X5R 1210)
3-Phase Transient Response
(Using D12S1R860A Power Block)
100
98
96
94
92
90
88
86
84
82
80
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 1.8V
O
V
OUT
(20mV/DIV)
I
OUT
(10A/DIV)
V
SW
(10V/DIV)
V
OUT
(10mV/DIV)
25mV
P-P
I
OUT
(10A/DIV)
38821 G13
38821 G14
100µs/DIV
2µs/DIV
POWER FET: BSC050N04LS G
SYNC FET: BSC010N04LS
V
V
= 0.9V/90A
V
= 1V/25A
OUT
OUT
IN
= 12V
V
= 12V
IN
5
10
15
V
20
(V)
25
30
SYNC = 500kHz
L = 210nH
SYNC = 1MHz
L = 210nH
IN
38821 G12
3+1 Channel Crosstalk
(Using D12S1R845A Power
Blocks)
Load Step Transient Response
Using AVP
Line Step Transient Response
(1-phase Using LTC4449)
V
OUT0
I
O
(1-PHASE)
20mV/DIV
10A/DIV
7V
V
IN
2V/DIV
V
OUT1
(3-PHASE)
20mV/DIV
1.8V
25%
LOAD STEP
I
OUT1
V
10A/DIV
OUT
V
OUT
50mV/DIV
10mV/DIV
38821 G15
38821 G16
38821 G17
100µs/DIV
200µs/DIV
200µs/DIV
38821f
10
For more information www.linear.com/LTC3882-1
LTC3882-1
Typical perForMance characTerisTics
Soft-Start Ramp
Start-Up Into a Prebiased Load
Soft-Off Ramp
RUN
2V/DIV
V
V
OUT
0.5V/DIV
0V
OUT
0.5V/DIV
V
OUT
I
, I
I , I
L1 L2
10A/DIV
L1 L2
1V/DIV
10A/DIV
38821 G18
38821 G19
38821 G20
5ms/DIV
TOFF_DELAY = 10ms
V
IN
= 12V
1ms/DIV
V
IN
= 12V
1ms/DIV
TOFF_FALL = 5ms
Regulated Output vs Temperature
VOUT_COMMAND INL
VOUT_COMMAND DNL
1.8000
1.7995
1.7990
1.7985
1.7980
1.7975
1.7970
1.5
1.0
0.5
0
1.0
0.8
VOUT_COMMAND = 1.8V
DIGITAL SERVO OFF
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–0.5
–1.0
–40 –20
0
20 40 60 80 100 120
0.3
1.1
1.9
2.7
3.5
(V)
4.3
5.1 5.5
0.3
1.1
1.9
2.7
3.5
(V)
4.3
5.1 5.5
TEMPERATURE (°C)
V
V
OUT
OUT
38821 G01a
38821 G01
38821 G02
Output Overvoltage Threshold
Error vs Temperature
Output Overcurrent Threshold
Error vs Temperature
PWM Frequency vs Temperature
0.10
0.05
0
500.2
500.1
500.0
499.9
499.8
499.7
499.6
499.5
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.05
–0.10
–0.15
–0.2
VOUT_OV_FAULT_LIMIT = 2V
V
RANGE = 1
FREQUENCY_SWITCH = 500kHz
OUT
–0.4
–40 –20
0
20 40 60 80 100 120
–40 –20
0
20 40 60 80 100 120
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
38821 G21
38821 G23
38821 G22
38821f
11
For more information www.linear.com/LTC3882-1
LTC3882-1
Typical perForMance characTerisTics
VIN(SNS) ADC TUE
VOUT ADC TUE
IOUT ADC TUE
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
0.40
0.30
0.20
0.10
0
8
6
4
2
0
–0.10
–0.20
–0.30
–0.40
–2
–4
–6
–8
0
5
10 15 20 25 30 35 40
VINSNS (V)
4.5
5
5.5
0
5
10
15
20
0.5
1
1.5
2
2.5
V
3
3.5
(V)
4
OUTPUT CURRENT (A)
OUT
38821 G24
38821 G25
38821 G26
SHARE_CLK Frequency vs
Temperature
IC Operating Current vs
Temperature
Temperature ADC TUE
1.0
0.8
31.0
30.8
30.6
30.4
30.2
30.0
29.8
29.6
29.4
110
105
100
95
V
CC
= 14V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
90
–40 –20
0
20 40 60 80 100 120
–50 –30 –10 10 30 50 70 90 110
–45 –25 –5 15 35 55 75 95 115
TEMPERATURE (°C)
TEMPERATURE (°C)
ACTUAL TEMPERATURE (°C)
38821 G29
38821 G28
38821 G27
38821f
12
For more information www.linear.com/LTC3882-1
LTC3882-1
pin FuncTions
frequency with a 125ns pulse width. A pull-up resistor to
3.3V is required in the application if SYNC is driven by
any LTC3882-1. Minimize the capacitance on this line to
ensure its time constant is fast enough for the application.
COMP0/COMP1 (Pin 1/Pin 29): Error Amplifier Outputs.
PWM duty cycle increases with this control voltage. These
are true low impedance outputs and cannot be directly
connectedtogetherwhenactive.ForPolyPhaseoperation,
wiringFBtoV
willthree-statetheerroramplifieroutput
DD33
SCL (Pin 9): Serial Bus Clock Input. A pull-up resistor to
3.3V is required in the application.
of that channel, making it a slave. PolyPhase control is
then implemented in part by connecting all slave COMP
pins together to one master error amplifier output.
SDA (Pin 10): Serial Bus Data Input and Output. A pull-up
resistor to 3.3V is required in the application.
TSNS0/TSNS1 (Pin 2/Pin 3): External Temperature Sense
Inputs. The LTC3882-1 supports two methods of calcula-
tion of external temperature based on forward-biased P/N
junctions between these pins and GND.
ALERT (Pin 11): Open-Drain Status Output. This pin may
be connected to the system SMBALERT wire-AND inter-
rupt signal and should be left open if not used. If used, a
pull-up resistor is required in the application. Operating
VINSNS (Pin 4): V Supply Sense. Connect to the V
IN
IN
voltage range is GND to V
.
DD33
power supply to provide line feedforward compensation.
FAULT0/FAULT1 (Pin 12/Pin 13): Programmable Digital
Inputs and Open-Drain Outputs for Fault Sharing. Used
forchannel-to-channelfaultcommunicationandpropaga-
tion. These pins should be left open if not used. If used,
a pull-up resistor to 3.3V is required in the application.
A change in V immediately modulates the input to the
IN
PWM comparator and inversely changes the pulse width
to provide excellent transient line regulation and fixed
modulator voltage gain. An external lowpass filter can be
added to this pin to prevent noisy signals from affecting
the loop gain.
RUN0/RUN1 (Pin 14/Pin 15): Run Control Inputs and
Open-Drain Outputs. A voltage above 2V is required on
these pins to enable the respective PWM channel. The
LTC3882-1 will drive these pins low under certain reset/
restart conditions regardless of any PMBus command
settings. A pull-up resistor to 3.3V is required in the ap-
plication.
I
(Pin 5): I
Ground Reference. The same
AVG
AVG_GND
I
should be shared between all channels of a
AVG_GND
PolyPhaserailandconnectedtosystemgroundatasingle
point. I
may be wired directly to GND on ICs that
AVG_GND
do not share phases with other chips.
PGOOD/PGOOD1 (Pin 6/Pin 27): Power Good Indicator
Open-DrainOutputs.Theseoutputsaredrivenlowthrough
a 30µs filter when the respective channel output is below
its programmed UV fault limit or above its programmed
OV fault limit. If used, a pull-up resistor is required in the
ASEL0/ASEL1 (Pin 16/Pin 17): Serial Bus Address Select
Pins.Connectoptional1%resistordividersbetweenV
DD25
and GND to these pins to select the serial bus interface
address. Refer to the Applications Information section
for more detail.
application. Operating voltage range is GND to V
.
DD33
V
/V
(Pin 18/Pin 19): Output Voltage
OUT0_CFG OUT1_CFG
PWM0/PWM1 (Pin 7/Pin 26): PWM Three-State Control
Outputs. These pins provide single-wire PWM switching
control for each channel to an external gate driver, DrMOS
Configuration Pins. Connect optional 1% resistor divid-
ers between V and GND to these pins to select the
DD25
output voltage for each channel. Refer to the Applications
Information section for more detail.
or power block. Operating voltage range is GND to V
.
DD33
SYNC (Pin 8): External Clock Synchronization Input and
Open-Drain Output. If desired, an external clock can be
applied to this pin to synchronize the internal PWM chan-
nels. If the LTC3882-1 is configured as a clock master, this
pin will also pull to ground at the selected PWM switching
FREQ_CFG(Pin20):FrequencyConfigurationPin.Connect
an optional 1% resistor divider between V
to this pin to configure PWM switching frequency. Refer
to the Applications Information section for more detail.
and GND
DD25
38821f
13
For more information www.linear.com/LTC3882-1
LTC3882-1
pin FuncTions
PHAS_CFG (Pin 21): Phase Configuration Pin. Connect
an optional 1% resistor divider between V
to this pin to configure the phase of each PWM channel
relative to SYNC. Refer to the Applications Information
section for more detail.
+
+
V
/V
(Pin36/Pin33):PositiveOutputVoltage
SENSE0 SENSE1
and GND
Sense Inputs. These pins must still be properly connected
on slave channels for accurate output current telemetry.
DD25
–
–
I
/I
(Pin 37/Pin 32): Current Sense Ampli-
SENSE0 SENSE1
fier Inputs. The (–) inputs to the amplifiers are normally
connected to the low side of a DCR sensing network or
output current sense resistor for each phase.
V
DD25
(Pin 22): Internal 2.5V Regulator Output. Bypass
this pin to GND with a low ESR 1µF capacitor. Do not load
thispinwithexternalcurrentbeyondthatrequiredforlocal
LTC3882-1 configuration pins, if any.
+
+
I
/I
(Pin 38/Pin 31): Current Sense Ampli-
SENSE0 SENSE1
fier Inputs. The (+) inputs are normally connected to the
high side of an output current sense resistor or the R-C
midpoint of a parallel DCR sense circuit.
SHARE_CLK (Pin 23): Share Clock Open-Drain Output
(bussed). Share Clock, nominally 100kHz, is used to
sequence multiple rails in a power system utilizing more
than one LTC PSM controller. A pull-up resistor is required
in the application. Minimize the capacitance on this line to
ensurethetimeconstantisfastenoughfortheapplication.
I
/I
(Pin39/Pin31):AverageCurrentControlPins.
AVG0 AVG1
A capacitor connected between these pins and I
storesavoltageproportionaltotheaverageoutputcurrent
of the master channel. PolyPhase control is then imple-
mented in part by connecting all slave I
to the master I
on channels that control single-phase outputs. Operating
voltage range is GND to 2.1V.
AVG_GND
Operating voltage range is GND to V
.
DD33
pins together
AVG
V
(Pin24):Internal3.3VRegulatorOutput.Bypassthis
output. This pin should be left open
DD33
AVG
pin to GND witha lowESR 2.2µF capacitor. TheLTC3882-1
may also be powered from an external 3.3V rail attached
to this pin, if also shorted to V . Do not overload this pin
CC
FB0/FB1(Pin40/Pin30):ErrorAmplifierInvertingInputs.
These pins provide an internally scaled version of the
output voltage for use in loop compensation. Refer to the
Applications Information section for additional details on
compensatingtheoutputvoltagecontrolloopwithexternal
components.
with external system current. Local pull-up resistors for
the LTC3882-1 itself may be powered from V
. Refer
DD33
to the Applications Information section for more detail.
V
(Pin 25): 3.3V Regulator Input. Bypass this pin to
CC
GND with a capacitor (0.1µF to 1µF ceramic) in close
proximity to the IC.
–
GND (Exposed Pad Pin 41): Ground and V
. All
SENSE1
–/
–
V
V
(Pin 35/Pin 34): Negative Output
small-signal and compensation components should
connect to this pad, which also serves as the negative
voltage sense input for channel 1. The exposed pad must
be soldered to a suitable PCB copper ground plane for
proper electrical operation and to obtain the specified
package thermal resistance.
SENSE0
SENSE1
Voltage Sense Inputs. These pins must still be properly
connected on slave channels for accurate output current
telemetry.
38821f
14
For more information www.linear.com/LTC3882-1
LTC3882-1
block DiagraM
ROM
RAM
EEPROM
VINSNS
PWM0
R_CONFIG
PMBus
I
AVG0
MCU AND
CUSTOM
LOGIC
SHARE_CLK
I
SENSE0
2.5V
REGULATOR
12-BIT
DAC
V
SENSE0
PGOOD0
PWM0
SYNC
PLL
V
REF
VOLTAGE
REFERENCE
I
AVG_GND
3.3V
REGULATOR
V
CC
PWM1
V
DD33
PGOOD1
V
BIAS AND
HOUSEKEEPING
SENSE1
12-BIT
DAC
PWM1
I
SENSE1
VINSNS
PWM0
I
AVG1
INTERNAL DATA BUS
V
SENSE0
VINSNS
16-BIT
ADC
I
SENSE0
ANALOG
MUX
TSNS0
PWM1
INTERNAL
TEMPERATURE
V
SENSE1
I
SENSE1
3882-1 BD
TSNS1
38821f
15
For more information www.linear.com/LTC3882-1
LTC3882-1
(Channel 0 Example)
TesT circuiT
LTC3882-1
1.024V
V
R
12-BIT
D/A
DIGITAL
+
–
EA
–
+
V
V
FB0
40
COMP0
1
SENSE0
SENSE0
35
36
+
LTC1055
–
TARGET = VOUT_COMMAND
1V
38821 TC
TiMing DiagraM
SDA
t
r
t
SU(DAT)
t
t
SP
t
HD(SDA)
r
t
t
t
f
t
f
BUF
LOW
SCL
t
t
t
SU(STO)
HD(STA)
SU(STA)
t
t
HIGH
HD(DAT)
38821 TD
START
CONDITION
REPEATED START
CONDITION
STOP
START
CONDITION CONDITION
operaTion
Overview
Major features include:
The LTC3882-1 is a dual channel/dual phase, constant
frequency analog voltage mode controller for DC/DC step-
down applications. It features a PMBus compliant digital
interface for monitoring and control of important power
system parameters. The chip operates from an IC power
supplybetween3Vand13.2Vandisintendedforconversion
• Digitally Programmable Output Voltage
• Digitally Programmable Output Current Limit
• Digitally Programmable Input Voltage Supervisor
• Digitally Programmable Output Voltage Supervisors
• Digitally Programmable Switching Frequency
• Digitally Programmable On and Off Delay Times
• Digitally Programmable Soft-Start/Stop
from V between 3V and 38V to output voltages between
IN
0.5V and 5.25V. It is designed to be used in a switching
architecture with external FET drivers, including higher
level integrations such as non-isolated power blocks.
38821f
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For more information www.linear.com/LTC3882-1
LTC3882-1
operaTion
• Operating Condition Telemetry
Main Control Loop
• PhaseLockedLoopforSynchronousPolyPhaseOpera-
The LTC3882-1 utilizes constant frequency voltage mode
control with leading-edge modulation. This provides
improved response to a load step increase, especially at
tion (2, 3, 4, 6, or 8 phases)
• Fully Differential Load Sense
larger V /V
ratios found in the low voltage, high cur-
IN OUT
• Non-Volatile Configuration Memory
rent solutions demanded by modern digital subsystems.
The LTC3882-1 leading-edge modulation architecture
doesnothaveaminimumon-timerequirement. Minimum
duty cycle will be determined by performance limits of
the external power stage. The IC is also capable of active
voltage positioning (AVP) to afford the smallest output
capacitors possible for a given output voltage accuracy
over the anticipated full load range. The LTC3882-1 error
amplifiers have high bandwidth, low offset and low out-
put impedance, allowing the control loop compensation
network to be optimized for very high crossover frequen-
cies and excellent transient response. The controller also
achieves outstanding line transient response by using
inputfeedforwardcompensationtoinstantaneouslyadjust
PWM duty cycle and significantly reduce output under/
overshootduringsupplyvoltagechanges.Thisalsohasthe
added advantage of making the DC loop gain independent
of input voltage.
• Optional External Configuration Resistors for Key Op-
erating Parameters
• Optional Time-Base Interconnect for Synchronization
Between Multiple Controllers
• Fault Event Data Logging
• Capable of Standalone Operation with Default Factory
Configuration
• PMBus Revision 1.2 Compliant Interface up to 400kHz
The PMBus interface provides access to important power
management data during system operation including:
• Average Input Voltage
• Average Output Voltages
• Average Output Currents
• Average PWM Duty Cycles
• Internal LTC3882-1 Temperature
• External Sensed Temperatures
The main PWM control loop used for each channel is
illustrated in Figure 1. During normal operation the top
MOSFET (power switch) driving choke L1 is commanded
off when the clock for that channel resets the RS latch.
The power switch is commanded back on when the main
PWM comparator VC, sets the RS latch. The error ampli-
fier EA output (COMP) controls the PWM duty cycle to
match the FB voltage to the EA positive terminal voltage
in steady state. A patented circuit adjusts this output for
VINSNS line feedforward.
• Warning and Fault Status, Including Input and Output
Undervoltage and Overvoltage
The LTC3882-1 supports four serial bus addressing
schemestoaccesstheindividualPWMchannelsseparately
or jointly.
Fault communication, reporting and system response
behavior are fully configurable. Two fault I/Os are pro-
vided (FAULT0, FAULT1) that can be controlled indepen-
dently. A separate ALERT pin also provides for a maskable
SMBALERT#. Fault responses for each channel may be
individually programmed, depending on the fault type.
PMBus status commands allow fault reporting over the
serial bus to identify a specific fault event.
The positive terminal of the EA is connected to the output
of a 12-bit DAC with values ranging from 0V to 1.024V. The
DAC value is determined by the resistor configuration pins
detailedinapplicationTable8,byvaluesretrievedfrominter-
nal EEPROM, or by a combination of PMBus commands to
synthesizethedesiredoutputvoltage.Refertothefollowing
PMBusCommandDetailssectionofthisdocumentformore
information. The LTC3882-1 supports two output ranges.
EA can regulate the output voltage to 5.5x the DAC output
(Range 0) or 2.75x the DAC output (Range 1).
38821f
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For more information www.linear.com/LTC3882-1
LTC3882-1
operaTion
LTC3882
PWM0
MODE
V
IN
OSCILLATOR
CLOCK
R
S
Q
PWM
LOGIC
GATE
DRIVER
7
0V
V
OC0
8-BIT DAC
IOUT_OC_FAULT_LIMIT
I
LIM
RAMP
VC
V
REV
I
REV
VINSNS
FEED
FORWARD
4
R
S
+
I
SENSE0
+
–
38
L1
+
–
CA
C
S
–
I
SENSE0
+
S
37
39
5
V
OUT
I
AVG0
C
OUT
SLAVE
ENABLE
I
AVG_GND
SLAVE
DETECT
MASTER
ENABLE
V
OV0
9-BIT DAC
VOUT_OV_FAULT_LIMIT
OV
UV
V
UV0
9-BIT DAC
VOUT_UV_FAULT_LIMIT
+
V
SENSE0
36
40
9R
2R
–
+
(RANGE 0)
LOOP
COMPENSATION
NETWORK
EA
FB0
V
SP0
12-BIT DAC
VOUT_COMMAND
–
V
SENSE0
35
1
COMP0
38821 F01
Figure 1. LTC3882-1 PWM Control Loop Diagram
38821f
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For more information www.linear.com/LTC3882-1
LTC3882-1
operaTion
VC discriminates its positive input against an internally
generatedPWMvoltageramp. Thepositiveinputisacom-
positecontrolbasedonCOMPvoltagewithlinefeedforward
compensation, and current sharing if the channel controls
a slave phase. When the ramp falls below this voltage the
comparator trips and sets the PWM latch.
The LTC3882-1 features an internal RAM built-in self-test
(BIST) that runs during initialization. Should RAM BIST
fail, the following steps are taken.
• Devicerespondsonlyatdeviceaddress0x7Candglobal
addresses 0x5A and 0x5B
• A persistent Memory Fault Detected is indicated by
+
If load current increases, V
and FB will droop
SENSE
STATUS_CML
slightly with respect to the 12-bit DAC output. This causes
the COMP voltage to increase until the average inductor
current matches the new load current and the desired
output voltage is restored. Programmable comparators
• Internal EEPROM is not accessed
• RUNn and SHARE_CLK are driven low continuously
Normal operation can be restored if the RAM BIST sub-
sequently passes, for instance as the result of another
MFR_RESET command issued to address 0x7C.
I
and I
monitor peak instantaneous forward and
LIM
REV
reverse inductor current for pulse-by-pulse protection.
The top power MOSFET is immediately commanded off if
the programmed positive limit is reached, and the bottom
MOSFET is immediately commanded off if the negative
limit is reached. Repeated peak overcurrent events cause
an overcurrent fault to be set.
During initialization all PWM outputs are disabled. The
RUNn pins and SHARE_CLK are held low and FAULTn
pins are high impedance. External configuration resistors
are identified and the contents of the onboard EEPROM
are read into the controller command memory space. The
LTC3882-1 can determine key operating parameters from
external configuration resistors according to application
Table 8 through Table 11. See the following Resistor
Configuration Pins section for more detail. The resistor
configuration pins only determine some of the preset
values of the controller. The remaining values, retrieved
from internal EEPROM, are programmed at the factory or
with PMBus commands.
When the top MOSFET is commanded off, the bottom
MOSFET is normally commanded on. In continuous con-
duction mode (CCM) the bottom MOSFET stays on until
comparator VC turns the top MOSFET back on. Otherwise
in discontinuous conduction mode (DCM, also known as
diode emulation) the bottom MOSFET is commanded off
if the I
comparator detects that the inductor current
REV
has decayed to approximately 0A. In any case the next
PWM cycle starts when the clock for that channel again
clears the RS latch.
Iftheconfigurationresistorpinsareallopen,theLTC3882-1
will use only EEPROM contents to determine all operating
parameters.IfIgnoreResistorConfigurationPinsisset(bit
6 of MFR_CONFIG_ALL_LTC3882-1), the LTC3882-1 will
use only its EEPROM contents to determine all operating
parametersexceptdeviceaddress. UnlessbothASELpins
arecompletelyopen, theLTC3882-1willalwaysdetermine
some portion of its device address from the resistors on
these pins. See Serial Bus Addressing later in this section.
Power-Up and Initialization
The LTC3882-1 is designed to provide stand-alone supply
sequencingwithcontrolledturn-onandturn-offfunctions.
It operates from a single IC input supply of 3V to 13.2V
while two on-chip linear regulators generate internal
2.5V and 3.3V. If V is below 4.5V, the V and V
CC
CC
DD33
pins must be shorted together and limited to a maximum
operating voltage of 3.6V. Controller configuration is
The internal microcontroller typically requires 70ms to
complete initialization from VDD33 ≥ 3V. At that point, an
internalcomparatormonitorsVINSNS,whichmustexceed
the VIN_ON threshold before output power sequencing
can begin (SHARE_CLK released, ready for TON_DELAY).
Accuratereadbacktelemetrycanthenrequireanadditional
100ms for initial round-robin A/D conversions.
38821f
reset by the internal UVLO threshold, where V
must
DD33
be at or above 3V and the internal 2.5V supply must be
within about 20% of its regulated value. At that point the
internal microcontroller begins initialization. A PMBus
RESTORE_USER_ALL or MFR_RESET command forces
this same initialization.
19
For more information www.linear.com/LTC3882-1
LTC3882-1
operaTion
Soft-Start
times. However, with LTC3882-1 digital control, on and
off ramping methods need not be the same, and ramping
configurations can be reprogrammed as needed without
hardware modification.
The RUN pins are released for external control after the
part initializes and VINSNS is greater than the VIN_ON
threshold. If multiple LTC3882-1 ICs are used in an ap-
plication, shared RUN pins are held low until all units
initialize and VINSNS exceeds the VIN_ON threshold for
alldevices.AcommonSHARE_CLKsignalcanalsoensure
all connected devices use the same time reference for
initial start-up even if RUN pins cannot be shared due to
other design requirements. SHARE_CLK is not released
by each IC until the conditions for power sequencing have
been fully satisfied.
Programmable fault responses and fault sharing can
ensure that any desired time-based output sequencing
and ramping control is properly accomplished each time
the system powers up or down. Refer to the Applications
Information section for various LTC3882-1 hardware and
PMBus command configurations needed to fully support
synchronization for time-based sequencing and output
ramping when using multiple ICs.
After a channel RUN pin rises above 2V and any specified
turn on delay (TON_DELAY) has expired, the LTC3882-1
performsaninitialmonotonicsoft-startramponthatchan-
nel. This is carried out with a digitally controlled ramp of
the regulated output voltage from 0V to the commanded
voltage set point over the programmed TON_RISE period,
allowinginrushcurrentcontrol. Duringthesoft-startramp,
the LTC3882-1 does not initiate PWM operation until the
commanded output exceeds the actual rail voltage. This
allows the regulator to start up into a pre-biased load
even when using gate drivers or power blocks that do not
support discontinuous operation. The soft-start feature
is disabled by setting the value of TON_RISE to any time
less than 0.25ms.
Voltage-Based Output Sequencing
It is also possible to sequence outputs using cascaded
voltage events. To do this, the PGOOD status output from
one PWM channel can be used to control the RUN pin
of a downstream channel. This keeps the downstream
channel off unless acceptable output conditions exist on
the controlling channel.
Output Disable
BothPWMchannelsaredisabledanytimeVINSNSisbelow
theVIN_OFFthreshold. Thepowerstagesareimmediately
shut off to stop the transfer of energy to the load(s) as
quickly as possible.
APWMchannelmayalsobedisabledinresponsetocertain
internal fault conditions, an external fault propagated into
a FAULT pin, or loss of SHARE_CLK. In these cases the
power stage is immediately shut off to stop the transfer
of energy to the load as quickly as possible. Refer to the
Time-Based Output Sequencing
The LTC3882-1 supports time-based on and off output
sequencing using a shared time reference (SHARE_CLK).
Followingavalidqualifiedcommandtoturnon,eachoutput
isenabledafterwaitingitsprogrammedTON_DELAY. This
can be used to sequence outputs in a prescribed order
that can be preprogrammed as needed without hardware
modification. Channel off-sequencing is accomplished in
a similar way with the TOFF_DELAY command.
-
following Fault Detection and Handling section for ad
ditional details related to fault recovery.
EachPWMchannelcanbedisabledwithaPMBusOPERA-
TIONcommandatanytimeifenabledbyON_OFF_CONFIG.
This will force a controlled turn-off response with defined
delay (TOFF_DELAY) and ramp down rate (TOFF_FALL).
The controller will maintain the programmed mode of
operation for TOFF_FALL. In DCM, the controller will not
draw current from the load and fall time will be set by
output capacitance and load current.
Output Ramping Control
The LTC3882-1 supports synchronized output on and off
ramping control using a shared time reference (SHARE_
CLK).Powerrailonandoffrelationshipssimilartothoseof
conventionalanalogtrackingfunctionscanbeachievedby
usingprogrammeddelaysandTON_RISEandTOFF_FALL
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For more information www.linear.com/LTC3882-1
LTC3882-1
operaTion
Finally, each PWM channel can be commanded off by
pulling the associated RUN pin low. Pulling the RUN pin
low can force the channel to perform a controlled turn off
or immediately disable the power stage, depending on the
programming of the ON_OFF_CONFIG command.
tor current reaches approximately 0A, preventing it from
going substantially negative. The external gate driver or
power block must have short delays to a high impedance
output, relative to the PWM cycle, to support DCM.
Efficiency at light loads in CCM is lower than in DCM.
Continuous conduction mode exhibits less interference
with audio circuitry but may result in reverse inductor
current, for instance at light loads or under large transient
conditions.
Minimum Output Disable Times
When a PMBus OPERATION command is used to turn off
an LTC3882-1 channel, a minimum output disable time of
120ms is imposed regardless of how quickly the channel
is commanded back on. If bit 4 of MFR_CHAN_CONFIG is
clear,aPMBuscommandtoturnthechanneloffalsopulses
the RUN pin low. Once the RUN pin is pulled low internally
or externally, a minimum output disable time (RUN forced
low) of TOFF_DELAY + TOFF_FALL + 136ms is enforced.
If MFR_RESTART_DELAY is greater than this mandatory
minimum, the larger value of MFR_RESTART_DELAY is
used. In either case the LTC3882-1 holds its own RUN
pin low during the entire disable period. These minimum
off times allow a consistent channel restart with coher-
ent monitor ADC values and make the LTC3882-1 highly
compatible with other LTC PMBus digital power system
management products.
Switching Frequency and Phase
There is a high degree of flexibility for setting the PWM
operating frequency of the LTC3882-1. The switching
frequency of the PWM can be established with an in-
ternal oscillator or an external time base. The internal
phase-locked loop (PLL) synchronizes PWM control to
this timing reference with proper phase relation, whether
the clock is provided internally or externally. The device
can also be configured to provide the master clock to
other ICs through PMBus command, EEPROM setting,
or external configuration resistors as outlined in applica-
tion Table 10. For PMbus or EEPROM configuration, the
LTC3882-1 is designated as a clock master by clearing
bit 4 of MFR_CONFIG_ALL_LTC3882-1. As clock master,
the LTC3882-1 will drive its open-drain SYNC pin at the
selected rate with a pulse width of 125ns. An external
Output Short Cycle
An output short cycle condition is created when a mas-
ter channel is commanded back on while waiting for
TOFF_DELAY or TOFF_FALL to expire. Any time this
occurs, the LTC3882-1 asserts the Short Cycle bit in
STATUS_MFR_SPECIFIC. Device response at that point
is governed by bits in MFR_CHAN_CONFIG_LTC3882-1
and SMBALERT_MASK. Refer to the detailed descriptions
of those commands for additional details. Generally, the
LTC3882-1 should be controlled so that short cycle condi-
tions are not created during normal operation.
pull-up resistor between SYNC and V
is required in
DD33
this case. Only one device connected to SYNC should be
designated to drive the pin. If more than one LTC3882-1
sharing SYNC is programmed as clock master, just one of
the devices is automatically elected to provide the clock.
The others disable their SYNC outputs and indicate this
with bit 10 of MFR_PADS_LTC3882-1.
TheLTC3882-1willautomaticallyacceptanexternalSYNC
input, disabling is own SYNC drive if necessary, as long
as the external clock frequency is greater than 1/2 of the
programmedinternaloscillator.Whetherconfiguredtodrive
SYNC or not, the LTC3882-1 can continue PWM operation
at the selected frequency (FREQUENCY_SWITCH) using
its own internal oscillator, if an external clock signal is
subsequently lost.
Light Load Current Operation
TheLTC3882-1hastwomodesofPWMoperation:discon-
tinuous conduction mode (DCM) and forced continuous
conduction mode (CCM). Mode selection is made with
the MFR_PWM_MODE command.
In DCM, the inductor current is not allowed to reverse.
The MFR_PWM_CONFIG_LTC3882-1 command can be
usedtoconfigurethephaseofeachchannel.Desiredphase
The reverse current comparator I
disables the external
REV
bottom MOSFET (synchronous rectifier) when the induc-
38821f
21
For more information www.linear.com/LTC3882-1
LTC3882-1
operaTion
can also be set from EEPROM or external configuration
resistors as outlined in Table 10. Phase designates the
relationship between the falling edge of SYNC and the
internal clock edge that resets the PWM latch. That reset
turns off the top power switch, producing a PWM falling
edge. Additional small propagation delays to the PWM
control pins will apply.
proportionally summed with the master error amplifier
COMP output to adjust the duty cycle and balance the
current contribution of that phase. Additional hardware
configurationanddigitalprogrammingrequirementsapply
in PolyPhase systems. Refer to the Applications Informa-
tion section for complete details on building PolyPhase
rails with the LTC3882-1.
The phase relationships and frequency are independent
of each other, providing numerous application options.
Multiple LTC3882-1 ICs can be synchronized to realize a
PolyPhase array. In this case the phases should be sepa-
rated by 360/n degrees, where n is the number of phases
driving the output voltage rail.
Active Voltage Positioning
Load slope is programmable in the LTC3882-1 via the
MFR_VOUT_AVP PMBus command. The inductor cur-
rent measured at the I
pins is converted to a voltage
SENSE
which is then subtracted from the voltage reference at the
positive input of the error amplifier. The final load slope
is defined by the inductor current sense element and the
bitssetintheMFR_VOUT_AVPPMBuscommand. Setting
MFR_VOUT_AVPtoavaluegreaterthan0.0%automatically
disables output servo mode for that channel.
PolyPhase Load Sharing
Multiple LTC3882-1 ICs can be combined to provide a bal-
anced load-share solution by configuring the necessary
pins. The SHARE_CLK and SYNC pins of all load-sharing
channels should be bussed together. Connecting the
SYNC pins synchronizes the PWM controllers with each
other. Bussing the SHARE_CLK pins together allows the
phases to start synchronously. Refer to the discussion in
the previous Power-Up and Initialization section. The last
device to see all start-up conditions satisfied controls the
initiation of power sequencing for all phases.
Input Supply Monitoring
TheinputsupplyvoltageissensedbytheLTC3882-1atthe
VINSNS pin. Undervoltage, overvoltage, valid on and off
levels can be programmed for V . Refer to the following
PMBusCommandDetailssectionformoreinformationon
programming the input supply thresholds. In addition, the
telemetry ADC monitors the VINSNS voltage relative to
GND. Conversion results are returned by the READ_VIN
PMBus command.
IN
Due to the low output impedance of the LTC3882-1 error
amplifiers, PolyPhase applications should use the error
amplifier of only one phase as the master. The FB pins of
each slave channel must be wired to V
, and the COMP
DD33
Output Voltage Sensing and Monitoring
pins of each slave phase must be connected to the master
error amplifier COMP output. This disables the slave error
amplifiers and provides a single point of voltage control
and loop stabilization for the PolyPhase output rail.
BothPWMchannelsallowremote,differentialsensingofthe
load voltage with V
pins. The channel 1 output sense
SENSE
–
pin V
is internally shorted to GND (the exposed
SENSE1
pad). The telemetry ADC is fully differential and makes its
measurements of the output voltages of channels 0 and 1
ForPolyPhaseloadsharingtheLTC3882-1alsoincorporates
anauxiliarycurrentsharingloop.ReferringbacktoFigure1,
the instantaneous current of each slave phase is sensed
atV
andV
,respectively.Conversionresults
SENSE0
SENSE1
are returned by the READ_VOUT PMBus command.
by current amplifier CA and compared to the I
pin. The
AVG
I
and I
pins of each phase are wired together,
Output Current Sensing and Monitoring
AVG
AVG_GND
and a small capacitor (50pF to 200pF) between I
and
AVG
Both channels allow differential sensing of the inductor
currentusingeithertheinductorDCRoraresistorinseries
with the inductor across the I
pins for a channel are multiplexed to the differential inputs
I
stores a voltage corresponding to the average
AVG_GND
master phase output current. The difference in this aver-
age and the instantaneous phase current is integrated.
The output of integrator S of each slave phase is then
pins. When the I
SENSE
SENSE
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For more information www.linear.com/LTC3882-1
LTC3882-1
operaTion
of the LTC3882-1 monitor ADC, they have an input range
of approximately 128mV and a noise floor of 7ꢀV
ASEL1,V
,V
,FREQ_CFG,andPHAS_CFG.
OUT0_CFG OUT1_CFG
.
If any of these pins are left open the value stored in the
corresponding EEPROM command is used. The resistor
configuration pins are only measured during power-up
and execution of RESTORE_USER_ALL or MFR_RESET
commands. If bit 6 of the MFR_CONFIG_ALL_LTC3882-1
command is set in EEPROM, all resistor inputs except
ASELn are ignored. Per the PMBus specification, all pin-
programmed parameters can be overridden at any time
by commands from the digital interface.
RMS
Peak-peaknoiseisapproximately46.5ꢀV.TheinternalADC
anti-aliasing filter and conversion rate produce an average
readingoftheI
differentialvoltage.Theresultingvalue
SENSE
is returned by the READ_IOUT PMBus command. Refer to
theApplicationsInformationsectionfordetailsonsensing
output current using inductor DCR or discrete resistors.
External and Internal Temperature Sense
Externaltemperaturecanbestbemeasuredusingaremote,
diode-connected PNP transistor such as the MMBT3906.
The emitter should be connected to a TSNS pin while the
baseandcollectorterminalsofthePNPtransistormustbe
shorted together and returned directly to the LTC3882-1
GND pin. Two different currents are applied to the diode
(nominally 2ꢀA and 32ꢀA) and the temperature is calcu-
The ASELn pin settings are described in application
Table 11. These pins can be used to select the entire
LTC3882-1 device address. ASEL0 always programs the
bottom four bits of the device address for the LTC3882-1
unless left open. ASEL1 can be used to program the three
most-significantbits.Eitherportionoftheaddresscanalso
be retrieved from the MFR_ADDRESS value in EEPROM.
If both pins are left open, the full 7-bit MFR_ADDRESS
value stored in EEPROM is used to determine the device
address. The LTC3882-1 always responds to 7-bit global
addresses 0x5A and 0x5B. MFR_ADDRESS should not be
set to either of these values.
lated from a ∆V measurement made with the internal
BE
16-bit monitor ADC.
The LTC3882-1 also supports direct V based external
BE
temperature measurements. In this case the diode or di-
ode network is trimmed to a specific voltage at a specific
current and temperature. In general this method does not
The V
pin settings are described in application
OUTn_CFG
yield as accurate a result as the ∆V measurement. Refer
Table 8. These pins select the output voltages for the
related channel.
BE
toMFR_PWM_MODE_LTC3882-1inthePMBusCommand
Detailssectionforadditionalinformationonprogramming
the LTC3882-1 for these two external temperature sense
configurations.
The following parameters are also set as a percentage of
the programmed V
if resistor configuration pins are
OUT
used to determined output voltage:
• VOUT_OV_FAULT_LIMIT: +10%
• VOUT_OV_WARN_LIMIT: +7.5%
• VOUT_MAX: +7.5%
The calculated temperature is returned by the PMBus
READ_TEMPERATURE_1 command. Refer to the Appli-
cations Information section for details on proper layout
of external temperature sense elements and PMBus
commands that can be used to improve the accuracy of
calculated temperatures.
• VOUT_MARGIN_HIGH: +5%
• VOUT_MARGIN_LOW: –5%
• VOUT_UV_WARN_LIMIT: –6.5%
• VOUT_UV_FAULT_LIMIT: –7%
The READ_TEMPERATURE_2 command returns the
internal junction temperature of the LTC3882-1 using an
on-chip diode with a ∆V measurement and calculation.
BE
Resistor Configuration Pins
The FREQ_CFG pin settings are described in application
Table 9. This pin selects the switching frequency of the
internal oscillator and enables the SYNC output if not left
open, shorted to GND or ignored by EEPROM setting.
Sixinputpinscanbeusedtoconfigurekeyoperatingparam-
eters with selected 1% resistors arranged between V
DD25
and GND as a divider to the pin(s). The pins are ASEL0,
38821f
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For more information www.linear.com/LTC3882-1
LTC3882-1
operaTion
The PHAS_CFG pin settings are described in Table 10.
This pin selects the phase relationships between the two
channels and the selected clock source.
Fault Detection
A variety of fault and warning detection, reporting and
handling mechanisms are provided by the LTC3882-1.
Fault or warning detection capabilities include:
Internal EEPROM with CRC
• Input Under/Overvoltage
The LTC3882-1 contains internal EEPROM to store user
configuration settings and fault log information. EEPROM
endurance and retention for user space and fault log
pages are specified in the Absolute Maximum Ratings and
Electrical Characteristics table. The LTC3882-1 EEPROM
also contains a manufacturing section that has internal
redundancy.
• Output Under/Overvoltage
• Output Overcurrent (Peak and Average)
• Internal and External Overtemperature and External
Undertemperature
• CML Fault (Communication, Memory, or Logic)
TheintegrityoftheentireonboardEEPROMischeckedwith
a CRC calculation each time its data is to be read, such as
after a power-on reset or execution of a RESTORE_USER_
ALL command. If a CRC error occurs, the CML bit is set
intheSTATUS_BYTEandSTATUS_WORDcommands,the
EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC
command is set, and the ALERT and RUN pins pulled
low (PWM channels off). At that point the device will only
respond at special address 0x7C, which is activated only
after an invalid CRC has been detected. The chip will also
respond at the global addresses 0x5A and 0x5B, but use
of these addresses when attempting to recover from a
CRC issue is not recommended. All power supply rails
associated with either PWM channel of a device reporting
an invalid CRC should remain disabled until the issue is
resolved.
• External Fault Detection via Bidirectional FAULT Pins
Reporting is covered in following sections on status com-
mands (registers) and ALERT pin function. Fault handling
mechanisms include hardwired, low-level PWM safety
responses that always occur, and higher-level program-
mable event management. Both types are covered in the
following sections.
Input Supply Faults
Input undervoltage and overvoltage limits are determined
frommultiplexedmonitorADCconversions.Thereforethe
inputUV/OVresponseisnaturallydeglitchedbythe100ms
typical conversion cycle of the ADC. There is no hardwired
low-level PWM response for any input supply fault.
Hardwired PWM Response to V
Faults
OUT
LTC recommends that the EEPROM not be written when
die temperature is greater than 85°C. If internal die tem-
perature exceeds 130°C, all EEPROM operations except
RESTORE_USER_ALL and MFR_RESET are disabled. Full
EEPROM operation is not re-enabled until die temperature
falls below 125°C. Refer to the Applications Information
section for equations to predict retention degradation due
to elevated operating temperatures.
V
undervoltage (UV) and overvoltage (OV) faults are
OUT
detected by supervisor comparators. The OV and UV fault
limits can be set in three ways:
• As a Percentage of V
if Using the Resistor Configu-
OUT
ration Pins
• From Stored EEPROM Values
• By PMBus Command
See the Applications Information section or contact the
factoryfordetailsonefficientin-systemEEPROMprogram-
ming, including bulk EEPROM programming, which the
LTC3882-1 also supports.
Theoutputovervoltagecomparatorguardsagainsttransient
overshootsaswellaslongtermovervoltagesattheoutput.
When an output OV fault is detected the top MOSFET for
that channel is commanded off and the bottom MOSFET is
commanded on until the overvoltage condition is cleared
38821f
24
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or for PWM control protocol 0, reverse overcurrent is
Hardwired PWM Response to I
Faults
OUT
detected. See I
faults below.
OUT
The LTC3882-1 measures average I
from the voltage
OUT
acrosstheI
pins,takingintoaccountthesenseresistor
UV faults and warnings are masked if the channel has
been commanded off or until all of the following criteria
are achieved.
SENSE
or DCR value and its associated temperature coefficient.
BothareprovidedbyPMBuscommandorEEPROMvalues.
An output overcurrent (OC) fault condition is detected by
a supervisor comparator for each PWM output when the
sensed instantaneous current for that channel reaches
its maximum allowed value. Refer to the IOUT_OC_
FAULT_LIMIT PMBus command for details. When an OC
fault is detected the controller immediately disables the
top FET, and the bottom FET is normally commanded on
for the remainder of that PWM cycle.
• TON_DELAY Has Expired
• TON_RISE Ramp Has Completed
• TON_MAX_FAULT_LIMIT Has Been Reached
• IOUT_OC_FAULT_LIMIT Has Not Been Reached
• TOFF_FALL Is Not in Progress
Output UV warnings are determined from multiplexed
monitor ADC conversions. The LTC3882-1 has no hard-
wired PWM response for output UV faults or warnings.
If programmed to operate in CCM, the LTC3882-1 also
uses the negative of IOUT_OC_FAULT_LIMIT to detect
a reverse overcurrent (ROC) fault. When an ROC fault
occurs the controller immediately disables both top and
bottom FETs, unless PWM output protocol 1 is selected
with MFR_PWM_MODE_LTC3882-1.
Power Good Indication (Master)
An LTC3882-1 master phase indicates Power Good on its
PGOOD pin and in PMBus commands STATUS_WORD
(paged) and MFR_PADS_LTC3882-1 based on pro-
grammed UV and OV fault limits. Power Good is indicated
OC and ROC faults are both handled according to the
IOUT_OC_FAULT_RESPONSE for that channel. Either
hardware response can result in current-limited operation
usingpulsetruncationorskipping.BecausetheLTC3882-1
uses leading edge modulation, this will cause a shift in
average phase toward 0° on the faulted channel and an
increase in input ripple current
on a master phase as long as it is enabled to run and V
OUT
is between the UV and OV fault limits. If a master chan-
nel is off for any reason, its PGOOD pin is driven low and
Power Not Good is indicated in the status commands.
Power Good Indication (Slave)
Output OC warnings are determined from multiplexed
monitorADCconversions.TheLTC3882-1hasnohardwired
PWM response if an output OC warning occurs.
As long as they are enabled, slave phases indicate Power
Good on PGOOD and in PMBus status commands, unless
a master error amplifier (EA) fault is detected. An EA fault
indicatesthebussedCOMPvoltageappearstobetoohigh.
Hardwired PWM Response to Temperature Faults
When a slave detects an EA fault, its output is immedi-
dately disabled and OV is indicated (see Figure 2). Any
valid higher-level OV fault response and propagation may
be set for a slave channel to handle a detected EA fault. If
the OV fault response is set to ignore, the slave output is
re-enabled when the EA/COMP condition clears.
An internal temperature sensor measured by the moni-
tor ADC protects against EEPROM and other IC damage.
When die temperature rises above 130°C, the LTC3882-1
will NACK any EEPROM-related command except RE-
STORE_USER_ALL and MFR_RESET and issue a CML
faultforInvalid/UnsupportedCommand.NormalEEPROM
access is re-enabled when die temperature drops below
125°C.Above160°C,thepartshutsdownallPWMoutputs
untildietemperatureisbelow150°C.Internaltemperature
fault limits cannot be adjusted. Writing to the EEPROM
above a die temperature of 85°C is strongly discouraged.
38821f
AslaveindicatesPowerNotGoodwithPMBusstatuscom-
mands during an EA fault, but its PGOOD pin remains high
impedance. If a slave phase is off for any other reason, its
PGOOD pin is also driven low.
25
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RefertotheAbsoluteMaximumRatingsforotherimportant
temperature limitations on internal EEPROM use.
No retry is attempted for a latch off fault response. In the
latch off state the gate drivers for the external MOSFETs
are immediately disabled to stop the transfer of energy
to the load as quickly as possible. The output remains
disabled until the channel is commanded off and then
on, or IC supply power is cycled. Commanding a PWM
channel off and on may require software and/or hardware
intervention depending on its programmed configuration.
External temperature sensors may also be monitored by
the onboard ADC. There is no hardwired PWM response
for sensed external temperature faults or warnings.
Hardwired PWM Response to Timing Faults
There is no hardwired PWM response to any timing faults.
The RUN pin must be released by any controlling external
application circuits for that channel to restart from the latch
off state. As the RUN pin for a given channel rises, associ-
ated internal fault indications are cleared automatically. The
LTC3882-1 can also be programmed to clear faults for both
outputs based solely on the RUN voltage of just one chan-
nel.SeetheMFR_CONFIG_ALL_LTC3882-1command.The
CLEAR_FAULTSPMBuscommandcanalsobeusedtoclear
all fault bits at any time, independent of PWM channel state.
TON_MAX_FAULT_LIMIT is the time allowed for V
to
OUT
rise and settle at start-up. The TON_MAX_FAULT_LIMIT
timer, which has a resolution of 10µs, is started after
TON_DELAY has been reached and a soft-start sequence
isstarted.IftheVOUT_UV_FAULT_LIMITisnotreachedor
an OC remains within the specified time, fault response is
determinedbythevalueofTON_MAX_FAULT_RESPONSE.
An internal watchdog detects if SHARE_CLK remains
low for more than 64µs. The part then actively holds
SHARE_CLKlowfor120ms,ensuringalldevicesconnected
to this shared control observe a minimum RETRY_DELAY
event.The LTC3882-1 sets the SHARE_CLK_LOW bit in
MFR_COMMON to indicate this fault condition.
Handlingofsomeinternallygeneratedfaultscanbedigitally
deglitched. See Table 12. External faults propagated into
the chip using FAULTn pins are not deglitched. Refer to
the following section on FAULT functions.
Status Registers and ALERT Masking
External Faults
Figure 2 summarizes the internal LTC3882-1 status reg-
isters accessible by PMBus command. These contain
indication of various faults, warnings and other important
operating conditions. As shown, the STATUS_BYTE and
STATUS_WORD commands also summarize contents of
other status registers. Refer to PMBus Command Details
for specific information.
There are no hardware-level responses to any external
faults propagated into the IC through the FAULTn pins.
Fault Handling
Higher-levelinputandoutputfaulteventhandling(response)
can be programmed as described in the following PMBus
Command Details section. For most faults, the LTC3882-1
canmanageresponseinoneofthreeways:ignore,autono-
mous recovery (hiccup), or latch off. The device takes no
additional action beyond previously discussed hardware-
level responses when programmed to ignore a fault.
NONE OF THE ABOVE in STATUS_BYTE indicates that
one or more of the bits in the most-significant nibble of
STATUS_WORD are also set.
In general, any asserted bit in a STATUS_x register also
pulls the ALERT pin low. Once set, ALERT will remain low
until one of the following occurs.
For autonomous recovery a new soft-start is attempted if
the fault condition is not present after the MFR_RETRY_
DELAY interval has elapsed. MFR_RETRY_DELAY can be
set from 120ms to 83 seconds in 1ms increments. If the
fault persists, the controller will continue to retry with an
interval specified by the MFR_RETRY_DELAY command.
This avoids damage to external regulator components
caused by repetitive, rapid power cycling.
• A CLEAR_FAULTS, RESTORE_USER_ALL or MFR_RE-
SET Command Is Issued
• The Related Status Bit Is Written to a One
• The Faulted Channel Is Properly Commanded Off and
Back On
38821f
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STATUS_WORD
STATUS_VOUT*
15 VOUT
14 IOUT
13 INPUT
12 MFR_SPECIFIC
11 POWER_GOOD#
10 (reads 0)
7
6
5
4
3
2
1
0
VOUT_OV Fault
VOUT_OV Warning
VOUT_UV Warning
VOUT_UV Fault
VOUT_MAX Warning
TON_MAX Fault
TOFF_MAX Warning
(reads 0)
STATUS_INPUT
7
6
5
4
3
2
1
0
VIN_OV Fault
(reads 0)
VIN_UV Warning
(reads 0)
Unit Off for Insuffcient VIN
(reads 0)
9
8
(reads 0)
(reads 0)
STATUS_BYTE
(PAGED)
(reads 0)
(reads 0)
7
6
5
4
3
2
1
0
BUSY
OFF
VOUT_OV
IOUT_OC
(reads 0)
TEMPERATURE
CML
NONE OF THE ABOVE
STATUS_IOUT
STATUS_MFR_SPECIFIC
7
6
5
4
3
2
1
0
IOUT_OC Fault
(reads 0)
IOUT_OC Warning
(reads 0)
7
6
5
4
3
2
1
0
Internal Temperature Fault
Internal Temperature Warning
EEPROM CRC Error
Internal PLL Unlocked
Fault Log Present
(reads 0)
VOUT Short Cycled
FAULT Low
(PAGED)
(reads 0)
(reads 0)
(reads 0)
(reads 0)
MFR_COMMON
7
6
5
4
3
2
1
0
Chip Not Driving ALERT Low
Chip Not Busy
(PAGED)
(PAGED)
Internal Calculations Not Pending
Output Not In Transition
EEPROM Initialized
(reads 0)
SHARE_CLK_LOW
(reads 0)
STATUS_TEMPERATURE
MFR_PADS_LTC3882-1
7
6
5
4
3
2
1
0
OT Fault
15 Channel 1 is Slave
14 Channel 0 is Slave
13 (reads 0)
12 (reads 0)
11 Invalid ADC Result(s)
OT Warning
(reads 0)
UT Fault
(reads 0)
(reads 0)
(reads 0)
(reads 0)
10 SYNC Output Disabled Externally
9
8
7
6
5
4
3
2
1
0
Channel 1 is POWER_GOOD
Channel 0 is POWER_GOOD
LTC3882-1 Forcing RUN1 Low
LTC3882-1 Forcing RUN0 Low
RUN1 Pin State
(PAGED)
STATUS_CML
7
6
5
4
3
2
1
0
Invalid/Unsupported Command
Invalid/Unsupported Data
Packet Error Check Failed
Memory Fault Detected
Processor Fault Detected
(reads 0)
RUN0 Pin State
LTC3882-1 Forcing FAULT1 Low
LTC3882-1 Forcing FAULT0 Low
FAULT1 Pin State
DESCRIPTION
MASKABLE GENERATES ALERT BIT CLEARABLE
General Fault or Warning Event
Dynamic
Status Derived from Other Bits
Yes
No
No
Yes
No
Not Directly
Yes
No
No
FAULT0 Pin State
Other Communication Fault
Other Memory or Logic Fault
*IF THE CHANNEL IS CONFIGURED AS A SLAVE AS INDICATED BY MFR_PADS_LTC3882-1[15:14], VOUT_OV FAULT INDICATES A DETECTED MASTER ERROR
AMPLIFIER FAULT (COMP VOLTAGE TOO HIGH). NO OTHER BITS IN STATUS_VOUT ARE ACTIVE ON SLAVE CHANNELS
38821 F02
Figure 2. LTC3882-1 Status Register Summary
• The LTC3882-1 Successfully Transmits Its Address
and STATUS_BYTE in the same fashion as the status bits
themselves. For example, if ALERT is masked for all bits
in Channel 0 STATUS_VOUT, then ALERT is effectively
masked for the VOUT bit in STATUS_WORD for PAGE 0.
During a PMBus Alert Response Address (ARA)
• IC Supply Power Is Cycled
With some exceptions, the SMBALERT_MASK command
can be used to prevent the LTC3882-1 from asserting
ALERT for bits in these registers on a bit-by-bit basis.
These mask settings are promoted to STATUS_WORD
The BUSY bit in STATUS_BYTE also asserts ALERT low
and cannot be masked. This bit can be set as a result of
interaction between internal operation and PMBus com-
38821f
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munication.Thisfaultoccurswhenacommandisreceived
that cannot be safely executed with one or both channels
enabled. As discussed in Application Information, BUSY
faults can be avoided by polling MFR_COMMON before
executing some commands.
Fault Logging
TheLTC3882-1hasfaultloggingcapability. Duringnormal
operationlogdataiscontinuouslyupdatedininternalRAM.
When a fault occurs that disables either PWM controller,
recordingtointernalmemoryishalted,thefaultloginforma-
tion is made available from RAM via the MFR_FAULT_LOG
command, and the contents of the RAM log are copied
into EEPROM. EEPROM fault logging is allowed above
a die temperature of 85°C, but 10 years of retention is
not guaranteed. When die temperature exceeds 130°C
EEPROM fault logging is delayed until the temperature
dropsbelow 125°C. Faults generatinga log should befully
cleared before the log is erased to prevent generation of
spurious fault logs. Faults propagated into the IC through
FAULTn pins do not trigger a fault logging event.
Status information contained in MFR_COMMON and
MFR_PADS_LTC3882-1 can be used to clarify the con-
tents of STATUS_BYTE or STATUS_WORD as shown,
but the contents of these registers do not affect the state
of the ALERT pin and may not directly influence bits in
STATUS_BYTE or STATUS_WORD.
FAULT Pin I/O
The LTC3882-1 can map various fault indicators to their
respective FAULT pin using the MFR_FAULT_PROPA-
GATE_LTC3882-1 command.
When the LTC3882-1 powers up it checks the EEPROM
for a valid fault log. If one is found the Valid Fault Log bit
in the STATUS_MFR_SPECIFIC PMBus command is set.
AdditionalfaultloggingwillbedisableduntiltheLTC3882-1
receives a CLEAR_FAULTS command. If the Memory Fault
Detected bit is also set in STATUS_CML, then the stored
fault log is partial. Data in one or more event records may
be incomplete or incorrect and MFR_CLEAR_FAULT_LOG
should also be commanded after all faults are cleared in
order to fully enable additional logging functions.
Channel-to-channel fault dependencies and communica-
tion can be created by connecting FAULT pins together. In
the event of an internal fault, one or more of the channels
is configured to pull the bussed FAULT pins low. All chan-
nels are then configured to shut down when the bussed
FAULT pins are pulled low (MFR_FAULT_RESPONSE set
to 0xc0). If latch off is the programmed response on the
faulted channel, the FAULT pin remains low until one of
the following occurs:
• A CLEAR_FAULTS, RESTORE_USER_ALL or MFR_RE-
TheMFR_FAULT_LOGcommandusesablockreadprotocol
with a fixed length of 147 bytes. The LTC3882-1 returns a
block byte count of zero if a fault log is not present.
SET Command Is Issued
• The Related Status Bit Is Written to a One
ContentsofafaultlogareshowninTable1throughTable4.
Refer to Table 6 for an explanation of data formats. Each
event record represents one complete conversion cycle
through all multiplexed monitor ADC inputs and related
status. The six most recent event records are maintained
in internal memory in reverse chronological order. When
a fault log is created the present ADC input cycle is com-
pleted and the ADC input being converted at the time of
the fault is noted in the log header record.
• The Faulted Channel Is Properly Commanded Off and
Back On
• IC Supply Power Is Cycled
For autonomous group retry, the faulted channel is con-
figured to release the FAULT pin(s) after a retry interval,
assuming the original fault has cleared. All the channels
in the group then begin a soft-start sequence.
As noted above, FAULT pins may be configured as inputs
to detect faults external to the controller that require an
immediate response. External faults propagated into the
chip using FAULT pins are not deglitched.
Refer to the MFR_FAULT_PROPAGATE command for ad-
ditional details.
38821f
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Table 1. LTC3882-1 Fault Log Contents
STARTING
ENDING
BYTE
RECORD TYPE
BYTE
COMMENTS
Header Information
Fault Event Record
0
26
46
See Table 2.
27
Fault may have occurred anywhere during this event record. See byte 4 of Table 2 and all of
Table 3 and Table 4.
Event Record N-1
Event Record N-2
Event Record N-3
Event Record N-4
Event Record N-5
47
67
66
86
Last complete cyclical data read before the fault was detected.
Older data records…
87
106
126
146
107
127
Oldest recorded data.
Table 2. Fault Log Header Information
BLOCK
BYTE
RECORD
BITS
[7:0]
FORMAT COUNT DETAILS
Fault Log Preface
ASC
0
1
Returns LTxx beginning at byte 0 if a partial or complete fault log exists. Word xx is
a factory identifier that may vary part to part.
[7:0]
[15:8]
[7:0]
Reg
2
3
Fault Source
[7:0]
Reg
Reg
4
Refer to Table 3.
MFR_REAL_TIME
[7:0]
5
48 bit share-clock counter value when fault occurred (200µs resolution).
[15:8]
[23:16]
[31:24]
[39:32]
[47:40]
[15:8]
[7:0]
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
MFR_VOUT_PEAK (PAGE 0)
MFR_VOUT_PEAK (PAGE 1)
MFR_IOUT_PEAK (PAGE 0)
MFR_IOUT_PEAK (PAGE 1)
MFR_VIN_PEAK
L16
L16
L11
L11
L11
L11
L11
L11
Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS command.
Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS command.
Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS command.
Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS command.
Peak READ_VIN since last power-on or CLEAR_PEAKS command.
External temperature sensor 0 during last event.
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
READ_TEMPERATURE1 (PAGE 0)
READ_TEMPERATURE1 (PAGE 1)
READ_TEMPERATURE2
[15:8]
[7:0]
[15:8]
[7:0]
External temperature sensor 1 during last event.
[15:8]
[7:0]
Internal temperature sensor during last event.
38821f
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Table 3. Fault Source Values
FAULT SOURCE VALUE
CAUSE OF FAULT LOG
TON_MAX
CHANNEL
0x00
0x01
0x02
0x03
0x05
0x06
0x07
0x0A
0x10
0x11
0x12
0x13
0x15
0x16
0x17
0x1A
0xFF
0
VOUT_OV
VOUT_UV
IOUT_OC
Over temperature
Under temperature
VIN_OV
Internal temperature
TON_MAX
1
VOUT_OV
VOUT_UV
IOUT_OC
Over temperature
Under temperature
VIN_OV
Internal temperature
MFR_FAULT_LOG_STORE
Table 4. Fault Log Event Record
DATA
BITS
[15:8]
[7:0]
FORMAT
RECORD BYTE INDEX
READ_VOUT (PAGE 0)
L16
0
1
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
[15:8]
[7:0]
L16
L11
L11
L11
L11
2
3
[15:8]
[7:0]
4
5
[15:8]
[7:0]
6
7
[15:8]
[7:0]
8
9
(Not used)
[15:8]
[7:0]
10
11
12
13
14
15
16
17
18
19
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
[7:0]
Reg
Reg
Reg
[7:0]
[15:8]
[7:0]
STATUS_WORD (PAGE 1)
[15:8]
[7:0]
Reg
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
[7:0]
Reg
Reg
[7:0]
38821f
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Factory Default Operation
memory are replaced with active command values from
internalRAM,andthatwillpermanentlyoverwritethefactory
defaults. Table 5 summarizes the default factory operation
settings of the LTC3882-1 if all resistor configuration pins
are left open. These defaults allow parameters listed in bold
text in the table to be overridden with configuration resistor
programming. Warning limits are given in Table 5 because
exceedingthemwillcausetheALERTpintobeassertedeven
if the PMBus interface is not being utilized.
The LTC3882-1 ships from the factory with a default con-
figuration stored in its non-volatile memory, unless custom
programming has been requested. These command values
areloadedintovolatileRAMwhenthechipisinitialized.Prior
to receiving any PMBus commands, a stock LTC3882-1 will
operate in the factory default mode. If a STORE_USER_
ALL command is executed, the contents of the non-volatile
Table 5. Factory Default Operation Summary
PARAMETER*
DEFAULT SETTING
UNITS
PMBus Address
All writes enabled to Channel 0 at address 0x4F (no PEC).
–
Operation
OPERATION enabled with RUN pin control and soft-off.
–
Input Voltage OFF Threshold
Input Voltage UV Warning Limit
Input Voltage ON Threshold
Input Voltage OV Fault Limit
Input Voltage OV Fault Response
Soft-Start Time
6.0
V
6.3
V
6.5
V
15.5
V
Latch off.
–
8 (with no delay).
ms
Maximum Start-Up Time (TMAX)
TMAX Fault Response
10
ms
Retry every 350ms.
–
Output Voltage UV Fault/Warning Limits
Output Voltage UV Fault Response
Output Voltage
0.900/0.925
V
Retry every 350ms.
–
1.000
V
Active Voltage Positioning
Disabled.
–
Output Voltage OV Warning/Fault Limits
Output Voltage OV Fault Response
Shut Down
1.075/1.100
V
Retry every 350ms.
–
8ms soft-off.
–
Output Current Sense Element
Output Current OC Warning/Fault Limits
Output Current OC Fault Response
PWM Switching Mode
0.63mΩ with 3930ppm/°C TC.
–
20/29.75
A
Ignore
–
Continuous inductor current only.
–
PWM Control Protocol
Three-State PWM.
–
PWM Switching Frequency
Channel 0/1 Phase
500
kHz
0/180
Degrees
Internal Overtemperature Warning/Fault Limits
Internal Overtemperature Responses
External Undertemperature Fault Limit
External Undertemperature Fault Response
External Overtemperature Warning/Fault Limits
External Overtemperature Fault Response
FAULT
130/160
°C
–
Warning: EEPROM disabled; Fault: PWM disabled.
–40
°C
–
Retry every 350ms.
85/100
°C
–
Retry every 350ms.
Asserts low for the following faults: V
external UT, TON_MAX, or output short cycle.
UV or OV, V OV, external or internal OT,
–
OUT
IN
ALERT Masking
ALERTs are masked for loss of PLL lock and external FAULT inputs.
–
*bold entries can be changed with external configuration resistors
38821f
31
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Serial Interface
• Read Byte
TheLTC3882-1hasaPMBuscompliantserialinterfacethat
can operate at any frequency between 10kHz and 400kHz.
The LTC3882-1 is a bus slave device that communicates
bidirectionallywithahost(master)usingstandardPMBus
protocols. The Timing Diagram found earlier in this docu-
ment, along with related Electrical Characteristics table
entries, definethetimingrelationshipsoftheSDAandSCL
bus signals. SDA and SCL must be high when the bus is
not in use. External pull-up resistors or current sources
are required on these lines.
• Read Word
• Block Read
• Block Write – Block Read Process Call
• Alert Response Address
The LTC3882-1 does not require PEC for Quick Command
under any circumstances. The LTC3882-1 also supports
group command protocol (GCP) as required by PMBus
specificationPartI,section5.2.3.GCPisusedtosendcom-
mands to more than one PMBus device in one continuous
transmission. It should not be used with commands that
require the receiving device to respond with data, such as
a STATUS_BYTE command. Refer to Part I of the PMBus
specification for additional details on using GCP.
PMBus, an incremental extension of the SMBus standard,
2
offersmorerobustoperationthana2-wireI Cinterface.In
addition to adding a protocol layer to improve interoper-
ability and facilitate reuse, PMBus supports bus timeout
recoveryforsystemreliability,optionalpacketerrorcheck-
ingtoensuredataintegrity, andperipheralhardwarealerts
forsystemfaultmanagement.Ingeneral,aprogrammable
AllLTC3882-1messagetransmissiontypesallowforpacket
errorchecking. ThelatersectiononSerialCommunication
Errors provides more detail on packet error checking.
2
device capable of functioning as an I C bus master can be
configuredforPMBusmanagementwithlittleornochange
Figure 4 to Figure 20 illustrate these protocols. Figure 3
provides a key to the protocol diagrams. Not all protocol
elementswillbepresentineverydatapacket.Forinstance,
not all packets are required to include the packet error
code. A number shown above a field in these diagrams
indicates the number of bits in that field. All data transfers
are initiated by the present bus master regardless of how
many times data direction flow may change during the
subsequenttransmission.TheLTC3882-1neverfunctions
as a bus master.
2
tohardware.However,notallI Ccontrollerssupportrepeat
start (restart) required for PMBus reads.
For a description of the minor extensions and exceptions
PMBus makes to the SMBus standard, refer to PMBus
SpecificationPartIRevision1.2Paragraph5onTransport.
For a description of the differences between SMBus and
2
I C, refer to System Management Bus (SMBus) Specifi-
cation Version 2.0 Appendix B on Differences Between
2
SMBus and I C.
This device includes handshaking features to ensure ro-
bust system communication. Please refer to the PMBus
Communication and Command Processing section in
Applications Information for more details.
The user is encouraged to reference Part I of the latest
PMBus Power System Management Protocol Specifica-
tion to understand how to interface the LTC3882-1 to a
PMBus system. This specification can be found at http://
www.pmbus.org/specs.html.
Serial Bus Addressing
TheLTC3882-1usesthefollowingstandardserialinterface
protocolsdefinedintheSMBusandPMBusspecifications:
The LTC3882-1 supports four types of serial bus ad-
dressing:
• Quick Command
• Send Byte
• Global Bus Addressing
• Power Rail Addressing
• Individual Device Addressing
• Write Byte
• Write Word
• Page+ Channel Addressing
38821f
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Global addressing provides a means for the bus master
to communicate with all LTC3882-1 devices on the bus
simultaneously. The LTC3882-1 global addresses of 0x5A
and0x5Bcannotbechangedordisabled. Commandssent
to address 0x5A are applied to both channels, as if the
PAGE command were set to 0xFF. Global address 0x5B is
paged, allowing channel-specific control of all LTC3882-1
devices on the bus. Other LTC device types may respond
at one or both of these global addresses. Reading from
global addresses is strongly discouraged.
PolyPhase rail. Different voltage rails should not attempt
to share a rail address. Reading from rail addresses is
also strongly discouraged.
Device addressing is the most common means used by a
bus master to communicate with an LTC3882-1. The value
of the device address is set by the combination of ASEL
pin programming and the MFR_ADDRESS command.
Refer to the previous section on Resistor Configuration
Pins for details.
Individual channel addressing allows the bus master to
communicate directly with a specific LTC3882-1 PWM
channel without first using a PAGE command. Refer to
the PAGE_PLUS commands for additional details.
Rail addressing provides a means for the bus master to
simultaneouslycommunicatewithallchannelsconnected
together to produce a single output voltage (PolyPhase).
While similar to global addressing, the rail address can
be dynamically assigned with the paged MFR_RAIL_AD-
DRESS command, allowing for any logical grouping of
channelsthatmightberequiredforreliablesystemcontrol.
Rail addresses should be unique for each single-phase or
Use of any of the four types of addressing requires careful
planning to avoid address-related bus conflicts. Commu-
nication to LTC3882-1 devices at global and rail addresses
should be limited to command write operations.
S
START CONDITION
REPEATED START CONDITION
Sr
Rd READ (BIT VALUE OF 1)
Wr WRITE (BIT VALUE OF 0)
A
ACKNOWLEDGE (BIT SHOULD BE 0), OR
NA NOT ACKNOWLEDGE (BIT SHOULD BE 1)
P
STOP CONDITION
PEC PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
...
CONTINUATION OF PROTOCOL
38821 F03
Figure 3. PMBus Packet Protocol Diagram Element Key
1
7
1
1
1
S
SLAVE ADDRESS Rd/Wr
A
P
38821 F04
Figure 4. Quick Command Protocol
1
7
1
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
P
38821 F05
Figure 5. Send Byte Protocol
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
PEC
A
P
38821 F06
Figure 6. Send Byte Protocol with PEC
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1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE
A
P
38821 F07
Figure 7. Write Byte Protocol
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE
A
PEC
A
P
38821 F08
Figure 8. Write Byte Protocol with PEC
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
38821 F09
Figure 9. Write Word Protocol
1
7
1
1
8
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
38821 F10
Figure 10. Write Word Protocol with PEC
1
7
1
1
8
1
1
7
1
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE
NA
P
38821 F11
Figure 11. Read Byte Protocol
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE
A
PEC
A
P
38821 F12
Figure 12. Read Byte Protocol with PEC
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE LOW
A
DATA BYTE HIGH NA
P
38821 F13
Figure 13. Read Word Protocol
1
7
1
1
8
1
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
38821 F14
Figure 14. Read Word Protocol with PEC
1
7
1
1
8
1
1
7
1
1
8
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
BYTE COUNT = N
A
…
8
1
8
1
8
1
1
…
DATA BYTE 1
A
DATA BYTE 2
A
…
DATA BYTE N NA
P
38821 F15
Figure 15. Block Read Protocol
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1
7
1
1
8
1
1
7
1
1
8
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
BYTE COUNT = N
A
…
8
1
8
1
8
1
8
1
1
…
…
DATA BYTE 1
A
DATA BYTE 2
A
DATA BYTE N
A
PEC
NA
P
38821 F16
Figure 16. Block Read Protocol with PEC
1
7
1
1
8
1
8
1
8
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
BYTE COUNT = M
A
DATA BYTE 1
A
…
8
1
8
1
DATA BYTE 2
A
…
DATA BYTE M
A
…
1
7
1
1
8
1
8
1
Sr SLAVE ADDRESS Rd
A
BYTE COUNT = N
A
DATA BYTE 1
A
…
8
8
1
1
DATA BYTE 2
A
…
DATA BYTE N NA
P
38821 F17
Figure 17. Block Write – Block Read Process Call
1
7
1
1
8
1
8
1
8
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
BYTE COUNT = M
A
DATA BYTE 1
A
…
8
1
8
1
…
DATA BYTE 2
A
…
DATA BYTE M
A
…
1
7
1
1
8
1
8
Sr SLAVE ADDRESS Rd
A
BYTE COUNT = N
A
DATA BYTE 1
A
…
8
1
8
1
8
1
1
DATA BYTE 2
A
…
DATA BYTE N
A
PEC
NA
P
38821 F18
Figure 18. Block Write – Block Read Process Call with PEC
1
7
1
1
8
1
1
ALERT RESPONSE
ADDRESS
S
Rd
A
DEVICE ADDRESS NA
P
38821 F19
Figure 19. Alert Response Address Protocol
1
7
1
1
8
1
8
1
1
ALERT RESPONSE
ADDRESS
S
Rd
A
DEVICE ADDRESS
A
PEC
NA
P
38821 F20
Figure 20. Alert Response Address Protocol with PEC
38821f
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Serial Bus Timeout
Serial Communication Errors
The LTC3882-1 implements a timeout feature to avoid
hanging the serial interface. The data packet timer be-
gins running at the first START event before the SLAVE
ADDRESS write byte and ends with the STOP bit. Packet
transmission must be completed before the timer expires,
or the LTC3882-1 will tri-state the bus and ignore all mes-
sage data. The data packet includes the SLAVE ADDRESS
byte, COMMAND CODE byte, repeated START and SLAVE
ADDRESS byte (if a read operation), all ACKNOWLEDGE
and flow control bits (R/W) and all data bytes.
The LTC3882-1 supports the optional PMBus packet error
checking protocol. This protocol appends a packet error
code (PEC) to the end of applicable message transfers to
improve communication reliability. The PEC is a CRC-8
error-checking byte calculated by the bus device sending
the last data byte. Refer to SMBus specification 1.2 or
higherforadditionalimplementationdetails.AllLTC3882-1
read operations will return a valid PEC if the bus master
requests it. If bit 2 in the MFR_CONFIG_ALL_LTC3882-1
command is set, the IC will not act in response to a bus
write operation unless a valid PEC is also received from
the host.
The packet timer is typically set to 30ms. If bit 3 of MFR_
CONFIG_ALL_LTC3882-1 is set, this period is extended
to 255ms. The LTC3882-1 automatically allows a packet
transmission time of 255ms for MFR_FAULT_LOG block
reads regardless of the setting of this bit. In no circum-
PEC errors on command writes, attempts to access un-
supportedcommands,orwritinginvaliddatatosupported
commands all cause the LTC3882-1 to generate a CML
fault. The CML bit is then set in the STATUS_BYTE and
STATUS_WORD commands, and the appropriate bit is set
in the STATUS_CML command.
stances will the timeout period be less than the t
specification (25ms minimum).
TIMEOUT
The LTC3882-1 supports the full PMBus frequency range
of 10kHz to 400kHz.
38821f
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PMBus Commands
protocols defined in the PMBus Specification V1.2, Part
II, Section 10.8.7, to communicate that it is busy. This
device includes handshaking features to eliminate busy
responses, simplify error handling software and ensure
robust communication and system behavior. Please refer
to PMBus Communication and Command Processing in
the Applications Information section for further details.
Table 7 lists supported PMBus commands and manufac-
turer specific commands. Additional information about
these commands can be found in Revision 1.2 of Part II of
thePMBusPowerSystemManagementProtocolSpecifica-
tionthatcanbefoundathttp://www.pmbus.org/specs.html.
Usersareencouragedtoreferencethatmanual.Exceptions
or manufacturer-specific implementations are detailed in
the tables below. All standard PMBus commands from
0x00 through 0xCF not listed in this table are implicitly
not supported by the LTC3882-1. All commands from
0xD0 through 0xFF not listed in this table are implicitly
reservedbythemanufacturer.TheLTC3882-1mayexecute
additional commands not listed in this table, and these
can change without notice. Reading these unlisted com-
mandsisharmlesstotheoperationoftheIC. Writestoany
unsupported or reserved command should be avoided, as
they may result in a CML fault and/or undesired operation
of the part.
LTC has made an effort to establish PMBus command
compatibility and functional uniformity among its family
of parts. However, differences may occur due to specific
productrequirements.CompatibilityofPMBuscommands
among any ICs should not be assumed based simply on
command name. Always refer to the manufacturer’s data
sheet of each device for a complete definition of a com-
mand function.
Data Formats
PMBus supports specific floating point number formats
and allows for a wide range of other data formats.
If PMBus commands are received faster than they are be-
ing processed, the part may become too busy to handle
new commands. In these cases the LTC3882-1 follows the
Table6describesthedataformatsusedbytheLTC3882-1.
Abbreviations of these formats appear throughout this
document.
Table 6. Abbreviations of Supported Data Formats
PMBus
SPECIFICATION
LTC
TERMINOLOGY
L11 Linear
REFERENCE TERMINOLOGY DEFINITION
EXAMPLE
N
Part II ¶7.1
Linear_5s_11s Floating point 16-bit data: value = Y • 2 , b[15:0] = 0x9807 = 10011_000_0000_0111
–13
where N = b[15:11] and Y = b[10:0], both value = 7 • 2 = 854E-6
two’s compliment binary integers.
–12
L16 Linear VOUT_MODE
CF DIRECT
Part II ¶8.2
Part II ¶7.2
Linear_16u
varies
Floating point 16-bit data: value = Y • 2 , b[15:0] = 0x4C00 = 0100_1100_0000_0000
–12
where Y = b[15:0], an unsigned integer.
value = 19456 • 2 = 4.75
16-bit data with a custom format
defined in the detailed PMBus command
description.
Often an unsigned or two’s compliment
integer.
Reg register bits
Part II ¶10.3
Reg
Per-bit meaning defined in detailed PMBus PMBus STATUS_BYTE command.
command description.
ASC text characters
Part II ¶22.2.1
ASCII
ISO/IEC 8859-1 [A05]
LTC (0x4C5443)
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Table 7. PMBus Command Summary
CMD
DATA
DEFAULT
VALUE
SEE
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
PAGE
0x00 Channel (page) presently selected for
any paged command.
R/W Byte
N
Reg
0x00
70
l
l
OPERATION
0x01 On, off and margin control.
R/W Byte
R/W Byte
Y
Y
Reg
Reg
0x80
0x1E
74
73
ON_OFF_CONFIG
0x02 RUN pin and PMBus on/off command
configuration.
CLEAR_FAULTS
0x03 Clear all set fault bits.
Send Byte
W Block
N
N
92
70
PAGE_PLUS_WRITE
0x05 Write a command directly to a specified
page.
PAGE_PLUS_READ
WRITE_PROTECT
STORE_USER_ALL
RESTORE_USER_ALL
CAPABILITY
0x06 Read a command directly from a
specified page.
Block R/W
Process
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
N
N
N
Y
Y
71
71
l
0x10 Protect the device against unintended
PMBus modifications.
R/W Byte
Send Byte
Send Byte
R Byte
Reg
0x00
0xB0
0x15 Store entire operating memory in
EEPROM.
103
103
72
0x16 Restore entire operating memory from
EEPROM.
0x19 Summary of supported optional PMBus
features.
Reg
Reg
Reg
L16
L16
L16
L16
L11
L11
L11
L11
L11
L16
l
SMBALERT_MASK
VOUT_MODE
0x1B Mask ALERT activity
Block R/W
R Byte
see CMD
details
100
80
0x20 Voltage-related format (Linear) and
exponent.
0x14
–12
2
l
l
l
l
l
l
l
l
l
l
VOUT_COMMAND
VOUT_MAX
0x21 Nominal V
value.
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
V
V
1.0V
0x1000
80
OUT
0x24 Maximum V
that can be set by any
5.5V
0x5800
81
OUT
command, including margin.
VOUT_MARGIN_HIGH
VOUT_MARGIN_LOW
VOUT_TRANSITION_RATE
FREQUENCY_SWITCH
VIN_ON
0x25
0x26
0x27
V
at high margin, must be greater
V
1.05V
0x10CD
81
OUT
than VOUT_COMMAND.
V
OUT
at low margin, must be less than
V
0.95V
0x0F33
81
VOUT_COMMAND.
V
slew rate for programmed output
V/ms
kHz
V
0.25
0xAA00
85
OUT
changes.
0x33 PWM frequency control.
500kHz
0xFBE8
75
0x35 Minimum input voltage to begin power
conversion.
6.5V
0xCB40
79
VIN_OFF
0x36 Decreasing input voltage at which power R/W Word
conversion stops.
V
6.0V
0xCB00
79
IOUT_CAL_GAIN
VOUT_OV_FAULT_LIMIT
0x38 Ratio of I
current.
voltage to sensed
R/W Word
mΩ
V
0.63mΩ
0xB285
83
SENSE
0x40
V
OUT
overvoltage fault limit.
R/W Word
1.1V
0x119A
81
l
l
VOUT_OV_FAULT_RESPONSE 0x41
V
V
overvoltage fault response.
overvoltage warning limit.
R/W Byte
Y
Y
Reg
L16
0xB8
96
82
OUT
VOUT_OV_WARN_LIMIT
0x42
R/W Word
V
1.075V
0x1133
OUT
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Table 7. PMBus Command Summary
CMD
DATA
DEFAULT
VALUE
SEE
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
l
VOUT_UV_WARN_LIMIT
0x43
V
V
V
undervoltage warning limit.
R/W Word
Y
L16
L16
V
0.925V
82
82
OUT
OUT
OUT
0x0ECD
l
VOUT_UV_FAULT_LIMIT
0x44
undervoltage fault limit.
R/W Word
Y
V
0.9V
0x0E66
l
l
VOUT_UV_FAULT_RESPONSE 0x45
undervoltage fault response.
R/W Byte
Y
Y
Reg
L11
0xB8
96
83
IOUT_OC_FAULT_LIMIT
0x46 Output overcurrent fault limit.
R/W Word
A
29.75A
0xDBB8
l
l
IOUT_OC_FAULT_RESPONSE
IOUT_OC_WARN_LIMIT
0x47 Output overcurrent fault response.
0x4A Output overcurrent warning limit.
R/W Byte
Y
Y
Reg
L11
0x00
97
83
R/W Word
A
20.0A
0xDA80
l
OT_FAULT_LIMIT
0x4F External overtemperature fault limit.
R/W Word
Y
L11
°C
100.0°C
0xEB20
86
l
l
OT_FAULT_RESPONSE
OT_WARN_LIMIT
0x50 External overtemperature fault response. R/W Byte
0x51 External overtemperature warning limit. R/W Word
Y
Y
Reg
L11
0xB8
98
86
°C
°C
85.0°C
0xEAA8
l
l
l
UT_FAULT_LIMIT
0x53 External undertemperature fault limit.
R/W Word
R/W Byte
R/W Word
Y
Y
N
L11
Reg
L11
–40.0°C
0xE580
87
98
79
UT_FAULT_RESPONSE
VIN_OV_FAULT_LIMIT
0x54 External undertemperature fault
response.
0xB8
0x55
V
IN
overvoltage fault limit.
V
15.5V
0xD3E0
l
l
VIN_OV_FAULT_RESPONSE
VIN_UV_WARN_LIMIT
0x56
0x58
V
V
overvoltage fault response.
undervoltage warning limit.
R/W Byte
Y
N
Reg
L11
0x80
95
79
IN
R/W Word
V
6.3V
0xCB26
IN
l
l
l
TON_DELAY
0x60 Delay from RUN pin or OPERATION ON
command to TON_RISE ramp start.
R/W Word
R/W Word
R/W Word
Y
Y
Y
L11
L11
L11
ms
ms
ms
0.0ms
84
84
85
0x8000
TON_RISE
0x61 Time for V
to rise from 0.0V to
8.0ms
0xD200
OUT
VOUT_COMMAND after TON_DELAY.
TON_MAX_FAULT_LIMIT
0x62 Maximum time for V
to rise above
10.0ms
0xD280
OUT
VOUT_UV_FAULT_LIMIT after
TON_DELAY.
l
l
l
l
TON_MAX_FAULT_RESPONSE 0x63 Fault response when TON_MAX_FAULT_ R/W Byte
LIMIT is exceeded.
Y
Y
Y
Y
Reg
L11
L11
L11
0xB8
99
85
85
85
TOFF_DELAY
0x64 Delay from RUN pin or OPERATION OFF R/W Word
command to TOFF_FALL ramp start.
ms
ms
ms
0.0ms
0x8000
TOFF_FALL
0x65 Time for V
to fall to 0.0V from
R/W Word
8.0ms
0xD200
OUT
VOUT_COMMAND after TOFF_DELAY.
TOFF_MAX_WARN_ LIMIT
0x66 Maximum time for V
to decay below R/W Word
150ms
0xF258
OUT
12.5% of VOUT_COMMAND after
TOFF_FALL completes.
STATUS_BYTE
STATUS_WORD
STATUS_VOUT
STATUS_IOUT
STATUS_INPUT
0x78 One-byte channel status summary.
0x79 Two-byte channel status summary.
R/W Byte
R/W Word
R/W Byte
R/W Byte
R/W Byte
Y
Y
Y
Y
N
Reg
Reg
Reg
Reg
Reg
87
88
88
89
89
0x7A
0x7B
V
fault and warning status.
fault and warning status.
OUT
I
OUT
0x7C Input supply fault and warning status.
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Table 7. PMBus Command Summary
CMD
DATA
DEFAULT
VALUE
SEE
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
STATUS_TEMPERATURE
0x7D External temperature fault and warning
status.
R/W Byte
Y
Reg
Reg
89
90
STATUS_CML
0x7E Communication, memory and logic fault R/W Byte
and warning status.
N
STATUS_MFR_ SPECIFIC
READ_VIN
0x80 LTC3882-1-specific status.
0x88 Measured V .
R/W Byte
R Word
R Word
R Word
R Word
R Word
R Word
R Word
R Word
R Byte
Y
N
Y
Y
Y
N
Y
Y
Y
N
Reg
L11
L16
L11
L11
L11
L11
L11
L11
Reg
90
92
93
93
94
94
94
94
93
72
V
V
IN
READ_VOUT
0x8B Measured V
.
OUT
READ_IOUT
0x8C Measured I
.
A
OUT
READ_TEMPERATURE_1
READ_TEMPERATURE_2
READ_DUTY_CYCLE
READ_FREQUENCY
READ_POUT
0x8D Measured external temperature.
0x8E Measured internal temperature.
0x94 Measured commanded PWM duty cycle.
0x95 Measured PWM input clock frequency.
0x96 Calculated output power.
°C
°C
%
kHz
W
PMBUS_REVISION
0x98 Supported PMBus version.
0x22
V1.2
MFR_ID
0x99 Manufacturer identification.
0x9A LTC model number.
R String
R String
R Block
N
N
N
ASC
ASC
ASC
LTC
104
MFR_MODEL
LTC3882-1 104
104
MFR_SERIAL
0x9E Device serial number.
LTC3882-1 Custom Commands
MFR_VOUT_MAX
0xA5 Maximum value of any V
command.
related
R Word
Y
L16
V
5.6V
0x599A
80
OUT
l
l
l
l
USER_DATA_00
USER_DATA_01
USER_DATA_02
USER_DATA_03
0xB0 EEPROM word reserved for LTpowerPlay. R/W Word
0xB1 EEPROM word reserved for LTpowerPlay. R/W Word
N
Y
N
Y
Reg
Reg
Reg
Reg
103
103
103
103
0xB2 EEPROM word reserved for OEM use.
R/W Word
0xB3 EEPROM word available for general data R/W Word
storage.
0x0000
0x0000
l
USER_DATA_04
0xB4 EEPROM word available for general data R/W Word
storage.
N
Reg
103
MFR_EE_UNLOCK
MFR_EE_ERASE
MFR_EE_DATA
0xBD (contact the factory)
0xBE (contact the factory)
0xBF (contact the factory)
103
103
103
77
l
MFR_CHAN_CONFIG_
LTC3882-1
0xD0 LTC3882-1 channel-specific
configuration.
R/W Byte
R/W Byte
Y
Reg
0x1D
l
l
MFR_CONFIG_ALL_LTC3882-1 0xD1 LTC3882-1 device-level configuration.
N
Y
Reg
Reg
0x01
73
MFR_FAULT_PROPAGATE_
LTC3882-1
0xD2 Configure LTC3882-1 status propagation R/W Word
0x6993
101
via FAULTn pins.
l
l
l
MFR_VOUT_AVP
0xD3 Specify V
load line.
R/W Word
Y
Y
Y
L11
Reg
Reg
%
0%
81
78
OUT
0x8000
MFR_PWM_MODE_LTC3882-1 0xD4 LTC3882-1 channel-specific PWM mode R/W Byte
control.
0xC8
0xC0
MFR_FAULT_RESPONSE
0xD5 PWM response when FAULTn pin is low. R/W Byte
101
38821f
40
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LTC3882-1
pMbꢀꢁ coMManD suMMary
Table 7. PMBus Command Summary
CMD
DATA
DEFAULT
VALUE
SEE
COMMAND NAME
CODE DESCRIPTION
TYPE
R Byte
R Word
PAGED FORMAT UNITS NVM
PAGE
MFR_OT_FAULT_RESPONSE
MFR_IOUT_PEAK
0xD6 Internal overtemperature fault response.
N
Y
Reg
L11
0xC0
98
93
0xD7 Maximum I
measurement since last
A
ms
ms
V
OUT
MFR_CLEAR_PEAKS.
l
l
MFR_RETRY_DELAY
MFR_RESTART_DELAY
MFR_VOUT_PEAK
MFR_VIN_PEAK
0xDB Minimum time before retry after a fault. R/W Word
Y
Y
Y
N
Y
L11
L11
L16
L11
L11
350ms
0xFABC
99
84
93
93
94
0xDC Minimum time RUN pin is held low by
the LTC3882-1.
R/W Word
R Word
R Word
R Word
500ms
0xFBE8
0xDD Maximum V
measurement since last
OUT
MFR_CLEAR_PEAKS.
0xDE Maximum V measurement since last
V
IN
MFR_CLEAR_PEAKS.
MFR_TEMPERATURE_1_PEAK 0xDF Maximum external temperature
°C
measurement since last MFR_CLEAR_
PEAKS.
MFR_CLEAR_PEAKS
MFR_PADS_LTC3882-1
MFR_ADDRESS
0xE3 Clear all peak values.
Send Byte
R Word
N
N
N
94
91
72
0xE5 State of selected LTC3882-1 pads.
Reg
Reg
l
0xE6 Specify right-justified 7-bit device
address.
R/W Byte
0x4F
MFR_FAULT_LOG_STORE
0xEA Force transfer of fault log from operating Send Byte
memory to EEPROM.
N
103
MFR_FAULT_LOG_CLEAR
MFR_FAULT_LOG
0xEC Clear existing EEPROM fault log.
0xEE Read fault log data.
Send Byte
R Block
N
N
N
N
102
102
91
Reg
Reg
MFR_COMMON
0xEF LTC-generic device status reporting.
R Byte
MFR_COMPARE_USER_ALL
0xF0 Compare operating memory with
EEPROM contents.
Send Byte
103
MFR_TEMPERATURE_2_PEAK 0xF4 Maximum internal temperature
measurement since last
R Word
N
L11
°C
94
MFR_CLEAR_PEAKS.
l
l
l
l
l
MFR_PWM_CONFIG_LTC3882-1 0xF5 LTC3882-1 PWM configuration common R/W Byte
to both channels.
N
Y
Y
Y
Y
Reg
CF
0x14
76
83
86
86
72
MFR_IOUT_CAL_GAIN_TC
0xF6 Output current sense element
temperature coefficient.
R/W Word
R/W Word
R/W Word
R/W Byte
ppm/°C
°C or V
3900ppm/°C
0x0F3C
MFR_TEMP_1_GAIN
0xF8 Slope for external temperature
calculations.
CF
1.0
0x4000
MFR_TEMP_1_OFFSET
MFR_RAIL_ADDRESS
0xF9 Offset addend for external temperature
calculations.
L11
Reg
0.0
0x8000
0xFA Specify unique right-justified 7-bit
address for channels comprising a
PolyPhase output.
0x80
MFR_RESET
0xFD Force full reset without removing power. Send Byte
N
74
NVM
l
Indicates a command value stored to internal EEPROM using STORE_USER_ALL or restored to RAM from internal EEPROM at power-up or
execution of RESTORE_USER_ALL or MFR_RESET.
38821f
41
For more information www.linear.com/LTC3882-1
LTC3882-1
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Efficiency Considerations
choosing a driver with very low drive resistance and a
MOSFET with low gate charge Q , gate resistance R
G
G
Normally, one of the primary goals of any LTC3882-1 ap-
plication will be to obtain the highest practical conversion
efficiency. The efficiency of a switching regulator is equal
to the output power divided by the input power. It is often
useful to analyze individual losses to determine what is
limitingtheefficiencyandtoascertainwhichchangewould
producethemostimprovement.Balancingorlimitingthese
individual losses plays a dominant role in the component
selection process outlined over the next few sections.
andMillercapacitanceC
can be estimated by:
.Absolutetransitionloss
MILLER
2
P
= (1.7) • V • I
• C • f
MILLER PWM
TRANS
IN
OUT
4. Gatedrivecurrentisequaltothesumofthetopandbot-
tomMOSFETgatechargesmultipliedbythefrequencyof
operation. These charges are based on the gate voltage
applied by the FET driver and can be determined from
manufacturer curves like the one shown in Figure 21.
Many driver ICs employ asymmetrical gate voltages for
top and bottom FETs.
Percent efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2, et al, are the individual losses as a percent-
Other sources of loss include body or Schottky diode
conduction during the driver dependent non-overlap time
andinductorcorelosses. Theselattercategoriesgenerally
account for less than 2% total additional loss.
age of input power: 100 • P /P .
Ln IN
Although all dissipative elements in the system produce
losses, four main sources usually account for most of
the losses in LTC3882-1 applications: IC supply current,
PWM Frequency and Inductor Selection
2
I R losses, topside power MOSFET transition losses and
TheselectionofthePWMswitchingfrequencyisatrade-off
betweenefficiency,transientresponseandcomponentsize.
High frequency operation reduces the size of the inductor
and output capacitor as well as increasing the maximum
practical control loop bandwidth. However, efficiency is
generally lower due to increased transition and switch-
ing losses. The inductor value is related to the switching
total gate drive current.
1. The LTC3882-1 IC supply current is a DC value given
in the Electrical Characteristics table. The absolute loss
created by the IC itself is approximately this current
timestheV supplyvoltage.ICsupplycurrenttypically
CC
results in a small loss (<0.1%).
frequency f
and step-down ratio. It should be selected
2
PWM
2. I R losses occur mainly in the DC resistances of the
to meet choke ripple current requirements. The inductor
value can be calculated using the following equation:
MOSFET, inductor, PCB routing, and input and output
capacitor ESR. Since each MOSFET is only on for part
ofthecycle,itson-resistanceiseffectivelymultipliedby
the percentage of the cycle it is on. Therefore the bot-
tom MOSFET should have a much lower on-resistance
⎛
⎞
⎛
⎞
VOUT
PWM •ΔIL
VOUT
L =
• 1–
⎜
⎟
⎜
⎟
f
V
⎝
⎠
⎝
⎠
IN
R
DS(ON)
than the top MOSFET in high step-down ratio
Allowing a larger value of choke ripple current (∆I ) leads
L
applications. It is crucial that careful attention is paid
to the layout of the power path on the PCB to minimize
its resistance. In a 2-phase 1.2V system, 1mΩ of PCB
resistance at the output costs 5% in efficiency with the
output running at 60A.
to smaller L, but results in greater core loss and higher
output voltage ripple for a given output capacitance and/
or ESR. A reasonable starting point for setting the ripple
current is 30% of the maximum output current.
The inductor saturation current rating needs to be higher
thanthepeakinductorcurrentduringtransientconditions.
3. Transition losses apply only to the topside MOSFET and
becomesignificantwhenoperatingathighinputvoltages
(typically above 12V). This loss can be minimized by
If I
is the maximum rated load current, then the maxi-
OUT
mum transient current I
would normally be chosen to
MAX
be some factor greater than I
(e.g., 1.6 • I ).
OUT
OUT
38821f
42
For more information www.linear.com/LTC3882-1
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The minimum saturation current rating should be chosen
to allow margin due to manufacturing and temperature
variation in the sense resistor or inductor DCR. A reason-
is normally less important for overall efficiency than its
input capacitance. MOSFET manufacturers have designed
special purpose devices that provide reasonably low on-
resistance with significantly reduced input capacitance
for the main switch application in switching regulators.
able I value would be 2.2 • I
.
SAT
OUT
The programmed current limit IOUT_OC_FAULT_LIMIT
must be low enough to ensure that the inductor never
saturates and high enough to allow increased current
duringtransientconditionswithmarginforDCRvariation.
For example, if
Selection criteria for the power MOSFETs include on-
resistance, gate charge, Miller capacitance, breakdown
voltage and maximum output current.
For maximum efficiency, R
and Q should be mini-
G
DS(ON)
I
I
= 2.2 • I , and
mized. Low R
minimizes conduction losses and low
SAT
OUT
DS(ON)
Q minimizes switching and transition losses. MOSFET
G
= 1.6 • I
MAX
OUT
gate charge can be taken from the typical gate charge
a reasonable output current limit would be
IOUT_OC_FAULT_LIMIT = 1.8 • I
curve included on most data sheets (Figure 21).
OUT
Once the value of L is known, the type of inductor must be
selected.Highefficiencyconvertersgenerallycannotafford
the core losses found in low cost powdered iron cores,
forcingtheuseofmoreexpensiveferriteormolypermalloy
cores.Also,corelossesdecreaseasinductanceincreases.
Unfortunately, increased inductance requires more turns
of wire, larger inductance and larger copper losses.
MILLER EFFECT
V
GS
Q
Q
B
A
Q
IN
C
Q
Q
V
MILLER = ( B – A)/ DS
38821 F21
Ferritedesignshaveverylowcorelossandarepreferredat
highswitchingfrequencies.However,thesecorematerials
exhibit hard saturation, causing an abrupt reduction in the
inductance when the peak current capability is exceeded.
Do not allow the core to saturate!
Figure 21. Typical MOSFET Gate Charge Curve
C
is the most important selection criteria for deter-
MILLER
mining the transition loss term in the top MOSFET but is
not directly specified on MOSFET data sheets. C
is
MILLER
equal to the increase in gate charge along the horizontal
axis of Figure 21 while the curve is approximately flat,
Power MOSFET Selection
divided by the specified change in V . This result is
DS
The LTC3882-1 requires at least two external N-channel
powerMOSFETsperchannel,oneforthetop(main)switch
andoneormoreforthebottom(synchronous)switch.The
number, type and on-resistance of the MOSFETs selected
should take into account the voltage step-down ratio and
the FET circuit position (main or synchronous switch).
A much smaller and lower input capacitance MOSFET
should be used for the top MOSFET in applications that
have an output voltage that is less than one-third of the
input voltage. At operating frequencies above 300kHz
then multiplied by the ratio of the actual application V
DS
to the V specified on the gate charge curve. When the
DS
controller is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
VOUT
Main Switch Duty Cycle =
V
IN
V – V
IN
OUT
Synchronous Switch Duty Cycle =
V
IN
and where V >> V , the top MOSFET on-resistance
IN
OUT
38821f
43
For more information www.linear.com/LTC3882-1
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The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
voltage rating of the MOSFET. If this ringing cannot be
avoided and exceeds the maximum rating of the device,
choose a higher voltage rated MOSFET.
VOUT
PMAIN
=
I
(
2 (1+δ)RDS(ON)
+
)
MAX
V
IN
MOSFET Driver Selection
2 IMAX
Gate driver ICs, DrMOS devices and power blocks with an
interface compatible with the LTC3882-1 3.3V three-state
PWM control output(s) can be used. An external resistor
divider may be needed to set three-state control voltage
outputs to mid-rail while in the high impedance state, de-
pendingonthedriverselected.Theseexternaldriver/power
circuits do not typically present a heavy capacitive load to
the LTC3882-1 PWM outputs. Suitable drivers such as the
LTC4449 are capable of driving large gate capacitances at
high transition rates. In fact, when driving MOSFETs with
very low gate charge, it is sometimes helpful to slow down
the drivers by adding small gate resistors (5Ω or less) to
reduce noise and EMI caused by fast transitions.
V
R
C
•
(
DR )(
)
IN
MILLER
2
⎡
⎢
⎢
⎣
⎤
1
1
+
f
(
)
⎥
PWM
V – VTH(IL) VTH(IL) ⎥
GG
⎦
V – V
IN
OUT
PSYNC
=
I
(
2 (1+δ)RDS(ON)
)
MAX
V
IN
where δ is the temperature dependency of R
, R
DS(ON) DR
is the effective top driver resistance, V is the drain po-
IN
tential and the change in drain potential in the particular
application. V is the applied gate voltage, V
is
GG
TH(IL)
the typical gate threshold voltage specified in the power
MOSFET data sheet at the specified drain current, and
Using PWM Protocols
C
is the capacitance calculated using the technique
MILLER
previously described.
For successful utilization of the driver selected, the
appropriate LT3882-1 PWM control protocol must be
programmed. The LTC3882-1 supports two three-state
PWM control protocols. See bit[1] of the MFR_PWM_
MODE_LTC3882-1 PMBus command.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
versus temperature curve.
DS(ON)
Typical values for δ range from 0.005/°C to 0.01/°C de-
pending on the particular MOSFET used.
2
The first of these protocols (bit[1]=0) is for drivers con-
trolled by a single 3-state input that have sufficiently short
delay to the diode emulation state (both top and bottom
power MOSFETs disabled in a fraction of a PWM cycle),
such as the LTC4449. The second protocol (bit[1]=1)
handles all other 3.3V compatible drivers with a single
3-state control input.
BothMOSFETshaveI RlosseswhilethetopsideN-channel
losses also include transition losses, which are highest
at high input voltages. For V < 20V the high current ef-
IN
ficiency generally improves with larger MOSFETs, while
for V > 20V the transition losses rapidly increase to
IN
the point that the use of a higher R
device with
DS(ON)
lower C
actually provides higher efficiency. The
MILLER
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
C Selection
IN
The input bypass capacitance for an LTC3882-1 circuit
needs to have ESR low enough to keep the supply drop
low as the top MOSFETs turn on, RMS current capability
adequate to withstand the ripple current at the input, and
a capacitance value large enough to maintain the input
voltage until the input supply can make up the difference.
Generally, a capacitor that meets the first two require-
ments (particularly a non-ceramic type) will have far more
Multiple MOSFETs can be used in parallel to lower R
DS(ON)
and meet the current and thermal requirements if desired.
If using discrete drivers and MOSFETs, check the stress
on the MOSFETs by independently measuring the drain-
to-source voltages directly across the device terminals.
Bewareofinductiveringingthatcouldexceedthemaximum
38821f
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capacitance than is required to keep capacitance-based
droop under control.
fromhigherinductance,largercasesizeandlimitedsurface
mountapplicability;andelectrolyticcapacitorshavehigher
ESRandcandryout.SanyoOS-CONSVP(D)series,Sanyo
POSCAP TQC series, or Panasonic EE-FT series aluminum
electrolyticcapacitorscanbeusedinparallelwithacouple
of high performance ceramic capacitors as an effective
means of achieving low ESR and high bulk capacitance.
The input capacitance voltage rating should be at least 1.4
times the maximum input voltage. Power loss due to ESR
2
occurs as I R dissipation in the capacitor itself. The input
capacitor RMS current and its impact on any preceding
input network is reduced by PolyPhase architecture. It can
be shown that the worst case RMS current occurs when
only one controller is operating. The controller with the
InadditiontoPWMbulkinputcapacitance,asmall(0.01ꢀF
to 1ꢀF) bypass capacitor between the chip VINSNS pin
and ground, placed close to the LTC3882-1, is also sug-
highest(V )(I )productshouldbeusedtodetermine
OUT OUT
the maximum RMS current requirement. Increasing the
outputcurrentdrawnfromtheotherout-of-phasecontrol-
ler will decrease the input RMS ripple current from this
maximum value. Two channel out-of-phase operation
typically reduces the input capacitor RMS ripple current
by a factor of 30% to 70%.
gested. A small resistor placed between the bulk C and
IN
theVINSNSpinprovidesfurtherisolationbetweenthetwo
channels. However, if the time constant of any such R-C
network on the VINSNS pin exceeds 30ns, dynamic line
transient response can be adversely affected.
C
OUT
Selection
In continuous inductor conduction mode, the source cur-
rent of the top power MOSFET is approximately a square
The selection of C
is primarily determined by the ESR
OUT
requiredtominimizevoltagerippleandloadsteptransients.
waveofdutycycleV /V .ThemaximumRMScapacitor
OUT IN
The output ripple ∆V
is approximately bounded by:
current in this case is given by:
OUT
⎛
⎞
1
VOUT V – V
(
)
IN
OUT
ΔVOUT ≤ ΔIL ESR+
⎜
⎟
IRMS ≈IOUT(MAX)
8•fPWM •COUT
⎝
⎠
V
IN
where ∆I is the inductor ripple current.
L
This formula has a maximum at V = 2V , where
IN
OUT
⎛
⎞
VOUT
L•fPWM
VOUT
I
= I /2
OUT
RMS
ΔIL =
1–
⎜
⎟
V
⎝
⎠
IN
This simple worst-case condition is commonly used for
design because even significant deviations do not offer
much relief.
Since ∆I increases with input voltage, the output ripple
L
voltage is highest at maximum input voltage. Typically
once the ESR requirement is satisfied, the capacitance is
adequate for filtering and has the necessary RMS current
rating.
Notethatmanufacturerripplecurrentratingsforcapacitors
are often based on only 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose
a capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. Always consult the
manufacturer if there is any question.
Manufacturers such as Sanyo, Panasonic and Cornell Du-
biliershouldbeconsideredforhighperformancethrough-
hole capacitors. The OS-CON semiconductor electrolyte
capacitor available from Sanyo has a good (ESR)(size)
product. An additional ceramic capacitor in parallel with
polarized capacitors is recommended to offset the effect
of lead inductance.
Ceramic, tantalum, semiconductor electrolyte (OS-CON),
hybrid conductive polymer (SUNCON) and switcher-rated
electrolyticcapacitorscanbeusedasinputcapacitors,but
each has drawbacks. Ceramics have high voltage coeffi-
cients of capacitance and may have audible piezoelectric
effects;tantalumsneedtobesurge-rated;OS-CONssuffer
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or transient current
38821f
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For more information www.linear.com/LTC3882-1
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handling requirements of the application. Aluminum elec-
trolytic and dry tantalum capacitors are both available in
surfacemountconfigurations.Newspecialpolymersurface
mount capacitors offer very low ESR also but have much
lower capacitive density per unit volume. In the case of
tantalum, it is critical that the capacitors are surge tested
for useinswitching power supplies. Severalexcellentout-
put capacitor choices include the Sanyo POSCAP TPD/E/F
series, the Kemet T520, T530 and A700 series, NEC/Tokin
NeoCapacitors and Panasonic SP series. Other suitable
capacitor types include Nichicon PL series and Sprague
595D series. Consult the manufacturer for other specific
recommendations.
tion to provide phase boost at the LC pole frequency for
significantly improving the control loop phase margin,
as shown in Figure 23.
C2
V
OUT
C1
C3
R3
R2
R1
INTERNAL
–
FB
EA
COMP
+
V
DAC
3882 F22
Figure 22. Type 3 Compensation Circuit
Feedback Loop Compensation
–1
TheLTC3882-1isavoltagemodecontrollerwithasecond,
dedicatedcurrentsharinglooptoprovideexcellentphase-
to-phase current sharing in PolyPhase applications. The
current sharing loop is internally compensated.
GAIN
+1
–1
0
FREQ
–90
PHASE
–180
–270
–380
BOOST
38821 F23
While Type 2 compensation for the voltage control loop
may be adequate in some applications (such as with the
use of high ESR bulk capacitors), Type 3 compensation
and ceramic capacitors are recommended for optimum
transient response.
Figure 23. Type 3 Compensation Frequency Response
In a typical LTC3882-1 circuit, the feedback loop closed
around this control amplifier and compensation network
consists of the line feedforward circuit, the modulator,
the external inductor and the output capacitor. All these
componentsaffectloopbehaviorandneedtobeaccounted
for in the frequency compensation.
Figure 22 shows a simplified view of the error amplifier EA
for one LTC3882-1 channel. The positive input of the error
amplifier is connected to the output of an internal 12-bit
DAC fed by a 1.024V reference, while the negative input is
connected to the FB pin and other internal circuits (not all
shown). R1 is internal to the IC with a value range given
The modulator consists of the PWM generator, the output
MOSFET drivers and the external MOSFETs themselves.
Step-down modulator gain varies linearly with the input
voltage. The line feedforward circuit compensates for this
by the R
parameter in the Electrical Characteristics
VSFB
table. The output is connected to COMP, from which the
PWM controller derives the required output duty cycle. To
speedupovershootrecoverytime,themaximumpotential
at the COMP pin is internally clamped.
changeingain, andprovidesaconstantgainA
of4V/V
MOD
fromtheerroramplifieroutputCOMPtotheinductorinput
(average DC voltage) regardless of V . The combination
IN
Unlike many regulators that use a transconductance (g )
m
of the line feedforward circuit and the modulator looks
like a linear voltage transfer function from COMP to the
inductor input with a fairly benign AC behavior at typical
loop compensation frequencies. Significant phase shift
will not begin to occur in this transfer function until half
the switching frequency.
amplifier, the LTC3882-1 is designed to use an inverting
summing amplifier topology with the FB pin configured
as a virtual ground. This allows feedback gain to be tightly
controlled by external components, which is not possible
with a simple g amplifier. The voltage feedback amplifier
m
also provides flexibility in choosing pole and zero loca-
tions. In particular, it allows the use of Type 3 compensa-
38821f
46
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Theexternalinductor/outputcapacitorcombinationmakes
a more significant contribution to loop behavior. These
componentscausea2ndorderamplituderoll-offthatfilters
the PWM waveform, resulting in the desired DC output
voltage. But the additional 180° phase shift produced by
this filter causes stability issues in the feedback loop and
must be frequency compensated. At higher frequencies,
the reactance of the output capacitor will approach its
ESR, and the roll-off due to the capacitor will stop, leaving
–20dB/decade and 90° of phase shift.
fPWM
10
fC =crossover frequency =
1
fZ1(ERR) =fLC =
2πR2C1
fC
5
1
fZ2(RES)
=
=
2π(R1+R3)C3
1
fP1(ERR) =fESR
=
2πR2(C1//C2)
1
fP2(RES) =5fC =
The transfer function of the Type 3 circuit shown in
Figure 22 is given by the following equation:
2πR3C3
Required error amplifier gain at frequency f is:
C
VCOMP
VOUT
–(1+sC1R2)[1+s(R1+R3)C3]
sR1(C1+C2)[1+s(C1//C2)R2](1+sC3R3)
=
2
2
⎛
⎞
⎛
⎞
fC
fC
f
ESR
≈ 40log 1+
–20log 1+
–15.56
⎜
⎟
⎜
⎟
f
⎝
⎠
⎝
⎠
LC
The RC network across the error amplifier and the feed-
forward components R3 and C3 introduce two pole-zero
pairs to obtain a phase boost at the system unity-gain
Once the value of resistor R1 (function of selected V
OUT
range) and pole/zero locations have been decided, the
value of R2, C1, C2, R3 and C3 can be obtained from the
previous equations.
(crossover)frequency,f .Intheory,thezerosandpolesare
C
placedsymmetricallyaroundf ,andthespreadbetweenthe
C
zeros and the poles is adjusted to give the desired phase
Compensating a switching power supply feedback loop is
a complex task. The applications shown in this data sheet
providetypicalvalues,optimizedforthepowercomponents
shown.Thoughsimilarpowercomponentsshouldsuffice,
substantially changing even one major power component
may degrade performance significantly. Stability also may
depend on circuit board layout. To verify the calculated
component values, all new circuit designs should be
prototyped and tested for stability.
boostatf .However,inpractice,ifthecrossoverfrequency
C
is much higher than the LC double-pole frequency, this
method of frequency compensation normally generates
a phase dip within the unity bandwidth and creates some
concern regarding conditional stability.
If conditional stability is a concern, move the error ampli-
fier zero to a lower frequency to avoid excessive phase
dip. The following equations can be used to compute the
feedback compensation component values:
The LTPowerCAD software tool can be used as a guide
through the entire power supply design process, includ-
ing optimization of circuit component values according to
system requirements.
1
fLC =
2π LCOUT
1
fESR
=
2πRESR OUT
C
PCB Layout Considerations
choose:
To prevent magnetic and electrical field radiation or high
frequency resonant problems and to ensure correct IC
operation, proper layout of the components connected
to the LTC3882-1 is essential. Refer to Figure 24, which
also illustrates current waveforms typically present in the
circuit branches. R
will be replaced with a dead short
SENSE
ifDCRsensingisused.Formaximumefficiency,theswitch
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noderiseandfalltimesshouldbeminimized.Thefollowing
PCB design priority list will help ensure proper topology.
sensing is used, place the top resistor (R1, Figure 25)
close to the switch node.
1. Place a ground or DC voltage layer between a power
layer and a small-signal layer. Generally, power planes
should be placed on the top layer (4-layer PCB), or top
and bottom layer if more than 4 layers are used. Use
wide/short copper traces for power components and
avoid improper use of thermal relief around power
plane vias to minimize resistance and inductance.
6. Place low ESR output capacitors adjacent to the sense
resistor output and ground. Output capacitor ground
connections must feed into the same copper that con-
nects to the input capacitor ground before connecting
back to system ground.
7. Connection of switching ground to system ground,
small-signalanaloggroundoranyinternalgroundplane
should be single-point. If the system has an internal
systemgroundplane, agoodwaytodothisistocluster
viasintoasinglestarpointtomaketheconnection.This
cluster should be located directly beneath the IC GND
paddle, which serves as both analog signal ground and
2. Low ESR input capacitors should be placed as close
as possible to switching FET supply and ground con-
nections with the shortest copper traces possible. The
switching FETs must be on the same layer of copper
as the input capacitors with a common topside drain
connection at C . Do not attempt to split the input
the negative sense for V
. A useful CAD technique
OUT1
IN
decoupling for the two channels, as a large resonant
loop can result. Vias should not be used to make these
connections. Avoid blocking forced air flow to the
switching FETs with large size passive components.
is to make separate ground nets and use a 0Ω resistor
to connect them to system ground.
8. Place all small-signal components away from high
frequency switching nodes. Place decoupling capaci-
tors for the LTC3882-1 immediately adjacent to the IC.
3. If using a discrete FET driver, place that IC close to the
switching FET gate terminals, keeping the connecting
traces short to produce clean drive signals. This rule
also applies to driver IC supply and ground pins that
connect to the switching FET source pins. The driver
IC can be placed on the opposite side of the PCB from
the switching FETs.
9. A good rule of thumb for via count in a given high cur-
rent path is to use 0.5A per via. Be consistent when
applying this rule.
10. Copper fills or pours are good for all power connec-
tions except as noted above in rule 3. Copper planes
on multiple layers can also be used in parallel. This
helps with thermal management and lowers trace
inductance, whichfurtherimprovesEMIperformance.
4. Place the inductor input as close as possible to the
switchingFETs.Minimizethesurfaceareaoftheswitch
node. Make the trace width the minimum needed to
support the maximum output current. Avoid copper
fillsorpours.Avoidrunningtheconnectiononmultiple
copper layers in parallel. Minimize capacitance from
the switch node to any other trace or plane.
Output Current Sensing
+
–
The I
and I
pins are high impedance inputs to
SENSE
SENSE
internalcurrentcomparators,thecurrent-sharingloopand
telemetry ADC. The common mode range of the current
senseinputsisapproximately0Vto5.5V.Continuouslinear
operation is provided throughout this range. Maximum
5. Place the output current sense resistor (if used) im-
mediately adjacent to the inductor output. PCB traces
for remote voltage and current sense should be run
togetherbacktotheLTC3882-1inpairswiththesmall-
est spacing possible on any given layer on which they
are routed. Avoid high frequency switching signals
and ideally shield with ground planes. Locate any filter
component on these traces next to the LTC3882-1,
and not at the Kelvin sense location. However, if DCR
+
–
differentialcurrentsenseinput(I
–I
)is70mV,
SENSE
SENSE
including any variation over temperature. These inputs
must be properly connected in the application at all times.
TomaximizeefficiencyatfullloadtheLTC3882-1isdesigned
to sense current through the inductor’s DCR, as shown in
Figure 25. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
38821f
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SW1
L1
R
SENSE1
V
OUT1
D1
C
OUT1
R
L1
V
IN
R
IN
C
IN
SW0
L0
R
SENSE0
V
OUT0
D0
C
OUT0
R
L0
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
38821 F24
Figure 24. High Frequency Paths and Branch Current Waveforms
for most inductors suitable to LTC3882-1 applications, is
between 0.3mΩ and 1mΩ. If the filter RC time constant is
chosen to be exactly equal to the L/DCR time constant of
the inductor, the voltage drop across the external capaci-
tor is equal to the voltage drop across the inductor DCR.
Check the manufacturer’s data sheet for specifications
regardingtheinductorDCRinordertoproperlydimension
the external filter components. The DCR of the inductor
can also be measured using a good RLC meter.
Resistor R1 should be placed close to the switch node,
to prevent noise from coupling into sensitive small-signal
nodes. Capacitor C1 should be placed close to the IC pins.
Anexampleofdiscreteresistorsensingofoutputcurrentis
showninFigure26. Previously, theparasiticinductanceof
the sense resistor could represent a relatively small error.
New high current density solutions may utilize low sense
resistor values producing sense voltages less than 20mV.
In addition, inductor ripple currents greater than 50%
with operation up to 1MHz are becoming more common.
Use the nominal or measured value of DCR to program
IOUT_CAL_GAIN (in mΩ). The temperature coefficient
of the inductor’s DCR is typically high, like copper. Again,
consultthemanufacturer’sdatasheet. TheLTC3882-1can
adjust for this non-ideality if the correct MFR_IOUT_CAL_
GAIN_TC value is programmed. Typically this coefficient
is around 3900ppm/°C.
Undertheseconditions,thevoltagedropacrossthesense
resistor’s parasitic inductance is no longer negligible. An
RC filter can be used to extract the resistive component
of the current sense signal in the presence of parasitic
inductance. Forexample, Figure27illustratesthevoltage
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waveform across a 2mΩ resistor with a 2010 footprint.
The waveform is the superposition of a purely resistive
component and a purely inductive component. If the
RC time constant is chosen to be close to the parasitic
inductance divided by the sense resistor (L/R), the re-
sultant waveform looks resistive, as shown in Figure 28.
If low value (<5mΩ) sense resistors are used, verify that
the signal across C resembles the current through the
F
inductor, and reduce R to eliminate any large step associ-
F
ated with the turn-on of the primary switch.
Output Voltage Sensing
Accurate Kelvin sensing techniques should be used
to connect the output voltage differentially back to the
For applications using low maximum sense voltages,
check the sense resistor manufacturer’s data sheet for
information about parasitic inductance. In the absence of
data, measure the voltage drop directly across the sense
resistor to extract the magnitude of the ESL step and the
following equation to determine the ESL:
LTC3882-1V
pinsofthemasterchannelforthebest
SENSE
output voltage regulation at the point of load. These pins
also provide the ADC inputs for output voltage telemetry.
VESL(STEP)
tON •tOFF
tON + tOFF
ESL =
•
∆IL
V
IN
VINSNS
12V
5V
LTC3882-1
V
CC
V
V
BOOST
TG
CC
INDUCTOR
DCR
V
DD33
LOGIC
L
LTC4449
PWM
+
IN
TS
V
OUT
BG
–
I
I
GND SENSE SENSE
GND
R1*
C1*
38821 F25
L
DCR
R1 • C1 =
*PLACE R1 NEAR INDUCTOR
+
–
PLACE C1 NEAR I
, I
PINS
SENSE SENSE
Figure 25. Inductor DCR Output Current Sense
V
IN
VINSNS
12V
5V
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
LTC3882-1
V
V
V
BOOST
TG
CC
CC
V
DD33
LOGIC
L
R
ESL
S
LTC4449
PWM
+
IN
TS
V
OUT
BG
C • 2R ≤ ESL/R
–
F
F
S
I
I
GND SENSE SENSE
GND
POLE-ZERO
CANCELLATION
C
F
R
R
F
F
38821 F26
FILTER COMPONENTS PLACED NEAR SENSE PINS
Figure 26. Discrete Resistor Output Current Sense
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While these considerations may or may not be important
start-up voltage ramp. The maximum rate at which the
LTC3882-1 can move the output in this fashion is 100µs/
step. Soft-start is disabled by setting TON_ RISE to any
value less than 0.250ms. The LTC3882-1 will perform the
necessary math internally to assure the voltage ramp is
controlled to the desired slope. However, the voltage slope
cannot be any faster than the fundamental limits of the
power stage. The smaller TON_RISE becomes, the more
noticeable an output voltage stair-step may become.
for slave channels, V
must be connected back to the
OUT
slave channel V
pin(s) in order for the I
telemetry
SENSE
OUT
ofthosephasestobeaccurate.Soingeneral,soundKelvin
V
sensing techniques for all LTC3882-1 channels is
OUT
recommended.
The LTC3882-1 also supports soft turn off in the same
manner it controls turn on. TOFF_FALL is processed when
the RUN pin goes low or if the part is commanded off.
If the part faults off or FAULT is pulled low and the part
is programmed to respond to this, the PWM instantly
commands the output off. The output will then decay as
a function of load current.
V
RSENSE
20mV/DIV
V
ESL(STEP)
38821 F27
500ns/DIV
Figure 27. Voltage Measured Directly Across RSENSE
The LTC3882-1 can produce a controlled ramp off as long
as the power stage is configured to run in CCM and the
TOFF_FALL time is sufficiently slow that the power stage
can achieve the desired slope. The TOFF_FALL time can
only be met if the power stage can sink sufficient current
under closed loop control to assure the output is at 0V
by the end of the fall time. If TOFF_FALL is shorter than
the time required to discharge the load capacitance, the
output will not reach 0V. In this case, the power stage will
V
ISENSE
20mV/DIV
38821 F28
500ns/DIV
still be commanded off at the end of TOFF_FALL and V
OUT
will decay at a rate determined by the load. If the control-
ler is set to run DCM, the controller will not pull negative
current and the output will only be pulled low by the load,
not the power stage. The maximum fall time is limited to
1.3 seconds. The smaller TOFF_FALL becomes, the more
noticeable an output voltage stair-step may become.
Figure 28. Voltage Measured at ISENSE Pins
Soft-Start and Stop
The LTC3882-1 uses digital ramp control to create both
soft-start and soft-stop.
The LTC3882-1 must enter the run state prior to soft-start.
The RUN pins are released after the part initializes and
VINSNS is determined to be greater than the VIN_ON
threshold.
Time-Based Output Sequencing and Ramping
TheLTC3882-1TON_DELAYandTOFF_DELAYcommands
canbeusedincombinationwiththeriseandfalltimecom-
mandscoveredintheprevioussectiontoimplementawide
range of versatile sequencing and ramping schemes. The
key to time-based sequencing and ramping is the ability of
LTC3882-1 master phases to move their outputs up and
down according to PMBus command values as shown in
Figure 29 and Figure 30.
Onceintherunstate,soft-startisperformedafteranyaddi-
tionalprescribeddelay(nextsection)byactivelyregulating
the load voltage while digitally ramping the target voltage
from 0V to the commanded voltage set point. Rise time of
thevoltagerampcanbeprogrammedusingtheTON_RISE
command to minimize inrush currents associated with
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AsshowninFigure29, itisimportanttorememberthatthe
hysteresis given in the Electrical Characteristics (EC) table
appliesaboveVOUT_UV_FAULT_LIMIT,whichspecifiesthe
UV limit when the output is falling out of regulation. For
turn-on,theoutputmustriseabovethisprogrammedlimit
plusthehysteresistoavoidexceedingTON_MAX_FAULT_
LIMIT. PGOOD is indicated at that point. For this reason,
VOUT_UV_FAULT_LIMITshouldbemorethan27mVbelow
the programmed output voltage in low range and more
RUN
PGOOD
DIGITAL SERVO
MODE ENABLED
FINAL OUTPUT
VOLTAGE REACHED
TON_MAX_FAULT_LIMIT
VOUT_UV_FAULT_LIMIT
DAC VOLTAGE
ERROR (NOT
TO SCALE)
TIME DELAY OF
<1S, TYPICAL
V
OUT
than54mVbelowV
inhighrange. Thereisafixeddelay
OUT
HYSTERESIS
(NOT TO SCALE)
and other timing uncertainty associated with all changes
in output voltage controlled by the LTC3882-1. A nominal
fixed timing delay of 270µs exists to process any change
in output voltage, including soft start/stop, margining and
generalchangesinVOUT_COMMANDvalue.Thestartofall
time-basedoutputoperationsoccurwithanuncertaintyof
50µs and have a nominal step resolution of 100µs. This
meanstheminimumTON_DELAYorTOFF_DELAYthatthe
LTC3882-1 can produce will range from 220µs to 320µs,
not including basic oscillator tolerances. For software-
based output changes (e.g., margining), this algorithmic
delay begins when the STOP bit is received on the serial
bus. An example of this minimum turn on/off delay and
step-wise output control can be seen in Figure 31, where
TON_DELAY = 0s and TON_RISE = 1ms.
38821 F29
TIME
TON_RISE
TON_DELAY
Figure 29. Time-Based VOUT Turn-On
RUN
V
OUT
38821 F30
TIME
TOFF_DELAY
TOFF_FALL
To effectively implement sequencing and synchronized
ramping between rails controlled by LTC digital power
products, two signals should be shared between all
controlling ICs: SHARE_CLK and RUN (CONTROL pin
on LTC297x products). This facilitates synchronized rail
sequencing on or off based on shared input supply state
(VIN_ONthreshold),externalhardwarecontrol(RUNpin),
or PMBus commands (possibly using global addressing).
Figure 30. Time-Based VOUT Turn-Off
greatly simplify actual system development because rails
can be re-sequenced without a hardware change as final
product requirements evolve. The LTpowerPlay GUI and
LTC3882-1 onboard EEPROM can be used for this task,
avoidingtheneedforfirmwaredevelopmenttomodifyturn
on/off relationships between rails. Entire power systems
can then easily be scaled up or down, facilitating reuse of
proven hardware macro designs.
Figure 32 shows an example of output supply sequencing
using TON_DELAY.
Usingthisscheme,conventionalcoincidentandratiometric
tracking can also be emulated by setting equivalent turn-
on/off delays and appropriate rise and fall times as shown
in Figure 33 and Figure 34.
Voltage-Based Output Sequencing
The LTC3882-1 is capable of voltage-based output se-
quencing. For concatenated events between members of
the LTC388x family, it is possible to control one RUN pin
from a PGOOD pin of a different controller as shown in
Inaddition,theseschemescaneasilybemixedandmatched
to create any necessary ramping controls, some of which
might prove difficult to implement with conventional
analog-only controllers. These programmable features
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Figure 35. This configuration hardware disables the next
downstream controller anytime the output is not within
the specified UV and OV limits, or the upstream controller
is disabled. When indicating power is not good, there is
a 30µs deglitching filter on the PGOOD output to assure
the signal does not toggle repeatedly at lower values of
V
OUT
(1V/DIV)
TON_RISE/FALL due to noise on V . If unwanted transi-
OUT
RUN
(5V/DIV)
tions still occur on PGOOD due to noise or longer rise/fall
settings, place a capacitor to ground on the PGOOD pin
to further filter the waveform. The RC time-constant of
the filter should be low enough to assure no appreciable
delay is incurred. A value of 300μs to 500μs will provide
some additional filtering without significantly delaying
the trigger event.
38821 F31
200µs/DIV
Figure 31. Example of 1ms TON_RISE
1V/DIV
VOUT4
VOUT3
VOUT2
VOUT1
PGOOD0
RUN 0
START
LTC3882-1
RUN 1
PGOOD1
(PGOOD PULL-UP RESISTORS
TO 3.3V NOT SHOWN)
RUN 0
RUN 1
PGOOD0
38821 F32
LTC3882-1
100ms/DIV
PGOOD1
Figure 32. LTC3882-1 Time-Based Supply Sequencing
TO NEXT CHANNEL
IN THE SEQUENCE
38821 F35
Figure 35. Cascade Sequencing Configuration
1V/DIV
VOUT4
VOUT3
VOUT2
VOUT1
1V/DIV
VOUT4
VOUT3
VOUT2
VOUT1
38821 F33
100ms/DIV
Figure 33. LTC3882-1 Time-Based Coincident Supply Ramping
38821 F36
100ms/DIV
1V/DIV
Figure 36. Cascade Sequencing Waveforms
VOUT4
VOUT3
VOUT2
VOUT1
When the system is turned off, rails will shut down in the
same order as they turn on, as shown in Figure 36. If a
different sequence is required, the circuit must be rewired
or delays must be added by programming TON_DELAY or
TOFF_DELAY.Afundamentallimitationofthisapplicationis
38821 F34
100ms/DIV
the inability of upstream rails to detect a start-up failure of
Figure 34. LTC3882-1 Time-Based Ratiometric Ramping
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downstreamrails.Duetothis,cascadesequencingshould
not be implemented without an external fast supervisor
to monitor downstream rails and assert a system fault if
problems occur.
AVP DISABLED
I
O
(10A/DIV)
Using Output Voltage Servo
173mV
V
OUT
For best output voltage accuracy, enable digital
servo mode on the master phase by setting bit 6 of
MFR_PWM_MODE_LTC3882-1. In digital servo mode,
the LTC3882-1 will adjust the regulated output voltage
basedonitsrelatedADCvoltagereading. Every100msthe
digital servo loop will step the LSB of the DAC (nominally
1.375mV or 0.6875mV depending on the voltage range
bit) until the output is at the correct ADC reading.
(50mV/DIV)
WITH AVP
I
O
(10A/DIV)
When the master channel is turned on, digital servo is
enabled after all of the following conditions are satisfied.
V
OUT
108mV
• MFR_PWM_MODE_LTC3882-1 Bit 6 Is Set
• The TON_RISE Sequence Is Complete
• A VOUT_UV_FAULT Is Not Present
• An IOUT_OC_FAULT Is Not Present
• MFR_AVP = 0%
(50mV/DIV)
LOOP: BW = 118kHz, PM = 58°, GM = 7dB
38821 F37
Figure 37. Active Voltage Positioning
output filter capacitance for some allowed output voltage
variation over the anticipated load range. An example of
AVP is shown in Figure 37. Refer to LTC Design Solution
10 for additional examples of using AVP to advantage.
Digital servo mode then engages after TON_MAX_
FAULT_LIMIT has expired as shown in Figure 29, unless
that limit is set to 0s (infinite). In that case, the mode is
engaged as soon as the above conditions are satisfied.
MFR_VOUT_AVP specifies the percent reduction in pro-
grammed V
from no load at an output current value
OUT
Using AVP
equal to IOUT_WARN_LIMIT. LTC3882-1 AVP supports
a maximum reduction in V of 15%, corresponding
OUT
The LTC3882-1 features digitally programmable active
voltage positioning (AVP), where output voltage set point
is automatically adjusted as a function of output current at
the full bandwidth of the converter. AVP normally entails
specifyinganoutputloadlineforavoltagemodeswitcherto
allowcurrentsharingbetweenmasterphasesconnectedin
parallel. While AVP can be used to this effect in LTC3882-1
to a 7.5% tolerance about a nominal output voltage at
roughly 50% load. In order to effectively use AVP, apply
the following steps.
1. Set IOUT_OC_WARN_LIMIT. This specifies the master
phase output current at which the programmed AVP
level will apply. Generally this is above the 100% load
point to avoid spurious warnings at full load.
applications, use of the LTC3882-1 I
current sharing
AVG
control loop is recommended instead. This will produce
more accurate sharing across a wider number of phases
without degrading supply output impedance.
2. VOUT_COMMANDshouldbesettothevalueofV de-
OUT
siredwithnoloadontheoutput.VOUT_MARGIN_HIGH/
LOW also specify no-load values when AVP is enabled.
AVP on the LTC3882-1 can only reduce the output from
these levels.
However,AVPcanstillbeusedtogreatbenefitinLTC3882-1
applications. AVP can be applied to minimize the size of
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3. Set MFR_VOUT_AVP to a percentage that produces the
desired output excursion as a function of current.
(READ_IOUT). The necessary correction, which will typi-
cally be less than several percent of the no load output
voltage, is calculated as:
For example, if the goal is to allow a 2.5% output change
on a 3.3V 6-phase supply rated at 120A during an output
load step from 20% to 80%, the following parameters
should be programmed.
VOS= VOUT_COMMAND
MFR_VOUT_AVP•READ_IOUT
100•IOUT_OC_WARN_LIMIT
⎛
⎝
⎞
• 1–
⎜
⎟
⎠
Firstsetanoutputcurrentwarninglevelforthemaster(one
of six phases) just slightly higher than the rated full load
to avoid spurious warnings. Typically this same setting
would also be applied to the five slave phases.
– READ_VOUT
PWM Frequency Synchronization
The LTC3882-1 incorporates an internal phase-locked
loop (PLL) which enables synchronization of both PWM
channels (falling edge PWM) to an external CMOS clock
from 250kHz to 1.25MHz. The PLL is locked to the falling
edgeoftheSYNCpinclocksignal. ThisPLLalsogenerates
very accurate channel phase relationships which can be
selected with the MFR_PWM_CONFIG_LTC3882-1 com-
mand. For PolyPhase applications, all phases should be
spaced evenly in the phase diagram for best results. For
instance, a 4-phase system should use a separation of
90° between channels.
IOUT_OC_WARN_LIMIT = 1.1 • 120A/6 = 22A
The open circuit output voltage calculation for the master
phase must reflect that the AVP specification in this case
only covers an output load swing of 60%.
VOUT_COMMAND = 3.3V(1 + 0.5 • 0.025/0.6)
= 3.3687V
The AVP calculation must then account for the fact that
IOUT_OC_WARN_LEVEL is set higher than the 100%
load point.
The PLL has a lock detection circuit. If the PLL should lose
lockduringoperation,bit4oftheSTATUS_MFR_SPECIFIC
command is asserted and the ALERT pin is pulled low,
unless masked. The fault can be cleared by writing a 1 to
STATUS_MFR_SPECIFIC bit 4. A spurious ALERT for an
unlocked PLL may occur at start-up or during a reset if
this fault is not masked.
100%•1.1•2• 3.3687–3.3
(
)
MFR_VOUT_AVP =
3.3687
= 4.487%
With the output voltage at 3.3V at 50% load these set-
tings will move V from approximately 3.34V to about
3.26V when the output load of the rail moves from 24A
to 96A. Note that V will drop to 3.23V at full load in
OUT
Neither PWM channel will transition from off to the RUN
state until PLL lock is indicated. When transitioning a
channel from off to RUN, bit 4 of STATUS_MFR_SPECIFIC
will be set if the PWM ramp generator for that channel
is not also locked to the desired PLL output frequency.
OUT
this design example.
Digital output servo mode is automatically disabled if
AVP is enabled on a master phase. AVP is active during
all output ramping when enabled (e.g., a TON_RISE se-
quence). AVP is disabled on master phases by program-
ming MFR_VOUT_AVP to 0.0% (factory default). AVP is
automatically disabled on phases configured as slaves
If the SYNC pin is not externally clocked in the application,
thePWMswilloperateatthefrequencyspecifiedbyanon-
zero FREQUENCY_SWITCH command. If that command
is set to 0x0000 (external clock only) in EEPROM or with
RCONFIG (FREQ_CFG pin grounded), then at power-up,
or MFR_RESET, or RESTORE_USER_ALL, the PWM will
not start without an external clock input. If the external
clock is lost while programmed for external clock only, or
if the PWM is simply switched to this setting under power
(FB tied to V ).
DD33
Because of related ISENSE input offsets, increased output
voltage error can occur at all operating currents when AVP
is engaged. To minimize this error a calibration offset can
be added to the master phase VOUT_COMMAND value
based on the READ_VOUT value obtained when operat-
ing at a known output current of at least 20% of full load
with no external clock present, the PLL will start/run at
38821f
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the lowest free running frequency created by the internal
VCO. This can be well below the intended PWM frequency
of the application and may cause undesirable operation of
theconverter.Forthisreason,itisgenerallyrecommended
that a useable PWM frequency be programmed for each
channel, regardless of whether that particiular LTC3882-1
unit serves as clock master, or not.
The shared I
and I
signals actively balance the
AVG
AVG_GND
amountofoutputcurrentdeliveredfromeachchannelusing
a secondary current sharing loop. A capacitor with a value
between 100pF and 200pF should be placed between I
AVG
and I
. This capacitance can be distributed across
AVG_GND
LTC3882-1 devices/pins for improved noise immunity. All
pins for a PolyPhase rail should be tied together
I
AVG_GND
and connected to a single ground point at or near the
package paddle of the master phase.
AllchannelsofaPolyPhaserailarerequiredtoshareSYNC
pins.Betweenrailsandforotherconfigurations,suchsyn-
chronizationisoptional. IftheSYNCpinissharedbetween
LTC3882-1s, only one LTC3882-1 should be programmed
to control the SYNC output.
Load sharing accuracy is based primarily on the current
sense amplifier offset of each phase (I
) and the
AVG_VOS
offset of slave current error amplifiers (V
). These are
SIOS
given in the EC table. Current sense gain errors between
LTC3882-1 channels will be negligible. The secondary
current sharing loop acts to average any errors among the
phases. Because of this error averaging and the random
nature of these variables, the EC table limits ensure actual
per-phase offset will be less than or equal to 300ꢀV for
most designs over the full operating temperature range.
PolyPhase Operation and Load Sharing
When the LTC3882-1 is used in a PolyPhase application,
the slave phases must be configured as such by con-
necting their FB pins to V
. Among other things, this
DD33
disablestheerroramplifiersoftheslavephases.Fiveother
pins must then also be shared between all channels of a
PolyPhase rail:
This signifies better than 2% matching when ꢁI
=
SENSE
15mV, not including external factors such as DCR make
tolerance.
• VINSNS
• COMP
+
It is necessary to properly connect V
on a slave
SENSE
phaseforaccurateI telemetry,eventhoughslavephases
• I
OUT
AVG
do use need this information for PWM control. While not
• I
AVG_GND
strictly required, the V
lines of slave phases can
SENSE
• SYNC
simply share with the master to provide additional output
voltagetelemetry.IftheonlyconcernisaccurateslaveI
OUT
UsingacommonVINSNSconnectionreducesthedynamic
range required by the current loop and helps maintain
well-controlled master modulator gain.
+
telemetry, V
SENSE
shorted to V
for that channel may be locally wired
SENSE
. V
–
–
to I
on a slave phase should always be
SENSE
–
for its master channel. I
OC/ROC
SENSE
OUT
The shared COMP signal allows the master phase error
amplifier to control the duty cycle of all slave phases to
produce the commanded output voltage.
function is not affected by V
wiring.
SENSE
All phases must be synchronized to the same shared
SYNC clock and should be programmed to run at the
same default PWM frequency. Phases should be selected
to be evenly spaced around a 360° phasor diagram, and
all phases on a PolyPhase rail should be selected to have
the same maximum duty cycle. Refer to details for MFR_
PWM_CONFIG_LTC3882-1. Figure 38 shows an example
of connections for three phases and Figure 39 shows an
example of an 8-phase rail. Additional shared signals in
thesefigureshighlighttheabilityoftheLTC3882-1tocom-
municate fault status between phases and rails, perform
Slave phases can detect system faults that cause the
master COMP (error amplifier) output to be too high. A
slave phase detecting this kind of error amplifier fault im-
mediately shuts off its PWM output, indicates the fault on
itsVOUT_OVFaultbit,andtakeswhateveradditionalaction
maybeindicatedbyVOUT_OV_FAULT_RESPONSEforthat
channel. If this response is set to only provide hardware-
level response (0x00), then normal channel operation will
automatically resume when the fault condition is cleared.
38821f
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V
IN
+
–
3-PHASE SENSE
1-PHASE SENSE
V
DD33
(0,120)
(60,240)
VINSNS
FB0
FB1
RUN0
RUN1
FAULT0
FAULT1
COMP0
COMP1
VINSNS
FB0
FB1
RUN0
RUN1
FAULT0
FAULT1
COMP0
COMP1
LTC3882-1
LTC3882-1
+
+
+
–
V
V
V
V
V
V
V
V
SENSE0
SENSE0
+
+
SENSE1
SENSE1
–
SENSE0
–
–
SENSE0
–
SENSE1
SENSE1
I
I
AVG_GND
AVG_GND
SYNC (ENABLED) SHARE_CLK
SYNC (DISABLED) SHARE_CLK
I
I
I
I
AVG0 AVG1
GND
GND
AVG0 AVG1
SYSTEM ON/OFF
BOTH ICs SAME DEFAULT FREQUENCY SWITCH
38821 F38
Figure 38. 3+1-Phase Application
38821f
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V
IN
+
–
V
SENSE
OUT
(90,270)
(0,180, CLOCK MASTER)
VINSNS
FB0
FB1
RUN0
RUN1
FAULT0
FAULT1
SYNC
COMP0
COMP1
VINSNS
FB0
FB1
RUN0
RUN1
FAULT0
FAULT1
SYNC
COMP0
COMP1
LTC3882-1
LTC3882-1
+
+
V
SENSE0
V
SENSE0
+
+
V
V
V
V
V
V
I
SENSE1
SENSE1
–
SENSE0
–
–
SENSE0
–
SENSE1
SENSE1
I
AVG_GND
SHARE_CLK
I
AVG_GND
SHARE_CLK
I
I
I
GND
GND
AVG0 AVG1
AVG0 AVG1
(135,315)
(45,225)
V
DD33
VINSNS
FB0
FB1
RUN0
RUN1
FAULT0
FAULT1
SYNC
COMP0
COMP1
VINSNS
FB0
FB1
RUN0
RUN1
FAULT0
FAULT1
SYNC
COMP0
COMP1
LTC3882-1
LTC3882-1
+
+
V
SENSE0
V
V
V
V
SENSE0
+
+
V
V
V
SENSE1
SENSE1
–
SENSE0
–
–
SENSE0
–
SENSE1
SENSE1
I
I
AVG_GND
AVG_GND
SHARE_CLK
SHARE_CLK
I
I
I
I
GND
GND
AVG0 AVG1
AVG0 AVG1
SYSTEM ON/OFF
ALL ICs SAME DEFAULT FREQUENCY SWITCH
38821 F39
Figure 39. 8-Phase Application
38821f
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SINGLE PHASE
DUAL PHASE
PGOOD pins of slave phases may be shorted to a master
PGOOD bus to indicate full output power is available, un-
less the slave channel is used in active phase shedding.
In that case, the slave PGOOD should be left disconnected
or used only to indicate operating status for that phase.
Output current fault and warning limits should each be set
to the same values across all PolyPhase channels using
IOUT_FAULT_LIMIT and IOUT_WARN_LIMIT. The cor-
rect sense resistance and related temperature coefficient
should also be set for each phase (IOUT_CAL_GAIN,
SW1 V
SW1 V
SW2 V
I
CIN
I
I
L1
L2
I
COUT
I
CIN
I
COUT
38821 F40
RIPPLE
Figure 40. Single and 2-Phase Current Waveforms
MFR_IOUT_CAL_GAIN_TC) to achieve accurate I
OUT
telemetry and consistent fault handling across phases.
Because the LTC3882-1 current sharing loop operates by
matching sensed voltage, it is important that well-matched
sense elements be used in the system. Current matching
parametersspecifiedfortheLTC3882-1donotincludethese
external sources of error, such as inductor DCR tolerance.
0.6
1-PHASE
0.5
0.4
0.3
Programming of V
for slave phases.
related parameters is not required
OUT
2-PHASE
0.2
APolyPhasepowersupplysignificantlyreducestheamount
of ripple current in both the input and output capacitors.
The RMS input ripple current is divided by, and the ef-
fective ripple frequency is multiplied by, the number of
phases used as long as the input voltage is greater than
the number of phases used times the output voltage. The
output ripple amplitude is also reduced by the number of
phasesused.Figure40graphicallyillustratestheprinciple.
0.1
0
0.1
0.5
0.7 0.8
0.2 0.3 0.4
0.6
0.9
DUTY FACTOR (V /V
)
OUT IN
38821 F41
Figure 41. Normalized RMS Input Ripple Current
1.0
0.9
0.8
The worst-case RMS ripple current for a single stage de-
sign peaks at an input voltage of twice the output voltage.
The worst case RMS ripple current for a 2-phase design
peaks at output voltages of 1/4 and 3/4 of the input volt-
age. When the RMS current is calculated, higher effective
duty factor results and the peak current levels are divided
as long as the current in each stage is balanced. Refer to
ApplicationNote19athttp://www.linear.com/designtools/
app_notes for a detailed description of how to calculate
RMS current for the single stage switching regulator. Fig-
ure 41 and Figure 42 illustrate how the input and output
currents are reduced by using an additional phase. For a
2-phaseconverter, theinputcurrentpeaksdropinhalfand
the frequency is doubled. The input capacitor requirement
is then theoretically reduced by a factor of four.
1-PHASE
0.7
0.6
0.5
0.4
0.3
2-PHASE
0.2
0.1
0
0.1
0.5
0.7 0.8
0.2 0.3 0.4
0.6
0.9
DUTY FACTOR (V /V
)
OUT IN
38821 F42
Figure 42. Normalized Output Ripple Current [IRMS ~ 0.3(DIC(PP))]
synchronizedtime-basedrailsequencingandrampingand
report accurate output current telemetry for all phases.
In general, only the PGOOD pin of the master phase needs
to be used for external Power Good indication. However,
38821f
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highnoiseenvironmentspreventuseoftheꢁV approach
BE
TSNS
with its lower signal levels.
LTC3882-1
GND
10nF
For either method, the slope of the external temperature
sensor can be modified with the coefficient stored in
MMBT3906
GND
38821 F43
MFR_TEMP_1_GAIN. With the ꢁV approach, typical
BE
Figure 43. External ΔVBE Temperature Sense
PNPs require temperature slope adjustments slightly
less than 1. The MMBT3906 has a recommended value
in this command of approximately MFR_TEMP_1_GAIN =
0.991 based on the ideality factor of 1.01. Simply invert
the ideality factor to calculate the MFR_TEMP_1_GAIN.
Different manufacturers and different lots may have dif-
ferent ideality factors. Consult with the manufacturer to
set this value. Bench characterization over temperature is
recommended when adjusting MFR_TEMP_1_GAIN for
the direct p-n junction measurement.
495µA
TSNS
LTC3882-1
1nF
1.35V AT 25°C
GND
38821 F44
GND
Figure 44. 2D+R Temperature Sense
External Temperature Sense
The offset of the external temperature sense can be ad-
justed by MFR_TEMP_1_OFFSET. For the ꢁV method a
BE
The LTC3882-1 facilitates external measurement of the
power stage temperature of each channel with several
silicon-junction-based means. The voltage produced by
the remote sense circuit is digitized by the internal ADC,
and the computed temperature value is returned by the
paged READ_TEMPERATURE_1 telemetry command.
value of 0 in this register sets the temperature offset to
–273.15°C. For a direct p-n junction measurement, this
parameteradjuststhenominalcircuitvoltageat25°Caway
from that shown in Figure 44.
To ensure proper use of these temperature adjustment
parameters,refertothespecificformulasgivenforthetwo
methodsbytheMFR_PWM_MODE_LTC3882-1command
in the later section covering PMBus command details, as
well as Application Note 137.
The most accurate external temperature measurement
can be made using a diode-connected PNP transistor
such as the MMBT3906 as shown in Figure 43 with bit 5
ofMFR_PWM_MODE_LTC3882-1setto0(ꢁV method).
BE
The BJT should be placed in contact with or immediately
adjacent to the power stage inductor. Its emitter should be
connected to the TSNSn pin while the base and collector
terminals of the PNP transistor must be returned to the
LTC3882-1 GND paddle using a Kelvin connection. For
best noise immunity, the connections should be routed
differentially and a 10nF capacitor should be placed in
parallel with the diode-connected PNP.
Resistor Configuration Pins
As a factory default, the LTC3882-1 is programmed to use
external resistor configuration, allowing output voltage,
PWM frequency and phasing, and the PMBus address to
be set without programming the part through its serial
interface or purchasing devices with custom EEPROM
contents. The RCONFIG pins all require a resistor divider
between V
and GND. The RCONFIG pins are only
DD25
The LTC3882-1 also supports direct junction voltage mea-
surementswhenbit5ofMFR_PWM_MODE_LTC3882-1is
settoone.Thefactorydefaultssupportaresistor-trimmed
dual diode network as shown in Figure 44. However, this
measurementmethodcanbeappliedtosimplesingle-diode
circuits of the type shown in Figure 43 with parameter
adjustments as described below. This second measure-
ment method is not generally as accurate as the first, but
it supports legacy power blocks or may prove necessary if
interrogated at initial power up and during a reset, so
modifying their values on the fly is not recommended.
RCONFIG pins on the same IC can be shared with a single
resistor divider if they require identical programming.
Resistors with a tolerance of 1% or better must be used
to assure proper operation. In the following tables, R
TOP
is connected between V
BOT
signals should not be routed near these pins.
and the RCONFIG pin, while
is connected between the pin and GND. Noisy clock
DD25
R
38821f
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Table 8. VOUTn_CFG Resistor Programming
Table 9. FREQ_CFG Resistor Programming
(kΩ) (kΩ)
R
TOP
(kΩ)
R
BOT
(kΩ)
V
(V)
OUT
SWITCHING
R
TOP
R
BOT
FREQUENCY (kHz)
0 or Open
10
Open
From EEPROM
0 or Open
20
Open
from EEPROM
23.2
15.8
20.5
17.4
17.8
15
5.0
3.3
17.8
15
1250
10
20
1000
16.2
16.2
20
2.5
20
12.7
11
900
1.8
20
750
1.5
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
11.3
9.09
7.32
5.76
4.32
3.57
1.96
0
600
20
1.35
1.25
1.2
500
20
12.7
11
450
20
400
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
11.3
9.09
7.32
5.76
4.32
3.57
1.96
0
1.15
1.1
350
300
250
1.05
0.9
External SYNC Only
0.75
0.65
0.6
Note that if SYNC pins are shared between LTC3882-1s,
only one SYNC output should be enabled. All other SYNC
outputs should be disabled. For example, if configuring
two LTC3882-1s as a 4-phase rail operating at a frequency
Output OFF*
from EEPROM)
(V
OUT
*OPERATION value and RUNn pin must both command the channel to
start from this configuration.
of 600kHz, both devices should have R
of 24.9kΩ and
TOP
R
of 11.3kΩ on the FREQ_CFG pin. In this case, select-
BOT
OutputvoltagecanbesetasshowninTable8.Forexample,
ing R of 24.9kΩ and R of 9.09kΩ for PHAS_CFG on
TOP
BOT
setting R
to 16.2kΩ and R
to 17.4kΩ is equivalent
TOP
BOT
thefirstIC(clockmaster)affords180°ofphaseseparation
to programming a VOUT_COMMAND value of 1.8V. Refer
to the Operations section for related parameters that are
also automatically set as a percentage of the programmed
and enables the SYNC output. The second device should
have R
of 20kΩ and R
of 12.7kΩ on PHAS_CFG,
TOP
BOT
to )disable its SYNC output and run its phases with 180°
of separation in quadrature with the first IC. Only mix
phase selections that have the same maximum duty cycle
specified. Refer to Tables 9 and 10.
V
if resistor configuration pins are used to determined
OUT
output voltage.
Table 10. PHAS_CFG Resistor Programming
R
(kΩ)
R
BOT
(kΩ)
θ
TO θ
θ
TO θ
1
MAXIMUM DUTY CYCLE
See MFR_PWM_CONFIG
87.5%
SYNC OUTPUT DISABLED
From EEPROM
Yes
TOP
SYNC
0
SYNC
0 or Open
20
Open
From EEPROM
From EEPROM
315°
15
135°
90°
45°
0°
20
12.7
11
270°
20
225°
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
11.3
9.09
7.32
5.76
4.32
3.57
1.96
0
180°
0°
180°
No
120°
60°
0°
300°
83.3%
Yes
240°
180°
0°
120°
0°
180°
No
0°
120°
38821f
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TheLTC3882-1addressisselectedbasedontheprogram-
ming of the two configuration pins ASEL0 and ASEL1
according to Table 11. ASEL0 programs the bottom four
bits of the device address for the LTC3882-1, and ASEL1
programs the three most-significant bits. Either portion of
theaddresscanalsoberetrievedfromtheMFR_ADDRESS
value in EEPROM. If both pins are left open, the full 7-bit
MFR_ADDRESS value stored in EEPROM is used to deter-
mine the device address. In the 4-phase example above,
it is recommended that one or both ASELn pins on both
partsbeprogrammedtocreatetwouniqueaddresses.The
LTC3882-1 also responds to 7-bit global addresses 0x5A
and 0x5B. MFR_ADDRESS and MFR_RAIL_ADDRESS
should not be set to either of these values.
supply attached to this pin if V and V
are shorted. If
DD33
CC
the internal 3.3V LDO is used, it can supply a peak current
of 85mA (including internal consumption), and the V
DD33
regulator output must be bypassed to GND with a low ESR
X5R or X7R ceramic capacitor with a value of 2.2μF. If an
external source supplies V , a local low ESR bypass
DD33
capacitor with a value between 0.01μF and 0.1μF should
be placed directly between the V and GND pins.
DD33
Donotdrawmorethan20mAfromtheinternal3.3Vregula-
tor for the host system, governed by IC power dissipation
asdiscussedinthenextsection.Thislimitincludescurrent
required for external pull up resistors for the LTC3882-1
that are terminated to V
.
DD33
V
powers a second internal 2.5V LDO whose output
DD33
is present on V
Table 11. ASELn Resistor Programming
. This 2.5V supply provides power for
DD25
ASEL1
ASEL0
muchoftheinternalprocessorlogicontheLTC3882-1.The
V output should be bypassed directly to GND with a
DD25
LTC3882-1 DEVICE
ADDRESS BITS[6:4]
LTC3882-1 DEVICE
ADDRESS BITS[3:0]
R
TOP
(kΩ)
R
(kΩ)
BOT
low ESR X5R or X7R ceramic capacitor with a value of 1μF
or greater. Do not draw any external system current from
this supply beyond that required for LTC3882-1 specific
configuration resistor dividers.
BINARY
HEX
BINARY
HEX
0 or Open
10
Open
from EEPROM
from EEPROM
1111
23.2
15.8
20.5
17.4
17.8
15
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
10
1110
16.2
16.2
20
1101
IC Junction Temperature
1100
The user must ensure that the maximum rated junction
temperatureisnotexceededunderalloperatingconditions.
1011
20
1010
The thermal resistance of the LTC3882-1 package (θ )
20
12.7
11
1001
JA
is 33°C/W, provided the exposed pad is in good thermal
contact with the PCB. The actual thermal resistance in the
applicationwilldependonforcedaircoolingandotherheat
sinking means, especially the amount of copper on the
PCB to which the LTC3882-1 is attached. The following
formula may be used to estimate the maximum average
20
1000
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
11.3
9.09
7.32
5.76
4.32
3.57
1.96
0
111
110
101
100
011
010
001
000
7
6
5
4
3
2
1
0
0111
0110
0101
0100
0011
power dissipation P (in watts) of the LTC3882-1 when
0010
D
V
CC
is supplied externally.
0001
0000
P = V (0.024 + f
• 1.6e-5 + I + I
)
D
CC
PWM
EXT
RC25
where:
Internal Regulator Outputs
The V pin provides supply current for much of the
I
= total external load drawn from V
, including
EXT
DD33
DD33
local pull-up resistors, in amps
internal LTC3882-1 analog circuitry at a nominal value of
I
= total current drawn from V by LTC3882-1
DD25
3.3V. The LTC3882-1 features an internal linear regulator
RC25
configuration resistor dividers, in amps
that can be used to supply 3.3V to V
from a higher
DD33
voltage V supply (up to 12V nominal). Use of this LDO is
CC
and the frequency f is given in kHz
PWM
PWM
optional. The LTC3882-1 will also accept an external 3.3V
38821f
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Configuring Open-Drain Pins
If an external source supplies V
directly, the following
DD33
formula may be used to estimate the maximum average
power dissipation P (in watts) of the LTC3882-1
The LTC3882-1 has the following open-drain pins:
D
3.3V Pins
P = V
D
(0.024 + f
• 1.6e-5 + I
)
DD33
PWM
RC25
1. PGOODn
The maximum junction temperature of the LTC3882-1 in
°C may then be found from the following equation
2. FAULTn
2. SYNC
T = T + 33 • P
D
J
A
3. SHARE_CLK
with ambient temperature T expressed in °C
A
5V-Capable Pins
Derating EEPROM Retention at Temperature
(These pins operate correctly when pulled to 3.3V.)
EEPROMreadoperationsbetween85°Cand125°Cwillnot
affect data storage. But retention will be degraded if the
EEPROM is written above 85°C or stored above 125°C. If
an occasional fault log is generated above 85°C, the slight
reduction in data retention in the EEPROM fault log area
will not affect the use of the function or other EEPROM
storage. See the Operation section for other high tem-
perature EEPROM functional details. Degradation in data
can be approximated by calculating the dimensionless
acceleration factor using the following equation.
1. RUNn
2. ALERT
3. SCL
4. SDA
All of the above pins have on-chip pull-down transistors
that can sink 3mA at 0.4V. The low-state threshold on
these pins is 1.4V, so ample noise margin exists with 3mA
of current. For 3.3V pins, 3mA of current is produced by
a 1.1k pull-up resistor. Unless there are transient speed
issues associated with the RC time constant of the net, a
10k resistor or larger is generally recommended.
⎡
⎢
⎤
⎥
⎛
⎞
Ea
k
1
1
⎛
⎞
•
−
⎜
⎟
⎠
⎜
⎟
AF = e⎣⎢⎝
T
+273
T
+273
⎝
⎠
⎥
⎦
USE
STRESS
Where:
AF = acceleration factor
The pull-up resistor for PGOOD should be terminated to
the LTC3882-1 V
pin or a separate bias supply under
DD33
3.6VthatisupbeforetheLTC3882-1isenabled.Otherwise,
power-not-good may be falsely indicated after the PWM
outputs are running.
Ea = activation energy = 1.4eV
–5
k = 8.617 • 10 eV/°K
The SYNC pin has an on-chip pull-down transistor with
the output held low for nominally 250ns when driven by
the LTC3882-1. If the internal oscillator is set for 500kHz
and the load is 100pF with a 1/3 rise time required, the
resistor calculation is as follows:
T
T
= is the specified junction temperature
USE
= actual junction temperature in °C
STRESS
Asanexample,ifthedeviceisstoredat130°Cfor10hours,
= 130°C, and
T
STRESS
2ꢀs–250ns
3•100pF
⎡
⎢
⎤
⎥
⎛
⎜
1.4
⎞
1
1
⎛
⎞
RPULLUP
=
= 5.83k
•
−
⎜
⎝
⎟
⎠
⎟
–5
⎠
AF = e⎣⎝
⎦ =1.66
398 403
8.617•10
The closest 1% resistor is 5.76k.
indicating the effect is the same as operating the device at
125°C for 10 • 1.66 = 16.6 hours, resulting in a retention
derating of 6.6 hours.
If timing errors are occurring or if the SYNC amplitude
is not as large as required, monitor the waveform and
determine if the RC time constant is too long for the
38821f
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For more information www.linear.com/LTC3882-1
LTC3882-1
applicaTions inForMaTion
application. If possible reduce the parasitic capacitance.
Otherwisereducethepull-upresistorsufficientlytoassure
proper operation.
Some computationally intensive commands (e.g., timing
parameters, temperatures, voltages and currents) have
internal processor execution times that may be long
relative to PMBus timing. If the part is busy processing
a command, and a new command(s) arrives, execution
may be delayed or processed in a different order than
received. The part indicates when internal calculations
are in process with bit 5 of MFR_COMMON (LTC3882-1
Calculations Not Pending). When the internal proces-
sor is busy calculating, bit 5 is cleared. When this bit is
set, the part is ready for another command. An example
polling loop is provided in Figure 46, which ensures that
commands are processed in order while simplifying error
handling routines. MFR_COMMON always returns valid
data at PMBus speeds between 10kHz and 400kHz.
The SHARE_CLK output has a nominal period of 10μs
and is pulled low for about 1μs. If the system load on this
shared line is 100pF, the resistor calculation for this line
with a 1/3 rise time is:
9ꢀs
3•100pF
RPULLUP
=
= 30k
The closest 1% resistor is 30.1k.
For high speed signals such as SDA, SCL and SYNC, a
lowervalueresistormayberequired.TheRCtimeconstant
should be set to 1/3 to 1/5 the required rise time to avoid
timingissues.Fora100pFloadanda400kHzPMBuscom-
munication rate, the resistor pull-up on the SDA and SCL
pins with the time constant set to 1/3 the rise time equals
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on part configuration it may either
NACK the command or return all ones (0xFF) for reads. It
may also generate a BUSY fault and ALERT notification,
or stretch the SCL clock low. For more information refer
to PMBus Specification V1.2, Part II, Section 10.8.7 and
SMBusV2.0section4.3.3.Clockstretchingcanbeenabled
by asserting bit 1 of MFR_CONFIG_ALL_LTC3882-1.
Clock stretching will only occur if enabled and the bus
communication speed exceeds 100kHz.
tRISE
3•100pF
RPULLUP
=
=1k
The closest 1% resistor value is 1k.
Be careful to minimize parasitic capacitance on the SDA
and SCL lines to avoid communication problems. To
estimate the loading capacitance, monitor the signal in
question and measure how long it takes for the desired
signal to reach approximately 63% of the output value.
This is one time constant.
PMBus protocols for busy devices are well accepted
standards but can make writing system level software
somewhat complex. The part provides three handshaking
status bits which reduce this complexity while enabling
robust system level communication. The three hand
PMBus Communication and Command Processing
The LTC3882-1 has a one deep buffer to hold the last data
written for each supported command prior to processing,
as shown in Figure 45. Two distinct parallel sections of
theLTC3882-1managecommandbufferingandcommand
processingtoensurethelastdatawrittentoanycommand
is never lost. When the part receives a new command
from the bus, command data buffering copies the data
into the write command data buffer and indicates to the
internal processor that data for that command should be
handled. The internal processor runs in parallel and per-
forms the sometimes slower task of fetching, converting
(to internal format) and executing commands so marked
for processing.
CMD
WRITE COMMAND
DATA BUFFER
PMBus
WRITE
DECODER
INTERNAL
PAGE
0x00
PROCESSOR
•
•
•
CMDS
FETCH,
CONVERT
DATA
AND
EXECUTE
DATA
MUX
VOUT_COMMAND 0x21
•
•
•
0xFD
MFR_RESET
x1
S
R
CALCULATIONS
PENDING
38821 F45
Figure 45. Write Command Data Processing
38821f
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LTC3882-1
applicaTions inForMaTion
shaking status bits are in the MFR_COMMON register.
When the part is busy executing an internal operation, it
will clear bit 6 of MFR_COMMON (LTC3882-1 Not BUSY).
When internal calculations are in process, the part will
clearbit5ofMFR_COMMON(LTC3882-1CalculationsNot
Pending). When the part is busy specifically because it is
ter that supports that function. Clock stretching does not
allow the LTC3882-1 to communicate reliably on busses
operating above 400kHz. Operating the LTC3882-1 with
PMBus SCL rates above 400kHz is not recommended.
System software that detects and properly recovers from
the standard PMBus NACK responses or BUSY faults
described in PMBus Specification V1.2, Part II, Section
10.8.7 is required to communicate above 100kHz without
clock stretching.
// wait until bits 6, 5, and 4 of MFR_COMMON are all set
do
{
mfrCommonValue = PMBUS_READ_BYTE(0xEF);
partReady = (mfrCommonValue & 0x68) == 0x68;
}while(!partReady)
Refer to Application Note 135 for techniques that may
also apply to implement a robust PMBus interface to the
LTC3882-1.
// now the part is ready to receive the next command
PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_COMMAND to 2V
Status and Fault Log Management
Figure 46. Example of a Polling Loop to Write VOUT_COMMAND
Due to internal operation, very infrequently the LS byte of
STATUS_WORD may be inconsistent with the state of bits
in the MS byte. This condition is quite transient and can
normallyberesolvedbysimplyre-readingSTATUS_WORD.
transitioning V
(margining, off/on, moving to a new
OUT
VOUT_COMMAND, etc.) it will clear bit 4 of MFR_COM-
MON (LTC3882-1 Output Not In Transition). These three
status bits can be polled with a PMBus read byte of the
MFR_COMMON register until all three bits are set. A com-
mand immediately following all these status bits being set
will be accepted without a NACK, BUSY fault or ALERT
notification. The part can NACK commands for other
reasons, however, as required by the PMBus specifica-
tion (e.g., an invalid command or data). An example of a
robustcommandwritealgorithmfortheVOUT_COMMAND
register is provided in Figure 46.
If power is lost during an internal store of a fault log to
EEPROM, a partial write of the log can result. In this situ-
ation, the LTC3882-1 will not indicate that a fault log is
present the next time adequate supply voltage is applied
(bit 3 of STATUS_MFR_SPECIFIC). The existence of a
partial fault log can be detected by examining the header
of the log (MFR_FAULT_LOG). If the first two words of
the Fault Log Preface contain valid data as specified by
Table2,andSTATUS_MFR_SPECIFICdoesnotindicatethe
presence of a complete fault log, then a partial log existed
in EEPROM at boot and has been retrieved to RAM. The
only way to then determine how much of the log is actually
validisby subjective evaluationofthe contents of each log
event record. MFR_CLEAR_FAULT_LOG will permanently
erase a partial fault log, allowing a subsequent log to be
written. It is a good practice to always check for a partial
fault log at power-up if fault logging is enabled (bit 7 of
MFR_CONFIG_ALL_LTC3882-1).
It is recommended that all command writes be preceded
with such a polling loop to avoid the extra complexity of
dealing with busy behavior or unwanted ALERT notifica-
tions. A simple way to achieve this is to embed the polling
in subroutines to write command bytes and words. This
polling mechanism will allow system software to remain
clean and simple while robustly communicating with the
part. For a detailed discussion of these topics and other
special cases please refer to the application note section
located at www.linear.com/designtools/app_notes.
LTpowerPlay – An Interactive Digital Power GUI
When communicating using bus speeds at or below
100kHz, the polling mechanism previously shown pro-
vides a simple solution that ensures robust communica-
tion without clock stretching. At bus speeds in excess
of 100kHz, it is strongly recommended that the part be
enabled to use clock stretching, requiring a PMBus mas-
LTpowerPlay is a powerful Windows-based development
environment that supports Linear Technology Power Sys-
tem Management ICs, including the LTC3882-1. LTpower-
Play can be used to evaluate LTC products by connecting
to a Linear Technology demo circuit or user application.
38821f
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For more information www.linear.com/LTC3882-1
LTC3882-1
applicaTions inForMaTion
LTpowerPlay can also be used offline (no hardware pres-
ent) to build multiple IC configuration files that can be
saved and later reloaded. LTpowerPlay uses the DC1613
If the system supply is restored while power is still applied
by the DC1613 or DC2086, the LTC3882-1 can often be
ready to initiate output soft-start before sufficient supply
bias for the power stage has been established. Create
additional LTC3882-1 delay with TON_DELAY or use a
common system RUN line to control both the LTC3882-1
and its related power stages based on acceptable operat-
2
USB-to-I C/SMBus/PMBus controller to communicate
with a system for evaluation, development or debug. The
software also features automatic update to remain up-
to-date with the latest device drivers and documentation
available from Linear Technology. A great deal of context
sensitive help is available within LTpowerPlay, along with
severaltutorials.Completeinformationisavailableathttp://
www.linear.com/ltpowerplay.
2
ing parameters, as shown in Figure 55. The DC1613 I C
connections are opto-isolated from the host PC USB. The
DC1613 3.3V current limit is only 100mA, so it should
only be used to power one or two LTC3882-1s in-system.
Because of this limited current sourcing capability, only
the LTC3882-1s, their associated pull-up resistors and the
Interfacing to the DC1613
2
2
I C pull-up resistors should be powered from the isolated
The LTC DC1613 USB-to-I C/SMBus/PMBus controller
3.3V supply provided by the DC1613. Using the DC2086
will enable in-system programming of several tens of
LTC3882-1deviceswithoutnormalsystempowerapplied.
can be interfaced to the LTC3882-1 on any board for
programming, telemetryandsystemdebug. Thisincludes
the DC1936 from Linear Technology, or any customer
target system. The controller, when used in conjunction
with LTpowerPlay, provides a powerful way to debug an
entire power system. Faults are quickly diagnosed using
telemetry, fault status registers and the fault log. The final
configuration can be quickly developed and stored to the
LTC3882-1EEPROMand/orLTpowerPlayconfigurationfile.
2
Any other device sharing the I C bus with the LTC3882-1
should not have body diodes between their SDA/SCL pins
andtheirrespectivelogicsupply,becausethiswillinterfere
with bus communication in the absence of system power.
HoldtheRUNpinslowexternallytoavoidprovidingpower
to the load until the part is fully configured.
The DC1613 can communicate with, program and even
power one or more LTC3882-1s, regardless of whether
system supplies are up. The DC2086 Powered Program-
ming Adapter can be used to extend the power sourcing
capability of the DC1613. Figure 47 illustrates an applica-
tion schematic for in-system programming of multiple
Design Example
As a design example, consider a 132W 2-phase applica-
tion such as the one shown in Figure 53, where V = 36V,
IN
V
= 3.3V, and I
= 40A. A fully discrete power stage
OUT
OUT
designisemployedtoallowbetteroptimizationgiventhese
demanding requirements. Assume that a secondary 5V
supply will be available in the system for the LTC3882-1
LTC3882-1s normally powered from a V system supply
CC
(5V to 12V). If V is applied, the DC1613 will not supply
CC
V
supply. The necessary local bypassing is then pro-
CC
theLTC3882-1sontheboard.IftheDC2086isused,PFETs
vided for the V
(2.2ꢀF) and V
(1ꢀF) LDO outputs.
DD25
DD33
with lower R , such as the SiA907EDJT, should be
DS(ON)
These LDO outputs should not be shared with other ICs
that might have outputs of the same name, because they
have independent, internal control loops. When V
is used as the LTC3882-1 supply input, it may be shared
with other ICs operating from that 3.3V supply. Local HF
bypassing of at least 0.1ꢀF is still required on V
this case.
used in place of the TP0101K devices. Figure 48 shows an
example when the system normally provides 3.3V directly
to the LTC3882-1(s).
DD33
If system supplies are not up in either of these circuits, the
in
DD33
DC1613 will power the LTC3882-1 V
supply, allowing
DD33
in-circuit configuration or manufacturing customization.
These circuits also facilitate remote diagnostics, control
and reprogramming of the LTC3882-1 while the host
system is fully operational, permitting very flexible in-
system debugging.
First, the regulated output is established by programming
the VOUT_COMMAND stored in EEPROM to 3.3V.
38821f
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For more information www.linear.com/LTC3882-1
LTC3882-1
applicaTions inForMaTion
SYSTEM
V
CC
TP0101K
LT6703-2
–IN
V
S
10k
V
V
CC
102k
10k
TP0101K
V
DD33
DD25
–
2.2µF
1µF
OUT
LTC3882-1
2N2002
10k
10k
SDA
SCL
+
10k
GND
400mV
REFERENCE
GND
LTC
CONTROLLER
HEADER
V
V
CC
DD33
4.7µF
V
DD25
2.2µF
1µF
ISOLATED 5V
SDA
LTC3882-1
SDA
SCL
SCL
GND
38821 F47
TO LTC DC1613
2
USB TO I C/SMBus/PMBus
CONTROLLER
Figure 47. DC1613 Connection (VCC Supply)
38821f
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LTC3882-1
applicaTions inForMaTion
ENBA
GND
STAT
ENBB
LTC4413
V
V
CC
INB
INA
OUTB
SYSTEM
3.3V
V
DD33
DD25
1µF
0.1µF
LTC3882-1
10k
10k
CONTROL CIRCUIT
SDA
SCL
OUTA
GND
LTC
CONTROLLER
HEADER
V
V
CC
DD33
ISOLATED 3.3V
V
DD25
SDA
SCL
0.1µF
1µF
LTC3882-1
SDA
SCL
GND
TO LTC DC1613
38821 F48
2
USB TO I C/SMBus/PMBus
CONTROLLER
Figure 48. DC1613 Connections (VDD33 Supply)
38821f
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LTC3882-1
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The frequency and phase are also set by EEPROM values.
Assume that solution footprint or vertical clearance is an
issue, so operating frequency will need to be increased
in an effort to minimize inductor value (size). This choice
could also result from the need to have above average
transient performance, although efficiency may be re-
duced slightly. FREQUENCY_SWITCH is set to 1.0MHz.
As a 2-phase system, MFR_PWM_CONFIG_LTC3882-1
is programmed to 0x14 to put Channel 0 phase at 0° and
Channel 1 phase at 180°. This produces the lowest input
ripple possible with this configuration and allows this
output to synchronize with other rails via SHARE_CLK.
A loop crossover frequency of 100kHz provides good
transient performance while still being well below the
switching frequency of the converter. The values of R29,
R30 and C25 to C27 were determined to produce a nomi-
nal system phase margin of about 65° at this bandwidth.
For the DCR sense filter network, R = 3.09k and C = 220nF
arechosentomatchtheL/DCRtimeconstantoftheinduc-
tor. PolyPhase connections (I , et al) are shown in the
AVG
schematic to ensure good output current sharing between
the two power stages.
External temperature sense will employ an accurate ꢁV
BE
method, and Q1 and Q2 serve to sense the temperature of
L1 and L2, respectively. These components will be located
immediately adjacent to their chokes and the 10nF filter
capacitors placed with the BJTs.
The design will plan on a nominal output ripple of 70% of
I
tominimizethemagneticsvolume,andtheinductance
OUT
value is chosen based on this assumption. Each channel
supplies an average 20A to the output at full load, result-
Resistor configuration is used on the ASELn pins to pro-
gram PMBus address (MFR_ADDRESS) to 0x4C. Each
LTC3882-1 must be configured for a unique address.
Using both ASELn pins to accomplish this programming
is recommended for simpliest in-system programming.
Check the selected address to avoid collision with global
addresses other any other specific devices. Identical
MFR_RAIL_ADDRESS can be set in EEPROM for both
channels to allow single-command control of common
rail parameters such as IOUT_OC_FAULT_LIMIT. The
LTC3882-1 also responds to 7-bit global addresses 0x5A
and 0x5B. MFR_ADDRESS and MFR_RAIL_ADDRESS
should not be set to either of these values.
ing in a ripple of 14A . A 200nH inductor per phase
P-P
would create this peak-to-peak ripple at 1.0MHz. A Pulse
PA0513.22LT 210nH inductor with a DCR of 0.32mΩ
typical is selected. Setting IOUT_FAULT_LIMIT to 35A per
phase leaves plenty of headroom for transient conditions
while still adequately protecting against the rated inductor
saturation current of 45A at temperature.
For top and bottom power FETs, the 40V rated Infineon
BSC050N04LSG and BSC010N04LS are chosen, respec-
tively. These afford both low R
G
improved efficiency at full load, if desired.
and low gate charge
DS(ON)
Q . Two of each of these could be paralleled to achieve
The LTC4449 gate driver is chosen for its fast response
PMBus connection (three signals), as well as shared
RUN control and fault propagation (FAULT) are provided.
SYNC can be used to synchronize other PWMs to this
rail if required.
(13ns), suitable gate drive, V capability (38V) and the
IN
easewithwhichitcanbeinterfacedtotheLTC3882-1.Basic
three-statecontrol,CCMoperation,fastboostrefresh,low
V
range and digital output voltage servo are selected
OUT
Pull-upsareprovidedonallthesesharedopen-drainsignals
assuming a maximum 100pF line load and PMBus rate of
100kHz. These pins should not be left floating. Termina-
tion to 3.3V ensures the absolute maximum ratings for
the pins are not exceeded. All other operating parameters
such as soft start/stop and desired faults responses are
programmedviaPMBuscommandvaluesstoredininternal
LTC3882-1 EEPROM.
by programming MFR_PWM_MODE_LTC3882-1 to 0xC0
for both channels.
For input filtering, a 47μF SUNCON capacitor and four
22μF ceramic capacitors are selected to provide accept-
able AC impedance against the designed converter ripple
current. Four 470μF 9mΩ POSCAPs and two 100μF
ceramic capacitors are chosen for the output to maintain
supply regulation during severe transient conditions and
to minimize output voltage ripple.
38821f
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LTC3882-1
(by functional groups)
pMbuꢀ coMManD DeTails
ADDRESSING AND WRITE PROTECT
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
PAGE
0x00 Channel (page) presently selected for any
paged command.
R/W Byte
N
Reg
0x00
PAGE_PLUS_WRITE
PAGE_PLUS_READ
0x05 Write a command directly to a specified page. W Block
N
N
0x06 Read a command directly from a specified
page.
Block R/W
Process
l
WRITE_PROTECT
0x10 Protect the device against unintended PMBus R/W Byte
modifications.
N
Reg
0x00
l
l
MFR_ADDRESS
0xE6 Specify right-justified 7-bit device address.
R/W Byte
R/W Byte
N
Y
Reg
Reg
0x4F
0x80
MFR_RAIL_ADDRESS
0xFA Specify unique right-justified 7-bit address
for channels comprising a PolyPhase output.
Related commands: MFR_COMMON.
PAGE
The PAGE command provides the ability to configure, control and monitor both PWM channels through only one
physical address, either the MFR_ADDRESS or GLOBAL device address. Each PAGE contains the operating memory
for one PWM channel.
Pages 0x00 and 0x01 correspond to Channel 0 and Channel 1, respectively, in this device.
Setting PAGE to 0xFF applies any following paged commands to both outputs. With PAGE set to 0xFF the LTC3882-1
will respond to read commands as if PAGE were set to 0x00 (Channel 0 results).
This command has one data byte.
PAGE_PLUS_WRITE
The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command and then send
the data for the command, all in one communication packet. Commands allowed by the present write protection level
may be sent with PAGE_PLUS_WRITE.
The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send
a non-paged command, the Page Number byte is ignored.
This command uses Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a com-
mand that has two data bytes is shown in Figure 49.
1
7
1
1
8
1
8
1
8
1
8
1
SLAVE
ADDRESS
PAGE_PLUS
COMMAND CODE
BLOCK COUNT
(= 4)
PAGE
NUMBER
COMMAND
CODE
S
W
A
A
A
A
A
…
8
1
8
1
8
1
1
LOWER DATA
BYTE
UPPER DATA
BYTE
A
A
PEC BYTE
A
P
38821 F49
Figure 49. Example of PAGE_PLUS_WRITE
38821f
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LTC3882-1
(Addressing and Write Protect)
pMbuꢀ coMManD DeTails
PAGE_PLUS_READ
The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command and then read
the data returned by the command, all in one communication packet .
The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access
data from a non-paged command, the Page Number byte is ignored.
This command uses Block Write – Block Read Process Call protocol. An example of the PAGE_PLUS_READ command
with PEC is shown in Figure 50.
NOTE: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another
PAGE_PLUS command. If this is attempted, the LTC3882-1 will NACK the entire PAGE_PLUS packet and issue a CML
fault for Invalid/Unsupported Data.
1
7
1
1
8
1
8
1
8
1
8
1
SLAVE
ADDRESS
PAGE_PLUS
COMMAND CODE
BLOCK COUNT
(= 2)
PAGE
NUMBER
COMMAND
CODE
S
W
A
A
A
A
A
…
1
7
1
1
8
1
8
1
8
1
8
1
1
SLAVE
ADDRESS
BLOCK COUNT
LOWER DATA
BYTE
UPPER DATA
BYTE
Sr
R
A
A
A
A
PEC BYTE
NA
P
(= 2)
38821 F50
Figure 50. Example of PAGE_PLUS_READ
WRITE_PROTECT
The WRITE_PROTECT command is used to control PMBus write access to the LTC3882-1.
Supported Values:
VALUE
0x80
MEANING
Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ALL and MFR_EE_UNLOCK commands.
0x40
Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ALL, MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS and CLEAR_FAULTS
commands. Individual faults can also be cleared by writing a 1 to the respective status bit.
0x20
0x00
Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ ALL, MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS, CLEAR_FAULTS,
ON_OFF_CONFIG and VOUT_COMMAND commands. Individual faults can be cleared by writing a 1 to the respective status bit.
Enables writes to all commands.
This command has one data byte.
38821f
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LTC3882-1
(Addressing and Write Protect)
pMbuꢀ coMManD DeTails
MFR_ADDRESS
The MFR_ADDRESS command sets the seven bits of the PMBus device address for this unit (right justified).
Setting this command to a value of 0x80 disables device-level addressing. The GLOBAL device addresses 0x5A and
0x5B cannot be disabled. The LTC3882-1 always responds at these addresses. Even if bit 6 of MFR_CONFIG_ALL_
LTC3882-1 is set to ignore the device resistor configuration pins, any valid address, or portion of an address, specified
with external resistors on ASEL0 or ASEL1 is applied. If both of these pins are open, the device address is determined
strictly by the MFR_ADDRESS value stored in EEPROM. Refer to the Operation section on Resistor Configuration Pins
for additional details.
This command has one data byte.
MFR_RAIL_ADDRESS
The MFR_RAIL_ADDRESS command sets a direct 7-bit PMBus address (right justified) for the active channel(s) as
determined by the PAGE command. This address should be common to all channels attached to a single power supply
rail. Setting this command to a value of 0x80 disables rail device addressing for the selected channel. Only command
writes should be made to the rail address. If a read is performed from this address, a CML fault may result.
This command has one data byte.
GENERAL DEVICE CONFIGURATION
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
PMBUS_REVISION
0x98 Supported PMBus version.
R Byte
Y
N
N
Reg
Reg
Reg
0x22
V1.2
CAPABILITY
0x19 Summary of supported optional PMBus
features.
R Byte
0xB0
l
MFR_CONFIG_ALL_LTC3882-1
0xD1 LTC3882-1 device-level configuration.
R/W Byte
0x01
PMBUS_REVISION
The PMBUS_REVISION command returns the revision of the PMBus Specification that the device supports. The
LTC3882-1 is compliant with PMBus Version 1.2, both Part I and Part II.
This read-only command has one data byte.
CAPABILITY
The CAPABILITY command reports some key LTC3882-1 features to the PMBus host device.
The LTC3882-1 supports packet error checking, 400kHz bus speeds and has an ALERT output.
This read-only command has one data byte.
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LTC3882-1
(General Device Configuration)
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MFR_CONFIG_ALL_LTC3882-1
The MFR_CONFIG_ALL_LTC3882-1 command provides device-level configuration common to multiple LTC PMBus
products.
Bit Definitions:
BIT
7
MEANING
Enable fault logging.
6
Ignore resistor configuration pins. Does not apply to ASEL0 or ASEL1.
Disable CML fault for Quick Command message.
Disable SYNC output.
5
4
3
Enable 255ms PMBus timeout.
2
Require valid PEC for PMBus write.
Enable PMBus clock stretching.
1
0
Execute CLEAR_FAULTS on rising edge of either RUN pin.
If a legal command is received with an invalid PEC, the LTC3882-1 will not execute the command, regardless of the state
of bit 2. If clock stretching is enabled, the LTC3882-1 only uses it as required, generally above SCL rates of 100kHz.
This command has one data byte.
ON, OFF AND MARGIN CONTROL
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
l
ON_OFF_CONFIG
0x02 RUN pin and PMBus on/off command
configuration.
R/W Byte
Y
Reg
Reg
0x1E
l
OPERATION
MFR_RESET
0x01 On, off and margin control.
R/W Byte
Send Byte
Y
N
0x80
0xFD Force full reset without removing power.
ON_OFF_CONFIG
The ON_OFF_CONFIG command specifies the combination of RUNn pin input state and PMBus commands needed to
turn the PWM channel on and off.
Supported Values:
VALUE
0x1F
MEANING
OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off.
OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when commanded off.
RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored.
RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored.
0x1E
0x17
0x16
Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored.
This command has one data byte.
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LTC3882-1
(On, Off and Margin Control)
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OPERATION
The OPERATION command is used to turn the PWM channel on and off in conjunction with RUN pin hardware control.
Thiscommandmayalsobeusedtomovetheoutputvoltagetomarginlevels. V changescommandedbyOPERATION
OUT
margin commands occur at the programmed VOUT_TRANSITION_RATE. The unit stays in the commanded operating
state until an OPERATION command or RUN pin voltage instructs the device to change to another state.
Execution of margin commands is delayed until any on-going TON_RISE or TOFF_FALL output sequencing is com-
pleted. Margin values are affected by AVP function, if enabled. Margin operations that ignore faults are not supported
by the LTC3882-1.
Supported Values:
VALUE
0xA8
MEANING
Margin high.
Margin low.
0x98
0x80
On (V
back to nominal even if bit 3 of ON_OFF_CONFIG is not set).
OUT
0x40*
0x00*
Soft off (with sequencing).
Immediate off (no sequencing).
*Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set.
Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored.
This command has one data byte.
MFR_RESET
This command provides a means to reset the LTC3882-1 from the serial bus. This forces the LTC3882-1 to turn off
both PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start
of both PWM channels, if enabled.
This write-only command has no data bytes.
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LTC3882-1
(PWM Configuration)
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PWM CONFIGURATION
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
l
FREQUENCY_SWITCH
0x33 PWM frequency control.
R/W Word
N
L11
Reg
kHz
500kHz
0xFBE8
l
MFR_PWM_CONFIG_LTC3882-1
0xF5 LTC3882-1 PWM configuration common to
both channels.
R/W Byte
N
0x14
l
l
MFR_CHAN_CONFIG_LTC3882-1
MFR_PWM_MODE_LTC3882-1
0xD0 LTC3882-1 channel-specific configuration.
R/W Byte
R/W Byte
Y
Y
Reg
Reg
0x1D
0xC8
0xD4 LTC3882-1 channel-specific PWM mode
control.
Related commands MFR_TEMP_1_GAIN_ADJUST, MFR_TEMP_1_OFFSET.
FREQUENCY_SWITCH
The FREQUENCY_SWITCH command sets the switching frequency of both LTC3882-1 PWM channels in kilohertz. At
most only one IC sharing SYNC should be programmed as clock master. See bit 4 in MFR_CONFIG_ALL_LTC3882-1.
FREQUENCY_SWITCH value will determine the free-running frequency of PWM operation if an expected external clock
source is not present or the bussed SYNC line becomes stuck due an external fault or conflict. Both PWM channels
must be turned off by the RUNn pins, OPERATION command, or their combination, to process this command. If this
command is sent while either PWM controller is operating, the LTC3882-1 will NACK the command byte, ignore the
command and its data, and assert a BUSY fault. A PLL Unlocked status may be reported after changing the value of
this command until the new frequency is established.
Supported Frequencies:
VALUE
0x0A71
0x03E8
0x0384
0x02EE
0x0258
0xFBE8
0xFB84
0xFB20
0xFABC
0XFA58
0xF3E8
0x0000
PWM FREQUENCY (TYPICAL)
1.25MHz
1MHz
900kHz
750kHz
600kHz
500kHz
450kHz
400kHz
350kHz
300kHz
250kHz
External SYNC Only
This command has two data bytes in Linear_5s_11s format.
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LTC3882-1
(PWM Configuration)
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MFR_PWM_CONFIG_LTC3882-1
The MFR_PWM_CONFIG_LTC3882-1 command controls PWM-related clocking for the LTC3882-1. Both PWM chan-
nels must be turned off by the RUNn pins, OPERATION command, or their combination, to process this command. If
this command is sent while either PWM controller is operating, the LTC3882-1 will NACK the command byte, ignore
the command and its data, and assert a BUSY fault.
Supported Values:
BIT
7
MEANING
(Reserved, must write as 0).
6
(Reserved, must write as 0).
5
(Reserved).
4
SHARE_CLK configuration:
0: SHARE_CLK continuously enabled once VINSNS ≥ VIN_ON after initialization.
1: SHARE_CLK always forced low if VINSNS ≤ VIN_OFF, then held low until VINSNS ≥ VIN_ON.
(Reserved).
3
2:0
Phase
Maximum Duty
Cycle
Value
Channel 0
135°
90°
Channel 1
315°
111b
110b
101b
100b
011b
010b
001b
000b
87.5%
270°
45°
225°
0°
180°
120°
60°
300°
83.3%
240°
0°
180°
0°
120°
Phase is expressed from the falling edge of SYNC to the falling edge of PWM.
This command has one data byte.
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LTC3882-1
(PWM Configuration)
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MFR_CHAN_CONFIG_LTC3882-1
The MFR_CHAN_CONFIG_LTC3882-1 command provides per-channel configuration common to multiple LTC PMBus
products.
Bit Definitions:
BIT
7:5
4
MEANING
(Reserved).
RUN pin control:
0: When the channel is commanded off, the associated RUN pin is pulsed low for TOFF_DELAY + TOFF_FALL + 136ms
(or MFR_RESTART_DELAY, if longer) regardless of the state of bit 3.
1: RUN pin is not pulsed low if channel is commanded off.
Short cycle control:
3
2
0: No special control. Device attempts to follow on/off commands exactly as issued.
1: Output is immediately disabled if commanded back on while waiting for TOFF_DELAY or TOFF_FALL to expire. A minimum off time
of 120ms is then enforced before the channel is turned back on. Additional delay will apply if bit 4 is clear.
SHARE_CLK output control:
0: No special control.
1: Output disabled if SHARE_CLK is held low.
(Reserved, must write as 0).
1
0
MFR_RETRY_DELAY control:
0: Output decay to 12.5% of programmed value required for retry after ANY action that turns off the rail.
1: Output decay not required for retry.
This command has one data byte.
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LTC3882-1
(PWM Configuration)
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MFR_PWM_MODE_LTC3882-1
TheMFR_PWM_MODE_LTC3882-1commandsetsimportantPWMcontrolsforeachchannel.Theaddressedchannel(s)
must be turned off by its RUN pin, OPERATION command, or their combination, when this command is issued. Oth-
erwise the LTC3882-1 will NACK the command byte, ignore the command and its data, and assert a BUSY fault.
When bit 5 is cleared, the LTC3882-1 computes temperature in °C from ꢁV measured by the ADC at the TSNSn pin as
BE
T = (G • ΔV • q/(K • ln(16))) – 273.15 + O
BE
When bit 5 is set, the LTC3882-1 computes temperature in °C from TSNSn voltage measured by the ADC as
T = (G • (1.35 – V
+ O)/4.3e-3) + 25
TSNSn
For both equations,
–14
G = MFR_TEMP_1_GAIN • 2 , and
O = MFR_TEMP_1_OFFSET
Supported Values:
BIT
MEANING
7
Output voltage range select:
0: Maximum V
1: Maximum V
= 5.25V.
= 2.65V.
OUT
OUT
6*
5
Enable V
servo.
OUT
External temperature sense:
0: ꢁV measurement.
BE
1: Direct voltage measurement.
4:3
BOOST refresh width:
11b: 250ns
10b: 125ns
01b: 50ns
00b: 25ns
2
1
(Reserved).
PWM control protocol:
0: 3-State PWM output.
1: 3-State PWM output with no DCM (including soft-start) or hardware ROC response (including OV).
0
PWM mode:
0: Forced continuous inductor current.
1: Discontinuous inductor current.
*This bit is ignored (servo disabled) if MFR_VOUT_AVP for this channel is programmed to a value greater than 0.0%.
This command has one data byte.
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LTC3882-1
(Input Voltage and Limits)
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INPUT VOLTAGE AND LIMITS
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
l
VIN_ON
0x35 Minimum input voltage to begin power
conversion.
R/W Word
N
N
N
N
L11
L11
L11
L11
V
V
V
V
6.5V
0xCB40
l
l
l
VIN_OFF
0x36 Decreasing input voltage at which power
conversion stops.
R/W Word
R/W Word
R/W Word
6.0V
0xCB00
VIN_OV_FAULT_LIMIT
VIN_UV_WARN_LIMIT
0x55
V
IN
overvoltage fault limit.
15.5V
0xD3E0
0x58
V
IN
undervoltage warning limit.
6.3V
0xCB26
Related commands: STATUS_INPUT, SMBALERT_MASK, READ_VIN, VIN_OV_FAULT_RESPONSE
VIN_ON
The VIN_ON command sets the input voltage, in volts, required to start power conversion.
This command has two data bytes in Linear_5s_11s format.
VIN_OFF
The VIN_OFF command sets the minimum input voltage, in volts, at which power conversion stops.
This command has two data bytes in Linear_5s_11s format.
VIN_OV_FAULT_LIMIT
The VIN_OV_FAULT_LIMIT command sets the value of the input voltage measured by the ADC, in volts, that causes
an input overvoltage fault.
This command has two data bytes in Linear_5s_11s format.
VIN_UV_WARN_LIMIT
The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC that causes an input under-
voltage warning. This warning is disabled until the input exceeds the input startup threshold value set by the VIN_ON
command and the unit has been enabled. If the VIN_UV_WARN_LIMIT is then exceeded, the device:
• Sets the INPUT Bit in the STATUS_WORD
• Sets the V Undervoltage Warning Bit in the STATUS_INPUT Command
IN
• Notifies the Host by Asserting ALERT, Unless Masked
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LTC3882-1
(Output Voltage and Limits)
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OUTPUT VOLTAGE AND LIMITS
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
–12
VOUT_MODE
0x20 Output voltage format and exponent.
0x21 Nominal V value.
R Byte
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Reg
L16
L16
L16
L11
L16
L16
L16
L16
L16
L16
2
0x14
l
l
l
l
l
l
l
l
l
l
VOUT_COMMAND
R/W Word
R Word
V
V
V
%
V
V
V
V
V
V
1.0V
0x1000
OUT
MFR_VOUT_MAX
0xA5 Maximum value of any V -related
5.6V
0x599A
OUT
command.
VOUT_MAX
0x24 Maximum V
that can be set by any
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
5.5V
0x5800
OUT
command, including margin.
MFR_VOUT_AVP
0xD3 Specify V load line.
0%
0x8000
OUT
VOUT_MARGIN_HIGH
VOUT_MARGIN_LOW
VOUT_OV_FAULT_LIMIT
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
VOUT_UV_FAULT_LIMIT
0x25
0x26
0x40
0x42
0x43
0x44
V
at high margin, must be greater than
1.05V
0x10CD
OUT
VOUT_COMMAND.
V
OUT
at low margin, must be less than
0.95V
0x0F33
VOUT_COMMAND.
V
OUT
V
OUT
V
OUT
V
OUT
overvoltage fault limit.
1.1V
0x119A
overvoltage warning limit.
undervoltage warning limit.
undervoltage fault limit.
1.075V
0x1133
0.925V
0x0ECD
0.9V
0x0E66
Related commands: OPERATION, STATUS_WORD, STATUS_VOUT, SMBALERT_MASK, READ_VOUT, MFR_VOUT_PEAK, READ_POUT, VOUT_OV_FAULT_
RESPONSE, VOUT_UV_FAULT_RESPONSE
VOUT_MODE
The VOUT_MODE command gives the format used by the LTC3882-1 for output voltage related commands. Only Linear
Mode is supported, with a mantissa expressed in microvolts. Sending the VOUT_MODE command to the LTC3882-1
using a write protocol will result in a CML fault.
This read-only command has one data byte.
VOUT_COMMAND
The VOUT_COMMAND is used to set the output voltage in volts (no load value if AVP is enabled). Execution of this
command is delayed until any on-going TON_RISE or TOFF_FALL output sequencing is completed, otherwise the
output voltage moves to a new value at VOUT_TRANSITION_RATE.
This command has two data bytes in Linear_16u format.
MFR_VOUT_MAX
The MFR_VOUT_MAX command returns the maximum value, in volts, allowed for any V -related command, in-
OUT
cluding VOUT_OV_FAULT_LIMIT. This value represents the maximum regulated voltage the selected channel could be
capable of producing.
This read-only command has two data bytes in Linear_16u format.
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LTC3882-1
(Output Voltage and Limits)
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VOUT_MAX
The VOUT_MAX command sets an upper limit, in volts, on the allowed value of any command that sets the output
voltage, including VOUT_MARGIN_HIGH. Setting VOUT_MAX to a value greater than MFR_VOUT_MAX will result in
a CML fault and VOUT_MAX will be set to the value of MFR_VOUT_MAX. A VOUT_MAX warning may also be gener-
ated if VOUT_MAX is set above 5.5V in output range 0 or above 2.75V in range 1. This command ensures that any
combination of commands attempting to set V
above VOUT_MAX will result in a warning with the output clamped
OUT
at VOUT_MAX. When a VOUT_MAX warning occurs, the device takes the following actions:
• Sets The Offending Command Value to the Voltage Specified by VOUT_MAX
• Sets the VOUT Bit in the STATUS_WORD
• Sets the VOUT_MAX Warning Bit in the STATUS_VOUT Command
• Notifies the Host by Asserting ALERT, Unless Masked
This command has two data bytes in Linear_16u format.
MFR_VOUT_AVP
The MFR_VOUT_AVP command sets the change in output voltage, in percent, for a full-scale change in output current.
MFR_VOUT_AVP can be used for active voltage positioning (AVP) requirements or passive current sharing schemes.
The LTC3882-1 interprets the IOUT_OC_WARN_LIMIT value as full-scale current for AVP. If MFR_VOUT_AVP is non-
zero, VOUT_COMMAND sets the maximum, no-load output voltage and servo mode for that channel is automatically
disabled. Setting MFR_VOUT_AVP to 0.0% automatically disables the AVP function. Refer to the Applications Informa-
tion section for additional details on range and resolution when using MFR_VOUT_AVP.
This command has two data bytes in Linear_5s_11s format.
VOUT_MARGIN_HIGH
The VOUT_MARGIN_HIGH command programs the output voltage, in volts, to be produced when Margin High is set
with the OPERATION command (no load value if AVP is enabled). The value must be greater than VOUT_ COMMAND.
This command has two data bytes in Linear_16u format.
VOUT_MARGIN_LOW
The VOUT_MARGIN_LOW command programs the output voltage, in volts, to be produced when Margin Low is set
by the OPERATION command (no load value if AVP is enabled). The value must be less than VOUT_COMMAND.
This command has two data bytes in Linear_16u format.
VOUT_OV_FAULT_LIMIT
TheVOUT_OV_FAULT_LIMITcommandsetsthevalueoftheoutputvoltagemeasuredbytheOVsupervisorattheV
SENSE
pins, in volts, which causes an output overvoltage fault. If VOUT_OV_FAULT_LIMIT is modified while the channel is on,
10ms should be allowed for the new value to take effect. Modifying V during that time can result an erroneous OV
OUT
fault. The LTC3882-1 sets MFR_COMMON bits[6:5] low while it establishes the new VOUT_OV_FAULT_LIMIT value.
This command has two data bytes in Linear_16u format.
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LTC3882-1
(Output Voltage and Limits)
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VOUT_OV_WARN_LIMIT
The VOUT_OV_WARN_LIMIT command sets the value, in volts, of the output voltage measured by the ADC at the
pins that causes an output overvoltage warning. If the VOUT_OV_WARN_LIMIT is exceeded, the device:
V
SENSE
• Sets the VOUT Bit in the STATUS_WORD
• Sets the V Overvoltage Warning Bit in the STATUS_VOUT Command
OUT
• Notifies the Host by Asserting ALERT, Unless Masked
This command has two data bytes in Linear_16u format.
VOUT_UV_WARN_LIMIT
The VOUT_UV_WARN_LIMIT command sets the value, in volts, of the output voltage measured by the ADC at the
V
SENSE
pins that causes an output undervoltage warning. If the VOUT_UV_WARN_LIMIT is exceeded, the device:
• Sets the VOUT Bit in the STATUS_WORD
• Sets the V Undervoltage Warning Bit in the STATUS_VOUT Command
OUT
• Notifies the Host by Asserting ALERT, Unless Masked
This command has two data bytes in Linear_16u format.
VOUT_UV_FAULT_LIMIT
The VOUT_UV_FAULT_LIMIT command sets the value of the output voltage measured by the UV supervisor at the
V
SENSE
pins, in volts, which causes an output undervoltage fault.
This command has two data bytes in Linear_16u format.
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LTC3882-1
(Output Current and Limits)
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OUTPUT CURRENT AND LIMITS
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
l
IOUT_CAL_GAIN
0x38 Ratio of I
voltage to sensed current.
R/W Word
R/W Word
R/W Word
R/W Word
Y
Y
Y
Y
L11
CF
mΩ
0.63mΩ
0xB285
SENSE
l
l
l
MFR_IOUT_CAL_GAIN_TC
IOUT_OC_FAULT_LIMIT
IOUT_OC_WARN_LIMIT
0xF6 Output current sense element temperature
coefficient.
ppm/°C
3900ppm/°C
0x0F3C
0x46 Output overcurrent fault limit.
L11
L11
A
A
29.75A
0xDBB8
0x4A Output overcurrent warning limit.
20.0A
0xDA80
Related commands: STATUS_IOUT, SMBALERT_MASK, READ_IOUT, MFR_IOUT_PEAK, READ_POUT, IOUT_OC_FAULT_RESPONSE, MFR_VOUT_AVP
IOUT_CAL_GAIN
The IOUT_CAL_GAIN command is used to set the resistance value of the output current sense element in milliohms.
This command has two data bytes in Linear_5s_11s format.
MFR_IOUT_CAL_GAIN_TC
The MFR_IOUT_CAL_GAIN_TC command sets the temperature coefficient of the output current sense element in
ppm/°C. Effective sense resistance, in milliohms, is computed by the LTC3882-1 as
R
SENSE
= IOUT_CAL_GAIN • (1 + 1E-6 • MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1 – 27))
This command has two data bytes representing a 2’s compliment integer.
IOUT_OC_FAULT_LIMIT
The IOUT_OC_FAULT_LIMIT command sets the value of the instantaneous peak output current, in amperes, which
will cause the OC supervisor to detect an output overcurrent fault. The LTC3882-1 uses the computed effective sense
resistance and the voltage across the I
inputs to determine the output current. The programmed limit voltage is
SENSE
rounded to the nearest 0.4mV in a range from 0.0mV to 80.0mV. Output overcurrent faults are ignored during TON_RISE
and TOFF_FALL output sequencing.
This command has two data bytes in Linear_5s_11s format.
IOUT_OC_WARN_LIMIT
TheIOUT_OC_WARN_LIMITcommandsetsthevalueoftheoutputcurrentmeasuredbytheADC,inamperes,thatcauses
anoutputovercurrentwarning.Toprovidemeaningfulresponses,thisvalueshouldbesetbelowIOUT_OC_FAULT_LIMIT
minus 1/2 of the maximum anticipated ripple current. If the IOUT_OC_WARN_LIMIT is exceeded, the device:
• Sets the IOUT Bit in the STATUS_WORD
• Sets the I
Overcurrent Warning Bit in the STATUS_IOUT Command
OUT
• Notifies the Host by Asserting ALERT, Unless Masked
Output overcurrent warnings are ignored during TON_RISE and TOFF_FALL output sequencing.
This command has two data bytes in Linear_5s_11s format.
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LTC3882-1
(Output Timing, Delays, and Ramping)
pMbuꢀ coMManD DeTails
OUTPUT TIMING, DELAYS, AND RAMPING
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
l
MFR_RESTART_DELAY
0xDC Minimum time RUN pin is held low by the
LTC3882-1.
R/W Word
Y
Y
Y
Y
Y
Y
Y
Y
L11
L11
L11
L11
L11
L11
L11
L11
ms
500ms
0xFBE8
l
l
l
l
l
l
l
TON_DELAY
0x60 Delay from RUN pin or OPERATION on
command to TON_RISE ramp start.
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
ms
0.0ms
0x8000
TON_RISE
0x61 Time for V
to rise from 0V to
ms
8.0ms
0xD200
OUT
VOUT_COMMAND after TON_DELAY.
TON_MAX_FAULT_LIMIT
VOUT_TRANSITION_RATE
TOFF_DELAY
0x62 Maximum time for V to rise above
ms
10.0ms
0xD280
OUT
VOUT_UV_FAULT_LIMIT after TON_DELAY.
0x27
V
slew rate for programmed output
V/ms
ms
0.25V/ms
0xAA00
OUT
changes.
0x64 Delay from RUN pin or OPERATION off
command to TOFF_FALL ramp start.
0.0ms
0x8000
TOFF_FALL
0x65 Time for V
to fall to 0V from
ms
8.0ms
0xD200
OUT
VOUT_COMMAND after TOFF_DELAY.
TOFF_MAX_WARN_LIMIT
0x66 Maximum time for V to decay below
ms
150ms
0xF258
OUT
12.5% of VOUT_COMMAND after TOFF_FALL
completes.
Related commands: MFR_RETRY_DELAY, STATUS_VOUT, SMBALERT_MASK, TON_MAX_FAULT_RESPONSE, MFR_CHAN_CONFIG_LTC3882-1,
MFR_PWM_MODE_LTC3882-1
These commands can be used to establish required on/off sequencing for any number of system power supply rails.
MFR_RESTART_DELAY
The MFR_RESTART DELAY command specifies the minimum PWM off time (RUN low) in milliseconds. The LTC3882-1
will actively hold its RUN pin low for this length of time if a falling RUN edge is detected. After this delay, a standard
start-up sequence can be initiated. A minimum of TOFF_DELAY + TOFF_FALL + 136ms is recommended for this com-
mand value. Valid value range is 136ms to 65.52 seconds. The LTC3882-1 uses a resolution of 16ms for this command
and will not produce delays outside of this range.
This command has two data bytes in Linear_5s_11s format.
TON_DELAY
The TON_DELAY command sets the delay, in milliseconds, between a start condition and the beginning of the output
voltage rise. Values from 0ms to 83 seconds are considered valid, and the LTC3882-1 will not produce delays outside
of this range.
This command has two data bytes in Linear_5s_11s format.
TON_RISE
The TON_RISE command sets the desired time, in milliseconds, from the point the output starts to rise until it enters
the regulation band. Values from 0 seconds to 1.3 seconds are considered valid, and the LTC3882-1 will not produce
rise times outside of this range. Values of TON_RISE less than 0.25ms or resulting slopes greater than 4V/ms will
result in an output step to the commanded voltage limited only by PWM analog loop response.
This command has two data bytes in Linear_5s_11s format.
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LTC3882-1
(Output Timing, Delays and Ramping)
pMbuꢀ coMManD DeTails
TON_MAX_FAULT_LIMIT
The TON_MAX_FAULT_LIMIT command sets the maximum time, in milliseconds, the unit is allowed from the beginning
of TON_RISE to power up the output without passing VOUT_UV_FAULT_LIMIT. A value of 0ms means there is no limit
and the unit can attempt to bring up the output voltage indefinitely. The maximum allowed TON_MAX is 8 seconds.
This command has two data bytes in Linear_5s_11s format.
VOUT_TRANSITION_RATE
The VOUT_TRANSITION_RATE command sets the rate at which the output voltage changes, in volts per millisecond
(or mV/ꢀs), in response to a VOUT_COMMAND or OPERATION (margin) command. This rate of change does not ap-
ply to operations that fully turn the PWM channel on or off. Values from 1mV/ms to 4V/ms are considered valid. The
LTC3882-1 will not produce V
transitions slower than 1mV/ms, and values exceeding 4V/ms cause the device to
OUT
transition the output as quickly as possible, limited only by PWM analog loop response.
This command has two data bytes in Linear_5s_11s format.
TOFF_DELAY
The TOFF_DELAY command sets the delay, in milliseconds, between a stop condition and the beginning of the output
voltage fall. Values from 0s to 16s are considered valid.
This command has two data bytes in Linear_5s_11s format.
TOFF_FALL
The TOFF_FALL command sets the time, in milliseconds, from the end of TOFF_DELAY until the output voltage is com-
manded fully to zero. The part attempts to linearly reduce the commanded output voltage to zero during TOFF_FALL.
At the end of this period, the PWM output is disabled.
The part will maintain its programmed PWM operating mode during TOFF_FALL. Using continuous conduction mode
will produce a well defined V
ramp off but may result in negative output current. The minimum supported fall time
OUT
is 0.25ms, or any value that results in a rate of fall exceeding 4V/ms. Programmed values less than this will result in a
commanded 0.25ms ramp, possibly limited by PWM analog loop response. Maximum fall time is 1.3 seconds.
In discontinuous conduction mode, the controller will not be able to draw current from the load and fall time will be
set by output capacitance and load current.
This command has two data bytes in Linear_5s_11s format.
TOFF_MAX_WARN_LIMIT
The TOFF_MAX_WARN_LIMIT command sets the time, in milliseconds, the unit is allotted to have the output off after
TOFF_FALL completes before a warning is issued. The output is considered off when V
VOUT_COMMAND value.
is less than 12.5% of the
OUT
A data value of 0ms means there is no limit and the unit can attempt to turn the output off indefinitely. There is also
no limit enforced if bit 0 of MFR_CHAN_CONFIG_LTC3882-1 is set.
This command has two data bytes in Linear_5s_11s format.
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LTC3882-1
(External Temperature and Limits)
TYPE
pMbuꢀ coMManD DeTails
EXTERNAL TEMPERATURE AND LIMITS
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
PAGED FORMAT UNITS NVM
l
MFR_TEMP_1_GAIN
0xF8 Set slope for external temperature
calculations.
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
Y
Y
Y
Y
Y
CF
1.0
0x4000
l
l
l
l
MFR_TEMP_1_OFFSET
OT_FAULT_LIMIT
OT_WARN_LIMIT
UT_FAULT_LIMIT
0xF9 Offset addend for external temperature
calculations.
L11
L11
L11
L11
°C or V
°C
0.0
0x8000
0x4F External overtemperature fault limit.
0x51 External overtemperature warning limit.
0x53 External undertemperature fault limit.
100.0°C
0xEB20
°C
85.0°C
0xEAA8
°C
–40.0°C
0xE580
Related commands: STATUS_TEMPERATURE, SMBALERT_MASK, MFR_TEMPERATURE1_PEAK, OT_FAULT_RESPONSE, UT_FAULT_RESPONSE,
STATUS_MFR_SPECIFIC, READ_TEMPERATURE_2, MFR_OT_FAULT_RESPONSE, MFR_PWM_MODE_LTC3882-1
MFR_TEMP_1_GAIN
The MFR_TEMP_1_GAIN command sets the slope used in the calculation of external temperature to account for non-
idealities in the element and remote sensing errors, if any. Refer to the MFR_PWM_MODE_LTC3882-1 command for
equation details.
This command has two data bytes representing a 2’s complement integer.
MFR_TEMP_1_OFFSET
The MFR_TEMP_1_OFFSET command sets the offset used in the calculation of external temperature to account for
non-idealities in the element and remote sensing errors, if any. The unit of measure for MFR_TEMP1_OFFSET depends
on bit 5 of MFR_PWM_MODE. MFR_TEMP1_ OFFSET is expressed volts if this bit is set and in °C otherwise. Refer to
the MFR_PWM_MODE_ LTC3882-1 command for equation details.
This command has two data bytes in Linear_5s_11s format.
OT_FAULT_LIMIT
The OT_FAULT_LIMIT command sets the value of sensed external temperature, in degrees Celsius, which causes an
overtemperature fault.
This command has two data bytes in Linear_5s_11s format.
OT_WARN_LIMIT
The OT_WARN_LIMIT command sets the value of sensed external temperature, in degrees Celsius, which causes an
overtemperature warning. If the OT_WARN_LIMIT is exceeded, the device:
• Sets the TEMPERATURE Bit in the STATUS_BYTE
• Sets the Overtemperature Warning Bit in the STATUS_TEMPERATURE Command
• Notifies the Host by Asserting ALERT, Unless Masked
This command has two data bytes in Linear_5s_11s format.
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LTC3882-1
(External Temperature Limits)
pMbuꢀ coMManD DeTails
UT_FAULT_LIMIT
The UT_FAULT_LIMIT command sets the value of sensed external temperature, in degrees Celsius, which causes an
undertemperature fault.
This command has two data bytes in Linear_5s_11s format.
STATUS REPORTING
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
STATUS_BYTE
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
0x78 One-byte channel status summary.
0x79 Two-byte channel status summary.
R/W Byte
R/W Word
R/W Byte
R/W Byte
R/W Byte
R/W Byte
Y
Y
Y
Y
N
Y
Reg
Reg
Reg
Reg
Reg
Reg
STATUS_WORD
STATUS_VOUT
0x7A
0x7B
V fault and warning status.
OUT
fault and warning status.
STATUS_IOUT
I
OUT
STATUS_INPUT
STATUS_TEMPERATURE
0x7C Input supply fault and warning status.
0x7D External temperature fault and warning
status.
STATUS_CML
0x7E Communication, memory and logic fault and R/W Byte
warning status.
N
Reg
STATUS_MFR_SPECIFIC
MFR_PADS_LTC3882-1
MFR_COMMON
0x80 LTC3882-1-specific status.
0xE5 State of selected LTC3882-1 pads.
0xEF LTC-generic device status reporting.
0x03 Clear all set fault bits.
R/W Byte
R Word
Y
N
N
N
Reg
Reg
Reg
R Byte
CLEAR_FAULTS
Send Byte
Refer to Figure 2 for a graphical depiction of these register contents and their relationships.
STATUS_BYTE
The STATUS_BYTE command returns a one-byte summary of the most critical faults.
STATUS_BYTE Message Contents:
BIT
7*
6
STATUS BIT NAME
MEANING
BUSY
OFF
A fault was declared because the LTC3882-1 was unable to respond.
This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not
being enabled.
5
4
VOUT_OV
IOUT_OC
VIN_UV
An output overvoltage fault has occurred.
An output overcurrent fault has occurred.
Not supported (LTC3882-1 returns 0).
3
2
TEMPERATURE
CML
A temperature fault or warning has occurred.
A communications, memory or logic fault has occurred.
1
0*
NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred.
*ALERT can be asserted if either of these bits is set. They may be cleared by writing a 1 to their bit position in the STATUS_BYTE, in lieu of a CLEAR_FAULTS
command.
This command has one data byte.
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LTC3882-1
(Status Reporting)
pMbuꢀ coMManD DeTails
STATUS_WORD
The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the STA-
TUS_WORD is the same as the STATUS_BYTE command.
STATUS_WORD High Byte Message Contents:
BIT
15
14
13
12
11
10
9
STATUS BIT NAME
VOUT
MEANING
An output voltage fault or warning has occurred.
An output current fault or warning has occurred.
An input voltage fault or warning has occurred.
A fault or warning specific to the LTC3882-1 has occurred.
The POWER_GOOD state is false if this bit is set.
Not supported (LTC3882-1 returns 0).
Not supported (LTC3882-1 returns 0).
Not supported (LTC3882-1 returns 0).
IOUT
INPUT
MFR_SPECIFIC
POWER_GOOD#
FANS
OTHER
8
UNKNOWN
This command has two data bytes.
STATUS_VOUT
The STATUS_VOUT command returns one byte of V
status information.
OUT
STATUS_VOUT Message Contents:
BIT
7
MEANING
V
OUT
V
OUT
V
OUT
V
OUT
overvoltage fault.
6
overvoltage warning.
undervoltage warning.
undervoltage fault.
5
4
3
VOUT_MAX warning.
2
TON_MAX fault.
1
TOFF_MAX warning.
0
Not supported by the LTC3882-1 (returns 0).
ALERT can be asserted if any of bits[7:1] are set. These may be cleared by writing a 1 to their bit position in STATUS_VOUT, in lieu of a CLEAR_FAULTS
command.
This command has one data byte.
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LTC3882-1
(Status Reporting)
pMbuꢀ coMManD DeTails
STATUS_IOUT
The STATUS_IOUT command returns one byte of I
status information.
OUT
STATUS_IOUT Message Contents:
BIT
7
MEANING
overcurrent fault.
I
OUT
6
Not supported (LTC3882-1 returns 0).
I overcurrent warning.
OUT
5
4:0
Not supported (LTC3882-1 returns 0).
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_IOUT, in lieu of a
CLEAR_FAULTS command.
This command has one data byte.
STATUS_INPUT
The STATUS_INPUT command returns one byte of V (VINSNS) status information.
IN
STATUS_INPUT Message Contents:
BIT
7
MEANING
overvoltage fault.
V
IN
6
Not supported (LTC3882-1 returns 0).
V undervoltage warning.
IN
5
4
Not supported (LTC3882-1 returns 0).
3
Unit off for insufficient V .
IN
2:0
Not supported (LTC3882-1 returns 0).
ALERT can be asserted if bit 7 is set. Bit 7 may be cleared by writing it to a 1, in lieu of a CLEAR_FAULTS command.
This command has one data byte.
STATUS_TEMPERATURE
The STATUS_TEMPERATURE command returns one byte of sensed external temperature status information.
STATUS_TEMPERATURE Message Contents:
BIT
7
MEANING
External overtemperature fault.
External overtemperature warning.
Not supported (LTC3882-1 returns 0).
External undertemperature fault.
Not supported (LTC3882-1 returns 0).
6
5
4
3:0
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_TEMPERATURE, in lieu
of a CLEAR_FAULTS command.
This command has one data byte.
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LTC3882-1
(Status Reporting)
pMbuꢀ coMManD DeTails
STATUS_CML
The STATUS_CML command returns one byte of status information on received commands, internal memory and logic.
STATUS_CML Message Contents:
BIT
7
MEANING
Invalid or unsupported command received.
Invalid or unsupported data received.
Packet error check failed.
6
5
4
Memory fault detected.
3
Processor fault detected.
2
Reserved (LTC3882-1 returns 0).
Other communication fault.
Other memory or logic fault.
1
0
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_CML, in lieu of a
CLEAR_FAULTS command.
This command has one data byte.
STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC command returns one byte with LTC3882-1 specific status information.
STATUS_MFR_SPECIFIC Message Contents:
BIT
7
MEANING
Internal temperature fault (>160°C).
Internal temperature warning (>130°C).
EEPROM CRC error.
6
5
4
Internal PLL unlocked.
Fault log present.
3
2
Not supported (LTC3882-1 returns 0).
Output short cycled.
1
0
FAULT low.
If any supported bits are set, the MFR bit in the STATUS_WORD will be set and ALERT may be asserted. Any supported bit may be cleared by writing a 1 to
that bit position in STATUS_MFR_SPECIFIC, in lieu of a CLEAR_FAULTS command.
This command has one data byte.
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LTC3882-1
(Status Reporting)
pMbuꢀ coMManD DeTails
MFR_PADS_LTC3882-1
The MFR_PADS_LTC3882-1 command provides status of the LTC3882-1 digital I/O and control pins, in addition to
general output voltage conditions.
MFR_PADS_LTC3882-1 Message Contents:
BIT
15
14
13:12
11
10
9
MEANING
Channel 1 is a slave.
Channel 0 is a slave.
Not supported (LTC3882-1 returns 0).
ADC results for I
may be invalid.
OUT
SYNC output disabled externally.
Channel 1 POWER_GOOD (normally returns 1 if slave).
Channel 0 POWER_GOOD (normally returns 1 if slave).
LTC3882-1 forcing RUN1 low.
LTC3882-1 forcing RUN0 low.
RUN1 pin state.
8
7
6
5
4
RUN0 pin state.
3
LTC3882-1 forcing FAULT1 low.
LTC3882-1 forcing FAULT0 low.
FAULT1 pin state.
2
1
0
FAULT0 pin state.
This read-only command has two data bytes.
MFR_COMMON
The MFR_COMMON command contains status bits that are common to multiple LTC PMBus products.
MFR_COMMON Message Contents:
BIT
7
MEANING
LTC3882-1 not forcing ALERT low.
LTC3882-1 not BUSY.
6
5
LTC3882-1 calculations not pending.
LTC3882-1 output not in transition.
LTC3882-1 EEPROM initialized.
Not supported (LTC3882-1 returns 0).
SHARE_CLK timeout.
4
3
2
1
0
Not supported (LTC3882-1 returns 0).
This read-only command has one data byte.
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LTC3882-1
(Status Reporting)
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CLEAR_FAULTS
The CLEAR_FAULTS command clears any fault bits that have been set and deasserts (releases) the ALERT pin. This
command clears all bits in all status commands simultaneously.
CLEAR_FAULTS does not cause a channel that has latched off for a fault condition to restart. Channels that are latched
off for a fault condition are restarted when the output is commanded to turn off and then on through the OPERATION
command or RUN pins, or IC supply power is cycled.
If a fault is still present when CLEAR_FAULTS is commanded, that fault bit will immediately be set and ALERT again
asserted low.
This write-only command has no data bytes.
TELEMETRY
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
READ_VIN
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
0x88 Measured V .
R Word
R Word
N
N
L11
L11
V
V
IN
MFR_VIN_PEAK
0xDE Maximum V measurement since last
IN
MFR_CLEAR_PEAKS.
READ_VOUT
0x8B Measured V
0xDD Maximum V
.
R Word
R Word
Y
Y
L16
L16
V
V
OUT
MFR_VOUT_PEAK
measurement since last
OUT
MFR_CLEAR_PEAKS.
READ_IOUT
0x8C Measured I
0xD7 Maximum I
.
R Word
R Word
Y
Y
L11
L11
A
A
OUT
MFR_IOUT_PEAK
measurement since last
OUT
MFR_CLEAR_PEAKS.
READ_POUT
0x96 Calculated output power.
0x8D Measured external temperature.
R Word
R Word
Y
Y
Y
L11
L11
L11
W
°C
°C
READ_TEMPERATURE_1
MFR_TEMPERATURE_1_PEAK
0xDF Maximum external temperature measurement R Word
since last MFR_CLEAR_PEAKS.
READ_TEMPERATURE_2
0x8E Measured internal temperature.
R Word
N
N
L11
L11
°C
°C
MFR_TEMPERATURE_2_PEAK
0xF4 Maximum internal temperature measurement R Word
since last MFR_CLEAR_PEAKS.
READ_DUTY_CYCLE
READ_FREQUENCY
MFR_CLEAR_PEAKS
0x94 Measured commanded PWM duty cycle.
0x95 Measured PWM input clock frequency.
0xE3 Clear all peak values.
R Word
R Word
Y
Y
N
L11
L11
%
kHz
Send Byte
Related commands: IOUT_CAL_GAIN, MFR_IOUT_CAL_GAIN_TC, MFR_PWM_MODE_LTC3882-1
READ_VIN
The READ_VIN command returns the input voltage measured between VINSNS and GND in volts.
This read-only command has two data bytes in Linear_5s_11s format.
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LTC3882-1
(Telemetry)
pMbuꢀ coMManD DeTails
MFR_VIN_PEAK
The MFR_VIN_PEAK command reports the highest voltage, in volts, measured for READ_VIN. This peak value can be
reset by a MFR_CLEAR_PEAKS command.
This read-only command has two data bytes in Linear_5s_11s format.
READ_VOUT
The READ_VOUT command returns the output voltage measured at the V
This read-only command has two data bytes in Linear_16u format.
pins in volts.
SENSE
MFR_VOUT_PEAK
The MFR_VOUT_PEAK command reports the highest voltage, in volts, measured for READ_VOUT. This peak value can
be reset by a MFR_CLEAR_PEAKS command.
This read-only command has two data bytes in Linear_16u format.
READ_IOUT
The READ_IOUT command returns the output current in amperes. This value is computed from:
• The differential voltage measured across the I
• The IOUT_CAL_GAIN value
pins
SENSE
• The MFR_IOUT_CAL_GAIN_TC value
• The READ_TEMPERATURE_1 value
• The MFR_TEMP_1_GAIN value
• The MFR_TEMP_1_OFFSET value
This read-only command has two data bytes in Linear_5s_11s format.
MFR_IOUT_PEAK
The MFR_IOUT_PEAK command reports the highest current, in amperes, calculated for READ_IOUT. This peak value
can be reset by a MFR_CLEAR_PEAKS command.
This read-only command has two data bytes in Linear_5s_11s format.
READ_POUT
The READ_POUT command reports the output power in watts. The value is calculated from the product of the most
recent correlated output voltage and current readings.
This read-only command has two data bytes in Linear_5s_11s format.
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LTC3882-1
(Telemetry)
pMbuꢀ coMManD DeTails
READ_TEMPERATURE_1
The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the external sense element.
This read-only command has two data bytes in Linear_5s_11s format.
MFR_TEMPERATURE_1_PEAK
The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, calculated for
READ_TEMPERATURE_1. This peak value can be reset by a MFR_CLEAR_PEAKS command.
This read-only command has two data bytes in Linear_5s_11s format.
READ_TEMPERATURE_2
The READ_TEMPERATURE_2 command returns the LTC3882-1 internal temperature in degrees Celsius.
This read-only command has two data bytes in Linear_5s_11s format.
MFR_TEMPERATURE_2_PEAK
The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, calculated for
READ_TEMPERATURE_2. This peak value can be reset by a MFR_CLEAR_PEAKS command.
This read-only command has two data bytes in Linear_5s_11s format.
READ_DUTY_CYCLE
The READ_DUTY_CYCLE command returns the duty cycle of the PWM control in percent. This will not be the exact duty
cycle of the PWM switch node due to efficiency losses in the power stage and current consumption of the LTC3882-1
itself.
This read-only command has two data bytes in Linear_5s_11s format.
READ_FREQUENCY
The READ_FREQUENCY command returns the switching frequency supplied to the internal PLL in kilohertz, whether
derived internally or provided by external clock on the SYNC pin. This may not be the actual PWM output switching
frequency during certain exception processing, such as an output overcurrent condition.
This read-only command has two data bytes in Linear_5s_11s format.
MFR_CLEAR_PEAKS
The MFR_CLEAR_PEAKS command resets all stored _PEAK values. The LTC3882-1 determines new peak values after
this command is received.
This write-only command has no data bytes.
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LTC3882-1
(Fault Response and Communication)
pMbuꢀ coMManD DeTails
FAULT RESPONSE AND COMMUNICATION
CMD
DATA
DEFAULT
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
VALUE
0x80
0xB8
0xB8
0x00
0xB8
0xB8
0xC0
0xB8
l
VIN_OV_FAULT_RESPONSE
VOUT_OV_FAULT_RESPONSE
VOUT_UV_FAULT_RESPONSE
IOUT_OC_FAULT_RESPONSE
OT_FAULT_RESPONSE
0x56
0x41
0x45
V
V
V
overvoltage fault response.
R/W Byte
R/W Byte
R/W Byte
R/W Byte
R/W Byte
R/W Byte
R/W Byte
R/W Byte
Y
Y
Y
Y
Y
Y
N
Y
Reg
Reg
Reg
Reg
Reg
Reg
Reg
Reg
IN
l
l
l
l
l
l
l
overvoltage fault response.
undervoltage fault response.
OUT
OUT
0x47 Output overcurrent fault response.
0x50 External overtemperature fault response.
0x54 External undertemperature fault response.
0xD6 Internal overtemperature fault response.
UT_FAULT_RESPONSE
MFR_OT_FAULT_RESPONSE
TON_MAX_FAULT_RESPONSE
0x63 Fault response when
TON_MAX_FAULT_LIMIT is exceeded.
l
l
l
l
MFR_RETRY_DELAY
SMBALERT_MASK
0xDB Minimum time before retry after a fault.
R/W Word
Block R/W
R/W Word
N
Y
Y
L11
Reg
Reg
ms
350ms
0xFABC
0x1B Mask ALERT Activity.
See CMD
Details
MFR_FAULT_PROPAGATE_
LTC3882-1
0xD2 Configure status propagation via FAULTn
0x6993
pins.
MFR_FAULT_RESPONSE
MFR_FAULT_LOG
0xD5 PWM response when FAULTn pin is low.
0xEE Read fault log data.
R/W Byte
R Block
Y
N
N
Reg
Reg
0xC0
MFR_FAULT_LOG_CLEAR
0xEC Clear existing EEPROM fault log.
Send Byte
Related commands: STATUS_BYTE, STATUS_WORD, MFR_PADS_LTC3882-1, MFR_RESTART_DELAY, MFR_CHAN_CONFIG_LTC3882-1, MFR_FAULT_
LOG_STORE, CLEAR_FAULTS
Thesecommandsdetailprogrammabledeviceresponsesfordetectedfaultsbeyondthehardware-levelactionsdescribed
in the Operations section. LTC3882-1 hardware-level fault responses cannot be modified. Refer to Table 1 to Table 4
for details of fault log contents. PMBus warning event responses are listed under _WARN_LIMIT command details.
VIN_OV_FAULT_RESPONSE
The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input overvolt-
age fault. The format for this command is given in Table 13. The device also:
• Sets the INPUT Bit in the STATUS_WORD
• Sets the V Overvoltage Fault Bit in the STATUS_INPUT Command
IN
• Notifies the Host by Asserting ALERT, Unless Masked
This command has one data byte.
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VOUT_OV_FAULT_RESPONSE
The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overvoltage fault. The format for this command is given in Table 12. The device also:
• Sets the VOUT_OV Bit in the STATUS_BYTE
• Sets the VOUT Bit in the STATUS_WORD
• Sets the V
Overvoltage Fault Bit in the STATUS_VOUT Command
OUT
• Notifies the Host by Asserting ALERT, Unless Masked
This command has one data byte.
VOUT_UV_FAULT_RESPONSE
The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
undervoltage fault. The format for this command is given in Table 12. The device also:
• Sets the VOUT Bit in the STATUS_WORD
• Sets the V
Undervoltage Fault Bit in the STATUS_VOUT Command,
OUT
• Notifies the Host by Asserting ALERT, Unless Masked
This command has one data byte.
Table 12. Data Byte Contents for VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE
BITS
DESCRIPTION
VALUE
MEANING
[7:6]
For all values of bits [7:6], the LTC3882-1:
00
The LTC3882-1 continues to operate indefinitely with the
normal hardware response described in the Operation
section.
• Sets the corresponding fault bits in the status commands.
• Notifies the host by asserting ALERT, unless masked.
01
The LTC3882-1 continues operating with the normal
hardware response for the delay time specified by bits [2:0].
If the fault is continuously present for the entire delay, the
unit then disables the output and does attempt to restart.
The fault, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The corresponding STATUS_VOUT bit is written to a one.
• The output is commanded off, then on, by the RUN pin or
OPERATION command.
• The device receives a RESTORE_USER_ALL command.
• The device receives an MFR_RESET command.
• IC supply power is cycled.
10
11
The LTC3882-1 immediately disables the output and
responds according to the retry setting in bits [5:3].
Not supported. Writing this value will generate a CML fault.
[5:3]
Retry setting.
000-110 The LTC3882-1 does not attempt to restart. The output
remains disabled until the fault is cleared, the device is
commanded off and then on, or bias power (LTC3882-1
power supply input) is cycled.
111
The LTC3882-1 attempts to restart continuously without
limitation with an interval set by MFR_RETRY_DELAY.
This response persists until the unit is commanded off, or
bias power is removed, or another fault response forces
shutdown without retry.
[2:0]
Delay time.
xxx
Response delay time in 10ꢀs increments. This delay
time determines how long the fault may have to persist
before the controller is disabled, depending on bits [7:6].
Hardware-level response, if any, will occur during this delay.
These bits always return zero if bits [7:6] are not set to 0x2.
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IOUT_OC_FAULT_RESPONSE
The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overcurrent fault. The device also:
• Sets the IOUT_OC Bit in the STATUS_BYTE
• Sets the IOUT Bit in the STATUS_WORD
• Sets the I
Overcurrent Fault Bit in the STATUS_IOUT Command
OUT
• Notifies the Host by Asserting ALERT
Output overcurrent faults are ignored during TON_RISE and TOFF_FALL output sequencing.
Data Byte Contents for IOUT_OC_FAULT_RESPONSE:
BITS
DESCRIPTION
VALUE
MEANING
[7:6]
For all values of bits [7:6], the LTC3882-1:
0x
The LTC3882-1 continues to operate indefinitely with the
normal hardware response described in the Operation
section.
• Sets the corresponding fault bits in the status commands.
• Notifies the host by asserting ALERT, unless masked.
10
11
The LTC3882-1 continues operating with the normal
hardware response for the delay time specified by bits
[2:0]. If the fault is continuously present for the entire delay,
the unit then disables the output and does not attempt to
restart.
The fault, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The corresponding STATUS_IOUT bit is written to a one.
• The output is commanded off, then on, by the RUN pin or
OPERATION command.
• The device receives a RESTORE_USER_ALL command.
• The device receives an MFR_RESET command.
• IC supply power is cycled.
The LTC3882-1 shuts down (disables the output) and
responds according to the retry setting in bits [5:3].
[5:3]
[2:0]
Retry setting.
000-110 The LTC3882-1 does not attempt to restart. The output
remains disabled until the fault is cleared, the device is
commanded off and then on, or bias power is cycled.
111
The LTC3882-1 attempts to restart continuously without
limitation with an interval set by MFR_RETRY_DELAY.
This response persists until the unit is commanded off,
bias power is removed, or another fault response forces
shutdown without retry.
Delay time.
xxx
Response delay time in 16ms increments. This delay time
determines how long the fault may have to persist before
the controller is disabled, depending on bits [7:6]. These
bits always return zero if bits [7:6] are not set to 0x2.
Programming an unsupported IOUT_OC_FAULT_RESPONSE value will generate a CML fault and the command will
be ignored.
This command has one data byte.
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OT_FAULT_RESPONSE
The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an overtemperature
fault. The format for this command is given in Table 13. The device also:
• Sets the TEMPERATURE Bit in the STATUS_BYTE
• Sets the Overtemperature Fault Bit in the STATUS_TEMPERATURE Command
• Notifies the Host by Asserting ALERT, Unless Masked
This command has one data byte.
UT_FAULT_RESPONSE
The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an undertemperature
fault. The format for this command is given in Table 13. The device also:
• Sets the TEMPERATURE Bit in the STATUS_BYTE
• Sets the Undertemperature Fault Bit in the STATUS_TEMPERATURE Command
• Notifies the Host by Asserting ALERT, Unless Masked
This command has one data byte.
MFR_OT_FAULT_RESPONSE
The MFR_OT_FAULT_RESPONSE command instructs the device on what action to take in response to an internal
overtemperature fault (150°C to 160°C). The device also:
• Sets the MFR Bit in the STATUS_WORD
• Sets the Overtemperature Fault Bit in the STATUS_MFR_SPECIFIC Command
• Notifies the Host by Asserting ALERT, Unless Masked
Supported Values:
VALUE
0xC0
MEANING
The LTC3882-1 continues to operate indefinitely with the normal hardware response described in the Operation section.
0x80
The LTC3882-1 shuts down immediately and does not attempt to restart. The output remains disabled until the fault is cleared and the unit
is commanded off and then on, or bias power (LTC3882-1 power supply input) is cycled.
Programming an unsupported MFR_OT_FAULT_RESPONSE value will generate a CML fault and the command will be
ignored.
This command has one data byte.
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TON_MAX_FAULT_RESPONSE
The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX
fault. The format for this command is given in Table 13. The device also:
• Sets the VOUT Bit in the STATUS_WORD
• Sets the TON_MAX_FAULT Bit in the STATUS_VOUT Command
• Notifies the Host by Asserting ALERT, Unless Masked
This command has one data byte.
Table 13. Data Byte Contents for the Following _FAULT_RESPONSE Commands: VIN_OV, OT, UT and TON_MAX
BITS
DESCRIPTION
VALUE
00
MEANING
[7:6]
For all values of bits [7:6], the LTC3882-1:
The LTC3882-1 continues operating without interruption.
Not supported. Writing this value will generate a CML fault.
• Sets the corresponding fault bits in the status commands.
• Notifies the host by asserting ALERT, unless masked.
01
10
The LTC3882-1 shuts down immediately (disables the
output) and responds according to the retry setting in bits
[5:3].
The fault, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The corresponding fault bit is written to a one.
• The output is commanded off, then on, by the RUN pin or
OPERATION command.
11
Not supported. Writing this value will generate a CML fault.
• The device receives a RESTORE_USER_ALL command.
• The device receives an MFR_RESET command.
• IC supply power is cycled.
[5:3]
[2:0]
Retry setting.
000-110 The LTC3882-1 does not attempt to restart. The output
remains disabled until the fault is cleared, the device is
commanded off and then on, or bias power is cycled.
111
The LTC3882-1 attempts to restart continuously without
limitation with an interval set by MFR_RETRY_DELAY.
This response persists until the unit is commanded off,
bias power is removed, or another fault response forces
shutdown without retry.
Delay time.
xxx
Not supported. Values ignored.
MFR_RETRY_DELAY
The MFR_RETRY_DELAY command sets the time in milliseconds between restart attempts for all retry fault responses.
The actual retry delay may be the longer of MFR_RETRY_DELAY or the time required for the output voltage to decay
below 12.5% of its programmed value. Decay qualification can be disabled using the MFR_CHAN_CONFIG_LTC3882-1
command. Retry delay starts once the fault is no longer detected by the LTC3882-1 or its FAULT pin is externally re-
leased. Legal values run from 120ms to 32.7 seconds.
This command has two data bytes in Linear_5s_11s format.
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SMBALERT_MASK
The SMBALERT_MASK command can be used to prevent a particular status bit or bits from asserting ALERT as they
are asserted.
Figure 51 shows an example of the Write Word format used to set an ALERT mask, in this case without PEC. The bits
in the mask byte align with bits in the specified status register. For example, if the STATUS_TEMPERATURE command
code is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warn-
ing would still set bit 6 of STATUS_TEMPERATURE but not assert ALERT. All other supported STATUS_TEMPERATURE
bits would continue to assert ALERT if set.
1
7
1
1
8
1
8
1
8
1
1
SLAVE
ADDRESS
SMBALERT_MASK
COMMAND CODE
STATUS_x
COMMAND CODE
S
W
A
A
A
MASK BYTE
A
P
38821 F51
Figure 51. Example of Setting SMBALERT_MASK
Figure 52 shows an example of the Block Write – Block Read Process Call protocol used to read back the present state
of any supported status register, again without PEC.
1
7
1
1
8
1
8
1
8
1
SLAVE
ADDRESS
SMBALERT_MASK
COMMAND CODE
BLOCK COUNT
(= 1)
STATUS_x
COMMAND CODE
S
W
A
A
A
A
…
1
7
1
1
8
1
8
1
1
SLAVE
ADDRESS
BLOCK COUNT
(= 1)
Sr
R
A
A
MASK BYTE
NA
P
38821 F52
Figure 52. Example of Reading SMBALERT_MASK
SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS_LTC3882-1.
Factory default masking for applicable status registers is shown below. Providing an unsupported command code to
SMBALERT_MASK will generate a CML for Invalid/Unsupported Data.
SMBALERT_MASK Default Setting: (Refer Also to Figure 2)
STATUS RESISTER
STATUS_VOUT
ALERT Mask Value MASKED BITS
0x00
0x00
0x00
0x00
0x00
0x11
None
STATUS_IOUT
None
STATUS_TEMPERATURE
STATUS_CML
None
None
STATUS_INPUT
None
STATUS_MFR_SPECIFIC
Bit 4 (internal PLL unlocked), bit 0 (FAULT low)
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MFR_FAULT_PROPAGATE_LTC3882-1
The MFR_FAULT_PROPAGATE_LTC3882-1 command determines events that cause FAULT to be asserted. Setting a
bit in this register to a one allows the specified condition to assert the FAULT output for that channel. FAULT is not as-
serted by a fault, even if set to propagate, if that FAULT_RESPONSE is set to Ignore. The state of SMBLALERT_MASK
does not affect FAULT propagation.
Supported Values:
BIT
15
14
13
12
11
10
9
PROPAGATED CONDITION
Waiting for V decay before restart.
OUT
V
OUT
short cycled (automatically deasserted 120ms after V
is fully OFF).
OUT
TON_MAX_FAULT_LIMIT exceeded.
(Reserved, must be set to 0).
MFR_OT_FAULT_LIMIT exceeded.
(Reserved, must be set to 0).
(Reserved, must be set to 0).
UT_FAULT_LIMIT exceeded.
OT_FAULT_LIMIT exceeded.
(Reserved).
8
7
6
5
(Reserved).
4
VIN_OV_FAULT_LIMIT exceeded.
(Reserved).
3
2
IOUT_OC_FAULT_LIMIT exceeded.
VOUT_UV_FAULT_LIMIT exceeded.
VOUT_OV_FAULT_LIMIT exceeded.
1
0
This command has two data bytes.
MFR_FAULT_RESPONSE
The MFR_FAULT_RESPONSE command instructs the device on what action to take in response to a FAULT pin being
pulled low by anything other than an internal fault.
Supported Values:
VALUE
0xC0
MEANING
Related PWM output is immediately disabled.
Input ignored, PWM operation continues without interruption.
0x00
When a FAULT pin is low, the device also:
• Sets the MFR_SPECIFIC Bit in the STATUS_WORD
• Sets Bit 0 in the STATUS_MFR_SPECIFIC Command to Indicate FAULT Is or Has Been Low
• Notifies the Host by Asserting ALERT, Unless Masked
This command has one data byte.
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MFR_FAULT_LOG
The MFR_FAULT_LOG command allows the contents of the fault log to be read. This log is created with a
MFR_FAULT_LOG_STOREcommandoratthefirstfaultoccurrenceafteraCLEAR_FAULTSorMFR_FAULT_LOG_CLEAR
command. If a fault occurs within the first second after applying power, some earlier pages in the log may not contain
valid data.
This read-only command uses block protocol with 147 bytes of data requiring an estimated data transfer time of 3.4ms
at 400kHz. The t
parameter is extended when this command is executed and a fault log is present.
TIMEOUT
MFR_FAULT_LOG_CLEAR
The MFR_FAULT_LOG_CLEAR command erases all stored fault log values. After a clear is issued, up to 8ms may be
required to clear related bit 3 in STATUS_MFR_SPECIFIC.
This write-only command has no data bytes.
EEPROM USER ACCESS
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
STORE_USER_ALL
RESTORE_USER_ALL
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
0x15 Store entire operating memory in EEPROM.
Send Byte
Send Byte
N
N
NA
NA
0x16 Restore entire operating memory from
EEPROM.
MFR_COMPARE_USER_ALL
MFR_FAULT_LOG_STORE
0xF0 Compare operating memory with EEPROM
contents.
Send Byte
Send Byte
N
N
0xEA Force transfer of fault log from operating
memory to EEPROM.
MFR_EE_UNLOCK
MFR_EE_ERASE
MFR_EE_DATA
USER_DATA_00
USER_DATA_01
USER_DATA_02
USER_DATA_03
0xBD (contact the factory)
0xBE (contact the factory)
0xBF (contact the factory)
l
0xB0 EEPROM word reserved for LTpowerPlay.
0xB1 EEPROM word reserved for LTpowerPlay.
0xB2 EEPROM word reserved for OEM use.
R/W Word
R/W Word
R/W Word
R/W Word
N
Y
N
Y
Reg
Reg
Reg
Reg
l
l
l
0xB3 EEPROM word available for general data
storage.
0x0000
0x0000
l
USER_DATA_04
0xB4 EEPROM word available for general data
storage.
R/W Word
N
Reg
Related commands: MFR_CONFIG_ALL_LTC3882-1
Note that if the LTC3882-1 die temperature exceeds 130°C, execution of any command in the above table except RE-
STORE_USER_ALL and MFR_FAULT_LOG_STORE will be disabled until the IC temperature drops below 125°C. RE-
STORE_USER_ALL is executed immediately, and MFR_FAULT_LOG_STORE is executed after the IC temperature drops
below 125°C. Refer to Table 4 for details of fault log contents. Using any command that writes data to the EEPROM is
strongly discouraged if bit 6 of STATUS_MFR_ SPECIFIC is set, indicating the internal die temperature is above 85°C.
Data retention of 10 years is not guaranteed if the EEPROM is written above a junction temperature of 85°C.
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LTC3882-1
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STORE_USER_ALL
The STORE_USER_ALL command instructs the PMBus device to copy the entire contents of the operating memory to
internal EEPROM PMBus configuration space.
This write-only command has no data bytes.
RESTORE_USER_ALL
The RESTORE_USER_ALL command instructs the PMBus device to copy the entire contents of the internal EEPROM
to matching locations in operating memory. The values in operating memory are overwritten by the values retrieved
from EEPROM. Both channels should be turned off prior to issuing this command. The LTC3882-1 ensures both PWM
channels are off, loads the operating memory from internal EEPROM, clears all faults, reads the resistor configuration
pins, and then performs a soft-start of both PWM channels, if enabled
This write-only command has no data bytes.
MFR_COMPARE_USER_ALL
The MFR_COMPARE_USER_ALL command instructs the LTC3882-1 to compare current operating memory (PMBus
command values in RAM) with the contents of the internal EEPROM. If the compared memories differ, a CML fault is
generated.
This write-only command has no data bytes.
MFR_FAULT_LOG_STORE
TheMFR_FAULT_LOG_STOREcommandforcesadatalogtobewrittentointernalEEPROMasifafaulteventhadoccurred.
This command will generate a CML fault if the Enable Fault Logging bit is cleared in MFR_CONFIG_ALL_LTC3882-1.
This write-only command has no data bytes.
MFR_EE_xxxx
The MFR_EE_xxxx commands facilitate bulk programming of the LTC3882-1 internal EEPROM. Contact the factory
for details.
USER_DATA_0x
The USER_DATA_0x commands provide uncommitted EEPROM locations that may be applied as system scratchpad
space. USER_DATA_00 and USER_DATA_01 should not be modified when using the LTpowerPlay GUI. Some contract
manufacturers also reserve use of USER_DATA_02 for their own inventory control.
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LTC3882-1
(Unit Identification)
pMbuꢀ coMManD DeTails
UNIT IDENTIFICATION
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
MFR_ID
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
0x99 Manufacturer identification.
0x9A LTC model number.
R String
R String
R Block
N
N
N
ASC
ASC
Reg
LTC
MFR_MODEL
MFR_SERIAL
LTC3882-1
0x9E Device serial number.
MFR_ID
The MFR_ID command returns the manufacturer ID of the LTC3882-1 using 8-bit ASCII characters.
This read-only command is in block format.
MFR_MODEL
The MFR_MODEL command returns the LTC part number using 8-bit ASCII characters.
This read-only command is in block format.
MFR_SERIAL
The MFR_SERIAL command returns the serial number of this specific device using a maximum of fourteen 8-bit ASCII
characters.
This read-only command is in block format.
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LTC3882-1
Typical applicaTions
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LTC3882-1
Typical applicaTions
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LTC3882-1
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-ꢀ728 Rev Ø)
0.70 0.05
6.50 0.05
5.ꢀ0 0.05
4.42 0.05
4.50 0.05
(4 SIDES)
4.42 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 0.05
R = 0.ꢀꢀ5
TYP
6.00 0.ꢀ0
(4 SIDES)
R = 0.ꢀ0
TYP
39 40
0.40 0.ꢀ0
PIN ꢀ TOP MARK
(SEE NOTE 6)
ꢀ
2
PIN ꢀ NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
4.42 0.ꢀ0
4.50 REF
(4-SIDES)
4.42 0.ꢀ0
(UJ40) QFN REV Ø 0406
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
BOTTOM VIEW—EXPOSED PAD
ꢀ. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE TOP AND BOTTOM OF PACKAGE
38821f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
107
LTC3882-1
Typical applicaTion
V
IN
7V TO 14V
1Ω
+
330µF
×2
100nF
5V
BIAS
+5V INPUT SUPPLY
V
1µF
2.2µF
DD33
V
V
CC
DD25
10Ω
2k
INPUT SUPPLY +5V TO +12V
V
IN
2.2µF
4.99k
1µF
4.7µF
10k
10k
10k
10k
4.99k
24
22
4
25
1µF
SMOD
4.99k
V
DD33
V
VINSNS
V
DD25
CC
22µF
×2
9
10
11
12
13
7
6
38
SCL
V
PHASE GH CGND GND BOOT
FDMF6820A
V
V
CIN
PWM0
PWM0
IN
DRV
100k
V
SDA
DD33
PGOOD0
+
PWM
PWM0
L1
ALERT
FAULT0
I
SENSE0
0.22µH
PULSE
DISB
RUN
37
36
35
40
PGND
V
–
+
–
OUT0
1.8V, 30A
V
I
V
V
FAULT1
RUN0
RUN1
SWH
SENSE0
SENSE0
SENSE0
14
15
23
8
+
RUN
CGND
100µF
×4
470µF
×4
1.21k
GL
FB0
SHARE_CLK
SYNC
GND
137Ω
10nF
0.22µF
100pF
1
COMP0
PLACE Q1,Q2 NEAR L1, L2 RESPECTIVELY
10nF 10nF
LTC3882-1
7.32k
220pF
16
17
ASEL0
ASEL1
16.2k
17.4k
V
2
3
Q1
Q2
DD25
TSNS0
TSNS1
5V
BIAS
220pF
7.32k
28
29
COMP1
FB1
1µF
2.2µF
10Ω
2k
10nF
100pF
18
19
20
21
39
30
137Ω
V
IN
V
V
OUT0_CFG
OUT1_CFG
1µF
SMOD
33
34
32
31
26
27
+
V
V
SENSE1
FREQ_CFG
PHAS_CFG
22µF
×2
0.22µF
1.21k
–
SENSE1
V
PHASE GH CGND GND BOOT
FDMF6820A
V
V
CIN
IN
DRV
–
I
I
I
AVG0
SENSE1
PWM
PWM1
RUN
+
I
AVG1
SENSE1
DISB
PWM1
PWM1
100k
PGND
V
V
I
OUT1
1V, 40A
470µF
DD33
AVG_GND
PGOOD1
GND
41
V
SWH
L2
0.22µH
PULSE
5
+
CGND
100µF
×4
×4
DrMOS: FAIRCHILD FD6802A
GL
GND
38821 F55
Figure 55. 1V/40A and 1.8V/30A 500kHz Converter with DrMOS Power Stage
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
LTM4676A
Dual 13A or Single 26A Step-Down DC/DC ꢀModule
Regulator with Digital Power Management
V
Up to 26.5V; 0.5V ≤ V
( 0.5%) ≤ 5.4V, 2% I
ADC Accuracy,
IN
OUT
OUT
2
Fault Logging, I C/PMBus Interface, 16mm × 16mm × 5mm, BGA
Package
2
LTC3887/
LTC3887-1
Dual Output PolyPhase Step-Down DC/DC Controller with
Digital Power System Management, 70ms Start-Up
V
Up to 24V, 0.5V ≤ V
≤ 5.5V, 70mS Start-Up, I C/PMBus
IN
OUT0,1
Interface, with EEPROM and 16-Bit ADC. –1 Version Operates with
DrMOS and Power Blocks
2
LTC3886
60V Dual Output Step-Down Controller with Digital Power
System Management. 70ms Start-Up
V
Up to 60V, 0.5V ≤ V
≤ 13.8V, Analog Control Loop, I C/
IN
OUT
PMBus Interface with EEPROM and 16-Bit ADC, Programmable Loop
Compensation
2
LTC3880/
LTC3880-1
Dual Output PolyPhase Step-Down DC/DC Controller with
Digital Power System Management
V
Up to 24V, 0.5V ≤ V
≤ 5.5V, Analog Control Loop, I C/PMBus
IN
OUT
Interface with EEPROM and 16-Bit ADC
2
LTC3883/
LTC3883-1
Single Phase Step-Down DC/DC Controller with Digital Power
System Management
V
Up to 24V, 0.5V ≤ V
≤ 5.5V, Input Current Sense Amplifier, I C/
IN
OUT
PMBus Interface with EEPROM and 16-Bit ADC
LTC2977
LTC2974
LTC3774
LTC3861
LTC4449
8-Channel PMBus Power System Manager Featuring
Accurate Output Voltage Measurement
Fault Logging to Internal EEPROM Monitors Eight Output Voltages, Input
Voltage and Die Temperature
Quad Digital Power Supply Manager with EEPROM
Controls and Monitors Four Outputs, 16-Bit ADC, Differential Inputs,
with Fault Logging
Dual, Multiphase Current Mode Synchronous Controller for
Sub-Milliohm DCR Sensing, with Remote Sense
Operates with Power Blocks, DrMOS Devices or External MOSFETs 4.5V
≤ V ≤ 38V
IN
Dual, Multiphase, Synchronous Step-Down DC/DC Controller Operates with Power Blocks, DrMOS Devices or External MOSFETs 3V≤
with Accurate Current Share
V
IN
≤ 24V
High Speed Synchronous N-Channel MOSFET Driver
V
Up to 38V, 4V ≤ V ≤ 6.5V, Adaptive Shoot-Through Protection,
CC
IN
2mm × 3mm DFN-8 Package
38821f
LT 0915 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
108
●
●
LINEAR TECHNOLOGY CORPORATION 2015
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3882-1
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