LTC3892HUH#PBF [Linear]
LTC3892 - 60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller; Package: QFN; Pins: 32; Temperature Range: -40°C to 125°C;型号: | LTC3892HUH#PBF |
厂家: | Linear |
描述: | LTC3892 - 60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller; Package: QFN; Pins: 32; Temperature Range: -40°C to 125°C |
文件: | 总38页 (文件大小:1316K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3892/
LTC3892-1/LTC3892-2
60V Low I , Dual, 2-Phase
Q
Synchronous Step-Down
DC/DC Controller
DESCRIPTION
FEATURES
The LTC®3892/LTC3892-1/LTC3892-2 is a high perfor-
mancedualstep-downDC/DCswitchingregulatorcontrol-
n
Wide V Range: 4.5V to 60V (65V Abs Max)
IN
n
Wide Output Voltage Range: 0.8V ≤ V
≤ 99% • V
OUT
IN
n
n
n
n
n
Adjustable Gate Drive Level 5V to 10V (OPTI-DRIVE) ler that drives all N-channel synchronous power MOSFET
No External Bootstrap Diodes Required
stages. Power loss and noise are minimized by operating
the two controller output stages out-of-phase.
Low Operating I : 29μA (One Channel On)
Q
Selectable Gate Drive UVLO Thresholds
The gate drive voltage can be programmed from 5V to
10V to allow the use of logic or standard-level FETs and
to maximize efficiency. Internal switches in the top gate
drivers eliminate the need for external bootstrap diodes.
Out-of-Phase Operation Reduces Required Input
Capacitance and Power Supply Induced Noise
Phase-Lockable Frequency: 75kHz to 850kHz
Selectable Continuous, Pulse Skipping or Low Ripple
Burst Mode® Operation at Light Loads
n
n
Awide4.5Vto60Vinputsupplyrangeencompassesawide
rangeofintermediatebusvoltagesandbatterychemistries.
n
n
n
n
n
Selectable Current Limit (LTC3892/LTC3892-2)
Very Low Dropout Operation: 99% Duty Cycle
Power Good Output Voltage Monitors (LTC3892/LTC3892-2)
Output voltages up to 99% of V can be regulated. OPTI-
IN
LOOP® compensation allows the transient response and
loop stability to be optimized over a wide range of output
capacitance and ESR values.
Low Shutdown I : 3.6μA
Q
Small 32-Lead 5mm × 5mm QFN Package (LTC3892/
LTC3892-2) or TSSOP Package (LTC3892-1)
The29μAno-loadquiescentcurrentextendsoperatingrun
time in battery powered systems. For a comparison of the
LTC3892 to the LTC3892-1 and LTC3892-2, see Table 1
in the Pin Functions section of this data sheet.
L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are
registered trademarks of Analog Devices, Inc. All other trademarks are the property of their
respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620, 6144194,
6177787, 6580258.
APPLICATIONS
n
Automotive and Industrial Power Systems
n
Distributed DC Power Systems
n
High Voltage Battery Operated Systems
TYPICAL APPLICATION
High Efficiency Dual 5V/12V Output Step-Down Converter
VIN
12.5V TO 60V
RUN1
TG1
VIN
RUN2
TG2
47µF
Efficiency vs Output Current
96
BOOST1
BOOST2
0.1µF
0.1µF
V
OUT
= 12V
IN
8mΩ
5.6µH
V
5mΩ
15µH
V
OUT2
OUT1
V
= 5V
95
94
93
92
91
90
89
88
5V
12V
SW1
SW2
Burst Mode OPERATION
8A
5A
BG1
BG2
220µF
150µF
LTC3892
+
+
SENSE1
SENSE2
100k
1nF
1nF
–
–
SENSE1
SENSE2
GATE DRIVE
DRV =5V
V
FB1
V
CC
FB2
DRV =6V
CC
ITH1
TRACK/SS1
ITH2
TRACK/SS2
DRV =8V
CC
DRV =10V
CC
7.15k
VPRG1
DRVSET
7.5k
34.8k
0.01
0.1
1
10
DRVUV
LOAD CURRENT (A)
100pF
0.1µF
100pF
0.1µF
3892 F01b
INTV
GND
DRV
CC
CC
2.2nF
1nF
0.1µF
4.7µF
3892 TA01
38921fc
1
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
ABSOLUTE MAXIMUM RATINGS (Notes 1, 3)
TRACK/SS1, TRACK/SS2 Voltages .............. –0.3V to 6V
Input Supply Voltage (V )......................... –0.3V to 65V
IN
PGOOD1, PGOOD2 Voltages
Top Side Driver Voltages
(LTC3892/LTC3892-2)............................. –0.3V to 6V
VPRG1, ILIM Voltages
(LTC3892/LTC3892-2)............................. –0.3V to 6V
Operating Junction Temperature Range (Note 2)
LTC3892E, LTC3892I,
(BOOST1, BOOST2) ............................... –0.3V to 76V
Switch Voltage (SW1, SW2).......................... –5V to 70V
DRV , (BOOST1-SW1),
CC
(BOOST2-SW2).......................................–0.3V to 11V
BG1, BG2, TG1, TG2...........................................(Note 8)
RUN1, RUN2 Voltages................................ –0.3V to 65V
LTC3892E-1, LTC3892I-1,
LTC3892E-2, LTC3892I-2................... –40°C to 125°C
LTC3892H,
LTC3892H-1, LTC3892H-2 ................. –40°C to 150°C
LTC3892MP, LTC3892MP-1,
+
+
–
SENSE1 , SENSE2 , SENSE1
–
SENSE2 Voltages ................................. –0.3V to 65V
PLLIN/MODE, FREQ Voltages ...................... –0.3V to 6V
EXTV Voltage ......................................... –0.3V to 14V
CC
LTC3892MP-2.................................... –55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
I
, I , V , V Voltages ..................... –0.3V to 6V
TH1 TH2 FB1 FB2
DRVSET, DRVUV Voltages ........................... –0.3V to 6V
PIN CONFIGURATION
LTC3892/LTC3892-2
LTC3892-1
TOP VIEW
TOP VIEW
1
2
TRACK/SS1
TG1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ITH1
V
FB1
+
3
SW1
SENSE1
SENSE1
32 31 30 29 28 27 26 25
–
4
BOOST1
BG1
FREQ
PLLIN/MODE
PGOOD1
1
2
3
4
5
6
7
8
24 BOOST1
23 BG1
5
FREQ
6
V
IN
PLLIN/MODE
V
22
21
IN
7
EXTV
CC
INTV
CC
29
GND
PGOOD2
EXTV
CC
33
GND
8
DRV
CC
RUN1
INTV
20 DRV
CC
CC
9
BG2
RUN2
RUN1
RUN2
ILIM
BG2
19
–
10
11
12
13
14
BOOST2
SW2
18 BOOST2
17 SW2
SENSE2
+
SENSE2
9
10 11 12 13 14 15 16
TG2
V
FB2
TRACK/SS2
DRVSET
ITH2
DRVUV
FE PACKAGE
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
= 150°C, θ = 44°C/W
28-LEAD PLASTIC TSSOP
T
= 150°C, θ = 30°C/W
JMAX
JA
T
JMAX
JA
EXPOSED PAD (PIN 29) IS GND, MUST BE CONNECTED TO GND
EXPOSED PAD (PIN 33) IS GND, MUST BE CONNECTED TO GND
38921fc
2
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
ORDER INFORMATION
http://www.linear.com/product/LTC3892#orderinfo
LEAD FREE FINISH
LTC3892EUH#PBF
LTC3892IUH#PBF
TAPE AND REEL
PART MARKING*
3892
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
LTC3892EUH#TRPBF
LTC3892IUH#TRPBF
LTC3892HUH#TRPBF
LTC3892MPUH#TRPBF
LTC3892EFE-1#TRPBF
LTC3892IFE-1#TRPBF
LTC3892HFE-1#TRPBF
32-Lead (5mm × 5mm) Plastic QFN
32-Lead (5mm × 5mm) Plastic QFN
32-Lead (5mm × 5mm) Plastic QFN
32-Lead (5mm × 5mm) Plastic QFN
28-Lead Plastic TSSOP
3892
LTC3892HUH#PBF
LTC3892MPUH#PBF
LTC3892EFE-1#PBF
LTC3892IFE-1#PBF
LTC3892HFE-1#PBF
LTC3892MPFE-1#PBF
LTC3892EUH-2#PBF
LTC3892IUH-2#PBF
LTC3892HUH-2#PBF
LTC3892MPUH-2#PBF
3892
3892
LTC3892FE-1
LTC3892FE-1
LTC3892FE-1
28-Lead Plastic TSSOP
28-Lead Plastic TSSOP
LTC3892MPFE-1#TRPBF LTC3892FE-1
28-Lead Plastic TSSOP
LTC3892EUH-2#TRPBF
LTC3892IUH-2#TRPBF
LTC3892HUH-2#TRPBF
38922
38922
38922
32-Lead (5mm × 5mm) Plastic QFN
32-Lead (5mm × 5mm) Plastic QFN
32-Lead (5mm × 5mm) Plastic QFN
32-Lead (5mm × 5mm) Plastic QFN
LTC3892MPUH-2#TRPBF 38922
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ . Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
38921fc
3
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN1,2 = 5V, VEXTVCC = 0V, VDRVSET = 0V,
VPRG1 = FLOAT unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
V
V
Input Supply Operating Voltage Range
4.5
60
V
IN
Channel 1 Regulated Feedback
Voltage
(Note 4) ITH1 Voltage = 1.2V
FB1
0°C to 85°C,VPRG1 =FLOAT (LTC3892/LTC3892-2)or LTC3892-1
VPRG1 = FLOAT (LTC3892/LTC3892-2) or LTC3892-1
VPRG1 = 0V (LTC3892/LTC3892-2)
0.792
0.788
3.234
4.890
0.800
0.800
3.3
0.808
0.812
3.366
5.110
V
V
V
V
l
l
l
VPRG1 = INTV (LTC3892/LTC3892-2)
5.0
CC
V
Channel 2 Regulated Feedback
Voltage
(Note 4) ITH2 Voltage = 1.2V
0°C to 85°C
V
V
FB2
0.792
0.788
0.800
0.800
0.808
0.812
l
I
I
Channel 2 Feedback Current
Channel 1 Feedback Current
(Note 4)
–2
50
nA
FB2
(Note 4)
FB1
VPRG1 = FLOAT (LTC3892/LTC3892-2) or LTC3892-1
VPRG1 = 0V (LTC3892/LTC3892-2)
–0.002
4
4
0.05
6
6
µA
µA
µA
VPRG1 = INTV (LTC3892/LTC3892-2)
CC
V
V
Reference Voltage Line Regulation
Output Voltage Load Regulation
(Note 4) V = 4.5V to 60V
0.002
0.01
0.02
0.1
%/V
%
REFLNREG
IN
l
l
(Note 4) Measured in Servo Loop,
∆ITH Voltage = 1.2V to 0.7V
LOADREG
(Note 4) Measured in Servo Loop,
∆ITH Voltage = 1.2V to 2V
–0.01
2
–0.1
%
g
m1,2
Transconductance Amplifier g
Input DC Supply Current
(Note 4) ITH1,2 = 1.2V, Sink/Source 5µA
mmho
m
I
Q
(Note 5) V
= 0V
DRVSET
Pulse-Skipping or Forced Continuous RUN1 = 5V and RUN2 = 0V or
Mode (One Channel On) RUN2 = 5V and RUN1 = 0V,
= 0.83V (No Load)
1.6
mA
V
FB1,2
Pulse-Skipping or Forced Continuous RUN1,2 = 5V, V
Mode (Both Channels On)
= 0.83V (No Load)
2.8
29
mA
µA
FB1,2
l
Sleep Mode (One Channel On)
RUN1 = 5V and RUN2 = 0V or
RUN2 = 5V and RUN1 = 0V,
55
V
= 0.83V (No Load)
FB1,2
Sleep Mode (Both Channels On)
Shutdown
RUN1,2 = 5V, V
RUN1,2 = 0V
= 0.83V (No Load)
34
55
10
µA
µA
FB1,2
3.6
UVLO
Undervoltage Lockout
DRV Ramping Up
CC
l
l
DRVUV = 0V
4.0
7.5
4.2
7.8
V
V
DRVUV = INTV
CC
DRV Ramping Down
CC
l
l
DRVUV = 0V
3.6
6.4
3.8
6.7
4.0
7.0
V
V
DRVUV = INTV
CC
V
Feedback Overvoltage Protection
Measured at V
Relative to Regulated V
FB1,2
7
10
13
%
OVL1,2
FB1,2
(LTC3892/LTC3892-1)
+
I
I
+
–
SENSE Pin Current
1
1
µA
SENSE1,2
–
SENSE Pins Current
V
V
< V
> V
– 0.5V
+ 0.5V
µA
µA
SENSE1,2
OUT1,2
OUT1,2
INTVCC
INTVCC
700
99
DF
Maximum Duty Factor for TG
Soft-Start Charge Current
In Dropout, FREQ = 0V
= 0V
97.5
8
%
MAX(TG)
I
V
10
12
µA
TRACK/SS1,2
TRACK/SS1,2
38921fc
4
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN1,2 = 5V, VEXTVCC = 0V, VDRVSET = 0V,
VPRG1 = FLOAT unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
1.275
75
MAX UNITS
l
V
V
V
ON
RUN Pin On Threshold
V
, V Rising
RUN1 RUN2
1.22
1.33
V
RUN1,2
RUN1,2
Hyst RUN Pin Hysteresis
mV
Maximum Current Sense Threshold
V
= 0.7V, V
– = 3.3V
SENSE(MAX)
FB1,2
SENSE1,2
l
l
l
I
I
I
= FLOAT (LTC3892/LTC3892-2) or LTC3892-1
= 0V (LTC3892/LTC3892-2)
66
43
90
75
50
100
84
58
109
mV
mV
mV
LIM
LIM
LIM
= INTV (LTC3892/LTC3892-2)
CC
V
Matching Between V
SENSE2(MAX)
and
V
= 0.7V, V
– = 3.3V
SENSE(MATCH)
SENSE1(MAX)
FB1,2
SENSE1,2
l
l
l
V
I
I
I
= FLOAT (LTC3892/LTC3892-2) or LTC3892-1
= 0V (LTC3892/LTC3892-2)
–8
–8
–8
0
0
0
8
8
8
mV
mV
mV
LIM
LIM
LIM
= INTV (LTC3892/LTC3892-2)
CC
Gate Driver
TG1,2
Pull-Up On-Resistance
V
V
V
= INTV
= INTV
2.2
1.0
Ω
Ω
DRVSET
DRVSET
CC
Pull-Down On-Resistance
BG1,2
Pull-Up On-Resistance
Pull-Down On-Resistance
2.2
1.0
Ω
Ω
CC
BDSW1,2
BOOST to DRV Switch On-
= 0V, V
= INTV
CC
3.7
Ω
CC
SW
DRVSET
Resistance
TG Transition Time:
Rise Time
(Note 6) V
= INTV
DRVSET
= 3300pF
= 3300pF
CC
CC
TG1,2 t
TG1,2 t
C
C
25
15
ns
ns
r
f
LOAD
LOAD
Fall Time
BG Transition Time:
Rise Time
Fall Time
(Note 6) V
= INTV
DRVSET
= 3300pF
= 3300pF
BG1,2 t
BG1,2 t
C
C
25
15
ns
ns
r
f
LOAD
LOAD
TG/BG t
Top Gate Off to Bottom Gate On
Delay
C
C
= 3300pF Each Driver, V
= INTV
= INTV
55
50
80
ns
ns
ns
1D
LOAD
DRVSET
DRVSET
CC
CC
Synchronous Switch-On Delay Time
BG/TG t
Bottom Gate Off to Top Gate On
Delay
Top Switch-On Delay Time
= 3300pF Each Driver, V
1D
LOAD
t
TG Minimum On-Time
(Note 7) V
= INTV
DRVSET CC
ON(MIN)1,2
DRV Linear Regulator
CC
V
DRV Voltage from Internal V LDO V
= 0V
IN
DRVCC(INT)
CC
IN
EXTVCC
7V < V < 60V, DRVSET = 0V
5.8
9.6
6.0
10.0
6.2
10.4
V
V
11V < V < 60V, DRVSET = INTV
IN
CC
V
V
V
V
DRV Load Regulation from V
I
= 0mA to 50mA, V = 0V
EXTVCC
0.9
2.0
%
LDOREG(INT)
DRVCC(EXT)
LDOREG(EXT)
EXTVCC
CC
IN
CC
LDO
DRV Voltage from Internal EXTV
7V < V < 13V, DRVSET = 0V
EXTVCC
11V < V
5.8
9.6
6.0
10.0
6.2
10.4
V
V
CC
CC
LDO
< 13V, DRVSET = INTV
EXTVCC
CC
DRV Load Regulation from Internal I = 0mA to 50mA, V = 8.5V,
EXTVCC
0.7
2.0
%
CC
CC
V
EXTV LDO
= 0V
CC
DRVSET
EXTV LDO Switchover Voltage
EXTV Ramping Positive
CC
CC
DRVUV = 0V
4.5
7.4
4.7
7.7
4.9
8.0
V
V
DRVUV = INTV
CC
V
V
V
V
EXTV Hysteresis
250
5.0
7.0
9.0
mV
V
LDOHYS
CC
Programmable DRV
Programmable DRV
Programmable DRV
R
R
R
= 50kΩ, V
= 70kΩ, V
= 90kΩ, V
= 0V
DRVCC(50kΩ)
DRVCC(70kΩ)
DRVCC(90kΩ)
CC
CC
CC
DRVSET
DRVSET
DRVSET
EXTVCC
EXTVCC
EXTVCC
= 0V
= 0V
6.4
7.6
V
V
38921fc
5
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN1,2,3 = 5V, VEXTVCC = 0V, VDRVSET = 0V,
VPRG1 = FLOAT unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
Oscillator and Phase-Locked Loop
f
f
f
f
f
f
Programmable Frequency
Programmable Frequency
Programmable Frequency
Low Fixed Frequency
R
R
R
=25kΩ, PLLIN/MODE = DC Voltage
= 65kΩ, PLLIN/MODE = DC Voltage
= 105kΩ, PLLIN/MODE = DC Voltage
= 0V, PLLIN/MODE = DC Voltage
105
440
835
350
535
kHz
25kΩ
65kΩ
105kΩ
LOW
FREQ
FREQ
FREQ
FREQ
FREQ
375
505
kHz
kHz
kHz
kHz
kHz
V
V
320
485
75
380
585
850
High Fixed Frequency
= INTV , PLLIN/MODE = DC Voltage
CC
HIGH
SYNC
l
Synchronizable Frequency
PLLIN/MODE = External Clock
l
l
PLLIN V
PLLIN V
PLLIN/MODE Input High Level
PLLIN/MODE Input Low Level
PLLIN/MODE = External Clock
PLLIN/MODE = External Clock
2.5
V
V
IH
IL
0.5
PGOOD1 and PGOOD2 Outputs (LTC3892/LTC3892-2)
V
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
I
= 2mA
= 5V
0.2
0.4
1
V
PGL
PGOOD
I
V
V
µA
PGOOD
PGOOD
V
with Respect to Set Regulated Voltage
PG
FB
V
Ramping Negative
–13
7
–10
2.5
–7
13
%
%
FB
Hysteresis
V
with Respect to Set Regulated Voltage
FB
V
Ramping Positive
10
2.5
%
%
FB
Hysteresis
t
Delay for Reporting a Fault
35
µs
PG
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Ratings for extended periods may affect device reliability and lifetime.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 2: The LTC3892/LTC3892-1/LTC3892-2 is tested under pulsed load
conditions such that T ≈ T . The LTC3892E/LTC3892E-1/LTC3892E-2
J
A
is guaranteed to meet performance specifications from 0°C to 85°C.
Specifications over the –40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with
statistical process controls. The LTC3892I/LTC3892I-1/LTC3892I-2 is
guaranteed over the –40°C to 125°C operating junction temperature
range, the LTC3892H/LTC3892H-1/LTC3892H-2 is guaranteed over
the –40°C to 150°C operating junction temperature range, and the
LTC3892MP/LTC3892MP-1/LTC3892MP-2 is tested and guaranteed over
the –55°C to 150°C operating junction temperature range. High junction
temperatures degrade operating lifetimes; operating lifetime is derated
for junction temperatures greater than 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors. The junction
Note 4: The LTC3892/LTC3892-1/LTC3892-2 is tested in a feedback loop
that servos V
to a specified voltage and measures the resultant
ITH1,2
V . The specification at 85°C is not tested in production and is assured
FB1,2
by design, characterization and correlation to production testing at other
temperatures (125°C for the LTC3892E/LTC3892E-1/LTC3892E-2 and
LTC3892I/LTC3892I-1/LTC3892I-2, 150°C for the LTC3892H/LTC3892H-1/
LTC3892H-2 and LTC3892MP/LTC3892MP-1/LTC3892MP-2). For
the LTC3892I/LTC3892I-1/LTC3892I-2 and LTC3892H/LTC3892H-1/
LTC3892H-2, the specification at 0°C is not tested in production and
is assured by design, characterization and correlation to production
testing at –40°C. For the LTC3892MP/LTC3892MP-1/LTC3892MP-2, the
specification at 0°C is not tested in production and is assured by design,
characterization and correlation to production testing at –55°C.
temperature (T , in °C) is calculated from the ambient temperature
J
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications information.
(T , in °C) and power dissipation (P , in Watts) according to the formula:
A
D
T = T + (P • θ )
JA
J
A
D
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
where θ = 44°C/W for the QFN package and where θ = 30°C/W for the
TSSOP package.
times are measured using 50% levels
Note 7: The minimum on-time condition is specified for an inductor
JA
JA
peak-to-peak ripple current >40% of I
(See Minimum On-Time
MAX
Considerations in the Applications Information section)
Note 8: Do not apply a voltage or current source to these pins. They must be
connected to capacitive loads only, otherwise permanent damage may occur.
38921fc
6
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Load Current
Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
10k
1k
BURST EFFICIENCY
FCM LOSS
100
10
V
V
V
V
V
V
= 10V
= 20V
= 30V
= 40V
= 50V
= 60V
IN
IN
IN
IN
IN
IN
V
= 12V
= 5V
PULSE-
IN
SKIPPING
V
OUT
LOSS
FIGURE 11 CIRCUIT
BURST LOSS
1
FIGURE 11 CIRCUIT
= 5V
PULSE-SKIPPING
EFFICIENCY
V
OUT
Burst Mode OPERATION
FCM EFFICIENCY
0.1
0.0001 0.001
0.01
0.1
1
10
0.0001 0.001
0.01
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
3892 G02
3892 G01
Load Step
Burst Mode Operation
Efficiency vs Input Voltage
96
95
94
93
92
91
90
89
88
87
86
V
OUT
100mV/DIV
AC COUPLED
DRVSET=INTV
CC
I
L
DRVSET=0V
2A/DIV
FIGURE 11 CIRCUIT
3892 G04
50µs/DIV
V
= 5V
OUT
LOAD
I
=8A
V
V
= 12V
OUT
IN
= 5V
0
5
10 15 20 25 30 35 40 45 50 55 60
FIGURE 13 CIRCUIT
INPUT VOLTAGE (V)
3892 G03
Load Step
Pulse-Skipping Mode
Load Step
Forced Continuous Mode
V
V
OUT
OUT
100mV/DIV
100mV/DIV
AC COUPLED
AC COUPLED
I
I
L
2A/DIV
L
2A/DIV
3892 G05
3892 G06
50µs/DIV
50µs/DIV
V
V
= 12V
OUT
FIGURE 13 CIRCUIT
V
V
= 12V
OUT
FIGURE 13 CIRCUIT
IN
IN
= 5V
= 5V
38921fc
7
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
TYPICAL PERFORMANCE CHARACTERISTICS
Inductor Current at Light Load
Soft Start-Up
RUN1, 2
5V/DIV
FORCED
CONTINUOUS
MODE
V
OUT2
2V/DIV
Burst Mode
OPERATION
1A/DIV
V
OUT1
2V/DIV
PULSE
SKIPPING
MODE
3892 G07
3892 G08
2µs/DIV
2ms/DIV
FIGURE 13 CIRCUIT
V
V
= 12V
IN
= 5V
OUT
LOAD
I
= 1mA
FIGURE 13 CIRCUIT
Regulated Feedback Voltage vs
Temperature
DRVCC and EXTVCC
vs Load Current
808
806
804
802
800
798
796
794
792
6.4
6.2
6
EXTV = 0V
CC
5.8
5.6
EXTV = 8.5V
CC
5.4
5.2
5
4.8
EXTV = 5V
CC
4.6
4.4
V
= 12V
IN
4.2
4
DRVSET = GND
25 50
LOAD CURRENT (mA)
-75 -50 -25
0
25 50 75 100 125 150
0
75
100
125
150
TEMPERATURE (°C)
3892 G10
3892 G09
EXTVCC Switchover and DRVCC
Voltages vs Temperature
Undervoltage Lockout
Threshold vs Temperature
11
10
9
8
7.5
7
RISING
DRV (DRVSET = INTV
)
CC
CC
DRVUV = INTV
CC
6.5
6
FALLING
DRVUV = INTV
CC
EXTV RISING
CC
8
5.5
5
EXTV FALLING
CC
7
DRV (DRVSET = 0V)
CC
4.5
4
DRVUV = GND
6
RISING
DRVUV = GND
EXTV RISING
CC
5
FALLING
3.5
3
EXTV FALLING
CC
4
–75 –50 –25
0
25 50 75 100 125 150
–75 –50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
3892 G11
3892 G12
38921fc
8
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
TYPICAL PERFORMANCE CHARACTERISTICS
SENSE Pins Total Input Current
vs VSENSE Voltage
SENSE– Pin Input Bias Current vs
Temperature
800
700
600
500
400
300
200
100
0
900
800
700
600
500
400
300
200
100
0
V
> INTV + 0.5V
CC
OUT
V
< INTV – 0.5V
CC
OUT
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65
COMMON MODE VOLTAGE (V)
–75 –50 –25
25 50 75 100 125 150
V
TEMPERATURE (°C)
SENSE
3892 G13
3892 G14
Maximum Current Sense
Threshold vs Duty Cycle
Foldback Current Limit
120
110
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
LTC3892-2
LTC3892/LTC3892-1
I
I
I
= INTV
= FLOAT
= GND
I
I
I
= INTV
CC
= FLOAT
= GND
LIM
LIM
LIM
CC
LIM
LIM
LIM
0
100 200 300 400 500 600 700 800
0
10 20 30 40 50 60 70 80 90 100
FEEDBACK VOLTAGE (mV)
DUTY CYCLE (%)
3892 G15
3892 G16
Maximum Current Sense
Threshold vs ITH Voltage
Shutdown (RUN) Threshold
vs Temperature
100
80
1.4
1.35
1.3
5% DUTY CYCLE
PULSE-SKIPPING
60
RISING
Burst Mode
OPERATION
1.25
1.2
40
FALLING
20
1.15
1.1
I
I
I
= GND
LIM
LIM
LIM
0
= FLOAT
= INTV
CC
–20
–40
1.05
FORCED CONTINUOUS MODE
1
0
0.2 0.4 0.6 0.8
(V)
1
1.2 1.4
–75 –50 –25
0
25 50 75 100 125 150
V
TEMPERATURE (°C)
ITH
3892 G17
3892 G18
38921fc
9
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
TYPICAL PERFORMANCE CHARACTERISTICS
DRVCC Line Regulation
Shutdown Current vs Temperature
11
10
9
8
7
6
5
4
3
2
1
0
V
= 12V
IN
DRVSET = INTV
CC
8
7
DRVSET = GND
6
5
0
5
10 15 20 25 30 35 40 45 50 55 60 65
–75 –50 –25
0
25 50 75 100 125 150
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3892 G19
3892 G20
Shutdown Current vs
Input Voltage
Quiescent Current vs Temperature
14
12
10
8
80
70
60
50
40
30
20
10
0
V
=12V
IN
ONE CHANNEL ON
Burst Mode OPERATION
DRVSET = 70kΩ
DRVSET=INTV
CC
6
DRVSET=GND
4
2
0
0
10
20
30
40
50
60
70
–75 –50 –25
0
25 50 75 100 125 150
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3892 G21
3899 G22
Oscillator Frequency vs
Temperature
TRACK/SS Pull-Up Current vs
Temperature
600
550
500
450
400
350
300
12
11.5
11
FREQ = INTV
CC
10.5
10
9.5
9
FREQ = GND
8.5
8
–75 –50 –25
0
25 50 75 100 125 150
-75 -50 -25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
3892 G24
3892 G23
38921fc
10
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
PIN FUNCTIONS (QFN (LTC3892 and LTC3892-2)/TSSOP (LTC3892-1))
FREQ (Pin 1/ Pin 5): The frequency control pin for the
internal VCO. Connecting this pin to GND forces the VCO
to a fixed low frequency of 350kHz. Connecting this pin
ILIM(Pin8/NA):CurrentComparatorSenseVoltageRange
Input. Tying this pin to GND or INTV or floating it sets
CC
the maximum current sense threshold (for both channels)
to one of three different levels (50mV, 100mV, or 75mV
respectively). This pin is available on the LTC3892 and
LTC3892-2,butnotontheLTC3892-1.FortheLTC3892-1,
the maximum current sense threshold is 75mV.
to INTV forces the VCO to a fixed high frequency of
CC
535kHz.Otherfrequenciesbetween50kHzand900kHzcan
be programmed using a resistor between FREQ and GND.
The resistor and an internal 20µA source current create a
voltage used by the internal oscillator to set the frequency.
V
(Pin11/Pin12):Thispinreceivestheremotelysensed
FB2
PLLIN/MODE (Pin 2/Pin 6): External Synchronization Input
toPhaseDetectorandForcedContinuousModeInput.When
anexternalclockisappliedtothispin,thephase-lockedloop
will force the rising TG1 signal to be synchronized with the
risingedgeoftheexternalclock,andtheregulatorswilloper-
ate in forced continuous mode on the LTC3892/LTC3892-1
and in pulse-skipping mode on the LTC3892-2. When not
synchronizingtoanexternalclock, this input, whichactson
bothcontrollers,determineshowtheLTC3892/LTC3892-1/
LTC3892-2operatesatlightloads.Pullingthispintoground
selects Burst Mode operation. An internal 100k resistor to
ground also invokes Burst Mode operation when the pin is
feedback voltage for channel 2 from an external resistor
divider across the output.
DRVUV (Pin13/Pin 14): Determines the higher or lower
DRV UVLO and EXTV switchover thresholds, as listed
CC
CC
on the Electrical Characteristics table. Connecting DRVUV
toGNDchoosesthelowerthresholdswhereastyingDRVUV
to INTV chooses the higher thresholds.
CC
DRVSET (Pin 14/Pin 15): Sets the regulated output volt-
age of the DRV LDO regulator. Connecting this pin to
CC
GND sets DRV to 6V whereas connecting it to INTV
CC
CC
sets DRV to 10V. Voltages between 5V and 10V can be
CC
programmed by placing a resistor (50k to 100k) between
the DRVSET pin and GND.
floated. Tying this pin to INTV forces continuous inductor
CC
current operation. Tying this pin to a voltage greater than
1.1V and less than INTV – 1.3V selects pulse-skipping
CC
DRV (Pin 20/Pin 21): Output of the Internal or External
CC
operation. This can be done by connecting a 100k resistor
Low Dropout (LDO) Regulator. The gate drivers are pow-
from this pin to INTV .
CC
ered from this voltage source. The DRV voltage is set
CC
by the DRVSET pin. Must be decoupled to ground with a
PGOOD1, PGOOD2 (Pins 3, 4/NA): Open-Drain Logic
minimum of 4.7µF ceramic or other low ESR capacitor.
Output. PGOOD1,2 is pulled to ground when the voltage
Do not use the DRV pin for any other purpose.
on the respective V
pin is not within 10ꢀ of its
CC
FB1,2
set point. These pins are available on the LTC3892 and
LTC3892-2, but not on the LTC3892-1.
EXTV (Pin 21/Pin 22): External Power Input to an Inter-
CC
nal LDO Connected to DRV . This LDO supplies DRV
CC
CC
power, bypassing the internal LDO powered from V
INTV (Pin 5/Pin 7): Output of the Internal 5V Low Drop-
IN
CC
whenever EXTV is higher than its switchover threshold
out Regulator. The low voltage analog and digital circuits
are powered from this voltage source. A low ESR 0.1µF
ceramic bypass capacitor should be connected between
INTV and GND, as close as possible to the IC. INTV
CC
(4.7V or 7.7V depending on the DRVUV pin). See EXTV
CC
ConnectionintheApplicationsInformationsection.Donot
float or exceed 14V on this pin. Do not connect EXTV
CC
CC
CC
to a voltage greater than V . Connect to GND if not used.
should not be used to power or bias any external circuitry
other than to configure the FREQ, PLLIN/MODE, DRVSET,
DRVUV and VPRG1 pins.
IN
V (Pin 22/Pin 23): Main Supply Pin. A bypass capacitor
IN
should be tied between this pin and the GND pin.
RUN1, RUN2 (Pins 6, 7/Pins 8, 9): Run Control Inputs for
EachController.Forcinganyofthesepinsbelow1.2Vshuts
downthatcontroller.Forcingbothofthesepinsbelow0.7V
shuts down the entire LTC3892/LTC3892-1/LTC3892-2,
reducing quiescent current to approximately 3.6µA.
BG1, BG2 (Pins 23, 19/Pins 24, 20): High Current Gate
Drives for Bottom N-Channel MOSFETs. Voltage swing at
these pins is from ground to DRV .
CC
38921fc
11
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
PIN FUNCTIONS (QFN (LTC3892 and LTC3892-2)/TSSOP (LTC3892-1))
BOOST1,BOOST2(Pins24,18/Pins25,19):Bootstrapped
Supplies to the Topside Floating Drivers. Capacitors are
connected between the BOOST and SW pins. Voltage
swingatBOOST1andBOOST2pinsisfromapproximately
V
to 0.8V. This pin is available on the LTC3892 and
FB1
LTC3892-2, but not on the LTC3892-1.
ITH1, ITH2 (Pins 29, 12/Pins 1, 13): Error Amplifier
Outputs and Switching Regulator Compensation Points.
Each associated channel’s current comparator trip point
increases with this control voltage.
DRV to (V
+ DRV ).
CC
IN1,2
CC
SW1, SW2 (Pins 25, 17/Pins 26, 18): Switch Node Con-
nections to Inductors.
V
(Pin 30/Pin 2): For the LTC3892-1, this pin receives
FB1
TG1, TG2 (Pins 26, 16/Pins 27, 17): High Current Gate
DrivesforTopN-ChannelMOSFETs. Thesearetheoutputs
the remotely sensed feedback voltage for channel 1 from
an external resistor divider across the output.
of floating drivers with a voltage swing equal to DRV
superimposed on the switch node voltage SW.
CC
FortheLTC3892andLTC3892-2, iftheVPRG1pinisfloat-
ing, the V pin receives the remotely sensed feedback
FB1
TRACK/SS1, TRACK/SS2 (Pins 27, 15/Pins 28, 16):
voltage for channel 1 from an external resistor divider
External Tracking and Soft-Start Input. The LTC3892/
across the output. If VPRG1 is tied to GND or INTV ,
CC
–
LTC3892-1/LTC3892-2 regulates the negative input (EA )
the V pin receives the remotely sensed output voltage
FB1
of the error amplifier to the smaller of 0.8V or the voltage
on the TRACK/SS pin. An internal 10µA pull-up current
source is connected to this pin. A capacitor to ground at
this pin sets the ramp time at start-up to the final regulated
output voltage. Alternatively, a resistor divider on another
supplyconnectedtotheTRACK/SSpinallowstheLTC3892/
LTC3892-1/LTC3892-2 output voltage to track the other
supply during start-up. The TRACK/SS pin is pulled low
in shutdown or in undervoltage lockout.
directly.
+
+
SENSE1 , SENSE2 (Pins 31, 10/Pins 3, 11): The (+)
Input to the Differential Current Comparators. The ITH pin
voltage and controlled offsets between the SENSE and
SENSE pins in conjunction with R
trip threshold.
–
+
set the current
SENSE
–
–
SENSE1 , SENSE2 (Pins 32, 9/Pins 4, 10): The (–) Input
–
totheDifferentialCurrentComparators.WhenSENSE1,2 is
–
greater than INTV , then SENSE1,2 pin supplies current
CC
VPRG1(Pin28/NA):Channel1OutputVoltageControlPin.
This pin sets channel 1 to adjustable output mode using
external feedback resistors or fixed 3.3V/5V output mode.
Floatingthispinallowstheoutputtobeprogrammedfrom
0.8V to 60V with an external resistor divider, regulating
to the current comparator.
GND (Exposed Pad Pin 33/Exposed Pad Pin 29): Ground.
The exposed pad must be soldered to the PCB for rated
electrical and thermal performance.
Table 1. Summary of the Differences Between the LTC3892, LTC3892-1 and LTC3892-2
LTC3892
LTC3892-1
No; fixed 75mV
LTC3892-2
ILIM pin for selectable current sense
voltage?
Yes; 50mV, 75mV, or 100mV
Yes; 50mV, 75mV, or 100mV
VPRG1 pin for fixed or adjustable V
?
Yes; fixed 3.3V or 5V (with internal No; only adjustable with external Yes; fixed 3.3V or 5V (with internal
OUT1
resistor divider) or adjustable with
external resistor divider
resistor divider
No PGOOD function
Yes; BG forced on
resistor divider) or adjustable with
external resistor divider
Independent PGOOD output for each
channel?
Yes; PGOOD1 and PGOOD2
Yes; PGOOD1 and PGOOD2
No; BG not forced on
No
Output overvoltage protection bottom gate
"crowbar?"
Yes; BG forced on
Current foldback during overcurrent events?
Yes
Yes
Light load operation when synchronized to
external clock using PLLIN/MODE
Forced Continuous
Forced Continuous
Pulse-skipping
(Discontinuous)
Package
32-Pin 5mm x 5mm QFN
(UH32)
28-Lead TSSOP
(FE28)
32-Pin 5mm x 5mm QFN
(UH32)
38921fc
12
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
FUNCTIONAL DIAGRAMS
CHANNELS 1 AND 2
DRV
CC
V
IN1,2
20µA
BOOST1,2
TG1,2
FREQ
CLK2
CLK1
VCO
C
B
TOP
BOT
DROPOUT
DET
C
IN
BOT
SW1,2
TOP ON
DRV
CC
C
S
R
Q
OUT
BG1,2
GND
PFD
V
OUT1,2
Q
SWITCHING
LOGIC
SHDN
L
R
SENSE
SYNC
DET
PLLIN/MODE
0.425V
+
–
SLEEP
100k
I
I
R
–
+
CMP
+
–
I
LIM
+
+
–
3mV
–
CURRENT
LIMIT
+
SENSE1,2
2.8V
+
–
PGOOD1
–
0.88V
EA1
0.65V
SENSE1,2
–
–
R
B
R1
V
FB1,2
+
–
SLOPE COMP
–
+
–
0.80V
EA
+
R2
R
A
0.72V
0.88V
TRACK/SS
+
–
PGOOD2
+
–
OV
C
0.88V
C
3.5V
ITH1,2
EA2
+
–
150nA
R
SHDN
RST
C
C
C2
0.72V
FOLDBACK
10µA
2(V
FB
)
TRACK/SS1,2
C
SS
LTC3892 AND LTC3892-1 SHDN
RUN1,2
VPRG1
LTC3892 AND LTC3892-2
NOT ON LTC3892-1
2.00V
1.20V
20µA
DRVSET
VPRG1
V
R1
0
R2
OUT1
DRVUV
FLOAT ADJUSTABLE
∞
GND
INTV
3.3V FIXED 625k 200k
5V FIXED 1.05M 200k
EXTV
CC
CC
DRV LDO/UVLO
CC
CONTROL
VPRG1 AFFECTS CHANNEL 1 ONLY,
IS ALWAYS ADJUSTABLE (R1 = 0, R2 = ∞)
V
IN
V
OUT2
LTC3892-1 (R1 = 0, R2 = ∞)
–
+
–
+
–
+
EN
EN
4.7V/
7.7V
DRV
CC
4R
INTV
CC
LDO
R
38921 FD
INTV
CC
38921fc
13
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
OPERATION (Refer to the Functional Diagrams)
If the input voltage decreases to a voltage close to its
output, the loop may enter dropout and attempt to turn
on the top MOSFET continuously. The dropout detector
detects this and forces the top MOSFET off for about one-
Main Control Loop
The LTC3892/LTC3892-1/LTC3892-2 uses a constant
frequency, current mode step-down architecture. The two
controller channels operate 180° out of phase with each
other. During normal operation, the external top MOSFET
is turned on when the clock for that channel sets the RS
latch, and is turned off when the main current compara-
twelfth of the clock period every tenth cycle to allow C to
B
recharge, resulting in about 99ꢀ duty cycle.
TheINTV supplypowersmostoftheotherinternalcircuits
CC
in the LTC3892/LTC3892-1/LTC3892-2. The INTV LDO
tor, I
, resets the RS latch. The peak inductor current
CMP
CC
CMP
at which I
regulates to a fixed value of 5V and its power is derived
trips and resets the latch is controlled by
from the DRV supply.
the voltage on the ITH pin, which is the output of the er-
CC
ror amplifier, EA. The error amplifier compares the output
Shutdown and Start-Up (RUN, TRACK/SS Pins)
voltage feedback signal at the V pin (which is generated
FB
with an external resistor divider connected across the
The two channels of the LTC3892/LTC3892-1/LTC3892-2
can be independently shut down using the RUN1 and
RUN2 pins. Pulling a RUN pin below 1.2V shuts down
the main control loop for that channel. Pulling both pins
below 0.7V disables both controllers and most internal
output voltage, V , to ground) to the internal 0.800V
OUT
reference voltage. When the load current increases, it
causes a slight decrease in V relative to the reference,
FB
which causes the EA to increase the ITH voltage until the
average inductor current matches the new load current.
circuits, including the DRV and INTV LDOs. In this
CC
CC
state, the LTC3892/LTC3892-1/LTC3892-2 draws only
After the top MOSFET is turned off each cycle, the bottom
MOSFETisturnedonuntileithertheinductorcurrentstarts
3.6μA of quiescent current.
to reverse, as indicated by the current comparator I , or
R
Releasing a RUN pin allows a small 150nA internal current
to pull up the pin to enable that controller. Each RUN pin
maybeexternallypulledupordrivendirectlybylogic.Each
RUN pin can tolerate up to 65V (absolute maximum), so it
the beginning of the next clock cycle.
DRV /EXTV /INTV Power
CC
CC
CC
can be conveniently tied to V in always-on applications
Power for the top and bottom MOSFET drivers is derived
fromtheDRV pin. TheDRV supplyvoltagecanbepro-
IN
where one or both controllers are enabled continuously
CC
CC
and never shut down.
grammed from 5V to 10V through control of the DRVSET
pin. When the EXTV pin is tied to a voltage below its
CC
The start-up of each controller’s output voltage V
is
OUT
switchovervoltage(4.7Vor7.7VdependingontheDRVSET
controlled by the voltage on the TRACK/SS pin (TRACK/
SS1 for channel 1, TRACK/SS2 for channel 2). When the
voltage on the TRACK/SS pin is less than the 0.8V internal
reference, the LTC3892/LTC3892-1/LTC3892-2 regulates
voltage), the V LDO (low dropout linear regulator) sup-
IN
plies power from V to DRV . If EXTV is taken above
IN
CC
CC
its switchover voltage, the V LDO is turned off and an
IN
EXTV LDO is turned on. Once enabled, the EXTV LDO
CC
CC
the V voltage to the TRACK/SS pin voltage instead of the
FB
supplies power from EXTV to DRV . Using the EXTV
CC
CC
CC
0.8V reference. This allows the TRACK/SS pin to be used
toprogramasoft-startbyconnectinganexternalcapacitor
from the TRACK/SS pin to GND. An internal 10μA pull-up
current charges this capacitor creating a voltage ramp on
the TRACK/SS pin. As the TRACK/SS voltage rises linearly
from 0V to 0.8V (and beyond up to about 4V), the output
pin allows the DRV power to be derived from a high
CC
efficiency external source such as one of the LTC3892/
LTC3892-1/LTC3892-2 switching regulator outputs.
Each top MOSFET driver is biased from the floating boot-
strapcapacitor,C ,whichnormallyrechargesduringeach
B
voltage V
rises smoothly from zero to its final value.
cycle through an internal switch whenever SW goes low.
OUT
38921fc
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OPERATION (Refer to the Functional Diagrams)
Alternatively the TRACK/SS pins can be used to make the
pin is reconnected to the output of the EA, the sleep signal
goes low, and the controller resumes normal operation
by turning on the top external MOSFET on the next cycle
of the internal oscillator.
start-up of V
to track that of another supply. Typically,
OUT
this requires connecting to the TRACK/SS pin an external
resistor divider from the other supply to ground (see
Applications Information section).
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Forced Continuous Mode)
(PLLIN/MODE Pin)
current comparator (I ) turns off the bottom external
R
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus,
the controller operates discontinuously.
The LTC3892/LTC3892-1/LTC3892-2 can be enabled to
enterhighefficiencyBurstModeoperation,pulse-skipping
mode, or forced continuous conduction mode at low load
currents. To select Burst Mode operation, tie the PLLIN/
MODE pin to GND. To select forced continuous opera-
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than in
Burst Mode operation. However, continuous operation
has the advantage of lower output voltage ripple and less
interferencetoaudiocircuitry.Inforcedcontinuousmode,
the output ripple is independent of load current.
tion, tie the PLLIN/MODE pin to INTV . To select pulse-
CC
skipping mode, tie the PLLIN/MODE pin to a DC voltage
greater than 1.1V and less than INTV – 1.3V. This can
CC
be done by connecting a 100kΩ resistor between PLLIN/
MODE and INTV .
CC
When a controller is enabled for Burst Mode operation,
the minimum peak current in the inductor is set to ap-
proximately 25ꢀ of the maximum sense voltage even
when the voltage on the ITH pin indicates a lower value.
If the average inductor current is higher than the load cur-
rent, the error amplifier, EA, will decrease the voltage on
the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off. The ITH pin is
then disconnected from the output of the EA and parked
at 0.450V.
WhenthePLLIN/MODEpinisconnectedforpulse-skipping
mode, the LTC3892/LTC3892-1/LTC3892-2 operates in
PWM pulse-skipping mode at light loads. In this mode,
constant frequency operation is maintained down to ap-
proximately 1ꢀ of designed maximum output current.
At very light loads, the current comparator, I
, may
CMP
remaintrippedforseveralcyclesandforcetheexternaltop
MOSFET to stay off for the same number of cycles (i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuousoperation, exhibitslowoutputrippleaswellas
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
efficiency than forced continuous mode, but not nearly as
high as Burst Mode operation.
In sleep mode, much of the internal circuitry is turned
off, reducing the quiescent current that the LTC3892/
LTC3892-1/LTC3892-2 draws. If one channel is in sleep
mode and the other channel is shut down, the LTC3892/
LTC3892-1/LTC3892-2 draws only 29μA of quiescent
current (with DRVSET = 0V). If both channels are in sleep
mode, it draws only 34μA of quiescent current. In sleep
mode, theloadcurrentissuppliedbytheoutputcapacitor.
As the output voltage decreases, the EA’s output begins
to rise. When the output voltage drops enough, the ITH
When an external clock is connected to the PLLIN/MODE
pintosynchronizetheinternaloscillator(seetheFrequency
Selection and Phase-Locked Loop section), the LTC3892/
LTC3892-1 operate in forced continuous mode while the
LTC3892-2operatesindiscontinuouspulseskippingmode.
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LTC3892-1/LTC3892-2
OPERATION (Refer to the Functional Diagrams)
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
and 850kHz. In other words, the LTC3892/LTC3892-1/
LTC3892-2’sPLLisguaranteedtolocktoanexternalclock
source whose frequency is between 75kHz and 850kHz.
Theselectionofswitchingfrequencyisatrade-offbetween
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.1V (falling). It is recommended
that the external clock source swing from ground (0V) to
at least 2.5V.
The switching frequency of the LTC3892/LTC3892-1/
LTC3892-2’s controllers can be selected using the FREQ
pin.
When an external clock is connected to the PLLIN/MODE
pin to synchronize the internal oscillator, the LTC3892/
LTC3892-1 operate in forced continuous mode while the
LTC3892-2operatesindiscontinuouspulseskippingmode.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to GND, tied to
Output Overvoltage Protection (LTC3892/LTC3892-1,
Not On LTC3892-2)
INTV orprogrammedthroughanexternalresistor. Tying
CC
FREQ to GND selects 350kHz while tying FREQ to INTV
CC
Each channel has an overvoltage comparator that guards
against transient overshoots as well as other more seri-
ous conditions that may overvoltage the output. When
selects535kHz. PlacingaresistorbetweenFREQandGND
allows the frequency to be programmed between 50kHz
and 900kHz, as shown in Figure 9.
the V
pin rises by more than 10ꢀ above its regula-
FB1,2
A phase-locked loop (PLL) is available on the LTC3892/
LTC3892-1/LTC3892-2 to synchronize the internal oscil-
lator to an external clock source that is connected to the
PLLIN/MODEpin.TheLTC3892/LTC3892-1/LTC3892-2’s
phase detector adjusts the voltage (through an internal
lowpass filter) of the VCO input to align the turn-on of
controller 1’s external top MOSFET to the rising edge of
the synchronizing signal. Thus, the turn-on of controller
2’s external top MOSFET is 180° out of phase to the rising
edge of the external clock source.
tion point of 0.800V, the top MOSFET is turned off and
the bottom MOSFET is turned on until the overvoltage
condition is cleared.
Foldback Current (LTC3892/LTC3892-1, Not On
LTC3892-2)
When the output voltage falls to less than 70ꢀ of its
nominal level, foldback current limiting is activated, pro-
gressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
The VCO input voltage is prebiased to the operating fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG1. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
interval (as long as the V
voltage is keeping up with
FB1,2
the TRACK/SS1,2 voltage).
Current foldback limiting is intended to limit power
dissipation during overcurrent and short-circuit fault
conditions. Note that while the current foldback func-
tion does not exist on the LTC3892-2 version, it is still
inherently protected during these fault conditions. The
LTC3892/LTC3892-1/LTC3892-2’s peak current mode
control architecture constantly monitors the inductor
currentandpreventscurrentrunawayunderallconditions.
The typical capture range of the LTC3892/LTC3892-1/
LTC3892-2’s phase-locked loop is from approximately
55kHz to 1MHz, with a guarantee to be between 75kHz
38921fc
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APPLICATIONS INFORMATION
TO SENSE FILTER
The Typical Application on the first page is a basic
LTC3892/LTC3892-1/LTC3892-2 application circuit.
LTC3892/LTC3892-1/LTC3892-2 can be configured to
use either DCR (inductor resistance) sensing or low value
resistor sensing. The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
NEXT TO THE CONTROLLER
C
OUT
CURRENT FLOW
38921 F03
INDUCTOR OR R
SENSE
Figure 1. Sense Lines Placement with Inductor or Sense Resistor
placed close to the switching node, to prevent noise from
coupling into sensitive small-signal nodes.
Low Value Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
R
(if R
is used) and inductor value. Next, the
SENSE
SENSE
in Figure 2a. R
output current.
is chosen based on the required
SENSE
powerMOSFETsandSchottkydiodesareselected. Finally,
input and output capacitors are selected.
Each controller’s current comparator has a maximum
threshold V . For the LTC3892-1, V
+
–
SENSE and SENSE Pins
SENSE(MAX)
SENSE(MAX)
+
–
is fixed at 75mV, while for the LTC3892 and LTC3892-2,
The SENSE and SENSE pins are the inputs to the cur-
rent comparators. The common mode voltage range on
these pins is 0V to 65V (absolute maximum), enabling
the LTC3892/LTC3892-1/LTC3892-2 to regulate output
voltages up to a nominal 60V (allowing margin for toler-
V
is either 50mV, 75mV or 100mV, as deter-
SENSE(MAX)
minedbythestateoftheILIMpin. Thecurrentcomparator
threshold voltage sets the peak of the inductor current,
yielding a maximum average output current, I
, equal
MAX
+
to the peak value less half the peak-to-peak ripple current,
ances and transients). The SENSE pin is high impedance
∆I .Tocalculatethesenseresistorvalue,usetheequation:
over the full common mode range, drawing at most 1μA.
This high impedance allows the current comparators to
be used in inductor DCR sensing. The impedance of the
L
VSENSE(MAX)
RSENSE
=
∆IL
–
SENSE pin changes depending on the common mode
IMAX +
2
–
voltage. When SENSE is less than INTV – 0.5V, a
CC
small current of less than 1μA flows out of the pin. When
When using a controller in very low dropout conditions,
the maximum output current level will be reduced due to
theinternalcompensationrequiredtomeetstabilitycriteria
for buck regulators operating at greater than 50ꢀ duty
factor. A curve is provided in the Typical Performance
Characteristics section to estimate this reduction in peak
inductorcurrentdependingupontheoperatingdutyfactor.
–
SENSE isaboveINTV +0.5V,ahighercurrent(≈700μA)
CC
flows into the pin. Between INTV – 0.5V and INTV
+
CC
CC
0.5V, the current transitions from the smaller current to
the higher current.
Filter components mutual to the sense lines should be
placed close to the LTC3892/LTC3892-1/LTC3892-2, and
the sense lines should run close together to a Kelvin con-
nection underneath the current sense element (shown in
Figure 1). Sensing current elsewhere can effectively add
parasitic inductance and capacitance to the current sense
element, degrading the information at the sense terminals
and making the programmed current limit unpredictable.
If DCR sensing is used (Figure 2b), resistor R1 should be
Inductor DCR Sensing
For applications requiring the highest possible efficiency
athighloadcurrents,theLTC3892/LTC3892-1/LTC3892-2
is capable of sensing the voltage drop across the induc-
tor DCR, as shown in Figure 2b. The DCR of the inductor
represents the small amount of DC winding resistance of
38921fc
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APPLICATIONS INFORMATION
V
IN1,2
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
BOOST
LTC3892/
LTC3892-1/
LTC3892-2
TG
SW
BG
R
SENSE
Using the inductor ripple current value from the Inductor
ValueCalculationsection,thetargetsenseresistorvalueis:
V
OUT1,2
VSENSE(MAX)
RSENSE(EQUIV)
=
+
SENSE1,2
∆IL
IMAX
+
CAP
PLACED NEAR SENSE PINS
2
–
SENSE1,2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
GND
38921 F04a
minimum value for V
teristics table.
in the Electrical Charac-
SENSE(MAX)
(2a) Using a Resistor to Sense Current
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
V
V
IN1,2
BOOST
INDUCTOR
DCR
LTC3892/
LTC3892-1/
LTC3892-2
TG
SW
BG
L
0.4ꢀ/°C. A conservative value for T
is 100°C.
L(MAX)
OUT1,2
To scale the maximum inductor DCR to the desired sense
resistor value (R ), use the divider ratio:
D
R1
R2
+
SENSE1,2
RSENSE(EQUIV)
C1*
RD =
–
DCRMAX atTL(MAX)
SENSE1,2
GND
*PLACE C1 NEAR SENSE PINS
C1isusuallyselectedtobeintherangeof0.1μFto0.47μF.
ThisforcesR1||R2toaround2k, reducingerrorthatmight
(R1||R2) • C1 = L/DCR
= DCR(R2/(R1+R2))
38921 F04b
R
SENSE(EQ)
+
have been caused by the SENSE pin’s 1μA current.
(2b) Using the Inductor DCR to Sense Current
Figure 2. Current Sensing Methods
The equivalent resistance R1||R2 is scaled to the room
temperature inductance and maximum DCR:
the copper, which can be less than 1mΩ for today’s low
value, high current inductors. In a high current application
requiring such an inductor, power loss through a sense
resistor would cost several points of efficiency compared
to inductor DCR sensing.
L
R1R2=
(DCR at 20°C)•C1
The sense resistor values are:
R1R2
RD
R1•RD
1−RD
R1=
; R2=
If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
V
IN(MAX) − VOUT •V
(
)
OUT
PLOSS R1=
R1
38921fc
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APPLICATIONS INFORMATION
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor,
due to the extra switching losses incurred through R1.
However,DCRsensingeliminatesasenseresistor,reduces
conduction losses and provides higher efficiency at heavy
loads.Peakefficiencyisaboutthesamewitheithermethod.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. Core loss is independent of core size for a
fixedinductorvalue,butitisverydependentoninductance
value selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET switching and gate charge losses. In addition to
this basic trade-off, the effect of inductor value on ripple
currentandlowcurrentoperationmustalsobeconsidered.
Power MOSFET and Schottky Diode
(Optional) Selection
Two external power MOSFETs must be selected for each
controller in the LTC3892/LTC3892-1/LTC3892-2: one
N-channel MOSFET for the top (main) switch and one
N-channel MOSFET for the bottom (synchronous) switch.
Theinductorvaluehasadirecteffectonripplecurrent.The
inductor ripple current, ∆I , decreases with higher induc-
L
tance or higher frequency and increases with higher V :
IN
The peak-to-peak drive levels are set by the DRV volt-
CC
1
VOUT
IN
age. This voltage can range from 5V to 10V depending
on configuration of the DRVSET pin. Therefore, both
logic-level and standard-level threshold MOSFETs can be
used in most applications depending on the programmed
∆IL =
V
1−
OUT
f L
( )( )
V
Accepting larger values of ∆I allows the use of low
L
inductances, but results in higher output voltage ripple
DRV voltage. Different UVLO thresholds appropriate
CC
and greater core losses. A reasonable starting point for
for logic-level or standard-level threshold MOSFETs can
setting ripple current is ∆I = 0.3(I
). The maximum
MAX
L
be selected by the DRVUV pin. Pay close attention to the
∆I occurs at the maximum input voltage.
L
BV
specification for the MOSFETs as well.
DSS
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
The LTC3892/LTC3892-1/LTC3892-2’s unique ability to
adjustthegatedrivelevelbetween5Vto10V(OPTI-DRIVE)
allows an application circuit to be precisely optimized
for efficiency. When adjusting the gate drive level, the
final arbiter is the total input current for the regulator. If
a change is made and the input current decreases, then
the efficiency has improved. If there is no change in input
current, then there is no change in efficiency.
25ꢀ of the current limit determined by R
. Lower
SENSE
inductor values (higher ∆I ) will cause this to occur at
L
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Selection criteria for the power MOSFETs include the
on-resistance R
, Miller capacitance C
DS(ON)
, input
MILLER
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voltage and maximum output current. Miller capacitance,
MILLER
a short-circuit when the synchronous switch is on close
to 100ꢀ of the period.
C
, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. C is equal to the increase in gate charge
The term (1 + δ) is generally given for a MOSFET in the
MILLER
form of a normalized R
vs Temperature curve, but
DS(ON)
along the horizontal axis while the curve is approximately
δ = 0.005/°C can be used as an approximation for low
flat divided by the specified change in V . This result is
DS
voltage MOSFETs.
then multiplied by the ratio of the application applied V
DS
Optional Schottky diodes placed across the synchronous
MOSFET conduct during the dead-time between the con-
duction of the two power MOSFETs. This prevents the
body diode of the synchronous MOSFET from turning
on, storing charge during the dead-time and requiring a
reverse recovery period that could cost as much as 3ꢀ
to the gate charge curve specified V . When the IC is
DS
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
VOUT
Main Switch Duty Cycle =
V
IN
in efficiency at high V . A 1A to 3A Schottky is generally
V − V
IN
IN
OUT
Synchronous Switch Duty Cycle =
a good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
V
IN
The MOSFET power dissipations at maximum output
current are given by:
2
VOUT
C and C Selection
OUT
PMAIN
(V )2
=
I
(
1+δ R
+
(
)
IN
)
OUT(MAX)
DS(ON)
V
IN
The selection of C is simplified by the 2-phase architec-
IN
I
OUT(MAX)
ture and its impact on the worst-case RMS current drawn
throughtheinputnetwork(battery/fuse/capacitor).Itcanbe
shown that the worst-case capacitor RMS current occurs
when only one controller is operating. The controller with
(RDR)(CMILLER)•
IN
2
1
1
+
(f)
V
DRVCC − VTHMIN
V
THMIN
the highest (V )(I ) product needs to be used in the
OUT OUT
formula shown in Equation 1 to determine the maximum
RMS capacitor current requirement. Increasing the out-
put current drawn from the other controller will actually
decrease the input RMS ripple current from its maximum
value. The opt-of-phase technique typically reduces the
input capacitor’s RMS ripple current by a factor of 30ꢀ
to 70ꢀ when compared to a single phase power supply
solution.
2
V − V
IN
OUT
PSYNC
=
I
(
1+δ R
DS(ON)
(
)
)
OUT(MAX)
V
IN
where δ is the temperature dependency of R
and
DS(ON)
R
(approximately 2Ω) is the effective driver resistance
DR
at the MOSFET’s Miller threshold voltage. V
typical MOSFET minimum threshold voltage.
is the
THMIN
2
Both MOSFETs have I R losses while the main N-channel
equations include an additional term for transition losses,
Incontinuousmode,thesourcecurrentofthetopMOSFET
is a square wave of duty cycle (V )/(V ). To prevent
OUT
IN
which are highest at high input voltages. For V < 20V
IN
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
the high current efficiency generally improves with larger
MOSFETs, while for V > 20V the transition losses rapidly
IN
increasetothepointthattheuseofahigherR
device
DS(ON)
withlowerC
actuallyprovideshigherefficiency.The
1/2
IMAX
MILLER
CIN Required IRMS
≈
V
V − V
IN
OUT
(
OUT )(
)
(1)
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
V
IN
38921fc
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APPLICATIONS INFORMATION
where f is the operating frequency, C
is the output
This formula has a maximum at V = 2V , where I
OUT
IN
OUT
RMS
capacitance and ∆I is the ripple current in the inductor.
= I /2. This simple worst-case condition is commonly
L
OUT
The output ripple is highest at maximum input voltage
usedfordesignbecauseevensignificantdeviationsdonot
offermuchrelief.Notethatcapacitormanufacturers’ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the
high operating frequency of the LTC3892/LTC3892-1/
since ∆I increases with input voltage.
L
Setting Output Voltage
The LTC3892/LTC3892-1/LTC3892-2 output voltages are
setbyanexternalfeedbackresistordividercarefullyplaced
across the output, as shown in Figure 3a. The regulated
output voltage is determined by:
LTC3892-2, ceramic capacitors can also be used for C .
Always consult the manufacturer if there is any question.
IN
RB
RA
V
OUT =0.8V 1+
The benefit of the LTC3892/LTC3892-1/LTC3892-2
2-phase operation can be calculated by using Equation 1
for the higher power controller and then calculating the
loss that would have resulted if both controller channels
switched on at the same time. The total RMS power lost
is lower when both controllers are operating due to the
reduced overlap of current pulses required through the
input capacitor’s ESR. This is why the input capacitor’s
requirementcalculatedabovefortheworst-casecontroller
is adequate for the dual controller design. Also, the input
protection fuse resistance, battery resistance, and PC
board trace resistance losses are also reduced due to the
reduced peak currents in a 2-phase system. The overall
benefit of a multiphase design will only be fully realized
when the source impedance of the power supply/battery
is included in the efficiency testing. The drains of the top
MOSFETs should be placed within 1cm of each other and
To improve the frequency response, a feedforward ca-
pacitor, C , may be used. Great care should be taken to
FF
route the V line away from noise sources, such as the
FB
inductor or the SW line.
For the LTC3892 and LTC3892-2, channel 1 has the
option to be programmed to a fixed 5V or 3.3V output
through control of the VPRG1 pin (not available on the
LTC3892-1). Figure 3b shows how the V
to sense the output voltage in fixed output mode. Tying
pin is used
FB1
VPRG1 to INTV or GND programs V
to 5V or 3.3V,
to adjustable
CC
OUT1
OUT1
respectively. Floating VPRG1 sets V
output mode using external resistors.
V
OUT
1/2 LTC3892/
LTC3892-1/
LTC3892-2
R
R
C
FF
B
A
shareacommonC (s).SeparatingthedrainsandC may
IN
IN
V
FB
produceundesirablevoltageandcurrentresonancesatV .
IN
A small (0.1μF to 1μF) bypass capacitor between the chip
IN
38921 F05a
V pinandground,placedclosetotheLTC3892/LTC3892-
(3a) Setting Adjustable Output Voltage
1/LTC3892-2, is also suggested. A 2.2Ω to 10Ω resistor
placed between C (C1) and the V pin provides further
IN
IN
LTC3892/
LTC3892-2
isolation, but is not required.
V
OUT1
The selection of C
is driven by the effective series
INTV /GND
CC
VPRG1
V
FB1
OUT
5V/3.3V
resistance (ESR). Typically, once the ESR requirement
C
OUT
is satisfied, the capacitance is adequate for filtering. The
38921 F05b
output ripple (∆V ) is approximated by:
OUT
(3b) Setting CH1 (LTC3892) to Fixed 5V/3.3V Voltage
Figure 3. Setting Buck Output Voltage
1
∆VOUT ≈ ∆I ESR+
L
8•f•COUT
38921fc
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RUN Pins
Tracking and Soft-Start (TRACK/SS1, TRACK/SS2 Pins)
is controlled by the voltage on
The LTC3892/LTC3892-1/LTC3892-2 is enabled using The start-up of each V
OUT
the RUN1 and RUN2 pins. The RUN pins have a rising theTRACK/SSpin(TRACK/SS1forchannel1,TRACK/SS2
thresholdof1.275Vwith75mVofhysteresis.PullingaRUN for channel 2). When the voltage on the TRACK/SS pin
pin below 1.2V shuts down the main control loop for that is less than the internal 0.8V reference, the LTC3892/
channel. Pulling both RUN pins below 0.7V disables the LTC3892-1/LTC3892-2 regulates the V pin voltage to
FB
controllersandmostinternalcircuits,includingtheDRV
the voltage on the TRACK/SS pin instead of the internal
and INTV LDOs. In this state, the LTC3892/LTC3892-1/ reference. The TRACK/SS pin can be used to program
CC
CC
LTC3892-2 draws only 3.6µA of quiescent current.
an external soft-start function or to allow V
another supply during start-up.
to track
OUT
Releasing a RUN pin allows a small 150nA internal current
to pull up the pin to enable that controller. Because of Soft-start is enabled by simply connecting a capacitor
condensation or other small board leakage pulling the pin from the TRACK/SS pin to ground, as shown in Figure 5.
down,itisrecommendedtheRUNpinsbeexternallypulled An internal 10μA current source charges the capacitor,
up or driven directly by logic. Each RUN pin can tolerate providingalinearrampingvoltageattheTRACK/SSpin.The
up to 65V (absolute maximum), so it can be conveniently LTC3892/LTC3892-1/LTC3892-2willregulateitsfeedback
tied to V in always-on applications where one or more voltage (and hence V ) according to the voltage on the
IN
OUT
controllersareenabledcontinuouslyandnevershutdown. TRACK/SS pin, allowing V
to rise smoothly from 0V
OUT
to its final regulated value. The total soft-start time will be
The RUN pins can be implemented as a UVLO by con-
necting them to the output of an external resistor divider
network off V , as shown in Figure 4.
approximately:
0.8V
IN
t
SS =CSS •
10µA
V
IN
1/2 LTC3892/
LTC3892-1/
LTC3892-2
1/2 LTC3892/
LTC3892/
R
R
B
RUN
LTC3892-2
TRACK/SS
A
C
SS
3892 F04
GND
38921 F06
Figure 4. Using the RUN Pins as a UVLO
Figure 5. Using the TRACK/SS Pin to Program Soft-Start
TherisingandfallingUVLOthresholdsarecalculatedusing
the RUN pin thresholds and pull-up current:
RB
RA
V
UVLO(RISING) = 1.275V 1+
– 150nA •RB
– 150nA •RB
RB
RA
V
UVLO(FALLING) = 1.20V 1+
38921fc
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APPLICATIONS INFORMATION
V
OUT
Alternatively, the TRACK/SS1 and TRACK/SS2 pins can
be used to track two (or more) supplies during start-up,
as shown qualitatively in Figures 6a and 6b. To do this, a
resistordividershouldbeconnectedfromthemastersup-
ply (V ) to the TRACK/SS pin of the slave supply (V ),
R
B
V
FB
R
A
1/2 LTC3892/
LTC3892-1/
LTC3892-2
X
OUT
V
X
as shown in Figure 7. During start-up V
according to the ratio set by the resistor divider:
will track V
OUT
X
R
R
TRACKB
TRACK/SS
VX
RA
R
TRACKA +RTRACKB
RA +RB
TRACKA
38921 F08
=
•
VOUT RTRACKA
Figure 7. Using the TRACK/SS Pin for Tracking
For coincident tracking (V
= V during start-up),
X
OUT
R = R
A
TRACKA
TRACKB
DRV and INTV Regulators and EXTV
CC
CC
CC
R = R
B
(OPTI-DRIVE)
TheLTC3892/LTC3892-1/LTC3892-2featurestwoseparate
internalP-channellowdropoutlinearregulators(LDO)that
V
V
X(MASTER)
OUT(SLAVE)
supply power at the DRV pin from either the V supply
CC
IN
pin or the EXTV pin depending on the connections of
CC
the EXTV , DRVSET, and DRVUV pins. A third P-channel
CC
LDOsuppliespowerattheINTV pinfromtheDRV pin.
CC
CC
DRV powers the gate drivers whereas INTV powers
CC
CC
much of the LTC3892/LTC3892-1/LTC3892-2’s internal
circuitry.TheV LDOandtheEXTV LDOregulateDRV
CC
IN
CC
38921 F07a
TIME
between 5V to 10V, depending on how the DRVSET pin
is set. Each of these LDOs can supply a peak current of
at least 50mA and must be bypassed to ground with a
minimum of 4.7μF ceramic capacitor. Good bypassing is
needed to supply the high transient currents required by
theMOSFETgatedriversandtopreventinteractionbetween
(6a) Coincident Tracking
V
V
X(MASTER)
the channels. The INTV supply must be bypassed with
CC
OUT(SLAVE)
a 0.1μF ceramic capacitor.
The DRVSET pin programs the DRV supply voltage and
CC
the DRVUV pin selects different DRV UVLO and EXTV
CC
CC
38921 F07b
TIME
switchover threshold voltages. Table 2a summarizes the
different DRVSET pin configurations along with the volt-
age settings that go with each configuration. Table 2b
summarizes the different DRVUV pin settings. Tying the
(6b) Ratiometric Tracking
Figure 6. Two Different Modes of Output Voltage Tracking
38921fc
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IC in this case is highest and is equal to V • I
. The
DRVSET pin to INTV programs DRV to 10V. Tying the
IN DRVCC
CC
CC
gate charge current is dependent on operating frequency
as discussed in the Efficiency Considerations section.
The junction temperature can be estimated by using the
equations given in Note 2 of the Electrical Characteristics.
For example, using the LTC3892 in the QFN package, the
DRVSET pin to GND programs DRV to 6V. By placing
CC
a 50k to 100k resistor between DRVSET and GND the
DRV voltage can be programmed between 5V to 10V,
CC
as shown in Figure 8.
Table 2a
DRV current is limited to less than 31mA from a 40V
CC
DRVSET PIN
DRV VOLTAGE
CC
supply when not using the EXTV supply at a 70°C ambi-
CC
GND
6V
10V
ent temperature:
INTV
CC
T = 70°C + (31mA)(40V)(44°C/W) = 125°C
J
Resistor to GND 50k to 100k
5V to 10V
To prevent the maximum junction temperature from being
Table 2b
exceeded, the V supply current must be checked while
IN
DRV UVLO
EXTV SWITCHOVER
CC
CC
operating in forced continuous mode (PLLIN/MODE =
RISING / FALLING
RISING / FALLING
THRESHOLD
INTV ) at maximum V .
DRVUV PIN
GND
INTV
THRESHOLDS
4.0V / 3.8V
7.5V / 6.7V
CC
IN
4.7V / 4.45V
7.7V / 7.45V
When the voltage applied to EXTV rises above its
CC
CC
switchover threshold, the V LDO is turned off and the
IN
EXTV LDO is enabled. The EXTV LDO remains on as
CC
CC
long as the voltage applied to EXTV remains above the
11
10
CC
switchover threshold minus the comparator hysteresis.
The EXTV LDO attempts to regulate the DRV voltage
CC
CC
9
tothevoltageasprogrammedbytheDRVSETpin,sowhile
EXTV is less than this voltage, the LDO is in dropout
8
7
6
5
CC
and the DRV voltage is approximately equal to EXTV .
CC
CC
When EXTV is greater than the programmed voltage,
CC
up to an absolute maximum of 14V, DRV is regulated
CC
to the programmed voltage.
Using the EXTV LDO allows the MOSFET driver and
4
CC
50
65
55 60
70
75 80 85 90 95 100
control power to be derived from one of the LTC3892/
DRVSET PIN RESISTOR (kΩ)
38921 F09
LTC3892-1/LTC3892-2’s switching regulator outputs
Figure 8. Relationship Between DRVCC Voltage
and Resistor Value at DRVSET Pin
(4.7V/7.7V ≤ V
≤ 14V) during normal operation and
OUT
fromtheV LDOwhentheoutputisoutofregulation(e.g.,
IN
start-up, shortcircuit). Ifmorecurrentisrequiredthrough
HighinputvoltageapplicationsinwhichlargeMOSFETsare
being driven at high frequencies may cause the maximum
junction temperature rating for the LTC3892/LTC3892-1/
the EXTV LDO than is specified, an external Schottky
CC
diode can be added between the EXTV and DRV pins.
CC
CC
In this case, do not apply more than 10V to the EXTV
CC
LTC3892-2 to be exceeded. The DRV current, which is
CC
pin and make sure that EXTV ≤ V .
CC
IN
dominated by the gate charge current, may be supplied by
Significant efficiency and thermal gains can be realized
by powering DRV from the output, since the V cur-
either the V LDO or the EXTV LDO. When the voltage
IN
CC
on the EXTV pin is less than its switchover threshold
CC
IN
CC
rent resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
(4.7V or 7.7V as determined by the DRVUV pin described
above), the V LDO is enabled. Power dissipation for the
IN
38921fc
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APPLICATIONS INFORMATION
For 5V to 14V regulator outputs, this means connecting
the boost voltage is above the input supply: V
= V
BOOST IN
the EXTV pin directly to V . Tying the EXTV pin to
+ V
. The value of the boost capacitor, C , needs to
CC
OUT
CC
DRVCC B
be 100 times that of the total input capacitance of the
topside MOSFET(s).
an 8.5V supply reduces the junction temperature in the
previous example from 125°C to:
T = 70°C + (31mA)(8.5V)(44°C/W) = 82°C
J
Fault Conditions: Current Limit and
Current Foldback
However,for3.3Vandotherlowvoltageoutputs,additional
circuitryisrequiredtoderiveDRV powerfromtheoutput.
CC
The LTC3892/LTC3892-1 (not the LTC3892-2) includes
current foldback to help limit load current when an output
is shorted to ground. If the output voltage falls below
70ꢀ of its nominal output level, then the maximum sense
voltage is progressively lowered from 100ꢀ to 40ꢀ of its
maximum selected value.
The following list summarizes the four possible connec-
tions for EXTV :
CC
1. EXTV grounded. This will cause DRV to be
CC
CC
powered from the internal V regulator resulting in
IN
increasedpowerdissipationintheLTC3892/LTC3892-1/
LTC3892-2 at high input voltages.
Under short-circuit conditions with very low duty cycles,
the channel will begin cycle skipping in order to limit
the short-circuit current. In this situation the bottom
MOSFET will be dissipating most of the power but less
than in normal operation. The short-circuit ripple current
is determined by the minimum on-time, t
LTC3892/LTC3892-1/LTC3892-2(≈80ns), theinputvoltage
and inductor value:
2. EXTV connected directly to V . This is the normal
CC
OUT
connection for a 5V to 14V regulator and provides the
highest efficiency.
3. EXTVCC connected to an external supply. If an external
supplyisavailableinthe5Vto14Vrange,itmaybeusedto
powerEXTVCCprovidingitiscompatiblewiththeMOSFET
gate drive requirements. Ensure that EXTVCC < VIN.
, of the
ON(MIN)
V
L
IN
∆IL(SC) = tON(MIN)
4. EXTV connected to an output-derivedboostnetwork.
CC
For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTV to an
CC
The resulting average short-circuit current is:
output-derivedvoltagethathasbeenboostedtogreater
1
2
than 4.7V/7.7V.
ISC = 40ꢀ•ILIM(MAX) − ∆IL(SC) (LTC3892/LTC3892-1)
Topside MOSFET Driver Supply (C )
B
1
2
ISC =ILIM(MAX) − ∆IL(SC)
(LTC3892-2)
External bootstrap capacitors, C , connected to the
B
BOOST pins supply the gate drive voltage for the topside
MOSFET. The LTC3892/LTC3892-1/LTC3892-2 features
Fault Conditions: Overvoltage Protection (Crowbar)
(LTC3892/LTC3892-1; not on LTC3892-2)
an internal switch between DRV and the BOOST pin
CC
for each controller. These internal switches eliminate the
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
muchhigherthannominallevels.Thecrowbarcauseshuge
currents to flow, that blow the fuse to protect against a
shortedtopMOSFETiftheshortoccurswhilethecontroller
is operating.
need for external bootstrap diodes between DRV and
CC
BOOST. CapacitorC intheFunctionalDiagramischarged
B
through this internal switch from DRV when the SW
CC
pin is low. When the topside MOSFET is to be turned on,
the driver places the C voltage across the gate-source
B
of the MOSFET. This enhances the top MOSFET switch
and turns it on. The switch node voltage, SW, rises to V
IN
A comparator monitors the output for overvoltage condi-
tions. The comparator detects faults greater than 10ꢀ
and the BOOST pin follows. With the topside MOSFET on,
38921fc
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above the nominal output voltage. When this condition
is sensed, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. ThebottomMOSFETremainsoncontinuouslyfor
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP, holds the voltage at the VCO input.
aslongastheovervoltageconditionpersists;ifV returns
OUT
to a safe level, normal operation automatically resumes.
AshortedtopMOSFETwillresultinahighcurrentcondition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
Note that the LTC3892/LTC3892-1/LTC3892-2 can only
be synchronized to an external clock whose frequency is
within range of the LTC3892/LTC3892-1/LTC3892-2’s
internal VCO, which is nominally 55kHz to 1MHz. This is
guaranteed to be between 75kHz and 850kHz. Typically,
the external clock (on the PLLIN/MODE pin) input high
threshold is 1.6V, while the input low threshold is 1.1V.
The LTC3892/LTC3892-1/LTC3892-2 is guaranteed to
synchronize to an external clock that swings up to at least
2.5V and down to 0.5V or less.
Fault Conditions: Overtemperature Protection
Athighertemperatures,orincaseswheretheinternalpower
dissipation causes excessive self heating on chip (such as
DRV shorttoground),theovertemperatureshutdowncir-
CC
cuitrywillshutdowntheLTC3892/LTC3892-1/LTC3892-2.
When the junction temperature exceeds approximately
175°C, the overtemperature circuitry disables the DRV
CC
LDO, causing the DRV supply to collapse and effectively
Rapid phase locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. The VCO’s input voltage is
prebiased at a frequency corresponding to the frequency
set by the FREQ pin. Once prebiased, the PLL only needs
to adjust the frequency slightly to achieve phase lock and
synchronization. Although it is not required that the free-
running frequency be near the external clock frequency,
doingsowillpreventtheoperatingfrequencyfrompassing
through a large range of frequencies as the PLL locks.
CC
shuttingdowntheentireLTC3892/LTC3892-1/LTC3892-2
chip. Once the junction temperature drops back to the ap-
proximately 155°C, the DRV LDO turns back on. Long-
CC
term overstress (T > 125°C) should be avoided as it can
J
degrade the performance or shorten the life of the part.
Phase-Locked Loop and Frequency Synchronization
The LTC3892/LTC3892-1/LTC3892-2 has an internal
phase-locked loop (PLL) comprised of a phase frequency
detector, a lowpass filter, and a voltage-controlled oscilla-
tor (VCO). This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the PLLIN/MODE pin. The turn-on
of controller 2’s top MOSFET is thus 180° out of phase
with the external clock. The phase detector is an edge
sensitivedigitaltypethatprovideszerodegreesphaseshift
between the external and internal oscillators. This type of
phase detector does not exhibit false lock to harmonics
of the external clock.
1000
900
800
700
600
500
400
300
200
100
If the external clock frequency is greater than the internal
oscillator’sfrequency,f ,thencurrentissourcedcontinu-
OSC
0
15 25 35 45 55 65 75 85 95 105 115 125
ously from the phase detector output, pulling up the VCO
FREQ PIN RESISTOR (kΩ)
38921 F10
input. When the external clock frequency is less than f
,
OSC
current is sunk continuously, pulling down the VCO input.
Figure 9. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin
38921fc
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Table 3 summarizes the different states in which the FREQ
pin can be used. When synchronized to an external clock,
the LTC3892/LTC3892-1/LTC3892-2 operates in forced
continuous mode at light loads.
produce the most improvement. Percent efficiency can
be expressed as:
ꢀEfficiency = 100ꢀ – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Table 3
FREQ PIN
PLLIN/MODE PIN
DC Voltage
FREQUENCY
350kHz
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
0V
INTV
DC Voltage
535kHz
CC
losses in LTC3892/LTC3892-1/LTC3892-2 circuits: 1) IC
Resistor to GND
Any of the Above
DC Voltage
50kHz to 900kHz
2
V current, 2) DRV regulator current, 3) I R losses, 4)
IN
CC
External Clock
75kHz to 850kHz
Phase Locked to
External Clock
Topside MOSFET transition losses.
1. The V current is the DC supply current given in the
IN
Minimum On-Time Considerations
Minimum on-time, t , is the smallest time duration
that the LTC3892/LTC3892-1/LTC3892-2 is capable of
turning on the top MOSFET. It is determined by internal
timing delays and the gate charge required to turn on the
top MOSFET. Low duty cycle applications may approach
this minimum on-time limit and care should be taken to
ensure that:
ElectricalCharacteristicstable,whichexcludesMOSFET
driverandcontrolcurrents. V currenttypicallyresults
ON(MIN)
IN
in a small (<0.1ꢀ) loss.
2. DRV current is the sum of the MOSFET driver and
CC
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
VOUT
from DRV to ground. The resulting dQ/dt is a cur-
CC
tON(MIN)
<
rent out of DRV that is typically much larger than the
V (f)
CC
IN
control circuit current. In continuous mode, I
GATECHG
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
= f(Q + Q ), where Q and Q are the gate charges of
T
B
T
B
the topside and bottom side MOSFETs.
SupplyingDRV fromanoutput-derivedsourcepower
CC
through EXTV will scale the V current required for
CC
IN
The minimum on-time for the LTC3892/LTC3892-1/
LTC3892-2 is approximately 80ns. However, as the peak
sense voltage decreases, the minimum on-time gradually
increases up to about 130ns. This is of particular concern
in forced continuous applications with low ripple current
at light loads. If the duty cycle drops below the minimum
on-timelimitinthissituation, asignificantamountofcycle
skipping can occur with correspondingly larger current
and voltage ripple.
thedriverandcontrolcircuitsbyafactorof(DutyCycle)/
(Efficiency). For example, in a 20V to 5V application,
10mAofDRV currentresultsinapproximately2.5mA
CC
of V current. This reduces the midcurrent loss from
IN
10ꢀ or more (if the driver was powered directly from
V ) to only a few percent.
IN
2
3. I R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resis-
tor and input and output capacitor ESR. In continuous
mode the average output current flows through L and
Efficiency Considerations
R
, but is chopped between the topside MOSFET
SENSE
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100ꢀ.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
and the synchronous MOSFET. If the two MOSFETs
have approximately the same R
, then the resis-
DS(ON)
tance of one MOSFET can simply be summed with the
2
resistances of L, R
and ESR to obtain I R losses.
SENSE
38921fc
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For example, if each R
= 30mΩ, R = 50mΩ,
or ringing, which would indicate a stability problem.
OPTI-LOOPcompensationallowsthetransientresponseto
be optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior, but it also provides
a DC-coupled and AC-filtered closed-loop response test
point. The DC step, rise time and settling at this test
point truly reflects the closed-loop response. Assuming
a predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin. The
ITH external components shown in Figure 12 circuit will
provide an adequate starting point for most applications.
DS(ON)
L
R
= 10mΩ and R
= 40mΩ (sum of both input
SENSE
ESR
andoutputcapacitancelosses),thenthetotalresistance
is 130mΩ. This results in losses ranging from 3ꢀ to
13ꢀ as the output current increases from 1A to 5A for
a 5V output, or a 4ꢀ to 20ꢀ loss for a 3.3V output.
Efficiency varies as the inverse square of V
for the
OUT
sameexternalcomponentsandoutputpowerlevel. The
combined effects of increasingly lower output voltages
andhighercurrentsrequiredbyhighperformancedigital
systemsisnotdoublingbutquadruplingtheimportance
of loss terms in the switching regulator system!
4. Transition losses apply only to the top MOSFET(s), and
become significant only when operating at high input
voltages (typically 20V or greater). Transition losses
can be estimated from:
The ITH series R -C filter sets the dominant pole-zero
C
C
loop compensation. The values can be modified slightly
to optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop gain and phase. An output current pulse of 20ꢀ
to 80ꢀ of full-load current having a rise time of 1μs to
10μs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
2
Transition Loss = (1.7) • V • I
• C
• f
IN
O(MAX)
RSS
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5ꢀ
to 10ꢀ efficiency degradation in portable systems. It
is very important to include these system level losses
during the design phase. The internal battery and fuse
resistancelossescanbeminimizedbymakingsurethat
C has adequate charge storage and very low ESR at
IN
the switching frequency. A 25W supply will typically
require a minimum of 20μF to 40μF of capacitance
having a maximum of 20mΩ to 50mΩ of ESR. Other
losses including Schottky conduction losses during
dead-time and inductor core losses generally account
for less than 2ꢀ total additional loss.
Placing a power MOSFET directly across the output ca-
pacitor and driving the gate with an appropriate signal
generator is a practical way to produce a realistic load step
condition. The initial output voltage step resulting from
the step change in output current may not be within the
bandwidth of the feedback loop, so this signal cannot be
used to determine phase margin. This is why it is better
to look at the ITH pin signal which is in the feedback loop
andisthefilteredandcompensatedcontrolloopresponse.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
The gain of the loop will be increased by increasing R
C
and the bandwidth of the loop will be increased by de-
creasing C . If R is increased by the same factor that C
C
load current. When a load step occurs, V
shifts by an
OUT
C
C
amount equal to ∆I
, where ESR is the effective
LOAD(ESR)
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loopsystemandwilldemonstratetheactualoverall
supply performance.
series resistance of C . ∆I
also begins to charge or
generating the feedback error signal that
forces the regulator to adapt to the current change and
OUT
LOAD
discharge C
OUT
return V
to its steady-state value. During this recov-
can be monitored for excessive overshoot
OUT
ery time V
OUT
38921fc
28
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LTC3892/
LTC3892-1/LTC3892-2
APPLICATIONS INFORMATION
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
ThepowerdissipationonthetopsideMOSFETcanbeeasily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: R
= 0.035Ω/0.022Ω, C
= 215pF.
DS(ON)
MILLER
with C , causing a rapid drop in V . No regulator can
At maximum input voltage with T(estimated) = 50°C:
OUT
OUT
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
3.3V
22V
2
PMAIN
=
5A
1+ 0.005 50°C−25°C
(
)
(
)
(
)
2 5A
C
to C
is greater than 1:50, the switch rise-time
0.035Ω + 22V
) (
2.5Ω 215pF •
)(
(
)
(
)
LOAD
OUT
2
should be controlled so that the load rise-time is limited
to approximately 25 • C . Thus a 10μF capacitor would
1
1
LOAD
(
+
350kHz =308mW
)
require a 250μs rise time, limiting the charging current
to about 200mA.
6V−2.3V 2.3V
Ashort-circuittogroundwillresultinafoldedbackcurrentof:
Design Example
80ns 22V
34mV 1
−
(
)
ISC =
=3.21A
As a design example for one channel, assume V = 12V
IN
0.01Ω 2
4.7µH
(nominal), V = 22V (maximum), V
= 3.3V, I
=
IN
OUT
MAX
5A, V
= 75mV and f = 350kHz. The inductance
SENSE(MAX)
with a typical value of R
and δ = (0.005/°C)(25°C)
DS(ON)
value is chosen first based on a 30ꢀ ripple current as-
sumption. The highest value of ripple current occurs at
the maximum input voltage. Tie the FREQ pin to GND,
generating 350kHz operation. The minimum inductance
for 30ꢀ ripple current is:
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
2
P
= (3.21A) (1.125) (0.022Ω) = 255mW
SYNC
which is less than under full-load conditions.
C is chosen for an RMS current rating of at least 3A at
VOUT
f L
( )( )
VOUT
IN
∆IL =
1−
temperature assuming only this channel is on. C
is
OUT
V
IN(NOM)
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
A 4.7μH inductor will produce 29ꢀ ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 5.73A. Increasing the ripple
current will also help ensure that the minimum on-time
of 80ns is not violated. The minimum on-time occurs at
V
= R (∆I ) = 0.02Ω (1.45A) = 29mV
ESR L P-P
O(RIPPLE)
PC Board Layout Checklist
maximum V :
IN
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. Figure 10 illustrates the current waveforms present in
the various branches of the 2-phase synchronous buck
regulators operating in the continuous mode. Check the
following in your layout:
VOUT
IN(MAX) ( )
3.3V
22V 350kHz
tON(MIN)
=
=
= 429ns
V
f
(
)
The equivalent R resistor value can be calculated by
SENSE
using the minimum value for the maximum current sense
threshold (66mV):
1. Are the top N-channel MOSFETs MTOP1 and MTOP2
located within 1cm of each other with a common drain
66mV
5.73A
RSENSE
≤
≈ 0.01Ω
connection at C ? Do not attempt to split the input
IN
decoupling for the two channels as it can cause a large
resonant loop.
Choosing 1ꢀ resistors: R = 25k and R = 78.7k yields
an output voltage of 3.32V.
A
B
38921fc
29
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
APPLICATIONS INFORMATION
SW1
L1
R
SENSE1
V
OUT1
C
R
L1
OUT1
V
IN
R
IN
C
IN
SW2
L2
R
SENSE2
V
OUT2
C
R
L2
OUT2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
38921 F11
Figure 10. Branch Current Waveforms
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
resistor connections should not be along the high cur-
rent input feeds from the input capacitor(s).
of C
must return to the combined C
(–) termi-
–
+
DRVCC
OUT
4. Are the SENSE and SENSE leads routed together with
minimumPCtracespacing?Thefiltercapacitorbetween
nals. The path formed by the top N-channel MOSFET,
Schottky diode and the C capacitor should have short
+
–
IN
SENSE and SENSE should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
5. IstheDRV anddecouplingcapacitorconnectedclose
CC
to the IC, between the DRV and the ground pin? This
CC
capacitor carries the MOSFET drivers’ current peaks.
3. Does the LTC3892/LTC3892-1/LTC3892-2 V pin’s
FB
6. Keep the switching nodes (SW1, SW2), top gate (TG1,
TG2), and boost nodes (BOOST1, BOOST2) away from
sensitive small-signal nodes, especially from the op-
resistive divider connect to the (+) terminal of C
?
OUT
The resistive divider must be connected between the
(+) terminal of C and signal ground. The feedback
OUT
38921fc
30
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LTC3892/
LTC3892-1/LTC3892-2
APPLICATIONS INFORMATION
positeschannel’svoltageandcurrentsensingfeedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the output side
of the LTC3892/LTC3892-1/LTC3892-2 and occupy
minimum PC trace area.
when the other channel is turning on its top MOSFET. This
occurs around 50ꢀ duty cycle on either channel due to
the phasing of the internal clocks and may cause minor
duty cycle jitter.
Reduce V from its nominal level to verify operation of
IN
7. Useamodifiedstargroundtechnique:alowimpedance,
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
the regulator in dropout. Check the operation of the un-
dervoltage lockout circuit by further lowering V while
IN
monitoring the outputs to verify operation.
with tie-ins for the bottom of the DRV decoupling
CC
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
capacitor, the bottom of the voltage feedback resistive
divider and the GND pin of the IC.
PC Board Layout Debugging
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
totheinternaloscillatorandprobetheactualoutputvoltage
as well. Check for proper performance over the operating
voltage and current range expected in the application. The
frequencyofoperationshouldbemaintainedovertheinput
voltage range down to dropout and until the output load
drops below the low current operation threshold—typi-
cally 25ꢀ of the maximum designed current level in Burst
Mode operation.
for inductive coupling between C , Schottky and the top
IN
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
Thedutycyclepercentageshouldbemaintainedfromcycle
tocycleinawell-designed,lownoisePCBimplementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controllerischeckedforitsindividualperformanceshould
both should multiple controllers be turned on at the same
time. A particularly difficult region of operation is when
one channel is nearing its current comparator trip point
38921fc
31
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
TYPICAL APPLICATIONS
VIN
8V TO 60V
C
2.2µF
x5
C
47µF
INB
INA
RUN1
TG1
VIN
RUN2
TG2
MTOP1
MTOP2
BOOST1
BOOST2
R
SNS2
8mΩ
L1
5.6µH
L2
15µH
R
5mΩ
SNS1
C
C
B2
0.1µF
B1
V
V
OUT2
0.1µF
OUT1
SW1
SW2
5V
12V*
8A
OUT1A
5A
OUT2A
C
C
C
OUT1B
10µF
C
OUT2B
10µF
MBOT1
MBOT2
BG1
BG2
220µF
150µF
LTC3892
+
+
SENSE1
SENSE2
R
A2
100k
C
C
SNS1
1nF
SNS2
1nF
–
–
SENSE1
SENSE2
V
FB1
ITH1
V
FB2
ITH2
R
7.15k
B2
TRACK/SS1
TRACK/SS2
R
PG1
1000k
EXTV
V
OUT2
C
R
34.8k
PGOOD1
R
7.5k
CC
C
ITH2B
ITH2
ITH1
ITH1B
R
100pF
100pF
PG2
1000k
ILIM
PGOOD2
VPRG1
C
SS1
0.1µF
C
C
C
SS2
ITH2A
ITH1A
FREQ
1nF
2.2nF
0.1µF
DRVSET
PLLIN/MODE
DRVUV
INTV
GND
DRV
CC
CC
R
FREQ
35.7k
C
C
DRVCC
4.7µF
INTVCC
0.1µF
3892 TA02
TOP1, TOP2: BSC057N08NS3
BOT1, BOT2: BSC036NE7NS3
L1: COILCRAFT XAL1010-562ME
L2: COILCRAFT XAL1010-153ME
*V
OUT2
FOLLOWS V WHEN V ≤ 12V
IN IN
Figure 11. High Efficiency Dual 5V/12V Step-Down Converter with 10V Gate Drive
Efficiency and Power Loss
vs Load Current
100
90
80
70
60
50
40
30
20
10
0
10k
1k
EFFICIENCY
100
10
POWER LOSS
1
V
V
= 12V
OUT
IN
= 5V
0.1
0.0001 0.001
0.01
0.1
1
10
LOAD CURRENT (A)
3892 TA02b
38921fc
32
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
TYPICAL APPLICATIONS
V
IN
4.5V TO 60V
C
INB
C
INA
100µF
RUN1
TG1
VIN
RUN2
TG2
2.2µF
x3
MTOP1
MTOP2
BOOST1
BOOST2
R
L2
8.0µH
SNS2
L1
4.7µH
R
SNS1
8mΩ
C
B2
0.1µF
C
B1
0.1µF
10mΩ
V
OUT2
8.5V*
3A
V
OUT1
SW1
SW2
3.3V
5A
C
C
C
C
OUT1A
OUT1B
10µF
OUT2A
330µF
OUT2B
10µF
MBOT1
MBOT2
BG1
BG2
470µF
LTC3892
+
+
SENSE1
SENSE2
R
A2
100k
C
SNS1
1nF
C
SNS2
1nF
–
–
SENSE1
SENSE2
V
FB1
ITH1
V
FB2
ITH2
R
B2
10.5k
TRACK/SS1
TRACK/SS2
R
PG1 100k
PGOOD1
EXTV
V
OUT2
C
R
R
34.8k
CC
ITH2B
ITH1
20k
ITH2
OPT
R
PG2
100k
C
ITH1B
100pF
PGOOD2
ILIM
C
C
SS2
0.01µF
ITH2A
VPRG1
FREQ
470pF
C
C
ITH1A
1nF
SS1
0.01µF
DRVSET
PLLIN/MODE
DRVUV
R
FREQ
41.2k
INTV
GND
DRV
CC
CC
C
4.7µF
C
DRVCC
INTVCC
0.1µF
3892 TA03
TOP1, TOP2, BOT1, BOT2: RJK0651DPB
L1: COILCRAFT SER1360-472KL
L2: COILCRAFT SER1360-802KL
*V
OUT2
FOLLOWS V WHEN V ≤ 8.5V
IN IN
C
: SANYO 6TPE470M
OUT1A
C
: SANYO 10TPE330M
OUT2A
Figure 12. High Efficiency Dual 3.3V/8.5V Step-Down Converter with 6V Gate Drive
Efficiency and Power Loss
vs Load Current
100
90
80
70
60
50
40
30
20
10
0
10k
1k
EFFICIENCY
100
10
POWER LOSS
1
V
V
= 12V
OUT
IN
= 3.3V
0.1
0.0001 0.001
0.01
0.1
1
10
LOAD CURRENT (A)
3892 TA03b
38921fc
33
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
TYPICAL APPLICATIONS
VIN
4.5V TO 60V
C
2.2µF
x3
C
INA
33µF
INB
RUN1
TG1
VIN
RUN2
TG2
MTOP1
MTOP2
BOOST1
BOOST2
R
SNS2
L1
4.9µH
L2
6.5µH
C
B1
0.1µF
R
9mΩ
SNS1
C
B2
15mΩ
V
OUT2
V
0.1µF
OUT1
5V
5A
8.5V*
3A
SW1
SW2
C
C
C
OUT1B
22µF
C
OUT1A
220µF
OUT2A
68µF
OUT2B
4.7µF
MBOT1
MBOT2
BG1
BG2
LTC3892-1
+
+
SENSE1
SENSE2
R
R
A1
C
A2
C
1nF
SNS1
SNS2
357k
649k
1nF
–
–
SENSE1
SENSE2
V
FB1
ITH1
V
FB2
ITH2
R
68.1k
R
68.1k
B2
B1
TRACK/SS1
TRACK/SS2
R
15kk
EXTV
V
OUT2
R
15k
ITH2
CC
ITH1
C
C
ITH1B
100pF
ITH2B
68pF
FREQ
DRVSET
C
C
1.5nF
C
SS1
0.1µF
C
SS2
ITH1A
ITH2A
0.1µF
2.2nF
PLLIN/MODE
DRVUV
R
DRVCC
80.6k
INTV
GND
DRV
CC
CC
C
C
DRVCC
4.7µF
INTVCC
0.1µF
3892 TA05
TOP1, TOP2, BOT1, BOT2: BSZ123N08NS3
L1: WURTH 744314490
*V
OUT2
FOLLOWS V WHEN V ≤ 8.5V
IN IN
L2: WURTH 744314490
C
: SANYO 6TPB220ML
OUT1A
C
: SANYO 10TPC68M
OUT2A
Figure 13. High Efficiency Dual-Phase Step-Down 5V/8.5V Converter with 8V Gate Drive
38921fc
34
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3892#packaging for the most recent package drawings.
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation EA
9.60 – 9.80*
(.378 – .386)
7.56
(.298)
7.56
(.298)
28 2726 25 24 23 22 21 20 19 18 1716 15
6.60 ±0.10
4.50 ±0.10
3.05
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
(.120)
SEE NOTE 4
6.40
(.252)
BSC
3.05
(.120)
0.45 ±0.05
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
5
7
1
2
3
4
6
8
9 10 12 13 14
11
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE28 (EA) TSSOP REV L 0117
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN
FOR EXPOSED PAD ATTACHMENT
MILLIMETERS
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3. DRAWING NOT TO SCALE
38921fc
35
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3892#packaging for the most recent package drawings.
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.45 ±0.05
3.50 REF
(4 SIDES)
3.45 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
0.75 ±0.05
5.00 ±0.10
(4 SIDES)
31 32
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.45 ±0.10
3.50 REF
(4-SIDES)
3.45 ±0.10
(UH32) QFN 0406 REV D
0.200 REF
0.25 ±0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
38921fc
36
For more information www.linear.com/LTC3892
LTC3892/
LTC3892-1/LTC3892-2
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
1 to 38
A
12/15 Add LTC3892-2 Version
B
05/16 Modified graph, Oscillator Frequency vs Temperature
10
C
07/17 Corrected LTC3892-2 Part Marking
5
11
Corrected EXTV Pin Description
CC
38921fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
37
LTC3892/
LTC3892-1/LTC3892-2
TYPICAL APPLICATION
VIN
16V TO 60V
C
C
INB
INA
100µF
2.2µF
RUN1
TG1
VIN
RUN2
TG2
x5
MTOP1
MTOP2
x2
x2
BOOST1
BOOST2
L1
10µH
R
SNS1
3mΩ
L2
10µH
R
SNS2
3mΩ
C
C
B2
0.1µF
B1
VOUT
12V
0.1µF
SW1
SW2
30A
OUT2A
150µF
C
C
C
C
OUT1B
10µF
OUT1A
150µF
OUT2B
10µF
MBOT1
x2
MBOT2
x2
BG1
BG2
LTC3892-1
+
+
SENSE1
SENSE2
R
A1
100k
C
C
SNS1
SNS2
1nF
1nF
–
–
SENSE1
SENSE2
V
FB1
ITH1
V
FB2
ITH2
R
B1
7.15k
TRACK/SS1
TRACK/SS2
C
ITH2A
47pF
EXTV
VOUT
R
CC
ITH1
9.78k
C
C
SS1
0.1µF
ITH1B
47pF
C
ITH1A
4.7nF
FREQ
DRVSET
PLLIN/MODE
DRVUV
INTV
GND
DRV
CC
CC
R
FREQ
29.4k
TOP1, TOP2: BSC123N08NS3G
BOT1, BOT2: BSC047N08NS3G
L1, L2: COILCRAFT SER2918H-103KL
C
C
DRVCC
4.7µF
INTVCC
0.1µF
Figure 14. High Current Dual-Phase Single Output Step-Down 12V Converter
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V,
LTC3890/LTC3890-1 60V, Low I , Dual 2-Phase Synchronous Step-Down
LTC3890-2/LTC3890-3 DC/DC Controller with 99% Duty Cycle
Q
IN
0.8V ≤ V
≤ 24V, I = 50μA
Q
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LTC3891
LTC3864
LTC3899
LTC3859AL
60V, Low I , Synchronous Step-Down DC/DC Controller PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V,
Q
IN
with 99% Duty Cycle
0.8V ≤ V
≤ 24V, I = 50μA
OUT Q
60V, Low I , High Voltage DC/DC Controller
Fixed Frequency 50kHz to 850kHz, 3.5V ≤ V ≤ 60V,
IN
Q
with 100% Duty Cycle
0.8V ≤ V
≤ V , I = 40μA, MSOP-12E, 3mm × 4mm DFN-12
OUT IN Q
60V, Triple Output, Buck/Buck/Boost Synchronous
4.5V (Down to 2.2V after Start-Up) ≤ V ≤ 60V, V
Up to 60V,
IN
OUT
Controller with 29µA Burst Mode I
Buck V
Range: 0.8V to 60V, Boost V
Up to 60V
Q
OUT
OUT
38V, Low I , Triple Output, Buck/Buck/Boost Synchronous 4.5V (Down to 2.5V after Start-Up) ≤ V ≤ 38V, V
Up to 60V,
Q
IN
OUT
Controller with 28µA Burst Mode I
Buck V
Range: 0.8V to 24V, Boost V Up to 60V,
Q
OUT
OUT
LTC3857/LTC3857-1
LTC3858/LTC3858-1
38V, Low I , Dual Output 2-Phase Synchronous
PLL Fixed Operating Frequency 50kHz to 900kHz, 4V ≤ V ≤ 38V,
IN
Q
Step-Down DC/DC Controller with 99% Duty Cycle
0.8V ≤ V
≤ 24V, I = 50μA/170μA
OUT Q
LTC3807
38V, Low I , Synchronous Step-Down Controller with
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 38V,
IN
Q
24V Output Voltage Capability
0.8V ≤ V
≤ 24V, I = 50μA
OUT Q
38921fc
LT 0717 REV C • PRINTED IN USA
www.linear.com/LTC3892
38
LINEAR TECHNOLOGY CORPORATION 2015
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