LTC3897 [Linear]
150V Low IQ, Synchronous Step-Down DC/DC Controller;型号: | LTC3897 |
厂家: | Linear |
描述: | 150V Low IQ, Synchronous Step-Down DC/DC Controller |
文件: | 总38页 (文件大小:2317K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC7801
150V Low I , Synchronous
Q
Step-Down DC/DC Controller
FeaTures
DescripTion
TheLTC®7801isahighperformancestep-downswitching
regulator DC/DC controller that drives an all N-channel
synchronous power MOSFET stage that can operate from
input voltages up to 140V. A constant frequency current
mode architecture allows a phase-lockable frequency of
up to 850kHz.
n
Wide V Range: 4V to 140V (150V Abs Max)
IN
n
Wide Output Voltage Range: 0.8V to 60V
Adjustable Gate Drive Level: 5V to 10V (OPTI-DRIVE)
Low Operating I : 40μA (Shutdown = 10μA)
100% Duty Cycle Operation
n
n
Q
n
n
n
n
n
n
n
n
No External Bootstrap Diode Required
Selectable Gate Drive UVLO Thresholds
Onboard LDO or External NMOS LDO for DRV
The gate drivevoltage can beprogrammed from 5V to10V
to allow the use of logic or standard-level FETs to maxi-
mize efficiency. An integrated switch in the top gate driver
eliminates the need for an external bootstrap diode. An
internalchargepumpallowsfor100%dutycycleoperation.
CC
EXTV LDO Powers Drivers from V
CC
OUT
Phase-Lockable Frequency (75kHz to 850kHz)
Programmable Fixed Frequency (50kHz to 900kHz)
Selectable Continuous, Pulse-Skipping or Low Ripple
Burst Mode® Operation at Light Loads
Thelow40μAno-loadquiescentcurrentextendsoperating
run time in battery-powered systems. OPTI-LOOP® com-
pensation allows the transient response to be optimized
over a wide range of output capacitance and ESR values.
The LTC7801 features a precision 0.8V reference and
power good output indicator. The output voltage can be
programmedbetween0.8Vto60Vusingexternalresistors.
n
n
n
n
Adjustable Burst Clamp
Power Good Output Voltage Monitor
Programmable Input Overvoltage Lockout
Small 24-Lead 4mm × 5mm QFN or TSSOP Packages
applicaTions
L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, PolyPhase, Linear Technology and the Linear logo
are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their
respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620, 6144194,
6177787, 6580258.
n
Automotive and Industrial Power Systems
n
High Voltage Battery Operated Systems
n
Telecommunications Power Systems
Typical applicaTion
High Efficiency High Voltage 12V Output Step-Down Regulator
Efficiency and Power Loss
vs Load Current
V
IN
7V to 140V
100
90
80
70
60
50
40
30
20
10
0
10k
1k
100µF
V
RUN
IN
NDRV
DRV
TG
EFFICIENCY
0.1µF
*V
FOLLOWS V WHEN V < 12V
IN IN
OUT
CC
BOOST
6mΩ
33µH
4.7µF
V
OUT
LTC7801
12V*
SW
5A
INTV
CC
100
10
1
BG
V
= 24V
IN
150µF
x3
CPUMP_EN
0.1µF
POWER LOSS
V
IN
= 48V
SENSE+
ITH
1nF
SENSE–
SS
10k
EXTV
0.1µF
30.1k
CC
100pF
511k
FREQ
V
FB
0.0001 0.001
0.01
0.1
1
10
4.7nF
36.5k
LOAD CURRENT (A)
GND
7801 TA01b
7801 TA01a
7801f
1
For more information www.linear.com/LTC7801
LTC7801
absoluTe MaxiMuM raTings
(Note 1)
Input Supply Voltage (V )....................... –0.3V to 150V
DRVSET, CPUMP_EN Voltages..................... –0.3V to 6V
NDRV.................................................................(Note 9)
IN
Top Side Driver Voltage BOOST ............... –0.3V to 150V
Switch Voltage (SW)................................... –5V to 150V
EXTV Voltage ......................................... –0.3V to 14V
CC
DRV , (BOOST-SW) Voltages....................–0.3V to 11V
ITH, V Voltages......................................... –0.3V to 6V
CC
FB
BG, TG ...............................................................(Note 8)
SS, OVLO Voltages ...................................... –0.3V to 6V
Operating Junction Temperature Range (Notes 2, 3)
LTC7801E, LTC7801I.......................... –40°C to 125°C
LTC7801H.......................................... –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
RUN Voltage............................................. –0.3V to 150V
+
–
SENSE , SENSE Voltages ......................... –0.3V to 65V
PLLIN, PGOOD Voltages .............................. –0.3V to 6V
MODE, DRVUV Voltages .............................. –0.3V to 6V
FREQ Voltage............................................... –0.3V to 6V
pin conFiguraTion
TOP VIEW
TOP VIEW
+
–
1
2
SENSE
OVLO
INTV
24
23
22
21
20
19
18
17
16
15
14
13
SENSE
SS
3
V
24 23 22 21 20
CC
FB
V
1
2
3
4
5
6
7
19
18
17
16
15
14
13
RUN
FB
4
RUN
ITH
ITH
MODE
EXTV
CC
5
EXTV
MODE
GND
CC
V
IN
6
V
IN
25
25
GND
NDRV
7
NDRV
DRV
CRUMP_EN
PLLIN
CPUMP_EN
PLLIN
DRV
BG
CC
8
CC
9
BG
PGOOD
FREQ
PGOOD
BOOST
10
11
12
BOOST
SW
8
9
10 11 12
DRVSET
DRVUV
TG
UFD PACKAGE
24-LEAD (4mm × 5mm) PLASTIC QFN
FE PACKAGE
24-LEAD PLASTIC TSSOP
T
= 150°C, θ = 43°C/W
JA
JMAX
T
= 150°C, θ = 33°C/W
JA
JMAX
EXPOSED PAD (PIN 25) IS GND, MUST BE
SOLDERED TO PCB FOR RATED ELECTRICAL AND
THERMAL CHARACTERISTICS
EXPOSED PAD (PIN 25) IS GND, MUST BE
SOLDERED TO PCB FOR RATED ELECTRICAL AND
THERMAL CHARACTERISTICS
http://www.linear.com/product/LTC7801#orderinfo
orDer inForMaTion
LEAD FREE FINISH
LTC7801EFE#PBF
LTC7801IFE#PBF
LTC7801HFE#PBF
LTC7801EUFD#PBF
LTC7801IUFD#PBF
LTC7801HUFD#PBF
TAPE AND REEL
PART MARKING
LTC7801FE
LTC7801FE
LTC7801FE
7801
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
LTC7801EFE#TRPBF
LTC7801IFE#TRPBF
LTC7801HFE#TRPBF
LTC7801EUFD#TRPBF
LTC7801IUFD#TRPBF
LTC7801HUFD#TRPBF
24-Lead Plastic TSSOP
24-Lead Plastic TSSOP
24-Lead Plastic TSSOP
24-Lead (4mm × 5mm) Plastic QFN
24-Lead (4mm × 5mm) Plastic QFN
24-Lead (4mm × 5mm) Plastic QFN
7801
7801
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
7801f
2
For more information www.linear.com/LTC7801
LTC7801
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, VEXTVCC = 0V, VDRVSET = 0V
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
4
TYP
MAX
140
60
UNITS
l
V
V
V
Input Supply Operating Voltage Range (Note 10) DRVUV = 0V
Regulated Output Voltage Set Point
V
V
IN
0.8
OUT
FB
Regulated Feedback Voltage
(Note 4); ITH Voltage = 1.2V
0°C to 85°C
0.792
0.788
0.800
0.800
0.808
0.812
V
V
l
I
Feedback Current
(Note 4)
–0.006
0.002
0.050
0.02
µA
FB
Reference Voltage Line Regulation
Output Voltage Load Regulation
(Note 4) V = 4.5V to 150V
%/V
IN
(Note 4) Measured in Servo Loop,
∆ITH Voltage = 1.2V to 0.7V
l
l
0.01
0.1
%
(Note 4) Measured in Servo Loop,
∆ITH Voltage = 1.2V to 1.6V
–0.01
2
–0.1
%
g
Transconductance Amplifier gm
Input DC Supply Current
(Note 4) ITH = 1.2V, Sink/Source 5µA
mmho
m
I
(Note 5) V
= 0V
DRVSET
Q
Pulse Skip or Forced Continuous Mode V = 0.83V (No Load)
2.5
40
10
mA
µA
µA
FB
Sleep Mode
V
= 0.83V (No Load)
55
20
FB
Shutdown
RUN = 0V
UVLO
Undervoltage Lockout
DRV Ramping Up
CC
l
l
DRVUV = 0V
4.0
7.5
4.2
7.8
V
V
DRVUV = INTV , DRVSET = INTV
CC
CC
DRV Ramping Down
CC
l
l
DRVUV = 0V
3.6
6.4
3.8
6.7
4.0
7.0
V
V
DRVUV = INTV , DRVSET = INTV
CC
CC
l
V
V
ON
RUN Pin ON Threshold
V
V
Rising
1.1
1.2
80
1.3
V
mV
V
RUN
RUN
Hyst RUN Pin Hysteresis
Overvoltage Lockout Threshold
RUN
l
OVLO
Rising
1.1
1.2
100
1
1.3
OVLO
OVLO Hyst OVLO Hysteresis
OVLO Delay
mV
µs
Feedback Overvoltage Protection
Measured at V , Relative to Regulated V
7
10
13
1
%
FB
FB
+
I
I
+
–
SENSE Pin Current
µA
SENSE
–
–
–
SENSE Pin Current
SENSE < V
– 0.5V
+ 0.5V
1
µA
µA
SENSE
INTVCC
INTVCC
SENSE > V
850
99
Maximum Duty Factor
In Dropout
CPUMP_EN = 0V, FREQ = 0V
98
100
%
CPUMP_EN = INTV
CC
I
Soft-Start Charge Current
V
V
= 0V
8
10
75
12
84
µA
SS
SS
FB
l
V
Maximum Current Sense Threshold
= 0.7V, V
– = 3.3V
SENSE
66
mV
SENSE(MAX)
7801f
3
For more information www.linear.com/LTC7801
LTC7801
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, VEXTVCC = 0V, VDRVSET = 0V
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Gate Driver
TG Pull-up On-Resistance
V
V
= INTV
= INTV
2.2
1.0
Ω
Ω
DRVSET
DRVSET
CC
TG Pull-down On-Resistance
BG Pull-up On-Resistance
BG Pull-down On-Resistance
2.0
1.0
Ω
Ω
CC
BOOST to DRV Switch On-Resistance V = 0V, V
= INTV
CC
11
Ω
CC
SW
DRVSET
TG Transition Time:
Rise Time
(Note 6) V
= INTV
DRVSET
= 3300pF
= 3300pF
CC
C
C
25
15
ns
ns
LOAD
LOAD
Fall Time
BG Transition Time:
Rise Time
(Note 6) V
= INTV
DRVSET
CC
C
C
= 3300pF
25
15
ns
ns
LOAD
LOAD
Fall Time
= 3300pF
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
C
C
= 3300pF each driver, V
= INTV
= INTV
LOAD
DRVSET
DRVSET
CC
CC
55
ns
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
= 3300pF each driver, V
LOAD
50
80
ns
ns
t
TG Minimum On-Time
(Note 7) V
= INTV
DRVSET CC
ON(MIN)
Charge Pump for High Side Driver Supply
Charge Pump Output Current
I
V
V
=16V, V = 12V, V
= 0V
= 0V
65
55
µA
µA
CPUMP
BOOST
BOOST
SW
FREQ
FREQ
=19V, V = 12V, V
SW
DRV LDO Regulator
CC
DRV Voltage from NDRV LDO
NDRV Driving External NFET, V
= 0V
CC
EXTVCC
Regulator
7V < V < 150V, DRVSET = 0V
5.8
9.6
6.0
10.0
6.2
10.4
V
V
IN
11V < V < 150V, DRVSET = INTV
IN
CC
DRV Load Regulation from NDRV
NDRV Driving External NFET
CC
CC
LDO Regulator
I
= 0mA to 50mA, V
= 0V
EXTVCC
0
1.0
%
DRV Voltage from Internal V LDO NDRV = DRV , V = 0V
CC EXTVCC
CC
IN
7V < V < 150V, DRVSET = 0V
5.6
9.5
5.85
9.85
6.1
10.3
V
V
IN
11V < V < 150V, DRVSET = INTV
IN
CC
DRV Load Regulation from V LDO
I
= 0mA to 50mA, V
= 0V
CC
IN
CC
EXTVCC
DRVSET = 0V
1.4
0.9
2.5
2.0
%
%
DRVSET = INTV
CC
DRV Voltage from Internal EXTV
7V < V < 13V, DRVSET = 0V
EXTVCC
5.8
9.6
6.0
10.0
6.2
10.4
V
V
CC
CC
LDO
11V < V
< 13V, DRVSET = INTV
EXTVCC
CC
DRV Load Regulation from Internal
I
= 0mA to 50mA
CC
CC
EXTV LDO
DRVSET = 0V, V
= 8.5V
EXTVCC
0.7
0.5
2.0
2.0
%
%
CC
DRVSET = INTV , V
= 13V
CC EXTVCC
EXTV LDO Switchover Voltage
EXTV Ramping Positive
CC
CC
DRVUV = 0V
4.5
7.4
4.7
7.7
4.9
8.0
V
V
DRVUV = INTV , DRVSET = INTV
CC
CC
EXTV Hysteresis
250
5.0
7.0
9.0
mV
CC
Programmable DRV
Programmable DRV
Programmable DRV
R
= 50k
CC
CC
CC
DRVSET
NDRV Driving External NFET, V
= 0V
= 0V
= 0V
V
EXTVCC
EXTVCC
EXTVCC
R
= 70k
DRVSET
NDRV Driving External NFET, V
6.4
7.6
V
R
= 90k
DRVSET
NDRV Driving External NFET, V
V
7801f
4
For more information www.linear.com/LTC7801
LTC7801
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, VEXTVCC = 0V, VDRVSET = 0V
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
INTV LDO Regulator
CC
INTVCC
V
INTV Voltage
I
CC
= 0mA to 2mA
4.7
5.0
5.2
V
CC
Oscillator and Phase-Locked Loop
Programmable Frequency
Programmable Frequency
Programmable Frequency
Low Fixed Frequency
R
R
R
= 25k, PLLIN = DC Voltage
= 65k, PLLIN = DC Voltage
=105k, PLLIN = DC Voltage
= 0V, PLLIN = DC Voltage
105
440
835
350
535
kHz
kHz
kHz
kHz
kHz
kHz
FREQ
FREQ
FREQ
FREQ
FREQ
375
505
V
V
320
485
75
380
585
850
High Fixed Frequency
= INTV , PLLIN = DC Voltage
CC
l
f
Synchronizable Frequency
PLLIN = External Clock
SYNC
l
l
PLLIN Input High Level
PLLIN Input Low Level
PLLIN = External Clock
PLLIN = External Clock
2.8
V
V
0.5
PGOOD Output
V
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
I
= 2mA
= 3.3V
0.02
0.04
10
V
PGL
PGOOD
I
V
V
µA
PGOOD
PGOOD
with Respect to Set Regulated Voltage
FB
V
Ramping Negative
–13
7
–10
2.5
–7
13
%
%
FB
Hysteresis
V
with Respect to Set Regulated Voltage
FB
V
Ramping Positive
10
2.5
%
%
FB
Hysteresis
Delay for Reporting a Fault
40
µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Ratings for extended periods may affect device reliability and
lifetime.
junction temperature may impair device reliability or permanently damage
the device.
Note 4: The LTC7801 is tested in a feedback loop that servos V to a
ITH
specified voltage and measures the resultant V . The specification at 85°C
FB
is not tested in production and is assured by design, characterization and
correlation to production testing at other temperatures (125°C for the
LTC7801E and LTC7801I, 150°C for the LTC7801H). For the LTC7801I
and LTC7801H, the specification at 0°C is not tested in production and is
assured by design, characterization and correlation to production testing
at –40°C.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See the Applications information
section.
Note 2: The LTC7801 is tested under pulsed load conditions such that T ≈
J
T . The LTC7801E is guaranteed to meet performance specifications from
A
0°C to 85°C. Specifications over the –40°C to 125°C operating junction
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC7801I is guaranteed over the
–40°C to 125°C operating junction temperature range and the LTC7801H
is guaranteed over the –40°C to 150°C operating junction temperature
range. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance
and other environmental factors. High temperatures degrade operating
lifetimes; operating lifetime is derated for junction temperatures greater
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
than 125ºC. The junction temperature (T , in °C) is calculated from the
J
peak-to-peak ripple current >40% of I
(See Minimum On-Time
MAX
ambient temperature (T , in °C) and power dissipation (P , in Watts)
A
D
Considerations in the Applications Information section).
according to the formula:
Note 8: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only, otherwise permanent damage may
occur.
T = T + (P • θ )
JA
J
A
D
where θ = 33°C/W for the TSSOP package and θ = 43°C/W for the
JA
JA
QFN package.
Note 9: Do not apply a voltage or current source to the NDRV pin, other
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
than tying NDRV to DRV when not used. If used it must be connected
CC
to capacitive loads only (see DRV Regulators in the Applications
CC
Information section), otherwise permanent damage may occur.
Note 10: The minimum input supply operating range is dependent on the
DRV UVLO thresholds as determined by the DRVUV pin setting.
CC
7801f
5
For more information www.linear.com/LTC7801
LTC7801
Typical perForMance characTerisTics
Efficiency and Power Loss
vs Load Current
Efficiency vs Load Current
Efficiency vs Input Voltage
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
10k
1k
100
98
96
94
92
90
88
86
84
82
80
BURST EFFICIENCY
FCM LOSS
PULSE–SKIPPING
LOSS
100
10
1
BURST LOSS
PULSE–SKIPPING
EFFICIENCY
V
= 24V
IN
IN
IN
IN
FIGURE 13 CIRCUIT
FIGURE 13 CIRCUIT
V
V
V
= 48V
FIGURE 13 CIRCUIT
= 12V
V
I
= 12V
LOAD
V
OUT
= 24V
= 100V
= 140V
OUT
IN
= 4A
V
= 12V
V
OUT
FCM EFFICIENCY
0.01 0.1
LOAD CURRENT (A)
0.0001 0.001
0.01
0.1
1
10
0.0001 0.001
1
10
20
40
60
80
100
120
140
LOAD CURRENT (A)
INPUT VOLTAGE (V)
7801 G02
7801 G01
7801 G03
Load Step Burst Mode
Operation
Load Step
Pulse-Skipping Mode
Load Step Forced
Continuous Mode
V
V
V
OUT
OUT
OUT
100mV/DIV
100mV/DIV
100mV/DIV
AC COUPLED
AC COUPLED
AC COUPLED
I
I
I
L
L
L
1A/DIV
1A/DIV
1A/DIV
7801 G04
7801 G04
7801 G06
200µs/DIV
200µs/DIV
200µs/DIV
FIGURE 13 CIRCUIT
V
IN
= 24V
V
= 24V
V
= 24V
IN
IN
FIGURE 13 CIRCUIT
FIGURE 13 CIRCUIT
Regulated Feedback Voltage
vs Temperature
Inductor Current at Light Load
Soft Start-Up
808
806
804
802
800
798
796
794
792
V
OUT
2V/DIV
FORCED
CONTINUOUS
MODE
BURST MODE
OPERATION
2A/DIV
RUN
2V/DIV
PULSE
SKIPPING
MODE
7801 G08
7801 G07
2ms/DIV
FIGURE 13 CIRCUIT
200µs/DIV
V
= 24V
V
= 24V
IN
IN
FIGURE 13 CIRCUIT
–75 –50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
7801 G09
7801f
6
For more information www.linear.com/LTC7801
LTC7801
Typical perForMance characTerisTics
DRVCC and EXTVCC
vs Load Current
EXTVCC Switchover and DRVCC
Voltages vs Temperature
EXTVCC Switchover and DRVCC
Voltages vs Temperature
6.5
6.0
5.5
5.0
4.5
4.0
6.5
6.0
5.5
5.0
4.5
4.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
EXTV = 8.5V
EXTV = 8.5V
CC
CC
NDRV LDO (NDRV FET),
EXTVCC = 0V
NDRV LDO (NDRV NFET),
NDRV LDO (NDRV FET),
EXTV = 0V
CC
EXTV = 0V
CC
V
LDO (No NDRV NFET),
CC
IN
V
LDO (No NDRV FET),
CC
IN
V
LDO (No NDRV FET),
CC
IN
EXTV = 0V
EXTV = 8.5V
EXTV = 0V
CC
EXTV = 0V,
EXTV RISING
CC
EXTV FALLING
CC
EXTV RISING
CC
EXTV = 5V
CC
EXTV FALLING
CC
DRVUV = DRVSET = 0V
DRVUV = DRVSET = 0V
DRVUV = DRVSET = INTV
CC
0
20
40
60
80
100
–75 –50 –25
0
25 50 75 100 125 150
–75 –50 –25
0
25 50 75 100 125 150
LOAD CURRENT (mA)
TEMPERATURE (°C)
TEMPERATURE (°C)
7801 G10
7801 G11
7801 G12
SENSE– Pin Input Current
vs VSENSE Voltage
SENSE– Pin Input Bias Current
vs Temperature
Undervoltage Lockout Threshold
vs Temperature
1000
900
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
RISING
DRVUV = INTV
CC
V
≥ INTV + 0.5V
OUT
CC
FALLING
DRVUV = 0V
RISING
FALLING
25 50 75 100 125 150
V
OUT
≤ INTV – 0.5V
CC
–75 –50 –25
0
25 50 75 100 125 150
0
5
10 15 20 25 30 35 40 45 50 55 60 65
COMMON MODE VOLTAGE (V)
–75 –50 –25
0
TEMPERATURE (°C)
V
TEMPERATURE (°C)
SENSE
7801 G14
7801 G13
7801 G15
Maximum Current Sense
Threshold vs ITH Voltage
RUN/OVLO Threshold
vs Temperature
Foldback Current Limit
100
90
80
70
60
50
40
30
20
10
0
100
80
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
5% DUTY CYCLE
OVLO RISING
PULSE–SKIPPING
60
RUN RISING
BURST MODE
OPERATION
40
20
RUN FALLING
0
–20
–40
OVLO FALLING
FORCED CONTINUOUS
0
100 200 300 400 500 600 700 800
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
(V)
–75 –50 –25
0
25 50 75 100 125 150
FEEDBACK VOLTAGE (mV)
V
ITH
TEMPERATURE (°C)
7801 G16
7801 G17
7801 G18
7801f
7
For more information www.linear.com/LTC7801
LTC7801
Typical perForMance characTerisTics
Shutdown Current
vs Input Voltage
DRVCC Line Regulation
Shutdown Current vs Temperature
11
10
9
20
18
16
14
12
10
8
30
25
20
15
10
5
EXTV = 0V
V
= 12V
CC
IN
DRVSET = INTV
CC
NDRV FET
8
No NDRV FET
7
6
V
= 6.3V
IN
DRVSET = 0V
4
6
2
5
0
0
0
15 30 45 60 75 90 105 120 135 150
–75 –50 –25
0
25 50 75 100 125 150
0
15 30 45 60 75 90 105 120 135 150
INPUT VOLTAGE (V)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
7801 G19
7801 G20
7801 G21
Oscillator Frequency
vs Temperature
SS Pull-Up Current
vs Temperature
Quiescent Current vs Temperature
100
90
80
70
60
50
40
30
20
10
0
600
550
500
450
400
350
300
12.0
11.5
11.0
10.5
10.0
9.5
V
= 12V
IN
BURST MODE OPERATION
FREQ = INTV
CC
DRVSET = 70kΩ
DRVSET = INTV
CC
DRVSET = 0V
9.0
8.5
FREQ = 0V
8.0
–75 –50 –25
0
25 50 75 100 125 150
–75 –50 –25
0
25 50 75 100 125 150
–75 –50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
7801 G22
7801 G23
7801 G24
Boost Charge Pump Voltage
vs SW Voltage
BOOST Charge Pump Charging
Current vs Frequency
BOOST Charge Pump Charging
Current vs SW Voltage
10
9
8
7
6
5
4
3
2
1
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
FREQ = 350kHz
V
V
= 16V
BOOST
SW
= 12V
V
- V = 4V
SW
BOOST
150°C
V
- V = 7V
SW
25°C
BOOST
–55°C
150°C
25°C
–55°C
150°C
25°C
–55°C
FREQ = 350kHz
10MΩ BETWEEN BOOST AND SW
0
5
10 15 20 25 30 35 40 45 50 55 60 65
SW VOLTAGE (V)
0
100 200 300 400 500 600 700 800 9001000
0
5
10 15 20 25 30 35 40 45 50 55 60 65
OPERATING FREQUENCY (kHz)
SW VOLTAGE (V)
7801 G25
7801 G26
7801 G27
7801f
8
For more information www.linear.com/LTC7801
LTC7801
pin FuncTions (QFN/TSSOP)
V
(Pin 1/Pin 3): Feedback Input. This pin receives the
to a fixed low frequency of 350kHz. Connecting the pin
FB
remotelysensedfeedbackvoltagefromanexternalresistor
to INTV forces the VCO to a fixed high frequency of
CC
divider across the output.
535kHz. Other frequencies between 50kHz and 900kHz
can be programmed by using a resistor between FREQ
and GND. An internal 20µA pull-up current develops the
voltage to be used by the VCO to control the frequency.
ITH (Pin 2/Pin 4): Error Amplifier Output and Switching
Regulator Compensation Point. The current comparator
trip point increases with this control voltage.
DRVSET (Pin 9/Pin 11): DRV Regulation Program Pin.
CC
MODE (Pin 3/Pin 5): Mode Select and Burst Clamp Adjust
Input. This input determines how the LTC7801 operates at
light loads. Pulling this pin to ground selects Burst Mode
operation with the burst clamp level defaulting to 25% of
This pin sets the regulated output voltage of the DRV
CC
linear regulator. Tying this pin to GND sets DRV to 6.0V.
CC
TyingthispintoINTV setsDRV to10V. Othervoltages
CC
CC
between 5V and 10V can be programmed by placing a
resistor (50k to 100k) between the DRVSET pin and GND.
An internal 20µA pull-up current develops the voltage to
V
. Tying this pin to a voltage between 0.5V and
SENSE(MAX)
1.0V selects Burst Mode operation and adjusts the burst
clamp between 10% and 60%. Tying this pin to INTV
CC
be used as the reference to the DRV LDO.
CC
forcescontinuousinductorcurrentoperation.Tyingthispin
to a voltage greater than 1.4V and less than INTV – 1.3V
DRVUV (Pin 10/Pin 12): DRV UVLO Program Pin. This
CC
CC
selects pulse-skipping operation.
pin determines the higher or lower DRV UVLO and
CC
EXTV switchover thresholds, as listed on the Electrical
CC
GND (Pin 4, Exposed Pin 25/Pin 6, Exposed Pad Pin 25):
Ground. All GND pins must be tied together for operation.
The exposed pad must be soldered to PCB ground for
rated electrical and thermal performance.
Characteristics table. Connecting DRVUV to GND chooses
the lower thresholds whereas tying DRVUV to INTV
chooses the higher thresholds. Do not float this pin.
CC
TG (Pin 11/Pin 13): High Current Gate Drives for Top N-
CPUMP_EN (Pin 5/Pin 7): Charge Pump Enable Pin for
the Top Gate Driver Boost Supply. Tying this pin to INTV
enables the boost supply charge pump and allows for
100% duty cycle operation in dropout. Tying this pin to
GND disables thecharge pump andenables boost refresh,
allowing for 99% duty cycle operation in dropout. Do not
float this pin.
Channel MOSFET. This is the output of floating high side
CC
driver with a voltage swing equal to DRV superimposed
CC
on the switch node voltage SW.
SW (Pin 12/Pin 14): Switch Node Connection to Inductor.
BOOST (Pin 13/Pin 15): Bootstrapped Supply to the Top-
side Floating Driver. A capacitor is connected between the
BOOST and SW pins. Voltage swing at the BOOST pin is
PLLIN (Pin 6/ Pin 8): External Synchronization Input to
Phase Detector. When an external clock is applied to this
pin, the phase-locked loop will force the rising TG signal
to be synchronized with the rising edge of the external
clock. If the MODE pin is set to Forced Continuous Mode
or Burst Mode operation, then the regulator operates in
ForcedContinuousModewhensynchronized.IftheMODE
pin is set to pulse-skipping mode, then the regulator oper-
ates in pulse-skipping mode when synchronized.
from approximately DRV to (V + DRV ).
CC
IN
CC
BG (Pin 14/Pin 16): High Current Gate Drive for Bottom
(Synchronous) N-Channel MOSFET. Voltage swing at this
pin is from ground to DRV .
CC
DRV (Pin 15/Pin 17): Output of the Internal or External
CC
Low Dropout Regulators. The gate drivers are powered
from this voltage source. The DRV voltage is set by
CC
the DRVSET pin. Must be decoupled to ground with a
PGOOD (Pin 7/Pin 9): Open-Drain Logic Output. PGOOD
minimum of 4.7µF ceramic or other low ESR capacitor,
is pulled to ground when the voltage on the V pin is not
FB
as close as possible to the IC. Do not use the DRV pin
CC
within 10% of its set point.
for any other purpose.
FREQ (Pin 8/Pin 10): Frequency Control Pin for the In-
ternal VCO. Connecting the pin to GND forces the VCO
7801f
9
For more information www.linear.com/LTC7801
LTC7801
pin FuncTions (QFN/TSSOP)
NDRV (Pin 16/Pin 18): Drive Output for External Pass
nected between INTV and GND, as close as possible to
CC
Device of the NDRV LDO Linear Regulator for DRV .
the LTC7801.
CC
Connect this pin to the gate of an external NMOS pass
OVLO(Pin21/Pin23):OvervoltageLockoutInput.Avoltage
device. An internal charge pump allows NDRV to regulate
on this pin above 1.2V disables switching of the controller.
above V for low dropout performance. To disable this
IN
TheDRV andINTV suppliesmaintainregulationduring
CC
CC
external NDRV LDO, tie NDRV to DRV .
CC
an OVLO event. Exceeding the OVLO threshold triggers a
soft-start reset. If the OVLO function is not used, connect
this pin to GND.
V (Pin 17/Pin 19): Main Supply Pin. A bypass capacitor
IN
should be tied between this pin and the GND pins.
+
EXTV (Pin 18/Pin 20): External Power Input to an
SENSE (Pin 22/Pin 24): The (+) Input to the Differential
CC
Internal LDO linear regulator Connected to DRV . This
Current Comparator. The ITH pin voltage and controlled
CC
–
+
LDO supplies DRV power from EXTV , bypassing the
offsets between the SENSE and SENSE pins in conjunc-
CC
CC
internal LDO powered from V or the external NDRV LDO
tion with R
set the current trip threshold.
IN
SENSE
whenever EXTV is higher than its switchover threshold
–
CC
SENSE (Pin 23/Pin 1): The (–) Input to the Differential
(4.7V or 7.7V depending on the DRVUV pin). See DRV
–
CC
CurrentComparator.WhenSENSE isgreaterthanINTV ,
CC
Regulators in the Applications Information section. Do
–
the SENSE pin supplies power to the current comparator.
not exceed 14V on this pin. Do not connect EXTV to a
CC
SS (Pin 24/Pin 2): Soft-Start Input. The LTC7801 regu-
lates the V voltage to the smaller of 0.8V or the voltage
voltage greater than V . If not used, connect to GND and
IN
place a 330k or smaller resistor between INTV and SS.
FB
CC
on the SS pin. An internal 10μA pull-up current source is
connected to this pin. A capacitor to ground at this pin
sets the ramp time to final regulated output voltage. The
SS pin is also used for the Regulator Shutdown (REGSD)
feature. A 5μA/1μA pull-down current can be connected
RUN (Pin 19/Pin 21): Run Control Input. Forcing this pin
below 1.12V shuts down the controller. Forcing this pin
below 0.7V shuts down the entire LTC7801, reducing
quiescent current to approximately 10µA. This pin can be
tied to V for always-on operation. Do not float this pin.
IN
on SS depending on the state of the EXTV LDO and the
CC
INTV (Pin 20/Pin 22): Output of the Internal 5V Low
voltage on SS. See Regulator Shutdown in the Operation
CC
Dropout Regulator. Many of the low voltage analog and
digital circuits are powered from this voltage source. A
low ESR 0.1µF ceramic bypass capacitor should be con-
sectionformoreinformation.TodefeattheREGSDfeature,
place a 330k or smaller resistor between INTV and SS.
CC
See Soft-Start Pin in the Applications Information section
for more information on defeating REGSD.
7801f
10
For more information www.linear.com/LTC7801
LTC7801
FuncTional DiagraM
PGOOD
CPUMP_EN
0.88V
EA–
EN
DRV
CC
CHARGE
PUMP
OVLO
0.72V
V
IN
BOOST
TG
1.2V
CB
RUN
C
IN
15M
TOP
DROPOUT
DETECT
S
Q
BOT
SW
3V
SWITCH
LOGIC
R
MODE
TOPON
DRV
CC
BG
BOT
GND
0.425V
SLEEP
CLK
VCO
L
R
SENSE
20µA
IR
V
OUT
ICMP
FREQ
C
OUT
PFD
+
SENSE
2mV
1.8V
BCLAMP
–
SENSE
PLLIN
SYNC
DET
V
FB
R
EA–
B
SLOPE COMP
100k
EA
0.80V
SS
R
A
0.88V
20µA
2.0V
1.2V
DRVSET
DRVUV
C
C1
ITH
EXTV
CC
DRV LDO/UVLO
CC
V
CONTROL
IN
3.5V
10µA
V
R
C
IN
C
C2
SHDN
CHARGE
PUMP
EN
EN
EN
4.7V/
7.7V
NDRV
SS
NDRV LDO
V
LDO
IN
EXTV
LDO
CC
DRV
C
SS
CC
REGSD
INTV
CC
LDO
4R
5µA/1uA
R
INTV
CC
7801 BD01
7801f
11
For more information www.linear.com/LTC7801
LTC7801
operaTion
Main Control Loop
If the NDRV LDO is being used with an external N-channel
MOSFET, the gate of the MOSFET tied to the NDRV pin
The LTC7801 uses a constant frequency, current mode
step-down architecture. During normal operation, the
external top MOSFET is turned on when the clock sets
is driven such that DRV regulates above the V LDO
CC
IN
regulationpoint,causingallDRV currenttoflowthrough
CC
theexternalN-channelMOSFET,bypassingtheinternalV
IN
the R latch, and is turned off when the main current
S
LDO pass device. If the NDRV LDO is not being used, all
DRV current flows through the internal P-channel pass
comparator, ICMP, resets the R latch. The peak inductor
S
CC
current at which ICMP trips and resets the latch is con-
trolled by the voltage on the ITH pin, which is the output
of the error amplifier, EA. The error amplifier compares
device between the V and DRV pins.
IN
CC
If EXTV is taken above its switchover voltage, the V
CC
IN
the output voltage feedback signal at the V pin (which
and NDRV LDOs are turned off and an EXTV LDO is
FB
CC
is generated with an external resistor divider connected
turned on. Once enabled, the EXTV LDO supplies power
CC
across the output voltage, V , to ground) to the internal
from EXTV to DRV . Using the EXTV pin allows the
OUT
CC CC CC
0.800Vreferencevoltage.Whentheloadcurrentincreases,
DRV power to be derived from a high efficiency external
CC
it causes a slight decrease in V relative to the reference,
source such as the LTC7801 switching regulator output.
FB
which causes the EA to increase the ITH voltage until the
TheINTV supplypowersmostoftheotherinternalcircuits
CC
average inductor current matches the new load current.
in the LTC7801. The INTV LDO regulates to a fixed value
CC
After the top MOSFET is turned off each cycle, the bottom
MOSFETisturnedonuntileithertheinductorcurrentstarts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
of 5V and its power is derived from the DRV supply.
CC
Top MOSFET Driver and Charge Pump (CPUMP_EN Pin)
The top MOSFET driver is biased from the floating boot-
strap capacitor, C , which normally recharges during each
B
DRV /EXTV /INTV Power
CC
CC
CC
cycle through an internal switch whenever SW goes low.
Power for the top and bottom MOSFET drivers is derived
from the DRV pin. The DRV supply voltage can be
Iftheinputvoltagedecreasestoavoltageclosetoitsoutput,
the loop may enter dropout and attempt to turn on the top
MOSFET continuously. The LTC7801 includes an internal
charge pump that allows the top MOSFET to be turned on
continuously at 100% duty cycle. This charge pump deliv-
CC
CC
programmed from 5V to 10V by setting the DRVSET pin.
Two separate LDOs (low dropout linear regulators) can
provide power from V to DRV . The internal V LDO
IN
CC
IN
usesaninternalP-channelpassdevicebetweentheV and
IN
ers current to C and is enabled when the CPUMP_EN pin
B
DRV pins. To prevent high on-chip power dissipation in
CC
is tied to INTV . Tying CPUMP_EN to GND disables the
CC
highinputvoltageapplications,theLTC7801alsoincludes
charge pump and causes the dropout detector to force the
an NDRV LDO that utilizes the NDRV pin to supply power
top MOSFET off for about one twelfth of the clock period
to DRV by driving the gate of an external N-channel
CC
every tenth cycle to allow C to recharge, resulting in an
B
MOSFET acting as a linear regulator with its source con-
effective 99% max duty cycle.
nected to DRV and drain connected to V . The NDRV
CC
IN
LDO includes an internal charge pump that allows NDRV
to be driven above V for low dropout performance.
Shutdown and Start-Up (RUN, SS Pins)
IN
The LTC7801 can be shut down using the RUN pin. Con-
necting the RUN pin below 1.12V shuts down the main
control loop. Connecting the RUN pin below 0.7V disables
the controller and most internal circuits, including the
When the EXTV pin is tied to a voltage below its swi-
CC
tchover voltage (4.7V or 7.7V depending on the DRVUV
pin), the V and NDRV LDOs are enabled and one of
IN
them supplies power from V to DRV . The V LDO
IN
CC
IN
DRV andINTV LDOs. Inthisstate, theLTC7801draws
CC
CC
has a slightly lower regulation point than the NDRV LDO.
only 10μA of quiescent current.
7801f
12
For more information www.linear.com/LTC7801
LTC7801
operaTion
The RUN pin has no internal pull-up current, so the pin
must be externally pulled up or driven directly by logic.
TheRUNpincantolerateupto150V(absolutemaximum),
In Burst Mode operation, if the average inductor current
is higher than the load current, the error amplifier, EA, will
decrease the voltage on the ITH pin. When the ITH volt-
age drops below 0.425V, the internal sleep signal goes
high (enabling sleep mode) and both external MOSFETs
are turned off. The ITH pin is then disconnected from the
output of the EA and parked at 0.450V.
so it can be conveniently tied to V in always-on applica-
IN
tions where the controller is enabled continuously and
never shut down.
The start-up of the controller’s output voltage V
is
OUT
controlled by the voltage on the SS pin. When the voltage
on the SS pin is less than the 0.8V internal reference, the
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC7801 draws
to only 40μA. In sleep mode, the load current is supplied
by the output capacitor. As the output voltage decreases,
the EA’s output begins to rise. When the output voltage
drops enough, the ITH pin is reconnected to the output
of the EA, the sleep signal goes low, and the controller
resumes normal operation by turning on the top external
MOSFET on the next cycle of the internal oscillator.
LTC7801 regulates the V voltage to the SS pin voltage
FB
instead of the 0.8V reference. This allows the SS pin to
be used to program a soft-start by connecting an exter-
nal capacitor from the SS pin to GND. An internal 10μA
pull-up current charges this capacitor creating a voltage
ramp on the SS pin. As the SS voltage rises linearly from
0V to 0.8V (and beyond), the output voltage V
smoothly from zero to its final value.
rises
OUT
When the controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus,
the controller operates discontinuously.
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Forced Continuous Mode) (MODE Pin)
The LTC7801 can be enabled to enter high efficiency
BurstModeoperation, constantfrequency pulse-skipping
mode, or forced continuous conduction mode at light load
currents. To select Burst Mode operation, tie the MODE
pin to GND or a voltage between 0.5V and 1.0V. To select
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than in
Burst Mode operation. However, continuous operation
has the advantage of lower output voltage ripple and less
interferencetoaudiocircuitry.Inforcedcontinuousmode,
the output ripple is independent of load current.
forced continuous operation, tie the MODE pin to INTV .
CC
To select pulse-skipping mode, tie the MODE pin to a DC
voltage greater than 1.4V and less than INTV – 1.3V.
CC
This can be done with a simple resistor divider off INTV ,
CC
with both resistors being 100k.
When the controller is enabled for Burst Mode operation,
the minimum peak current in the inductor (burst clamp) is
adjustable and can be programmed by the voltage on the
MODE pin. Tying the MODE pin to GND sets the default
burst clamp to approximately 25% of the maximum sense
voltage even when the voltage on the ITH pin indicates a
lowervalue.Avoltagebetween0.5Vand1.0VontheMODE
pin programs the burst clamp linearly between 10% and
60% of the maximum sense voltage.
WhentheMODEpinisconnectedforpulse-skippingmode,
the LTC7801 operates in PWM pulse-skipping mode at
light loads. In this mode, constant frequency operation
is maintained down to approximately 1% of designed
maximum output current. At very light loads, the current
comparator, ICMP, may remain tripped for several cycles
and force the external top MOSFET to stay off for the same
number of cycles (i.e., skipping pulses). The inductor cur-
rent is not allowed to reverse (discontinuous operation).
7801f
13
For more information www.linear.com/LTC7801
LTC7801
operaTion
This mode, like forced continuous operation, exhibits low
output ripple as well as low audio noise and reduced RF
interference as compared to Burst Mode operation. It pro-
videshigherlowcurrentefficiencythanforcedcontinuous
mode, but not nearly as high as Burst Mode operation.
At high output voltages, the efficiency in pulse-skipping
mode is comparable to force continuous mode.
The VCO input voltage is prebiased to the operating fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
If the PLLIN pin is clocked by an external clock source to
use the phase-locked loop (see Frequency Selection and
Phase-Locked Loop section), then the LTC7801 operates
in forced continuous operation when the MODE pin is
set to forced continuous or Burst Mode operation. The
controller operates in pulse-skipping mode when clocked
by an external clock source with the MODE pin set to
pulse-skipping mode.
The typical capture range of the LTC7801’s phase-locked
loop is from approximately 55kHz to 1MHz, with a guaran-
tee to be between 75kHz and 850kHz. In other words, the
LTC7801’s PLL is guaranteed to lock to an external clock
source whose frequency is between 75kHz and 850kHz.
It is recommended that the external clock source swing
from ground (0V) to at least 2.8V.
Frequency Selection and Phase-Locked Loop (FREQ
and PLLIN Pins)
Input Supply Overvoltage Lockout (OVLO Pin)
TheLTC7801implementsaprotectionfeaturethatinhibits
switching when the input voltage rises above a program-
mableoperatingrange.Byusingaresistordividerfromthe
input supply to ground, the OVLO pin serves as a precise
input supply voltage monitor. Switching is disabled when
theOVLOpinrisesabove1.2V, whichcanbeconfiguredto
limit switching to a specific range of input supply voltage.
Theselectionofswitchingfrequencyisatrade-offbetween
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC7801 can be selected
using the FREQ pin.
When switching is disabled, the LTC7801 can safely sus-
tain input voltages up to the absolute maximum rating of
150V. Input supply overvoltage events trigger a soft-start
reset, which results in a graceful recovery from an input
supply transient.
If the PLLIN pin is not being driven by an external clock
source, the FREQ pin can be tied to GND, tied to INTV
CC
or programmed through an external resistor. Tying FREQ
to GND selects 350kHz while tying FREQ to INTV se-
CC
lects 535kHz. Placing a resistor between FREQ and GND
allows the frequency to be programmed between 50kHz
and 900kHz, as shown in Figure 12.
Output Overvoltage Protection
An overvoltage comparator guards against transient over-
shoots as well as other more serious conditions that may
overvoltage the output. When the V pin rises by more
than 10% above its regulation point of 0.800V, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
A phase-locked loop (PLL) is available on the LTC7801
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN pin. The LTC7801’s
phase detector adjusts the voltage (through an internal
lowpass filter) of the VCO input to align the turn-on of the
external top MOSFET to the rising edge of the synchroniz-
ing signal.
FB
7801f
14
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LTC7801
operaTion
Power Good Pin
where the EXTV LDO becomes disabled (EXTV below
CC CC
the switchover threshold) for an extended period of time
could result in overheating of the IC (or overheating the
external N-channel MOSFET if the NDRV LDO is used). In
ThePGOODpinisconnectedtoanopendrainofaninternal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when the V pin voltage is not within
FB
thecaseswhereEXTV istiedtotheregulatoroutput, this
CC
10%ofthe0.8Vreferencevoltage.ThePGOODpinisalso
eventcouldhappenduringoverloadconditionssuchasan
output short to ground. The LTC7801 includes a regulator
shutdown (REGSD) feature that shuts down the regulator
to substantially reduce power dissipation and the risk of
overheating during such events.
pulled low when the RUN pin is low (shut down). When
the V pin voltage is within the 10% requirement, the
FB
MOSFET is turned off and the pin is allowed to be pulled
up by an external resistor to a source no greater than 6V.
Foldback Current
The REGSD circuit monitors the EXTV LDO and the SS
CC
pin to determine when to shut down the regulator. Refer
When the output voltage falls to less than 70% of its
nominal level, foldback current limiting is activated, pro-
gressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
to the timing diagram in Figure 1. Whenever SS is above
2.2Vand theEXTV LDOisnotswitchedover(theEXTV
CC
CC
pin is below the switchover threshold), the internal 10μA
pull-up current on SS turns off and a 5μA pull-down cur-
rentturnson, dischargingSS. OnceSSdischargesto2.0V
interval (as long as the V voltage is keeping up with the
FB
and theEXTV pinremainsbelowtheEXTV switchover
CC
CC
SS voltage). Foldback current limiting is intended to limit
powerdissipationduringovercurrentandshort-circuitfault
conditions. NotethattheLTC7801continuouslymonitors
the inductor current and prevents current runaway under
all conditions.
threshold, the pull-down current reduces to 1μA and the
regulator shuts down, eliminating all DRV switching
CC
current. Switching stays off until the SS pin discharges
to approximately 200mV, at which point the 10μA pull-up
currentturnsbackonandtheregulatorre-enablesswitch-
ing. If the short-circuit persists, the regulator cycles on
and off at a low duty cycle interval of about 12%.
Regulator Shutdown (REGSD)
High input voltage applications typically require using the
EXTV LDOtokeeppowerdissipationlow.Faultconditions
CC
EXTV SWITCHOVER
CC
THRESHOLD (FALLING)
SHORT-CIRCUIT EVENT
SHORT REMOVED
FROM V
OUT
V
OUT
/EXTV
CC
0V
I
= 5µA
SS
(SINK)
2.2V
2.0V
I
= 10µA
SS
I
= 10µA
SS
SS
(SOURCE)
I
= 1µA
(SINK)
(SOURCE)
0.8V
SS
0.2V
0V
START-UP INTO
SHORT-CIRCUIT
TG/BG
7801 F01
Figure 1. Regulator Shutdown Operation
7801f
15
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TheTypicalApplicationonthefirstpageisabasicLTC7801
application circuit. LTC7801 can be configured to use
either DCR (inductor resistance) sensing or low value
resistor sensing. The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
programmed current limit unpredictable. If DCR sensing
is used (Figure 3b), resistor R1 should be placed close to
the switching node, to prevent noise from coupling into
sensitive small-signal nodes.
TO SENSE FILTER
NEXT TO THE CONTROLLER
C
OUT
CURRENT FLOW
7801 F02
INDUCTOR OR R
SENSE
R
SENSE
(if R
is used) and inductor value. Next, the
Figure 2. Sense Lines Placement with Inductor or Sense Resistor
SENSE
power MOSFETs are selected. Finally, input and output
capacitors are selected.
Low Value Resistor Current Sensing
+
–
SENSE and SENSE Pins
A typical sensing circuit using a discrete resistor is shown
+
–
The SENSE and SENSE pins are the inputs to the cur-
rent comparator. The common mode voltage range on
these pins is 0V to 65V (absolute maximum), enabling
the LTC7801 to regulate output voltages up to a nominal
set point of 60V (allowing margin for tolerances and tran-
in Figure 3a. R
output current.
is chosen based on the required
SENSE
The current comparator has a maximum threshold
determined by the ILIM setting. The current
V
SENSE(MAX)
+
comparator threshold voltage sets the peak of the induc-
sients). The SENSE pin is high impedance over the full
tor current, yielding a maximum average output current,
common mode range, drawing at most 1μA. This high
impedance allows the current comparators to be used in
I
, equal to the peak value less half the peak-to-peak
MAX
–
ripple current, ∆I . To calculate the sense resistor value,
L
inductor DCR sensing. The impedance of the SENSE pin
use the equation:
changes depending on the common mode voltage. When
–
SENSE is less than INTV – 0.5V, a small current of less
VSENSE(MAX)
CC
–
RSENSE
=
than 1μA flows out of the pin. When SENSE is above
∆IL
IMAX
+
INTV + 0.5V, a higher current (≈850μA) flows into the
CC
2
pin.BetweenINTV –0.5VandINTV +0.5V,thecurrent
CC
CC
transitions from the smaller current to the higher current.
Normally in high duty cycle conditions, the maximum
output current level will be reduced due to the internal
compensationrequiredtomeetstabilitycriterionoperating
at greater than 50% duty factor. The LTC7801, however,
uses a proprietary circuit to nullify the effect of slope
compensation on the current limit performance.
Filter components mutual to the sense lines should be
placed close to the LTC7801, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 2). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
7801f
16
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V
If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
IN
BOOST
LTC7801
TG
SW
BG
R
SENSE
V
OUT
+
SENSE
CAP
PLACED NEAR SENSE PINS
–
SENSE
GND
7801 F03a
Using the inductor ripple current value from the Inductor
ValueCalculationsection,thetargetsenseresistorvalueis:
(3a) Using a Resistor to Sense Current
V
V
VSENSE(MAX)
IN
RSENSE(EQUIV)
=
∆IL
2
IMAX
+
BOOST
INDUCTOR
DCR
LTC7801
TG
SW
BG
L
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
OUT
R1
minimum value for V
teristics table.
in the Electrical Charac-
SENSE(MAX)
+
SENSE
C1*
R2
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
–
SENSE
GND
*PLACE C1 NEAR SENSE PINS
(R1||R2) • C1 = L/DCR
= DCR(R2/(R1+R2))
7801 F03b
R
SENSE(EQ)
0.4%/°C. A conservative value for T
is 100°C.
L(MAX)
(3b) Using the Inductor DCR to Sense Current
Figure 3. Current Sensing Methods
To scale the maximum inductor DCR to the desired sense
resistor value (R ), use the divider ratio:
D
RSENSE(EQUIV)
RD =
Inductor DCR Sensing
DCRMAX at T
L(MAX)
For applications requiring the highest possible efficiency
at high load currents, the LTC7801 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 3b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such
an inductor, power loss through a sense resistor would
cost several points of efficiency compared to inductor
DCR sensing.
C1isusuallyselectedtobeintherangeof0.1μFto0.47μF.
ThisforcesR1||R2toaround2k, reducingerrorthatmight
+
have been caused by the SENSE pin’s 1μA current.
The equivalent resistance R1||R2 is scaled to the tempera-
ture inductance and maximum DCR:
L
R1||R2 =
(DCR at 20°C)•C1
7801f
17
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The values for R1 and R2 are:
Accepting larger values of ∆I allows the use of low in-
L
ductances, but results in higher output voltage ripple and
R1||R2
RD
R1•RD
1− RD
R1=
; R2 =
greater core losses. A reasonable starting point for setting
ripple current is ∆I = 0.3(I
). The maximum ∆I occurs
L
L
MAX
at the maximum input voltage.
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
the burst clamp, which can be programmed between 10%
V
IN(MAX) − VOUT • V
(
)
OUT
PLOSS R1=
and 60% of the current limit determined by R
. (For
R1
SENSE
more information see the Burst Clamp Programming sec-
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
totheextraswitchinglossesincurredthroughR1.However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
tion.) Lower inductor values (higher ∆I ) will cause this
L
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
affordthecorelossfoundinlowcostpowderedironcores,
forcingtheuseofmoreexpensiveferriteormolypermalloy
cores. Actual core loss is independent of core size for a
fixedinductorvalue,butitisverydependentoninductance
value selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET switching and gate charge losses. In addition to
this basic trade-off, the effect of inductor value on ripple
currentandlowcurrentoperationmustalsobeconsidered.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Theinductorvaluehasadirecteffectonripplecurrent.The
inductor ripple current, ∆I , decreases with higher induc-
L
tance or higher frequency and increases with higher V :
IN
1
VOUT
∆IL =
V
1−
OUT
(f)(L)
V
IN
Power MOSFET Selection
Two external power MOSFETs must be selected for the
LTC7801 controller: one N-channel MOSFET for the top
(main) switch, and one N-channel MOSFET for the bottom
(synchronous) switch.
7801f
18
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The peak-to-peak drive levels are set by the DRV volt-
The MOSFET power dissipations at maximum output
current are given by:
CC
age. This voltage can range from 5V to 10V depending on
configurationoftheDRVSETpin.Therefore,bothlogic-level
and standard-level threshold MOSFETs can be used in
2
VOUT
PMAIN
=
I
1+ δ R
+
(
)
(
)
OUT(MAX)
DS(ON)
V
IN
most applications depending on the programmed DRV
CC
voltage. Pay close attention to the BV
the MOSFETs as well.
specification for
IOUT(MAX)
DSS
(V )2
(R )(CMILLER)•
DR
IN
2
TheLTC7801’sabilitytoadjustthegatedrivelevelbetween
5V to 10V (OPTI-DRIVE) allows an application circuit to
be precisely optimized for efficiency. When adjusting the
gate drive level, the final arbiter is the total input current
for the regulator. If a change is made and the input cur-
rent decreases, then the efficiency has improved. If there
is no change in input current, then there is no change in
efficiency.
1
1
+
(f)
V
− VTHMIN
V
THMIN
DRVCC
2
V − V
IN
OUT
P
=
I
1+ δ R
DS(ON)
(
)
(
)
SYNC
OUT(MAX)
V
IN
where δ is the temperature dependency of R
DR
at the MOSFET’s Miller threshold voltage. V
typical MOSFET minimum threshold voltage.
and
DS(ON)
R
(approximately 2Ω) is the effective driver resistance
is the
THMIN
Selection criteria for the power MOSFETs include the
on-resistance R
, Miller capacitance C
DS(ON)
, input
MILLER
2
voltage and maximum output current. Miller capacitance,
, can be approximated from the gate charge curve
Both MOSFETs have I R losses while the main N-channel
equations include an additional term for transition losses,
C
MILLER
usually provided on the MOSFET manufacturers’ data
sheet. C is equal to the increase in gate charge
which are highest at high input voltages. For V < 20V
IN
MILLER
the high current efficiency generally improves with larger
along the horizontal axis while the curve is approximately
MOSFETs, while for V > 20V the transition losses rapidly
IN
flat divided by the specified change in V . This result is
DS
increasetothepointthattheuseofahigherR
withlowerC
device
DS(ON)
then multiplied by the ratio of the application applied V
DS
actuallyprovideshigherefficiency.The
MILLER
to the gate charge curve specified V . When the IC is
DS
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
VOUT
MAIN SWITCH DUTY CYCLE =
The term (1+ δ) is generally given for a MOSFET in the
V
IN
form of a normalized R
vs Temperature curve, but
DS(ON)
V − V
δ = 0.005/°C can be used as an approximation for low
IN
OUT
SYNCHRONOUS SWITCH DUTY CYCLE =
voltage MOSFETs.
V
IN
C and C
Selection
IN
OUT
TheselectionofC isusuallybasedofftheworst-caseRMS
IN
input current. The highest (V )(I ) product needs to
OUT OUT
be used in the formula shown in Equation 1 to determine
the maximum RMS capacitor current requirement.
7801f
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Incontinuousmode,thesourcecurrentofthetopMOSFET
Setting Output Voltage
is a square wave of duty cycle (V )/(V ). To prevent
OUT
IN
The LTC7801 output voltage is set by an external feedback
resistordividercarefullyplacedacrosstheoutput,asshown
in Figure 4. The regulated output voltage is determined by:
large voltage transients, a low ESR capacitor sized for the
maximumRMScurrentmustbeused.ThemaximumRMS
capacitor current is given by:
RB
RA
IMAX
1/2
VOUT = 0.8V 1+
CIN Required IRMS
≈
(V )(V − V
)
[
]
IN
OUT
OUT
V
IN
To improve the frequency response, a feedforward ca-
This formula has a maximum at V = 2V , where I
RMS
OUT
IN
OUT
pacitor, C , may be used. Great care should be taken to
FF
= I /2. This simple worst-case condition is commonly
route the V line away from noise sources, such as the
FB
usedfordesignbecauseevensignificantdeviationsdonot
offermuchrelief.Notethatcapacitormanufacturers’ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC7801, ceramic capacitors
inductor or the SW line.
V
OUT
LTC7801
R
R
C
FF
B
V
FB
A
7801 F04
can also be used for C . Always consult the manufacturer
IN
if there is any question.
Figure 4. Setting Output Voltage
A small (0.1μF to 1μF) bypass capacitor between the chip
V pin and ground, placed close to the LTC7801, is also
IN
RUN Pin and Overvoltage/Undervoltage Lockout
suggested. A small (≤10Ω) resistor placed between C
IN
(C1) and the V pin provides further isolation.
The LTC7801 is enabled using the RUN pin. It has a rising
thresholdof1.2Vwith80mVofhysteresis.PullingtheRUN
pin below 1.12V shuts down the main control loop. Pull-
ing it below 0.7V disables the controller and most internal
IN
The selection of C
is driven by the effective series
OUT
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
circuits, including the DRV and INTV LDOs. In this
CC
CC
output ripple (∆V ) is approximated by:
OUT
state the LTC7801 draws only 10μA of quiescent current.
1
The RUN pin is high impedance below 3V and must be
externally pulled up/down or driven directly by logic. The
RUN pin can tolerate up to 150V (absolute maximum), so
∆VOUT ≈ ∆I ESR+
L
8 • f •COUT
where f is the operating frequency, C
is the output
OUT
it can be conveniently tied to V in always-on applications
IN
capacitance and ∆I is the ripple current in the inductor.
L
where the controller is enabled continuously and never
shut down. Above 3V, the RUN pin has approximately a
15MΩ impedance to an internal 3V clamp.
The output ripple is highest at maximum input voltage
since ∆I increases with input voltage.
L
7801f
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TheRUNandOVLOpinscanalternativelybeconfiguredas
For applications that do not require a precise OVLO, the
OVLO pin can be tied directly to ground. The RUN pin in
this type of application can be used as an external UVLO
using the previous equations with R5 = 0Ω.
undervoltage(UVLO)andovervoltage(OVLO)lockoutson
the V supply with a resistor divider from V to ground.
IN
IN
A simple resistor divider can be used as shown in Figure
5 to meet specific V voltage requirements.
IN
Similarly, for applications that do not require a precise
UVLO, the RUN pin can be tied to V . In this configura-
IN
V
IN
tion, the UVLO threshold is limited to the internal DRV
CC
UVLOthresholdsasshownintheElectricalCharacteristics
table. The resistor values for the OVLO can be computed
using the previous equations with R3 = 0Ω.
R3
RUN
LTC7801
OVLO
R4
R5
Soft-Start (SS) Pin
7801 F05
The start-up of V
is controlled by the voltage on the
OUT
SS pin. When the voltage on the SS pin is less than the
Figure 5. Adjustable UV and OV Lockout
internal 0.8V reference, the LTC7801 regulates the V pin
FB
voltage to the voltage on the SS pin instead of the internal
reference. The SS pin can be used to program an external
soft-start function.
The current that flows through the R3-R4-R5 divider will
directly add to the shutdown, sleep, and active current of
the LTC7801, and care should be taken to minimize the
impact of this current on the overall efficiency of the ap-
plication circuit. Resistor values in the megaohm range
mayberequiredtokeeptheimpactonquiescentshutdown
and sleep currents low. To pick resistor values, the sum
Soft-startisenabledbysimplyconnectingacapacitorfrom
the SS pin to ground, as shown in Figure 6. An internal
10μA current source charges the capacitor, providing a
linear ramping voltage at the SS pin. The LTC7801 will
regulate its feedback voltage (and hence V ) according
OUT
totalofR3+R3+R5(R
)shouldbechosenfirstbased
tothevoltageontheSSpin,allowingV torisesmoothly
TOTAL
OUT
on the allowable DC current that can be drawn from V .
from 0V to its final regulated value. The total soft-start
IN
time will be approximately:
The individual values of R3, R4 and R5 can be calculated
from the following equations:
0.8V
10µA
tSS = CSS
•
1.20V
R5 = RTOTAL
R4 = RTOTAL
•
•
RISING V OVLO THRESHOLD
IN
1.20V
LTC7801
− R5
RISING V OVLO THRESHOLD
IN
SS
C
SS
R3 = RTOTAL − R5− R4
GND
7801 F06
Figure 6. Using the SS Pin to Program Soft-Start
7801f
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usesaninternalP-channelpassdevicebetweentheEXTV
The SS pin also controls the timing of the regulator
shutdown (REGSD) feature (as discussed in Regulator
ShutdownoftheOperationsection).Iftheapplicationdoes
not require the use of the EXTV LDO (the EXTV pin
CC
and DRV pins. The NDRV LDO utilizes the NDRV pin to
CC
drive the gate of an external N-channel MOSFET acting as
a linear regulator with its drain connected to V .
IN
CC
CC
is grounded), the REGSD feature must be defeated with
The NDRV LDO provides an alternative method to supply
a pull-up resistor between SS and INTV , as shown in
CC
power to DRV from the input supply without dissipating
CC
Figure 7. Any resistor 330k or smaller between SS and
the power inside the LTC7801 IC. It has an internal charge
INTV defeats the 5μA pull-down current on SS that
CC
pump that allows NDRV to be driven above the V sup-
IN
turns on once SS reaches 2.2V (with the EXTV LDO
CC
ply, allowing for low dropout performance. The V LDO
IN
not enabled), preventing SS from discharging to 2.0V
and shutting down the regulator. Note the current through
this pull-up resistor adds to the internal 10μA SS pull-up
current at start-up, causing the total soft-start time to
be shorter than what it is calculated without the pull-up
resistor. The total soft-start time with the pull-up resistor
is approximately:
has a slightly lower regulation point than the NDRV LDO,
such that all DRV current flows through the external N-
CC
channel MOSFET (and not through the internal P-channel
pass device) once DRV reaches regulation.
CC
When laying out the PC board, care should be taken to
route NDRV away from any switching nodes, especially
SW, TG, and BOOST. Coupling to the NDRV node could
cause its voltage to collapse and the NDRV LDO to lose
0.8V
tSS ≈ CSS
•
4.6V
RSS
regulation. If this occurs, the internal V LDO would
IN
10µA+
take over and maintain DRV voltage at a slightly lower
CC
regulation point. However, internal heating of the IC would
become a concern. High frequency noise on the drain of
the external NFET could also couple into the NDRV node
(throughthegate-to-draincapacitanceoftheNDRVNFET)
and adversely affect NDRV regulation. The following are
methods that could mitigate this potential issue (refer to
Figure 8a).
where R is the value of the resistor between the SS and
SS
INTV pins.
CC
INTV
CC
R
SS
LTC7801
SS
1. Add local decoupling capacitors right next to the drain
of the external NDRV NFET in the PCB layout.
C
SS
GND EXTV
CC
7801 F07
2. Insert a resistor (~100Ω) in series with the gate of the
NDRV NFET.
Figure 7. Using the SS Pin to Program Soft-Start
with EXTVCC Unused/Grounded to Defeat REGSD
3. Insert a small capacitor (~1nF) between the gate and
source of the NDRV NFET.
When testing the application circuit, be sure the NDRV
voltage does not collapse over the entire input voltage
and output current operating range of the buck regulator.
DRV Regulators (OPTI-DRIVE)
CC
The LTC7801 features three separate low dropout linear
regulators (LDO) that can supply power at the DRV pin.
CC
TheinternalV LDOusesaninternalP-channelpassdevice
IN
betweentheV andDRV pins. TheinternalEXTV LDO
IN
CC
CC
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If the NDRV LDO is not being used, connect the NDRV pin
Table 1a.
to DRV (Figure 8b).
CC
DRVSET PIN
DRV VOLTAGE
CC
GND
6V
V
IN
INTV
10V
CC
V
IN
Resistor to GND 50k to 100k
5V to 10V
LTC7801
R1*
NDRV
C2*
Table 1b.
C1*
DRV
CC
DRV UVLO
EXTV SWITCHOVER
CC
CC
RISING/FALLING
RISING/FALLING
THRESHOLD
DRVUV
GND
INTV
THRESHOLDS
GND
4.0V/3.8V
4.7V/4.45V
7.7V/7.45V
*R1, C1 AND C2 ARE OPTIONAL
7801 F08a
7.5V/6.7V
CC
Figure 8a. Configuring the NDRV LDO
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
V
IN
NDRV LDO
or EXTV LDO
V
IN
CC
NDRV
LTC7801
DRV
CC
INTERNAL V LDO
IN
GND
7801 F08b
50 55 60 65 70 75 80 85 90 95 100 105
Figure 8b. Disabling the NDRV LDO
DRVSET PIN RESISTOR (kΩ)
7801 F09
The DRV supply is regulated between 5V to 10V, de-
Figure 9. Relationship Between DRVCC Voltage
and Resistor Value at DRVSET Pin
CC
pending on how the DRVSET pin is set. The internal V
IN
and EXTV LDOs can supply a peak current of at least
50mA. The DRV pin must be bypassed to ground with
CC
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC7801 to be
CC
a minimum of 4.7μF ceramic capacitor. Good bypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers.
exceeded. The DRV current, which is dominated by the
CC
gate charge current, may be supplied by the V LDO,
IN
The DRVSET pin programs the DRV supply voltage and
CC
NDRV LDO or the EXTV LDO. When the voltage on the
CC
the DRVUV pin selects different DRV UVLO and EXTV
CC
CC
EXTV pin is less than its switchover threshold (4.7V or
CC
switchover threshold voltages. Table 1a summarizes the
different DRVSET pin configurations along with the volt-
age settings that go with each configuration. Table 1b
summarizes the different DRVUV pin settings. Tying the
7.7V as determined by the DRVUV pin described above),
the V and NDRV LDOs are enabled. Power dissipation
IN
in this case is highest and is equal to V • IDRV . If the
IN
CC
NDRV LDO is not being used, this power is dissipated
inside the IC. The gate charge current is dependent on
operating frequency as discussed in the Efficiency Con-
siderations section.
DRVSET pin to INTV programs DRV to 10V. Tying the
CC
CC
DRVSET pin to GND programs DRV to 6V. Placing a 50k
CC
to 100k resistor between DRVSET and GND the programs
DRV between 5V to 10V, as shown in Figure 9.
CC
7801f
23
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The junction temperature can be estimated by using the
For 5V to 14V regulator outputs, this means connecting
the EXTV pin directly to V . Tying the EXTV pin to
equations given in Note 2 of the Electrical Characteristics.
CC
OUT
CC
For example, if DRV is set to 6V, the DRV current is
an 8.5V supply reduces the junction temperature in the
CC
CC
limited to less than 32mA from a 40V supply when not
previous example from 125°C to:
using the EXTV or NDRV LDOs at a 70°C ambient tem-
CC
T = 70°C + (32mA)(8.5V)(43°C/W) = 82°C
J
perature in the QFN package:
However, for 3.3V and other low voltage outputs, addi-
T = 70°C + (32mA)(40V)(43°C/W) = 125°C
J
tional circuitry is required to derive DRV power from
CC
To prevent the maximum junction temperature from being
the output.
exceeded, the V supply current must be checked while
IN
The following list summarizes the five possible connec-
operating in forced continuous mode (MODE = INTV )
CC
tions for EXTV :
CC
at maximum V .
IN
1. EXTV grounded. This will cause DRV to be pow-
CC
CC
When the voltage applied to EXTV rises above its swi-
CC
ered from the internal V or NDRV LDO resulting in
IN
tchover threshold, the V and NDRV LDOs are turned off
IN
an efficiency penalty of up to 10% at high input volt-
and the EXTV LDO is enabled. The EXTV LDO remains
CC
CC
ages. If EXTV is grounded, the REGSD feature must
CC
onaslongasthevoltageappliedtoEXTV remainsabove
CC
be defeated with a pull-up resistor 330k or smaller
theswitchoverthresholdminusthecomparatorhysteresis.
between SS and INTV .
CC
TheEXTV LDOattemptstoregulatetheDRV voltageto
CC
CC
2. EXTV connecteddirectlytotheregulatoroutput.This
the voltage as programmed by the DRVSET pin, so while
CC
is the normal connection for a 5V to 14V regulator and
EXTV is less than this voltage, the LDO is in dropout
CC
provides the highest efficiency.
and the DRV voltage is approximately equal to EXTV .
CC
CC
When EXTV is greater than the programmed voltage,
CC
3. EXTV connected to an external supply. If an external
CC
up to an absolute maximum of 14V, DRV is regulated
CC
supply is available in the 5V to 14V range, it may be
to the programmed voltage.
used to power EXTV providing it is compatible with
CC
the MOSFET gate drive requirements. Ensure that
Using the EXTV LDO allows the MOSFET driver and
CC
EXTV ≤ V .
control power to be derived from the LTC7801’s switch-
CC
IN
ing regulator output (4.7V/7.7V ≤ V
≤ 14V) during
OUT
4. EXTV connected to the regulator output through an
CC
normal operation and from the V or NDRV LDO when the
IN
external zener diode. If the output voltage is greater
output is out of regulation (e.g., start-up, short-circuit).
than 14V, a zener diode can be used to drop the
If more current is required through the EXTV LDO than
CC
necessary voltage between V
and EXTV such
CC
OUT
is specified, an external Schottky diode can be added
that EXTV remains below 14V (Figure 10). In this
CC
between the EXTV and DRV pins. In this case, do not
CC
CC
configuration,abypasscapacitoronEXTV ofatleast
CC
apply more than 10V to the EXTV pin and make sure
CC
0.1μF is recommended. An optional resistor between
that EXTV ≤ V .
CC
IN
EXTV and GND can be inserted to ensure adequate
CC
bias current through the zener diode.
Significant efficiency and thermal gains can be realized
by powering DRV from the output, since the V cur-
CC
IN
V
OUT
> 14V
rent resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
LTC7801
EXTV
EXTV < 14V
CC
CC
0.1µF
GND
7801 F10
Figure 10. Using a Zener Diode Between VOUT and EXTVCC
7801f
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5. EXTV connectedtoanoutput-derivedboostnetwork
CC
VMODE − 0.4V
BURST CLAMP =
where V
•100
off the regulator output. For 3.3V and other low volt-
1V
age regulators, efficiency gains can still be realized by
connecting EXTV to an output-derived voltage that
is the voltage on the MODE pin and Burst
CC
MODE
has been boosted to greater than 4.7V/7.7V. Ensure
Clamp is the percentage of V
. The burst clamp
SENSE(MAX)
that EXTV ≤ V .
levelisdeterminedbythedesiredamountofoutputvoltage
ripple at low output loads. As the burst clamp increases,
the sleep time between pulses and the output voltage
ripple increase.
CC
IN
INTV Regulator
CC
AnadditionalP-channelLDOsuppliespowerattheINTV
CC
pin from the DRV pin. Whereas DRV powers the gate
CC
CC
The MODE pin is high impedance and V
can be set
MODE
drivers, INTV powers much of the LTC7801’s internal
CC
by a resistor divider from the INTV pin (Figure 11a).
CC
circuitry. The INTV supply must be bypassed with a
CC
Alternatively, the MODE pin can be tied directly to the
0.1μF ceramic capacitor. INTV is also used as a pull-up
CC
V
FB
pin to set the burst clamp to 40% (V
= 0.8V),
MODE
to bias other pins, such as MODE, PGOOD, etc.
or through an additional divider resistor (R3). As shown
in Figure 11b, this resistor can be placed below V to
FB
MODE
Topside MOSFET Driver Supply (C )
B
program the burst clamp between 10% and 40% (V
= 0.5V to 0.8V) or above V to program the burst clamp
AnexternalbootstrapcapacitorC connectedtotheBOOST
FB
MODE
B
between 40% and 60% (V
= 0.8V to 1.0V).
pinsuppliesthegatedrivevoltageforthetopsideMOSFET.
The LTC7801 features an internal switch between DRV
CC
and the BOOST pin. This internal switch eliminates the
need for an external bootstrap diode between DRV and
CC
BOOST. Capacitor C in the Functional Diagram is charged
B
through this internal switch from DRV when the SW
CC
INTV
CC
pin is low. When the topside MOSFET is to be turned on,
LTC7801
R2
R1
the driver places the C voltage across the gate-source
B
MODE
of the MOSFET. This enhances the top MOSFET switch
7801 F11a
and turns it on. The switch node voltage, SW, rises to V
IN
and the BOOST pin follows. With the topside MOSFET on,
BURST CLAMP = 10% TO 60%
the BOOST voltage is above the input supply: V
=
BOOST
(11a) Using INTVCC to Program the Burst Clamp
V + V
. The value of the boost capacitor, C , needs
IN
DRVCC
B
to be 100 times that of the total input capacitance of the
topside MOSFET(s).
V
OUT
V
OUT
R2
R3
Burst Clamp Programming
V
MODE
LTC7801
FB
Burst Mode operation is enabled if the voltage on the
MODE pin is 0V or in the range between 0.5V to 1V. The
burst clamp, which sets the minimum peak inductor cur-
rent, can be programmed by the MODE pin voltage. If
the MODE pin is grounded, the burst clamp is set to 25%
of the maximum sense voltage (V
pin voltage between 0.5V and 1V varies the burst clamp
LTC7801
MODE
R3
R1
R2
R1
V
FB
7801 F11b
BURST CLAMP = 10% TO 40% BURST CLAMP = 40% TO 60%
). A MODE
SENSE(MAX)
(11b) Using VFB to Program the Burst Clamp
linearly between 10% and 60% of V
the following equation:
through
SENSE(MAX)
Figure 11. Programming the Burst Clamp
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Fault Conditions: Current Limit and Current Foldback
AshortedtopMOSFETwillresultinahighcurrentcondition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
The LTC7801 includes current foldback to help limit
load current when the output is shorted to ground. If
the output voltage falls below 70% of its nominal output
level, then the maximum sense voltage is progressively
lowered from 100% to 40% of its maximum selected
value. Under short-circuit conditions with very low duty
cycles, the LTC7801 will begin cycle skipping in order to
limit the short-circuit current. In this situation the bottom
MOSFET will be dissipating most of the power but less
than in normal operation. The short-circuit ripple current
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self heating on chip,
the overtemperature shutdown circuitry will shut down
the LTC7801. When the junction temperature exceeds ap-
proximately175°C,theovertemperaturecircuitrydisables
theDRV LDO, causingtheDRV supplytocollapseand
is determined by the minimum on-time, t
, of the
CC
CC
ON(MIN)
effectively shutting down the entire LTC7801 chip. Once
LTC7801 (≈80ns), the input voltage and inductor value:
the junction temperature drops back to the approximately
V
L
IN
155°C, the DRV LDO turns back on. Long term over-
∆IL(SC) = t
CC
ON(MIN)
stress (T > 125°C) should be avoided as it can degrade
J
the performance or shorten the life of the part.
The resulting average short-circuit current is:
Phase-Locked Loop and Frequency Synchronization
1
2
ISC = 45% •ILIM(MAX) − ∆IL(SC)
The LTC7801 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter,
and a voltage-controlled oscillator (VCO). This allows
the turn-on of the top MOSFET to be locked to the rising
edge of an external clock signal applied to the PLLIN pin.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
muchhigherthannominallevels.Thecrowbarcauseshuge
currents to flow, that blow the fuse to protect against a
shorted top MOSFET if the short occurs while the control-
ler is operating.
If the external clock frequency is greater than the inter-
A comparator monitors the output for overvoltage condi-
tions. The comparator detects faults greater than 10%
above the nominal output voltage. When this condition
is sensed, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. ThebottomMOSFETremainsoncontinuouslyfor
nal oscillator’s frequency, f , then current is sourced
OSC
continuously from the phase detector output, pulling up
the VCO input. When the external clock frequency is less
than f , current is sunk continuously, pulling down the
OSC
VCO input.
aslongastheovervoltageconditionpersists;ifV returns
OUT
to a safe level, normal operation automatically resumes.
7801f
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1000
900
800
700
600
500
400
300
200
100
0
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
C , holds the voltage at the VCO input.
LP
Note that the LTC7801 can only be synchronized to an
external clock whose frequency is within range of the
LTC7801’sinternalVCO,whichisnominally55kHzto1MHz.
This is guaranteed to be between 75kHz and 850kHz. The
LTC7801isguaranteedtosynchronizetoanexternalclock
that swings up to at least 2.8V and down to 0.5V or less.
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
7801 F12
Figure 12. Relationship Between Oscillator Frequency
and Resistor Value at the FREQ Pin
Rapid phase-locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. The VCO’s input voltage is
prebiased at a frequency corresponding to the frequency
set by the FREQ pin. Once prebiased, the PLL only needs
to adjust the frequency slightly to achieve phase lock and
synchronization. Although it is not required that the free-
running frequency be near the external clock frequency,
doingsowillpreventtheoperatingfrequencyfrompassing
through a large range of frequencies as the PLL locks.
Minimum On-Time Considerations
Minimum on-time t
is the smallest time duration
ON(MIN)
that the LTC7801 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
VOUT
tON(MIN)
<
V (f)
IN
Table 2 summarizes the different states in which the FREQ
pin can be used. When synchronized to an external clock,
the LTC7801 operates in forced continuous mode at light
loads if the MODE pin is set to Burst Mode operation or
forced continuous operation. If the MODE pin is set to
pulse-skipping operation, the LTC7801 maintains pulse-
skipping operation when synchronized.
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC7801 is approximately
80ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
130ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
Table 2.
FREQ PIN
PLLIN PIN
DC Voltage
DC Voltage
DC Voltage
FREQUENCY
350kHz
0V
INTV
535kHz
CC
Resistor to GND
Any of the Above
50kHz to 900kHz
External Clock
75kHz to 850kHz
Phase Locked to
External Clock
7801f
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Efficiency Considerations
2
3. I RlossesarepredictedfromtheDCresistancesofthe
fuse (if used), MOSFET, inductor, current sense resis-
tor and input and output capacitor ESR. In continuous
mode the average output current flows through L and
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
R
, but is chopped between the topside MOSFET
SENSE
and the synchronous MOSFET. If the two MOSFETs
have approximately the same R
, then the resis-
DS(ON)
tance of one MOSFET can simply be summed with the
2
%Efficiency = 100% – (L1 + L2 + L3 + ...)
resistances of L, R
and ESR to obtain I R losses.
SENSE
For example, if each R
= 30mΩ, R = 50mΩ,
DS(ON)
L
where L1, L2, etc. are the individual losses as a percent-
age of input power.
R
= 10mΩ and R
= 40mΩ (sum of both
SENSE
ESR
input and output capacitance losses), then the total
resistance is 130mΩ. This results in losses ranging
from 3% to 13% as the output current increases from
1A to 5A for a 5V output, or a 4% to 20% loss for a
3.3V output. Efficiency varies as the inverse square
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC7801 circuits: 1) IC V current, 2) DRV
IN
CC
2
regulator current, 3) I R losses, 4) Topside MOSFET
transition losses.
of V
for the same external components and output
OUT
power level. The combined effects of increasingly
lower output voltages and higher currents required
by high performance digital systems is not doubling
but quadrupling the importance of loss terms in the
switching regulator system!
1. The V current is the DC supply current given in the
IN
Electrical Characteristics table, which excludes MOS-
FET driver and control currents. V current typically
IN
results in a small (< 0.1%) loss.
2. DRV current is the sum of the MOSFET driver and
CC
4. Transition losses apply only to the top MOSFET(s) and
become significant only when operating at high input
voltages (typically 20V or greater). Transition losses
can be estimated from:
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched
from low to high to low again, a packet of charge, dQ,
2
moves from DRV to ground. The resulting dQ/dt is
CC
Transition Loss = (1.7) • V • I
• C
• f
IN
O(MAX)
RSS
a current out of DRV that is typically much larger
CC
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these system level losses during the
design phase. The internal battery and fuse resistance
than the control circuit current. In continuous mode,
I
= f(Q + Q ), where Q and Q are the gate
GATECHG
T B T B
charges of the topside and bottom side MOSFETs.
Supplying DRV from an output-derived source
CC
power through EXTV will scale the V current re-
CC
IN
losses can be minimized by making sure that C has ad-
IN
quired for the driver and control circuits by a factor
equate charge storage and very low ESR at the switching
frequency.A25Wsupplywilltypicallyrequireaminimumof
20μF to 40μF of capacitance having a maximum of 20mΩ
to50mΩofESR. OtherlossesincludingSchottkyconduc-
tion losses during dead-time and inductor core losses
generally account for less than 2% total additional loss.
of (Duty Cycle)/(Efficiency). For example, in a 20V
to 5V application, 10mA of DRV current results in
CC
approximately 2.5mA of V current. This reduces the
IN
midcurrent loss from 10% or more (if the driver was
powered directly from V ) to only a few percent.
IN
7801f
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Checking Transient Response
that will give a sense of the overall loop stability without
breaking the feedback loop.
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
Placing a power MOSFET directly across the output ca-
pacitor and driving the gate with an appropriate signal
generator is a practical way to producea realistic load step
condition. The initial output voltage step resulting from
the step change in output current may not be within the
bandwidth of the feedback loop, so this signal cannot be
used to determine phase margin. This is why it is better
to look at the ITH pin signal which is in the feedback loop
andisthefilteredandcompensatedcontrolloopresponse.
load current. When a load step occurs, V
shifts by an
OUT
amount equal to ∆I
(ESR), where ESR is the effective
LOAD
series resistance of C . ∆I
also begins to charge or
OUT
LOAD
discharge C
generating the feedback error signal that
OUT
forces the regulator to adapt to the current change and
return V to its steady-state value. During this recovery
OUT
time V
can be monitored for excessive overshoot or
OUT
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior, but it also provides
a DC coupled and AC filtered closed-loop response test
point. The DC step, rise time and settling at this test
point truly reflects the closed-loop response. Assuming
a predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in the first page circuit will
provide an adequate starting point for most applications.
The gain of the loop will be increased by increasing R
C
and the bandwidth of the loop will be increased by de-
creasing C . If R is increased by the same factor that C
C
C
C
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loopsystemandwilldemonstratetheactualoverall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with C , causing a rapid drop in V . No regulator can
OUT
OUT
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
The ITH series R -C filter sets the dominant pole-zero
C
C
loop compensation. The values can be modified slightly
to optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1μs to
10μs will produce output voltage and ITH pin waveforms
C
LOAD
to C
is greater than 1:50, the switch rise time
OUT
should be controlled so that the load rise time is limited
to approximately 25 • C . Thus a 10μF capacitor would
LOAD
require a 250μs rise time, limiting the charging current
to about 200mA.
7801f
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Design Example
A short-circuit to ground will result in a folded back cur-
rent of:
As a design example, assume V = 12V (nominal), V =
IN
IN
22V (max), V
= 3.3V, I
= 5A, V = 75mV
34mV 1 80ns(22V)
OUT
MAX
SENSE(MAX)
ISC =
−
= 3.21A
and f = 350kHz. The inductance value is chosen first based
on a 30% ripple current assumption. The highest value
of ripple current occurs at the maximum input voltage.
Tie the FREQ pin to GND, generating 350kHz operation.
The inductor ripple current can be calculated from the
following equation:
0.01Ω 2
4.7µH
with a typical value of R
and δ = (0.005/°C)(25°C)
DS(ON)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
2
P
SYNC
= (3.21A) (1.125) (0.022Ω) = 255mW
VOUT
(f)(L)
VOUT
whichislessthanunderfull-loadconditions.C ischosen
IN
∆IL =
1−
IN(NOM)
V
for an RMS current rating of at least 3A at temperature.
C
OUT
ischosenwithanESRof0.02Ωforlowoutputripple.
A 4.7μH inductor will produce 29% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 5.73A. Increasing the ripple
current will also help ensure that the minimum on-time
of 80ns is not violated. The minimum on-time occurs at
The output ripple in continuous mode will be highest at
the maximum input voltage. The output voltage ripple due
to ESR is approximately:
V
= R (∆I ) = 0.02Ω (1.45A) = 29mV
ESR L P-P
ORIPPLE
maximum V :
IN
PC Board Layout Checklist
VOUT
3.3V
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC.
tON(MIN)
=
=
= 429ns
V
IN(MAX)(f) 22V(350kHz)
The equivalent R
resistor value can be calculated by
SENSE
1. Are the signal and power grounds kept separate?
The combined IC signal ground pin and the ground
using the minimum value for the maximum current sense
threshold (66mV):
return of C
must return to the combined C
DRVCC
OUT
66mV
5.73A
(–) terminals. The path formed by the top N-channel
RSENSE
≤
0.01Ω
MOSFET, bottom N-channel MOSFET and the C ca-
IN
pacitor should have short leads and PC trace lengths.
Theoutputcapacitor(–)terminalsshouldbeconnected
as close as possible to the (–) terminals of the input
capacitor by placing the capacitors next to each other.
Choosing 1% resistors: R = 24.9k and R = 78.7k yields
an output voltage of 3.33V.
A
B
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Fairchild FDS6982S dual
2. Does the LTC7801 V pin’s resistive divider connect
FB
MOSFET results in: R
= 0.035Ω/0.022Ω, C
DS(ON)
MILLER
to the (+) terminal of C ? The resistive divider must
OUT
= 215pF. With 6V gate drive and maximum input voltage
be connected between the (+) terminal of C
and
OUT
with T(estimated) = 50°C:
signal ground. The feedback resistor connections
should not be along the high current input feeds from
the input capacitor(s).
3.3V
22V
PMAIN
=
(5A)2 1+ (0.005)(50°C− 25°C
[
]
–
+
5A
2
and SENSE leads routed together
3. Are the SENSE
(0.035Ω)+ (22V)2 (2.5Ω)(215pF)•
with minimum PC trace spacing? The filter capacitor
+
–
between SENSE and SENSE should be as close as
possible to the IC. Ensure accurate current sensing
with Kelvin connections at the SENSE resistor.
7801f
1
1
+
(350kHz)= 308mW
6V − 2.3V 2.3V
30
For more information www.linear.com/LTC7801
LTC7801
applicaTions inForMaTion
4. IstheDRV anddecouplingcapacitorconnectedclose
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
CC
totheIC, betweentheDRV andthegroundpin?This
CC
capacitor carries the MOSFET drivers’ current peaks.
5. Keep the SW, TG, and BOOST nodes away from sensi-
tive small-signal nodes. All of these nodes have very
large and fast moving signals and therefore should be
kept on the output side of the LTC7801 and occupy
minimum PC trace area.
6. Useamodifiedstargroundtechnique:alowimpedance,
largecopperareacentralgroundingpointonthesame
sideofthePCboardastheinputandoutputcapacitors
for inductive coupling between C , the top MOSFET and
IN
with tie-ins for the bottom of the DRV decoupling
the bottom MOSFET to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
CC
capacitor, the bottom of the voltage feedback resistive
divider and the GND pin of the IC.
PC Board Layout Debugging
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
It is helpful to use a DC-50MHz current probe to monitor
thecurrentintheinductorwhiletestingthecircuit.Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator and probe the actual
outputvoltageaswell. Checkforproperperformanceover
the operating voltage and current range expected in the
application. The frequency of operation should be main-
tained over the input voltage range down to dropout and
until the output load drops below the low current opera-
tion threshold—typically 25% of the maximum designed
current level in Burst Mode operation.
Pin Clearance/Creepage Considerations
Thedutycyclepercentageshouldbemaintainedfromcycle
tocycleinawell-designed,lownoisePCBimplementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required.
TheLTC7801isavailableintwopackages(QFNandTSSOP)
with identical functionality. However, the space between
adjacent pins on the LTC7801 may not provide sufficient
PC board trace clearance between high and low voltage
pins in some higher voltage applications. In applications
where clearance is required, the LTC3895 should be used.
The LTC3895 has removed pins between all the adjacent
high voltage and low voltage pins, providing 0.68mm
clearance which is sufficient for most applications. For
more information, refer to the printed circuit board design
standards described in IPC-2221 (www.ipc.org).
Reduce V from its nominal level to verify operation of
IN
the regulator in dropout. Check the operation of the un-
dervoltage lockout circuit by further lowering V while
IN
monitoring the output to verify operation.
7801f
31
For more information www.linear.com/LTC7801
LTC7801
Typical applicaTions
High Efficiency 140V to 3.3V Step-Down Regulator
V
IN
12V to 140V
C
C
INB
INA
100µF
0.47µF
x3
M
TOP
V
TG
IN
x2
RUN
BOOST
L1
3.3µH
R
3mΩ
SENSE
NDRV
C
B
V
OUT
0.1µF
3.3V
DRV
CC
SW
10A
C
4.7µF
DRV
CC
C
C
OUTA
470µF
OUTB
LTC7801
M
BOT
BG
100µF
x2
PLLIN
+
OVLO
SENSE
MODE
C
SNS
CPUMP_EN
1nF
–
SENSE
PGOOD
V
FB
R
100k
PGOOD
EXTV
CC
ITH
INTV
CC
SS
R
4.99k
ITH
DRVSET
DRVUV
C
INTV
CC
C
C
ITHB
SS
0.1µF
0.1µF
100pF
FREQ
C
ITHA
R
FREQ
6.8nF
34k
GND
L2
470µH
V
SW
IN
C
INC
RUN
R
B
0.47µF
267k
OVLO
C
OUT2
V
FB
4.7µF
LTC3639
R
196k
A
M
, M : BSC520N15NS3G
FBO
VPRG1
SS
TOP BOT
L1: WURTH 7443310330
I
SET
C
: KEMET T520D477M0O6A1E015
OUTA
GND
GND
GND
VPRG2
L2: COILCRAFT MSS1048T-474KLB
7801 TA02a
Efficiency and Power Loss
vs Load Current
Efficiency vs Load Current
Efficiency vs Input Voltage
100
90
80
70
60
50
40
30
20
10
0
100k
10k
1k
100
90
85
80
75
70
65
60
55
50
PULSE–SKIPPING
V
= 3.3V
OUT
V
= 3.3V
OUT
BURST EFFICIENCY
90
80
70
60
50
40
30
20
10
0
EFFICIENCY
FCM LOSS
PS LOSS
100
10
FCM
EFFICIENCY
V
V
V
V
V
= 12V
BURST LOSS
IN
IN
IN
IN
IN
M
BOT
M
BOT
M
BOT
M
BOT
: BSC190N15NS3G, I
: BSC190N15NS3G, I
: BSC520N15NS3G, I
: BSC520N15NS3G, I
= 5A
= 24V
LOAD
LOAD
LOAD
LOAD
= 10A
= 5A
= 48V
= 100V
= 140V
V
OUT
= 24V
= 3.3V
IN
= 10A
V
1
0.0001 0.001
0.01
0.1
1
10
0.0001 0.001
0.01
0.1
1
10
0
20
40
60
80 100 120 140
LOAD CURRENT (A)
LOAD CURRENT (A)
INPUT VOLTAGE (V)
7801 TA02b
7801 TA02c
7801 TA02d
7801f
32
For more information www.linear.com/LTC7801
LTC7801
Typical applicaTions
High Efficiency Switching Surge Stopper
V
IN
12V*
C
INA
C
INB
100µF
0.47µF
x4
M
TOP
V
IN
TG
RUN
BOOST
L1
15µH
R
8mΩ
SENSE
NDRV
C
B
R
1M
V
OUT
OVLOB
0.1µF
12V**
DRV
CC
SW
*SURGES TO 140V,
OVLO TIMER LIMITS
SWITCHING TIME
5A
C
4.7µF
DRV
CC
C
22µF
C
OUTA
39µF
OUTB
LTC7801
R
M
BOT
BG
SENSE+
SENSE-
OVLOC
1M
ABOVE 36V TO 4 SECONDS
OVLO
R
OVLOA
**V
FOLLOWS V WHEN V < 18V,
IN IN
REGULATES TO 18V WHEN V > 18V
IN
C
OVLO
OUT
C
SNS
34.9k
V
3.3µF
OUT
1nF
R
1M
B
CPUMP_EN
V
PIN NOT USED
IN THIS CIRCUIT: PGOOD
FB
INTV
CC
DRVSET
DRVUV
MODE
R
100k
SS
ITH
FREQ
R
10k
ITH
R
A
SS
C
0.1µF
C
ITHB
100pF
R
42.2k
INTV
46.4k
FREQ
CC
M
BOT
: BSC190N15NS3G
TOP
EXTV
CC
C
M
: BSC520N15NS3G
ITHA
C
0.1µF
SS
4.7nF
L1: WURTH 74435571500
PLLIN
C
OUTA
: OS-CON 35SVPF39M
GND
7801 TA03a
V
V
IN
20V/DIV
IN
20V/DIV
V
OUT
V
OUT
20V/DIV
20V/DIV
GND
GND
7801 TA03b
7801 TA03c
100µs/DIV
20ms/DIV
7801f
33
For more information www.linear.com/LTC7801
LTC7801
Typical applicaTions
High Efficiency 140V to 24V Step-Down Regulator
V
IN
8V to 140V
C
INA
C
INB
100µF
0.47µF
x4
MTOP
x2
V
TG
IN
RUN
BOOST
R
6mΩ
L1
33µH
SENSE
NDRV
C
B
V
OUT
0.1µF
10Ω
24V*
DRV
CC
V
SW
OUT
5A
C
4.7µF
DRV
CC
C
10µF
C
OUTA
68µF
OUTB
D
LTC7801
EXT
MBOT
BG
12V
EXTV
+
CC
SENSE
*V
follows V when
IN
OUT
IN
C
C
SNS
1nF
EXT
V
< 24V
1µF
R
806k
B
–
SENSE
OVLO
V
FB
INTV
CC
PIN NOT USED
IN THIS CIRCUIT: PGOOD
DRVUV
ITH
DRVSET
CPUMP_EN
MODE
R
23.7k
R
A
28k
ITH
FREQ
C
0.1µF
C
ITHB
100pF
INTV
CC
SS
R
36.5k
FREQ
PLLIN
C
C
SS
ITHA
3.3nF
0.1µF
GND
7801 TA04
MTOP, MBOT: BSC520N15NS3G
: DIODES INC. SMAZ12-13-F
D
EXT
L1: WURTH 7443633300
: SUNCON 35CE68LX
C
OUTA
7801f
34
For more information www.linear.com/LTC7801
LTC7801
Typical applicaTions
High Efficiency 60V to 5V Step-Down Regulator with Surge Protection to 140V
V
IN
8V to 60V*
C
INA
C
INB
100µF
0.47µF
x3
MTOP
x2
V
TG
IN
RUN
BOOST
*Surges to 140V,
L1
4.7µH
OVLO stops switching
NDRV
C
B
V
OUT
when V > 65V
IN
0.1µF
DRV
5V
CC
R
1M
OVLOB
SW
10A
C
OUTB
C
4.7µF
LTC7801
DRV
CC
R
SNS
2.43k
MBOT
BG
100µF
x2
OVLO
C
+
OUTA
SENSE
470µF
C
R
SNS
OVLOA
PLLIN
CPUMP_EN
MODE
1M
470nF
18.7k
–
SENSE
V
FB
ITH
INTV
CC
PINS NOT USED
IN THIS CIRCUIT: PGOOD
191k
DRVSET
R
4.99k
ITH
FREQ
DRVUV
R
330k
SS
C
ITHB
EXTV
CC
100pF
SS
R
36.5k
FREQ
C
0.1µF
C
ITHA
3.3nF
INTV
CC
C
SS
0.1µF
GND
7801 TA05
MTOP: BSC520N15NS3G
MBOT: BSC042NE7NS3G
L1: COILCRAFT XAL1010-472ME
C : KEMET T520D477M006ATE015
OUTA
7801f
35
For more information www.linear.com/LTC7801
LTC7801
package DescripTion
Please refer to http://www.linear.com/product/LTC7801#packaging for the most recent package drawings.
UFD Package
24-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-ꢀ696 Rev A)
0.70 0.05
4.50 0.05
3.ꢀ0 0.05
2.65 0.05
2.00 REF
3.65 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
3.00 REF
4.ꢀ0 0.05
5.50 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.05 TYP
PIN ꢀ NOTCH
2.00 REF
R = 0.20 OR C = 0.35
R = 0.ꢀꢀ5
TYP
0.75 0.05
4.00 0.ꢀ0
(2 SIDES)
23
24
0.40 0.ꢀ0
PIN ꢀ
TOP MARK
(NOTE 6)
ꢀ
2
5.00 0.ꢀ0
(2 SIDES)
3.00 REF
3.65 0.ꢀ0
2.65 0.ꢀ0
(UFD24) QFN 0506 REV A
0.25 0.05
0.200 REF
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
7801f
36
For more information www.linear.com/LTC7801
LTC7801
package DescripTion
Please refer to http://www.linear.com/product/LTC7801#packaging for the most recent package drawings.
FE Package
24-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1771 Rev B)
Exposed Pad Variation AA
7.70 – 7.90*
3.25
(.128)
(.303 – .311)
3.25
(.128)
24 23 22 21 20 19 18 17 16 15 14 13
6.60 ±0.10
4.50 ±0.10
2.74
(.108)
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10 11 12
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE24 (AA) TSSOP REV B 0910
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
7801f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnectionof itscircuits asdescribedhereinwill notinfringeon existing patent rights.
37
LTC7801
Typical applicaTion
V
IN
7V to 140V
C
C
INB
0.47µF
x3
INA
100µF
M
TOP
x2
L1
33µH
V
TG
IN
RUN
BOOST
R
SENSE
8mΩ
NDRV
C
B
V
OUT
0.1µF
12V*
DRV
CC
SW
5A
C
4.7µF
DRV
CC
C
C
OUTA
150µF
x3
OUTB
22µF
LTC7801
M
BOT
BG
OVLO
+
SENSE
*V
FOLLOWS V WHEN V < 12V
IN IN
OUT
DRVUV
MODE
C
SNS
1nF
–
SENSE
C
R
511k
B
B
PGOOD
10pF
EXTV
CC
R
PGOOD
100k
V
FB
ITH
INTV
CC
SS
R
ITH
10k
CPUMP_EN
DRVSET
FREQ
C
0.1µF
R
36.5k
INTV
A
CC
C
SS
0.1µF
C
ITHB
100pF
R
DRVSET
80.6k
PLLIN
C
ITHA
4.7nF
M
, M : BSC520N15NS3G
TOP BOT
R
30.1k
FREQ
L1: WURTH 7443633300
C
: AVX TPSD157M016R0125
GND
OUTA
7801 F13
Figure 13. High Efficiency 140V to 12V Step-Down Regulator
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
4V ≤ V ≤ 140V, 150V , 0.8V ≤ V
LTC3895
LTC7800
LTC3871
150V Low I , Synchronous Step-Down DC/DC Controller
≤ 60V, I = 40µA PLL Fixed
OUT Q
Q
IN
PK
100% Duty Cycle Capability, Adjustable 5V to 10V Gate Drive Frequency 50kHz to 900kHz
60V, Low I , Synchronous Step-Down DC/DC Controller
4V ≤ V ≤ 60V, 0.8V ≤ V
≤ 24V, I = 50µA PLL Fixed Frequency
OUT Q
Q
IN
with 99% Duty Cycle
320kHz to 2.25MHz
Bidirectional PolyPhase® Synchronous Buck or Boost
Controller
V
HIGH
Up to 100V, V
Up to 30V, High Power Buck or Boost On Demand
LOW
LTC3892/
LTC3892-1
60V Low I , Dual, 2-Phase Synchronous Step-Down DC/DC 4V ≤ V ≤ 60V, 0.8V ≤ V
≤ 0.99V , PLL Fixed Frequency 50kHz to
Q
IN
OUT IN
Controller with 99% Duty Cycle
900kHz, Adjustable 5V to 10V Gate Drive, I = 29µA
Q
LTC3639
LTC3638
LTC7138
LTC3899
LTC7860
LT8631
High Efficiency, 140V 100mA Synchronous Step-Down
Regulator
Integrated Power MOSFETs, 4V ≤ V ≤ 150V, 0.8V ≤ V
Q
≤ V ,
IN
IN
OUT
OUT
OUT
I = 12µA, MSOP-16 (12)
High Efficiency, 150V 250mA Synchronous Step-Down
Regulator
Integrated Power MOSFETs, 4V ≤ V ≤ 150V, 0.8V ≤ V
≤ V ,
IN
IN
I = 12µA, MSOP-16 (12)
Q
High Efficiency, 150V 400mA Synchronous Step-Down
Regulator
Integrated Power MOSFETs, 4V ≤ V ≤ 150V, 0.8V ≤ V
≤ V ,
IN
IN
I = 12µA, MSOP-16 (12)
Q
60V Triple Output, Buck/Buck/Boost Synchronous Controller 4.5V(Down to 2.2V After Start-Up) ≤ V ≤ 60V, Buck V
Range: 0.8V to
IN
OUT
with 30µA Burst Mode I
60V, Boost V
Up to 60V
OUT
Q
+
High Efficiency Switching Surge Stopper
3.5V ≤ V ≤ 60V, Expandable to 200V , Adjustable V
Clamp and
IN
OUT
Current Limit, Power Inductor Improves EMI, MSOP-12
100V, 1A Synchronous Micropower Step-Down Regulator
Integrated Power MOSFETs, 3V ≤ V ≤ 100V, 0.8V ≤ V
Q
≤ 60V,
OUT
IN
I = 7µA, TSSOP-20(16)
LTC3896
LTC3897
LTC7103
150V Low I , Synchronous Inverting DC/DC Controller
4V ≤ V ≤ 140V, 150V , –60V ≤ V
≤ –0.8V, Ground-Reference
Q
IN
PK
OUT
Interface Pins, Adjustable 5V to 10V Gate Drive, I = 40µA
Q
PolyPhase Synchronous Boost Controller with Input/Output 4.5V ≤ V ≤ 65V, V
Protection and Adjustable Gate Drive Voltage
Up to 60V, I = 55µA Fixed Frequency 50kHz to
Q
IN
OUT
900kHz
105V, 2.3A Low EMI Synchronous Step-Down Regulator
4.4V ≤ V ≤ 105V, 1V ≤ V
≤ V , I = 2µA Fixed Frequency 200kHz to
OUT IN Q
IN
2MHz, 5mm × 6mm QFN
7801f
LT 0517 • PRINTED IN USA
www.linear.com/LTC7801
38
LINEAR TECHNOLOGY CORPORATION 2017
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500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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