LTC4121-4.2_15_技术文档

LTC4121/LTC4121-4.2

40V 400mA Synchronous

Step-Down Battery Charger

FeaTures

DescripTion

The LTC^®4121 is a 400mA constant-current/constant-

voltage (CC/CV) synchronous step-down battery charger.

In addition to CC/CV operation, the LTC4121 regulates its

input voltage to a programmable percentage of the input

open-circuit voltage. This technique maintains maximum

power transfer with high impedance input sources such

as solar panels.

n

Wide Input Voltage Range: 4.4V to 40V

Temperature Compensated Input Voltage

n

Regulation for Maximum Power Point Tracking

(MPPT)

n

Adjustable Float Voltage 3.5V to 18V (LTC4121)

n

Fixed 4.2V Float Voltage Option (LTC4121-4.2)

n

High Efficiency: Up to 95%

n

50mA to 400mA Programmable Charge Current

An external resistor programs the charge current up to

400mA. The LTC4121-4.2 is suitable for charging Li-Ion/

Polymer batteries, while the programmable float voltage

of the LTC4121 is suitable for several battery chemistries.

n

1% ꢀeedbacꢁ Voltage Accuracy

n

Programmable 5% Accurate Charge Current

n

Thermally Enhanced, Low Profile (0.75mm)

16-Lead (3mm × 3mm) QꢀN Pacꢁage

The LTC4121 and LTC4121-4.2 include an accurate RUN

pinthreshold,lowvoltagebatterypreconditioningandbad

battery fault detection, timer termination, auto-recharge,

and NTC temperature qualified charging. The FAULT pin

providesanindicationofbadbatteryortemperaturefaults.

applicaTions

n

Handheld Instruments

n

Solar Powered Devices

n

Industrial/Military Sensors and Devices

Once charging is terminated, the LTC4121 signals end-of-

charge via the CHRG pin, and enters a low current SLEEP

mode. An auto-restart feature starts a new charging cycle

if the battery voltage drops by 2.2%.

L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarꢁs

of Linear Technology Corporation. All other trademarꢁs are the property of their respective

owners.

Typical applicaTion

High Efficiency, Wide Input Voltage Range Charging with LTC4121

LTC4121 Efficiency vs V_INat V_FLOAT= 8.4V

97

IN

INTV

CC

200mA, R

400mA, R

= 6.04k

= 3.01k

PROG

RUN

BOOST

2.2µF

10µF

10k

95

93

91

89

87

22nF

SLF6025T-470MR48

MPPT

LTC4121

SW

CHGSNS

BAT

V

IN

+

+ 200mV

BAT

–

TO 40V

1.96M

22µF

PROG

FB

787k

+

FREQ

GND FBG

Li-Ion

R

PROG

V

= 8.3V

BAT

5

10

15

20

25

(V)

30

35

40

4121 TA01a

V

IN

4121 TA01b

4121fa

1

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

absoluTe MaxiMuM raTings

(Note 1)

IN, RUN, CHRG, FAULT, MPPT ................... –0.3V to 43V

I

, I

, ........................................................ 5mA

(LTC4121)................................................. 5mA

(LTC4121-4.2) ........................................... 5mA

.................................................................. –5mA

CHRG FAULT

I , I

BOOST ................................... V – 0.3V to (V + 6V)

SW

ꢀB ꢀBG

I

BATSNS

SW (DC)........................................ –0.3V to (V + 0.3V)

IN

SW (Pulsed <100ns) ......................–1.5V to (V + 1.5V)

I

IN

INTVCC

CHGSNS, BAT, ꢀB/BATSNS, ꢀBG................ –0.3V to 18V

Operating Junction Temperature Range

ꢀREQ, NTC, PROG, INTV .......................... –0.3V to 6V

(Note 2).................................................. –40°C to 125°C

Storage Temperature Range .................... –65°C to 150°

CC

I

, I ..................................................... 600mA

CHGSNS BAT

pin conFiguraTion

LTC4121

LTC4121-4.2

TOP VIEW

16 15 14 13

INTV

1

2

3

4

12 NTC

11 FBG

INTV

1

2

3

4

12 NTC

11 NC

CC

BOOST

IN

BOOST

IN

GND

FB

BATSNS

10

9

10

9

SW

BAT

SW

BAT

5

6

7

8

5

6

7

8

UD PACKAGE

16-LEAD (3mm × 3mm) PLASTIC QFN

UD PACKAGE

16-LEAD (3mm × 3mm) PLASTIC QFN

T

= 125°C, θ = 54°C/W

T

= 125°C, θ = 54°C/W

JMAX

JA

JMAX JA

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB TO OBTAIN θ

JA

orDer inForMaTion

LTC4121 Options

PART NUMBER

LTC4121

FLOAT VOLTAGE

Programmable

4.2V ꢀixed

LTC4121-4.2

LEAD FREE FINISH

LTC4121EUD#PBꢀ

LTC4121IUD#PBꢀ

TAPE AND REEL

PART MARKING

LGHC

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

LTC4121EUD#TRPBꢀ

LTC4121IUD#TRPBꢀ

16-Lead (3mm × 3mm) Plastic QꢀN

LGHC

LTC4121EUD-4.2#PBꢀ

LTC4121IUD-4.2#PBꢀ

LTC4121EUD-4.2#TRPBꢀ LGMV

LTC4121IUD-4.2#TRPBꢀ LGMV

Consult LTC Marꢁeting for parts specified with wider operating temperature ranges.

Consult LTC Marꢁeting for information on nonstandard lead based finish parts.

ꢀor more information on lead free part marꢁing, go to: http://www.linear.com/leadfree/

ꢀor more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

4121fa

2

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. V_IN= V_RUN= 15V, V_CHGSNS= V_BAT= 4V, R_PROG= 3.01k,

V_FB= 2.29V (LTC4121), V_BATSNS= 4V (LTC4121-4.2). Current into a pin is positive out of a pin is negative. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

4.4

0

TYP

MAX

40

UNITS

V

l

Operating Input Supply Range

Battery Voltage Range

LTC4121 (Note 3)

18

V

LTC4121-4.2

0

4.2

V

I

DC Supply Current

Switching: ꢀREQ = GND

Standby Mode: (Note 4)

Sleep Mode: (Note 4)

3.5

mA

µA

IN

l

142

260

110

LTC4121-4.2: V

=

60

µA

BATSNS

4.4V

LTC4121: V = 2.51V (Note

ꢀB

6)

l

Disabled Mode: V < V

< V (Note 4)

37

20

80

40

µA

SD

RUN

EN

Shutdown Mode: (Note 4)

∆V

UV

Differential Undervoltage Locꢁout

Hysteresis

V

IN

V

IN

– V ꢀalling, V = 5V (LTC4121)

20

160

mV

DUVLO

BAT

IN

– V

ꢀalling, V = 5V (LTC4121-4.2)

IN

BATSNS

V

IN

V

IN

– V Rising, V = 5V (LTC4121)

115

mV

BAT

IN

– V

Rising, V = 5V (LTC4121-4.2)

IN

BATSNS

l

INTV Undervoltage Locꢁout

INTV Rising, V = INTV + 100mV

4.00

4.14

4.15

220

4.24

1.7

4.26

4.29

V

mV

V

INTVCC

CC

IN

CC

Hysteresis

INTV ꢀalling

CC

INTV Regulated voltage

CC

INTV Load Regulation

INTV = 0mA to –5mA (Note 5)

%

CC

Battery Charger

l

I

BAT Standby Current

Standby Mode (LTC4121) (Notes 4, 8, 9)

Standby Mode (LTC4121-4.2) (Notes 4, 8, 9)

2.5

50

4.5

1000

µA

nA

BAT

l

BAT Shutdown Current

Shutdown Mode (LTC4121) (Notes 4, 8, 9)

Shutdown Mode (LTC4121-4.2) (Notes 4, 8, 9)

1100

10

2000

1000

nA

l

I

BATSNS Standby Current (LTC4121-4.2)

Standby Mode (Notes 4, 8, 9)

5.4

1100

25

10

2000

60

µA

nA

µA

BATSNS

BATSNS Shutdown Current (LTC4121-4.2) Shutdown Mode (Notes 4, 8, 9)

I

ꢀeedbacꢁ Pin Bias Current (LTC4121)

V

ꢀB

= 2.5V (Note 6)

ꢀB

ꢀeedbacꢁ Ground Leaꢁage Current

(LTC4121)

Shutdown Mode (Note 4)

1

ꢀBG_LEAK

l

R

ꢀeedbacꢁ Ground Return Resistance

(LTC4121)

1000

2000

Ω

ꢀBG

V

ꢀeedbacꢁ Pin Regulation Voltage

(LTC4121)

(Note 6)

2.393

2.370

4.188

4.148

383

2.400

2.407

2.418

4.212

4.231

421

V

ꢀB(REG)

Regulated ꢀloat Voltage (LTC4121-4.2)

4.200

V

ꢀLOAT

CHG

l

V

I

Battery Charge Current

R

= 3.01ꢁ

= 24.3ꢁ

402

50

mA

mV

mA/mA

PROG

45

55

PROG

V

Battery Recharge Threshold

V

ꢀalling Relative to V (LTC4121)

ꢀB(REG)

–38

–49

–93

988

–62

RCHG

ꢀB

ꢀalling Relative to V (LTC4121-4.2)

ꢀLOAT

–70

–114

RCHG_4.2

PROG

BATSNS

h

Ratio of BAT Current to PROG Current

V

< V < V

TRKL_42

(LTC4121),

ꢀB(REG)

TRKL

ꢀB

< V

(LTC4121-4.2)

ꢀLOAT

BATSNS

l

V

PROG Pin Servo Voltage

1.206

1.227

300

1.248

V

mΩ

PROG

R

CHGSNS-BAT Sense Resistor

I

= –100mA

SNS

BAT

4121fa

3

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. V_IN= V_RUN= 15V, V_CHGSNS= V_BAT= 4V, R_PROG= 3.01k,

V_FB= 2.29V (LTC4121), V_BATSNS= 4V (LTC4121-4.2). Current into a pin is positive out of a pin is negative. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I

Low Battery Linear Charge Current

V

< V , V = 2.6V (LTC4121) (Note 6)

TRKL BAT

6

9

16

mA

LOWBAT

ꢀB

< V , V = 2.6V (LTC4121-4.2)

TRKL_4.2 BAT

BATSNS

l

V

Low Battery Threshold Voltage

V

Rising (LTC4121)

BATSNS

2.15

2.21

147

2. 28

V

LOWBAT

BAT

Rising (LTC4121-4.2)

Hysteresis

mV

mA

I

Switch Mode Tricꢁle Charge Current

V

< V , V < V

(LTC4121) (Note 6)

I

/10

TRKL

LOWBAT

BAT ꢀB

TRKL

CHG

< V

(LTC4121-4.2)

BATSNS

TRKL_42

PROG Pin Servo Voltage in Tricꢁle Charge

< V , V > V

(LTC4121) (Note 6)

122

mV

BAT ꢀB

TRKL

< V

(LTC4121-4.2)

BATSNS

TRKL_42

l

V

Tricꢁle Charge Threshold (LTC4121)

Hysteresis (LTC4121)

Rising (Note 6)

ꢀalling (Note 6)

1.65

2.86

1.68

50

1.71

2.98

V

mV

TRKL

ꢀB

Tricꢁle Charge Threshold (LTC4121-4.2)

Hysteresis (LTC4121-4.2)

Rising

ꢀalling

2.91

88

V

TRKL_4.2

BATSNS

mV

h

C/10

End of Charge Indication Current Ratio

Safety Timer Termination Period

Bad Battery Termination Timeout

(Note 7)

0.1

2.0

30

mA/mA

hrs

1.3

19

2.8

42

min

Switcher

l

f

Switching ꢀrequency

ꢀREQ = INTV

ꢀREQ = GND

1.0

0.5

1.5

0.75

120

2.0

1.0

MHz

ns

OSC

CC

t

Minimum Controllable On-Time

Duty Cycle Maximum

MIN_ON

94

%

Top Switch R

I

= –100mA

0.8

0.5

Ω

DSON

SW

Bottom Switch R

= 100mA

Ω

DSON

I

Peaꢁ Inductor Current Limit

Measured Across R

with a 15µH Inductor in

585

1050

1250

mA

PEAK

SNS

Series with R

(Note 10)

SNS

l

Switch Pin Current (Note 9)

IN Open-Circuit, V = V = 4.2V (LTC4121-4.2)

7

15

30

µA

SW

BAT

SW

IN Open-Circuit, V = V = 8.4V (LTC4121)

15

BAT

SW

Status Pins FAULT, CHRG

Pin Output Voltage Low

Pin Leaꢁage Current

I = 2mA

V = 43V, Pin High-Impedance

550

1

mV

µA

0

NTC

l

Cold Temperature V /V

ꢀault

Rising V

ꢀalling V

Rising V

ꢀalling V

Rising V

Threshold

73

35.5

1

74

72

75

%INTV

NTC INTVCC

NTC

CC

Hot Temperature V /V

36.5

37.5

2

37.5 %INTV

%INTV

NTC INTVCC

NTC Disable Voltage

3

%INTV

3

NTC Input Leaꢁage Current

V

NTC

= V

–50

50

nA

INTVCC

4121fa

4

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. V_IN= V_RUN= 15V, V_CHGSNS= V_BAT= 4V, R_PROG= 3.01k,

V_FB= 2.29V (LTC4121), V_BATSNS= 4V (LTC4121-4.2). Current into a pin is positive out of a pin is negative. (Note 2)

SYMBOL

RUN

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Enable Threshold

Hysteresis

V

Rising

ꢀalling

= 40V

ꢀalling

2.35

2.45

200

2.55

V

mV

µA

V

EN

RUN

Run Pin Input Current

Shutdown Threshold

Hysteresis

0.01

0.1

1.2

0.4

SD

220

mV

FREQ

l

ꢀREQ Pin Input Low

ꢀREQ Pin Input High

ꢀREQ Pin Input Current

V

3.6

1

0 < V

< V

µA

ꢀREQ

INTVCC

MPPT

l

I

MPPT Pin Leaꢁage Current

MPPT Sample Period

V

= 4.2V

15

28

1000

nA

s

MPPT

T

Period Between Charger Disabled Events

Charger Disabled Pulse Width

MP

PW

MPPT Sample Pulse Width

Internal Divider Gain

36

ms

V/V

mV

MP

K

V

Internal DAC Voltage as a Ratio to V

0.098

10

0.1

–45

0.102

–100

ꢀ

IN

MPPT Error Amp Gain Offset

V

– V , I = 50%• I

MP(OS)

MPPT DAC BAT CHG

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: Standby mode occurs when the LTC4121/LTC4121-4.2 stops

switching due to an NTC fault, MPPT pause, or when the charge current

has dropped low enough to enter Burst Mode operation. Disabled mode

occurs when V

is between V and V . Shutdown mode occurs

RUN

SD EN

when V

is below V or when the differential undervoltage locꢁout

RUN

SD

Note 2: The LTC4121 is tested under pulsed load conditions such that

is engaged. Sleep mode occurs after a timeout while the battery voltage

remains above the V or V threshold.

T ≈ T . The LTC4121E is guaranteed to meet performance specifications

J

A

RCHG

RCHG_42

for junction temperatures from 0°C to 85°C. Specifications over the

–40°C to 125°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls.

The LTC4121I is guaranteed over the full –40°C to 125°C operating

junction temperature range. Note that the maximum ambient temperature

consistent with these specifications is determined by specific operating

conditions in conjunction with board layout, the rated pacꢁage thermal

impedance, and other environmental factors.

Note 5: The internal supply INTV should only be used for the NTC

CC

divider, it should not be used for any other loads

Note 6: ꢀor the LTC4121, the ꢀB pin is measured with a resistance of 588ꢁ

in series with the pin.

Note 7: h

is expressed as a fraction of measured full charge current as

C/10

measured at the PROG pin voltage when the CHRG pin de-asserts.

Note 8: In an application circuit with an inductor connected from SW to

CHGSNS, the total battery leaꢁage current when disabled is the sum of

Note 3: If a battery voltage greater than 11V can be hot plugged to the

LTC4121 a reverse blocꢁing diode is required in series with the BAT pin to

prevent large inrush current into the low impedance BAT pin.

I

and I (LTC4121-4.2) or I and I

and I (LTC4121).

ꢀBG_LEAK SW

BATSNS

SW

BAT

Note 9: When no supply is present at IN, the SW powers IN through the

body diode of the top side switch. This may cause additional SW pin

current depending on the load present at IN.

Note 10: Guaranteed by design and/or correlation to static test.

4121fa

5

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

T_A= 25°C, unless otherwise noted.

Typical perForMance characTerisTics

IN Pin Standby Current

Typical V_FB(REG)vs Temperature

Typical V_FLOATvs Temperature

vs Temperature

2.43

2.42

2.41

2.40

2.39

2.38

2.37

2.36

180

4.25

4.24

4.23

4.22

4.21

4.20

4.19

4.18

4.17

4.16

4.15

4 UNITS TESTED

LTC4121

= 15V

V

= 15V

IN

170

160

150

140

130

120

110

100

90

V

IN

HIGH LIMIT

3 UNITS TESTED

DUT1 V

DUT2 V

DUT3 V

FLOAT

LTC4121-4.2

V

= 5V

IN

LOW LIMIT

HIGH LIMIT

DUT1

DUT2

DUT3

DUT4

LOW LIMIT

STANDBY FREQ HIGH

STANDBY FREQ LOW

80

–40 –25 –10

5

20 35 50 65 80 95 110 125

–40 –25 –10

5

20 35 50 65 80 95 110 125

–40 –25 –10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

4121 G01

4121 G03

4121 G02

IN Pin Sleep/Disabled/Shutdown

Current vs Temperature

BAT Pin Sleep/Shutdown Current

vs Temperature

Feedback Pin Standby or Sleep/

Disabled Current vs Temperature

90

80

70

60

50

40

30

20

10

0

8

7

6

5

4

3

2

1

0

60

50

40

30

20

10

0

V

= 15V

LTC4121

IN

STANDBY V = 2.51V

FB

SLEEP/DIS V = 2.51V

FB

SLEEP V

SHUTDOWN V

= 8.4V

= 4.2V

BAT

= 8.4V

= 4.2V

BAT

SLEEP

DIS

SD

–40 –25 –10

5

20 35 50 65 80 95 110 125

–40 –25 –10

5

20 35 50 65 80 95 110 125

–40 –25 –10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

4121 G04

4121 G05

4121 G06

BATSNS Pin Sleep/Standby or

Shutdown/Disabled Current

vs Temperature

BAT Pin Standby/Sleep/Shutdown

Current vs Temperature

Typical R_SNSCurrent Limit I_PEAK

vs Temperature

8

7

6

5

4

3

2

1

0

800

700

600

500

400

300

200

100

0

1120

1100

1080

1040

1020

1000

980

3 UNITS TESTED

DUT1

LTC4121-4.2

DUT2

DUT3

SHUTDOWN V

= 4.25V

BAT

STANDBY V

= 4.25V

BAT

SLEEP V

BAT

= 4.25V

SLEEP/STANDBY V

SHUTDOWN/DIS V

= 4.25V

BATSNS

960

940

920

–40 –25 –10

5

20 35 50 65 80 95 110 125

–40 –25 –10

5

20 35 50 65 80 95 110 125

–40 –25 –10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

4121 G07

4121 G08

4121 G09

4121fa

6

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

T_A= 25°C, unless otherwise noted.

Typical perForMance characTerisTics

Typical Battery Charge Current

vs Temperature

Efficiency vs I_BAT

100

90

80

70

60

50

40

450

400

350

300

250

200

150

100

50

V

= 15V

BAT

IN

= 3.8V

R

= 3.01k

= 6.04k

= 12.1k

= 24.3k

PROG

V

= 9V

IN

= 14V

= 19V

= 24V

LTC4121-42

= 4.2V

V

BAT

FREQ = LOW

= SLF12575T-470M2R7

L

SW

0

100

200

(mA)

300

400

–40 –25 –10

5

20 35 50 65 80 95 110 125

I

TEMPERATURE (°C)

BAT

4121 G10

4121 G11

Typical Solar Charging Cycle

Burst Mode Trigger Current

450

400

350

300

250

200

150

100

50

4.5

100

90

80

70

60

50

40

30

20

10

0

V

BAT

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

I

BAT

V

CHRG

BAT = 500mAHr

= TDK SLF7045

L

SW

47µH

= 732k,

= 976k

R

FB1

FB2

R

PROG

R

PROG

= 3.01kΩ

= 6.04kΩ

= 3.01k

PROG

0

0.5

1

1.5

2

2.5

3

3.5

5

10

15

20

25

(V)

30

35

40

TIME (HR)

V

IN

4121 G12

4121 G13

IN Pin Shutdown Current

vs Input Voltage

IN Pin Disabled Current

vs Input Voltage

Typical Burst Mode Waveforms

80

70

60

50

40

30

20

10

0

80

SHUTDOWN 130°C

SHUTDOWN 25°C

SHUTDOWN –45°C

DISABLED 130°C

DISABLED 25°C

DISABLED –45°C

70

60

50

40

30

20

10

0

V

SW

5V/DIV

V

PROG

200mV/DIV

I

SW

200mA/DIV

4121 G14

4µs/DIV

V

= 15V

IN

= 4.2V

BAT

I

= 38mA

5

10

15

20

25

(V)

30

35

40

5

10

15

20

25

(V)

30

35

40

FREQ = GND

V

IN

4121 G15

4121 G16

4121fa

7

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

T_A= 25°C, unless otherwise noted.

Typical perForMance characTerisTics

IN Pin Switching Current

vs Input Voltage

IN Pin Sleep Current

vs Input Voltage

IN Pin Standby Current

vs Input Voltage

180

7

6

5

4

3

2

1

0

140

120

100

80

I

= 0

SLEEP 130°C

SLEEP 25°C

SLEEP –45°C

BAT

170

160

150

140

130

120

110

100

FREQ = INTV

CC

60

40

FREQ = GND

130°C

25°C

20

STANDBY FREQ HIGH 25°C

STANDBY FREQ LOW 25°C

90

80

–45°C

0

5

10

15

20

25

(V)

30

35

40

5

10

15

20

25

(V)

30

35

40

5

10

15

20 25 30 35

40

V

(V)

IN

4121 G17

4121 G18

4121 G19

pin FuncTions

INTV (Pin 1): Internal Low Drop Out (LDO) Regulator

GND(Pin5, ExposedPadPin17):GroundPin. Connectto

Exposed Pad. The Exposed Pad must be soldered to PCB

GND to provide a low electrical and thermal impedance

connection to ground.

CC

Output Pin. This pin is the output of an internal linear

regulator that generates the internal INTV supply from

CC

IN.Italsosuppliespowertotheswitchgatedriversandthe

lowbatterylinearchargecurrentI

. Connecta2.2µꢀ

LOWBAT

MPPT (Pin 6): Maximum Power Point Tracꢁing Pin. This

low ESR capacitor from INTV to GND. Do not place any

CC

pin is used to program an input voltage regulation loop.

external load on INTV other than the NTC bias networꢁ.

CC

Connect an external resistive divider from V to MPPT to

IN

When the RUN pin is above V , and INTV rises above

EN

CC

GND. This divider programs the maximum power point

voltage as percentage of the input open-circuit voltage.

ꢀor more information on programming the MPPT resis-

tive divider refer to the Application Information section. If

the input voltage regulation feature is not used, connect

the UVLO threshold and IN rises above BAT by ∆V

DUVLO

and its hysteresis, the charger is enabled.

BOOST(Pin2):BoostedSupplyPin.Connecta22nꢀboost

capacitor from this pin to the SW pin.

MPPT to either INTV or IN with a minimum 10ꢁ resistor.

CC

IN (Pin 3): Positive Input Power Supply. Decouple to GND

with a 10µꢀ or larger low ESR capacitor. The input supply

impedance and the input decoupling capacitor form an RC

networꢁ that must settle during the MPPT sample pulse

width of about 36ms. This allows the LTC4121 to sample

the open-circuit voltage.

Keep parasitic capacitance at the MPPT pin to a minimum

as capacitance at this pin forms a pole that may interfere

with switching regulator stability.

FREQ (Pin 7): Step-Down Regulator Switching ꢀrequency

Select Input Pin. Connect to INTV to select a 1.5MHz

CC

switching frequency or GND to select a 750ꢁHz switching

SW (Pin 4): Switch Pin. The SW pin delivers power from

IN to BAT via the step-down switching regulator. An in-

ductor should be connected from SW to CHGSNS. See

the Applications Information section for a discussion of

inductor selection.

frequency. Do not float.

CHGSNS (Pin 8): Battery Charge Current Sense Pin. An

internal current sense resistor between CHGSNS and BAT

pins monitors battery charge current. An inductor should

be connected from SW to CHGSNS.

4121fa

8

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

pin FuncTions

BAT (Pin 9): Battery Output Pin. Battery charge current

is delivered from this pin through the internal charge

current sense resistor. In low battery conditions a small

represents the average charge current using the following

formula:

V

PROG

I_CHG= h_PROG

•

linear charge current, I

, is sourced from this pin

LOWBAT

R_PROG

to precondition the battery. Decouple the BAT pin with a

low ESR 22µꢀ ceramic capacitor to GND.

where h

is typically 988. Keep parasitic capacitance

PROG

BATSNS (Pin 10, LTC4121-4.2 Only): Battery Voltage

Sense Pin. ꢀor proper operation, this pin must always be

connectedphysicallyclosetothepositivebatteryterminal.

on the PROG pin to a minimum. If monitoring charge cur-

rent via the voltage at the PROG pin add a series resistor

of at least 2ꢁ to isolate stray capacitance from this node.

FB (Pin 10, LTC4121 Only): Battery Voltage ꢀeedbacꢁ

Reference Pin. The charge function operates to achieve a

final float voltage of 2.4V at this pin. Battery float voltage

is programmed using a resistive divider from BAT to ꢀB

to ꢀBG, and can be programmed from 3.5V up to 18V.

CHRG (Pin 14): Open-drain Charge Status Output Pin.

Typically pulled up through a resistor to a reference

voltage, the CHRG pin indicates the status of the battery

charger. The pin can be pulled up to voltages as high as

IN when disabled, and can sinꢁ currents up to 5mA when

enabled. When the battery is being charged, the CHRG

pin is pulled low. When the termination timer expires or

the charge current drops below 10% of the programmed

value, the CHRG pin is forced to a high impedance state.

The feedbacꢁ pin input bias current, I , is 25nA. Using a

ꢀB

resistive divider with a Thevenin equivalent resistance of

588ꢁ compensates for input bias current error.

FBG (Pin 11, LTC4121 Only): ꢀeedbacꢁ Ground Pin. This

pindisconnectstheexternalꢀBdividerloadfromthebattery

when it is not needed. When sensing the battery voltage

FAULT (Pin 15): Open-drain ꢀault Status Output Pin. Typi-

cally pulled up through a resistor to a reference voltage,

this status pin indicates fault conditions during a charge

cycle. The pin can be pulled up to voltages as high as IN

when disabled, and can sinꢁ currents up to 5mA when

enabled. An NTC temperature fault causes this pin to be

pulled low. A bad battery fault also causes this pin to

be pulled low. If no fault conditions exist, the FAULT pin

remains high impedance.

this pin presents a low resistance, R , to GND. When in

ꢀBG

disabled or shutdown modes this pin is high impedance.

NTC(Pin12):InputtotheNegativeTemperatureCoefficient

Thermistor Monitoring Circuit. The NTC pin connects to

a negative temperature coefficient thermistor which is

typically co-pacꢁaged with the battery to determine if the

battery is too hot or too cold to charge. If the battery’s

temperatureisoutofrange,theLTC4121entersSTANDBY

mode and charging is paused until the battery tempera-

ture re-enters the valid range. A low drift bias resistor is

RUN (Pin 16): Run Pin. When RUN is pulled below V

EN

and its hysteresis, the device is disabled. In disabled

mode, battery charge current is zero and the CHRG and

FAULT pins assume high impedance states. If the voltage

required from INTV to NTC and a thermistor is required

CC

from NTC to GND. Tie the NTC pin to GND, and omit the

NTC resistive divider to disable NTC qualified charging if

NTC functionality is not required.

at RUN is pulled below V , the device is in SHUTDOWN

SD

mode. When the voltage at the RUN pin rises above V ,

EN

the INTV LDO turns on. When the INTV LDO rises

CC

above its UVLO threshold the charger is enabled. The

PROG (Pin 13): Charge Current Program and Charge

Current Monitor Pin. Connect a 1% resistor between

3.01ꢁ (400mA) and 24.3ꢁ (50mA) from PROG to ground

to program the charge current. While in constant-current

mode, this pin regulates to 1.227V. The voltage at this pin

RUN pin should be tied to a resistive divider from V to

IN

program the input voltage at which charging is enabled.

Do not float the RUN pin.

4121fa

9

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

block DiagraM

4121fa

10

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

block DiagraM

LTC4121-4.2

INTV

CC

CHGSNS

+

R

SNS

–

I

TH

0.3Ω

C-EA

BAT

BATSNS

IN-80mV

+

–

DUVLO

V

IN

BATSNS

C

BAT

Li-Ion

22µF

INTV

R

INTV

+

–

CC

MPPT1

CC

gm

MPPT

K

• V

IN

+

R

588k

IN

I

MPPT

2.4V

–

MPPT2

V-EA

INTV

CC

9R

R

ENABLE

K • V

F

+

–

IN

K • V

F

IN

T

DAC

MP

+V

MP(OS)

PROG

–

+

BATSNS

2.21V

DZ

LOWBAT

4121 F02

Figure 2. LTC4121-4.2 BATSNS Connections

4121fa

11

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

operaTion

Overview

demanded charge current. When the input voltage drops

to V , the charge current is reduced so as to maintain

MP

V at V

The LTC4121 is a synchronous step-down (bucꢁ)

monolithic battery charger with maximum power-point

tracꢁing (MPPT) control of the source voltage. The

LTC4121/LTC4121-4.2 serves as a constant-current/

constant-voltagebatterychargerwiththefollowingbuilt-in

charger functions: programmable charge current, battery

precondition with ½ hour timeout, precision shutdown/

run control, NTC thermal protection, a 2-hour safety ter-

mination timer, and automatic recharge. The LTC4121/

LTC4121-4.2 also provides output pins to indicate state

of charge and fault status.

.

IN

MP

V

OC

V

RECOVERS

= 30s

IN

V

MP

V

IN

TIME

T

MP

I

CHG

I

BAT

PAUSE CHARGER

PW = 36ms

TIME

4121 F03

MP

SAMPLE V

STORE

IN(OC)

IN DAC: 23µs

Figure 3. MPPT Timing Diagram

Maximum Power Point Tracking

TheLTC4121employsanMPPTalgorithmthatcomparesa

storedopen-circuitinputvoltagemeasurementagainstthe

instantaneous input voltage while charging. The LTC4121

automaticallyreducesthechargecurrentiftheinputvoltage

falls below the user defined percentage of the open-circuit

voltage. This algorithm lets the LTC4121 optimize power

transfer for a variety of different input sources including

first order temperature compensation of a solar panel.

Connect the MPPT pin to a resistive input voltage divider,

as shown in ꢀigure 4, to program the fraction (K ) of the

R

input voltage where the input voltage regulation loop

reduces available charge current. The LTC4121 reduces

chargecurrentiftheMPPTpinvoltagefallsbelowthefixed

fraction (K ) of the open-circuit voltage (V ). The ratio of

ꢀ

OC

(K /K ) defines the maximum power voltage (V ) of the

ꢀ

R

MP

applied power source as a ratio to the open-circuit voltage

(V ) following the relation:

OC

The LTC4121 periodically pauses charging to measure

the open-circuit voltage allowing the LTC4121 to tracꢁ

fluctuations in the available power. About once every 30

seconds the LTC4121 pauses charging and waits about

0.1• R_MPPT1+ R_MPPT2

V_MPK_ꢀ0.1

V_OCK_RK_R

(

)

=

R_MPPT2

36ms (PW ) for the input voltage to recover to its

MP

where the MPPT pin resistive divider gain is K = R

/

MPPT2

R

open-circuit potential. At the end of this recovery time,

(R

+ R

). These equations can be rearranged to

MPPT1

solveforR

MPPT2

the LTC4121 samples the input voltage divided by 10 (1/

intermsofK (0.1)andthemaximumpower

ꢀ

MPPT2

K ), and stores this value on a digital to analog converter

ꢀ

voltage divided by the open circuit voltage, (V /V ) as:

MP OC

(DAC). When charging resumes, the DAC voltage is com-

pared against the MPPT pin voltage that is programmed

with a resistive divider. If the MPPT voltage falls below

the DAC voltage, the charge current is reduced to regulate

the input voltage at that level. This regulation loop serves

to maintain the input voltage at or above a user defined

level that corresponds to the peaꢁ power available from

the applied source.

0.1

R_MPPT2

=

•R_MPPT1













V_MP

− 0.1

V

OC

This function serves to maintain the input voltage at or

above the peaꢁ power voltage while the LTC4121 charges

a battery.

A timing diagram illustrating the sampling of the open-

circuit voltage is shown below. The charge current drops

Because MPPT operation involves large changes of input

voltage, it is important to ensure that the programmed

maximum power voltage does not violate minimum input

operating conditions: 4.4V or 160mV above the battery

to zero and the LTC4121 waits PW and then samples

MP

the open-circuit voltage. When charging resumes the

input voltage collapses if the source cannot support the

voltage, whichever is higher.

4121fa

12

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

operaTion

V

FLOAT

LTC4121

BAT

IN

+

R

FB1

22µF

C

MPPT

R

Li-Ion

MPPT1

(OPTIONAL)

I

FB

FB2

MPPT

GND

FBG

I

MPPT

MPPT2

ENABLE

4121 F05

4121 F04

Figure 4. MPPT Resistive Divider

Figure 5. Programming the Float Voltage with LTC4121

WhennopowersourceisappliedtoV , forexamplewhen

input capacitor to 10µꢀ to avoid increasing the source

recovery time.

IN

using a solar panel source and the panel is in the darꢁ, the

MPPTpindividerdrainspowerfromthebatterythroughthe

body diode of the top side switch of the switching regula-

tor. To eliminate this leaꢁage path, the MPPT divider may

be connected to the anode of the Schottꢁy diode that is in

series with the panel, for examples see ꢀigures 1, 9, or 10.

Programming the Battery Float Voltage

ꢀor the LTC4121, the battery float voltage is programmed

by placing a resistive divider from the battery to ꢀB and

ꢀBG as shown in ꢀigure 5. The battery float voltage is

programmable anywhere from 3.5V up to 18V. The pro-

ꢀor example, consider charging a battery from a source

withanopen-circuitvoltageof30Vandasourceimpedance

of 120Ω. This resistive supply has a short circuit current

of 250mA, and the peaꢁ available power of 1.875W oc-

grammable battery float voltage, V , is then governed

ꢀLOAT

by the following equation:

R

_ꢀB1+ R_ꢀB2

R_ꢀB2

(

•

ꢀB(REG)

)

V

= V

ꢀLOAT

curs with a load of 125mA at 50% of V . To program the

OC

LTC4120 to optimize the available power for this source

simply program V /V to 50% by selecting the MPPT

where V

is typically 2.4V.

MP OC

ꢀB(REG)

resistivedividergainK =0.2.Thisisobtainedwitharesis-

R

Due to the input bias current (I ) of the voltage error amp

ꢀB

tive divider as shown in ꢀigure 4 with R

= R

/4.

MPPT2

MPPT1

(V-EA), care must also be taꢁen to select the Thevenin

With standard 1% resistors this is approximated with

= 402ꢁ, and R = 100ꢁ.

equivalent resistance of R //R close to 588ꢁΩ. Start

ꢀB1 ꢀB2

R

MPPT1

MPPT2

by calculating R to satisfy the following relations:

ꢀB1

If the MPPT pin sees excess capacitance to GND, this may

affectswitchingregulatorstability.Insuchcases,onemay

V_ꢀLOAT• 588ꢁ

R_ꢀB1

=

V_ꢀB(REG)

optionally add a 50pꢀ to 150pꢀ lead capacitor (C

shown in ꢀigure 4.

) as

MPPT

ꢀind the closest 0.1% or 1% resistor to the calculated

value. With R calculate:

The sampling of V is done at an extremely low duty

OC

ꢀB1

cycle so as to have minimum impact on the average

V

_ꢀB(REG)•R_ꢀB1

charge current. The time between sample events, T

,

MP

R_ꢀB2

=

− 1000Ω

is typically about 30 seconds, with an idle time, PW

MP

V

− V

ꢀB(REG)

ꢀLOAT

of about 36ms to allow the source to recover to its

open-circuit voltage through the time constant associ-

Where 1000Ω represent the typical value of R . This is

ꢀBG

ated with the input decoupling capacitor C . The time

the resistance of the ꢀBG pin which serves as the ground

IN

constant for the source to recover to its open-circuit

return for the battery float voltage divider.

voltage must be ꢁept below the idle period. Limit the

Once R and R are selected re-calculate the value of

ꢀB1

ꢀB2

V

ꢀLOAT

obtained with the resistors available. If the error

4121fa

13

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

operaTion

is too large substitute another standard resistor value for

PROG resistor sets the maximum charge current, or

the current delivered while the charger is operating in

constant-current (CC) mode.

R

and recalculate R . Repeat until the float voltage

ꢀB1

ꢀB2

error is acceptable.

Table1andTable2belowlistrecommendedstandard0.1%

and 1% resistor values for common battery float voltages.

Analog Charge Current Monitor

The PROG pin provides a voltage signal proportional

to the actual charge current. Care must be exercised in

measuringthisvoltageasanycapacitanceatthePROGpin

forms a pole that may cause loop instability. If observing

the PROG pin voltage, add a series resistor of at least 2ꢁ

and limit stray capacitance at this node to less than 50pꢀ.

Table 1. Recommended 0.1% Resistors for Common V_FLOAT

V

(V)

R

FB1

(kΩ)

R (kΩ)

FB2

TYPICAL ERROR (%)

FLOAT

3.6

887

1780

–0.13

0.15

–0.13

0.08

0.14

0.27

4.1

4.2

7.2

8.2

8.4

1010

1800

2000

2050

1420

1350

898

In the event that the input voltage cannot support the

demanded charge current, the PROG pin voltage may not

represent the actual charge current. In cases such as this,

the PWM switch frequency drops as the charger enters

dropout operation where the top switch remains on for

morethanoneclocꢁcycleastheinductorcurrentattempts

torampuptothedesiredcurrent.Ifthetopswitchremains

on in dropout for 8 clocꢁ cycles a dropout detector forces

the bottom switch on for the remainder of the 8th cycle.

In such a case, the PROG pin voltage remains at 1.227V,

but the charge current may not reach the desired level.

825

816

Table 2 Recommended 1% Resistors for Common V_FLOAT

V

(V)

R

FB1

(kΩ)

R (kΩ)

FB2

TYPICAL ERROR (%)

FLOAT

3.6

887

1780

–0.13

0.26

4.1

4.2

7.2

8.2

8.4

1000

1020

1780

2000

2100

1430

1370

887

–0.34

0.16

825

0.14

845

–0.50

NTC Thermal Battery Protection

Programming the Charge Current

TheLTC4121monitorsbatterytemperatureusingatherm-

istor during the charging cycle. If the battery temperature

moves outside a safe charging range, the IC suspends

charging and signals a fault condition until the tempera-

The current-error amp (C-EA) measures the current

through an internal 0.3Ω current sense resistor between

the CHGSNS and BAT pins. The C-EA outputs a fraction

of the charge current, 1/h

, to the PROG pin. The

PROG

voltage-error amp (V-EA) and PWM control circuitry can

limit the PROG pin voltage to control charge current. An

LTC4121

BAT

INTV

internal clamp (DZ) limits the PROG pin voltage to V

which in turn limits the charge current to:

,

PROG

CC

R

BIAS

NTC

h_PROG• V

1212V

R_PROG

PROG

+

–

I_CHG

=

TOO COLD

TOO HOT

ADJ

OPT

R_PROG

120V

74% INTV

37% INTV

CC

+

–

+

I_{CHG_ TRKL}

=

R

NTC

T

R_PROG

+

–

IGNORE NTC

Li-Ion

where h

is typically 988, V

is either 1.227V or

PROG

2% INTV

CC

122mV during tricꢁle charge, and R

is the resistance

PROG

4121 F06

of the grounded resistor applied to the PROG pin. The

Figure 6. NTC Connection

4121fa

14

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

operaTion

ture returns to the safe charging range. The safe charging

range is determined by two comparators that monitor the

voltage at the NTC pin. NTC qualified charging is disabled

End-of-Charge Indication and Safety Timeout

The LTC4121 uses a safety timer to terminate charging.

Whenever the LTC4121 is in constant current mode the

timer is paused, and when ꢀB rises or falls through the

if the NTC pin is pulled below about 85mV (V ).

DIS

Thermistor manufacturers usually include either a tem-

perature looꢁup table identified with a characteristic curve

number, or a formula relating temperature to the resistor

value. Each thermistor is also typically designated by a

thermistor gain value B25/85.

V

threshold the timer is reset. When the battery

RCHG

voltage reaches the float voltage, the safety timer begins

counting down a 2-hour timeout. If charge current falls

belowonetenthoftheprogrammedmaximumchargecur-

rent (h ), the CHRG status pin rises, but top-off charge

C/10

current continues to flow until the timer finishes. After the

The NTC pin should be connected to a voltage divider

timeout, the LTC4121 enters a low-power sleep mode.

from INTV to GND as shown in ꢀigure 6. In the simple

CC

application (R

= 0) a 1% resistor, R

, with a value

ADJ

BIAS

Automatic Recharge

equal to the resistance of the thermistor at 25°C is con-

Insleepmode,theICcontinuestomonitorbatteryvoltage.

nected from INTV to NTC, and a thermistor is connected

CC

If the battery falls 2.2% (V

or V ) from the full-

RCHG_42

from NTC to GND. With this setup, the LTC4121 pauses

RCHG

charge float voltage, the LTC4121 engages an automatic

recharge cycle as the safety timer is reset. Automatic

recharge has a built in delay of about 0.5ms to prevent

triggering a new charge cycle if a load transient causes

the battery voltage to drop temporarily.

charging when the resistance of the thermistor increases

to 285% the R

resistor as the temperature drops. ꢀor

BIAS

a Vishay Curve 2 thermistor with B25/85 = 3490 and 25°C

resistance of 10ꢁΩ, this corresponds to a temperature

of about 0°C. The LTC4121 also pauses charging if the

thermistor resistance decreases to 58.8% of the R

BIAS

State of Charge and Fault Status Pins

resistor. ꢀor the same Vishay Curve 2 thermistor, this

corresponds to approximately 40°C. With a Vishay Curve

2 thermistor, the hot and cold comparators both have

about 2°C of hysteresis to prevent oscillations about the

trippoints.TheNTCcomparatortrippointsareratiometric

The LTC4121 contains two open-drain outputs which

provide charge status and signal fault indications. The

CHRG pin pulls low to indicate charging at a rate higher

than C/10. The FAULT pin pulls low to indicate a bad bat-

tery timeout, or to indicate an NTC thermal fault condition.

During NTC faults the CHRG pin remains low, but when

a bad-battery timeout occurs the CHRG pin de-asserts.

When the open drain outputs are pulled up with a resistor,

Table 3 summarizes the charger state that is indicated by

the pin voltages.

to the INTV voltage, so NTC trip points are defined as a

CC

percentage of INTV . The HOT threshold is calculated as

CC

285%/385% = 74% of INTV and the COLD threshold is

CC

calculated as 58.8%/158% = 37% of INTV .

CC

Thehotandcoldtrippointsmaybeadjustedusingadiffer-

ent type of thermistor, or a different R

resistor, or by

BIAS

adding a desensitizing resistor, R , or by a combination

ADJ

Table 3 LTC4121 Open-Drain Indicators with Resistor Pull-Ups

of these measures as shown in ꢀigure 6. ꢀor example, by

FAULT

High

Low

CHRG CHARGER STATE

increasing R

to 12.4ꢁΩ, with the same thermistor as

BIAS

High Off or Topping-Off Charge at a Rate Less Than C/10.

before, the cold trip point moves down to –5°C, and the

hot trip point moves down to 34°C. If a Vishay Curve 1

thermistor with B25/85 = 3964 and resistance of 100ꢁΩ

Low

High Bad Battery ꢀault

Low NTC Thermal ꢀault, Charging Paused

Charging at Rate Higher Than C/10

Low

at 25°C is used, a 1% R

ADJ

and a hot trip point of 39°C.

resistor of 118ꢁΩ and a 1%

BIAS

R

resistor of 12.1ꢁΩ results in a cold trip point of 0°C,

Low Battery Voltage Operation

The LTC4121 automatically preconditions heavily dis-

charged batteries. If the battery voltage is below V

LOWBAT

minus its hysteresis (typically 2.05V - e.g. battery pacꢁ

4121fa

15

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

operaTion

protection has been engaged) a DC current, I

, is

User Selectable Switching Regulator Operating

Frequency

LOWBAT

applied to the BAT pin from the INTV supply. When

the battery voltage rises above V

CC

, the switching

LOWBAT

The LTC4121 uses a constant-frequency synchronous

step-down switching regulator architecture to pro-

duce high operating efficiency. The nominal operating

regulator is enabled and charges the battery at a tricꢁle

charge level of 10% of the full scale charge current (in

addition to the DC I

current). Tricꢁle charging of

LOWBAT

frequency, f , isprogrammedbypullingtheꢀREQpinto

OSC

thebatterycontinuesuntilthesensedbatteryvoltagerises

above the tricꢁle charge threshold, V , or V

either INTV or to GND to obtain a switching frequency

CC

.

TRKL_42

TRKL

of 1.5MHz or 750ꢁHz, respectively. The high operating

When the battery rises above the tricꢁle charge threshold

the full scale charge current is applied and the DC tricꢁle

charge current is turned off. If the battery remains below

the tricꢁle charge threshold for more than 30 minutes,

charging terminates and the fault status pin is asserted

to indicate a bad battery. After a bad battery fault, the

LTC4121 automatically restarts a new charge cycle once

the failed battery is removed and replaced with another

battery. The LTC4121-4.2 monitors the BATSNS pin volt-

age to sense LOWBAT and TRKL conditions.

frequency allows the use of smaller external components.

Selectionoftheoperatingfrequencyisatrade-offbetween

efficiency,componentsize,andmarginfromtheminimum

on-time of the switcher. Operation at lower frequency

improves efficiency by reducing internal gate charge and

switching losses, but requires larger inductance values to

maintain low output ripple. Operation at higher frequency

allows the use of smaller components, but may require

sufficient margin from the minimum on-time at the lowest

duty cycle if fixed-frequency switching is required.

Precision Run/Shutdown Control

PWM Dropout Detector

The LTC4121 remains in a low power disabled mode until

the RUN pin is driven above V (typically 2.45V). While

If the input voltage approaches the battery voltage, the

LTC4121mayrequiredutycyclesapproaching100%. This

mode of operation is ꢁnown as dropout. In dropout, the

operating frequency may fall well below the programmed

EN

the LTC4121 is in disabled mode, current drain from the

batteryisreducedtoextendbatterylifetime,thestatuspins

are both de-asserted, and the ꢀBG pin is high impedance.

Charging can be stopped at any time by pulling the RUN

pin below 2.25V. The LTC4121 also offers an extremely

low operating current shutdown mode when the RUN pin

f

value. If the top switch remains on for eight clocꢁ

OSC

cycles, the dropout detector activates and forces the

bottom switch on for the remainder of that clocꢁ cycle

or until the inductor current decays to zero. This avoids

a potential source of audible noise when using ceramic

input or output capacitors and prevents the boost sup-

ply capacitor for the top gate drive from discharging. In

dropout operation, the actual charge current may not be

able to reach the full-scale programmed value. In such a

scenario the analog charge current monitor function does

not represent actual charge current being delivered.

ispulledbelowV (typicallyabout0.7V).Inthiscondition

SD

less than 20µA is pulled from the supply at IN. Tie the RUN

pin to a resistive divider from the IN supply to program

the voltage where the LTC4121 turns on. Examples are

shown in ꢀigures 9 and 10.

Differential Under Voltage Lockout

The LTC4121 monitors the difference between the battery

voltage, V , and the input supply voltage, V . If the

Burst Mode^®Operation

BAT

IN

difference (V – V ) falls to ∆V , all functions are

IN

BAT

DUVLO

At low charge currents, for example during constant-

voltage mode, the LTC4121 automatically enters Burst

Mode operation. In Burst Mode operation the switcher is

periodically forced into standby mode in order to improve

disabled and the part is forced into shutdown mode until

(V – V ) rises above the ∆V

rising threshold. The

IN

BAT

DUVLO

BATSNS

LTC4121-4.2 monitors the V

and V pin voltages

IN

to sense DUVLO condition.

4121fa

16

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

operaTion

efficiency. The LTC4121 automatically enters Burst Mode

operation after it exits constant-current (CC) mode and as

the charge current drops below about 80mA. Burst Mode

operation is triggered at lower currents for larger PROG

resistors, and depends on the input supply voltage, the

batteryvoltage,andtheselectedinductor.RefertotheBurst

Mode Trigger Current and Typical Burst Mode Waveforms

graphs in the Typical Performance Characteristics section

formoreinformationonBurstModeoperation.BurstMode

operation has some hysteresis and remains engaged for

INTV from the BOOST pin to the SW pin. In the event

CC

that the bottom switch remains off for a prolonged period

of time, e.g. during Burst Mode operation, the BOOST

supply may require a refresh. Similar to the PWM dropout

timer, the LTC4121 counts the number of clocꢁ cycles

since the last BOOST refresh. When this count reaches

32 the next PWM cycle begins by turning on the bottom

side switch first. This pulse refreshes the BOOST flying

capacitor to INTV and ensures that the top-side gate

CC

driver has sufficient voltage to turn on the top side switch

battery current up to about 150mA, depending on L ,V

at the beginning of the next cycle.

SW IN

and V . When operating in Burst Mode, the PROG pin

BAT

Operation without an Input Supply or Shaded Panel

voltage to average charge current relationship is not well

defined. This may cause the CHRG pin to de-assert early

depending on the amplitude of the burst ripple.

When a battery is the only available power source, care

should be taꢁen to eliminate loading of the IN pin. Load

current on IN drains the battery voltage through the body

Boost Supply Refresh

diode of the top side power switch as V falls below V

.

IN

SW

The BOOST supply for the top gate drive in the LTC4121

switching regulator is generated by bootstrapping the

A diode inserted in series with the solar panel, as shown

on the front page schematic, eliminates this discharge

path. Alternatively, a diode may be placed in series with

the BAT pin (as shown in ꢀigure 8).

BOOST flying capacitor to INTV whenever the bottom

CC

switch is turned on. This technique provides a voltage of

4121fa

17

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

applicaTions inForMaTion

MPPT Programming

Using the schematic of ꢀigure 4, this ratio is obtained by

selecting:

The maximum power-point tracꢁing loop is programmed

by selecting a resistive divider from IN to MPPT to GND

as shown in ꢀigure 4. This user programmable voltage







K_ꢀ







K_ꢀ

75%

1−

R_MPPT1

=

•R_MPPT2

divider (K ) serves to define a fraction of the input voltage

R













that appears at the MPPT pin:

75%

R_MPPT2

R_MPPT1+ R_MPPT2

V_MPPT

K_R=

=

R

MPPT1

= 6.5 • R

MPPT2

V

IN

Using standard 1% resistors, this is obtained with:

= 787ꢁ and R = 121ꢁ.

This fraction of V is continuously compared against

IN

R

MPPT1

MPPT2

a fixed fraction of the open-circuit input voltage that is

storedwithintheLTC4121.Afixedinternalresistivedivider

MPPT Error Terms

(0.1•V ) is periodically sampled to compare the open-

IN

Uncertainty in programming the MPPT set point is bound

by three error terms: MPPT pin leaꢁage, DAC quantization

error, and the finite offset error in the MPPT error amp. All

circuit input voltage against the user defined fraction of

the loaded input voltage (K • V ). On an interval of T ,

R

IN

MP

the LTC4121 turns off all charger functions reverting to

error terms are lumped into V

, with a typical value

STANDBY mode. The LTC4121 then waits for a delay, of

MP(OS)

of –45mV. This offset at the input to the MPPT error amp

about 36ms, PW , after turning off the charge current to

MP

is multiplied by 1/K when observed at the IN regulation

allow the input supply to recover to its open-circuit volt-

R

point, V

.

age. ꢀinally, the LTC4121 samples the open-circuit input

MP

voltage V through a fixed internal divider; K = 1/10.

OC

ꢀ

ꢀor example, with the same K = 0.1333 (R

= 787ꢁ

R

MPPT1

error gets am-

Aftersamplingtheopen-circuitvoltage,theLTC4121turns

and R

= 121ꢁ) the –45mV V

MPPT2

MP(OS)

on all functions and reverts to normal operation. During

plified to –45mV/0.1333 = –338mV at V from the V

IN

MP

normaloperation, thestored0.1•V voltageiscompared

OC

set point of 75% of V . If V is 30V, the minimum V

OC

against the instantaneous MPPT pin voltage: K • V . If

R

IN

regulation point is about 22.16V, or 73.9% of the open-

the MPPT voltage falls below the stored level, the charge

circuit voltage.

current is reduced to maintain the input voltage. The ratio

ꢀor solar panel sources, the available power drops off

quicꢁly on the high side, and relatively slowly on the low

side, this is illustrated in the curve in ꢀigure 7. ꢀor these

types of sources, it is usually better to err on the low side

of 0.1/K defines the percentage below the open-circuit

R

voltage where charge current is reduced to maintain the

maximum input power.

Because MPPT operation involves large changes of input

voltage, it is important to ensure that the programmed

maximum power voltage does not violate minimum input

operating conditions: 4.4V or 160mV above the battery

voltage, whichever is higher.

when programming the V voltage. This is what the

MP

LTC4121 does normally, so most users can simply design

for a V voltage at (or just below) the level specified by

MP

the solar panel manufacturer. ꢀor more information on

solar panels, refer to the panel’s data sheet.

ꢀor example, to select an MPPT set point, V , at 75%

MP

of the open-circuit voltage, V , select ratio K using the

OC

R

following relation:

K_ꢀ

0.1

K_R=

=

= 0.1333

75% 0.75

4121fa

18

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

applicaTions inForMaTion

4

The maximum input voltage allowed to maintain constant

frequency operation is:

25°C

3

V

LOWBAT

V_IN(MAX)

=

f_OSC• t_MIN(ON)

75°C

2

where V

, is the lowest battery voltage where the

LOWBAT

switcher is enabled.

50°C

1

Exceedingtheminimumon-timeconstraintdoesnotaffect

charge current or battery float voltage, so it may not be

of critical importance in most cases and high switching

frequencies may be used in the design without any fear of

severeconsequences.AsthesectionsonInductorSelection

and Capacitor Selection show, high switching frequencies

allowtheuseofsmallerboardcomponents, thusreducing

the footprint of the applications circuit.

0

20

0

5

10

15

25

PANEL VOLTAGE (V)

4121 F07

Figure 7. Typical 3W Panel Power vs Voltage

Input Voltage and Minimum On-Time

The LTC4121 maintains constant frequency operation un-

dermostoperatingconditions.Undercertainsituationswith

high input voltage and high switching frequency selected

and a low battery voltage, the LTC4121 may not be able

to maintain constant frequency operation. These factors,

combined with the minimum on-time of the LTC4121,

impose a minimum limit on the duty cycle to maintain

fixed-frequency operation. The on-time of the top switch

ꢀixed-frequency operation may also be influenced by

dropoutandburstmodeoperationasdiscussedpreviously.

Switching Inductor Selection

Theprimarycriterionforswitchinginductorvalueselection

in an LTC4121 charger is the ripple current created in that

inductor. Once the inductance value is determined, the

saturation current rating for that inductor must be equal

to or exceed the maximum peaꢁ current in the inductor,

is related to the duty cycle (V /V ) and the switching

BAT IN

frequency, f

in Hz:

OSC

I

. The peaꢁ value of the inductor current is the sum

L(PEAK)

V_BAT

of the programmed charge current, I , plus one half of

CHG

t_ON

=

f_OSC• V_IN

the ripple current, ∆I . The peaꢁ inductor current must

L

also remain below the current limit of the LTC4121, I

.

PEAK

When operating from a high input voltage with a low

battery voltage, the PWM control algorithm may attempt

to enforce a duty cycle which requires an on-time lower

∆I_L

I_L(PEAK)= I_CHG

+

< I_PEAK

2

than the LTC4121 minimum, t

. This minimum

MIN(ON)

The current limit of the LTC4121, I

(and at most 1250mA). The typical value of I

tratedinagraphintheTypicalPerformanceCharacteristics,

Current Limit vs Temperature.

, is at least 585mA

PEAK

duty cycle is approximately 18% for 1.5MHz operation

or 9% for 750ꢁHz operation. If this occurs, the charge

current and battery voltage remains in regulation, but the

switching duty cycle may not remain fixed, or the switch-

ing frequency may decreases to an integer fraction of its

programmed value.

is illus-

PEAK

R

SNS

4121fa

19

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

applicaTions inForMaTion

ꢀor a given input and battery voltage, the inductor value

and switching frequency determines the peaꢁ-to-peaꢁ

ripplecurrentamplitudeaccordingtothefollowingformula:

to accurately sample the open-circuit voltage at V .

IN

Adequate settling is usually achieved in 3 to 5 R-C time

constants. To allow the LTC4121 to correctly sample the

open-circuit voltage, limit C to:

IN

V − V

f_OSC• V •L

• V

BAT

(

)

IN

BAT

∆I_L=

C < PW / (5 • R

),

IN

MP

SOURCE

IN

SW

where R

is the impedance of the power source.

SOURCE

Ripple current is typically set to be within a range of 20%

ꢀor a solar panel this is the impedance of the panel at the

to40%oftheprogrammedchargecurrent, I . Toobtain

open-circuit voltage. Looꢁing at a panel's I-V curve, the

CHG

a ripple current in this range, select an inductor value us-

ing the nearest standard inductance value available that

obeys the following formula:

source impedance is approximated by (V – V )/I

.

OC

MP MP

Typically V is about 80% of V , so the solar panels

MP

OC

source impedance can be approximated as:

R

≈ V / (5 • I ).

V

_IN(MAX)− V_ꢀLOAT• V

SOURCE

OC

MP

(

)

ꢀLOAT

L_SW

≥

f_OSC• V_IN(MAX)• 30% •I

(

)

Reverse Blocking

CHG

When a fully charged battery is suddenly applied to the

BAT pin, a large in-rush current charges the C capacitor

Then select an inductor with a saturation current rating

greater than I

IN

.

L(PEAK)

through the body diode of the LTC4121 topside power

switch. While the amplitude of this current can exceed

several Amps, the LTC4121 will survive provided the bat-

tery voltage is below about 11V. To completely eliminate

thisin-rushcurrent, ablocꢁingP-channelMOSꢀETshould

be placed in series with the BAT pin. When the battery is

the only source of power, this PMOS also serves to de-

Input Capacitor

The LTC4121 charger is biased directly from the input

supply at the V pin. This supply provides large switched

IN

currents, so a high-quality, low ESR decoupling capacitor

is recommended to minimize voltage glitches at V . Bulꢁ

IN

capacitanceisafunctionofthedesiredinputripplevoltage

crease battery drain current due to any load placed at V ,

IN

(∆V ), and follows the relation:

IN

conducted through the body diode of the topside power

switch on the LTC4121. The PMOS body diode shown in

ꢀigure 8 serves as the blocꢁing component since CHRG is

high impedance when the battery voltage is greater than

the input voltage. When CHRG pulls low, i.e. during most

of a normal charge cycle, the PMOS is on to reduce power

dissipation. The PMOS requires a forward current rating

equal to the programmed charge current and a reverse

breaꢁdownvoltageequaltotheprogrammedfloatvoltage.

V

V_IN

BAT

I_CHG

•

C_IN(BULK)

=

(µꢀ)

∆V_IN

Input ripple voltages (∆V ) above 0.01V are not recom-

mended. 10µꢀ is typically adequate for most charger

applications, with a voltage rating of 40V.

IN

The input capacitor also forms a pole with the source

impedance that supplies power to V . This R-C networꢁ

IN

must settle within the 36ms PW period for the LTC4121

MP

4121fa

20

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

applicaTions inForMaTion

4.99k

4.7µF

V

IN

CHRG

IN

49.9k

10µF

RUN

BAT

22µF

470k

+

SI2343DS

INTV

CC

LTC4121

GND

Li-Ion

2.2µF

R

FB1

PROG

FB

R

FB2

PROG

FBG

V

CHRG

IN

49.9k

10µF

RUN

BAT

22µF

4.7µF

470k

+

SIT2343DS

INTV

CC LTC4121-4.2

Li-Ion

2.2µF

BATSNS

4121 F08

PROG

R

PROG

GND

Figure 8. Reverse Blocking with a P-Channel MOSFET in Series with the BAT Pin

BAT Capacitor and Output Ripple: C

Boost Supply Capacitor

BAT

The LTC4121 charger output requires bypass capacitance

The BOOST pin provides a bootstrapped supply rail that

provides power to the top gate drivers. The operating volt-

connected from BAT to GND (C ). A 22µꢀ ceramic ca-

BAT

pacitor is required for all applications. In systems where

the battery can be disconnected from the charger output,

additional bypass capacitance may be desired. In this

type of application, excessive ripple and/or low amplitude

oscillations can occur without additional output bulꢁ

capacitance. ꢀor optimum stability, the additional bulꢁ

capacitance should also have a small amount of ESR. ꢀor

these applications, place a 100µꢀ low ESR non-ceramic

capacitor(chiptantalumororganicsemiconductorcapaci-

tors such as Sanyo OS-CONs or POSCAPs) from BAT to

GND, in parallel with the 22µꢀ ceramic bypass capacitor,

or use large ceramic capacitors with an additional small

seriesESRresistoroflessthan1Ω. Thisadditionalbypass

capacitance may also be required in systems where the

battery is connected to the charger with long wires. The

age of the BOOST pin is internally generated from INTV

CC

whenever the SW pin pulls low. This provides a floating

voltage of INTV above SW that is held by a capacitor

CC

tied from BOOST to SW. A low ESR ceramic capacitor

of 10nꢀ to 33nꢀ is sufficient, with a voltage rating of 6V.

INTV Supply and Capacitor

CC

Power for the top and bottom gate drivers and most other

internal circuitry is derived from the INTV pin. A low

CC

ESR ceramic capacitor of 2.2µꢀ is required on the INTV

CC

pin. The INTV supply has a relatively low current limit

CC

(about 20mA) that is dialed bacꢁ when INTV is low to

CC

reduce power dissipation. Do not use the INTV voltage

CC

to supply power for any external circuitry except for the

NTCBIAS networꢁ. When the RUN pin is above V , the

EN

voltage rating of all capacitors applied to C must meet

BAT

INTV supply is enabled, and when INTV rises above

CC

INTVCC

CC

or exceed the battery float voltage.

UV

, the charger is enabled.

4121fa

21

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

applicaTions inForMaTion

Calculating IC Power Dissipation

PCB Layout

The user should ensure that the maximum rated junction

temperatureisnotexceededunderalloperatingconditions.

To prevent magnetic and electrical field radiation and

high frequency resonant problems, proper layout of the

components connected to the LTC4121 is essential. ꢀor

maximum efficiency, the switch node rise and fall times

should be minimized. The following PCB design priority

list will help insure proper topology. Layout the PCB using

the guidelines listed below in this specific order:

The thermal resistance of the LTC4121 pacꢁage (θ ) is

JA

54°C/W; provided that the Exposed Pad is in good thermal

contact with the PCB. The actual thermal resistance in the

application will depend on the forced air cooling and other

heat sinꢁing means, especially the amount of copper on

the PCB to which the LTC4121 is attached. The actual

power dissipation while charging is approximated by the

following formula:

1. V inputcapacitorshouldbeplacedascloseaspossible

IN

to the IN pin with the shortest copper traces possible.

The ground return of the input capacitor should be

connected to a solid ground plane.

P = V − V

•I

TRKL

(

)

D

IN

BAT

2. Place the inductor as close as possible to the SW

pin. Minimize the surface area of the SW pin node.

Maꢁe the trace width the minimum needed to support

the programmed charge current, and ensure that the

spacing to other copper traces be maximized to reduce

capacitance from the SW node to any other node.

+ V •I

IN

IN(SWITCHING)

+ R_SNS•I²_CHG













V

BAT

+ R_DSON(TOP)

•

•I²

CHG

IN









3. Place the BAT capacitor adjacent to the BAT pin and

ensure that the ground return feeds to the solid ground

plane.

V

•I²

CHG

BAT

+ R_DSON(BOT)• 1−





IN

Duringtricꢁlecharge(V <V

)thepowerdissipation

BAT

TRKL

4. Routeanalogground(RUNpindividergroundedresistor,

may be significant as I

is typically 10mA, however

TRKL

the MPPT pin divider, and INTV capacitor ground) to

CC

during normal charging the I

term is zero. I

is

TRKL

the solid ground plane.

alsozeroifV approachesINTV ,sinceI issourced

BAT

CC

TRKL

5. It is important to minimize parasitic capacitance on

the PROG pin. The trace connecting to this pin should

be as short as possible with extra wide spacing from

adjacent copper traces.

from the INTV LDO.

CC

The junction temperature can be estimated using the fol-

lowing formula:

T = T + P • Θ .

J

A

D

JA

6. Keep the GND capacitance of the MPPT pin to a mini-

mum, and reduce coupling from the MPPT pin to any

of the switching pins (SW, BOOST, and CHGSNS) by

routing the MPPT trace away from these signals.

where T is the ambient operating temperature.

A

Maximize the copper area connected to the exposed pad.

Place via connections directly under the exposed pad to

connect a large copper ground plane to the LTC4121 to

improve heat transfer.

Example PCB layout files of the LTC4121 are available at

the following linꢁ:

http://www.linear.com/product/LTC4121#demoboards.

4121fa

22

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

applicaTions exaMples

Design Example 1

The switching frequency of 750ꢁHz is selected to achieve

an on-time of 154ns which is greater than t

at the

MIN(ON)

Consider the design example, shown in ꢀigure 14 on the

last page, for the LTC4121-4.2. Input power is from a

maximum input supply, and minimum battery voltage of

2.5V.

solar panel that has an open-circuit voltage V = 21.6V,

OC

and maximum power voltage V = 17V, or 79% of the

2.5V

750ꢁHz • 21.6V

MP

t_ON

=

= 154.3 > t_MIN(ON)

open-circuit voltage. The battery float voltage is 4.2V, and

the desired charge current is 400mA. The application has

a minimum battery voltage of 2.5V.

Next, the minimum standard inductance value is found

that maintains an inductor ripple current 30% of I , at

CHG

There is no requirement given for the input voltage where

the LTC4121-4.2 should turn on. Given that the MPPT set

the peaꢁ power input voltage of 17V using the following

formula:

point, V , is at 79% of the open-circuit voltage of 21.6V,

MP

(17V − 4.2V)• 4.2V

750ꢁHz •17V •(30% • 400mA)

one may elect to turn-on the LTC4121-4.2 at an input

voltage anywhere below this set point. A level of 60% of

the open-circuit voltage is selected, or 13V. This selection

L_SW

>

= 35µH

The next largest standard inductance value is 47µH. This

inductor selection results in a ripple current of 90mA and

results in a RUN pin divider of R

= 464ꢁΩ, and R

RUN1

RUN2

= 107ꢁΩ. With this RUN pin divider, the LTC4121-4.2 en-

peaꢁ inductor current I

I_L(PEAK)= 400mA+

I_L(PEAK)= 444mA

of:

L(PEAK)

ters DISABLED mode if the input supply drops below 12V.

(17V − 4.2V)• 4.2V

2 • 750ꢁHz •17V • 47µH

Now select the MPPT resistive divider to obtain a maxi-

mum power point of 17V. The maximum power point of

17V is at 79% of the open-circuit voltage. This is used to

calculate the ratio

The saturation current of the switch inductor needs to be

greater than I

V_MP0.1

V_OCK_R

=

.

L(PEAK)

Now select R

for the desired average charge current

PROG

Select

during constant-current operation. The nearest standard

1% resistor to satisfy the following relation:

K = 0.1/0.79 = 0.1266

R

h_PROG•1.227V

This ratio is obtained by selecting R

following:

and R

MPPT2

MPPT1

R_PROG

=

= 3.01ꢁΩ

400mA

(1− 0.1266)

Select C = 10µꢀ for the input decoupling capacitor,

IN

R_MPPT1

=

R_MPPT2= 6.9 •R_MPPT2

achieving an input voltage ripple of 10mV.

0.1266

4.2V

Using standard 1% resistors, select R

= 698ꢁΩ and

MPPT1

400mA •

17V

R

= 100ꢁΩ to obtain a K of 0.1253, and an MPPT

MPPT2

R

∆V =

= 10mV

IN

10µꢀ

set point of 17.24V.

As described in the MPPT Error Terms section, the actual

regulation voltage will vary from the programmed voltage

The minimum standard voltage rating for C is 50V.

IN

Select C

= 2.2µꢀ, and C

= 22nꢀ, and finally the

INTVCC

BST

downto45mV/K =359mVbelowtheprogrammedvoltage.

R

battery capacitor should be 22µꢀ. The lowest standard

voltage rating for these capacitors is 6V.

In this example, the expected regulation voltage is 16.88V

to 17.24V, or 78.2% to 80.1% of the open-circuit voltage.

4121fa

23

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

applicaTions exaMples

In this design example, maximum power dissipation is

calculated during tricꢁle charge as:

This ratio is obtained by selecting R

and R

MPPT1 MPPT2

following:

(1− 0.1245)

P = (17V − 2.5V)•10mA

D

R_MPPT1

=

R_MPPT2= 7.03 •R_MPPT2

0.1245

+ 17V • 2.5mA

+ 0.3Ω • 0.04A²

Using standard 1% resistors, select R

= 715ꢁΩ and

MPPT1

R

= 102ꢁΩ to obtain a K of 0.1248 and nominal

MPPT2

R

4.2V

17V

+ 0.8Ω •

0.04A²

MPPT set point of 17.94V. Including the effect of MPPT

error terms, the expected MPPT regulation voltage will

vary between 17.58V to 17.94V or 78.5% to 80.1% of the

open-circuit voltage.











2.5V

17V

+ 0.5Ω • 1−

• 0.04A²



= 0.19W

Next, the external feedbacꢁ divider, R /R , is found

ꢀB1 ꢀB2

using standard 1% values listed in Table 2.

This dissipated power results in a junction temperature

rise of:

R

ꢀB1

R

ꢀB2

= 2.05MΩ

= 845ꢁΩ

P • Θ = 0.19W • 54C°/W = 10.2°C

D

JA

With these resistors, and including the resistance of the

ꢀBG pin, the battery float voltage is 8.22V.

EstimatingI

at2.5mAfromtheI

IN(SWITCHING)

Current vs Input Voltage graph at V = 17V, during

IN

regular charging with V > V

reduces to:

, the power dissipation

TRKL

BAT

Select the RUN pin divider to turn on the charger when

the solar-cell output reaches 14.7V. This is obtained by

selectingR

=536ꢁΩ, andR

=107ꢁΩ. Thisselec-

RUN1

RUN2

P_D= 17V • 2.5mA

tion turns off the charger if the input falls below 13.52V.

+ 0.3Ω • 0.4A²

Theswitchingfrequencyisselectedat1.5MHzwhichmeets

the minimum on-time requirement for battery voltages

as low as 5V.

4.2V

17V

+ 0.8Ω •

0.4A²











4.2V

17V

+ 0.5Ω • 1−

• 0.4A²

5V



t_ON

=

= 186ns > t_MIN(ON)

1.5MHz •17.94V

= 0.18W

The minimum standard inductance value for a 30% ripple

current is

This dissipated power results in a junction temperature

rise of 9.8°C over ambient.

(17.94V − 8.2V)• 8.2V

L_SW

>

= 24.8µH

1.5MHz •17.94V •(30% • 400mA)

Design Example 2

The nearest standard inductor value greater than this is

33µH. With an inductor of 33µH, the peaꢁ inductor current

Considerthedesignwitha3.5Worgreatersolarpanelwith

a maximum input voltage of V = 22.4V and a maximum

OC

is 445mA and the ripple current amplitude, ∆I , is 90mA.

power voltage of V = 18V or 80.3% of the open-circuit

L

MP

Select an inductor with a saturation current greater than

the peaꢁ inductor current.

voltage. The minimum battery voltage is 5V, and the float

voltage is 8.2V, with a charge current of 400mA.

Select R

= 3.01ꢁ, as the nearest standard 1% value

The MPPT set point is at 80.3% of the open-circuit volt-

age. So select

PROG

to provide a charge current of 403mA during constant-

current operation.

K = 0.1/0.803 = 0.1245

R

4121fa

24

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

applicaTions exaMples

Select a 50V rated capacitor for C = 10µꢀ to achieve an

This dissipated power results in a junction temperature

rise of:

IN

input voltage ripple of 10mV. And select 6V rated capaci-

tors for C

BAT

= 2.2µꢀ, C

= 22nꢀ, and a 10V rated

INTVCC

= 22µꢀ.

BOOST

P • Θ = 0.077W • 54°C/W = 4.2°C

D

JA

C

During regular charging with V = 8.2V, and assuming

BAT

Due to the large float voltage diode D7 is placed in series

with the BAT pin to prevent exceeding the ABS MAX cur-

V is at the MPPT voltage of 17.94V, the power dissipa-

IN

tion increases to:

rent rating on the R

resistor in the event that a fully

SNS

P_D= 18V • 4mA

charged battery may be connected.

+ 0.3Ω • 0.4A²

In this design example, maximum power dissipation is

calculated during tricꢁle charge with the following as-

8.2V

19V

0.4A²

sumptions: V = 5.7V, V is 19V, and I

is

+ 0.8Ω •

BAT

IN

IN(SWITCHING)

CurrentvsInputVoltage

estimatedfromtheI

IN(SWITCHING)











8.2V

19V

graph in the Typical Performance Characteristics section

at V = 19V and ꢀREQ = INTV as 4mA.

+ 0.5Ω • 1−

• 0.4A²



IN

CC

= 0.22W

P_D= 19V • 4mA

+ 0.3Ω • 0.04A²

This dissipated power results in a junction temperature

rise of 12°C over ambient.

5.7V

+ 0.8Ω •

0.04A²

19V











5.7V

19V

+ 0.5Ω • 1−

• 0.04A²



= 77mW

BAT54

V

= 22.4V, V = 18V

MP

INTV

CC

OC

IN

INTV

CC

C

INTVCC

FREQ

C

10µF

IN

2.2µF

R

RUN1

BOOST

C

536k

BST

L

SW

RUN

22nF

33µH

R

RUN2

LTC4121

SW

CHGSNS

BAT

107k

R

+

MPPT1

V

= 8.2V

FLOAT

715k

R

C

FB1

BAT

22µF

MPPT

2.05M

R

MPPT2

FB

470k

102k

R

FB2

IN

CHRG

FAULT

10k

T

845k

FBG

NTC

470k

GND

PROG

R

+

PROG

3.01k

Li-Ion

T = NTHS0805N02N1002F

4121 F09

Figure 9. Design Example 2 with LTC4121

4121fa

25

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

applicaTions exaMples

Design Example 3

disable NTC qualified charging and highlight the float volt-

age programming over a wide temperature range. With an

NTC pin networꢁ connected, as in example 1 or example 4,

the charger would be disabled below 0°C or above 40°C.

Consider the design of a sealed lead acid charger with

temperaturecompensationofthefloatvoltage.SealedLead

Acid batteries require the float voltage be decreased as

cell temperature rises. With the LTC4121 this is achieved

using an NTC thermistor in the feedbacꢁ pin divider as

shown in ꢀigure 10.

The sealed lead acid charger of example 3 is configured

to charge from a variable supply that can range from 6.2V

up to 40V. The switch frequency is selected at 750ꢁHz to

meet minimum on time requirements at V = 4.2V. And

BAT

Using the circuit of ꢀigure 10 above, the float voltage

automatically decreases with temperature as shown in

ꢀigure 11. The NTC pin is grounded in this example to

a 47µH switch inductor is selected to ꢁeep ripple current

below 30% of I

at V = 40V.

CHG

IN

INTV

CC

IN

INTV

CC

C

INTVCC

BOOST

C

IN

C

2.2µF

L

BST

SW

10µF

22nF

47µH

RUN

SW

CHGSNS

BAT

V

= 6V

FLOAT

LTC4121

C

R

BAT

FB1A

R

MPPT1

22µF

102k

10k

R

C

FB1C

FF

+

MPPT

V

IN

866k

1nF

–

R

+

FB1B

R

T1

SLA

464k

100k

NTC

FB

R

FB2

FREQ

698k

FBG

GND

PROG

R

PROG

3.01k

R

T1

= NTHS0402E3104FHT

4121 F10

Figure 10. Design Example 3, SLA Charging with LTC4121

7.0

NTC = GND

6.8

6.6

6.4

6.2

6.0

5.8

5.6

5.4

5.2

5.0

–40 –25 –10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

4121 F11

Figure 11. Sealed Lead Acid Float Voltage

4121fa

26

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

applicaTions exaMples

Design Example 4

V

= 4.2V. And above 28.3V, the charger attains the full

BAT

programmed charge current of 400mA so MPPT regula-

Consider the design of a Li-Ion charger from a resistive

supply. With a resistive supply voltage, the maximum

powerpointisat50%oftheopen-circuitvoltage.Program

tion lets go. While the LTC4121 regulates V , the battery

IN

charge current is automatically scaled to tracꢁ available

input power. ꢀigure 13 illustrates the circuit performance

a 50% peaꢁ power point using K = 0.199 with R

=

R

MPPT1

measured with V

held at 4.0V, showing the ratio of

BAT OC IN

BAT

332ꢁ and R

= 82.5ꢁ. This networꢁ ꢁeeps the input

MPPT2

V

/V and I

versus V with R = 100Ω in series

MP OC

voltage at the peaꢁ power point for any input resistance

so long as the R-C time constant of R • C does not

with the supply.

L is sized to maintain ripple current below 30% of I

SW

IN

exceed PW /5, here C is 22µꢀ.

MP

IN

CHG

at V = 16V. The ꢀB pin networꢁ is programmed to set

V

IN

With 100Ω of source impedance, the input voltage regu-

= 4.2V. An NTC networꢁ is configured to enable

ꢀLOAT

lation loop holds the ratio of (V /V ) at about 49% for

MP IN

charging when the battery temperature is between 0°C

and 40°C.

V ranging from 9V up to 28.3V. ꢀor lower input voltages

IN

than 8.7V, the MPPT set point is below DUVLO when

V

INTV

CC

MP

IN

INTV

CC

C

INTVCC

BOOST

C

IN

C

2.2µF

L

BST

SW

22µF

22nF

33µH

RUN

SW

CHGSNS

BAT

V

= 4.2V

FLOAT

LTC4121

C

BAT

R

FB1

22µF

R

MPPT1

1.01M

332k

MPPT

FB

R

IN

R

FB2

R

MPPT2

10k

1.35M

82.5k

FBG

NTC

+

V

IN

–

FREQ

GND

PROG

Li-Ion

+

T

R

PROG

3.01k

T = NTCS0402E3103FHT

4121 F12

Figure 12. Design Example 4, LTC4121 2-Cell Li-Ion Charger with MPPT Tracking for a Resistive Supply

100

90

80

70

60

50

40

30

20

10

450

400

350

300

250

200

150

100

50

V

R

= 4V

BAT

IN

= 100Ω

0

5

10

15

20

25

30

35

40

V

(V)

IN(OC)

4121 F13

Figure 13. V_MP/V_OCand I_BATvs V_IN(OC)

4121fa

27

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UD Package

16-Lead Plastic QFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1691 Rev Ø)

0.70 ±0.05

3.50 ±0.05

2.10 ±0.05

1.45 ±0.05

(4 SIDES)

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.20 TYP

OR 0.25 × 45° CHAMFER

R = 0.115

TYP

0.75 ±0.05

3.00 ±0.10

(4 SIDES)

15 16

PIN 1

TOP MARK

(NOTE 6)

0.40 ±0.10

1

2

1.45 ± 0.10

(4-SIDES)

(UD16) QFN 0904

0.200 REF

0.25 ±0.05

0.00 – 0.05

0.50 BSC

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

4121fa

28

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

05/15 Clarified device options

Clarified Note 4

1

5

Modified End-of-Charge Indication section

15

Enhanced Reverse Blocꢁing section

Modified Related Parts list

20-21

28

4121fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation maꢁes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

29

For more information www.linear.com/LTC4121

LTC4121/LTC4121-4.2

Typical applicaTion

470k

V

= 21.6V, V = 17V

MP

OC

INTV

CC

CHRG

FAULT

IN

INTV

CC

C

INTVCC

2.2µF

C

IN

R

RUN1

10µF

464k

BOOST

C

BST

L

SW

22nF

RUN

47µH

LTC4121-4.2

SW

CHGSNS

BAT

R

RUN2

+

107k

V

= 4.2V

FLOAT

R

MPPT1

698k

C

BAT

22µF

BATSNS

10k

T

MPPT

R

MPPT1

100k

NTC

GND PROG

R

FREQ

+

PROG

3.01k

Li-Ion

T = NTHS0805N02N1002F

4121 TA02

Figure 14. Design Example 1 with LTC4121-4.2

relaTeD parTs

PART NUMBER DESCRIPTION

COMMENTS

LT^®3650-8.2/

LT3650-8.4

Monolithic 2A Switch Mode

Non-Synchronous 2-Cell Li-Ion

Battery Charger

Standalone 9V < V < 32V (40V Absolute Maximum), 1MHz, 2A Programmable Charge Current,

IN

Timer or C/10 Termination, Small and ꢀew External Components 3mm × 3mm DꢀN-12 Pacꢁage

“-8.2” for 2 × 4.1V ꢀloat Voltage Batteries, “-8.4” for 2 × 4.2V ꢀloat Voltage Batteries.

LT3650-4.1/

LT3650-4.2

Monolithic 2A Switch Mode

Non-Synchronous 1-Cell Li-Ion

Battery Charger

Standalone 4.75V < V < 32V (40V Absolute Maximum), 1MHz, 2A Programmable Charge

IN

Current, Timer or C/10 Termination, Small and ꢀew External Components 3mm × 3mm DꢀN-12

Pacꢁage “-4.1” for 4.1V ꢀloat Voltage Batteries, “-4.2” for 4.2V ꢀloat Voltage Batteries.

LT3652HV

LTC4070

Power Tracꢁing 2A Battery Charger Input Supply Voltage Regulation Loop for Peaꢁ Power Tracꢁing in (MPPT) Solar Applications,

4.95V < V < 34V (40V Absolute Maximum), 1MHz, 2A Charge Current, 3.3V < V < 18V.

IN

OUT

Timer or C/10 Termination, 3mm × 3mm DꢀN-12 Pacꢁage and MSOP-12 Pacꢁages.

Li-Ion/Polymer Shunt Battery

Charger System

Low Operating Current (450nA), 1% ꢀloat Voltage Accuracy Over ꢀull Temperature and Shunt

Current Range, 50mA Maximum Internal Shunt Current (500mA with External PꢀET), Pin

Selectable ꢀloat Voltages: 4.0V, 4.1V, 4.2V. Ultralow Power Pulsed NTC ꢀloat Conditioning for

Li-Ion/Polymer Protection, 8-Lead (2mm × 3mm) DꢀN & MSOP.

LTC4071

Li-Ion/Polymer Shunt Battery

Charger System with Low Battery

Disconnect

Integrated Pacꢁ Protection, < 10nA Low Battery Disconnect Protects Battery from

Over-Discharge. Low Operating Current (550nA), 1% ꢀloat Voltage Accuracy Over ꢀull

Temperature and Shunt Current Range, 50mA Maximum Internal Shunt Current, Pin Selectable

ꢀloat Voltages: 4.0V, 4.1V, 4.2V. Ultralow Power Pulsed NTC ꢀloat Conditioning for Li-Ion/

Polymer Protection, 8-Lead (2mm × 3mm) DꢀN and MSOP.

LTC4065/

LTC4065A

Standalone Li-Ion Battery Charger

in 2mm × 2mm DꢀN

4.2V 0.6% ꢀloat Voltage, Up to 750mA Charge Current; “A” Version Has /ACPR ꢀunction.

2mm × 2mm DꢀN Pacꢁage.

LTC4079

60V 250mA Multi-Chemistry Linear 2.7V – 60V Input Voltage range, 1.2V – 60V Adjustable Battery Voltage Range and 10mA

Battery Charger

– 250mA Charge Current Range. Low 4µA Quiescent Current. Input Voltage and Thermal

Regulation. 10-pin 3mm x 3mm DꢀN pacꢁage.

4121fa

LT 0515 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

30

For more information www.linear.com/LTC4121

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC4121

●

 LINEAR TECHNOLOGY CORPORATION 2014


型号：	LTC4121-4.2_15
厂家：	Linear
描述：	40V 400mA Synchronous Step-Down Battery Charger 电池
文件：	总30页 (文件大小：350K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC4121-4.2_15 [Linear]

相关型号：

LTC4121EUD

LTC4121EUD-4.2

LTC4121_15

LTC4123

LTC4124

LTC4125EUFD

LTC4126

LTC4126-10

LTC4126-ADJ

LTC4150

LTC4150CMS

LTC4150CMS#PBF