LTC4150IMS [Linear]
Coulomb Counter/ Battery Gas Gauge; 库仑计/电池电量监测计
| 型号： | LTC4150IMS |
| 厂家： | 
Linear |
| 描述： | Coulomb Counter/ Battery Gas Gauge |
| 文件： | 总12页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4150
Coulomb Counter/
Battery Gas Gauge
U
DESCRIPTIO
FEATURES
TheLTC®4150measuresbatterydepletionandchargingin
handheld PC and portable product applications. The de-
vice monitors current through an external sense resistor
between the battery’s positive terminal and the battery’s
load or charger. A voltage-to-frequency converter trans-
forms the current sense voltage into a series of output
pulses at the interrupt pin. These pulses correspond to a
fixed quantity of charge flowing into or out of the battery.
The part also indicates charge polarity as the battery is
depleted or charged.
■
Indicates Charge Quantity and Polarity
■
±50mV Sense Voltage Range
■
Precision Timer Capacitor or Crystal Not Required
■
2.7V to 8.5V Operation
High Side Sense
32.55Hz/V Charge Count Frequency
1.5µA Shutdown Current
10-Pin MSOP Package
■
■
■
■
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APPLICATIO S
The LTC4150 is intended for 1-cell or 2-cell Li-Ion and
3-cell to 6-cell NiCd or NiMH applications.
■
Battery Chargers
Palmtop Computers and PDAs
Cellular Telephones and Wireless Modems
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
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TYPICAL APPLICATIO
Integral Nonlinearity, % of Full Scale
0.5
CHARGER
R
SENSE
LOAD
+
0.4
4.7µF
0.3
R
R
L
0.2
L
–
+
SENSE SENSE
V
DD
INT
0.1
+
C
C
F
0
4.7µF
CLR
POL
LTC4150
GND
µP
CHG
–
DISCHG
F
–0.1
–0.2
–0.3
–0.4
–0.5
SHDN
4150 TA01a
–50
–25
0
25
50
CURRENT SENSE VOLTAGE (mV)
4150 TA01b
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LTC4150
W W U W
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ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
TOP VIEW
Supply Voltage (VDD)...................................–0.3V to 9V
Input Voltage Range
NUMBER
+
SENSE
SENSE
1
2
3
4
5
10 INT
–
+
–
9
8
7
6
CLR
C
V
GND
POL
LTC4150CMS
LTC4150IMS
F
F
DD
Digital Inputs (CLR, SHDN) ....... –0.3V to (VDD + 0.3)
C
–
+
SENSE–, SENSE+ , CF , CF ........ –0.3V to (VDD + 0.3)
SHDN
MS PACKAGE
10-LEAD PLASTIC MSOP
Output Voltage Range
Digital Outputs (INT, POL).......................–0.3V to 9V
Operating Temperature Range
MS PART MARKING
LTQW
TJMAX = 125°C, θJA = 160°C/W
LTC4150CMS .......................................... 0°C to 70°C
LTC4150IMS ..................................... –40°C TO 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 2.7V and 8.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
Digital Input Low Voltage, CLR, SHDN
Digital Input High Voltage, CLR, SHDN
Digital Output Low Voltage, INT, POL
Digital Output Leakage Current, INT, POL
Differential Offset Voltage (Note 4)
●
●
●
●
0.7
V
V
IL
1.9
IH
I
= 1.6mA, V = 2.7V
0.5
1
V
OL
OL
DD
I
V
V
= V = 8.5V
POL
0.01
µA
LEAK
INT
DD
V
= 4.0V
±100
±150
µV
µV
OS
●
●
V
V
= 8.0V
±100
±150
µV
µV
DD
DD
= 2.7V to 8.5V
±150
±200
µV
µV
●
●
●
V
V
Sense Voltage Common Mode Input Range
Sense Voltage Differential Input Range
Average Differential Input Resistance,
V
– 0.06
V + 0.06
DD
V
V
SENSE(CM)
SENSE
DD
+
–
SENSE – SENSE
–0.05
155
0.05
390
R
V
= 4.1V (Note 3)
270
2.5
kΩ
IDR
DD
+
–
Across SENSE and SENSE
V
Undervoltage Lockout Threshold
V
Rising
●
2.7
V
UVLO
DD
Power Supply Current
I
Supply Current, Operating
V
V
= 8.5V
= 2.7V
●
●
115
80
140
100
µA
µA
DD
DD
DD
I
Supply Current, Shutdown
V
V
= 8.5V
= 2.7V
●
●
10
1.5
µA
µA
DD(SD)
DD
DD
AC Characteristics
G
VF
Voltage to Frequency Gain
V
= 50mV to –50mV,
DD
32.0
31.8
32.55
33.1
33.3
Hz/V
Hz/V
SENSE
2.7V ≤ V ≤ 8.5V
●
∆G (V
)
Gain Variation with Supply
2.7V ≤ V ≤ 8.5V
0
0.5
%/V
VF DD
DD
∆G (TEMP) Gain Variation with Temperature
(Note 2)
●
●
–0.03
0.03
%/ ºC
VF
INL
Integral Nonlinearity
–0.4
–0.5
0.4
0.5
%
%
t
t
CLR Pulse Width to Reset INT,
INT and CLR Not Connected
Figure 2
20
µs
CLR
INT
INT Low Time, INT Connected to CLR
Figure 3, C = 15pF
●
1
µs
L
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LTC4150
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
Note 3: Measured at least 20ms after power on.
Note 4: Tested in feedback loop to SENSE and SENSE .
+
–
of a device may be impaired.
Note 2: Guaranteed by design and not tested in production.
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TYPICAL PERFOR A CE CHARACTERISTICS (Specifications are at TA = 25°C, unless
otherwise noted.)
Voltage to Frequency Gain
vs Supply Voltage
Voltage to Frequency Gain
vs Temperature
Operating IDD vs VDD
+1.00
+0.75
+0.50
+0.25
0
+1.00
+0.75
+0.50
+0.25
0
140
120
100
80
V
= 50mV
SENSE
V
= 2.7V
DD
V
= 25mV
SENSE
V
= 8.5V
DD
V
= 50mV
SENSE
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
60
2
3
4
5
6
7
8
9
-50 -25
0
25
50
75 100 125
2
3
4
5
6
7
8
9
10
V
(V)
TEMPERATURE (°C)
V
(V)
DD
DD
4150 G01
4150 G02
4150 G03
Undervoltage Lockout Threshold
vs Temperature
Shutdown IDD vs VDD
Digital Output Low Voltage vs VDD
6
5
4
3
2
1
0
400
350
300
250
200
150
100
50
2.60
2.59
2.58
2.57
2.56
2.55
2.54
2.53
2.52
I
= 1.6mA
RISING EDGE
OL
POL PIN
INT PIN
0
2
3
4
5
6
7
8
9
10
2
3
4
5
6
7
8
9
-50 -25
0
25
50
75 100 125
V
(V)
V
DD
(V)
TEMPERATURE (°C)
DD
4150 G04
4150 G05
4150 G06
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LTC4150
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PI FU CTIO S
SENSE+ (Pin1): Positive Sense Input. This is the
noninverting current sense input. Connect SENSE+ to the
load and charger side of the sense resistor. Full-scale
current sense input is 50mV. SENSE+ must be within
60mV of VDD for proper operation.
SENSE– (Pin2):NegativeSenseInput.Thisistheinverting
current sense input. Connect SENSE– to the positive
battery terminal side of the sense resistor. Full-scale
current sense input is 50mV. SENSE– must be within
60mV of VDD for proper operation.
POL (Pin 6): Battery Current Polarity Open-Drain Output.
POL indicates the most recent battery current polarity
when INT is high. A low state indicates the current is
flowingoutofthebatterywhilehighimpedancemeansthe
currentisgoingintothebattery.POLlatchesitsstatewhen
INT is asserted low. POL is an open-drain output and can
be pulled up to any logic supply up to 9V. In shutdown,
POL is high impedance.
GND (Pin 7): Ground. Connect directly to the negative
battery terminal.
+
CF (Pin 3): Filter Capacitor Positive Input. A capacitor
VDD (Pin 8): Positive Power Supply. Connect to the load
+
–
connected between CF and CF filters and averages noise
and charger side of the sense resistor. SENSE+ also
connects to VDD. VDD operating range is 2.7V to 8.5V.
Bypass VDD with 4.7µF capacitor.
andfastbatterycurrentvariations. A4.7µFvalueisrecom-
+
–
mended. If filtering is not desired, leave CF and CF
unconnected.
CLR (Pin 9): Clear Interrupt Digital Input. When asserted
low for more than 20µs, CLR resets INT high. Charge
counting is unaffected. INT may be directly connected to
CLR. In this case the LTC4150 will capture each assertion
ofINTandwaitatleast1µsbeforeresettingit.Thisensures
thatINTpulseslowforatleast1µsbutgivesautomaticINT
reset. In applications with a logic supply VCC > VDD, a
resistive divider must be used between INT and CLR. See
the Applications Information section.
–
CF (Pin 4): Filter Capacitor Negative Input. A capacitor
+
–
connected between CF and CF filters and averages noise
andfastbatterycurrentvariations. A4.7µFvalueisrecom-
+
–
mended. If filtering is not desired, leave CF and CF
unconnected.
SHDN (Pin 5): Shutdown Digital Input. When asserted
low, SHDN forces the LTC4150 into its low current con-
sumption power-down mode and resets the part. In appli-
cations with logic supply VCC > VDD, a resistive divider
must be used between SHDN and the logic which drives it.
See the Applications Information section.
INT (Pin 10): Charge Count Interrupt Open-Drain Output.
INT latches low every 1/(VSENSE • GVF) seconds and is
reset by a low pulse at CLR. INT is an open-drain output
and can be pulled up to any logic supply of up to 9V. In
shutdown INT is high impedance.
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LTC4150
W
BLOCK DIAGRA
CHARGER
LOAD
REFHI
1.7V
V
DD
INT
S3
+
–
OFLOW/
UFLOW
S
R
Q
100pF
+
SENSE
S1
2k
2k
COUNTER
UP/DN
200k
CLR
–
+
200k
C
F
CONTROL
LOGIC
AMPLIFIER
CHARGE
POL
R
SENSE
C
F
+
POLARITY
DETECTION
+
–
–
–
C
F
DISCHARGE
200k
S2
I
BAT
SENSE
GND
REFLO
0.95V
SHDN
4150 F01
Figure 1. Block Diagram
W U
W
TI I G DIAGRA S
50% 50%
CLR
INT
t
CLR
50% 50%
INT
t
INT
4150 F02
4150 F03
Figure 2. CLR Pulse Width to Reset INT,
CLR and INT Not Connected
Figure 3. INT Minimum Pulse Width, CLR and INT Connected
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LTC4150
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OPERATIO
Charge is the time integral of current. The LTC4150
measuresbatterycurrentbymonitoringthevoltagedevel-
oped across a sense resistor and then integrates this
information in several stages to infer charge. The Block
Diagram shows the stages described below. As each unit
of charge passes into or out of the battery, the LTC4150
INT pin interrupts an external microcontroller and the POL
pin reports the polarity of the charge unit. The external
microcontroller then resets INT with the CLR input in
preparation for the next interrupt issued by the LTC4150.
The value of each charge unit is determined by the sense
resistor value and the sense voltage to interupt frequency
gain GVF of the LTC4150.
CHARGE COUNTING
First, the current measurement is filtered by capacitor CF
+
–
connected across pins CF and CF . This averages fast
changes in current arising from ripple, noise and spikes in
the load or charging current.
Second, the filter’s output is applied to an integrator with
the amplifier and 100pF capacitor at its core. When the
integratoroutputrampstoREFHIorREFLOlevels,switches
S1 and S2 reverse the ramp direction. By observing the
condition of S1 and S2 and the ramp direction, polarity is
determined. The integrating interval is trimmed to 600µs
at 50mV full-scale sense voltage.
Third,acounterisincrementedordecrementedeverytime
the integrator changes ramp direction. The counter effec-
tively increases integration time by a factor of 1024,
greatly reducing microcontroller overhead required to
service interrupts from the LTC4150.
Power-On and Start-Up Initialization
When power is first applied to the LTC4150, all internal
circuitryisreset.Afteraninitializationinterval,theLTC4150
begins counting charge. This interval depends on VDD and
the voltage across the sense resistor but will be at least
5ms. It may take an additional 80ms for the LTC4150 to
accurately track the sense voltage. An internal undervolt-
age lockout circuit monitors VDD and resets all circuitry
when VDD falls below 2.5V.
At each counter under or overflow, the INT output latches
low, flagging a microcontroller. Simultaneously, the POL
output is latched to indicate the polarity of the observed
charge. With this information, the microcontroller can
total the charge over long periods of time, developing an
accurate estimate of the battery’s condition. Once the
interrupt is recognized, the microcontroller resets INT
with a low going pulse on CLR and awaits the next
interrupt. Alternatively, INT can drive CLR.
Asserting SHDN low also resets the LTC4150’s internal
circuitry and reduces the supply current to 1.5µA. In this
condition, POL and INT outputs are high impedance. The
LTC4150 resumes counting after another initialization
interval. Shutdown minimizes battery drain when both the
charger and load are off.
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LTC4150
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APPLICATIO S I FOR ATIO
SENSE VOLTAGE INPUT AND FILTERS
Coulomb Counting
Since the overall integration time is set by internally
trimming the LTC4150, no external timing capacitor or
trimming is necessary. The only external component that
affects the transfer function of interrupts per coulomb of
charge is the sense resistor, RSENSE. The common mode
rangefortheSENSE+ andSENSE– pinsisVDD ±60mV,with
a maximum differential voltage range of ±50mV. SENSE+
isnormallytiedtoVDD, sothereisnocommonmodeissue
when SENSE– operates within the 50mV differential limit
relative to SENSE+.
The LTC4150’s transfer function is quantified as a voltage
to frequency gain GVF, where output frequency is the
number of interrupts per second and input voltage is the
differential drive VSENSE across SENSE+ and SENSE–. The
number of interrupts per second will be:
f = GVF • ⏐VSENSE
where
VSENSE = IBATTERY • RSENSE
Therefore,
f = GVF • ⏐IBATTERY • RSENSE
⏐
(2)
(3)
(4)
ChooseRSENSE toprovide50mVdropatmaximumcharge
ordischargecurrent,whicheverisgreater.CalculateRSENSE
from:
⏐
Since I • t = Q, coulombs of battery charge per INT pulse
can be derived from Equation 4:
50mV
IMAX
(1)
RSENSE
=
1
(5)
One INT =
Coulombs
GVF •RSENSE
Batterycapacityismostoftenexpressedinampere-hours.
The sense input range is small (±50mV) to minimize the
loss across RSENSE. To preserve accuracy, use Kelvin
connections at RSENSE
.
1Ah = 3600 Coulombs
(6)
(7)
(8)
The external filter capacitor CF operates against a total on-
chip resistance of 4k to form a lowpass filter that averages
battery current and improves accuracy in the presence of
noise, spikes and ripple. 4.7µF is recommended for gen-
eral applications but can be extended to higher values as
long as the capacitor’s leakage is low. A 10nA leakage is
roughly equivalent to the input offset error of the integra-
tor. Ceramic capacitors are suitable for this use.
Combining Equations 5 and 6:
1
One INT =
[Ah]
3600 •GVF •RSENSE
or
1Ah = 3600 • GVF • RSENSE Interrupts
The charge measurement may be further scaled within the
microcontroller. However, the number of interrupts, cou-
lombs or Ah all represent battery charge.
Switching regulators are a particular concern because
they generate high levels of current ripple which may flow
through the battery. The VDD and SENSE+ connection to
the charger and load should be bypassed by at least 4.7µF
at the LTC4150 if a switching regulator is present.
The LTC4150’s transfer function is set only by the value of
the sense resistor and the gain GVF. Once RSENSE is
selected using Equation 1, the charge per interrupt can be
determined from Equation 5 or 7.
The LTC4150 maintains high accuracy even when Burst
Mode® switching regulators are used. Burst pulse “on”
levels must be within the specified differential input volt-
Note that RSENSE is not chosen to set the relationship
between ampere-hours of battery charge and number of
interrupts issued by the LTC4150. Rather, RSENSE is
chosen to keep the maximum sense voltage equal to or
less than the LTC4150’s 50mV full-scale sense input.
+
–
age range of 50mV as measured at CF and CF . To retain
accurate charge information, the LTC4150 must remain
enabled during Burst Mode operation. If the LTC4150
shuts down or VDD drops below 2.5V, the part resets and
charge information is lost.
Burst Mode is registered trademark of Linear Technology Corporation.
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LTC4150
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APPLICATIO S I FOR ATIO
INT, POL and CLR
Interfacing to INT, POL, CLR and SHDN
INT asserts low each time the LTC4150 measures a unit of
charge. At the same time, POL is latched to indicate the
polarity of the charge unit. The integrator and counter
continuerunning, sothemicrocontrollermustserviceand
clear the interrupt before another unit of charge accumu-
lates. Otherwise, one measurement will be lost. The time
available between interrupts is the reciprocal of
Equation 2:
The LTC4150 operates directly from the battery, while in
most cases the microcontroller supply comes from some
separate, regulatedsource. ThisposesnoproblemforINT
and POL because they are open-drain outputs and can be
pulled up to any voltage 9V or less, regardless of the
voltage applied to the LTC4150’s VDD.
CLR and SHDN inputs require special attention. To drive
them, the microcontroller or external logic must generate
a minimum logic high level of 1.9V. The maximum input
level for these pins is VDD + 0.3V. If the microcontroller’s
supply is more than this, resistive dividers must be used
on CLR and SHDN. The schematic in Figure 6 shows an
application with INT driving CLR and microcontroller VCC
> VDD. The resistive dividers on CLR and SHDN keep the
voltages at these pins within the LTC4150’s VDD range.
Choose R2 and R1 so that:
1
Time per INT Assertion =
(9)
GVF •⏐VSENSE
⏐
At 50mV full scale, the minimum time available is 596ms.
To be conservative and accommodate for small, unex-
pectedexcursionsabovethe50mVsensevoltagelimit,the
microcontroller should process the interrupt and polarity
information and clear INT within 500ms.
(R1 + R2) ≥ 50RL
(12)
Toggling CLR low for at least 20µs resets INT high and
unlatchesPOL.SincetheLTC4150’sintegratorandcounter
operate independently of the INT and POL latches, no
charge information is lost during the latched period or
whileCLRislow.Charge/dischargeinformationcontinues
to accumulate during those intervals and accuracy is
unaffected.
R1
R1+R2
(13)
1.9V ≤
VCC ≤ VDD (Minimum)
Equation13alsoappliestotheselectionofR3andR4. The
minimum VDD is the lowest supply to the LTC4150 when
the battery powering it is at its lowest discharged voltage.
Once cleared, INT idles in a high state and POL indicates
real-time polarity of the battery current. POL high indi-
cates charge flowing into the battery and low indicates
charge flowing out. Indication of a polarity change re-
quires at least:
When the battery is removed in any application, the CLR
and SHDN inputs are unpredictable. INT and POL outputs
may be erratic and should be ignored until after the battery
is replaced.
If desired, the simple logic of Figure 4 may be used to
derive separate charge and discharge pulse trains from
INT and POL.
2
tPOL
=
(10)
GVF •1024 •⏐VSENSE
⏐
where VSENSE is the smallest sense voltage magnitude
before and after the polarity change.
CHARGE
INT
CLR
Open-drain outputs POL and INT can sink IOL = 1.6mA at
LTC4150
V
OL =0.5V.Theminimumpull-upresistanceforthesepins
DISCHARGE
should be:
POL
4150 F04
RL > (VCC – 0.5) / 1.6mA
(11)
Figure 4. Unravelling Polarity—
Separate Charge and Discharge Outputs
where VCC is the logic supply voltage. Because speed isn’t
an issue, pull-up resistors of 10k or higher are adequate.
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LTC4150
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APPLICATIO S I FOR ATIO
AUTOMATIC CHARGE COUNT INTERRUPT AND CLEAR
the battery VDD, use Figure 6. The resistor dividers on CLR
and SHDN keep the voltages at these pins within the
LTC4150’s VDD range. Choose an RL value using Equation
11 and R1-R4 values using Equation 13. In either applica-
tion,theLTC4150willcapturethefirstassertionofINTand
wait at least 1µs before resetting it. This insures that INT
pulses low for at least 1µs but gives automatic INT reset.
In applications where a CLR pulse is unavailable, it’s easy
to make the LTC4150 run autonomously, as shown in
Figures 5 and 6. If the microcontroller VCC is less than or
equal to the battery VDD, INT may be directly connected to
CLR, as in Figure 5. The only requirement is that the
microcontrollershouldbeabletoprovideahighlogiclevel
of 1.9V to SHDN. If the microcontroller VCC is greater than
POWER-DOWN
SWITCH
LOAD
C
L
PROCESSOR
47µF
V
CC
R
L
R
L
1
10
9
+
SENSE
INT
LTC4150
R
CLR
SENSE
8
2
3
–
V
DD
SENSE
C2
4.7µF
+
2.7V TO 8.5V
BATTERY
+
7
6
C
F
GND
µP
C
F
4.7µF
4
5
–
C
F
SHDN
POL
4150 F05
Figure 5. Application with INT Direct Drive of CLR and Separate Microprocessor Supply VCC ≤ VDD
POWER-DOWN
SWITCH
LOAD
C
L
PROCESSOR
47µF
V
CC
R
L
R
L
1
10
9
+
SENSE
INT
LTC4150
R
CLR
SENSE
R2
R1
8
2
3
–
V
DD
SENSE
C2
4.7µF
+
+
7
6
C
F
BATTERY
< V
GND
µP
V
C
BATTERY
CC
F
4.7µF
4
5
–
C
F
SHDN
POL
SHUTDOWN
R4
R3
4150 F06
Figure 6. Application with INT Driving CLR and Separate Microprocessor Supply VCC > VDD
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LTC4150
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APPLICATIO S I FOR ATIO
TO CHARGER
PC BOARD LAYOUT SUGGESTIONS
Keep all traces as short as possible to minimize noise and
inaccuracy. The supply bypass capacitor C2 should be
placed close to the LTC4150. The 4.7µF filter capacitor CF
should be placed close the CF and CF pins and should be
a low leakage, unpolarized type. Use a 4-wire Kelvin sense
connection for the sense resistor, locating it close to the
LTC4150 with short sense traces to the SENSE+ and
SENSE– pins and longer force lines to the battery pack and
powered load, see Figure 7.
PIN 1
R
SENSE
LTC4150
+
–
4150 F07
TO BATTERY
Figure 7. Kelvin Connection on SENSE Resistor
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TYPICAL APPLICATIO S
Figure 8 shows a typical application designed for a single
cell lithium-ion battery and 500mA maximum load current.
Use Equation 1 to calculate RSENSE = 0.05V / 0.5A = 0.1Ω.
With a microcontroller supply = 5V, Equation 11 gives
RL > 2.875k. The nearest standard value is 3k.
From Equation 12, RL = 3k gives R1 + R2 equal to 150.5k.
A single cell lithium-ion battery can discharge as low as
2.7V.
With RSENSE = 0.1Ω, Equation 7 shows that each interrupt
corresponds to 0.085mAh. Equation 14, derived from
Equation2,givesthenumberofINTassertionsforaverage
battery current, IBATT, over a time, t, in seconds:
From Equation 13, select R1 = 75k; the nearest standard
value for R2 is 76.8k.
INT Assertions = GVF • IBATT • RSENSE • t
(14)
Also from Equation 13, we choose R3 = 75k and R4 =
76.8k.
Loading the battery so that 51.5mA is drawn from it over
600secondsresultsin100INTassertions.Foran800mAh
battery, this is (51.5mA • 1/6h) / 800mAh = 11% of the
battery’s capacity.
POWER-DOWN
SWITCH
LOAD
C
L
5.0V
47µF
R
R
L
3k
L
3k
1
10
9
+
SENSE
INT
R
SENSE
0.1Ω
R2
76.8k
LTC4150
CLR
8
2
3
–
V
DD
SENSE
C2
4.7µF
SINGLE-CELL
Li-Ion
3.0V ~ 4.2V
+
7
6
+
C
F
R1
75k
GND
µP
C
F
4.7µF
4
5
–
C
F
SHDN
POL
SHUTDOWN
R4
76.8k
R3
75k
4150 F08
Figure 8. Typical Application, Single Cell Lithium-Ion Battery
4150fa
10
LTC4150
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
REF
0.50
0.305 ± 0.038
(.0120 ± .0015)
TYP
(.0197)
10 9
8
7 6
BSC
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4 5
0.53 ± 0.152
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.127 ± 0.076
(.005 ± .003)
MSOP (MS) 0603
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
4150fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LTC4150
U
TYPICAL APPLICATIO S
CHARGER
LOAD
+
SENSE
INT
CD40110B
CD40110B
CD40110B
CD40110B
CD40110B
LTC4150
CLR
1.2Ω
1.1Ω
100mΩ
–
SENSE
+
SENSE RESISTANCE = 0.0852Ω
= 588mA
I
MAX
10,000 PULSES = 1Ah
4150 F09
Figure 9. Ampere-Hour Gauge
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1732
Lithium-Ion Linear Battery Charger Controller
Simple Charger uses External FET, Features Preset Voltages, C/10
Charger Detection and Programmable Timer, Input Power Good Indication
LTC1733
LTC1734
LTC1734L
LTC1998
LTC4006
Monolithic Lithium-Ion Linear Battery Charger
Lithium-Ion Linear Battery Charger in ThinSOTTM
Lithium-Ion Linear Battery Charger in ThinSOT
Lithium-Ion Low Battery Detector
Standalone Charger with Programmable Timer, Up to 1.5A Charge Current
Simple ThinSOT Charger, No Blocking Diode, No Sense Resistor Needed
Low Current Version of LTC1734
1% Accurate 2.5µA Quiescent Current, SOT-23
Small, High Efficiency, Fixed Voltage,
Lithium-Ion Battery Charger
Constant-Current/Constant Voltage Switching Regulator with Termination
Timer, AC Adapter Current Limit and Thermistor Sensor in a Small
16-Pin Package
LTC4050
Lithium-Ion Linear Battery Charger Controller
Simple Charger uses External FET, Features Preset Voltages, C/10
Charger Detection and Programmable Timer, Input Power Good Indication,
Thermistor Interface
LTC4052
LTC4053
LTC4054
Monolithic Lithium-Ion Battery Pulse Charger
No Blocking Diode or External Power FET Required, Safety Current Limit
USB Compatible Monolithic Lithium-Ion Battery Charger Standalone Charger with Programmable Timer, Up to 1.25A Charge Current
800mA Standalone Linear Lithium-Ion Battery Charger No External MOSFET, Sense Resistor or Blocking Diode Required, Charge
with Thermal Regulation in ThinSOT
USB Power Manager
Current Monitor for Gas Gauging, C/10 Charge Termination
LTC4410
LTC4412
For Simultaneous Operation of USB Peripheral and Battery Charging from
USB Port, Keeps Current Drawn from USB Port Constant, Keeps Battery
Fresh, Use with the LTC4053, LTC1733, LTC4054
PowerPath™ Controller in ThinSOT
More Efficient Diode OR’ing, Automatic Switching Between DC Sources,
Simplified Load Sharing, 3V ≤ VIN ≤ 28V
ThinSOT and PowerPath are trademarks of Linear Technology Corporation.
4150fa
LT/TP 1004 1K REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2003
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