LTC4251IS6#TRPBF [Linear]
LTC4251 - Negative Voltage Hot Swap Controllers in SOT-23; Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C;
| 型号： | LTC4251IS6#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC4251 - Negative Voltage Hot Swap Controllers in SOT-23; Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C 光电二极管 控制器 |
| 文件： | 总20页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4251/LTC4251-1/
LTC4251-2
Negative Voltage
Hot Swap Controllers in SOT-23
U
DESCRIPTIO
FEATURES
The LTC®4251/LTC4251-1/LTC4251-2 negative voltage
Hot SwapTM controllers allow a board to be safely inserted
and removed from a live backplane. Output current is
controlled by three stages of current limiting: a timed
circuitbreaker,activecurrentlimitingandafastfeedforward
paththatlimitspeakcurrentunderworst-casecatastrophic
fault conditions.
■
Allows Safe Board Insertion and Removal from a
Live –48V Backplane
■
Floating Topology Permits Very High Voltage
Operation
■
Programmable Analog Current Limit with Circuit
Breaker Timer
■
Fast Response Time Limits Peak Fault Current
■
Programmable Timer
Programmable undervoltage and overvoltage detectors
disconnect the load whenever the input supply exceeds
the desired operating range. The supply input is shunt
regulated, allowing safe operation with very high supply
voltages. A multifunction timer delays initial start-up and
controls the circuit breaker’s response time.
■
Programmable Undervoltage/Overvoltage Protection
Low Profile (1mm) ThinSOTTM Package
■
U
APPLICATIO S
■
Hot Board Insertion
TheLTC4251UV/OVthresholdsaredesignedtomatchthe
standard telecom operating range of –43V to –75V. The
LTC4251-1 UV/OV thresholds extend the operating range
toencompass–36Vto –72V. TheLTC4251-2implements
a UV threshold of –43V only.
■
Electronic Circuit Breaker
■
–48V Distributed Power Systems
■
Negative Power Supply Control
■
Central Office Switching
■
Programmable Current Limiting Circuit
■
High Availability Servers
Disk Arrays
All parts are available in the 6-Pin SOT-23 package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
ThinSOT and Hot Swap are trademarks of Linear Technology Corporation.
■
U
TYPICAL APPLICATIO
–48V, 2.5A Hot Swap Controller
Start-Up Behavior
GND
R
*
IN
+
GND
10k
C
L
GATE
5V/DIV
LOAD
OUT
(SHORT PIN)
500mW
100µF
R1
402k
1%
V
3
C
IN
1µF
V
IN
5
4
6
1
Q1
IRF530S
SENSE
2.5A/DIV
UV/OV GATE
LTC4251
C1
10nF
3
TIMER SENSE
1
R2
32.4k
1%
R
C
R
V
S
EE
V
10Ω
OUT
0.02Ω
20V/DIV
2
C
C
T
C
2
150nF
18nF
4
425112 TA01
–48V
425112 TA02
*TWO 0.25W RESISTORS IN SERIES FOR
ON THE PCB ARE RECOMMENDED.
1ms/DIV
R
IN
425112fa
1
LTC4251/LTC4251-1/
LTC4251-2
W W
U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1), All Voltages are Referred to V
TOP VIEW
EE
SENSE 1
6 GATE
Current into VIN (100µs Pulse) ........................... 100mA
Minimum VIN Voltage ........................................... –0.3V
Gate, UV/OV, Timer Voltage.......................–0.3V to 16V
Sense Voltage ............................................–0.6V to 16V
Current Out of Sense Pin (20µs Pulse) ............. –200mA
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
V
2
3
5 UV/OV*
4 TIMER
EE
V
IN
S6 PACKAGE
6-LEAD PLASTIC SOT-23
*UV FOR LTC4251-2
TJMAX = 125°C, θJA = 256°C/W
S6 PART MARKING
ORDER PART NUMBER
LTC4251CS6
LTC4251IS6
LTC4251-
LTUQ
LTUR
LTQU
LTQV
LTK6
LTAAZ
LTC4251C/LTC4251-1C/LTC4251-2C...... 0°C to 70°C
LTC4251I/LTC4251-1I/LTC4251-2I .... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
1CS6
LTC4251-1IS6
LTC4251-
2CS6
LTC4251-2IS6
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Notes 2, 3)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
13
MAX UNITS
V
V
V
V
V
V
to V Zener Voltage
I
I
= 2mA
●
11.5
14.5
V
Ω
Z
IN
IN
IN
IN
IN
EE
IN
IN
r
to V Zener Dynamic Impedance
= 2mA to 30mA
5
Z
EE
I
Supply Current
UV/OV = 4V, V = (V – 0.3V)
●
●
0.8
9.2
1
2
mA
V
IN
IN
Z
V
V
V
V
V
Undervoltage Lockout
Undervoltage Lockout Hysteresis
Coming out of UVLO (Rising V )
11.5
LKO
LKH
CB
IN
V
Circuit Breaker Current Limit Voltage
Analog Current Limit Voltage
Fast Current Limit Voltage
V
V
V
= (V
– V )
EE
●
●
●
●
40
80
50
60
120
300
80
mV
mV
mV
CB
SENSE
= (V
– V )
EE
100
200
ACL
FCL
ACL
FCL
SENSE
= (V
– V
)
EE
150
40
SENSE
I
GATE Pin Output Current
UV/OV = 4V, V
UV/OV = 4V, V
UV/OV = 4V, V
= V , V = 0V (Sourcing)
EE GATE
– V = 0.15V, V
– V = 0.3V, V
58
17
190
µA
mA
mA
GATE
SENSE
SENSE
SENSE
= 3V (Sinking)
= 1V (Sinking)
EE
GATE
EE
GATE
V
V
V
External MOSFET Gate Drive
Gate Low Threshold
V
– V , I = 2mA
●
10
12
V
Z
V
V
GATE
GATEL
UVHI
GATE
EE IN
(Before Gate Ramp-Up)
0.5
UV Threshold High
LTC4251/LTC4251-2
LTC4251-1
●
●
3.075 3.225 3.375
2.300 2.420 2.540
V
V
V
V
V
UV Threshold Low
UV Hysteresis
LTC4251/LTC4251-2
LTC4251-1
●
●
2.775 2.925 3.075
2.050 2.160 2.270
V
V
UVLO
UVHST
OVHI
LTC4251/LTC4251-2
LTC4251-1
0.30
0.26
V
V
OV Threshold High
LTC4251
LTC4251-1
●
●
5.85
5.86
6.15
6.17
6.45
6.48
V
V
425112fa
2
LTC4251/LTC4251-1/
LTC4251-2
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Notes 2, 3)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
V
OV Threshold Low
LTC4251
LTC4251-1
●
●
5.25
5.61
5.55
5.91
5.85
6.21
V
V
OVLO
V
OV Hysteresis
LTC4251
LTC4251-1
0.60
0.26
V
V
OVHST
I
I
SENSE Input Current
UV/OV Input Current
UV/OV = 4V, V
UV/OV = 4V
= 50mV
SENSE
●
●
–30
–15
±0.1
4
µA
µA
V
SENSE
INP
±1
V
V
Timer Voltage High Threshold
Timer Voltage Low Threshold
Timer Current
TMRH
TMRL
TMR
1
V
I
Timer On (Initial Cycle, Sourcing), V
Timer Off (Initial Cycle, Sinking), V
Timer On (Circuit Breaker, Sourcing), V
Timer Off (Cooling Cycle, Sinking), V
= 2V
5.8
28
230
5.8
µA
mA
µA
TMR
= 2V
TMR
TMR
= 2V
= 2V
µA
TMR
t
t
UV Low to GATE Low
OV High to GATE Low
0.7
1
µs
µs
PLLUG
PHLOG
LTC4251/LTC4251-1
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to V unless otherwise
EE
specified.
Note 3: UV/OV = 4V refers to UV = 4V for the LTC4251-2.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
UV/OV = 4V refers to UV = 4V for the LTC4251-2.
I
vs Temperature
I
vs V
r vs Temperature
IN
IN
IN
Z
2000
1800
1600
1400
1200
1000
800
10
1000
100
10
V
= (V – 0.3V)
I
= 2mA
IN
Z
IN
T
= –40°C
9
8
7
6
5
4
3
2
A
T
= 25°C
= 85°C
A
T
A
600
T
= 125°C
A
1
400
200
0
0.1
–55 –35 –15
5
25 45 65 85 105 125
85 105
125
0
2
4
6
8
10 12 14 16 18 20 22
(V)
–55 –35 –15
5
25 45 65
TEMPERATURE (°C)
TEMPERATURE (°C)
V
IN
425112 G01
425112 G02
425112 G03
425112fa
3
LTC4251/LTC4251-1/
LTC4251-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
UV/OV = 4V refers to UV = 4V for the LTC4251-2.
vs Undervoltage Lockout Hysteresis
Undervoltage Lockout V
Temperature
LKO
V vs Temperature
Z
V
vs Temperature
LKH
12.0
11.5
11.0
10.5
10.0
9.5
1.6
1.4
1.2
1
14.5
14.0
13.5
13.0
12.5
12.0
I
= 2mA
IN
0.8
0.6
0.4
0.2
0
9.0
8.5
8.0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
45
85 105 125
25
65
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425112 G05
425112 G06
425112 G04
Circuit Breaker Current Limit
Analog Current Limit Voltage V
vs Temperature
Fast Current Limit Voltage V
vs Temperature
ACL
FCL
Voltage V vs Temperature
CB
120
115
110
105
100
95
60
58
56
54
52
50
48
46
44
42
40
300
275
250
225
200
175
150
90
85
80
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425112 G08
425112 G07
425112 G09
I
(Source) vs Temperature
I
(ACL, Sink) vs Temperature
I
(FCL, Sink) vs Temperature
GATE
GATE
GATE
400
350
300
250
200
150
100
50
30
25
20
15
10
5
70
65
60
55
50
45
40
UV/0V = 4V
TIMER = 0V
UV/0V = 4V
TIMER = 0V
V
V
UV/0V = 4V
TIMER = 0V
V
V
– V = 0.3V
= V
V
V
– V = 0.15V
SENSE
= 1V
EE
SENSE
EE
SENSE EE
= 0V
= 3V
GATE
GATE
GATE
0
0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425112 G12
425112 G11
425112 G10
425112fa
4
LTC4251/LTC4251-1/
LTC4251-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
UV/OV = 4V refers to UV = 4V for the LTC4251-2.
V
GATE
vs Temperature
V
GATEL
vs Temperature
UV Threshold vs Temperature
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.375
UV/0V = 4V
UV/0V = 4V,
= 0V,
GATE THRESHOLD
BEFORE RAMP-UP
LTC4251/LTC4251-2
V
V
= 0V
V
TMR
SENSE
TMR
= V
3.275
EE
V
UVH
3.175
3.075
2.975
V
UVL
2.875
2.775
–55 –35 –15
5
25 45 65 85 105 125
85
105 125
–55 –35 –15
5
25 45 65
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425112 G13
425112 G14
425112 G15
UV Threshold vs Temperature
OV Threshold vs Temperature
OV Threshold vs Temperature
6.51
6.41
6.31
6.21
6.11
6.01
5.91
5.81
5.71
5.61
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05
6.45
6.25
6.05
5.85
5.65
5.45
5.25
LTC4251-1
LTC4251-1
LTC4251
V
OVH
V
UVHI
V
OVHI
V
OVLO
V
OVL
V
UVLO
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425112 G18
425112 G16
425112 G17
I
vs Temperature
I
vs (V
– V )
TIMER Threshold vs Temperature
SENSE
SENSE
SENSE
EE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–10
–12
–14
–16
–18
–20
–22
–24
–26
–28
–30
0.01
0.1
V
TMRH
1.0
10
V
TMRL
UV/0V = 4V
TIMER = 0V
GATE = HIGH
UV/0V = 4V
100
1000
TIMER = 0V
GATE = HIGH
V
– V = 50mV
T = 25°C
SENSE
EE
A
–1.5 –1.0 –0.5
(V
0
0.5 1.0 1.5
– V ) (V)
2.0
–55 –35 –15
5
45
85 105 125
25
65
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
SENSE
EE
425112 G20
425112 G21
425112 G19
425112fa
5
LTC4251/LTC4251-1/
LTC4251-2
U W
UV/OV = 4V refers to UV = 4V for the LTC4251-2.
TYPICAL PERFOR A CE CHARACTERISTICS
I
(Initial Cycle, Sourcing) vs
I
(Initial Cycle, Sinking) vs
I
(Circuit Breaking, Sourcing)
TMR
TMR
TMR
Temperature
Temperature
vs Temperature
10
9
8
7
6
5
4
3
2
1
0
280
260
240
220
200
180
50
45
40
35
30
25
20
15
10
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425112 G22
425112 G24
425112 G23
t
and t
PHLOG
I
(Cooling Cycle, Sinking)
PLLUG
TMR
vs Temperature
vs Temperature
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
10
9
8
7
6
5
4
3
2
1
0
t
(LTC4251/LTC4251-1)
PHLOG
PLLUG
t
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
425112 G26
425112 G25
425112fa
6
LTC4251/LTC4251-1/
LTC4251-2
U
U
U
PI FU CTIO S
UV/OV refers to the UV pin for the LTC4251-2. The OV comparator in the LTC4251-2 is disabled. All
references in the text to overvoltage, OV, V and V do not apply to the LTC4251-2.
OVHI
OVLO
SENSE (Pin 1): Circuit Breaker/Current Limit SENSE Pin.
Load current is monitored by sense resistor RS connected
between SENSE and VEE, and controlled in three steps. If
SENSE exceeds VCB (50mV), the circuit breaker compara-
tor activates a 230µA TIMER pin pull-up current. The
LTC4251/LTC4251-1/LTC4251-2latchoffwhenCTcharges
to4V. IfSENSEexceedsVACL (100mV), theanalogcurrent
limitamplifierpullsGATEdownandregulatestheMOSFET
current at VACL/RS. In the event of a catastrophic short-
circuit, SENSE may overshoot 100mV. If SENSE reaches
VFCL (200mV), the fast current limit comparator pulls
GATE low with a strong pull-down. To disable the circuit
breakerandcurrentlimitfunctions,connectSENSEtoVEE.
If SENSE exceeds 50mV while GATE is high, a 230µA pull-
upcurrentchargesCT. IfSENSEdropsbelow50mVbefore
TIMER reaches 4V, a 5.8µA pull-down current slowly
dischargesCT.IntheeventthatCT eventuallyintegratesup
to the 4V VTMRH threshold, TIMER latches high with a
5.8µA pull-up source and GATE quickly pulls low. The
LTC4251/LTC4251-1/LTC4251-2 fault latches may be
cleared by either pulling TIMER low with an external
device, or by pulling UV/OV below VUVLO
.
UV/OV (Pin 5): Undervoltage/Overvoltage Input. This dual
function pin detects undervoltage as well as overvoltage.
The high threshold at the UV comparator is set at VUVHI
with VUVHST hysteresis. The high threshold at the OV
comparator is set at VOVHI with VOVHST hysteresis. If
UV/OV < VUVLO or UV/OV > VOVHI, GATE pulls low. If
UV/OV > VUVHI and UV/OV < VOVLO, the LTC4251/
LTC4251-1/LTC4251-2 attempt to start-up. The internal
UVLO at VIN always overrides UV/OV. A low at UV resets
aninternalfaultlatch.AhighatOVpullsGATElowbutdoes
not reset the fault latch. A 1nF to 10nF capacitor at UV/OV
eliminates transients and switching noise from affecting
the UV/OV thresholds and prevents glitches at the GATE
pin.
Kelvin-sense connections between the sense resistor and
the VEE and SENSE pins are strongly recommended, see
Figure 6.
VEE (Pin 2): Negative Supply Voltage Input. Connect this
pin to the negative side of the power supply.
VIN (Pin 3): Positive Supply Input. Connect this pin to the
positive side of the supply through a dropping resistor. A
shunt regulator typically clamps VIN at 13V. An internal
undervoltage lockout (UVLO) circuit holds GATE low until
the VIN pin is greater than VLKO (9.2V), overriding UV/OV.
If UV is high, OV is low and VIN comes out of UVLO, TIMER
starts an initial timing cycle before initiating a GATE ramp
up. If VIN drops below approximately 8.2V, GATE pulls low
immediately.
GATE (Pin 6): N-Channel MOSFET Gate Drive Output. This
pin is pulled high by a 58µA current source. GATE is pulled
lowbyinvalidconditionsatVIN (UVLO),UV/OV,orthefault
latch. GATE is actively servoed to control fault current as
measured at SENSE. A compensation capacitor at GATE
stabilizes this loop. A comparator monitors GATE to
ensure that it is low before allowing an initial timing cycle,
GATE ramp up after an overvoltage event, or restart after
a current limit fault.
TIMER (Pin 4): Timer Input. TIMER is used to generate a
delay at start up, and to delay shutdown in the event of an
output overload. TIMER starts an initial timing cycle when
the following conditions are met: UV is high, OV is low, VIN
clears UVLO, TIMER pin is low, GATE is lower than VGATEL
and VSENSE – VEE < VCB. A pull-up current of 5.8µA then
charges CT, generating a time delay. If CT charges to
VTMRH (4V) the timing cycle terminates, TIMER quickly
pulls low and GATE is activated.
425112fa
7
LTC4251/LTC4251-1/
LTC4251-2
W
BLOCK DIAGRA
V
3
IN
V
V
IN
V
–
+
OVHI
OV**
58µA
6
GATE
V
EE
+
–
0.5V
UV/OV*
5
–
+
EE
UV
V
UVLO
4V
V
V
IN
IN
LOGIC
+
–
230µA
5.8µA
–
+
FCL
200mV
V
IN
V
+
–
EE
22µA
4
TIMER
–
+
+
ACL
V
= 10mV
OS
5k
1V
5.8µA
V
EE
+
–
–
V
V
V
EE
EE
EE
+
–
1
SENSE
CB
50mV
V
+
–
EE
2
425112 BD
*UV FOR THE LTC4251-2
** THE OV COMPARATOR IS DISABLED FOR LTC4251-2
V
EE
U
OPERATIO
Note that for simplicity, the following assumptions are made in the text. Firstly, UV/OV also means the UV
pin of the LTC4251-2. Secondly, all overvoltage conditions and references to OV, V
the OV comparator in this part is disabled.
and V
do not apply to the LTC4251-2 as
OVHI
OVLO
Hot Circuit Insertion
external MOSFET switch (see Figure 1). Both inrush con-
trol and short-circuit protection are provided by the
MOSFET.
When circuit boards are inserted into a live backplane, the
supplybypasscapacitorscandrawhugetransientcurrents
from the power bus as they charge. The flow of current
damages the connector pins and glitches the power bus,
causing other boards in the system to reset. The LTC4251/
LTC4251-1/LTC4251-2 are designed to turn on a circuit
board supply in a controlled manner, allowing insertion or
removal without glitches or connector damage.
A detailed schematic is shown in Figure 2. –48V and
–48RTN receive power through the longest connector
pins, and are the first to connect when the board is
inserted. The GATE pin holds the MOSFET off during this
time. UV/OV determines whether or not the MOSFET
should be turned on based upon internal, high-accuracy
thresholds and an external divider. UV/OV does double
duty by also monitoring whether or not the connector is
seated. The top of the divider detects –48RTN by way of a
short connector pin that is the last to mate during the
Initial Start-Up
The LTC4251/LTC4251-1/LTC4251-2 reside on a remov-
able circuit board and control the path between the con-
nector and load or power conversion circuitry with an
insertion sequence.
425112fa
8
LTC4251/LTC4251-1/
LTC4251-2
U
OPERATIO
PLUG-IN BOARD
is released. GATE sources 58µA (IGATE), charging the
MOSFET gate and associated capacitance.
–48RTN
+
+
ISOLATED
DC/DC
LTC4251
+
LOW
VOLTAGE
CIRCUITRY
C
LOAD
CONVERTER
MODULE
Two modes of operation are possible during the time the
MOSFET is first turning on, depending on the values of
external components, MOSFET characteristics and nomi-
nal design current. One possibility is that the MOSFET will
turn on gradually so that the inrush into the load capaci-
tance remains a low value. The output will simply ramp to
–48V and the MOSFET will be fully enhanced. A second
possibilityisthattheloadcurrentexceedsthecurrentlimit
threshold of 100mV/RS. In this case, the LTC4251/
LTC4251-1/LTC4251-2 will ramp the output by sourcing
100mV/RS current into the load capacitance. It is impor-
tant to set the timer delay so that, regardless of which
start-up mode is used, the start-up time is less than the
TIMERdelaytime.Ifthisconditionisnotmet,theLTC4251/
LTC4251-1/LTC4251-2 may shut down after one TIMER
delay.
–48V
–
–
BACKPLANE
425112 F01
Figure 1. Basic LTC4251 Hot Swap Topology
–48RTN
LONG
R
IN
10k
500mW
R1
402k
1%
SHORT
C
IN
1µF
V
IN
UV/OV
TIMER
+
LTC4251
C
L
C1
10nF
100µF
TYP
V
SENSE GATE
EE
R2
32.4k
1%
R
C
C
C
C
T
10Ω
18nF
150nF
3
LONG
4
–48V
1
2
425112 F02
R
S
Q1
IRF530S
20mΩ
Figure 2. –48V, 2.5A Hot Swap Controller
Board Removal
If the board is withdrawn from the card cage, the UV/OV
divider is the first to lose connection. This shuts off the
MOSFET and commutates the flow of current in the
connector. When the power pins subsequently separate,
there is no arcing.
Interlock Conditions
A start-up sequence commences once five initial “inter-
lock” conditions are met:
1. The input voltage VIN exceeds 9.2V (VLKO
)
2. The voltage at UV/OV falls within the range of VUVHI to
VOVLO (UV > VUVHI, LTC4251-2)
Current Control
Three levels of protection handle short-circuit and over-
load conditions. Load current is monitored by SENSE and
resistor RS. There are three distinct thresholds at SENSE:
50mV for a timed circuit breaker function; 100mV for an
analogcurrentlimitloop;and200mVforafast,feedforward
comparator which limits peak current in the event of a
catastrophic short-circuit.
3. The (SENSE – VEE) voltage is <50mV (VCB)
4. The voltage on the timer capacitor (CT) is less than 1V
(VTMRL
)
5. GATE is less than 0.5V (VGATEL
)
The first two conditions are continuously monitored and
the latter three are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
If, owingtoanoutputoverload, thevoltagedropacrossRS
exceeds 50mV, TIMER sources 230µA into CT. CT eventu-
allychargestoa4VthresholdandtheLTC4251/LTC4251-1/
LTC4251-2latchoff. IftheoverloadgoesawayandSENSE
measures less than 50mV, CT slowly discharges (5.8µA).
In this way the circuit breaker function will also respond to
low duty cycle overloads, and accounts for fast heating
and slow cooling characteristic of the MOSFET.
TIMER begins the start-up sequence by sourcing 5.8µA
intoCT. IfVIN orUV/OVfallsoutofrange, thestart-upcycle
stopsandTIMERdischargesCT tolessthan1V, thenwaits
until the aforementioned conditions are once again met. If
CT successfully charges to 4V, TIMER pulls low and GATE
425112fa
9
LTC4251/LTC4251-1/
LTC4251-2
U
OPERATIO
Higher overloads are handled by an analog current limit
loop. If the drop across RS reaches 100mV, the current
limiting loop servos the MOSFET gate and maintains a
constant output current of 100mV/RS. Note that because
SENSE > 50mV, TIMER charges CT during this time and
the LTC4251/LTC4251-1/LTC4251-2 will eventually shut
down.
The LTC4251/LTC4251-1/LTC4251-2 circuit breaker latch
is reset by either pulling UV/OV momentarily low, or drop-
pingtheinputvoltageVINbelowtheinternalUVLOthreshold
of 8.2V.
Although short-circuits are the most obvious fault type,
several operating conditions may invoke overcurrent pro-
tection. Noise spikes from the backplane or load, input
steps caused by the connection of a second, higher
voltage supply, transient currents caused by faults on
adjacentcircuitboardssharingthesamepowerbus,orthe
insertion of non-hot swappable products could cause
higher than anticipated input current and temporary de-
tection of an overcurrent condition. The action of TIMER
and CT rejects these events allowing the LTC4251/
LTC4251-1/LTC4251-2 to “ride out” temporary overloads
and disturbances that would trip a simple current com-
parator and in some cases, blow a fuse.
Low impedance failures on the load side of the LTC4251/
LTC4251-1/LTC4251-2 coupled with 48V or more driving
potential can produce current slew rates well in excess of
50A/µs. Under these conditions, overshoot is inevitable. A
fastSENSEcomparatorwithathresholdof200mVdetects
overshoot and pulls GATE low much harder and hence
much faster than can the weaker current limit loop. The
100mV/RS current limit loop then takes over, and servos
the current as previously described. As before, TIMER
runs and latches the LTC4251/LTC4251-1/LTC4251-2 off
when CT reaches 4V.
W U U
U
APPLICATIO S I FOR ATIO
(Refer to Block Diagram)
SHUNT REGULATOR
UV/OV COMPARATORS
A fast responding regulator shunts the LTC4251/ Two hysteretic comparators for detecting under- and
LTC4251-1/LTC4251-2 VIN pin. Power is derived from overvoltage conditions, with the following thresholds,
–48RTNbyanexternalcurrentlimitingresistor. Theshunt monitor the dual function UV/OV pin:
regulator clamps VIN to 13V (VZ). A 1µF decoupling
UV turning on at VUVHI
capacitor at VIN filters supply transients and contributes a
UV turning off at VUVLO
OV turning off at VOVHI
OV turning on at VOVLO
short delay at start-up. A 10k 1/2W (RIN) resistor can be
two 5k 1/4W resistors in series.
INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)
The UV and OV trip point ratio for LTC4251 is designed to
match the standard telecom operating range of 43V to
75V. The LTC4251-2 implements a UV threshold of 43V
only.
Internal circuitry monitors VIN for undervoltage. The exact
thresholds are defined by VLKO and its hysteresis, VLKH
.
When VIN rises above 9.2V (VLKO) the chip is enabled;
below 8.2V (VLKO-VLKH) it is disabled and GATE is pulled
low.TheUVLOfunctionatVIN shouldnotbeconfusedwith
the UV/OV pin. These are completely separate functions.
A divider (R1, R2) is used to scale the supply voltage.
Using R1 = 402k and R2 = 32.4k gives a typical operating
range of 43.2V to 74.4V. The under- and overvoltage
shutdown thresholds are then 39.2V and 82.5V. 1%
divider resistors are recommended to preserve threshold
accuracy. The same resistor values can be used for the
LTC4251-2.
425112fa
10
LTC4251/LTC4251-1/
LTC4251-2
W U U
APPLICATIO S I FOR ATIO
U
The R1-R2 divider values shown in the Typical Application
set a standing current of slightly more than 100µA, and
define an impedance at UV/OV of 30k. In most applica-
tions, 30k impedance coupled with 300mV UV hysteresis
makestheLTC4251/LTC4251-1/LTC4251-2insensitiveto
noise.Ifmorenoiseimmunityisdesired,adda1nFto10nF
filter capacitor from UV/OV to VEE.
1. 5.8µA slow charge; initial timing delay
2. 230µA fast charge; circuit breaker delay
3. 5.8µA slow discharge; circuit breaker “cool-off”
4. Low impedance switch; resets capacitor after initial
timing delay, in undervoltage lockout, and in overvolt-
age
TheUVandOVtrippointthresholdsfortheLTC4251-1are
designed to encompass the standard telecom operating
range of –36V to –72V.
For initial startup, the 5.8µA pull-up is used. The low
impedance switch is turned off and the 5.8µA current
source is enabled when the four interlock conditions are
met. CT charges to 4V in a time period given by:
A divider (R1, R2) is used to scale the supply voltage.
Using R1 = 442k and R2 = 34.8k gives a typical operating
range of 33.2V to 81V. The typical under- and overvoltage
shutdown thresholds are then 29.6V and 84.5V. 1%
divider resistors are recommended to preserve threshold
accuracy.
4V •CT
5.8µA
t =
(1)
When CT reaches 4V (VTMRH), the low impedance switch
turns on and discharges CT. The GATE output is enabled
and the load turns on.
The R1-R2 divider values shown in the Typical Application
set a standing current of slightly more than 100µA, and
define an impedance at UV/OV of 32k. In most applica-
tions, 32k impedance coupled with 260mV UV hysteresis
makes the LTC4251-1 insensitive to noise. If more noise
immunityisdesired,adda1nFto10nFfiltercapacitorfrom
UV/OV to VEE.
CIRCUIT BREAKER TIMER OPERATION
If the SENSE pin detects more than 50mV across RS, the
TIMER pin charges CT with 230µA. If CT charges to 4V, the
GATE pin pulls low and the LTC4251/LTC4251-1/
LTC4251-2 latch off. The part remains latched off until
either the UV/OV pin is momentarily pulsed low, or VIN
dips into UVLO and is then restored. The circuit breaker
timeout period is given by
UV/OV OPERATION
A low input to the UV comparator will reset the chip and
pull the GATE and TIMER pins low. A low-to-high UV
transition will initiate an initial timing sequence if the three
remaining interlock conditions are met.
4V •CT
230µA
t =
(2)
Overvoltage conditions detected by the OV comparator
will also pull GATE low, thereby shutting down the load,
but it will not reset the circuit breaker latch. Returning the
supply voltage to an acceptable range restarts the GATE
pin provided all interlock conditions except TIMER are
met.
Intermittent overloads may exceed the 50mV threshold at
SENSE, butiftheirdurationissufficientlyshortTIMERwill
not reach 4V and the LTC4251/LTC4251-1/LTC4251-2
will not latch off. To handle this situation, the TIMER
dischargesCT slowlywitha5.8µApull-downwheneverthe
SENSE voltage is less than 50mV. Therefore any intermit-
tentoverloadwithanaggregatedutycycleof2.5%ormore
will eventually trip the circuit breaker and latch off the
LTC4251/LTC4251-1/LTC4251-2. Figure 3 shows the cir-
cuit breaker response time in seconds normalized to 1µF.
The asymmetric charging and discharging of CT is a fair
gauge of MOSFET heating.
TIMER
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor, CT, is used at
TIMER to provide timing for the LTC4251/LTC4251-1/
LTC4251-2.Fourdifferentcharginganddischargingmodes
are available at TIMER:
425112fa
11
LTC4251/LTC4251-1/
LTC4251-2
W U U
U
APPLICATIO S I FOR ATIO
10
IftheSENSEpinencountersavoltagegreaterthan100mV,
the ACL amplifier will servo GATE downwards in an
attempt to control the MOSFET current. Since GATE over-
drives the MOSFET in normal operation, the ACL amplifier
needs time to discharge GATE to the threshold of the
MOSFET. For a mild overload, the ACL amplifier can
control the MOSFET current, but in the event of a severe
overload the current may overshoot. At SENSE = 200mV,
the FCL comparator takes over, quickly discharging the
GATE pin to near VEE potential. FCL then releases, and the
ACL amplifier takes over. All the while TIMER is running.
The effect of FCL is to add a nonlinear response to the
control loop in favor of reducing MOSFET current.
1
t
4
=
C (µF) (235.8 • D) – 5.8
T
0.1
0.01
0
20
40
60
80
100
FAULT DUTY CYCLE, D (%)
425112 F03
Figure 3. Circuit Breaker Response Time
GATE
Owing to inductive effects in the system, FCL typically
overcorrects the current limit loop, and GATE under-
shoots. A zero in the loop (resistor RC in series with the
gate capacitor) helps the ACL amplifier recover.
GATE is pulled low to VEE under any of the following
conditions: in UVLO, during the initial timing cycle, in an
overvoltage condition, or when the LTC4251/LTC4251-1/
LTC4251-2 are latched off after a short-circuit. When
GATEturnson,a58µAcurrentsourcechargestheMOSFET
gate and any associated external capacitance. VIN limits
gate drive to no more than 14.5V.
SHORT-CIRCUIT OPERATION
Circuit behavior arising from a load-side low impedance
shortisshowninFigure4. Initially, thecurrentovershoots
the analog current limit level of VSENSE = 100mV (Trace 2)
astheGATEpinworkstobringVGS undercontrol(Trace 3).
The overshoot glitches the backplane in the negative
direction, and when the current is reduced to 100mV/RS
the backplane responds by glitching in the positive
direction.
Gate-drain capacitance (CGD) feed through at the first
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at VIN,
and eliminates current spikes at insertion. A large external
gate-sourcecapacitoristhusunnecessaryforthepurpose
of compensating CGD. Instead, a smaller value (≥10nF)
capacitor CC is adequate. CC also provides compensation
for the analog current limit loop.
TIMERcommenceschargingCT (Trace4)whiletheanalog
currentlimitloopmaintainsthefaultcurrentat100mV/RS,
which in this case is 5A (Trace 2). Note that the backplane
voltage (Trace 1) sags under load. When CT reaches 4V,
GATE turns off, the load current drops to zero and the
backplane rings up to over 100V. The positive peak is
usually limited by avalanche breakdown in the MOSFET,
and can be further limited by adding a zener diode across
the input from – 48V to – 48RTN, such as Diodes Inc.
SMAT70A.
SENSE
The SENSE pin is monitored by the circuit breaker (CB)
comparator, the analog current limit (ACL) amplifier, and
thefastcurrentlimit(FCL)comparator.Eachofthesethree
measures the potential of SENSE relative to VEE. If SENSE
exceeds 50mV, the CB comparator activates the 230µA
TIMER pull-up. At 100mV, the ACL amplifier servos the
MOSFET current, and at 200mV the FCL comparator
abruptlypullsGATElowinanattempttobringtheMOSFET
current under control. If any of these conditions persists
long enough for TIMER to charge CT to 4V (see Equa-
tion (2)), the LTC4251/LTC4251-1/LTC4251-2 latch off
and pull GATE low.
A low-impedance short on one card may influence the
behavior of others sharing the same backplane. The initial
glitch and backplane sag as seen in Figure 4, Trace 1, can
robchargefromoutputcapacitorsonadjacentcards. When
the faulty card shuts down, current flows in to refresh the
425112fa
12
LTC4251/LTC4251-1/
LTC4251-2
W U U
APPLICATIO S I FOR ATIO
U
capacitors. If LTC4251, LTC4251-1 or LTC4251-2s are
used throughout, they respond by limiting the inrush cur-
where 40mV represents the guaranteed minimum circuit
breaker threshold.
rent to a value of 100mV/R . If C is sized correctly, the
S
T
During the initial charging process, the LTC4251/
LTC4251-1/LTC4251-2 may operate the MOSFET in cur-
rent limit, forcing 80mV to 120mV across RS. The mini-
mum inrush current is given by:
capacitors will recharge long before C times out.
T
SUPPLY RING
OWING TO
MOSFET
SUPPLY RING
OWING
TO CURRENT
OVERSHOOT
–48RTN
50V/DIV
TURN-OFF
TRACE 1
TRACE 2
80mV
RS
ONSET OF OUTPUT
SHORT-CIRCUIT
IINRUSH(MIN)
=
(4)
SENSE
200mV/DIV
FAST CURRENT
LIMIT
GATE
10V/DIV
Maximum short-circuit current limit is calculated using
maximum VSENSE, or:
TRACE 3
TRACE 4
ANALOG
CURRENT LIMIT
TIMER
5V/DIV
LATCH OFF
120mV
C
RAMP
ISHORT−CIRCUIT(MAX)
=
TIMER
(5)
425112 F04
RS
2ms/DIV
Figure 4. Output Short-Circuit Behavior
(All Waveforms are Referenced to V
The TIMER capacitor CT must be selected based on the
slowest expected charging rate; otherwise TIMER might
time out before the load capacitor is fully charged. A value
forCT iscalculatedbasedonthemaximumtimeittakesthe
load capacitor to charge. That time is given by:
EE)
MOSFET SELECTION
The external MOSFET switch must have adequate safe
operating area (SOA) to charge the load capacitance on
start-up and handle short-circuit conditions until TIMER
latchoff. These considerations take precedence over DC
current ratings. A MOSFET with adequate SOA for a given
application can always handle the required current, but the
oppositecannotbesaid.Consultthemanufacturer’sMOSFET
data sheet for safe operating area and effective transient
thermal impedance curves.
CL •VSUPPLY(MAX)
C •V
I
tCL CHARGE
=
=
(6)
IINRUSH(MIN)
Substituting Equation (4) for IINRUSH(MIN) and equating
(6) with (2) gives:
CL •VSUPPLY(MAX) •RS •230µA
CT
=
(7)
(4V •80mV)
MOSFET selection is a three-step process. First, R is
S
calculated, and then the time required to charge the load
capacitance is determined. This timing, along with the
maximumshort-circuitcurrentandmaximuminputvoltage
defines an operating point that is checked against the
MOSFET’s SOA curve.
Returning to Equation (2), the TIMER period is calculated
and used in conjunction with VSUPPLY(MAX) and
ISHORT-CIRCUIT(MAX) tochecktheSOAcurvesofaprospec-
tive MOSFET.
As a numerical design example, consider a 30W load,
which requires 1A input current at 36V. If VSUPPLY(MAX) =
72V and CL = 100µF, Equation (3) gives RSENSE = 40mΩ;
Equation (7) gives CT = 207nF. To account for errors in
RSENSE, CT, TIMER current (230µA) and TIMER threshold
(4V), the calculated value should be multiplied by 1.5,
giving a nearest standard value of CT = 330nF.
Tobeginadesign,firstspecifytherequiredloadcurrentand
load capacitance, I and C . The circuit breaker current trip
L
L
point (50mV/R ) should be set to accommodate the maxi-
S
mum load current. Note that maximum input current to a
DC/DC converter is expected at V
by:
. R is given
SUPPLY (MIN)
S
40mV
IL(MAX)
If a short-circuit occurs, a current of up to 120mV/40mΩ
= 3A will flow in the MOSFET for 5.7ms as dictated by
RS
=
(3)
425112fa
13
LTC4251/LTC4251-1/
LTC4251-2
W U U
U
APPLICATIO S I FOR ATIO
CT = 330nF in Equation (2). The MOSFET must be selected
based on this criterion. The IRF530S can handle 100V and
3A for 10ms, and is safe to use in this application.
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
60
MTY100N10E
50
SUMMARY OF DESIGN FLOW
40
IRF3710
To summarize the design flow, consider the application
shown in Figure 2, which was designed for 50W:
30
IRF540
IRF530
20
Calculate maximum load current: 50W/36V = 1.4A; allow-
ing 83% converter efficiency, IIN (MAX) = 1.7A.
IRF740
10
0
0
4000
MOSFET C (pF)
6000
2000
8000
Calculate RS: from Equation (3) RS = 20mΩ.
ISS
425112 F05
CalculateCT:fromEquation(7)CT =150nF(including1.5X
correction factor).
Figure 5. Recommended Compensation
Capacitor C vs MOSFET C
C
ISS
Calculate TIMER period: from Equation (2) the short-
circuit time-out period is t = 2.6ms.
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the VEE and
SENSE pins are strongly recommended. The drawing in
Figure 6 illustrates the correct way of making connections
between the LTC4251/LTC4251-1/LTC4251-2 and the
sense resistor. PCB layout should be balanced and sym-
metrical to minimize wiring errors. In addition, the PCB
layout for the sense resistor should include good thermal
management techniques for optimal sense resistor power
dissipation.
Calculate maximum short-circuit current: from Equation
(5) maximum short-circuit current could be as high as
120mV/20mΩ = 6A.
Consult MOSFET SOA curves: the IRF530S can handle 6A
at 72V for 5ms, so it is safe to use in this application.
FREQUENCY COMPENSATION
The LTC4251/LTC4251-1/LTC4251-2 typical frequency
compensation network for the analog current limit loop is
a series RC (10Ω) and CC connected to VEE. Figure 5
depicts the relationship between the compensation ca-
pacitor CC and the MOSFET’s CISS. The line in Figure 5 is
used to select a starting value for CC based upon the
MOSFET’s CISS specification. Optimized values for CC are
shown for several popular MOSFETs. Differences in the
optimized value of CC versus the starting value are small.
Nevertheless, compensation values should be verified by
board level short-circuit testing.
CURRENT FLOW
FROM LOAD
CURRENT FLOW
TO –48V BACKPLANE
SENSE RESISTOR
TRACK WIDTH W:
W
0.03" PER AMP
ON 1 OZ COPPER
425112 F06
TO
SENSE
TO
EE
V
Figure 6. Making PCB Connections to the Sense Resistor
As seen in Figure 4 previously, at the onset of a short-
circuit event, the input supply voltage can ring dramati-
callyowingtoseriesinductance. Ifthisvoltageavalanches
theMOSFET,currentcontinuestoflowthroughtheMOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
TIMING WAVEFORMS
System Power-Up
Figure 7 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
time point 1, the supply ramps up, together with UV/OV
425112fa
14
LTC4251/LTC4251-1/
LTC4251-2
W U U
APPLICATIO S I FOR ATIO
U
and VOUT. VIN follows at a slower rate as set by the VIN
bypass capacitor. At time point 2, VIN exceeds VLKO and
timing cycle terminates. The TIMER capacitor is then
quickly discharged. At time point 4, the VTMRL threshold is
reached and the conditions of GATE < VGATEL and SENSE
< VCB must be satisfied before a start-up cycle is allowed
to begin. GATE sources 58µA into the external MOSFET
gate and compensation network. When the GATE voltage
reaches the MOSFET’s threshold, current begins flowing
into the load capacitor. At time point 5, the SENSE voltage
(VSENSE–VEE )reachestheVCB thresholdandactivatesthe
TIMER. The TIMER capacitor is charged by a 230µA
current source pull-up. At time point 6, the analog current
limit loop activates. Between time point 6 and time point 7,
the GATE voltage is held essentially constant and the
sense voltage is regulated at VACL. As the load capacitor
nears full charge, its current begins to decline. At time
point 7, the load current falls and the sense voltage drops
belowVACL. Theanalogcurrentlimitloopshutsoffandthe
GATE pin ramps further. At time point 8, the sense voltage
drops below VCB and TIMER now discharges through a
5.8µA current source pull-down. At time point 9, GATE
reaches its maximum voltage as determined by VIN.
the internal logic checks for VUVHI < UV/OV < VOVLO
,
TIMER < VTMRL, GATE < VGATEL and SENSE < VCB. When
all conditions are met, an initial timing cycle starts and the
TIMER capacitor is charged by a 5.8µA current source
pull-up. At time point 3, TIMER reaches the VTMRH thresh-
old and the initial timing cycle terminates. The TIMER
capacitor is then quickly discharged. At time point 4, the
V
TMRL threshold is reached and the conditions of GATE <
VGATEL and SENSE < VCB must be satisfied before a start-
up cycle is allowed to begin. GATE sources 58µA into the
external MOSFET gate and compensation network. When
the GATE voltage reaches the MOSFET’s threshold,
current begins flowing into the load capacitor. At time
point5, theSENSEvoltage(VSENSE –VEE )reachestheVCB
threshold and activates the TIMER. The TIMER capacitor
is charged by a 230µA current-source pull-up. At time
point 6, the analog current limit loop activates. Between
time point 6 and time point 7, the GATE voltage is held
essentially constant and the sense voltage is regulated at
VACL. As the load capacitor nears full charge, its current
begins to decline. At point 7, the load current falls and the
sense voltage drops below VACL. The analog current limit
loop shuts off and the GATE pin ramps further. At time
point 8, the sense voltage drops below VCB and TIMER
now discharges through a 5.8µA current source pull-
down. At time point 9, GATE reaches its maximum voltage
as determined by VIN.
Undervoltage Lockout Timing
InFigure9,whenUV/OVdropsbelowVUVLO (timepoint1),
TIMER and GATE pull low. If current has been flowing, the
SENSE pin voltage decreases to zero as GATE collapses.
When UV/OV recovers and clears VUVHI (time point 2), an
initial time cycle begins followed by a start-up cycle.
Undervoltage Timing with Overvoltage Glitch
Live Insertion with Short Pin Control of UV/OV
In Figure 10, when UV/OV clears VUVHI (time point 1), an
initial timing cycle starts. If the system bus voltage over-
shoots VOVHI as shown at time point 2, TIMER discharges.
At time point 3, the supply voltage recovers and drops
belowtheVOVLO threshold. Theinitialtimingcyclerestarts
followed by a start-up cycle.
In this example as shown in Figure 8, power is delivered
through long connector pins whereas the UV/OV divider
makescontactthroughashortpin.Thisensuresthepower
connections are firmly established before the LTC4251/
LTC4251-1/LTC4251-2 are activated. At time point 1, the
power pins make contact and VIN ramps through VLKO. At
time point 2, the UV/OV divider makes contact and its
voltage exceeds VUVHI. In addition, the internal logic
checks for VUVHI < UV/OV < VOVHI, TIMER < VTMRL, GATE
< VGATEL and SENSE < VCB. When all conditions are met,
an initial timing cycle starts and the TIMER capacitor is
charged by a 5.8µA current source pull-up. At time point
3, TIMER reaches the VTMRH threshold and the initial
Overvoltage Timing
During normal operation, if UV/OV exceeds VOVHI as
shown at time point 1 of Figure 11, the TIMER status is
unaffected. Nevertheless, GATE pulls down and discon-
nects the load. At time point 2, UV/OV recovers and drops
below the VOVLO threshold. A gate ramp up cycle ensues.
425112fa
15
LTC4251/LTC4251-1/
LTC4251-2
W U U
U
APPLICATIO S I FOR ATIO
If the overvoltage glitch is long enough to deplete the load
capacitor, a full start-up cycle may occur as shown be-
tween time points 3 through 6.
Timer Behavior
In Figure 12a, the TIMER capacitor charges at 230µA if the
SENSE pin exceeds VCB. It is discharged with 5.8µA if the
V
IN
CLEARS V , CHECK V
LKO
<UV/0V < V
, TIMER< V
OVLO
, GATE < V
TMRL
AND SENSE < V
.
CB
UVHI
GATEL
TIMER CLEARS V
, CHECK GATE < V
TMRL
AND SENSE < V .
GATEL CB
1
2
3
4
5 6
7 8
9
GND-V
EE
UV/0V
V
LKO
V
IN
V
TMRH
5.8µA
TIMER
GATE
230µA
5.8µA
V
TMRL
5.8µA
58µA
58µA
V
V
ACL
SENSE
CB
V
OUT
425112 F07
INITIAL TIMING CYCLE
START-UP CYCLE
Figure 7. System Power-Up Timing (All Waveforms are Referenced to V )
EE
UV/0V CLEARS V , CHECK V < V
UVHI IN
– V , TIMER < V , GATE < V
LKH TMRL GATEL
AND SENSE < V .
CB
LKO
TIMER CLEARS V
, CHECK GATE < V
AND SENSE < V .
CB
TMRL
GATEL
1
2
3
4
5 6
7 8
9
GND-V
EE
V
UVHI
UV/0V
V
LKO
V
IN
V
TMRH
5.8µA
TIMER
GATE
230µA
5.8µA
V
TMRL
5.8µA
58µA
58µA
V
V
ACL
CB
SENSE
V
OUT
425112 F08
INITIAL TIMING CYCLE
START-UP CYCLE
Figure 8. Power-Up Timing with a Short-Pin (All Waveforms are Referenced to V )
EE
425112fa
16
LTC4251/LTC4251-1/
LTC4251-2
W U U
APPLICATIO S I FOR ATIO
U
SENSE pin is less than VCB. In Figure 12b, when TIMER
exceeds VTMRH, TIMER is latched high by the 5.8µA pull-
up and GATE pulls down immediately. In Figure 12c,
multiple momentary faults cause the TIMER capacitor to
integrate until it latches.
current amplifier can establish control. If TIMER reaches
VTMRH, GATE pulls low and latches off.
Resetting a Fault Latch
As shown in Figure 14, a latched fault is reset by either
pullingUV/OVbelowVUVLO orpullingTIMERbelowVTMRL
.
Analog Current Limit and Fast Current Limit
An initial timing cycle is initiated if UV/OV is used for reset.
IfTIMERisusedforreset,theinitialtimingcycleisskipped.
In Figure 13a, when SENSE exceeds VACL, GATE is regu-
lated by the analog current limit amplifier loop. When
SENSE drops below VACL, GATE is allowed to pull up. In
Figure 13b, when a severe fault occurs, SENSE exceeds
Internal Soft-Start
An internal soft-start feature ramps the positive input of
the analog current limit amplifier during initial start-up.
V
FCL and GATE immediately pulls down until the analog
V
UV/0V
DROPS BELOW V
. TIMER, GATE, AND SENSE ARE PULLED TO V .
UVLO
EE
AND SENSE < V .
CB
V
UV/0V
CLEARS V
, CHECK TIMER < V
, GATE < V
TMRL
UVHI
GATEL
TIMER CLEARS V
, CHECK GATE < V
AND SENSE < V .
CB
TMRL
GATEL
1
2
3
4
5 6
7 8 9
V
UVHI
UV/0V
TIMER
GATE
V
UVLO
V
TMRH
5.8µA
230µA
5.8µA
V
TMRL
5.8µA
58µA
58µA
V
V
ACL
SENSE
CB
425112 F09
INITIAL TIMING CYCLE
START-UP CYCLE
Figure 9. Undervoltage Lockout Timing (All Waveforms are Referenced to V )
EE
V
CLEARS V . CHECK TIMER < V , GATE < V
UVHI TMRL GATEL
AND SENSE < V .
CB
UV/0V
V
OVERSHOOTS V
AND TIMER ABORTS INITIAL TIMING CYCLE.
AND TIMER RESTARTS INITIAL TIMING CYCLE.
OVLO
UV/0V
V
OVHI
DROPS BELOW V
UV/0V
TIMER CLEARS V
, CHECK GATE < V
AND SENSE < V .
CB
TMRL
GATEL
1
2 3
4
5
6
7
8 9 10
V
OVHI
V
OVLO
UV/0V
TIMER
GATE
V
UVHI
V
TMRH
5.8µA
230µA
5.8µA
V
TMRL
5.8µA
58µA
58µA
V
V
ACL
SENSE
CB
425112 F10
START-UP CYCLE
INITIAL TIMING CYCLE
Figure 10. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to V )
EE
425112fa
17
LTC4251/LTC4251-1/
LTC4251-2
W U U
U
APPLICATIO S I FOR ATIO
The ramp duration is approximately 200µs. This feature
reduces load current dl/dt at start-up. As illustrated in
Figure 15, soft-startisinitiatedbyaTIMERtransitionfrom
VTMRH to VTMRL or when UV/OV falls below the VOVLO
threshold after an OV fault. After soft-start duration, load
current is limited by VACL/RS.
V
OVERSHOOTS V
AND GATE PULLS TO V . TIMER UNAFFECTED.
UV/0V
OVHI
EE
V
UV/0V
DROPS BELOW V
AND GATE RESTARTS.
OVLO
1
2
3 4
5 6
7
V
OVHI
UV/0V
V
OVLO
V
TMRH
230µA
TIMER
GATE
5.8µA
5.8µA
5.8µA
5.8µA
58µA
58µA
V
V
ACL
SENSE
CB
425112 F11
Figure 11. Overvoltage Timing (All Waveforms are Referenced to V )
EE
TIMER LATCHES OFF
TIMER LATCHES OFF
1
2
1
2
1
2
3
4
5.8µA
5.8µA
V
TMRH
V
230µA
V
TMRL
TMRH
5.8µA
230µA
230µA
TIMER
GATE
230µA
TIMER
GATE
TIMER
GATE
5.8µA
5.8µA
V
V
ACL
V
ACL
ACL
V
V
CB
V
SENSE
SENSE
SENSE
CB
CB
V
OUT
V
V
OUT
OUT
425112 F12c
CB FAULT
CB FAULT
425112 F12a
425112 F12b
(12a) Momentary Circuit-Breaker Fault
(12b) Circuit-Breaker Time-Out
(12c) Multiple Circuit-Breaker Faults
Figure 12. Timer Behavior (All Waveforms are Referenced to V )
EE
TIMER LATCHES OFF
1
2
1 2
3 4
5.8µA
V
TMRH
V
TMRH
230µA
TIMER
GATE
TIMER
GATE
230µA
5.8µA
5.8µA
58µA
V
FCL
V
ACL
V
ACL
SENSE
V
SENSE
CB
V
CB
V
V
OUT
OUT
425112 F13b
425112 F13a
(13a) Analog Current Limit Fault
(13b) Fast Current Limit Fault
Figure 13. Current Limit Behavior (All Waveforms are Referenced to V )
EE
425112fa
18
LTC4251/LTC4251-1/
LTC4251-2
W U U
APPLICATIO S I FOR ATIO
U
RESET LATCHED TIMER FAULT BY EXTERNAL LOW PULSE.
1 2 3 4 5 6
END OF INITIAL TIMING CYCLE
5.8µA
1
2
3
4
5
6
V
TMRH
5.8µA
V
TMRH
230µA
TIMER
GATE
5.8µA
V
TMRL
5.8µA
TIMER
GATE
230µA
~V
V
TMRL
58µA
GS(th)
58µA
58µA
V
V
ACL
V
ACL
SENSE
CB
SENSE
V
425112 F14
CB
V
ACL
+ 10mV
INTERNAL
SOFT-START
REFERENCE
Figure 14. Latched Fault Reset Timing
10mV
425112 F15
(All Waveforms are Referenced to V )
EE
Figure 15. Internal Soft-Start Timing
(All Waveforms are Referenced to V )
EE
U
PACKAGE DESCRIPTIO
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
2.90 BSC
(NOTE 4)
0.62
MAX
0.95
REF
1.22 REF
1.50 – 1.75
(NOTE 4)
2.80 BSC
1.4 MIN
3.85 MAX 2.62 REF
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
425112fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC4251/LTC4251-1/
LTC4251-2
U
TYPICAL APPLICATIO S
GND
R
IN
+
GND
10k
C
L
LOAD
(SHORT PIN)
500mW
100µF
R1
402k
1%
3
C
IN
1µF
V
IN
5
4
6
1
Q1
IRF540
UV/OV GATE
LTC4251
C1
R3
22Ω
10nF
3
4
TIMER SENSE
R2
1
R
C
V
EE
32.4k
R
S
PUSH-
RESET
10Ω
S1
1%
C
82nF
0.01Ω
2
C
C
T
22nF
2
425112 TA03
–48V
Figure 16. –48V/5A Application with Reverse
SENSE Pin Limiting and Push-Reset at TIMER Pin
GND
R
IN
10k
R3
31.6k
+
GND
(SHORT PIN)
R1
C
L
LOAD
OUT
500mW
100µF
V
3
442k
1%
C
IN
1µF
D1
V
IN
BZX84C36
5
4
6
1
Q1
IRF540S
UV/OV GATE
LTC4251-1
C1
10nF
R4
22Ω
3
4
TIMER SENSE
1
R2
34.8k
1%
R
C
R
S
V
EE
10Ω
0.02Ω
2
C
C
T
C
2
220nF
22nF
425112 TA04
V
= –48V
SUPPLY
Figure 17. Power-Limited Circuit Breaker Application
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1640AH/LT1640AL Negative High Voltage Hot Swap Controllers in SO-8
Negative High Voltage Supplies from –10V to –80V
Supplies from 9V to 80V, Latched Off/Autoretry
3V to 16.5V, Overvoltage Protection up to 33V
LT1641-1/LT1641-2
LTC1642
Positive High Voltage Hot Swap Controllers in SO-8
Fault Protected Hot Swap Controller
LTC1921
Dual –48V Supply and Fuse Monitor
±1V UV and ±1.5V OV Threshold Accuracy, ±200V Transient
Protection, Drives Three Optoisolators for Status
LT4250
–48V Hot Swap Controller in SO-8
Active Current Limiting, Supplies from –20V to –80V
LTC4252-1/
LTC4252-2
Negative Voltage Hot Swap Controller in MSOP
Fast Active Current Limiting with Drain Accelerated Response,
Supplies from –15V
LTC4253
Negative Voltage Hot Swap Controller with
3-Output Sequencer
Fast Active Current Limiting with Drain Accelerated Response,
Supplies from –15V
425112fa
LT 0406 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408) 432-1900 FAX:(408)434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2001
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