LTC4252-1IMS [Linear]
Negative Voltage Hot Swap Controllers; 负电压热插拔控制器
| 型号： | LTC4252-1IMS |
| 厂家： | 
Linear |
| 描述： | Negative Voltage Hot Swap Controllers |
| 文件： | 总32页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4252-1/LTC4252-2
Negative Voltage
Hot Swap Controllers
U
FEATURES
DESCRIPTIO
■
Allows Safe Board Insertion and Removal from a
The LTC®4252 negative voltage Hot SwapTM controller
allows a board to be safely inserted and removed from a
livebackplane.Outputcurrentiscontrolledbythreestages
of current limiting: a timed circuit breaker, active current
limiting and a fast feedforward path that limits peak
current under worst-case catastrophic fault conditions.
Live –48V Backplane
■
Floating Topology Permits Very High Voltage
Operation
■
Programmable Analog Current Limit With Circuit
Breaker Timer
■
Fast Response Time Limits Peak Fault Current
Programmable undervoltage and overvoltage detectors
disconnect the load whenever the input supply exceeds
the desired operating range. The LTC4252’s supply input
is shunt regulated, allowing safe operation with very high
supply voltages. A multifunction timer delays initial start-
up and controls the circuit breaker’s response time. The
circuit breaker’s response time is accelerated by sensing
excessive MOSFET drain voltage, keeping the MOSFET
within its safe operating area (SOA). A programmable
soft-start circuit controls MOSFET inrush current at start-
up. A power good status output can enable a power
module at start-up or disable it if the circuit breaker trips.
■
Programmable Soft-Start Current Limit
■
Programmable Timer with Drain Voltage
Accelerated Response
■
Programmable Undervoltage/Overvoltage Protection
■
LTC4252-1: Latch Off After Fault
LTC4252-2: Automatic Retry After Fault
■
U
APPLICATIO S
■
Hot Board Insertion
■
Electronic Circuit Breaker
■
–48V Distributed Power Systems
■
■
■
■
■
The LTC4252-1 latches off after a circuit breaker fault times
out. The LTC4252-2 provides automatic retry after a fault.
TheLTC4252isavailableineitheran8-pinor10-pinMSOP.
Negative Power Supply Control
Central Office Switching
Programmable Current Limiting Circuit
High Availability Servers
Disk Arrays
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
U
TYPICAL APPLICATIO
–48V/2.5A Hot Swap Controller
Start-Up Behavior
GND
R
IN
+
3× 1.8k IN SERIES
C
L
1/4W EACH
100µF
LOAD
EN
GATE
5V/DIV
C
IN
1µF
R3
GND
1
5.1k
(SHORT PIN)
V
R1
402k
1%
IN
LTC4252-1
PWRGD
V
SENSE
2.5A/DIV
OUT
*
8
9
2
7
6
4
OV
R
D
1M
UV
DRAIN
GATE
R2
32.4k
1%
10
3
Q1
IRF530S
TIMER
SS
V
OUT
C
20V/DIV
T
SENSE
V
EE
0.33µF
R
10Ω
R
S
0.02Ω
C
5
C1
10nF
C
SS
68nF
C
18nF
C
PWRGD
10V/DIV
4252-1/2 TA01
–48V
* M0C207
1ms/DIV
4252-1/2 TA01a
425212f
1
LTC4252-1/LTC4252-2
W W U W
ABSOLUTE AXI U RATI GS
All Voltages Referred to VEE (Note 1)
Current into VIN (100µs Pulse) ........................... 100mA
VIN, DRAIN Pin Minimum Voltage ....................... –0.3V
Input/Output Pins
(Except SENSE and DRAIN) Voltage ..........–0.3V to 16V
SENSE Pin Voltage ................................... –0.6V to 16V
Current Out of SENSE Pin (20µs Pulse)........... –200mA
Current into DRAIN Pin (100µs Pulse) ................. 20mA
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
LTC4252-1C/LTC4252-2C ....................... 0°C to 70°C
LTC4252-1I/LTC4252-2I ................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
U
W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
NUMBER
LTC4252-1CMS8
LTC4252-2CMS8
LTC4252-1IMS8
LTC4252-2IMS8
LTC4252-1CMS
TOP VIEW
TOP VIEW
V
1
2
3
4
5
10 TIMER
IN
LTC4252-2CMS
LTC4252-1IMS
LTC4252-2IMS
V
SS
SENSE
1
2
3
4
8 TIMER
7 UV/OV
6 DRAIN
5 GATE
IN
PWRGD
SS
9
8
7
6
UV
OV
DRAIN
GATE
SENSE
V
V
EE
EE
MS8 PACKAGE
MS PACKAGE
10-LEAD PLASTIC MSOP
MS8 PART MARKING
MS PART MARKING
8-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 160°C/W
TJMAX = 125°C, θJA = 160°C/W
LTWN
LTWQ
LTRS
LTRT
LTWM
LTWP
LTRQ
LTRR
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
13
MAX
UNITS
V
V
V
V
V
V
V
– V Zener Voltage
I
I
= 2mA
●
12
14.5
Z
IN
IN
IN
IN
IN
EE
IN
IN
r
– V Zener Dynamic Impedance
= 2mA to 30mA
5
Ω
Z
EE
I
Supply Current
UV = OV = 4V, V = (V – 0.3V)
●
●
0.8
9.2
1
2
mA
V
IN
IN
Z
V
V
V
V
V
V
Undervoltage Lockout
Undervoltage Lockout Hysteresis
Coming Out of UVLO (Rising V )
12
LKO
LKH
CB
IN
V
Circuit Breaker Current Limit Voltage
Analog Current Limit Voltage
Fast Current Limit Voltage
SS Voltage
V
V
V
= (V
– V )
EE
●
●
●
40
80
50
60
mV
mV
mV
V
CB
SENSE
= (V
– V ), SS = Open or 2.2V
100
200
2.2
100
120
300
ACL
FCL
SS
ACL
FCL
SENSE
SENSE
EE
= (V
– V
)
150
EE
After End of SS Timing Cycle
R
SS Output Impedance
SS Pin Current
kΩ
SS
I
UV = OV = 4V, V
UV = OV = 0V, V
= V , V = 0V (Sourcing)
= V , V = 2V (Sinking)
22
28
µA
mA
SS
SENSE
SENSE
EE SS
EE SS
V
V
Analog Current Limit Offset Voltage
10
mV
V/V
OS
+V
SS
Ratio (V
+ V ) to SS Voltage
0.05
ACL OS
V
ACL
OS
425212f
2
LTC4252-1/LTC4252-2
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
UV = OV = 4V, V
MIN
TYP
MAX
UNITS
I
GATE Pin Output Current
= V ,
EE
●
40
58
80
µA
GATE
SENSE
= 0V (Sourcing)
V
GATE
UV = OV = 4V, V
GATE
– V = 0.15V,
17
mA
mA
SENSE
= 3V (Sinking)
EE
V
UV = OV = 4V, V
– V = 0.3V,
190
SENSE
= 1V (Sinking)
EE
V
V
V
GATE
GATE
GATEH
V
V
External MOSFET Gate Drive
Gate High Threshold
– V , I = 2mA
●
10
12
V
Z
V
V
GATE
EE IN
= V – V , I = 2mA,
GATE IN
2.8
GATEH
IN
for PWRGD Status (MS Only)
V
V
V
V
V
V
V
Gate Low Threshold
(Before Gate Ramp-Up)
0.5
3.225
2.925
0.3
V
V
GATEL
UVHI
UV Pin Threshold HIGH
UV Pin Threshold LOW
UV Pin Hysteresis
●
●
3.075
2.775
3.375
3.075
V
UVLO
UVHST
OVHI
V
OV Pin Threshold HIGH
OV Pin Threshold LOW
OV Pin Hysteresis
●
●
5.85
5.25
6.15
5.55
0.6
6.45
5.85
V
V
OVLO
OVHST
SENSE
INP
V
I
I
SENSE Pin Input Current
UV, OV Pin Input Current
TIMER Pin Voltage High Threshold
TIMER Pin Voltage Low Threshold
TIMER Pin Current
UV = OV = 4V, V
UV = OV = 4V
= 50mV
●
●
–30
–15
±0.1
4
µA
µA
V
SENSE
±10
V
V
TMRH
TMRL
TMR
1
V
I
Timer On (Initial Cycle/Latchoff/
Shutdown Cooling, Sourcing), V
5.8
µA
= 2V
TMR
Timer Off (Initial Cycle, Sinking), V
= 2V
28
mA
TMR
Timer On (Circuit Breaker, Sourcing,
= 0µA), V = 2V
230
µA
I
DRN
TMR
Timer On (Circuit Breaker, Sourcing,
= 50µA), V = 2V
630
5.8
8
µA
µA
I
DRN
TMR
Timer Off (Circuit Breaker/
Shutdown Cooling, Sinking), V
= 2V
TMR
∆I
[(I
TMR
at I
= 50µA) – (I
50µA
at I
= 0µA)] Timer On (Circuit Breaker with I = 50µA)
DRN
µA/µA
TMRACC
DRN
TMR
DRN
∆I
DRN
V
DRAIN Pin Voltage Low Threshold
DRAIN Leakage Current
For PWRGD Status (MS Only)
2.385
±0.1
7
V
µA
V
DRNL
I
V
= 5V
DRAIN
±1
DRNL
V
V
DRAIN Pin Clamp Voltage
PWRGD Output Low Voltage
I
= 50µA
DRN
DRNCL
PGL
I
I
= 1.6mA (MS Only)
= 5mA (MS Only)
●
●
0.2
0.4
1.1
V
V
PG
PG
I
t
t
t
PWRGD Pull-Up Current
SS Default Ramp Period
UV Low to Gate Low
OV High to Gate Low
V
= 0V (Sourcing) (MS Only)
PWRGD
●
40
58
180
0.4
0.4
80
µA
µs
µs
µs
PGH
SS pin floating, V ramps from 0.2V to 2V
SS
SS
PLLUG
PHLOG
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
pins are negative. All voltages are referenced to V unless otherwise
specified.
EE
Note 2: All currents into device pins are positive; all currents out of device
425212f
3
LTC4252-1/LTC4252-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
rZ vs Temperature
VZ vs Temperature
IIN vs Temperature
10
9
2000
1800
1600
1400
1200
1000
800
14.5
14.0
13.5
13.0
12.5
12.0
I
= 2mA
V = (V – 0.3V)
IN Z
I
IN
= 2mA
IN
8
7
6
5
600
4
400
3
200
2
0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G04
4252-1/2 G03
4252-1/2 G01
Undervoltage Lockout VLKO
vs Temperature
Undervoltage Lockout Hysteresis
VLKH vs Temperature
IIN vs VIN
12.0
11.5
11.0
10.5
10.0
9.5
1000
1.5
1.3
T
= –40°C
A
100
10
1
T
= 25°C
= 85°C
A
1.1
T
A
0.9
0.7
0.5
T
A
= 125°C
9.0
8.5
8.0
0.1
–55 –35 –15
5
25 45 65 85 105 125
0
2
4
6
8
10 12 14 16 18 20 22
(V)
–55 –35 –15
5
25 45 65 95 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
V
IN
4252-1/2 G05
4252-1/2 G02
4252-1/2 G06
Analog Current Limit Voltage
VACL vs Temperature
Circuit Breaker Current Limit
Voltage VCB vs Temperature
Fast Current Limit Voltage VFCL
vs Temperature
120
115
110
105
100
95
300
275
250
225
200
175
150
60
58
56
54
52
50
48
46
44
42
40
90
85
80
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G08
4252-1/2 G09
4252-1/2 G07
425212f
4
LTC4252-1/LTC4252-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
ISS (Sinking) vs Temperature
VSS vs Temperature
RSS vs Temperature
45
110
108
106
104
102
100
98
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05
2.00
UV = OV = V
= V
EE
SENSE
I
= 2mA
40
35
30
25
20
15
10
5
IN
V
= 2V
SS
96
94
92
0
90
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45
125
65 85 105
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G28
4252-1/2 G39
4252-1/2 G26
VOS vs Temperature
(VACL + VOS)/VSS vs Temperature
IGATE (Sourcing) vs Temperature
70
11.0
10.8
10.6
10.4
10.2
10.0
9.8
0.060
0.058
0.056
0.054
0.052
0.050
0.048
0.046
0.044
0.042
0.040
UV/0V = 4V
TIMER = 0V
V
V
= V
65
60
55
50
45
40
SENSE
GATE
EE
= 0V
9.6
9.4
9.2
9.0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G10
4252-1/2 G29
4252-1/2 G30
IGATE (ACL, Sinking)
vs Temperature
IGATE (FCL, Sinking)
vs Temperature
VGATE vs Temperature
400
350
300
250
200
150
100
50
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
30
25
20
15
10
5
UV/0V = 4V
TIMER = 0V
UV/0V = 4V
TIMER = 0V
UV/0V = 4V
TIMER = 0V
V
V
– V = 0.3V
V
= V
SENSE EE
V
V
– V = 0.15V
SENSE
GATE
EE
SENSE
GATE
EE
= 1V
= 3V
0
0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
45
85 105 125
–55 –35 –15
5
25 45 65 85 105 125
25
65
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G12
4252-1/2 G13
4252-1/2 G11
425212f
5
LTC4252-1/LTC4252-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
VGATEH vs Temperature
VGATEL vs Temperature
UV Threshold vs Temperature
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.375
3.275
3.175
3.075
2.975
2.875
2.775
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
UV/0V = 4V
TIMER = 0V
GATE THRESHOLD
BEFORE RAMP-UP
V
I
= V – V
,
GATE
GATEH
IN
IN
= 2mA
(MS ONLY)
V
UVH
V
UVL
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G14
4252-1/2 G15
4252-1/2 G31
ISENSE vs Temperature
ISENSE vs (VSENSE – VEE)
OV Threshold vs Temperature
6.45
6.25
6.05
5.85
5.65
5.45
5.25
–10
–12
–14
–16
–18
–20
–22
–24
–26
–28
–30
0.01
0.1
V
OVH
1.0
10
V
OVL
UV/0V = 4V
TIMER = 0V
GATE = HIGH
UV/0V = 4V
100
TIMER = 0V
GATE = HIGH
V
– V = 50mV
EE
T
= 25°C
SENSE
A
1000
–55 –35 –15
5
25 45 65 85 105 125
–1.5 –1.0 –0.5
(V
0
0.5 1.0 1.5
– V ) (V)
2.0
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
SENSE
EE
4252-1/2 G16
4252-1/2 G18
4252-1/2 G17
ITMR (Initial Cycle, Sourcing)
vs Temperature
ITMR (Initial Cycle, Sinking)
vs Temperature
TIMER Threshold
vs Temperature
50
45
40
35
30
25
20
15
10
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
9
8
7
6
5
4
3
2
1
0
TIMER = 2V
TIMER = 2V
V
TMRH
V
TMRL
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
85
105 125
–55 –35 –15
5
25 45 65
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G21
4252-1/2 G19
4252-1/2 G20
425212f
6
LTC4252-1/LTC4252-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
ITMR (Circuit Breaker, Sourcing)
vs Temperature
ITMR (Circuit Breaker, IDRN = 50µA,
ITMR (Cooling Cycle, Sinking)
vs Temperature
Sourcing) vs Temperature
690
670
650
630
610
590
570
550
280
260
240
220
200
180
10
9
8
7
6
5
4
3
2
1
0
TIMER = 2V
TIMER = 2V
TIMER = 2V
I
= 50µA
I
= 0µA
DRN
DRN
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G32
4252-1/2 G22
4252-1/2 G23
IDRN vs VDRAIN
ITMR vs IDRN
∆ITMRACC/∆IDRN vs Temperature
10
100
9.0
8.8
8.6
8.4
8.2
8.0
7.8
7.6
7.4
7.2
7.0
I
= 2mA
IN
TIMER ON
(CIRCUIT BREAKING,
10
1
I
= 50µA)
DRN
0.1
1
T
= 125°C
A
0.01
T
= 85°C
A
0.001
0.0001
0.00001
T
2
= 25°C
A
T
= –40°C
A
0.1
0.001
0
4
6
8
10 12 14 16
(V)
0.01
0.1
(mA)
1
10
–55 –35 –15
5
25 45 65 85 105 125
I
V
TEMPERATURE (°C)
DRN
DRAIN
4252-1/2 G33
4252-1/2 G25
4252-1/2 G34
VDRNL vs Temperature
VDRNCL vs Temperature
VPGL vs Temperature
2.60
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
8.0
7.8
7.6
7.4
7.2
7.0
6.8
6.6
6.4
6.2
6.0
3.0
2.5
2.0
1.5
1.0
0.5
0
I
= 50µA
DRN
(MS ONLY)
FOR PWRGD STATUS (MS ONLY)
I
= 10mA
PG
I
I
= 5mA
PG
PG
= 1.6mA
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G35
4252-1/2 G36
4252-1/2 G37
425212f
7
LTC4252-1/LTC4252-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
tPLLUG and tPHLOG
vs Temperature
tSS vs Temperature
IPGH vs Temperature
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
62
61
60
59
58
57
56
55
220
210
200
190
180
170
160
150
SS PIN FLOATING,
V
= 0V
PWRGD
V
RAMPS FROM 0.2V TO 2V
(MS ONLY)
SS
t
PLLUG
t
PHLOG
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE °(C)
TEMPERATURE (°C)
4252-1/2 G38
4252-1/2 G24
4252-1/2 G27
U
U
U
PI FU CTIO S
(MS/MS8)
VIN (Pin 1/Pin 1): Positive Supply Input. Connect this pin
to the positive side of the supply through a dropping
resistor. A shunt regulator clamps VIN at 13V. An internal
undervoltage lockout (UVLO) circuit holds GATE low until
the VIN pin is greater than VLKO (9.2V), overriding UV and
OV. If UV is high, OV is low and VIN comes out of UVLO,
TIMERstartsaninitialtimingcyclebeforeinitiatingaGATE
ramp-up. If VIN drops below approximately 8.2V, GATE
pulls low immediately.
low until SS exceeds 20 • VOS = 0.2V. SS is internally
shunted by a 100k resistor (RSS) which limits the SS pin
voltage to 2.2V. This corresponds to an analog current
limit SENSE voltage of 100mV. If the SS capacitor is
omitted, theSSpinrampsfrom0Vto2.2Vinabout220µs.
The SS pin is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
PWRGD (Pin 2/Not Available): Power Good Status Out-
put (MS only). At start-up, PWRGD latches low if DRAIN
is below 2.385V and GATE is within 2.8V of VIN. PWRGD
status is reset by UV, VIN (UVLO) or a circuit breaker fault
timeout.Thispinisinternallypulledhighbya58µAcurrent
source.
SENSE (Pin 4/Pin 3): Circuit Breaker/Current Limit Sense
Pin. Load current is monitored by a sense resistor RS
connected between SENSE and VEE, and controlled in
three steps. If SENSE exceeds VCB (50mV), the circuit
breaker comparator activates a (230µA+8•IDRN) TIMER
pull-up current. If SENSE exceeds VACL (100mV), the
analog current limit amplifier pulls GATE down to regulate
the MOSFET current at VACL/RS. In the event of a cata-
strophic short-circuit, SENSE may overshoot 100mV. If
SENSE reaches VFCL (200mV), the fast current limit com-
paratorpullsGATElowwithastrongpull-down.Todisable
the circuit breaker and current limit functions, connect
SENSE to VEE.
SS (Pin 3/Pin 2): Soft-Start Pin. This pin is used to ramp
inrush current during start up, thereby effecting control
over di/dt. A 20x attenuated version of the SS pin voltage
is presented to the current limit amplifier. This attenuated
voltage limits the MOSFET’s drain current through the
sense resistor during the soft-start current limiting. At the
beginning of a start-up cycle, the SS capacitor (CSS) is
ramped by a 22µA current source. The GATE pin is held
425212f
8
LTC4252-1/LTC4252-2
U
U
U
PI FU CTIO S
(MS/MS8)
VEE (Pin 5/Pin 4): Negative Supply Voltage Input. Connect
UV (Pin 9/Pin 7): Undervoltage Input. The active low
threshold at the UV pin is set at 2.925V with 0.3V hyster-
esis. If UV < 2.925V, PWRGD pulls high, both GATE and
TIMER pull low. If UV rises above 3.225V, this initiates an
initial timing cycle followed by GATE start-up. The internal
UVLO at VIN always overrides UV. A low at UV resets an
internal fault latch. A 1nF to 10nF capacitor at UV prevents
transients and switching noise from affecting the UV
thresholds and prevents glitches at the GATE pin.
this pin to the negative side of the power supply.
GATE (Pin 6/Pin 5): N-Channel MOSFET Gate Drive Out-
put. Thispinispulledhighbya58µAcurrentsource. GATE
is pulled low by invalid conditions at VIN (UVLO), UV, OV,
or a circuit breaker fault timeout. GATE is actively servoed
to control the fault current as measured at SENSE. A
compensation capacitor at GATE stabilizes this loop. A
comparator monitors GATE to ensure that it is low before
allowing an initial timing cycle, GATE ramp-up after an
overvoltage event or restart after a current limit fault.
During GATE start-up, a second comparator detects if
GATE is within 2.8V of VIN before PWRGD is set (MS
package only).
TIMER (Pin 10/Pin 8): Timer Input. TIMER is used to
generate an initial timing delay at start-up and to delay
shutdown in the event of an output overload (circuit
breaker fault). TIMER starts an initial timing cycle when
the following conditions are met: UV is high, OV is low, VIN
clearsUVLO, TIMERpinislow, GATEislowerthanVGATEL
,
DRAIN (Pin7/Pin 6): Drain Sense Input. Connecting an
external resistor, RD, between this pin and the MOSFET’s
drain (VOUT) allows voltage sensing below 6.15V and
currentfeedbacktoTIMER.AcomparatordetectsifDRAIN
is below 2.385V and together with the GATE high com-
SS < 0.2V, and VSENSE – VEE < VCB. A pull-up current of
5.8µA then charges CT, generating a time delay. If CT
chargestoVTMRH (4V),thetimingcycleterminates,TIMER
quickly pulls low and GATE is activated.
parator sets the PWRGD flag. If VOUT is above VDRNCL
,
If SENSE exceeds 50mV while GATE is high, a circuit
breaker cycle begins with a 230µA pull-up current charg-
ing CT. If DRAIN is approximately 7V during this cycle, the
timerpull-uphasanadditionalcurrentof8•IDRN.IfSENSE
drops below 50mV before TIMER reaches 4V, a 5.8µA
pull-down current slowly discharges the CT. In the event
that CT eventually integrates up to the VTMRH threshold,
the circuit breaker trips, GATE quickly pulls low and
PWRGD pulls high. The LTC4252-1 TIMER pin latches
high with a 5.8µA pull-up source. This latched fault is
clearedbyeitherpullingTIMERlowwithanexternaldevice
or by pulling UV below 2.925V. The LTC4252-2 the starts
a shutdown cooling cycle following an overcurrent fault.
This cycle consists of 4 discharging ramps and 3 charging
ramps. The charging and discharging currents are 5.8µA
andTIMERrampsbetweenits1Vand4Vthresholds.Atthe
completion of a shutdown cooling cycle, the LTC4252-2
attempts a start-up cycle.
DRAIN clamps at approximately VDRNCL. The current
through RD is internally multiplied by 8 and added to
TIMER’s 230µA pullup current during a circuit breaker
fault cycle. This reduces the fault time and MOSFET
heating.
OV(Pin8/Pin7):OvervoltageInput.Theactivehighthresh-
old at the OV pin is set at 6.15V with 0.6V hysteresis. If OV
> 6.15V, GATE pulls low. When OV returns below 5.55V,
GATE start-up begins without an initial timing cycle. If an
overvoltage condition occurs in the middle of an initial
timing cycle, the initial timing cycle is restarted after the
overvoltage condition goes away. An overvoltage condi-
tion does not reset the PWRGD flag. The internal UVLO at
VIN always overrides OV. A 1nF to 10nF capacitor at OV
preventstransientsandswitchingnoisefromaffectingthe
OV thresholds and prevents glitches at the GATE pin.
425212f
9
LTC4252-1/LTC4252-2
W
BLOCK DIAGRA
V
IN
–
+
DRAIN
V
IN
2.385V
6.15V
8×
1×
V
EE
V
IN
1×
1×
58µA
V
EE
PWRGD **
GATE
V
IN
6.15V
–
+
58µA
V
EE
OV *
UV *
2.8V
–
V
IN
+
–
V
EE
–
+
+
2.925V
V
IN
–
+
LOGIC
V
IN
230µA
5.8µA
4V
–
+
0.5V
TIMER
+
–
–
+
FCL
200mV
+
V
EE
–
V
5.8µA
EE
1V
V
EE
V
IN
22µA
+
SS
V
OS
= 10mV
ACL
95k
+
–
–
V
EE
R
SS
+
–
V
5k
EE
SENSE
CB
50mV
V
EE
V
EE
+
–
4252-1/2 BD
V
EE
*OV AND UV ARE TIED TOGETHER ON THE MS8 PACKAGE. OV AND UV ARE SEPARATE PINS ON THE MS PACKAGE
** ONLY AVAILABLE IN THE MS PACKAGE
425212f
10
LTC4252-1/LTC4252-2
U
OPERATIO
Hot Circuit Insertion
Interlock Conditions
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient cur-
rents from the power bus as they charge. The flow of
current damages the connector pins and glitches the
power bus, causing other boards in the system to reset.
The LTC4252 is designed to turn on a circuit board supply
in a controlled manner, allowing insertion or removal
without glitches or connector damage.
A start-up sequence commences once these “interlock”
conditions are met.
1. The input voltage VIN exceeds 9.2V (UVLO).
2. The voltage at UV > 3.225V.
3. The voltage at OV < 5.55V.
4. The (SENSE – VEE) voltage is < 50mV (VCB).
5. The voltage at SS is < 0.2V (20 • VOS).
6. The voltage on the TIMER capacitor (CT) is < 1V (VTMRL).
7. The voltage at GATE is < 0.5V (VGATEL).
Initial Start-Up
The LTC4252 resides on a removable circuit board and
controls the path between the connector and load or
powerconversioncircuitrywithanexternalMOSFETswitch
(see Figure 1). Both inrush control and short-circuit pro-
tection are provided by the MOSFET.
The first three conditions are continuously monitored and
the latter four are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
A detailed schematic is shown in Figure 2. –48V and
–48RTN receive power through the longest connector
pinsandarethefirsttoconnectwhentheboardisinserted.
The GATE pin holds the MOSFET off during this time. UV/
OV determines whether or not the MOSFET should be
turned on based upon internal high accuracy thresholds
and an external divider. UV/OV does double duty by also
monitoringwhetherornottheconnectorisseated.Thetop
of the divider detects –48RTN by way of a short connector
pin that is the last to mate during the insertion sequence.
TIMER begins the start-up sequence by sourcing 5.8µA
intoCT.IfVIN,UVorOVfallsoutofrange,thestart-upcycle
stopsandTIMERdischargesCT tolessthan1V, thenwaits
until the aforementioned conditions are once again met. If
CT successfully charges to 4V, TIMER pulls low and both
SS and GATE pins are released. GATE sources 58µA
(IGATE), chargingtheMOSFETgateandassociatedcapaci-
tance. The SS voltage ramp limits VSENSE to control the
inrush current. PWRGD pulls active low when GATE is
within 2.8V of VIN and DRAIN is lower than VDRNL
.
PLUG-IN BOARD
LONG
–48RTN
+
+
LONG
–48RTN
ISOLATED
DC/DC
LTC4252
+
LOW
VOLTAGE
CIRCUITRY
R
IN
+
C
C
LOAD
LOAD
10k
CONVERTER
MODULE
100µF
1/2W
1
LONG
TYP
R1
402k
1%
–48V
SHORT
–
–
C
IN
1µF
V
IN
7
8
2
BACKPLANE
UV/OV
TIMER
SS
4252-1/2 F01
LTC4252-1
C1
10nF
Figure 1. Basic LTC4252 Hot Swap Topology
6
DRAIN
SENSE GATE
V
EE
4
3
5
C
SS
68nF
R2
32.4k
1%
R
D
R
C
C
1M
C
T
0.33µF
C
10Ω
18nF
LONG
–48V
4252-1/2 F02
R
S
0.02Ω
Q1
IRF530S
Figure 2. –48V, 2.5A Hot Swap Controller
425212f
11
LTC4252-1/LTC4252-2
U
OPERATIO
Two modes of operation are possible during the time the
MOSFET is first turning on, depending on the values of
external components, MOSFET characteristics and nomi-
nal design current. One possibility is that the MOSFET will
turn on gradually so that the inrush into the load capaci-
tance remains a low value. The output will simply ramp to
–48V and the LTC4252 will fully enhance the MOSFET. A
secondpossibilityisthattheloadcurrentexceedsthesoft-
startcurrentlimitthresholdof[VSS(t)/20–VOS]/RS.Inthis
case the LTC4252 will ramp the output by sourcing soft-
start limited current into the load capacitance. If the soft-
start voltage is below 1.2V, the circuit breaker TIMER is
held low. Above 1.2V, TIMER ramps up. It is important to
set the timer delay so that, regardless of which start-up
mode is used, the TIMER ramp is less than one circuit
breaker delay time. If this condition is not met, the
LTC4252-1 may shut down after one circuit breaker delay
time whereas the LTC4252-2 may continue to autoretry.
Higher overloads are handled by an analog current limit
loop. If the drop across RS reaches 100mV, the current
limiting loop servos the MOSFET gate and maintains a
constant output current of 100mV/RS. In current limit
mode, VOUT typically rises and this increases MOSFET
heating. If VOUT > VDRNCL (7V), connecting an external
resistor, RD, between VOUT and DRAIN allows the fault
timing cycle to be shortened by accelerating the charging
of the TIMER capacitor. The TIMER pull-up current is
increased by 8 • IDRN. Note that because SENSE > 50mV,
TIMER charges CT during this time and the LTC4252 will
eventually shut down.
Low impedance failures on the load side of the LTC4252
coupled with 48V or more driving potential can produce
current slew rates well in excess of 50A/µs. Under these
conditions, overshoot is inevitable. A fast SENSE com-
parator with a threshold of 200mV detects overshoot and
pulls GATE low much harder and hence much faster than
the weaker current limit loop. The 100mV/RS current limit
loop then takes over and servos the current as previously
described. As before, TIMER runs and shuts down the
LTC4252 when CT reaches 4V.
Board Removal
If the board is withdrawn from the card cage, the UV/OV
divider is the first to lose connection. This shuts off the
MOSFET and commutates the flow of current in the
connector. When the power pins subsequently separate,
there is no arcing.
If CT reaches 4V, the LTC4252-1 latches off with a 5.8µA
pull-up current source whereas the LTC4252-2 starts a
shutdown cooling cycle. The LTC4252-1 circuit breaker
latchisresetbyeitherpullingUVmomentarilylowordrop-
ping the input voltage VIN below the internal UVLO thresh-
oldof8.2VorpullingTIMERmomentarilylowwithaswitch.
The LTC4252-2 retries after its shutdown cooling cycle.
Current Control
Three levels of protection handle short-circuit and over-
load conditions. Load current is monitored by SENSE and
resistor RS. There are three distinct thresholds at SENSE:
50mV for a timed circuit breaker function; 100mV for an
analogcurrentlimitloop;and200mVforafast,feedforward
comparator which limits peak current in the event of a
catastrophic short-circuit.
Although short-circuits are the most obvious fault type,
several operating conditions may invoke overcurrent pro-
tection. Noise spikes from the backplane or load, input
steps caused by the connection of a second, higher
voltage supply, transient currents caused by faults on
adjacent circuit boards sharing the same power bus or the
insertion of non-hot-swappable products could cause
higher than anticipated input current and temporary de-
tection of an overcurrent condition. The action of TIMER
and CT rejects these events allowing the LTC4252 to “ride
out” temporary overloads and disturbances that could trip
a simple current comparator and, in some cases, blow a
fuse.
If, owingtoanoutputoverload, thevoltagedropacrossRS
exceeds 50mV, TIMER sources 230µA into CT. CT eventu-
ally charges to a 4V threshold and the LTC4252 shuts off.
IftheoverloadgoesawaybeforeCT reaches4VandSENSE
measures less than 50mV, CT slowly discharges (5.8µA).
In this way the LTC4252’s circuit breaker function re-
sponds to low duty cycle overloads and accounts for fast
heating and slow cooling characteristics of the MOSFET.
425212f
12
LTC4252-1/LTC4252-2
U
W
U U
APPLICATIO S I FOR ATIO
SHUNT REGULATOR
UV low-to-high (VUVHI) = 3.225V
A fast responding regulator shunts the LTC4252 VIN pin.
Power is derived from –48RTN by an external current
limiting resistor. The shunt regulator clamps VIN to 13V
(VZ). A 1µF decoupling capacitor at VIN filters supply
transients and contributes a short delay at start-up. RIN
should be chosen to accommodate both VIN supply cur-
rent and the drive required for an optocoupler if the
PWRGD function on the 10-pin MS package is used.
Higher current through RIN results in higher dissipation
for RIN and the LTC4252. An alternative is a separate NPN
buffer driving the optocoupler as shown in Figure 3.
Multiple 1/4W resistors can replace a single higher power
RIN resistor.
UV high-to-low (VUVLO) = 2.925V
An OV hysteretic comparator detects overvoltage condi-
tions at the OV pin, with the following thresholds:
OV low-to-high (VOVHI) = 6.150V
OV high-to-low (VOVLO) = 5.550V
The UV and OV trip point ratio is designed to match the
standard telecom operating range of 43V to 75V when
connected together as in Figure 2. A divider (R1, R2) is
used to scale the supply voltage. Using R1 = 402k and R2
= 32.4k gives a typical operating range of 43.2V to 74.4V.
The under- and overvoltage shutdown thresholds are then
39.2V and 82.5V. 1% divider resistors are recommended
to preserve threshold accuracy.
INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)
The R1-R2 divider values shown in the Typical Application
set a standing current of slightly more than 100µA and
define an impedance at UV/OV of 30kΩ. In most applica-
tions, 30kΩ impedance coupled with 300mV UV hyster-
esismakestheLTC4252insensitivetonoise.Ifmorenoise
immunityisdesired,adda1nFto10nFfiltercapacitorfrom
UV/OV to VEE.
A hysteretic comparator, UVLO, monitors VIN for
undervoltage. The thresholds are defined by VLKO and its
hysteresis, VLKH. When VIN rises above 9.2V (VLKO) the
chipisenabled;below8.2V(VLKO –VLKH)itisdisabledand
GATE is pulled low. The UVLO function at VIN should not
be confused with the UV/OV pin(s). These are completely
separate functions.
Separate UV and OV pins are available in the 10-pin MS
package and can be used for a wider operating range such
as 35.5V to 76V as shown in Figure 3. Other combinations
are possible with different resistor arrangements.
UV/OV COMPARATORS
An UV hysteretic comparator detects undervoltage condi-
tions at the UV pin, with the following thresholds:
GND
R
IN
+
10k
C
R4
22k
L
1/2W
100µF
Q2
C
IN
1µF
LOAD
EN
R5
2.2k
GND
1
(SHORT PIN)
R1
V
IN
LTC4252-1
PWRGD
432k
*
1%
9
8
2
7
6
4
UV
R
D
1M
R2
14k
1%
OV
DRAIN
GATE
10
3
Q1
IRF530S
TIMER
SS
R3
32.4k
1%
C
T
SENSE
V
EE
330nF
R
R
S
0.02Ω
C
5
C2
10nF
C
10Ω
SS
68nF
C
C
18nF
4252-1/2 F03
–48V
* M0C207
Q2: MMBT5551LT1
Figure 3. –48V/2.5A Application with Wider Input Operating Range
425212f
13
LTC4252-1/LTC4252-2
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APPLICATIO S I FOR ATIO
UV/OV OPERATION
TIMER to provide timing for the LTC4252. Four different
charging and discharging modes are available at TIMER:
A low input to the UV comparator will reset the chip and
pull the GATE and TIMER pins low. A low-to-high UV
transition will initiate an initial timing sequence if the other
interlock conditions are met. A high-to-low transition in
theUVcomparatorimmediatelyshutsdowntheLTC4252,
pulls the MOSFET gate low and resets the latched PWRGD
high.
1) A 5.8µA slow charge; initial timing and shutdown
cooling delay.
2) A (230µA + 8 • IDRN) fast charge; circuit breaker delay.
3) A 5.8µA slow discharge; circuit breaker "cool off" and
shutdown cooling.
4) Low impedance switch; resets the TIMER capacitor
after an initial timing delay, in UVLO, in UV and in OV
during initial timing.
Overvoltage conditions detected by the OV comparator
will also pull GATE low, thereby shutting down the load.
However, it will not reset the circuit breaker TIMER,
PWRGD flag or shutdown cooling timer. Returning the
supply voltage to an acceptable range restarts the GATE
pin if all the interlock conditions except TIMER are met.
Only during the initial timing cycle does an OV condition
reset the TIMER.
For initial start-up, the 5.8µA pull-up is used. The low
impedance switch is turned off and the 5.8µA current
source is enabled when the interlock conditions are met.
CT charges to 4V in a time period given by:
4V •CT
5.8µA
t =
(2)
DRAIN
Connecting an external resistor, RD, to the dual function
DRAIN pin allows VOUT sensing without it being damaged
by large voltage transients. Below 6.15V, negligible pin
leakage allows a DRAIN low comparator to detect VOUT
less than 2.385V (VDRNL). This condition, together with
the GATE low comparator, sets the PWRGD flag.
When CT reaches 4V (VTMRH), the low impedance switch
turns on and discharges CT. A GATE start-up cycle begins
and both SS and GATE are released.
CIRCUIT BREAKER TIMER OPERATION
If the SENSE pin detects more than a 50mV drop across
RS, the TIMER pin charges CT with (230µA + 8 • IDRN). If
CTchargesto4V,theGATEpinpullslowandtheLTC4252-1
latchesoffwhiletheLTC4252-2startsashutdowncooling
cycle. The LTC4252-1 remains latched off until the UV pin
is momentarily pulsed low or TIMER is momentarily
discharged low by an external switch or VIN dips below
UVLO and is then restored. The circuit breaker timeout
period is given by:
If VOUT > VDRNCL (7V), the DRAIN pin is clamped at about
7V and the current flowing in RD is given by:
VOUT − VDRNCL
IDRN
≈
(1)
RD
This current is scaled up 8 times during a circuit breaker
fault and is added to the nominal 230µA TIMER current.
ThisacceleratesthefaultTIMERpull-upwhentheMOSFET’s
drain-source voltage exceeds 7V and effectively shortens
the MOSFET heating duration.
4V •CT
230µA + 8•IDRN
t =
(3)
TIMER
If VOUT < 6.15V, an internal PMOS device isolates any
DRAIN pin leakage current, making IDRN = 0µA in Equation
(3). If VOUT > 7V (VDRNCL) during the circuit breaker fault
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor CT is used at
425212f
14
LTC4252-1/LTC4252-2
U
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APPLICATIO S I FOR ATIO
period, the charging of CT accelerates by 8 • IDRN of
a shutdown cooling cycle begins if TIMER reaches the 4V
threshold. TIMER starts with a 5.8µA pull-down until it
reaches the 1V threshold. Then, the 5.8µA pull-up turns
back on until TIMER reaches the 4V threshold. Four 5.8µA
pull-down cycles and three 5.8µA pull-up cycles occur
between the 1V and 4V thresholds, creating a time interval
given by:
Equation (1).
Intermittent overloads may exceed the 50mV threshold at
SENSE, but, if their duration is sufficiently short, TIMER
willnotreach4VandtheLTC4252willnotshuttheexternal
MOSFET off. To handle this situation, the TIMER dis-
charges CT slowly with a 5.8µA pull-down whenever the
SENSE voltage is less than 50mV. Therefore, any intermit-
tent overload with VOUT < 6.15V and an aggregate duty
cycle of 2.5% or more will eventually trip the circuit
breaker and shut down the LTC4252. Figure 4 shows the
circuit breaker response time in seconds normalized to
1µF for IDRN = 0µA. The asymmetric charging and dis-
charging of CT is a fair gauge of MOSFET heating.
7 •3V •CT
tSHUTDOWN
=
(5)
5.8µA
At the 1V threshold of the last pull-down cycle, a GATE
ramp-up is attempted.
SOFT-START
The normalized circuit response time is estimated by
Soft-start limits the inrush current profile during GATE
start-up. Unduly long soft-start intervals can exceed the
MOSFET’s SOA rating if powering up into an active load. If
SS floats, an internal current source ramps SS from 0V to
2.2Vinabout220µs. ConnectinganexternalcapacitorCSS
from SS to ground modifies the ramp to approximate an
RC response of:
t
4
=
(4)
CT (µF)
235.8 + 8•I
•D − 5.8
(
[
)
]
DRN
10
I
= 0µA
DRN
t
1
0.1
−
t
4
RSS •CSS
=
VSS(t) ≈ VSS • 1− e
C (µF)
[(235.8 + 8 • I
) • D – 5.8]
T
DRN
(6)
Aninternalresistordivider(95k/5k)scalesVSS(t)downby
20 times to give the analog current limit threshold:
0.01
0
20
40
60
80
100
VSS(t)
FAULT DUTY CYCLE (%)
VACL(t) =
− VOS
(7)
4252-1/2 F04
20
Figure 4. Circuit-Breaker Response Time
This allows the inrush current to be limited to VACL(t)/RS.
Theoffsetvoltage, VOS (10mV), ensuresCSS issufficiently
discharged and the ACL amplifier is in current limit before
GATE start-up. SS is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
SHUTDOWN COOLING CYCLE
For the LTC4252-1 (latchoff version), TIMER latches high
with a 5.8µA pull-up after the circuit breaker fault TIMER
reaches 4V. For the LTC4252-2 (automatic retry version),
425212f
15
LTC4252-1/LTC4252-2
U
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APPLICATIO S I FOR ATIO
GATE
needs time to discharge GATE to the threshold of the
MOSFET.ForamildoverloadtheACLamplifiercancontrol
the MOSFET current, but in the event of a severe overload
the current may overshoot. At SENSE = 200mV the FCL
comparator takes over, quickly discharging the GATE pin
to near VEE potential. FCL then releases and the ACL
amplifier takes over. All the while TIMER is running. The
effect of FCL is to add a nonlinear response to the control
loop in favor of reducing MOSFET current.
GATE is pulled low to VEE under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out. When GATE turns
on, a 58µA current source charges the MOSFET gate and
any associated external capacitance. VIN limits the gate
drive to no more than 14.5V.
Gate-drain capacitance (CGD) feedthrough at the first
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at VIN
and eliminates current spikes at insertion. A large external
gate-sourcecapacitoristhusunnecessaryforthepurpose
of compensating CGD. Instead, a smaller value (≥ 10nF)
capacitor CC is adequate. CC also provides compensation
for the analog current limit loop.
Owing to inductive effects in the system, FCL typically
overcorrects the current limit loop and GATE under-
shoots. A zero in the loop (resistor RC in series with the
gate capacitor) helps the ACL amplifier to recover.
SHORT-CIRCUIT OPERATION
Circuit behavior arising from a load side low impedance
short is shown in Figure 5 for the LTC4252. Initially, the
current overshoots the fast current limit level of VSENSE
=
GATE has two comparators: the GATE low comparator
looks for < 0.5V threshold prior to initial timing or a GATE
start-up cycle; the GATE high comparator looks for < 2.8V
relative to VIN and, together with the DRAIN low compara-
tor, sets PWRGD status during GATE startup.
200mV(Trace2)astheGATEpinworkstobringVGS under
control (Trace 3). The overshoot glitches the backplane in
the negative direction and when the current is reduced to
100mV/RS, the backplane responds by glitching in the
positive direction.
SUPPLY RING OWING TO
CURRENT OVERSHOOT
SUPPLY RING OWING TO
MOSFET TURN OFF
SENSE
The SENSE pin is monitored by the circuit breaker (CB)
comparator, the analog current limit (ACL) amplifier and
thefastcurrentlimit(FCL)comparator.Eachofthesethree
measures the potential of SENSE relative to VEE. When
SENSE exceeds 50mV, the CB comparator activates the
230µATIMERpull-up.At100mV,theACLamplifierservos
the MOSFET current and, at 200mV, the FCL comparator
abruptlypullsGATElowinanattempttobringtheMOSFET
current under control. If any of these conditions persists
long enough for TIMER to charge CT to 4V (see Equa-
tion 3), the LTC4252 shuts down and pulls GATE low.
–48RTN
50V/DIV
ONSET OF OUTPUT SHORT-CIRCUIT
FAST CURRENT LIMIT
SENSE
200mV/DIV
GATE
10V/DIV
ANALOG CURRENT LIMIT
TIMER
5V/DIV
IftheSENSEpinencountersavoltagegreaterthan100mV,
the ACL amplifier will servo GATE downwards in an
attempt to control the MOSFET current. Since GATE over-
drives the MOSFET in normal operation, the ACL amplifier
LATCH OFF
C
RAMP
TIMER
0.5ms/DIV
4252-1/2 F05
Figure 5. Output Short-Circuit Behavior of LTC4252
425212f
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TIMERcommenceschargingCT (Trace4)whiletheanalog
currentlimitloopmaintainsthefaultcurrentat100mV/RS,
which in this case is 5A (Trace 2). Note that the backplane
voltage (Trace 1) sags under load. Timer pull-up is accel-
erated by VOUT. When CT reaches 4V, GATE turns off,
PWRGD pulls high, the load current drops to zero and the
backplane rings up to over 100V. The positive peak is
usually limited by avalanche breakdown in the MOSFET
and can be further limited by adding a zener diode across
the input from –48V to –48RTN, such as Diodes Inc.
SMAT70A.
MOSFET selection is a 3-step process by assuming the
absenseofasoft-startcapacitor.First,RS iscalculatedand
then the time required to charge the load capacitance is
determined. This timing, along with the maximum short-
circuit current and maximum input voltage defines an
operatingpointthatischeckedagainsttheMOSFET’sSOA
curve.
To begin a design, first specify the required load current
and Ioad capacitance, IL and CL. The circuit breaker
current trip point (VCB/RS) should be set to accommodate
the maximum load current. Note that maximum input
A low impedance short on one card may influence the
behavior of others sharing the same backplane. The initial
glitch and backplane sag as seen in Figure 5 Trace 1, can
rob charge from output capacitors on adjacent cards.
When the faulty card shuts down, current flows in to
refresh the capacitors. If LTC4252s are used by the other
cards, they respond by limiting the inrush current to a
value of 100mV/RS. If CT is sized correctly, the capacitors
will recharge long before CT times out.
current to a DC/DC converter is expected at VSUPPLY(MIN)
RS is given by:
.
VCB(MIN)
IL(MAX)
RS =
(8)
where VCB(MIN) = 40mV represents the guaranteed mini-
mum circuit breaker threshold.
During the initial charging process, the LTC4252 may
operate the MOSFET in current limit, forcing (VACL) be-
tween 80mV to 120mV across RS. The minimum inrush
current is given by:
POWER GOOD, PWRGD
PWRGD latches low if GATE charges up to within 2.8V of
VIN andDRAINpullsbelowVDRNL duringstart-up.PWRGD
is reset in UVLO, in a UV condition or if CT charges up to
4V. An overvoltage condition has no effect on PWRGD
status. A58µAcurrentpullsthispinhighduringreset. Due
to voltage transients between the power module and
PWRGD, optoisolation is recommended. This pin pro-
vides sufficent drive for an optocoupler.
80mV
RS
IINRUSH(MIN)
=
(9)
Maximum short-circuit current limit is calculated using
the maximum VSENSE. This gives
120mV
ISHORTCIRCUIT(MAX)
=
(10)
RS
The TIMER capacitor CT must be selected based on the
slowest expected charging rate; otherwise TIMER might
time out before the load capacitor is fully charged. A value
forCT iscalculatedbasedonthemaximumtimeittakesthe
load capacitor to charge. That time is given by:
MOSFET SELECTION
The external MOSFET switch must have adequate safe
operating area (SOA) to handle short-circuit conditions
until TIMER times out. These considerations take prece-
dence over DC current ratings. A MOSFET with adequate
SOAforagivenapplicationcanalwayshandletherequired
current, but the opposite may not be true. Consult the
manufacturer’sMOSFETdatasheetforsafeoperatingarea
and effective transient thermal impedance curves.
C L•VSUPPLY(MAX)
C •V
I
tCL(CHARGE)
=
=
(11)
IINRUSH(MIN)
425212f
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The maximum current flowing in the DRAIN pin is given
by:
FromtheSOAcurvesofaprospectiveMOSFET, determine
the time allowed, tSOA(MAX). CSS is given by:
tSOA(MAX)
0.916•RSS
V
SUPPLY(MAX)− VDRNCL
CSS
=
(15)
IDRN(MAX)
=
(12)
RD
In the above example, 60mV/40mΩ gives 1.5A. tSOA(MAX)
for the IRF530S is 40ms. From Equation (15),
CSS = 437nF. Actual board evaluation showed that
CSS = 100nF was appropriate. The ratio (RSS • CSS) to
tCL(CHARGE) is a good gauge as a large ratio may result in
the time-out period expiring. This gauge is determined
empirically with board level evaluation.
Approximating a linear charging rate as IDRN drops from
IDRN(MAX) to zero, the IDRN component in Equation (3) can
be approximated with 0.5 • IDRN(MAX). Rearranging equa-
tion, TIMER capacitor CT is given by:
tCL(CHARGE) • 230µA + 4 •I
(
)
DRN(MAX)
CT =
(13)
4V
SUMMARY OF DESIGN FLOW
Returning to Equation (3), the TIMER period is calculated
and used in conjunction with VSUPPLY(MAX) and
ISHORTCIRCUIT(MAX) to check the SOA curves of a prospec-
tive MOSFET.
To summarize the design flow, consider the application
shown in Figure 2. It was designed for 50W.
Calculate the maximum load current: 50W/36V = 1.4A;
allowing for 83% converter efficiency, IIN(MAX) = 1.7A.
As a numerical design example, consider a 30W load,
which requires 1A input current at 36V. If VSUPPLY(MAX)
=
Calculate RS: from Equation (8) RS = 20mΩ.
72V and CL = 100µF, RD = 1MΩ, Equation (8) gives RS =
40mΩ; Equation (13) gives CT = 441nF. To account for
errorsinRS, CT, TIMERcurrent(230µA), TIMERthreshold
(4V), RD, DRAIN current multiplier and DRAIN voltage
clamp (VDRNCL), the calculated value should be multiplied
by 1.5, giving the nearest standard value of CT = 680nF.
Calculate ISHORTCIRCUIT(MAX): from Equation (9)
ISHORTCIRCUIT(MAX) = 6A.
Select a MOSFET that can handle 6A at 72V: IRF530S.
Calculate CT: from Equation (13) CT = 220nF. Select
CT = 330nF, which gives the circuit breaker time-out pe-
riod tMAX = 1.76ms.
If a short-circuit occurs, a current of up to 120mV/
40mΩ = 3A will flow in the MOSFET for 3.6ms as dictated
by CT = 680nF in Equation (3). The MOSFET must be
selected based on this criterion. The IRF530S can handle
100Vand3Afor10msandissafetouseinthisapplication.
Consult MOSFET SOA curves: the IRF530S can handle 6A
at 72V for 5ms, so it is safe to use in this application.
Calculate CSS: using Equations (14) and (15) select
CSS = 68nF.
Computingthemaximumsoft-startcapacitorvalueduring
soft-start to a load short is complicated by the nonlinear
MOSFET’s SOA characteristics and the RSSCSS response.
An overly conservative but simple approach begins with
the maximum circuit breaker current, given by:
FREQUENCY COMPENSATION
TheLTC4252typicalfrequencycompensationnetworkfor
the analog current limit loop is a series RC (10Ω) and CC
connected to VEE. Figure 6 depicts the relationship be-
tween the compensation capacitor CC and the MOSFET’s
CISS. The line in Figure 6 is used to select a starting value
60mV
RS
ICB(MAX)
=
(14)
425212f
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60
CURRENT FLOW
FROM LOAD
CURRENT FLOW
TO –48V BACKPLANE
NTY100N10
50
40
30
20
10
0
SENSE RESISTOR
TRACK WIDTH W:
W
0.03" PER AMP
IRF3710
ON 1 OZ COPPER
IRF540
IRF530
4252-1/2 F07
IRF740
TO
SENSE
TO
EE
V
0
2000
4000
MOSFET C (pF)
6000
8000
Figure 7. Making PCB Connections to the Sense Resistor
ISS
4252-1/2 F06
Figure 6. Recommended Compensation
Capacitor CC vs MOSFET CISS
TIMING WAVEFORMS
System Power-Up
for CC based upon the MOSFET’s CISS specification. Opti-
mized values for CC are shown for several popular
MOSFETs. Differences in the optimized value of CC versus
the starting value are small. Nevertheless, compensation
values should be verified by board level short-circuit
testing.
Figure 8 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
time point 1, the supply ramps up, together with UV/OV,
VOUT and DRAIN. VIN and PWRGD follow at a slower rate
as set by the VIN bypass capacitor. At time point 2, VIN
As seen in Figure 5 previously, at the onset of a short-
circuit event, the input supply voltage can ring dramati-
callyowingtoseriesinductance. Ifthisvoltageavalanches
theMOSFET,currentcontinuestoflowthroughtheMOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
exceeds VLKO and the internal logic checks for UV > VUVHI
,
OV < VOVLO, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS
and TIMER < VTMRL. If all conditions are met, an initial
timing cycle starts and the TIMER capacitor is charged by
a 5.8µA current source pull-up. At time point 3, TIMER
reaches the VTMRH threshold and the initial timing cycle
terminates. The TIMER capacitor is quickly discharged. At
time point 4, the VTMRL threshold is reached and the
conditions of GATE < VGATEL, SENSE < VCB and
SS < 20 • VOS must be satisfied before a GATE ramp-up
cycle begins. SS ramps up as dictated by RSS • CSS (as in
Equation 6); GATE is held low by the analog current limit
(ACL) amplifier until SS crosses 20 • VOS. Upon releasing
GATE, 58µA sources into the external MOSFET gate and
compensation network. When the GATE voltage reaches
the MOSFET’s threshold, current begins flowing into the
load capacitor at time point 5. At time point 6, load current
reaches the SS control level and the analog current limit
loop activates. Between time points 6 and 8, the GATE
voltage is servoed, the SENSE voltage is regulated at
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connectionsbetweenthesenseresistorandtheLTC4252’s
VEE and SENSE pins are strongly recommended. The
drawing in Figure 7 illustrates the correct way of making
connections between the LTC4252 and the sense resistor.
PCB layout should be balanced and symmetrical to mini-
mize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
425212f
19
LTC4252-1/LTC4252-2
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V
CLEARS V , CHECK UV > V
, OV < V
, GATE < V
, SENSE < V , SS < 20 • V AND TIMER < V
IN
LKO
UVHI
OVLO
GATEL
CB
OS
TMRL
TIMER CLEARS V
, CHECK GATE < V
, SENSE < V AND SS < 20 • V
CB
TMRL
GATEL
OS
1
2
3 4 56
7
8 9 10 11
GND – V OR
EE
(–48RTN) – (–48V)
UV/OV
V
V
LKO
IN
V
TMRH
230µA + 8 • I
DRN
5.8µA
TIMER
5.8µA
5.8µA
V
TMRL
58µA
V
– V
GATEH
IN
GATE
SS
58µA
V
GATEL
20 • (V
20 • (V + V
+ V
)
)
ACL
OS
CB
OS
OS
20 • V
V
V
ACL
CB
SENSE
V
OUT
V
V
DRNCL
DRNL
DRAIN
PWRGD
GATE
START-UP
INITIAL TIMING
4252-1/2 F08
Figure 8. System Power-Up Timing (All Waveforms are Referenced to VEE)
VACL(t) (Equation 7) and soft-start limits the slew rate of
the load current. If the SENSE voltage (VSENSE – VEE)
reaches the VCB threshold at time point 7, the circuit
breaker TIMER activates. The TIMER capacitor, CT, is
chargedbya(230µA+8•IDRN)currentpull-up.Astheload
capacitor nears full charge, load current begins to decline.
At time point 8, the load current falls and the SENSE
voltage drops below VACL(t). The analog current limit loop
shuts off and the GATE pin ramps further. At time point 9,
the SENSE voltage drops below VCB, the fault TIMER cycle
ends, followed by a 5.8µA discharge cycle (cool off). The
durationbetweentimepoints7and9mustbeshorterthan
one circuit breaker delay to avoid a fault time out during
GATEramp-up.WhenGATErampspasttheVGATEH thresh-
old at time point 10, PWRGD pulls low. At time point 11,
GATE reaches its maximum voltage as determined by VIN.
Live Insertion with Short Pin Control of UV/OV
In the example shown in Figure 9, power is delivered
through long connector pins whereas the UV/OV divider
makescontactthroughashortpin.Thisensuresthepower
connections are firmly established before the LTC4252 is
activated.Attimepoint1,thepowerpinsmakecontactand
425212f
20
LTC4252-1/LTC4252-2
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UV CLEARS V
, CHECK OV < V
, GATE < V
, SENSE < V , SS < 20 • V AND TIMER < V
UVHI
OVHI
GATEL
CB
OS
TMRL
TIMER CLEARS V
, CHECK GATE < V
, SENSE < V AND SS < 20 • V
CB OS
TMRL
GATEL
1
2
3 4 56
7
8 9 1011
GND – V OR
EE
(–48RTN) – (–48V)
V
UVHI
V
UV/OV
V
IN
LKO
V
TMRH
230µA + 8 • I
DRN
5.8µA
TIMER
GATE
5.8µA
V
5.8µA
TMRL
58µA
V
– V
GATEH
IN
58µA
V
GATEL
20 • (V
20 • (V + V
+ V
)
)
ACL
OS
SS
CB
OS
OS
20 • V
V
V
ACL
CB
SENSE
V
OUT
V
V
DRNCL
DRNL
DRAIN
PWRGD
GATE
START-UP
INITIAL TIMING
4252-1/2 F09
Figure 9. Power-Up Timing with a Short Pin (All Waveforms are Referenced to VEE)
VIN rampsthroughVLKO.Attimepoint2,theUV/OVdivider
makes contact and its voltage exceeds VUVHI. In addition,
RSS • CSS; GATE is held low by the analog current limit
amplifier until SS crosses 20 • VOS. Upon releasing GATE,
58µAsourcesintotheexternalMOSFETgateandcompen-
sation network. When the GATE voltage reaches the
MOSFET’s threshold, current begins flowing into the load
capacitor at time point 5. At time point 6, load current
reaches the SS control level and the analog current limit
loop activates. Between time points 6 and 8, the GATE
voltage is servoed, the SENSE voltage is regulated at
the internal logic checks for OV < VOVHI, GATE < VGATEL
,
SENSE < VCB, SS < 20 • VOS and TIMER < VTMRL. If all
conditions are met, an initial timing cycle starts and the
TIMER capacitor is charged by a 5.8µA current source
pull-up. At time point 3, TIMER reaches the VTMRH thresh-
old and the initial timing cycle terminates. The TIMER
capacitor is quickly discharged. At time point 4, the VTMRL
threshold is reached and the conditions of GATE < VGATEL
,
VACL(t) and soft-start limits the slew rate of the load
SENSE < VCB and SS < 20 • VOS must be satisfied before
a GATE start-up cycle begins. SS ramps up as dictated by
current. If the SENSE voltage (VSENSE – VEE) reaches the
VCB threshold at time point 7, the circuit breaker TIMER
425212f
21
LTC4252-1/LTC4252-2
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activates.TheTIMERcapacitor,CT,ischargedbya(230µA
+ 8 • IDRN) current pull-up. As the load capacitor nears full
charge, load current begins to decline. At point 8, the load
current falls and the SENSE voltage drops below VACL(t).
The analog current limit loop shuts off and the GATE pin
ramps further. At time point 9, the SENSE voltage drops
below VCB and the fault TIMER cycle ends, followed by a
5.8µA discharge cycle (cool off). When GATE ramps past
VGATEH threshold at time point 10, PWRGD pulls low. At
time point 11, GATE reaches its maximum voltage as
determined by VIN.
When UV recovers and clears VUVHI (time point 2), an
initial timer cycle begins followed by a start-up cycle.
VIN Undervoltage Lockout Timing
The VIN undervoltage lockout comparator, UVLO, has a
similartimingbehaviorastheUVpintimingexceptitlooks
for VIN < (VLKO – VLKH) to shut down and VIN > VLKO to
start. In an undervoltage lockout condition, both UV and
OV comparators are held off. When VIN exits undervoltage
lockout, the UV and OV comparators are enabled.
Undervoltage Timing with Overvoltage Glitch
Undervoltage Timing
In Figure 11, both UV and OV pins are connected together.
WhenUVclearsVUVHI (timepoint1), aninitialtimingcycle
starts. If the system bus voltage overshoots VOVHI as
shown at time point 2, TIMER discharges. At time point 3,
the supply voltage recovers and drops below the VOVLO
In Figure 10 when UV pin drops below VUVLO (time
point 1), the LTC4252 shuts down with TIMER, SS and
GATE all pulling low. If current has been flowing, the
SENSE pin voltage decreases to zero as GATE collapses.
UV DROPS BELOW V . GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES
UVLO
UV CLEARS V
, CHECK OV CONDITION, GATE < V
, SENSE < V , SS < 20 • V AND TIMER < V
UVHI
GATEL
CB
OS
TMRL
TIMER CLEARS V , CHECK GATE < V , SENSE < V AND SS < 20 • V
TMRL GATEL CB OS
1
2
3 4 56
7
8 910 11
V
UVHI
UVLO
UV
V
V
TMRH
230µA + 8 • I
DRN
5.8µA
TIMER
5.8µA
V
TMRL
5.8µA
58µA
V
IN
– V
GATEH
GATE
58µA
V
GATEL
20 • (V
20 • (V + V
+ V
)
)
ACL
OS
CB
OS
OS
SS
20 • V
V
V
ACL
SENSE
CB
V
V
DRNCL
DRAIN
DRNL
PWRGD
GATE
START-UP
INITIAL TIMING
4252-1/2 F10
Figure 10. Undervoltage Timing (All Waveforms are Referenced to VEE)
425212f
22
LTC4252-1/LTC4252-2
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UV/OV CLEARS V
, CHECK OV CONDITION, GATE < V
, SENSE < V , SS < 20 • V AND TIMER < V
GATEL CB OS TMRL
UVHI
UV/OV OVERSHOOTS V
AND TIMER ABORTS INITIAL TIMING CYCLE
OVHI
UV/OV DROPS BELOW V
AND TIMER RESTARTS INITIAL TIMING CYCLE
OVLO
TIMER CLEARS V
, CHECK GATE < V
, SENSE < V AND SS < 20 • V
TMRL
GATEL
CB
OS
10 12
9 11
1
2
3
4 5 67
8
V
OVHI
V
OVLO
UV/OV
V
UVHI
V
TMRH
230µA + 8 • I
DRN
5.8µA
TIMER
GATE
5.8µA
V
TMRL
5.8µA
58µA
V
IN
– V
GATEH
58µA
V
GATEL
20 • (V
20 • (V + V
+ V
)
)
ACL
OS
SS
CB
OS
OS
20 • V
V
V
ACL
SENSE
DRAIN
CB
V
V
DRNCL
DRNL
PWRGD
GATE
START-UP
INITIAL TIMING
4252-1/2 F11
Figure 11. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to VEE)
threshold. The initial timing cycle restarts, followed by a
GATE start-up cycle.
Circuit Breaker Timing
In Figure 13a, the TIMER capacitor charges at 230µA if the
SENSE pin exceeds VCB but VDRN is less than 6.15V. If the
SENSE pin drops below VCB before TIMER reaches the
Overvoltage Timing
During normal operation, if the OV pin exceeds VOVHI as
shownattimepoint1ofFigure12, theTIMERandPWRGD
status are unaffected. Nevertheless, SS and GATE pull
down and the load is disconnected. At time point 2, OV
recovers and drops below the VOVLO threshold. A GATE
start-up cycle begins. If the overvoltage glitch is long
enough to deplete the load capacitor, a full start-up cycle
as shown between time points 4 through 7 may occur.
V
TMRH threshold, TIMERisdischargedby5.8µA. InFigure
13b, when TIMER exceeds VTMRH, GATE pulls down
immediately and the LTC4252 shuts down. In Figure 13c,
multiple momentary faults cause the TIMER capacitor to
integrate and reach VTMRH. GATE pull down follows and
theLTC4252shutsdown.Duringshutdown,theLTC4252-1
latches TIMER high with a 5.8µA pull-up current source;
the LTC4252-2 activates a shutdown cooling cycle.
425212f
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OV OVERSHOOTS V
. GATE AND SS ARE PULLED DOWN, PWRGD AND TIMER ARE UNAFFECTED
OVHI
OV DROPS BELOW V
, CHECK GATE < V
, SENSE < V AND SS < 20 • V
CB
OVLO
GATEL
OS
1
2 34
5
67 8 9
V
OVHI
OV
V
OVLO
V
TMRH
5.8µA
230µA + 8 • I
TIMER
GATE
DRN
5.8µA
58µA
V
IN
– V
GATEH
58µA
V
GATEL
20 • (V
+ V
OS
)
ACL
20 • (V + V
CB OS
)
SS
20 • V
OS
V
V
ACL
SENSE
CB
GATE
START-UP
4252-1/2 F12
Figure 12. Overvoltage Timing (All Waveforms are Referenced to VEE)
CB TIMES OUT
CB TIMES OUT
1
2
1
2
1
2
3
4
V
V
V
TMRH
TMRH
TMRH
5.8µA
5.8µA
230µA + 8 • I
230µA + 8 • I
DRN
TIMER
TIMER
GATE
SS
TIMER
GATE
SS
230µA + 8 • I
DRN
230µA + 8 • I
DRN
DRN
GATE
SS
V
V
V
V
V
V
ACL
ACL
ACL
CB
CB
CB
SENSE
SENSE
SENSE
V
V
OUT
V
OUT
OUT
V
V
DRNCL
DRNCL
DRAIN
DRAIN
DRAIN
PWRGD
PWRGD
PWRGD
CB FAULT
CB FAULT
CB FAULT
CB FAULT
4252-1/2 F13
(13a) Momentary Circuit-Breaker Fault
(13b) Circuit-Breaker Time Out
(13c) Multiple Circuit-Breaker Fault
Figure 13. Circuit-Breaker Timing Behavior (All Waveforms are Referenced to VEE)
425212f
24
LTC4252-1/LTC4252-2
U
W U U
APPLICATIO S I FOR ATIO
Resetting a Fault Latch (LTC4252-1)
The duration of the TIMER reset pulse should be smaller
than the time taken to reach 0.2V at SS pin. With a single
pole mechanical pushbutton switch, this may not be
feasible. A double pole, single throw pushbutton switch
removes this restriction by connecting the second switch
to the SS pin. With this method, both the SS and TIMER
pins are released at the same time (see Figure 19).
The latched circuit breaker fault of LTC4252-1 benefits
from long cooling time. It is reset by pulling the UV pin
below VUVLO with a switch. Reset is also accomplished by
pulling the VIN pin momentarily below (VLKO – VLKH). A
third reset method involves pulling the TIMER pin below
VTMRL as shown in Figure 14. An initial timing cycle is
skipped if TIMER is used for reset. An initial timing cycle
is generated if reset by the UV pin or the VIN pin.
SWITCH RESETS LATCHED TIMER
SWITCH RELEASES SS
1
2 34
5
67 8 9
5.8µA
TIMER
V
V
TMRH
230µA + 8 • I
5.8µA
DRN
5.8µA
TMRL
58µA
V
– V
GATEH
IN
GATE
SS
58µA
V
GATEL
20 • (V
+ V
)
)
ACL
OS
20 • (V + V
CB
OS
OS
20 • V
V
V
ACL
CB
SENSE
DRAIN
V
V
DRNCL
DRNL
PWRGD
GATE START-UP
MOMENTARY DPST SWITCH RESET
4252-1/2 F14
Figure 14. Pushbutton Reset of LTC4252-1’s Latched Fault (All Waveforms are Referenced to VEE)
425212f
25
LTC4252-1/LTC4252-2
U
W U U
APPLICATIO S I FOR ATIO
Shutdown Cooling Cycle (LTC4252-2)
discharge phases and three 5.8µA charge phases in this
shutdown cooling cycle spanning time points 2 and 3. At
time point 3, the LTC4252 automatic retry occurs with a
start-up cycle. Good thermal management techniques are
highlyrecommended;powerandthermaldissipationmust
be carefully evaluated when implementing the automatic
retry scheme.
Figure 15 shows the timer behavior of the LTC4252-2. At
time point 2, TIMER exceeds VTMRH, GATE pulls down
immediately and the LTC4252 shuts down. TIMER starts
a shutdown cooling cycle by discharging TIMER with
5.8µA to the VTMRL threshold. TIMER then charges with
5.8µA to the VTMRH threshold. There are four 5.8µA
CIRCUIT BREAKER TIMES OUT
RETRY
1
2
3 45
6
78 9 10
V
230µA + 8 • I
TMRH
230µA + 8 • I
DRN
5.8µA
5.8µA
5.8µA
DRN
5.8µA
5.8µA
5.8µA
5.8µA
5.8µA
TIMER
5.8µA
V
TMRL
58µA
V
– V
GATEH
IN
58µA
GATE
SS
V
GATEL
20 • (V
+ V
)
)
ACL
OS
20 • (V + V
CB
OS
OS
20 • V
V
V
ACL
CB
SENSE
V
OUT
V
V
DRNCL
DRNL
DRAIN
PWRGD
GATE
START-UP
4252-1/2 F15
SHUTDOWN COOLING
CB
Figure 15. Shutdown Cooling Timing Behavior of LTC4252-2 (All Waveforms are Referenced to VEE)
425212f
26
LTC4252-1/LTC4252-2
U
W
U U
APPLICATIO S I FOR ATIO
Analog Current Limit and Fast Current Limit
causes VOUT to exceed VDRNCL, the DRAIN pin is clamped
at VDRNCL. IDRN flows into the DRAIN pin and is multiplied
by 8. This extra current is added to the TIMER pull-up
current of 230µA. This accelerated TIMER current of
[230µA+8 • IDRN] produces a shorter circuit breaker fault
delay. Careful selection of CT, RD and MOSFET can help
prevent SOA damage in a low impedance fault condition.
In Figure 16a, when SENSE exceeds VACL, GATE is regu-
lated by the analog current limit amplifier loop. When
SENSE drops below VACL, GATE is allowed to pull up. In
Figure 16b, when a severe fault occurs, SENSE exceeds
VFCL and GATE immediately pulls down until the analog
current amplifier can establish control. If the severe fault
CB TIMES OUT
12
34
1
2
V
TMRH
V
TMRH
230µA + 8 • I
230µA + 8 • I
DRN
DRN
5.8µA
TIMER
TIMER
5.8µA
GATE
SS
GATE
SS
V
V
ACL
V
FCL
SENSE
SENSE
V
ACL
CB
V
CB
V
OUT
V
OUT
V
DRNCL
DRAIN
DRAIN
PWRGD
PWRGD
4252-1/2 F16
(16a) Analog Current Limit Fault
(16b) Fast Current Limit Fault
Figure 16. Current Limit Behavior (All Waveforms are Referenced to VEE)
425212f
27
LTC4252-1/LTC4252-2
U
W U U
APPLICATIO S I FOR ATIO
Soft-Start
control value of VACL(t) (Equation 7). At time point 6, the
GATE voltage is controlled by the current limit amplifier.
The soft-start control voltage reaches the circuit breaker
voltage, VCB, at time point 7 and the circuit breaker TIMER
activates. As the load capacitor nears full charge, load
current begins to decline below VACL(t). The current limit
loop shuts off and GATE releases at time point 8. At time
point 9, the SENSE voltage falls below VCB and TIMER
deactivates.
If the SS pin is not connected, this pin defaults to a linear
voltage ramp, from 0V to 2.2V in about 220µs at GATE
start-up, as shown in Figure 17a. If a soft-start capacitor,
CSS, is connected to this SS pin, the soft-start response is
modified from a linear ramp to an RC response (Equa-
tion 6), as shown in Figure 17b. This feature allows load
current to slowly ramp-up at GATE start-up. Soft-start is
initiated at time point 3 by a TIMER transition from VTMRH
to VTMRL (time points 1 to 2) or by the OV pin falling below
the VOVLO threshold after an OV condition. When the SS
pin is below 0.2V, the analog current limit amplifier holds
GATE low. Above 0.2V, GATE is released and 58µA ramps
up the compensation network and GATE capacitance at
time point 4. Meanwhile, the SS pin voltage continues to
ramp up. When GATE reaches the MOSFET’s threshold,
the MOSFET begins to conduct. Due to the MOSFET’s high
gm, the MOSFET current quickly reaches the soft-start
Large values of CSS can cause premature circuit breaker
time out as VACL(t) may exceed the VCB potential during
the circuit breaker delay. The load capacitor is unable to
achieve full charge in one GATE start-up cycle. A more
serioussideeffectoflargeCSS valuesisSOAdurationmay
be exceeded during soft-start into a low impedance load.
A soft-start voltage below VCB will not activate the circuit
breaker TIMER.
END OF INTIAL TIMING CYCLE
END OF INTIAL TIMING CYCLE
12 34 567
7a
8 9 10 11
12 3 4 5 6
7
8 9 10 11
V
V
TMRH
TMRH
5.8µA
5.8µA
230µA + 8 • I
230µA + 8 • I
DRN
DRN
TIMER
GATE
TIMER
GATE
V
V
TMRL
TMRL
58µA
58µA
V
– V
V
– V
GATEH
IN
GATEH
IN
V
V
GS(th)
GS(th)
58µA
+ V
58µA
20 • (V
20 • (V
SS
)
+ V
)
OS
ACL
OS
ACL
20 • (V + V
)
OS
20 • (V + V
CB
)
SS
CB
OS
20 • V
20 • V
OS
OS
V
V
V
ACL
CB
ACL
SENSE
SENSE
V
CB
V
V
DRNCL
DRNCL
V
DRNL
V
DRNL
DRAIN
DRAIN
PWRGD
PWRGD
4252-1/2 F17
(17a) Without External CSS
(17b) With External CSS
Figure 17. Soft-Start Timing (All Waveforms are Referenced to VEE)
425212f
28
LTC4252-1/LTC4252-2
U
W U U
APPLICATIO S I FOR ATIO
Power Limit Circuit Breaker
when
SUPPLY = 0.5 • (VSUPPLY(MIN) + VSUPPLY(MAX)) = 54V.
Figure 18 shows the LTC4252-2 in a power limit circuit
breaking application. The SENSE pin is modulated by the
boardsupplyvoltage, VSUPPLY. Thezenervoltage, VZ isset
to be the same as the low supply operating voltage,
VSUPPLY(MIN) = 36V. If the goal is to have the high supply
operating voltage, VSUPPLY(MAX) = 72V give the same
power at VSUPPLY(MIN), then resistors R4 and R6 are
selected using the ratio:
V
The peak power at the fault current limit occurs at the
supply overvoltage threshold. The fault current limited
power is:
POWERFAULT
VSUPPLY
=
R6
R4
(18)
• VACL – V
– V •
Z
(
)
SUPPLY
RS
R6
VCB
=
(16)
R4 VSUPPLY(MAX)
If R6 is 22Ω, R4 is 31.6k. The peak circuit breaker power
limit is:
2
V
SUPPLY(MIN) + VSUPPLY(MAX)
(
=
)
POWERMAX
4 •VSUPPLY(MIN) •VSUPPLY(MAX)
•POWERSUPPLY(MIN)
(17)
= 1.125•POWERSUPPLY(MIN)
GND
+
R
IN
R4
31.6k
C
L
100µF
3× 1.8k
1/4W EACH
C
R5
5.6k
IN
LOAD
EN
GND
1
1µF
(SHORT PIN)
R1
V
IN
D1
432k
V
LTC4252-1
PWRGD
BZX84C36
OUT
*
1%
9
8
2
7
6
4
UV
R
1M
D
R2
14k
1%
OV
DRAIN
GATE
10
3
Q1
IRF530S
TIMER
SS
R6 22Ω
C
SS
R3
32.4k
1%
SENSE
V
EE
0.33µF
R
R
S
0.02Ω
C
5
C1
10nF
C
T
68nF
10Ω
C
C
18nF
4252-1/2 F18
–48V
* M0C207
Figure 18. Power Limit Circuit Breaking Application
425212f
29
LTC4252-1/LTC4252-2
U
PACKAGE DESCRIPTIO
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.52
(.206)
REF
0.65
(.0256)
BSC
0.42 ± 0.04
(.0165 ± .0015)
TYP
8
7 6 5
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.88 ± 0.1
(.192 ± .004)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
0.53 ± 0.015
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.077)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
0.13 ± 0.05
(.005 ± .002)
0.65
(.0256)
BCS
MSOP (MS8) 1001
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
425212f
30
LTC4252-1/LTC4252-2
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
0.50
0.305 ± 0.038
(.0120 ± .0015)
TYP
(.0197)
10 9
8
7 6
BSC
REF
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.88 ± 0.10
(.192 ± .004)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4 5
0.53 ± 0.01
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
0.13 ± 0.05
(.005 ± .002)
MSOP (MS) 0402
0.50
(.0197)
TYP
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
425212f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
31
LTC4252-1/LTC4252-2
U
TYPICAL APPLICATIO
GND
R
IN
+
C
L
2× 5.1k IN SERIES
LOAD
100µF
1/4W EACH
GND
1
C
IN
(SHORT PIN)
R1
V
OUT
1µF
V
IN
R
402k
1%
D
LTC4252-1
1M
7
8
2
6
5
3
UV/OV
TIMER
SS
DRAIN
GATE
R2
Q1
IRF540S
32.4k
C
1%
T
SENSE
V
EE
150nF
R
R
S
0.01Ω
R3
22Ω
C
4
C1
10nF
C
10Ω
SS
PUSH
RESET
27nF
C
C
22nF
4252-1/2 F19
–48V
Figure 19. –48V/5A Application
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1640AH/LT1640AL Negative High Voltage Hot Swap Controllers in SO-8
Negative High Voltage Supplies from –10V to –80V
Supplies from 9V to 80V, Latched Off/Autoretry
3V to 16.5V, Overvoltage Protection up to 33V
Active Current Limiting, Supplies from –20V to –80V
Fast Active Current Limiting, Supplies from –15V
LT1641-1/LT1641-2
LTC1642
Positive High Voltage Hot Swap Controllers in SO-8
Fault Protected Hot Swap Controller
LT4250
–48V Hot Swap Controller in SO-8
LTC4251/LTC4251-1
LTC4253
–48V Hot Swap Controllers in SOT-23
–48V Hot Swap Controller with Sequencer
Fast Current Limiting with Three Sequenced Power Good Outputs,
Supplies from –15V
425212f
LT/TP 0702 2K PRINTED IN USA
32 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
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