LTC4252-1_12 [Linear]
Negative Voltage Hot Swap Controllers; 负电压热插拔控制器型号: | LTC4252-1_12 |
厂家: | Linear |
描述: | Negative Voltage Hot Swap Controllers |
文件: | 总36页 (文件大小:310K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
Negative Voltage
Hot Swap Controllers
NOT RECOMMENDED FOR NEW DESIGNS
Please See LTC4252B/LTC4252C for Drop-In Replacement
FEATURES
DESCRIPTION
The LTC®4252 negative voltage Hot SwapTM controller
allows a board to be safely inserted and removed from a
livebackplane.Outputcurrentiscontrolledbythreestages
of current limiting: a timed circuit breaker, active current
limitingandafastfeedforwardpaththatlimitspeakcurrent
under worst-case catastrophic fault conditions.
n
Allows Safe Board Insertion and Removal from a
Live –48V Backplane
n
Floating Topology Permits Very High Voltage Operation
n
Programmable Analog Current Limit With Circuit
Breaker Timer
n
Fast Response Time Limits Peak Fault Current
n
Programmable Soft-Start Current Limit
Adjustable undervoltage and overvoltage detectors dis-
connect the load whenever the input supply exceeds the
desired operating range. The LTC4252’s supply input is
shunt regulated, allowing safe operation with very high
supply voltages. A multifunction timer delays initial start-
up and controls the circuit breaker’s response time. The
circuit breaker’s response time is accelerated by sensing
excessive MOSFET drain voltage, keeping the MOSFET
within its safe operating area (SOA). An adjustable soft-
start circuit controls MOSFET inrush current at start-up.
n
Programmable Timer with Drain Voltage
Accelerated Response
n
±±1 Undervoltage/Overvoltage Threshold Accuracy
(LTC4252A)
■
Adjustable Undervoltage/Overvoltage Protection
■
LTC4252-1/LTC4252A-1: Latch Off After Fault
■
LTC4252-2: Automatic Retry After Fault
■
Available in 8-Pin and 10-Pin MSOP Packages
APPLICATIONS
TheLTC4252-1/LTC4252A-1latchoffafteracircuitbreaker
fault times out. The LTC4252-2 provides automatic retry
after a fault. The LTC4252A-1/LTC4252A-2 feature tight
1ꢀ undervoltage/overvoltage threshold accuracy. The
LTC4252 is available in either an 8-pin or 10-pin MSOP.
n
Hot Board Insertion
n
Electronic Circuit Breaker
n
–48V Distributed Power Systems
n
Negative Power Supply Control
n
Central Office Switching
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
n
High Availability Servers
n
ATCA
TYPICAL APPLICATION
–48V/2.5A Hot Swap Controller
–48RTN
Start-Up Behavior
R
+
IN
C
GATE
L
3× 1.8k IN SERIES
1/4W EACH
100μF
LOAD
EN
5V/DIV
†
C
R3
1μF 5.1k
IN
D
IN
–48RTN
(SHORT PIN)
**
DDZ13B
V
R1
IN
LTC4252-1
PWRGD
SENSE
2.5A/DIV
402k
1ꢀ
V
OUT
*
OV
R
D
1M
UV
DRAIN
GATE
V
R2
32.4k
1ꢀ
OUT
Q1
IRF530S
TIMER
SS
20V/DIV
C
T
0.33μF
SENSE
V
EE
R
R
C
S
C1
10nF
C
10Ω
C
0.02Ω
SS
68nF
C
18nF
PWRGD
10V/DIV
425212 TA01
–48V
1ms/DIV
425212 TA01a
†
* M0C207
**DIODES, INC
RECOMMENDED FOR HARSH ENVIRONMENTS
425212fd
1
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
ABSOLUTE MAXIMUM RATINGS
All Voltages Referred to VEE (Note ±)
Current into V (100μs Pulse) .............................100mA
IN
Input/Output Pins
(Except SENSE and DRAIN) Voltage .......... –0.3V to 16V
SENSE Pin Voltage.................................... –0.6V to 16V
Current Out of SENSE Pin (20μs Pulse) .......... –200mA
Current into DRAIN Pin (100μs Pulse) ...................20mA
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
IN
V , DRAIN Pin Minimum Voltage........................ –0.3V
LTC4252-1C/LTC4252-2C
LTC4252A-1C/LTC4252A-2C.................... 0°C to 70°C
LTC4252-1I/LTC4252-2I
LTC4252A-1I/LTC4252A-2I ................. –40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
V
1
2
3
4
5
10 TIMER
IN
V
SS
SENSE
1
2
3
4
8 TIMER
7 UV/OV
6 DRAIN
5 GATE
IN
PWRGD
SS
9
8
7
6
UV
OV
DRAIN
GATE
SENSE
V
EE
V
EE
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS PACKAGE
10-LEAD PLASTIC MSOP
T
= 125°C, θ = 160°C/W
JA
JMAX
T
= 125°C, θ = 160°C/W
JMAX
JA
ORDER INFORMATION
LEAD FREE FINISH
LTC4252-1CMS8
LTC4252-2CMS8
LTC4252-1IMS8
LTC4252-2IMS8
LEAD BASED FINISH
LTC4252-1CMS
LTC4252-2CMS
LTC4252A-1CMS
LTC4252A-2CMS
LTC4252-1IMS
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
PACKAGE DESCRIPTION
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
TEMPERATURE RANGE
0°C to 70°C
LTC4252-1CMS8#TRPBF LTWM
LTC4252-2CMS8#TRPBF LTWP
LTC4252-1IMS8#TRPBF LTRQ
LTC4252-2IMS8#TRPBF LTRR
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
TEMPERATURE RANGE
0°C to 70°C
TAPE AND REEL
PART MARKING
LTC4252-1CMS#TR
LTC4252-2CMS#TR
LTC4252A-1CMS#TR
LTC4252A-2CMS#TR
LTC4252-1IMS#TR
LTC4252-2IMS#TR
LTC4252A-1IMS#TR
LTC4252A-2IMS#TR
LTWN
LTWQ
LTAFX
LTAGE
LTRS
0°C to 70°C
0°C to 70°C
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
LTC4252-2IMS
LTRT
LTC4252A-1IMS
LTC4252A-2IMS
LTAFY
LTAGF
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
425212fd
2
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
LTC4252-±/-2
LTC4252A-±/-2
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
13
5
MAX
MIN
TYP
13
5
MAX UNITS
l
V
V
V
V
V
V
– V Zener Voltage
I
IN
I
IN
= 2mA
11.5
14.5
11.5
14.5
V
Ω
Z
IN
IN
IN
IN
IN
EE
r
Z
– V Zener Dynamic Impedance
= 2mA to 30mA
EE
●
●
I
Supply Current
UV = OV = 4V, V = (V – 0.3V)
0.8
9.2
1
2
0.9
9
2
mA
V
IN
IN
Z
V
V
V
V
Undervoltage Lockout
Undervoltage Lockout Hysteresis
Coming Out of UVLO (Rising V )
11.5
10
LKO
LKH
CB
IN
0.5
50
V
●
●
Circuit Breaker Current Limit Voltage
Analog Current Limit Voltage
V
V
= (V
– V )
EE
40
80
50
100
60
45
55
mV
mV
CB
SENSE
= (V
– V ),
120
ACL
ACL
SENSE
EE
SS = Open or 2.2V
●
●
V
V
/
Analog Current Limit Voltage/
Circuit Breaker Voltage
V
= (V
– V ),
1.05
150
1.20
1.38
300
V/V
ACL
CB
ACL
SENSE
EE
SS = Open or 1.4V
= (V – V )
EE
V
FCL
V
SS
Fast Current Limit Voltage
SS Voltage
V
FCL
150
200
2.2
100
22
300
200
1.4
50
mV
V
SENSE
After End of SS Timing Cycle
R
SS Output Impedance
SS Pin Current
kΩ
μA
SS
I
UV = OV = 4V, V
= V
= V
,
,
28
SS
SENSE
EE
V
= 0V (Sourcing)
SS
UV = OV = 0V, V
28
28
mA
SENSE
EE
V
= 2V (Sinking)
SS
V
Analog Current Limit Offset Voltage
10
10
mV
V/V
OS
V
V
+V
/
Ratio (V
+ V ) to SS Voltage
0.05
0.05
ACL OS
SS
ACL
OS
●
I
GATE Pin Output Current
UV = OV = 4V, V
GATE
= V
,
40
10
58
17
80
40
10
58
17
80
μA
mA
mA
GATE
SENSE
EE
V
= 0V (Sourcing)
UV = OV = 4V, V
GATE
– V = 0.15V,
EE
SENSE
V
= 3V (Sinking)
UV = OV = 4V, V
– V = 0.3V,
190
190
SENSE
EE
V
V
V
= 1V (Sinking)
GATE
GATE
GATEH
●
V
V
External MOSFET Gate Drive
Gate High Threshold
– V , I = 2mA
12
V
12
V
Z
V
V
GATE
EE IN
Z
= V – V , I = 2mA,
GATE IN
2.8
2.8
GATEH
IN
for PWRGD Status (MS Only)
V
V
V
V
V
V
V
V
V
Gate Low Threshold
(Before Gate Ramp-Up)
0.5
0.5
V
V
GATEL
UVHI
UVLO
UV
●
●
●
●
●
●
●
●
●
●
UV Pin Threshold HIGH
UV Pin Threshold LOW
UV Pin Threshold
3.075 3.225 3.375
2.775 2.925 3.075
V
Low-to-High Transition
3.05
292
3.08
324
3.11
356
V
UV Pin Hysteresis
(●
for LTC4252A Only)
300
mV
V
UVHST
OVHI
OVLO
OV
OV Pin Threshold HIGH
OV Pin Threshold LOW
OV Pin Threshold
5.85
5.25
6.15
5.55
6.45
5.85
V
Low-to-High Transition
for LTC4252A Only)
5.04
82
5.09
102
–15
0.1
4
5.14
122
–30
1
V
OV Pin Hysteresis
(●
600
–15
0.1
4
mV
μA
μA
V
OVHST
SENSE
INP
I
I
SENSE Pin Input Current
UV, OV Pin Input Current
TIMER Pin Voltage High Threshold
TIMER Pin Voltage Low Threshold
UV = OV = 4V, V
UV = OV = 4V
= 50mV
–30
1
SENSE
V
V
TMRH
TMRL
1
1
V
425212fd
3
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
LTC4252-±/-2
LTC4252A-±/-2
SYMBOL PARAMETER
TIMER Pin Current
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX UNITS
I
Timer On (Initial Cycle/Latchoff/
Shutdown Cooling, Sourcing),
5.8
5.8
μA
TMR
V
TMR
= 2V
Timer Off (Initial Cycle, Sinking),
= 2V
28
230
630
5.8
28
230
630
5.8
mA
μA
μA
μA
V
TMR
Timer On (Circuit Breaker, Sourcing,
= 0μA), V = 2V
I
DRN
TMR
Timer On (Circuit Breaker, Sourcing,
= 50μA), V = 2V
I
DRN
TMR
Timer Off (Circuit Breaker/
Shutdown Cooling, Sinking),
V
= 2V
TMR
ΔI
TMRACC
ΔI
DRN
/
[(I
at I
DRN
= 50μA) – (I
at I =
DRN
Timer On (Circuit Breaker with
I = 50μA)
DRN
8
8
μA/μA
TMR
DRN
TMR
0μA)]/ΔI
V
DRAIN Pin Voltage Low Threshold
DRAIN Leakage Current
For PWRGD Status (MS Only)
= 5V (4V for LTC4252A)
2.385
0.1
7
2.385
0.1
6
V
μA
V
DRNL
DRNL
I
V
DRAIN
1
1
V
V
DRAIN Pin Clamp Voltage
PWRGD Output Low Voltage
I
= 50μA
DRNCL
DRN
●
●
I
PG
I
PG
= 1.6mA (MS Only)
= 5mA (MS Only)
0.2
0.4
1.1
0.2
0.4
1.1
V
V
PGL
●
I
t
PWRGD Pull-Up Current
V
= 0V (Sourcing) (MS Only)
40
58
80
40
58
80
μA
μs
PGH
PWRGD
SS Default Ramp Period
SS Pin Floating, V Ramps from
0.2V to 2V
180
SS
SS
SS Pin Floating, V Ramps from
230
μs
SS
0.1V to 0.9V
t
t
UV Low to Gate Low
OV High to Gate Low
0.4
0.4
0.4
0.4
μs
μs
PLLUG
PHLOG
Note ±: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to V unless otherwise
EE
specified.
425212fd
4
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
TYPICAL PERFORMANCE CHARACTERISTICS
VZ vs Temperature
rZ vs Temperature
IIN vs Temperature
14.5
14.0
13.5
13.0
12.5
12.0
10
9
2000
1800
1600
1400
1200
1000
800
I
= 2mA
I
= 2mA
V
= (V – 0.3V)
IN Z
IN
IN
8
7
6
5
600
4
400
3
200
2
0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425212 G04
425212 G03
425212 G01
Undervoltage Lockout VLKO
vs Temperature
Undervoltage Lockout Hysteresis
VLKH vs Temperature
IIN vs VIN
1000
100
10
12.0
11.5
11.0
10.5
10.0
9.5
1.5
1.3
T
= –40°C
A
T
= 25°C
A
1.1
T
= 85°C
A
0.9
0.7
0.5
T
= 125°C
A
1
9.0
8.5
0.1
8.0
0
2
4
6
8
10 12 14 16 18 20 22
(V)
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
45
95 105 125
25
65
V
TEMPERATURE (°C)
TEMPERATURE (°C)
IN
425212 G02
425212 G05
425212 G06
Circuit Breaker Current Limit
Voltage VCB vs Temperature
Analog Current Limit Voltage
VACL vs Temperature
Fast Current Limit Voltage VFCL
vs Temperature
60
120
115
110
105
100
95
300
275
250
225
200
175
150
58
56
54
52
50
48
46
44
42
40
90
85
80
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
45
85 105 125
–55 –35 –15
5
45
85 105 125
25
65
25
65
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425212 G07
425212 G08
425212 G09
425212fd
5
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
TYPICAL PERFORMANCE CHARACTERISTICS
VSS vs Temperature
RSS vs Temperature
ISS (Sinking) vs Temperature
45
40
35
30
25
20
15
10
5
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05
2.00
110
108
106
104
102
100
98
UV = OV = V
= V
EE
SENSE
I
= 2mA
IN
V
= 2V
SS
96
94
92
0
90
–55 –35 –15
5
25 45
125
65 85 105
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425212 G39
425212 G26
425212 G28
VOS vs Temperature
(VACL + VOS)/VSS vs Temperature
IGATE (Sourcing) vs Temperature
70
11.0
10.8
10.6
10.4
10.2
10.0
9.8
0.060
0.058
0.056
0.054
0.052
0.050
0.048
0.046
0.044
0.042
0.040
UV/0V = 4V
TIMER = 0V
V
V
= V
65
60
55
50
45
40
SENSE
GATE
EE
= 0V
9.6
9.4
9.2
9.0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425212 G10
425212 G29
425212 G30
IGATE (ACL, Sinking)
vs Temperature
IGATE (FCL, Sinking)
vs Temperature
VGATE vs Temperature
30
25
20
15
10
5
400
350
300
250
200
150
100
50
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
UV/0V = 4V
TIMER = 0V
UV/0V = 4V
TIMER = 0V
UV/0V = 4V
TIMER = 0V
V
V
– V = 0.15V
V
V
– V = 0.3V
V
= V
SENSE
GATE
EE
SENSE EE
= 1V
GATE
SENSE
EE
= 3V
0
0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
85
105 125
–55 –35 –15
5
25 45 65
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425212 G11
425212 G12
425212 G13
425212fd
6
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
TYPICAL PERFORMANCE CHARACTERISTICS
VGATEH vs Temperature
VGATEL vs Temperature
UV Threshold vs Temperature
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.375
3.275
3.175
3.075
2.975
2.875
2.775
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
UV/0V = 4V
TIMER = 0V
GATE THRESHOLD
BEFORE RAMP-UP
V
IN
= V – V
,
GATE
GATEH
IN
I
= 2mA
(MS ONLY)
V
UVH
V
UV
V
UVL
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425212 G14
425212 G15
425212 G31
OV Threshold vs Temperature
ISENSE vs Temperature
ISENSE vs (VSENSE – VEE)
6.45
6.25
6.05
5.85
5.65
5.45
5.25
5.05
4.85
–10
–12
–14
–16
–18
–20
–22
–24
–26
–28
–30
0.01
0.1
V
OVH
1.0
V
OVL
10
UV/0V = 4V
TIMER = 0V
GATE = HIGH
UV/0V = 4V
V
100
OV
TIMER = 0V
GATE = HIGH
V
– V = 50mV
EE
T = 25°C
SENSE
A
1000
–1.5 –1.0 –0.5
(V
0
0.5 1.0 1.5
– V ) (V)
2.0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
SENSE
EE
425212 G18
425212 G16
425212 G17
TIMER Threshold
vs Temperature
ITMR (Initial Cycle, Sourcing)
ITMR (Initial Cycle, Sinking)
vs Temperature
vs Temperature
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
9
8
7
6
5
4
3
2
1
0
50
45
40
35
30
25
20
15
10
TIMER = 2V
TIMER = 2V
V
TMRH
V
TMRL
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425212 G19
425212 G20
425212 G21
425212fd
7
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
TYPICAL PERFORMANCE CHARACTERISTICS
ITMR (Circuit Breaker, Sourcing)
vs Temperature
ITMR (Circuit Breaker, IDRN = 50μA,
Sourcing) vs Temperature
ITMR (Cooling Cycle, Sinking)
vs Temperature
690
670
650
630
610
590
570
550
10
9
8
7
6
5
4
3
2
1
0
280
260
240
220
200
180
TIMER = 2V
TIMER = 2V
TIMER = 2V
I
= 50μA
I
= 0μA
DRN
DRN
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
425212 G22
425212 G32
425212 G23
ITMR vs IDRN
∆ITMRACC/∆IDRN vs Temperature
IDRN vs VDRAIN
10
100
10
9.0
8.8
8.6
8.4
8.2
8.0
7.8
7.6
7.4
7.2
7.0
I
= 2mA
IN
TIMER ON
(CIRCUIT BREAKING,
I
= 50μA)
DRN
1
0.1
1
T
= 125°C
A
0.01
T
= 85°C
A
0.001
0.0001
0.00001
T
2
= 25°C
4
A
T
= –40°C
A
0.1
0
6
8
10 12 14 16
(V)
0.001
0.01
0.1
(mA)
1
10
–55 –35 –15
5
25 45 65 85 105 125
I
V
TEMPERATURE (°C)
DRN
DRAIN
425212 G33
425212 G25
425212 G34
VDRNL vs Temperature
VDRNCL vs Temperature
VPGL vs Temperature
2.60
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
8.0
7.8
7.6
7.4
7.2
7.0
6.8
6.6
6.4
6.2
6.0
3.0
2.5
2.0
1.5
1.0
0.5
0
I
= 50μA
DRN
(MS ONLY)
FOR PWRGD STATUS (MS ONLY)
I
= 10mA
PG
I
I
= 5mA
PG
PG
= 1.6mA
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425212 G35
425212 G36
425212 G37
425212fd
8
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
TYPICAL PERFORMANCE CHARACTERISTICS
tPLLUG and tPHLOG
vs Temperature
IPGH vs Temperature
tSS vs Temperature
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
62
61
60
59
58
57
56
55
220
210
200
190
180
170
160
150
SS PIN FLOATING,
V
= 0V
PWRGD
V
RAMPS FROM 0.2V TO 2V
(MS ONLY)
SS
t
PLLUG
t
PHLOG
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425212 G38
425212 G24
425212 G27
PIN FUNCTIONS (MS/MS8)
V
(Pin ±/Pin ±): Positive Supply Input. Connect this
GATE pin is held low until SS exceeds 20 • V = 0.2V.
OS
IN
pin to the positive side of the supply through a dropping
SS is internally shunted by a 100k resistor (R ) which
SS
resistor. A shunt regulator clamps V at 13V. An internal
limits the SS pin voltage to 2.2V (50k resistor and 1.4V
for the LTC4252A). This corresponds to an analog current
limitSENSEvoltageof100mV(60mVfortheLTC4252A).If
the SS capacitor is omitted, the SS pin ramps up in about
180μs. The SS pin is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
IN
undervoltage lockout (UVLO) circuit holds GATE low until
the V pin is greater than V , overriding UV and OV. If
IN
LKO
UV is high, OV is low and V comes out of UVLO, TIMER
IN
starts an initial timing cycle before initiating a GATE ramp-
up. If V drops below approximately 8.2V, GATE pulls low
IN
immediately.
PWRGD(Pin2/NotAvailable):PowerGoodStatusOutput
(MS only). At start-up, PWRGD latches low if DRAIN is
SENSE (Pin 4/Pin 3): Circuit Breaker/Current Limit Sense
below 2.385V and GATE is within 2.8V of V . PWRGD
Pin. Load current is monitored by a sense resistor R con-
IN
S
status is reset by UV, V (UVLO) or a circuit breaker fault
nected between SENSE and V , and controlled in three
EE
IN
timeout. This pin is internally pulled high by a 58μA cur-
steps. If SENSE exceeds V (50mV), the circuit breaker
CB
rent source.
comparator activates a (230μA + 8 • I ) TIMER pull-up
DRN
current. If SENSE exceeds V , the analog current limit
ACL
SS (Pin 3/Pin 2): Soft-Start Pin. This pin is used to ramp
inrush current during start up, thereby effecting control
over di/dt. A 20x attenuated version of the SS pin voltage
is presented to the current limit amplifier. This attenuated
voltagelimitstheMOSFET’sdraincurrentthroughthesense
resistorduringthesoft-startcurrentlimiting. Atthebegin-
amplifierpullsGATEdowntoregulatetheMOSFETcurrent
at V /R . In the event of a catastrophic short-circuit,
ACL
S
SENSE may overshoot. If SENSE reaches V (200mV),
FCL
the fast current limit comparator pulls GATE low with a
strong pull-down. To disable the circuit breaker and cur-
rent limit functions, connect SENSE to V .
EE
ning of a start-up cycle, the SS capacitor (C ) is ramped
by a 22μA (28μA for the LTC4252A) current source. The
SS
425212fd
9
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
PIN FUNCTIONS (MS/MS8)
V (Pin 5/Pin 4): Negative Supply Voltage Input. Connect
UV(Pin9/Pin7):UndervoltageInput.Theactivelowthresh-
old at the UV pin is set at 2.925V with 0.3V hysteresis. If
UV < 2.925V, PWRGD pulls high, both GATE and TIMER
pull low. If UV rises above 3.225V, this initiates an initial
timing cycle followed by GATE start-up. The LTC4252A
UV pin is set at 3.08V with 324mV hysteresis. If UV <
2.756V, PWRGD pulls high, both GATE and TIMER pull
low. If UV rises above 3.08V, this initiates an initial timing
EE
this pin to the negative side of the power supply.
GATE(Pin6/Pin5):N-ChannelMOSFETGateDriveOutput.
This pin is pulled high by a 58μA current source. GATE is
pulled low by invalid conditions at V (UVLO), UV, OV, or
IN
a circuit breaker fault timeout. GATE is actively servoed to
controlthefaultcurrentasmeasuredatSENSE.Acompen-
sationcapacitoratGATEstabilizesthisloop. Acomparator
monitors GATE to ensure that it is low before allowing an
initial timing cycle, GATE ramp-up after an overvoltage
event or restart after a current limit fault. During GATE
start-up, a second comparator detects if GATE is within
cycle followed by GATE start-up. The internal UVLO at V
IN
always overrides UV. A low at UV resets an internal fault
latch. A 1nF to 10nF capacitor at UV prevents transients
and switching noise from affecting the UV thresholds and
prevents glitches at the GATE pin.
2.8V of V before PWRGD is set (MS package only).
IN
TIMER (Pin ±0/Pin 8): Timer Input. TIMER is used to
generate an initial timing delay at start-up and to delay
shutdown in the event of an output overload (circuit
breaker fault). TIMER starts an initial timing cycle when
DRAIN (Pin 7/Pin 6): Drain Sense Input. Connecting an
external resistor, R , between this pin and the MOSFET’s
D
drain (V ) allows voltage sensing below 6.15V (5V for
OUT
LTC4252A) and current feedback to TIMER. A comparator
the following conditions are met: UV is high, OV is low, V
IN
detects if DRAIN is below 2.385V and together with the
clears UVLO, TIMER pin is low, GATE is lower than V
,
GATEL
GATE high comparator sets the PWRGD flag. If V
is
OUT
SS < 0.2V, and V
– V < V . A pull-up current of
SENSE
EE
CB
above V
, DRAIN clamps at approximately V
.
DRNCL
DRNCL
5.8μA then charges C , generating a time delay. If C
T
T
The current through R is internally multiplied by 8 and
D
chargestoV
(4V),thetimingcycleterminates,TIMER
TMRH
added to TIMER’s 230μA pullup current during a circuit
breakerfaultcycle.ThisreducesthefaulttimeandMOSFET
heating.
quickly pulls low and GATE is activated.
If SENSE exceeds 50mV while GATE is high, a circuit
breakercyclebeginswitha230μApull-upcurrentcharging
OV(Pin8/Pin7):OvervoltageInput.Theactivehighthresh-
old at the OV pin is set at 6.15V with 0.6V hysteresis. If OV
> 6.15V, GATE pulls low. When OV returns below 5.55V,
GATE start-up begins without an initial timing cycle. The
LTC4252A OV pin is set at 5.09V with 102mV hysteresis.
If OV > 5.09V, GATE pulls low. When OV returns below
4.988V, GATE start-up begins without an initial timing
cycle. If an overvoltage condition occurs in the middle of
an initial timing cycle, the initial timing cycle is restarted
after the overvoltage condition goes away. An overvoltage
conditiondoesnotresetthePWRGDflag.TheinternalUVLO
C . If DRAIN is approximately 7V (6V for LTC4252A) dur-
T
ing this cycle, the timer pull-up has an additional current
of 8 • I . If SENSE drops below 50mV before TIMER
DRN
reaches 4V, a 5.8μA pull-down current slowly discharges
the C . In the event that C eventually integrates up to the
T
T
V
threshold, the circuit breaker trips, GATE quickly
TMRH
pulls low and PWRGD pulls high. The LTC4252-1 TIMER
pin latches high with a 5.8μA pull-up source. This latched
faultisclearedbyeitherpullingTIMERlowwithanexternal
deviceorbypullingUVbelowV
.TheLTC4252-2starts
UVLO
a shutdown cooling cycle following an overcurrent fault.
This cycle consists of 4 discharging ramps and 3 charging
ramps. The charging and discharging currents are 5.8μA
and TIMER ramps between its 1V and 4V thresholds. At
thecompletionofashutdowncoolingcycle,theLTC4252-2
attempts a start-up cycle.
at V always overrides OV. A 1nF to 10nF capacitor at OV
IN
prevents transients and switching noise from affecting
the OV thresholds and prevents glitches at the GATE pin.
425212fd
10
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
BLOCK DIAGRAM
V
IN
–
+
DRAIN
V
IN
2.385V
6.15V
(5V)
8×
1×
V
EE
V
IN
1×
1×
58μA
V
EE
PWRGD **
V
IN
6.15V
(5.09V)
–
+
58μA
V
EE
GATE
OV *
UV *
2.8V
–
V
IN
+
–
V
EE
–(+)
+
2.925V
(3.08V)
+(
)
–
V
IN
–
+
LOGIC
V
IN
230μA
5.8μA
4V
–
+
0.5V
TIMER
+
–
–
+
FCL
200mV
+
V
EE
–
V
5.8μA
IN
EE
1V
EE
V
V
22μA
(28μA)
+
SS
V
= 10mV
OS
ACL
95k
(47.5k)
+
–
–
V
EE
R
SS
+
–
V
5k
EE
SENSE
(2.5k)
CB
50mV
V
EE
V
+
–
EE
425212 BD
V
EE
*OV AND UV ARE TIED TOGETHER ON THE MS8 PACKAGE. OV AND UV ARE SEPARATE PINS ON THE MS PACKAGE
** ONLY AVAILABLE IN THE MS PACKAGE
FOR COMPONENTS, CURRENT AND VOLTAGE WITH TWO VALUES, VALUES IN PARENTHESES REFER
TO THE LTC4252A. VALUES WITHOUT PARENTHESES REFER TO THE LTC4252
425212fd
11
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
OPERATION
Hot Circuit Insertion
Interlock Conditions
When circuit boards are inserted into a live backplane, the
supplybypasscapacitorscandrawhugetransientcurrents
from the power bus as they charge. The flow of current
damages the connector pins and glitches the power bus,
causing other boards in the system to reset. The LTC4252
isdesignedtoturnonacircuitboardsupplyinacontrolled
manner, allowing insertion or removal without glitches or
connector damage.
A start-up sequence commences once these “interlock”
conditions are met.
1. The input voltage V exceeds V
(UVLO).
IN
LKO
2. The voltage at UV > V
3. The voltage at OV < V
.
UVHI
.
OVLO
4. The (SENSE – V ) voltage is < 50mV (V ).
EE
CB
5. The voltage at SS is < 0.2V (20 • V ).
OS
Initial Start-Up
6. ThevoltageontheTIMERcapacitor(C ) is < 1V (V
).
T
TMRL
The LTC4252 resides on a removable circuit board and
controlsthepathbetweentheconnectorandloadorpower
conversion circuitry with an external MOSFET switch (see
Figure 1). Both inrush control and short-circuit protection
are provided by the MOSFET.
7. The voltage at GATE is < 0.5V (V
).
GATEL
The first three conditions are continuously monitored and
the latter four are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
AdetailedschematicfortheLTC4252AisshowninFigure2.
–48Vand–48RTNreceivepowerthroughthelongestcon-
nector pins and are the first to connect when the board is
inserted. The GATE pin holds the MOSFET off during this
time. UV and OV determine whether or not the MOSFET
should be turned on based upon internal high accuracy
thresholds and an external divider. UV and OV do double
duty by also monitoring whether or not the connector is
seated. The top of the divider detects –48RTN by way of
a short connector pin that is the last to mate during the
insertion sequence.
TIMER begins the start-up sequence by sourcing 5.8μA
into C . If V , UV or OV falls out of range, the start-up
T
IN
cycle stops and TIMER discharges C to less than 1V, then
T
waits until the aforementioned conditions are once again
met. If C successfully charges to 4V, TIMER pulls low
T
and both SS and GATE pins are released. GATE sources
58μA (I
), charging the MOSFET gate and associated
GATE
capacitance. The SS voltage ramp limits V
to control
SENSE
the inrush current. PWRGD pulls active low when GATE is
within 2.8V of V and DRAIN is lower than V
.
IN
DRNL
LONG
PLUG-IN BOARD
LONG
–48RTN
R
IN
–48RTN
+
+
+
+
D
3 × 1.8k IN SERIES
IN
C
LOAD
ISOLATED
DC/DC
DDZ13B**
1/4W EACH
LTC4252
100μF
+
LOW
VOLTAGE
CIRCUITRY
C
LOAD
R1
392k
1ꢀ
CONVERTER
MODULE
SHORT
C
IN
V
OV
UV
IN
LONG
1μF
–48V
–
–
LTC4252A-1
C1
10nF
TIMER
BACKPLANE
4252-1/2 F01
SS
DRAIN
V
SENSE GATE
EE
Figure ±. Basic LTC4252 Hot Swap Topology
C
SS
R2
30.1k
1ꢀ
68nF
R
D
C
1M
T
R
C
0.68μF
C
C
10Ω
10nF
LONG
–48V
425212 F02
R
S
0.02Ω
Q1
IRF530S
**DIODES, INC
†
RECOMMENDED FOR HARSH ENVIRONMENTS
Figure 2. –48V, 2.5A Hot Swap Controller
425212fd
12
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
OPERATION
Two modes of operation are possible during the time the
MOSFET is first turning on, depending on the values of
externalcomponents,MOSFETcharacteristicsandnominal
designcurrent.OnepossibilityisthattheMOSFETwillturn
on gradually so that the inrush into the load capacitance
remains a low value. The output will simply ramp to –48V
and the LTC4252 will fully enhance the MOSFET. A second
possibility is that the load current exceeds the soft-start
Higher overloads are handled by an analog current limit
loop.IfthedropacrossR reachesV ,thecurrentlimiting
S
ACL
loop servos the MOSFET gate and maintains a constant
output current of V /R . In current limit mode, V
ACL
S
OUT
typicallyrisesandthisincreasesMOSFETheating.IfV
>
OUT
V
,connectinganexternalresistor,R ,betweenV
DRNCL
D OUT
and DRAIN allows the fault timing cycle to be shortened
by accelerating the charging of the TIMER capacitor. The
currentlimitthresholdof[V (t)/20–V ]/R .Inthiscase
TIMER pull-up current is increased by 8 • I . Note that
DRN
SS
OS
S
the LTC4252 will ramp the output by sourcing soft-start
limited current into the load capacitance. If the soft-start
voltage is below 1.2V, the circuit breaker TIMER is held
low. Above 1.2V, TIMER ramps up. It is important to set
the timer delay so that, regardless of which start-up mode
is used, the TIMER ramp is less than one circuit breaker
delay time. If this condition is not met, the LTC4252-1 may
shut down after one circuit breaker delay time whereas
the LTC4252-2 may continue to autoretry.
because SENSE > 50mV, TIMER charges C during this
T
time and the LTC4252 will eventually shut down.
Low impedance failures on the load side of the LTC4252
coupled with 48V or more driving potential can produce
current slew rates well in excess of 50A/μs. Under these
conditions, overshoot is inevitable. A fast SENSE com-
parator with a threshold of 200mV detects overshoot and
pulls GATE low much harder and hence much faster than
the weaker current limit loop. The V /R current limit
ACL
S
loop then takes over and servos the current as previously
Board Removal
described. As before, TIMER runs and shuts down the
If the board is withdrawn from the card cage, the UV and
OV divider is the first to lose connection. This shuts off
the MOSFET and commutates the flow of current in the
connector. When the power pins subsequently separate,
there is no arcing.
LTC4252 when C reaches 4V.
T
If C reaches 4V, the LTC4252-1 latches off with a 5.8μA
T
pull-up current source whereas the LTC4252-2 starts a
shutdown cooling cycle. The LTC4252-1 circuit breaker
latch is reset by either pulling UV momentarily low or
dropping the input voltage V below the internal UVLO
IN
Current Control
thresholdorpullingTIMERmomentarilylowwithaswitch.
Three levels of protection handle short-circuit and over-
load conditions. Load current is monitored by SENSE and
The LTC4252-2 retries after its shutdown cooling cycle.
Although short-circuits are the most obvious fault type,
several operating conditions may invoke overcurrent
protection. Noisespikesfromthebackplaneorload, input
stepscausedbytheconnectionofasecond,highervoltage
supply, transient currents caused by faults on adjacent
circuit boards sharing the same power bus or the inser-
tion of non-hot-swappable products could cause higher
than anticipated input current and temporary detection
of an overcurrent condition. The action of TIMER and CT
rejects these events allowing the LTC4252 to “ride out”
temporary overloads and disturbances that could trip a
simplecurrentcomparatorand,insomecases,blowafuse.
resistor R . There are three distinct thresholds at SENSE:
S
50mV for a timed circuit breaker function; 100mV for an
analog current limit loop (60mV for the LTC4252A); and
200mV for a fast, feedforward comparator which limits
peak current in the event of a catastrophic short-circuit.
If, owingtoanoutputoverload, thevoltagedropacrossR
S
exceeds50mV,TIMERsources230μAintoC .C eventually
T
T
charges to a 4V threshold and the LTC4252 shuts off. If
the overload goes away before C reaches 4V and SENSE
T
measureslessthan50mV,C slowlydischarges(5.8μA).In
T
this way the LTC4252’s circuit breaker function responds
to low duty cycle overloads and accounts for fast heating
and slow cooling characteristics of the MOSFET.
425212fd
13
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
SHUNT REGULATOR
Kelvin terminal as illustrated in Figure 3, keeping trace
lengthsbetweenV , C , D andV asshortaspossible.
IN IN IN
EE
AfastrespondingshuntregulatorclampstheV pinto13V
IN
(VZ). Power is derived from –48RTN by an external current
INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)
limiting resistor, R . A 1μF decoupling capacitor, C filters
IN
IN
supply transients and contributes a short delay at start-up.
Ahystereticcomparator,UVLO,monitorsV forundervolt-
IN
age. ThethresholdsaredefinedbyV anditshysteresis,
To meet creepage requirements R may be split into two or
LKO
IN
V
.WhenV risesaboveV thechipisenabled;below
more series connected units. This introduces a wider total
spacing than is possible with a single component while at
the same time ballasting the potential across the gap under
each resistor. The LTC4252 is fundamentally a low voltage
device that operates with –48V as its reference ground. To
further protect against arc discharge into its pins, the area
in and around the LTC4252 and all associated components
should be free of any other planes such as chasis ground,
return, or secondary-side power and ground planes.
LKH
IN LKO
(V
– V ) it is disabled and GATE is pulled low. The
LKH
LKO
UVLO function at V should not be confused with the
IN
UV/OV pin(s). These are completely separate functions.
UV/OV COMPARATORS (LTC4252)
An UV hysteretic comparator detects undervoltage condi-
tions at the UV pin, with the following thresholds:
UV low-to-high (V
UV high-to-low (V
) = 3.225V
UVHI
V may be biased with additional current up to 30mA to
IN
accomodate external loading such as the PWRGD opto-
) = 2.925V
UVLO
coupler shown in Figure 23. As an alternative to running
An OV hysteretic comparator detects overvoltage condi-
tions at the OV pin, with the following thresholds:
higher current, simply buffer V with an emitter follower
IN
as shown in Figure 3. Another method shown in Figure
OV low-to-high (V
OV high-to-low (V
) = 6.150V
OVHI
) = 5.550V
OVLO
19 cascodes the PWRGD output.
V is rated handle 30mA within the thermal limits of the
IN
package,andistestedtosurvivea100μs,100mApulse. To
The UV and OV trip point ratio is designed to match the
standardtelecomoperatingrangeof43Vto82Vwhencon-
nected together as in the typical application. A divider (R1,
R2) is used to scale the supply voltage. Using R1 = 402k
protect V against damage from higher amplitude spikes,
IN
clamp V to V with a 13V Zener diode. Star connect
IN
EE
V and all V -referred components to the sense resistor
EE
EE
–48RTN
R
10k
1/2W
IN
+
C
L
R4
100μF
22k
Q2
†
D
C
IN
IN
**
LOAD
DDZ13B
R5
2.2k
1μF
–48RTN
(SHORT PIN)
1
V
R1
432k
1ꢀ
IN
EN
LTC4252-1
*
9
8
2
UV
PWRGD
R
D
1M
R2
4.75k
1ꢀ
7
6
4
OV
DRAIN
GATE
10
3
Q1
IRF530S
TIMER
SS
R3
38.3k
1ꢀ
C
T
SENSE
V
EE
330nF
R
C
R
S
C2
10nF
5
10Ω
C
0.02Ω
SS
C
C
68nF
18nF
–48V
425212 F03
* M0C207
Q2: MMBT5551LT1
**DIODES, INC
RECOMMENDED FOR HARSH ENVIRONMENTS
†
Figure 3. –48V/2.5A Application with Different Input Operating Range
425212fd
14
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
and R2 = 32.4k gives a typical operating range of 43.2V
to 82.5V. The undervoltage shutdown and overvoltage
recovery thresholds are then 39.2V and 74.4V. 1ꢀ divider
resistorsarerecommendedtopreservethresholdaccuracy.
OV low-to-high (V ) = 5.09V
OV
OV high-to-low (V – V
) = 4.988V
OVHST
OV
The UV and OV trip point ratio is designed to match the
standard telecom operating range of 43V to 71V when
connected together as in Figure 2. A divider (R1, R2) is
used to scale the supply voltage. Using R1 = 390k and R2
= 30.1k gives a typical operating range of 43V to 71V. The
undervoltage shutdown and overvoltage recovery thresh-
olds are then 38.5V and 69.6V respectively. 1ꢀ divider
resistorsarerecommendedtopreservethresholdaccuracy.
The R1-R2 divider values shown in the Typical Application
set a standing current of slightly more than 100μA and
define an impedance at UV/OV of 30kΩ. In most applica-
tions,30kΩimpedancecoupledwith300mVUVhysteresis
makes the LTC4252 insensitive to noise. If more noise
immunity is desired, add a 1nF to 10nF filter capacitor
from UV/OV to V .
EE
The R1-R2 divider values shown in Figure 2 set a standing
currentofslightlymorethan100μAanddefineanimpedance
at UV/OV of 28kΩ. In most applications, 28kΩ impedance
coupled with 324mV UV hysteresis makes the LTC4252A
insensitive to noise. If more noise immunity is desired, add
Separate UV and OV pins are available in the 10-pin MS
package and can be used for a different operating range
such as 35.5V to 76V as shown in Figure 3. Other combi-
nations are possible with different resistor arrangements.
a 1nF to 10nF filter capacitor from UV/OV to V .
EE
UV/OV COMPARATORS (LTC4252A)
The UV and OV pins can be used for a wider operat-
ing range such as 35.5V to 76V as shown in Figure 4.
Other combinations are possible with different resistor
arrangements.
A UV hysteretic comparator detects undervoltage condi-
tions at the UV pin, with the following thresholds:
UV low-to-high (V ) = 3.08V
UV
UV high-to-low (V – V
) = 2.756V
UVHST
UV
UV/OV OPERATION
An OV hysteretic comparator detects overvoltage condi-
tions at the OV pin, with the following thresholds:
AlowinputtotheUVcomparatorwillresetthechipandpull
the GATE and TIMER pins low. A low-to-high UV transition
will initiate an initial timing sequence if the other interlock
–48RTN
R
IN
+
10k
1/2W
C
R4
L
100μF
22k
Q2
†
D
C
IN
IN
**
LOAD
DDZ13B
R5
2.2k
1μF
–48RTN
1
(SHORT PIN)
R1
V
IN
EN
464k
1ꢀ
LTC4252A-1
*
9
8
2
UV
OV
PWRGD
R
1M
D
R2
10k
1ꢀ
7
6
4
DRAIN
GATE
10
3
Q1
IRF530S
TIMER
SS
R3
34k
1ꢀ
C
T
SENSE
V
EE
0.68μF
R
R
S
0.02Ω
C
5
C2
10nF
C
10Ω
C
SS
68nF
C
10nF
–48V
425212 F04
* M0C207
Q2: MMBT5551LT1
**DIODES, INC
†
RECOMMENDED FOR HARSH ENVIRONMENTS
Figure 4. –48V/2.5A Application with Wider Input Operating Range
425212fd
15
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
conditions are met. A high-to-low transition in the UV
comparator immediately shuts down the LTC4252, pulls
the MOSFET gate low and resets the latched PWRGD high.
4) Low impedance switch; resets the TIMER capacitor
after an initial timing delay, in UVLO, in UV and in OV
during initial timing.
Overvoltage conditions detected by the OV compara-
tor will also pull GATE low, thereby shutting down the
load. However, it will not reset the circuit breaker TIMER,
PWRGD flag or shutdown cooling timer. Returning the
supply voltage to an acceptable range restarts the GATE
pin if all the interlock conditions except TIMER are met.
Only during the initial timing cycle does an OV condition
reset the TIMER.
For initial start-up, the 5.8μA pull-up is used. The low
impedance switch is turned off and the 5.8μA current
source is enabled when the interlock conditions are met.
C charges to 4V in a time period given by:
T
4V •CT
t=
5.8μA
(2)
), the low impedance switch
TMRH
When C reaches 4V (V
T
turns on and discharges C . A GATE start-up cycle begins
T
DRAIN
and both SS and GATE are released.
Connecting an external resistor, R , to the dual function
D
CIRCUIT BREAKER TIMER OPERATION
DRAIN pin allows V
sensing* without it being dam-
OUT
aged by large voltage transients. Below 5V, negligible pin
leakage allows a DRAIN low comparator to detect V
If the SENSE pin detects more than a 50mV drop across
OUT
R , the TIMER pin charges C with (230μA + 8 • I ). If
S
T
DRN
less than 2.385V (V
). This condition, together with
DRNL
C chargesto4V,theGATEpinpullslowandtheLTC4252-1
T
the GATE low comparator, sets the PWRGD flag.
latches off while the LTC4252-2 starts a shutdown cooling
cycle. The LTC4252-1 remains latched off until the UV
pin is momentarily pulsed low or TIMER is momentarily
If V
DRNCL
> V
, the DRAIN pin is clamped at about
OUT
DRNCL
V
and the current flowing in R is given by:
D
discharged low by an external switch or V dips below
IN
V
OUT -VDRNCL
UVLO and is then restored. The circuit breaker timeout
IDRN
≈
(1)
RD
period is given by:
This current is scaled up 8 times during a circuit breaker
fault and is added to the nominal 230μA TIMER current.
This accelerates the fault TIMER pull-up when the MOS-
4V •CT
t=
230μA+8•IDRN
(3)
FET’sdrain-sourcevoltageexceedsV
andeffectively
DRNCL
If V
< 5V, an internal PMOS device isolates any DRAIN
OUT
shortens the MOSFET heating duration.
pin leakage current, making I
= 0μA in Equation (3).
DRN
If V
> V
during the circuit breaker fault period,
OUT
DRNCL
the charging of C accelerates by 8 • I
of Equation (1).
TIMER
T
DRN
Intermittent overloads may exceed the 50mV threshold at
SENSE, but, if their duration is sufficiently short, TIMER
willnotreach4VandtheLTC4252willnotshuttheexternal
MOSFEToff.Tohandlethissituation,theTIMERdischarges
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor C is used at
T
TIMER to provide timing for the LTC4252. Four different
charging and discharging modes are available at TIMER:
C slowly with a 5.8μA pull-down whenever the SENSE
T
1) A 5.8μA slow charge; initial timing and shutdown cool-
ing delay.
voltage is less than 50mV. Therefore, any intermittent
overload with V
> 5V and an aggregate duty cycle of
OUT
2) A (230μA + 8 • I ) fast charge; circuit breaker delay.
DRN
3) A 5.8μA slow discharge; circuit breaker “cool off” and
shutdown cooling.
*V
OUT
as viewed by the MOSFET; i.e., V .
DS
425212fd
16
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
10
SOFT-START
I
= 0μA
DRN
Soft-start limits the inrush current profile during GATE
start-up. Unduly long soft-start intervals can exceed the
MOSFET’s SOA rating if powering up into an active load.
If SS floats, an internal current source ramps SS from 0V
to 2.2V for the LTC4252 or 0V to 1.4V for the LTC4252A
1
0.1
t
4
=
C (μF)
T
<ꢀꢁꢂꢃꢄꢅꢆꢇꢆꢅꢆtꢆ*
ꢈꢆtꢆ%ꢆoꢆꢃꢄꢅ>
DRN
in about 230μs. Connecting an external capacitor C
SS
from SS to ground modifies the ramp to approximate an
RC response of:
0.01
0
20
40
60
80
100
⎛
⎞
⎛
⎜
t
⎞
–
FAULT DUTY CYCLE (ꢀ)
⎜
⎟
R
• C
⎟
⎝
⎠
425212 F05
SS SS
V
(t)≈V • 1–e
SS
SS
⎜
⎟
⎜
⎝
⎟
⎠
Figure 5. Circuit-Breaker Response Time
(6)
An internal resistive divider (95k/5k for the LTC4252 or
2.5ꢀ or more will eventually trip the circuit breaker and
shutdowntheLTC4252.Figure5showsthecircuitbreaker
47.5k/2.5k for the LTC4252A) scales V (t) down by 20
SS
times to give the analog current limit threshold:
response time in seconds normalized to 1μF for I
=
DRN
0μA. The asymmetric charging and discharging of C is
VSS (t)
20
T
VACL (t)=
–VOS
a fair gauge of MOSFET heating.
(7)
The normalized circuit response time is estimated by
This allows the inrush current to be limited to V (t)/R .
ACL
S
t
4
Theoffsetvoltage, V (10mV), ensuresC issufficiently
OS
SS
=
discharged and the ACL amplifier is in current limit before
GATE start-up. SS is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
CT (μF)
⎡
⎤
•D–5.8
235.8+8•I
(4)
(
)
DRN
⎣
⎦
SHUTDOWN COOLING CYCLE
For the LTC4252-1 (latchoff version), TIMER latches high
with a 5.8μA pull-up after the circuit breaker fault TIMER
reaches 4V. For the LTC4252-2 (automatic retry version),
a shutdown cooling cycle begins if TIMER reaches the
4V threshold. TIMER starts with a 5.8μA pull-down until
it reaches the 1V threshold. Then, the 5.8μA pull-up turns
back on until TIMER reaches the 4V threshold. Four 5.8μA
pull-down cycles and three 5.8μA pull-up cycles occur
between the 1V and 4V thresholds, creating a time interval
given by:
GATE
GATE is pulled low to V under any of the following
EE
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out. When GATE turns
on, a 58μA current source charges the MOSFET gate and
any associated external capacitance. V limits the gate
IN
drive to no more than 14.5V.
7•3V •CT
5.8μA
tSHUTDOWN
=
Gate-drain capacitance (C ) feedthrough at the first
GD
(5)
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
At the 1V threshold of the last pull-down cycle, a GATE
ramp-up is attempted.
pulls GATE low with practically no usable voltage at V
IN
425212fd
17
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
and eliminates current spikes at insertion. A large external
SHORT-CIRCUIT OPERATION
gate-sourcecapacitoristhusunnecessaryforthepurpose
Circuit behavior arising from a load side low impedance
short is shown in Figure 6 for the LTC4252. Initially, the
of compensating C . Instead, a smaller value (≥ 10nF)
GD
capacitor C is adequate. C also provides compensation
C
C
current overshoots the fast current limit level of V
=
SENSE
GS
for the analog current limit loop.
200mV (Trace 2) as the GATE pin works to bring V under
GATE has two comparators: the GATE low comparator
looks for < 0.5V threshold prior to initial timing or a GATE
start-up cycle; the GATE high comparator looks for < 2.8V
control (Trace 3). The overshoot glitches the backplane
in the negative direction and when the current is reduced
to 100mV/R , the backplane responds by glitching in the
S
relative to V and, together with the DRAIN low compara-
positive direction.
IN
tor, sets PWRGD status during GATE startup.
TIMERcommenceschargingC (Trace4)whiletheanalog
currentlimitloopmaintainsthefaultcurrentat100mV/R ,
T
S
SENSE
which in this case is 5A (Trace 2). Note that the backplane
voltage (Trace 1) sags under load. Timer pull-up is ac-
celerated by V . When C reaches 4V, GATE turns off,
The SENSE pin is monitored by the circuit breaker (CB)
comparator, the analog current limit (ACL) amplifier and
thefastcurrentlimit(FCL)comparator. Eachofthesethree
OUT
T
PWRGD pulls high, the load current drops to zero and the
backplane rings up to over 100V. The transient associated
with the GATE turn off can be controlled with a snubber to
reduceringingandatransientvoltagesuppressor(suchas
Diodes Inc. SMAT70A) to clip off large spikes. The choice
of RC for the snubber is usually done experimentally. The
value of the snubber capacitor is usually chosen between
measures the potential of SENSE relative to V . When
EE
SENSE exceeds 50mV, the CB comparator activates the
230μATIMERpull-up.At100mV(60mVfortheLTC4252A),
the ACL amplifier servos the MOSFET current and, at
200mV, the FCL comparator abruptly pulls GATE low in
an attempt to bring the MOSFET current under control. If
any of these conditions persists long enough for TIMER
10 to 100 times the MOSFET C . The value of the snub-
ber resistor is typically between 3Ω to 100Ω.
OSS
to charge C to 4V (see Equation 3), the LTC4252 shuts
T
down and pulls GATE low.
SUPPLY RING OWING TO
CURRENT OVERSHOOT
SUPPLY RING OWING TO
MOSFET TURN OFF
If the SENSE pin encounters a voltage greater than V
,
ACL
theACLamplifierwillservoGATEdownwardsinanattempt
to control the MOSFET current. Since GATE overdrives the
MOSFETinnormaloperation,theACLamplifierneedstime
to discharge GATE to the threshold of the MOSFET. For a
mild overload the ACL amplifier can control the MOSFET
current, but in the event of a severe overload the current
may overshoot. At SENSE = 200mV the FCL comparator
–48RTN
50V/DIV
ONSET OF OUTPUT SHORT-CIRCUIT
FAST CURRENT LIMIT
SENSE
200mV/DIV
takes over, quickly discharging the GATE pin to near V
EE
potential. FCL then releases and the ACL amplifier takes
over. All the while TIMER is running. The effect of FCL is
to add a nonlinear response to the control loop in favor
of reducing MOSFET current.
GATE
10V/DIV
ANALOG CURRENT LIMIT
TIMER
5V/DIV
LATCH OFF
Owing to inductive effects in the system, FCL typically
overcorrectsthecurrentlimitloopandGATEundershoots.
A zero in the loop (resistor RC in series with the gate ca-
pacitor) helps the ACL amplifier to recover.
C
RAMP
TIMER
425212 F06
0.5ms/DIV
Figure 6. Output Short-Circuit Behavior of LTC4252
425212fd
18
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
A low impedance short on one card may influence the
behavior of others sharing the same backplane. The initial
glitch and backplane sag as seen in Figure 6 Trace 1, can
rob charge from output capacitors on adjacent cards.
When the faulty card shuts down, current flows in to
refresh the capacitors. If LTC4252s are used by the other
cards, they respond by limiting the inrush current to a
To begin a design, first specify the required load current
and Ioad capacitance, I and C . The circuit breaker cur-
L
L
rent trip point (V /R ) should be set to accommodate
CB
S
the maximum load current. Note that maximum input
current to a DC/DC converter is expected at V
.
SUPPLY(MIN)
R is given by:
S
VCB(MIN)
RS =
value of 100mV/R . If C is sized correctly, the capacitors
S
T
IL(MAX)
(8)
will recharge long before C times out.
T
where V
= 40mV (45mV for LTC4252A) represents
CB(MIN)
the guaranteed minimum circuit breaker threshold.
POWER GOOD, PWRGD
Duringtheinitialchargingprocess,theLTC4252mayoper-
PWRGD latches low if GATE charges up to within 2.8V of
ate the MOSFET in current limit, forcing (V ) between
ACL
V andDRAINpullsbelowV
duringstart-up.PWRGD
IN
DRNL
80mV to 120mV (V
is 54mV to 66mV for LTC4252A)
across R . The minimum inrush current is given by:
ACL
is reset in UVLO, in a UV condition or if C charges up
T
S
to 4V. An overvoltage condition has no effect on PWRGD
status. A 58μA current pulls this pin high during reset.
Due to voltage transients between the power module and
PWRGD,optoisolationisrecommended.Thispinprovides
sufficent drive for an optocoupler. Figure 19 shows an
alternative NPN configuration with a limiting base resistor
for the PWRGD interface. The module enable input should
have protection from the negative input current.
80mV
RS
IINRUSH(MIN)
=
(9)
Maximum short-circuit current limit is calculated using
the maximum V . This gives
ACL
120mV
RS
ISHORTCIRCUIT(MAX)
=
(10)
MOSFET SELECTION
The TIMER capacitor C must be selected based on the
T
slowest expected charging rate; otherwise TIMER might
The external MOSFET switch must have adequate safe
operating area (SOA) to handle short-circuit conditions
until TIMER times out. These considerations take prece-
dence over DC current ratings. A MOSFET with adequate
SOAforagivenapplicationcanalwayshandletherequired
current, but the opposite may not be true. Consult the
manufacturer’s MOSFET data sheet for safe operating
area and effective transient thermal impedance curves.
time out before the load capacitor is fully charged. A value
for C is calculated based on the maximum time it takes
T
the load capacitor to charge. That time is given by:
CL •VSUPPLY(MAX)
C•V
I
tCL(CHARGE)
=
=
I
INRUSH(MIN)
(11)
ThemaximumcurrentflowingintheDRAINpinisgivenby:
SUPPLY(MAX)–VDRNCL
MOSFET selection is a 3-step process by assuming the
absense of a soft-start capacitor. First, R is calculated
and then the time required to charge the load capacitance
is determined. This timing, along with the maximum
short-circuit current and maximum input voltage defines
an operating point that is checked against the MOSFET’s
SOA curve.
V
IDRN(MAX)
=
S
RD
(12)
425212fd
19
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
Approximating a linear charging rate as I
drops from
was appropriate. The ratio (R • C ) to t
is
DRN
SS
SS
CL(CHARGE)
I
to zero, the I
component in Equation (3)
a good gauge as a large ratio may result in the time-out
period expiring. This gauge is determined empirically with
board level evaluation.
DRN(MAX)
DRN
can be approximated with 0.5 • I
. Rearranging
DRN(MAX)
equation, TIMER capacitor C is given by:
T
tCL(CHARGE) • 230μA+4•I
(
)
DRN(MAX)
SUMMARY OF DESIGN FLOW
CT =
(13)
4V
To summarize the design flow, consider the application
shown in Figure 2 with the LTC4252A. It was designed
for 80W.
Returning to Equation (3), the TIMER period is calcu-
lated and used in conjunction with V and
SUPPLY(MAX)
I
to check the SOA curves of a prospec-
SHORTCIRCUIT(MAX)
Calculate the maximum load current: 80W/43V = 1.86A;
allowing for 83ꢀ converter efficiency, I
tive MOSFET.
As a numerical design example, consider a 30W load,
which requires 1A input current at 36V. If V
= 2.2A.
IN(MAX)
Calculate R : from Equation (8) R = 20mΩ.
S
S
SUPPLY(MAX)
Calculate I : from Equation (10)
SHORTCIRCUIT(MAX)
= 72V and C = 100μF, R = 1MΩ, Equation (8) gives R
L
D
S
= 40mΩ; Equation (13) gives C = 441nF. To account for
T
66mV
20mꢁ
ISHORTCIRCUIT(MAX)
=
=3.3A
errorsinR , C , TIMERcurrent(230μA), TIMERthreshold
S
T
(4V), R , DRAIN current multiplier and DRAIN voltage
D
Select a MOSFET that can handle 3.3A at 71V: IRF530S.
clamp (V
), the calculated value should be multiplied
DRNCL
by 1.5, giving the nearest standard value of C = 680nF.
T
Calculate C : from Equation (13) C = 322nF. Select
T
T
C = 680nF, which gives the circuit breaker time-out period
Ifashort-circuitoccurs,acurrentofupto120mV/40mΩ=3A
willflowintheMOSFETfor5.6msasdictatedbyC =680nF
T
t = 5.6ms.
T
in Equation (3). The MOSFET must be selected based on
this criterion. The IRF530S can handle 100V and 3A for
10ms and is safe to use in this application.
ConsultMOSFETSOAcurves:theIRF530Scanhandle3.3A
at 100V for 8.2ms, so it is safe to use in this application.
Calculate C : using Equations (14) and (15) select
SS
Computingthemaximumsoft-startcapacitorvalueduring
soft-start to a load short is complicated by the nonlinear
C
SS
= 68nF.
MOSFET’s SOA characteristics and the R C response.
SS SS
FREQUENCY COMPENSATION
An overly conservative but simple approach begins with
the maximum circuit breaker current, given by:
VCB(MAX)
TheLTC4252Atypicalfrequencycompensationnetworkfor
the analog current limit loop is a series R (10Ω) and C
C
C
ICB(MAX)
=
connectedtoV .Figure7depictstherelationshipbetween
EE
RS
(14)
the compensation capacitor C and the MOSFET’s C
.
C
C
ISS
where V
= 60mV (55mV for the LTC4252A).
CB(MAX)
The line in Figure 7 is used to select a starting value for C
based upon the MOSFET’s C specification. Optimized
ISS
From the SOA curves of a prospective MOSFET, determine
values for C are shown for several popular MOSFETs.
C
the time allowed, t
. C is given by:
SOA(MAX) SS
tSOA(MAX)
DifferencesintheoptimizedvalueofC versusthestarting
C
CSS =
valuearesmall.Nevertheless,compensationvaluesshould
0.916•RSS
(15)
SOA(MAX)
be verified by board level short-circuit testing.
In the above example, 60mV/40mΩ gives 1.5A. t
for the IRF530S is 40ms. From Equation (15), C
=
SS
437nF. Actual board evaluation showed that C = 100nF
SS
425212fd
20
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
60
CURRENT FLOW
FROM LOAD
CURRENT FLOW
TO –48V BACKPLANE
NTY100N10
50
40
30
SENSE RESISTOR
TRACK WIDTH W:
W
0.03" PER AMP
ON 1 OZ COPPER
IRF3710
IRF540S
20
10
0
425212 F08
IRF530S
IRF740
TO
SENSE
TO
EE
V
0
2000
4000
6000
8000
MOSFET C (pF)
ISS
Figure 8. Making PCB Connections to the Sense Resistor
425212 F07
Figure 7. Recommended Compensation
Capacitor CC vs MOSFET CISS
time point 1, the supply ramps up, together with UV/OV,
V
and DRAIN. V and PWRGD follow at a slower rate
OUT
IN
as set by the V bypass capacitor. At time point 2, V
IN
IN
,
As seen in Figure 6 previously, at the onset of a short-
circuitevent,theinputsupplyvoltagecanringdramatically
owing to series inductance. If this voltage avalanches the
MOSFET, current continues to flow through the MOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
exceeds V and the internal logic checks for UV > V
LKO
UVHI
OV < V
, GATE < V
, SENSE < V , SS < 20 • V
OVLO
GATEL CB OS
and TIMER < V
. If all conditions are met, an initial
TMRL
timing cycle starts and the TIMER capacitor is charged
by a 5.8μA current source pull-up. At time point 3, TIMER
reaches the V
threshold and the initial timing cycle
TMRH
terminates. The TIMER capacitor is quickly discharged. At
timepoint4,theV thresholdisreachedandthecondi-
TMRL
tions of GATE < V
, SENSE < V and SS < 20 • V
GATEL
CB OS
must be satisfied before a GATE ramp-up cycle begins.
SENSE RESISTOR CONSIDERATIONS
SS ramps up as dictated by R • C (as in Equation 6);
SS
SS
GATE is held low by the analog current limit (ACL) ampli-
Forpropercircuitbreakeroperation,Kelvin-sensePCBcon-
nectionsbetweenthesenseresistorandtheLTC4252’sV
fier until SS crosses 20 • V . Upon releasing GATE, 58μA
OS
EE
sources into the external MOSFET gate and compensation
network. When the GATE voltage reaches the MOSFET’s
threshold, current begins flowing into the load capacitor
at time point 5. At time point 6, load current reaches the
SScontrollevelandtheanalogcurrentlimitloopactivates.
Between time points 6 and 8, the GATE voltage is servoed,
andSENSEpinsarestronglyrecommended.Thedrawingin
Figure 8 illustrates the correct way of making connections
between the LTC4252 and the sense resistor. PCB layout
should be balanced and symmetrical to minimize wiring
errors. In addition, the PCB layout for the sense resistor
should include good thermal management techniques for
optimal sense resistor power dissipation.
the SENSE voltage is regulated at V (t) (Equation 7) and
ACL
soft-start limits the slew rate of the load current. If the
SENSE voltage (V
– V ) reaches the V threshold
SENSE
EE CB
TIMING WAVEFORMS
System Power-Up
at time point 7, the circuit breaker TIMER activates. The
TIMER capacitor, C , is charged by a (230μA + 8 • I
)
DRN
T
current pull-up. As the load capacitor nears full charge,
Figure 9 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
load current begins to decline.
425212fd
21
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
V
CLEARS V , CHECK UV > V
, OV < V
, GATE < V
, SENSE < V ꢉꢆ44ꢆꢊꢆꢁꢋꢆtꢆ7 AND TIMER < V
IN
LKO
UVHI
OVLO
GATEL
CB
OS
TMRL
TIMER CLEARS V
, CHECK GATE < V
, SENSE < V ꢆ"/%ꢆ44ꢆꢊꢆꢁꢋꢆtꢆ7
TMRL
GATEL
CB
OS
1
2
3 4 56
7
8 9 10 11
GND – V OR
EE
(–48RTN) – (–48V)
UV/OV
V
V
LKO
IN
V
TMRH
ꢁꢂꢋ"ꢆꢇꢆꢅꢆtꢆ*
DRN
5.8μA
TIMER
5.8μA
5.8μA
V
TMRL
58μA
V
– V
GATEH
IN
GATE
SS
58μA
V
GATEL
ꢁꢋꢆtꢆꢀ7
ꢁꢋꢆtꢆꢀ7 + V
+ V
)
)
ACL
OS
OS
CB
ꢁꢋꢆtꢆ7
OS
V
V
ACL
CB
SENSE
V
OUT
V
V
DRNCL
DRNL
DRAIN
PWRGD
425212 F09
GATE
START-UP
INITIAL TIMING
Figure 9. System Power-Up Timing (All Waveforms Are Referenced to VEE)
Attimepoint8,theloadcurrentfallsandtheSENSEvoltage
makescontactthroughashortpin.Thisensuresthepower
connections are firmly established before the LTC4252 is
activated. At time point 1, the power pins make contact
drops below V (t). The analog current limit loop shuts
ACL
off and the GATE pin ramps further. At time point 9, the
SENSE voltage drops below V , the fault TIMER cycle
and V ramps through V . At time point 2, the UV/OV
CB
IN LKO
divider makes contact and its voltage exceeds V
addition, the internal logic checks for OV < V
ends, followed by a 5.8μA discharge cycle (cool off). The
duration between time points 7 and 9 must be shorter than
one circuit breaker delay to avoid a fault time out during
. In
UVHI
OVHI
, GATE
< V
V
, SENSE < V , SS < 20 • V and TIMER <
GATEL
CB OS
GATEramp-up. WhenGATErampspasttheV
thresh-
. If all conditions are met, an initial timing cycle
GATEH
TMRL
old at time point 10, PWRGD pulls low. At time point 11,
starts and the TIMER capacitor is charged by a 5.8μA
current source pull-up. At time point 3, TIMER reaches the
GATE reaches its maximum voltage as determined by V .
IN
V
TMRH
threshold and the initial timing cycle terminates.
Live Insertion with Short Pin Control of UV/OV
The TIMER capacitor is quickly discharged. At time point
4, the V threshold is reached and the conditions of
TMRL
In the example shown in Figure 10, power is delivered
through long connector pins whereas the UV/OV divider
GATE < V
, SENSE < V and SS < 20 • V must be
GATEL
CB OS
425212fd
22
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
UV CLEARS V
, CHECK OV < V
, GATE < V
, SENSE < V ꢉꢆ44ꢆꢊꢆꢁꢋꢆtꢆ7 AND TIMER < V
UVHI
OVHI
GATEL
CB
OS
TMRL
TIMER CLEARS V
, CHECK GATE < V
, SENSE < V ꢆ"/%ꢆ44ꢆꢊꢆꢁꢋꢆtꢆ7
TMRL
GATEL
CB
OS
1
2
3 4 56
7
8 9 1011
GND – V OR
EE
(–48RTN) – (–48V)
V
UVHI
V
UV/OV
V
IN
LKO
V
TMRH
ꢁꢂꢋ"ꢆꢇꢆꢅꢆtꢆ*
DRN
5.8μA
TIMER
GATE
5.8μA
V
5.8μA
TMRL
58μA
V
– V
GATEH
IN
58μA
V
GATEL
ꢁꢋꢆtꢆꢀ7
ꢁꢋꢆtꢆꢀ7 + V
+ V
)
)
ACL
OS
OS
SS
CB
ꢁꢋꢆtꢆ7
OS
V
V
ACL
CB
SENSE
V
OUT
V
V
DRNCL
DRNL
DRAIN
PWRGD
GATE
START-UP
425212 F10
INITIAL TIMING
Figure ±0. Power-Up Timing with a Short Pin (All Waveforms Are Referenced to VEE)
satisfiedbeforeaGATEstart-upcyclebegins.SSrampsup
V
threshold at time point 7, the circuit breaker TIMER
CB
as dictated by R • C ; GATE is held low by the analog
activates. TheTIMERcapacitor, C , ischargedbya(230μA
SS
SS
T
current limit amplifier until SS crosses 20 • V . Upon
+ 8 • I ) current pull-up. As the load capacitor nears full
OS
DRN
releasing GATE, 58μA sources into the external MOSFET
gate and compensation network. When the GATE voltage
reaches the MOSFET’s threshold, current begins flowing
into the load capacitor at time point 5. At time point 6,
load current reaches the SS control level and the analog
current limit loop activates. Between time points 6 and 8,
theGATEvoltageisservoed,theSENSEvoltageisregulated
charge, load current begins to decline. At point 8, the load
current falls and the SENSE voltage drops below V (t).
ACL
The analog current limit loop shuts off and the GATE pin
ramps further. At time point 9, the SENSE voltage drops
below V and the fault TIMER cycle ends, followed by a
CB
5.8μA discharge cycle (cool off). When GATE ramps past
V
threshold at time point 10, PWRGD pulls low. At
GATEH
at V (t) and soft-start limits the slew rate of the load
time point 11, GATE reaches its maximum voltage as
determined by V .
ACL
current. If the SENSE voltage (V
– V ) reaches the
SENSE
EE
IN
425212fd
23
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
Undervoltage Timing
cycle starts. If the system bus voltage overshoots V
OVHI
as shown at time point 2, TIMER discharges. At time point
3, the supply voltage recovers and drops below the V
InFigure11whenUVpindropsbelowV
(timepoint1),
UVLO
OVLO
the LTC4252 shuts down with TIMER, SS and GATE all
pulling low. If current has been flowing, the SENSE pin
voltage decreases to zero as GATE collapses. When UV
threshold. The initial timing cycle restarts, followed by a
GATE start-up cycle.
recovers and clears V
(time point 2), an initial timer
UVHI
Overvoltage Timing
cycle begins followed by a GATE start-up cycle.
During normal operation, if the OV pin exceeds V
as
OVHI
V Undervoltage Lockout Timing
IN
shownattimepoint1ofFigure13, theTIMERandPWRGD
statusareunaffected.Nevertheless,SSandGATEpulldown
and the load is disconnected. At time point 2, OV recovers
The V undervoltage lockout comparator, UVLO, has a
IN
similartimingbehaviorastheUVpintimingexceptitlooks
and drops below the V
threshold. A GATE start-up
OVLO
for V < (V
– V ) to shut down and V > V
to
IN
LKO
LKH
IN
LKO
cycle begins. If the overvoltage glitch is long enough to
deplete the load capacitor, a full start-up cycle as shown
between time points 4 through 7 may occur.
start. In an undervoltage lockout condition, both UV and
OV comparators are held off. When V exits undervoltage
lockout, the UV and OV comparators are enabled.
IN
Circuit Breaker Timing
Undervoltage Timing with Overvoltage Glitch
In Figure 14a, the TIMER capacitor charges at 230μA if
In Figure 12, both UV and OV pins are connected together.
the SENSE pin exceeds V but V
is less than 5V. If
CB
DRN
When UV clears V
(time point 1), an initial timing
UVHI
the SENSE pin drops below V before TIMER reaches
CB
UV DROPS BELOW V
. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES
UVLO
UV CLEARS V
, CHECK OV CONDITION, GATE < V
, SENSE < V ꢉꢆ44ꢆꢊꢆꢁꢋꢆtꢆ7 AND TIMER < V
UVHI
GATEL
CB
OS
TMRL
TIMER CLEARS V
, CHECK GATE < V
, SENSE < V ꢆ"/%ꢆ44ꢆꢊꢆꢁꢋꢆtꢆ7
TMRL
GATEL
CB
OS
1
2
3 4 56
7
8 910 11
V
UVHI
UVLO
UV
V
V
TMRH
ꢁꢂꢋ"ꢆꢇꢆꢅꢆtꢆ*
DRN
5.8μA
TIMER
5.8μA
V
5.8μA
TMRL
58μA
V
– V
GATEH
IN
GATE
58μA
V
GATEL
ꢁꢋꢆtꢆꢀ7
ꢁꢋꢆtꢆꢀ7 + V
+ V
)
)
ACL
OS
OS
CB
SS
ꢁꢋꢆtꢆ7
OS
V
V
ACL
CB
SENSE
V
V
DRNCL
DRNL
DRAIN
PWRGD
GATE
START-UP
425212 F11
INITIAL TIMING
Figure ±±. Undervoltage Timing (All Waveforms Are Referenced to VEE)
425212fd
24
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
UV/OV CLEARS V
, CHECK OV CONDITION, GATE < V
, SENSE < V ꢉꢆ44ꢆꢊꢆꢁꢋꢆtꢆ7 AND TIMER < V
GATEL CB OS TMRL
UVHI
UV/OV OVERSHOOTS V
AND TIMER ABORTS INITIAL TIMING CYCLE
OVHI
UV/OV DROPS BELOW V
AND TIMER RESTARTS INITIAL TIMING CYCLE
OVLO
TIMER CLEARS V
, CHECK GATE < V
, SENSE < V ꢆ"/%ꢆ44ꢆꢊꢆꢁꢋꢆtꢆ7
TMRL
GATEL
CB
OS
10 12
9 11
1
2
3
4 5 67
8
V
OVHI
V
OVLO
UV/OV
V
UVHI
V
TMRH
ꢁꢂꢋ"ꢆꢇꢆꢅꢆtꢆ*
DRN
5.8μA
TIMER
GATE
5.8μA
V
5.8μA
TMRL
58μA
V
– V
GATEH
IN
58μA
V
GATEL
ꢁꢋꢆtꢆꢀ7
ꢁꢋꢆtꢆꢀ7 + V
+ V
)
OS
)
OS
ACL
SS
CB
ꢁꢋꢆtꢆ7
OS
V
V
ACL
CB
SENSE
DRAIN
V
V
DRNCL
DRNL
PWRGD
GATE
START-UP
425212 F12
INITIAL TIMING
Figure ±2. Undervoltage Timing with an Overvoltage Glitch (All Waveforms Are Referenced to VEE)
OV OVERSHOOTS V
. GATE AND SS ARE PULLED DOWN, PWRGD AND TIMER ARE UNAFFECTED
OVHI
OV DROPS BELOW V
, CHECK GATE < V
, SENSE < V ꢆ"/%ꢆ44ꢆꢊꢆꢁꢋꢆtꢆ7
OVLO
GATEL
CB
OS
1
2 34
5
67 8 9
V
OVHI
OV
V
OVLO
V
TMRH
5.8μA
ꢁꢂꢋ"ꢆꢇꢆꢅꢆtꢆ*
TIMER
GATE
DRN
5.8μA
58μA
V
– V
GATEH
IN
58μA
V
GATEL
ꢁꢋꢆtꢆꢀ7
+ V
)
OS
ACL
ꢁꢋꢆtꢆꢀ7 + V
)
OS
SS
CB
ꢁꢋꢆtꢆ7
OS
V
V
ACL
CB
SENSE
425212 F13
GATE
START-UP
Figure ±3. Overvoltage Timing (All Waveforms Are Referenced to VEE)
425212fd
25
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
CB TIMES OUT
2
CB TIMES OUT
1
2
1
1
2
3
4
V
V
V
TMRH
TMRH
TMRH
5.8μA
ꢁꢂꢋ"ꢆꢇꢆꢅꢆtꢆ*
5.8μA
ꢁꢂꢋ"ꢆꢇꢆꢅꢆtꢆ*
ꢁꢂꢋ"ꢆꢇꢆꢅꢆtꢆ*
DRN
TIMER
TIMER
GATE
SS
TIMER
GATE
SS
ꢁꢂꢋ"ꢆꢇꢆꢅꢆtꢆ*
DRN
DRN
DRN
GATE
SS
V
V
V
V
V
V
ACL
CB
ACL
CB
ACL
CB
SENSE
SENSE
SENSE
V
OUT
V
OUT
V
OUT
V
V
DRNCL
DRNCL
DRAIN
DRAIN
DRAIN
PWRGD
PWRGD
PWRGD
CB FAULT
CB FAULT
CB FAULT
CB FAULT
425212 F14
(±4a) Momentary Circuit-Breaker Fault
(±4b) Circuit-Breaker Time Out
(±4c) Multiple Circuit-Breaker Fault
Figure ±4. Circuit-Breaker Timing Behavior (All Waveforms Are Referenced to VEE)
the V
threshold, TIMER is discharged by 5.8μA. In
pole mechanical pushbutton switch, this may not be
TMRH
Figure14b,whenTIMERexceedsV
,GATEpullsdown
feasible. A double pole, single throw pushbutton switch
removes this restriction by connecting the second switch
to the SS pin. With this method, both the SS and TIMER
pins are released at the same time (see Figure 24).
TMRH
immediately and the LTC4252 shuts down. In Figure 14c,
multiple momentary faults cause the TIMER capacitor to
integrate and reach V
. GATE pull down follows and
TMRH
theLTC4252shutsdown.Duringshutdown,theLTC4252-1
latches TIMER high with a 5.8μA pull-up current source;
the LTC4252-2 activates a shutdown cooling cycle.
Shutdown Cooling Cycle (LTC4252-2)
Figure 16 shows the timer behavior of the LTC4252-2. At
time point 2, TIMER exceeds V
, GATE pulls down
TMRH
Resetting a Fault Latch (LTC4252-±)
immediately and the LTC4252 shuts down. TIMER starts
a shutdown cooling cycle by discharging TIMER with
The latched circuit breaker fault of LTC4252-1 benefits
from long cooling time. It is reset by pulling the UV pin
5.8μA to the V
threshold. TIMER then charges with
TMRH
TMRL
5.8μA to the V
below V
with a switch. Reset is also accomplished by
threshold. There are four 5.8μA
UVLO
pulling the V pin momentarily below (V
– V ). A
discharge phases and three 5.8μA charge phases in this
shutdown cooling cycle spanning time points 2 and 3. At
time point 3, the LTC4252 automatic retry occurs with a
start-up cycle. Good thermal management techniques are
highlyrecommended;powerandthermaldissipationmust
be carefully evaluated when implementing the automatic
retry scheme.
IN
LKO
LKH
third reset method involves pulling the TIMER pin below
as shown in Figure 15. An initial timing cycle is
V
TMRL
skipped if TIMER is used for reset. An initial timing cycle
is generated if reset by the UV pin or the V pin.
IN
The duration of the TIMER reset pulse should be smaller
than the time taken to reach 0.2V at SS pin. With a single
425212fd
26
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
SWITCH RESETS LATCHED TIMER
SWITCH RELEASES SS
1
2 34
5
67 8 9
5.8μA
TIMER
V
V
TMRH
ꢁꢂꢋ"ꢆꢇꢆꢅꢆtꢆ*
5.8μA
5.8μA
DRN
TMRL
58μA
V
– V
GATEH
IN
GATE
SS
58μA
V
GATEL
ꢁꢋꢆtꢆꢀ7
+ V
)
)
ACL
OS
OS
ꢁꢋꢆtꢆꢀ7 + V
CB
ꢁꢋꢆtꢆ7
OS
V
V
ACL
CB
SENSE
DRAIN
V
V
DRNCL
DRNL
PWRGD
425212 F15
GATE START-UP
MOMENTARY DPST SWITCH RESET
Figure ±5. Pushbutton Reset of LTC4252-±’s Latched Fault
(All Waveforms Are Referenced to VEE)
CIRCUIT BREAKER TIMES OUT
RETRY
3 45
1
2
6
78 9 10
V
TMRH
ꢁꢂꢋ"ꢆꢇꢆꢅꢆtꢆ*
ꢁꢂꢋ"ꢆꢇꢆꢅꢆtꢆ*
DRN
5.8μA
5.8μA
5.8μA
DRN
5.8μA
5.8μA
5.8μA
5.8μA
5.8μA
GATEH
TIMER
5.8μA
V
TMRL
58μA
V
– V
IN
58μA
GATE
SS
V
GATEL
ꢁꢋꢆtꢆꢀ7
+ V
)
)
ACL
OS
OS
ꢁꢋꢆtꢆꢀ7 + V
CB
ꢁꢋꢆtꢆ7
OS
V
V
ACL
CB
SENSE
V
OUT
V
V
DRNCL
DRNL
DRAIN
PWRGD
425212 F16
GATE
START-UP
SHUTDOWN COOLING
CB FAULT
Figure ±6. Shutdown Cooling Timing Behavior of LTC4252-2 (All Waveforms Are Referenced to VEE)
425212fd
27
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
Analog Current Limit and Fast Current Limit
shown in Figure 18a. If a soft-start capacitor, C , is con-
SS
nected to this SS pin, the soft-start response is modified
from a linear ramp to an RC response (Equation 6), as
shown in Figure 18b. This feature allows load current to
slowly ramp-up at GATE start-up. Soft-start is initiated at
In Figure 17a, when SENSE exceeds V , GATE is
ACL
regulated by the analog current limit amplifier loop. When
SENSE drops below V , GATE is allowed to pull up. In
ACL
Figure 17b, when a severe fault occurs, SENSE exceeds
time point 3 by a TIMER transition from V
to V
TMRH
TMRL
V
FCL
and GATE immediately pulls down until the analog
(time points 1 to 2) or by the OV pin falling below the
current amplifier establishes control. If the severe fault
causes V to exceed V , the DRAIN pin is clamped
V
threshold after an OV condition. When the SS pin
OVLO
OUT
DRNCL
is below 0.2V, the analog current limit amplifier holds
GATE low. Above 0.2V, GATE is released and 58μA ramps
up the compensation network and GATE capacitance at
time point 4. Meanwhile, the SS pin voltage continues to
ramp up. When GATE reaches the MOSFET’s threshold,
the MOSFET begins to conduct. Due to the MOSFET’s high
at V
. I
flows into the DRAIN pin and is multiplied
DRNCL DRN
by 8. This extra current is added to the TIMER pull-up
current of 230μA. This accelerated TIMER current of
[230μA+8 • I ] produces a shorter circuit breaker fault
DRN
delay. Careful selection of C , R and MOSFET can help
T
D
prevent SOA damage in a low impedance fault condition.
g , the MOSFET current quickly reaches the soft-start
m
control value of V (t) (Equation 7). At time point 6, the
ACL
Soft-Start
GATE voltage is controlled by the current limit amplifier.
If the SS pin is not connected, this pin defaults to a linear
voltage ramp, from 0V to 2.2V in about 180μs (or 0V to
1.4V in 230μs for the LTC4252A) at GATE start-up, as
The soft-start control voltage reaches the circuit breaker
voltage, V , at time point 7 and the circuit breaker TIMER
CB
activates. As the load capacitor nears full charge, load
CB TIMES OUT
12
34
1
2
V
TMRH
V
TMRH
ꢁꢂꢋ"ꢆꢇꢆꢅꢆtꢆ*
DRN
ꢁꢂꢋ"ꢆꢇꢆꢅꢆtꢆ*
DRN
5.8μA
TIMER
TIMER
5.8μA
GATE
SS
GATE
SS
V
V
ACL
CB
V
FCL
SENSE
SENSE
V
ACL
V
CB
V
V
OUT
OUT
V
DRNCL
DRAIN
DRAIN
425212 F17
PWRGD
PWRGD
(±7a) Analog Current Limit Fault
(±7b) Fast Current Limit Fault
Figure ±7. Current Limit Behavior (All Waveforms Are Referenced to VEE)
425212fd
28
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
END OF INTIAL TIMING CYCLE
END OF INTIAL TIMING CYCLE
12 34 567
7a
8
9
10 11
5.8μA
12 3 4 5 6
7
8
9
10 11
5.8μA
V
V
ꢁꢂꢋ"ꢆꢇꢆꢅꢆtꢆ*
ꢁꢂꢋ"ꢆꢇꢆꢅꢆtꢆ*
TMRH
TMRH
DRN
DRN
TIMER
GATE
TIMER
GATE
V
V
TMRL
TMRL
58μA
58μA
V
– V
V
– V
GATEH
IN
GATEH
IN
V
V
GS(th)
GS(th)
58μA
+ V
58μA
ꢁꢋꢆtꢆꢀ7
ꢁꢋꢆtꢆꢀ7
)
+ V
)
OS
ACL
OS
ACL
ꢁꢋꢆtꢆꢀ7 + V
)
OS
ꢁꢋꢆtꢆꢀ7 + V
)
SS
SS
CB
CB
OS
ꢁꢋꢆtꢆ7
ꢁꢋꢆtꢆ7
OS
OS
V
V
V
ACL
CB
ACL
SENSE
SENSE
V
CB
V
V
DRNCL
DRNCL
V
V
DRNL
DRNL
DRAIN
DRAIN
PWRGD
PWRGD
425212 F18
(±8a) Without External CSS
(±8b) With External CSS
Figure ±8. Soft-Start Timing (All Waveforms Are Referenced to VEE)
current begins to decline below V (t). The current limit
ACL
VCB
R4 VSUPPLY(MAX)
R6
=
loop shuts off and GATE releases at time point 8. At time
point 9, the SENSE voltage falls below V and TIMER
(16)
CB
deactivates.
If R6 is 27Ω, R4 is 38.3k. The peak circuit breaker power
limit is:
Large values of C can cause premature circuit breaker
SS
2
time out as V (t) may exceed the V potential during
ACL
CB
V
SUPPLY(MIN) +VSUPPLY(MAX)
(
)
the circuit breaker delay. The load capacitor is unable to
POWERMAX
=
achieve full charge in one GATE start-up cycle. A more
4•VSUPPLY(MIN) •VSUPPLY(MAX)
•POWERSUPPLY(MIN)
serious side effect of large C values is SOA duration
SS
may be exceeded during soft-start into a low impedance
=1.064•POWERSUPPLY(MIN)
load. A soft-start voltage below V will not activate the
(17)
CB
circuit breaker TIMER.
when
Power Limit Circuit Breaker
V
= 0.5 • (V
+ V ) = 57V.
SUPPLY(MAX)
SUPPLY
SUPPLY(MIN)
Figure 19 shows the LTC4252A-1 in a power limit circuit
breaking application. The SENSE pin is modulated by the
Thepeakpoweratthefaultcurrentlimitoccursatthesupply
overvoltage threshold. The fault current limited power is:
board supply voltage, V
. The D1 Zener voltage, V
SUPPLY
Z
POWERFAULT
=
is set to be the same as the low supply operating voltage,
VSUPPLY
R6
R4
⎛
⎝
⎞
V
= 43V. If the goal is to have the high supply
SUPPLY(MIN)
operating voltage, V
• V – V
–V •
(
)
⎜
⎟
⎠
ACL
SUPPLY
Z
= 71V giving the same
RS
SUPPLY(MAX)
(18)
power at V
selected using the ratio:
, then resistors R4 and R6 are
SUPPLY(MIN)
425212fd
29
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
–48RTN
+
R
IN
R4
38.3k
C
L
100μF
3× 1.8k
1/4W EACH
C
IN
†
R5
D
1μF
LOAD
EN
IN
**
–48RTN
100k
DDZ13B
1
(SHORT PIN)
R1
D1
V
IN
392k
*
V
BZV85C43
OUT
LTC4252A-1
PWRGD
1ꢀ
9
8
2
7
6
4
UV
R
1M
D
OV
DRAIN
GATE
10
3
Q1
IRF530S
TIMER
SS
R6 27Ω
R2
30.1k
1ꢀ
C
T
SENSE
V
EE
0.68μF
R
R
S
0.02Ω
C
5
C1
10nF
C
10Ω
C
SS
68nF
C
10nF
425212 F19
–48V
*FMMT493
**DIODES, INC
RECOMMENDED FOR HARSH ENVIRONMENTS
†
Figure ±9. Power Limit Circuit Breaking Application
Circuit Breaker with Foldback Current Limit
Capacitor C3 and resistor R4 prevent Q1 from momen-
tarily turning on when the power pins first make contact.
Without C3 and R4, capacitor C2 pulls the gate of Q1 up
Figure 20 shows the LTC4252A in a foldback current limit
application.WhenV isshortedtothe–48VRTNsupply,
OUT
to a voltage roughly equal to V • C2/C
before the
EE
GS(Q1)
current flows through resistors R4 and R5. This results in
a voltage drop across R5 and a corresponding reduction
LTC4252A powers up. By placing capacitor C3 in parallel
with the gate capacitance of Q1 and isolating them from
C2 using resistor R4, the problem is solved. The value of
C3 is given by:
in voltage drop across the sense resistor, R , as the ACL
S
amplifier servos the sense voltage between the SENSE
and V pins to about 60mV. The short-circuit current
EE
VSUPPLY(MAX)
through R reduces as the V
voltage increases during
S
OUT
C3=
• C2+C
(
)
GD(Q1)
anoutputshort-circuitcondition.Withoutfoldbackcurrent
limiting resistor R5, the current is limited to 3A during
analog current limit. With R5, the short-circuit current is
VGS(TH),Q1
(20)
C3 ≈ 35 • C2 for V
= 71V
SUPPLY(MAX)
limited to 0.5A when V
is shorted to 71V.
OUT
whereV
andV
istheMOSFET’sminimumgatethreshold
isthemaximumoperatinginputvoltage.
GS(TH),Q1
Inrush Control Without a Sense Resistor
During Power-Up
SUPPLY(MAX)
Diode-ORing
Figure 21 shows the LTC4252A in an application where the
inrushcurrentiscontrolledwithoutasenseresistorduring
power-up. This setup is suitable only for applications that
don’t require short-circut protection from the LTC4252A.
Resistor R4 and capacitor C2 act as a feedback network
to accurately control the inrush current. The C2 capacitor
can be calculated with the following equation:
Figure22showstheLTC4252usedasdiode-oringwithHot
Swap capability in a dual –48V power supply application.
The conventional diode-OR method uses two high power
diodes and heat sinks to contain the large heat dissipation
of the diodes. With the LTC4252 controlling the external
FETs Q2 and Q3 in a diode-OR manner, the small turn-on
voltage across the fully enhanced Q2 and Q3 reduces the
power dissipation significantly.
I
GATE •CL
C2=
I
(19)
= 58μA and C is the total load capacitance.
INRUSH
where I
GATE
L
425212fd
30
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
–48RTN
+
R
IN
C
L
3× 1.8k
100μF
1/4W EACH
LOAD
R3
5.1k
†
C
IN
EN
D
IN
1μF
**
–48RTN
(SHORT PIN)
DDZ13B
1
R1
V
IN
392k
*
LTC4252A-1
PWRGD
V
1ꢀ
2
OUT
8
9
OV
UV
R
1M
D
7
DRAIN
R4
38.3k
C1
10nF
R
10Ω
G
10
3
6
4
Q1
IRF530S
TIMER
SS
GATE
R5 27Ω
R2
30.1k
1ꢀ
C
T
SENSE
V
EE
0.68μF
R
C
R
S
5
10Ω
C
C
0.02Ω
SS
C
10nF
68nF
425212 F20
–48V
†
*MOC207 **DIODES, INC
RECOMMENDED FOR HARSH ENVIRONMENTS
Figure 20. Circuit Breaker with Foldback Current Limit Application
–48RTN
+
R
IN
C
L
3× 1.8k
100μF
1/4W EACH
LOAD
R3
5.1k
†
C
EN
D
IN
IN
**
–48RTN
(SHORT PIN)
1
1μF
DDZ13B
R1
392k
1ꢀ
V
IN
*
LTC4252A-1
V
2
OUT
8
9
OV
UV
PWRGD
R
1M
D
7
DRAIN
C2
10nF
100V
C1
10nF
R4
1k
1ꢀ
R
10Ω
G
10
3
6
4
Q1
TIMER
SS
GATE
IRF530S
R2
30.1k
1ꢀ
C
T
SENSE
V
EE
0.68μF
C3
330nF
25V
5
C
SS
68nF
425212 F21
–48V
†
*MOC207
**DIODES, INC
RECOMMENDED FOR HARSH ENVIRONMENTS
Figure 2±. Inrush Control Without a Sense Resistor Application
At power-up, Q5 and Q8 are held off low by the SS pin
of the LTC4252; resistors R5 and R8 pull the SENSE pin
rises as current flows into R5 and R8 through resistors R3
andR6. TheACLamplifieroftheLTC4252servosthesense
voltage to about 100mV as the GATE voltage regulates Q2
and Q3. Current flows into R4, Q4 and R7, Q7 as Q2 and
Q3 turn on. The respective node voltages at the R3 and R4
connection and the R6 and R7 connection are always kept
equal to their respective sense voltages by the Q4 and Q2
closed to V . V is connected to the power supply with
EE EE
lower voltage through the body diodes Q2 or Q3 until Q2
or Q3 is turned on. This allows the LTC4252 to perform
a start-up cycle and ramp up the SS and GATE voltage.
As the SS voltage ramps up to 2.2V, it turns on Q5 and Q8
andpullsTIMERlowthroughQ6andQ9.Thesensevoltage
V
drop and the Q7 and Q3 V drop assuming the Q5
and Q8 V drop is negligible.
DS
DS
DS
425212fd
31
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
Hot Swap SECTION
–48RTN
R
IN1
3 × 1.8k IN SERIES
1/4W EACH
LOAD
MODULE
†
C
IN
D
IN1
1μF
**
R1
DDZ13B
1
R
D
402k
1M
7
8
V
IN
6
UV/OV
TIMER
DRAIN
C1
10nF
5
3
Q1
IRF530S
GATE
R
C1
LTC4252-1
C
R2
32.4k
T
10Ω
0.33μF
C
C1
22nF
2
SS
SENSE
V
EE
RS
0.02Ω
4
C
SS
68nF
DIODE-OR CIRCUIT FOR CHANNEL A
–48V A
R
IN2
3 × 1.8k IN SERIES
1/4W EACH
1
†
D
IN2
V
IN
R3
12k
**
9
2
7
DDZ13B
DRAIN
UV
PWRGD
C
IN2
1μF
R4
Q5
FDV301N
LTC4252-2
150Ω
10
3
4
6
TIMER
SENSE
Q4
BSS131
Q6
FDV301N
SS
OV
8
Q2
GATE
IRF530S
V
EE
R
R5
560Ω
C2
10μ
5
C
C2
22nF
DIODE-OR CIRCUIT FOR CHANNEL B
–48V B
R
IN3
3 × 1.8k IN SERIES
1/4W EACH
1
†
D
IN3
V
IN
**
R6
12k
9
2
7
DDZ13B
DRAIN
UV
PWRGD
C
IN3
1μF
R7
150Ω
Q8
FDV301N
LTC4252-2
10
3
4
6
TIMER
SENSE
Q7
Q9
FDV301N
SS
OV
BSS131
8
Q3
GATE
IRF530S
V
R
EE
R8
560Ω
C3
10Ω
5
C
C3
22nF
425212 F22
†
**DIODES, INC
RECOMMENDED FOR HARSH ENVIRONMENTS
Figure 22. –48V/2.5A Diode-OR Application
425212fd
32
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
The internal fault latches of the LTC4252 are disabled as
the TIMER pin is always held low by the SS voltage when
Q2 and Q3 are in analog current limit.
the current flow. The sense voltage is lifted up and causes
the fast comparator of LTC4252 to trip and pull the GATE
low instantly. The channel A supply short will not cause
Q3 of channel B diode-OR circuit to turn off.
If both power supplies from channel A and B are exactly
equal, then equal load current will flow through Q2 and
Q3 to the load module via the Hot Swap section.
Similarly, when the channel B supply is shorted to the
–48V RTN (or GND), large current flows into Q7 momen-
tarily and creates a voltage drop across R7, which in turn
reduces the gate-to-source voltage of Q7, thus limiting
the current flow. The increase in sense voltage will trip
the fast comparator of LTC4252 and pull the GATE low
instantly. The channel B supply short will not cause Q2
of channel A diode-OR circuit to turn off. The load short
at the output of Q1 is protected by the Hot Swap section.
If the channel A supply is greater than the channel B by
more than 100mV, the sense voltage will rise above the
fast comparator trip threshold of 200mV, the GATE will
be pulled low and Q2 is turned off. The GATE ramps up
and regulates Q2 when the channel A supply is equal to
the channel B supply. Likewise, if the channel B supply is
greater than channel A by more than 100mV, it trips the
fast comparator and GATE is pulled low and Q3 is turned
off.TheGATErampsupandregulatesQ3whenthechannel
B supply is equal to the channel A supply.
Using an EMI Filter Module
Many applications place an EMI filter module in the power
path to prevent switching noise of the module from being
injected back onto the power supply. A typical application
using the Lucent FLTR100V10 filter module is shown in
Figure 23. When using a filter, an optoisolator is required
to prevent common mode transients from destroying the
PWRGD and ON/OFF pins.
Resistors R4, R7 and external FETs Q4 and Q7 limit the
current flow into Q5 and Q8 during their respective sup-
ply source short. When the channel A supply is shorted
to the –48V RTN (or GND), large current flows into Q4
momentarily and creates a voltage drop across R4, which
in turn reduces the gate-to-source voltage of Q4, limiting
–48RTN
(LONG PIN)
R
IN
3× 1.8k
1/4W
1
2
9
8
†
+
+
+
C
V
V
5V
D
R3
–48RTN
IN
IN
OUT
IN
**
1μF
DDZ13B
5.1k
(SHORT PIN)
SENSE
1
7
R1
392k
1ꢀ
TRIM
V
IN
LTC4252A-1
OV
*
ON/OFF
+
2
8
9
C6
100μF
16V
PWRGD
LUCENT
JW050A1-E
7
+
+
V
V
OUT
UV
DRAIN
IN
LUCENT
FLTR100V10
C2
0.1μF
100V
R
D
1M
C1
10nF
+
C3
0.1μF
100V
C4
100μF
100V
C5
6
5
0.1μF
100V
–
10
3
6
4
SENSE
Q1
IRF530S
1N4003
TIMER
GATE
4
–
–
–
–
R2
30.1k
1ꢀ
V
IN
V
V
V
OUT
OUT
IN
SS
V
SENSE
R
10Ω
R
S
0.02Ω
CASE
3
CASE
C
EE
C
T
0.68μF
5
C
SS
68nF
C
10nF
C
425212 F23
–48V
†
*MOC207 **DIODES, INC
RECOMMENDED FOR HARSH ENVIRONMENTS
Figure 23. Typical Application Using a Filter Module
425212fd
33
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
3.00 0.102
(.118 .004)
(NOTE 3)
0.52
(.0205)
REF
8
7 6
5
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .006)
0.889 0.127
DETAIL “A”
0.254
(.010)
(.035 .005)
0° – 6° TYP
GAUGE PLANE
5.23
(.206)
MIN
1
2
3
4
3.20 – 3.45
(.126 – .136)
0.53 0.152
(.021 .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
0.65
(.0256)
BSC
0.42 0.038
(.0165 .0015)
TYP
SEATING
PLANE
0.22 – 0.38
0.1016 0.0508
RECOMMENDED SOLDER PAD LAYOUT
(.009 – .015)
(.004 .002)
0.65
(.0256)
BSC
TYP
NOTE:
MSOP (MS8) 0307 REV F
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
MS Package
±0-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
3.00 0.102
(.118 .004)
(NOTE 3)
0.497 0.076
(.0196 .003)
REF
10 9
8
7 6
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .006)
0.889 0.127
(.035 .005)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
5.23
(.206)
MIN
1
2
3
4 5
3.20 – 3.45
(.126 – .136)
0.53 0.152
(.021 .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
0.50
(.0197)
BSC
0.305 0.038
(.0120 .0015)
TYP
SEATING
PLANE
RECOMMENDED SOLDER PAD LAYOUT
0.17 – 0.27
(.007 – .011)
TYP
0.1016 0.0508
(.004 .002)
0.50
(.0197)
BSC
MSOP (MS) 0307 REV E
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
425212fd
34
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
REVISION HISTORY (Revision history begins at Rev C)
REV
DATE
DESCRIPTION
PAGE NUMBER
C
2/11
Revised Typical Application drawings
Revised Figures 2, 3, 4, 19, 20, 21, 22 and 23
Replaced Shunt Regulator section in Applications Information
Not recommended for new designs
1, 36
12, 14, 15, 30, 31, 32, 33
14
1
D
3/12
425212fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
TYPICAL APPLICATION
–48RTN
R
IN
+
C
L
2× 5.1k IN SERIES
LOAD
100μF
1/4W EACH
C
IN
†
D
1μF
IN
**
DDZ13B
–48RTN
(SHORT PIN)
1
V
OUT
V
R1
IN
R
402k
1ꢀ
D
LTC4252-1
1M
7
8
2
6
5
3
UV/OV
TIMER
SS
DRAIN
GATE
R2
Q1
IRF540S
32.4k
C
1ꢀ
T
SENSE
V
EE
150nF
R
C
10Ω
R
S
0.01Ω
R3
22Ω
4
C1
10nF
C
SS
PUSH
RESET
27nF
C
C
22nF
425212 F24
–48V
†
**DIODES, INC
RECOMMENDED FOR HARSH ENVIRONMENTS
Figure 24. –48V/5A Application
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1640AH/LT1640AL Negative High Voltage Hot Swap Controllers in SO-8
Negative High Voltage Supplies from –10V to –80V
Supplies from 9V to 80V, Latched Off/Autoretry
3V to 16.5V, Overvoltage Protection up to 33V
Operates from –6V to –16V
LT1641-1/LT1641-2
LTC1642
Positive High Voltage Hot Swap Controllers in SO-8
Fault Protected Hot Swap Controller
Negative Voltage Hot Swap Controller
Dual Supply Hot Swap Controller
LTC4214
LTC4220
2.2V to 16.5V Operation
LT4250
–48V Hot Swap Controller in SO-8
Active Current Limiting, Supplies from –20V to –80V
Fast Active Current Limiting, Supplies from –15V
LTC4251/LTC4251-1
LTC4253
–48V Hot Swap Controllers in SOT-23
–48V Hot Swap Controller with Sequencer
Fast Current Limiting with Three Sequenced Power Good Outputs,
Supplies from –15V
425212fd
LT 0312 REV D • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
© LINEAR TECHNOLOGY CORPORATION 2001
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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