LTC4259ACGW_技术文档

LTC4259A

Quad IEEE 802.3af

Power over Ethernet Controller

with AC Disconnect

U

FEATURES

DESCRIPTIO

The LTC^®4259A is a quad –48V Hot Swap^TMcontroller

designed for use in IEEE 802.3af compliant Power

SourcingEquipment(PSE).Itconsistsoffourindependent

ports, each with output current limit, short-circuit protec-

tion, complete Powered Device (PD) detection and classi-

ficationcapability,andprogrammablePDdisconnectusing

■

Controls Four Independent –48V Powered

Ethernet Ports

■

Each Port Includes:

– IEEE 802^®.3af Compliant PD Detection and

Classification

– Output Current Limit with Foldback

– Short-Circuit Protection with Fast Gate Pull-Down

– PD Disconnect Using AC or DC Sensing

– Power Good Indication

ACorDCsensing.UsedwithpowerMOSFETsandpassives

asinFigure1,theLTC4259AcanimplementacompleteIEEE

802.3af-compliant PSE.

Operates Autonomously or Controlled by I²C^TM

Serial Interface

■

The LTC4259A can operate autonomously or be controlled

2

by an I C serial interface. Up to 16 LTC4259As may coexist

4-Bit Programmable Digital Address Allows Control

of Up to 64 Ports

on the same data bus, allowing up to 64 powered Ethernet

ports to be controlled with only two digital lines. Fault con-

ditions are optionally signaled with the INT pin to eliminate

software polling.

■

Programmable INT Pin Eliminates Software Polling

Current and Duty Cycle Limits Protect External FETs

Available in a 36-Pin SSOP Package

U

External power MOSFETs, current sense resistors and di-

odes allow easy scaling of current and power dissipation

levels and provide protection against voltage and current

spikes and ESD events.

APPLICATIO S

■

IEEE 802.3af Compliant Endpoint and Midspan

Power Sources

IP Phone Systems

DTE Power Distribution

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

The LTC4259A is available in a 36-pin SSOP package.

■

Linear Technology also provides solutions for 802.3af PD

applications with the LTC4257 and LTC4257-1.

Hot Swap is a trademark of Linear Technology Corporation. 802 is a registered trademark of

Instutute of Electrical and Electronics Engineers, Inc. I²C is a trademark of Philips Electronics N.V.

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TYPICAL APPLICATIO

0.1µF

100V X7R

3.3V

0.1µF

INT

SHDN1 SHDN2SHDN3 SHDN4

V

OSCIN AUTO BYP

RESET

SCL

DD

SDAIN

SDAOUT

AD0

AD1

AD2

DETECT1

DETECT2

DETECT3

LTC4259A

0.1µF 100V

×4

SMAJ58A

×4

CMPD3003

×4

DETECT4

SENSE1 GATE1 OUT1 SENSE2 GATE2 OUT2 SENSE3 GATE3 OUT3 SENSE4 GATE4 OUT4

AD3

1k

×4

DGND AGND

V

EE

0.47µF

100V ×4

10k

R

S1

X7R

PORT1

PORT2

PORT3

PORT4

–48V

Q1

R

S2

0.1µF

Q2

R

S3

Q3

R

S4

4259A F01

Q4

RS1 TO RS4: 0.5Ω

Q1 TO Q4: IRFM120A

S1B ×4

Figure 1. Complete 4-Port Powered Ethernet Power Source

4259Af

1

LTC4259A

W W U W

U W

U

ABSOLUTE AXI U RATI GS

(Note 1)

PACKAGE/ORDER I FOR ATIO

TOP VIEW

Supply Voltages

ORDER PART

NUMBER

1

2

36 OSCIN

35 AUTO

RESET

BYP

V_DDto DGND .......................................... –0.3V to 5V

V

_EEto AGND ......................................... 0.3V to –70V

3

34

OUT1

INT

LTC4259ACGW

4

33 GATE1

32 SENSE1

31 OUT2

SCL

DGND to AGND (Note 2) .................................... ±1V

Digital Pins

5

SDAOUT

SDAIN

AD3

6

SCL, SDAIN, SDAOUT, INT, AUTO, RESET

SHDNn, ADn................. DGND – 0.3V to DGND + 5V

Analog Pins

7

30 GATE2

29 SENSE2

8

AD2

9

28

V

EE

AD1

10

11

12

13

14

15

16

17

18

27 OUT3

AD0

GATEn (Note 3) ................... V_EE– 0.3V to V_EE+ 12V

DETECTn Peak Currents (Note 4) .................. ±80mA

SENSEn ................................. V_EE– 0.3V to V_EE+ 1V

OUTn .................................... V_EE– 70V to V_EE+ 70V

OSCIN .......................... DGND – 0.3V to DGND + 5V

BYP Current .................................................... ±1mA

Operating Ambient Temperature Range...... 0°C to 70°C

Junction Temperature (Note 5)............................ 150°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

26 GATE3

25 SENSE3

24 OUT4

DETECT1

DETECT2

DETECT3

DETECT4

DGND

23 GATE4

22 SENSE4

21 AGND

20 SHDN4

19 SHDN3

V

DD

SHDN1

SHDN2

GW PACKAGE

36-LEAD PLASTIC SSOP

T_JMAX= 150°C, θ_JA= 80°C/W

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. AGND = DGND = 0V, V_DD= 3.3V, V_EE= –48V unless otherwise noted

(Note 6).

SYMBOL PARAMETER

Power Supplies

CONDITIONS

MIN

TYP

MAX

UNITS

V

Supply Voltage

Supply Current

●

3

3.3

4

–57

5

V

DD

EE

DD

EE

To Maintain IEEE Compliant Output (Note 7)

Normal Operation

–48

I

2.5

–2

mA

DD

EE

DD

EE

●

–5

100

mA

Classification Into a Short (V

= 0V) (Note 8)

DETECTn

V

UVLO Voltage

2.7

–31

–28

V

DDMIN

DD

EE

UVLO Voltage (Turning On)

UVLO Voltage (Turning Off)

V

– AGND

EEMINON

EEMINOFF

EE

Detection

I

Detection Current

First Point, V

= –10V

DETECTn

●

235

145

300

190

µA

DET

DETECTn

Second Point, V

= –3.5V

V

Detection Voltage Compliance

Open Circuit, Measured at DETECTn Pin

●

–20

17

–23

19

V

kΩ

DET

R

Minimum Valid Signature Resistance

Maximum Valid Signature Resistance

15.2

26.7

DETMIN

29

33

DETMAX

Classification

V

Classification Voltage

0mA < I

< 31mA

CLASS

●

–16.4

55

–21

75

V

CLASS

I

Classification Current Compliance

Classification Threshold Current

Into Short (V

= 0V)

mA

DETECT

Class 0-1

Class 1-2

Class 2-3

Class 3-4

●

5.5

13

21

31

45

6.5

14.5

23

7.5

16

25

35

51

mA

TCLASS

33

Class 4-Overcurrent

48

4259Af

2

LTC4259A

ELECTRICAL CHARACTERISTICS

(Note 6).

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. AGND = DGND = 0V, V_DD= 3.3V, V_EE= –48V unless otherwise noted

SYMBOL PARAMETER

Gate Driver

CONDITIONS

MIN

TYP

MAX

UNITS

I

GATE Pin Current

Gate On, V

Gate Off, V

= V

EE

●

–20

30

–50

50

–70

95

µA

mA

V

GON

GOFF

GPD

GATEn

GATE Pin Current

= V + 5V

EE

GATEn

GATE Pin Short-Circuit Pull-Down

V

= V + 5V

100

13

GATEn

EE

∆V

External Gate Voltage (V

– V

)

EE

I = –1µA (Note 3)

GATE

●

10

1

15

GATE

GATEn

Output Voltage Sense

V

Power Good Threshold Voltage

Out Pin Bias Current

V

– V

EE

●

2

3

V

PG

OUTn

I

0V > V

> –10V

OUT

●

–6

–18

µA

VOUT

–10V > V

> –30V

V

= –48V

–20

OUT

Current Sense

V

Overcurrent Detection Sense Voltage

Current Limit Sense Voltage

V

– V , V

= V (Note 9)

166

187.5

212.5

199

mV

CUT

LIM

SENSEn

EE OUT

EE

V

– V , V

= V

EE

= AGND – 30V

= AGND – 10V

201

30.2

224

mV

SENSEn

EE OUT

– V , V

EE OUT

– V , V

EE OUT

V

DC Disconnect Sense Voltage

Short-Circuit Sense Voltage

SENSE Pin Bias Current

V

– V

2.52

3.75

275

–50

4.97

mV

µA

MIN

SC

SENSEn

EE

I

V

= V

SENSE

SENSEn

EE

AC Disconnect (Note 10)

R

Input Impedance of OSCIN Pin

0.1V < V

< 3V, f < 200Hz

SINEIN

●

200

500

kΩ

OSCIN

VACD

OSCIN

A

Voltage Gain OSCIN to DETECT1, 2

Voltage Gain OSCIN to DETECT3, 4

Port Powered, PD Not Present

●

–2.7

2.7

–3

3

–3.3

3.3

V/V

I

AC Disconnect DETECTn Output Current Port Powered, –6V < V

< 0V

●

±600

µA

ACDMAX

ACDMIN

DETECTn

Remain Connected DETECT Pin Current Port Powered, V

= –3.4V

150

200

260

DETECTn

Digital Interface

V

Digital Output Low Voltage

I

= 3mA, I = 3mA

●

0.4

0.7

V

OLD

SDAOUT

INT

= 5mA, I = 5mA

INT

V

Digital Input Low Voltage

Digital Input High Voltage

SCL, SDAIN, RESET, SHDNn, AUTO

AD0 to AD3, RESET, SHDNn

AUTO

●

0.8

V

ILD

IHD

2.4

R

Pull-Up Resistor to V

50

kΩ

PU

PD

DD

Pull-Down Resistor to DGND

AC Characteristics

t

Detection Delay

From Detect Command or Application of PD to Port

to Detect Complete

●

170

590

ms

DETDLY

t

Detection Duration

Classification Delay

Time to Measure PD Signature Resistance (Figure 2)

●

170

230

52

ms

DET

From Successful Detect in Auto or Semiauto Mode

to Class Complete

From Classify Command in Manual

10.1

CLSDLY

●

10.1

420

13

ms

t

Classification Duration

(Figure 2)

CLASS

PON

Power On Delay, Auto Mode

From Valid Detect to Port On in Auto Mode (Figure 2)

●

90

1

ms

From Port On Command to GATE Pin Current = I

(Note 10)

GON

t

Maximum Current Limit Duration During

Port Start-Up

t

= 0, t

= 1, t

= 0 (Figure 3)

●

50

25

100

200

60

30

120

240

70

35

140

280

ms

START

START1

START0

= 1

= 0

= 1

4259Af

3

LTC4259A

ELECTRICAL CHARACTERISTICS

(Note 6).

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. AGND = DGND = 0V, V_DD= 3.3V, V_EE= –48V unless otherwise noted

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

t

Maximum Current Limit Duration After

Port Start-Up

t

= 0, t

= 1, t

= 0 (Figure 3)

●

50

25

100

200

60

30

120

240

70

35

140

280

ms

ICUT

ICUT1

ICUT0

= 1

= 0

= 1

DC

Maximum Current Limit Duty Cycle

Disconnect Delay

Reg16h = 00h

●

5.8

6.3

6.7

%

CLMAX

t

= 0, t

= 1, t

= 0 (Figures 4, 5)

●

300

75

150

600

360

90

180

720

400

100

200

800

ms

DIS

DIS1

DIS0

= 1

= 0

= 1

t

DC Disconnect Minimum Pulse

Width Sensitivity

V

– V > 5mV, V = –48V (Figure 4)

OUTn

●

0.02

1

ms

VMIN

SENSEn

EE

(Note 11)

2

I C Timing

f

t

Clock Frequency

(Note 11)

●

400

kHz

µs

ns

µs

ns

SCLK

Bus Free Time

Figure 6 (Notes 11, 12)

(Notes 11, 12, 13)

1.3

600

1.3

600

150

200

600

20

1

Start Hold Time

2

SCL Low Time

3

SCL High Time

4

Data Hold Time

5

Data Set-Up Time

6

Start Set-Up Time

Stop Set-Up Time

SCL, SDAIN Rise Time

SCL, SDAIN Fall Time

Fault Present to INT Pin Low

Stop Condition to INT Pin Low

ARA to INT Pin High Time

7

8

300

150

200

300

r

20

f

20

FLTINT

STOPINT

ARAINT

(Notes 11, 12, 13)

60

(Notes 11, 12)

20

Note 1: Absolute Maximum Ratings are those values beyond which the life

of the device may be impaired.

Note 7: The LTC4259A is designed to maintain a port voltage of –46.6V to

–57V and the V supply voltage range accounts for the drop across the

EE

diode, MOSFET and sense resistor.

Note 2: DGND and AGND should be tied together in normal operation.

Note 3: An internal clamp limits the GATE pins to a minimum of 12V above

Note 8: V supply current, while classifying a short, is measured

EE

indirectly by measuring the DETECTn pin current while classifying a short.

V

. Driving this pin beyond the clamp may damage the part.

EE

Note 9: The LTC4259A implements overload current detection per IEEE

Note 4: When a port powers on or off, the transient voltage on the port

802.3af. The minimum overload current (I ) is dependent on port

CUT

couples through C (Figure 16). The LTC4259A contains internal

DET

voltage; I

= 15.4W/V

. An IEEE compliant system using the

CUT_MIN

PORT_MIN

protection circuitry to withstand transient currents of up to 80mA for 5ms.

As long as the absolute value of the current remains below 80mA, the

LTC4259A will keep the voltage at the DETECTn pin within the absolute

LTC4259A should maintain port voltage above –46.6V.

Note 10: Unless otherwise specified, AC disconnect specifications require

the following conditions: the DETECT pin is connected to the port as

shown in Figure 1, a valid sine wave is applied to OSCIN, the OSCFAIL bit

is cleared and the AC Disconnect Enable bits are set.

maximum voltage range. A properly sized R

should limit the current to

DET

less than 60mA.

Note 5: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 6: All currents into device pins are positive; all currents out of device

pins are negative. All voltages are referenced to ground (AGND and DGND)

unless otherwise specified.

Note 11: Guaranteed by design, not subject to test.

Note 12: Values measured at V and V

Note 13: If fault occurs during an I C transaction, the INT pin will not be

pulled down until a stop condition is present on the I C bus.

.

ILD

IHD

2

4259Af

4

LTC4259A

W U

TEST TI I G

PD

INSERTED

V

0V

PORTn

t

DET

PORT

TURN ON

(AUTO MODE)

V

CLASS

V

T

V

EE

GATEn

INT

4259A F02

t

CLSDLY

t

CLASS

t

PON

DETDLY

Figure 2. Detect, Class and Turn-On Timing in Auto or Semiauto Modes

V

LIM

V

CUT

V

TO V

EE

SENSEn

0V

t

, t

START ICUT

INT

4259A F03

Figure 3. Current Limit Timing

V

OSCIN

V

OUTn

V

SENSEn

V

MIN

I

TO V

ACDMIN

EE

I

DETECTn

PD REMOVED

INT

t

DIS

INT

VMIN

4259A F04

t

DIS

4259A F05

Figure 4. DC Disconnect Timing

Figure 5. AC Disconnect Timing

t

3

t

r

t

4

t

f

SCL

t

7

t

8

t

2

5

6

SDA

4259A F06

t

1

Figure 6. I²C Interface Timing

4259Af

5

LTC4259A

W U

W

TI I G DIAGRA S

SCL

SDA

AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

0

1

0

START BY

MASTER

ACK BY

SLAVE

ACK BY

SLAVE

ACK BY

SLAVE

STOP BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

REGISTER ADDRESS BYTE

FRAME 3

DATA BYTE

4259A F07

Figure 7. Writing to a Register

SCL

SDA

AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK

AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

0

1

0

1

0

START BY

MASTER

ACK BY

SLAVE

ACK BY

SLAVE

REPEATED

START BY

MASTER

ACK BY

SLAVE

NO ACK BY

MASTER

STOP BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

REGISTER ADDRESS BYTE

FRAME 1

FRAME 2

DATA BYTE

SERIAL BUS ADDRESS BYTE

4259A F08

Figure 8. Reading from a Register

SCL

SDA

0

1

0

AD3 AD2 AD1 AD0 R/W

FRAME 1

ACK

D7 D6 D5 D4 D3 D2 D1 D0

ACK

STOP BY

MASTER

START BY

MASTER

ACK BY

SLAVE

NO ACK BY

MASTER

FRAME 2

DATA BYTE

SERIAL BUS ADDRESS BYTE

4259A F09

Figure 9. Reading the Interrupt Register (Short Form)

SCL

SDA

0

1

0

R/W

ACK

0

1

0

AD3 AD2 AD1 AD0

1

ACK

STOP BY

MASTER

START BY

MASTER

ACK BY

SLAVE

NO ACK BY

MASTER

FRAME 1

ALERT RESPONSE ADDRESS BYTE

FRAME 2

SERIAL BUS ADDRESS BYTE

4259A F10

Figure 10. Reading from Alert Response Address

4259Af

6

LTC4259A

U

PI FU CTIO S

RESET (Pin 1): Chip Reset, Active Low. When the RESET

pin is low, the LTC4259A is held inactive with all ports off

and all internal registers reset to their power-up states.

When RESET is pulled high, the LTC4259A begins normal

operation. RESET can be connected to an external capaci-

tor or RC network to provide a power turn-on delay.

Internal filtering of the RESET pin prevents glitches less

than 1µs wide from resetting the LTC4259A. Pull RESET

high with ≤10k or tie to V_DD.

AD3(Pin7):AddressBit3.Tietheaddresspinshighorlow

to set the I²C serial address to which the LTC4259A

responds. This address will be (010A₃A₂A₁A₀)_b. Pull AD3

high or low with ≤10k or tie to V_DDor DGND.

AD2 (Pin 8): Address Bit 2. See AD3.

AD1 (Pin 9): Address Bit 1. See AD3.

AD0 (Pin 10): Address Bit 0. See AD3.

DETECT1 (Pin 11): Detect Sense, Port 1. The LTC4259A

Powered Device (PD) detection, classification and AC

disconnect hardware monitors port 1 with this pin. Con-

nect DETECT1 to the output port via a 0.47µF 100V X7R

capacitor in series with a 1k resistor, both in parallel with

a low leakage diode (see Figure 1). The resistor and

capacitor may be eliminated if AC disconnect is not used.

BYP (Pin 2): Bypass Output. The BYP pin is used to

connect the internally generated –20V supply to an exter-

nal 0.1µF bypass capacitor. Use a 100V rated 0.1µF, X7R

capacitor.DonotconnecttheBYPpintoanyotherexternal

circuitry.

INT (Pin 3): Interrupt Output, Open Drain. INT will pull low

when any one of several events occur in the LTC4259A. It

will return to a high impedance state when bits 6 or 7 are

set in the Reset PB register (1Ah). The INT signal can be

used to generate an interrupt to the host processor,

eliminating the need for continuous software polling.

Individual INT events can be disabled using the Int Mask

register (01h). See Register Functions and Applications

Information for more information. The INT pin is only

updated between I²C transactions.

DETECT2(Pin12):DetectionSense,Port2.SeeDETECT1.

DETECT3(Pin13):DetectionSense,Port3.SeeDETECT1.

DETECT4(Pin14):DetectionSense,Port4.SeeDETECT1.

DGND (Pin 15): Digital Ground. DGND should be con-

nected to the return from the 3.3V supply. DGND and

AGND should be tied together.

V_DD(Pin 16): Logic Power Supply. Connect to a 3.3V

power supply relative to DGND. V_DDmust be bypassed to

DGND near the LTC4259A with at least a 0.1µF capacitor.

SCL (Pin 4): Serial Clock Input. High impedance clock

input for the I²C serial interface bus. The SCL pin should

be connected directly to the I²C SCL bus line.

SHDN1 (Pin 17): Shutdown Port 1, Active Low. When

pulled low, SHDN1 shuts down port 1, regardless of the

state of the internal registers. Pulling SHDN1 low is

equivalent to setting the Reset Port 1 bit in the Reset

Pushbutton register (1Ah). Internal filtering of the SHDN1

pin prevents glitches less than 1µs wide from reseting the

LTC4259A. Pull SHDN1 high with ≤10k or tie to V_DD.

SDAOUT (Pin 5): Serial Data Output, Open Drain Data

OutputfortheI²CSerialInterfaceBus.TheLTC4259Auses

two pins to implement the bidirectional SDA function to

simplify optoisolation of the I²C bus. To implement a stan-

dardbidirectionalSDApin,tieSDAOUTandSDAINtogether.

See Applications Information for more information.

SHDN2 (Pin 18): Shutdown Port 2, Active Low. See

SDAIN(Pin6):SerialDataInput.Highimpedancedatainput

for the I²C serial interface bus. The LTC4259A uses two

pins to implement the bidirectional SDA function to sim-

plify optoisolation of the I²C bus. To implement a standard

bidirectional SDA pin, tie SDAOUT and SDAIN together.

See Applications Information for more information.

SHDN1.

SHDN3 (Pin 19): Shutdown Port 3, Active Low. See

SHDN1.

SHDN4 (Pin 20): Shutdown Port 4, Active Low. See

SHDN1.

4259Af

7

LTC4259A

U

PI FU CTIO S

AGND (Pin 21): Analog Ground. AGND should be con-

nected to the return from the –48V supply. AGND and

DGND should be tied together.

SENSE3(Pin25):Port3CurrentSenseInput.SeeSENSE4.

GATE3 (Pin 26): Port 3 Gate Drive. See GATE4.

OUT3 (Pin 27): Port 3 Output Voltage Monitor. See OUT4.

SENSE4 (Pin 22): Port 4 Current Sense Input. SENSE4

monitors the external MOSFET current via a 0.5Ω sense

resistor between SENSE4 and V_EE. Whenever the voltage

across the sense resistor exceeds the overcurrent detec-

tionthresholdV_CUT, thecurrentlimitfaulttimercountsup.

Ifthevoltageacrossthesenseresistorreachesthecurrent

limit threshold V_LIM(typically 25mV/50mA higher), the

GATE4 pin voltage is lowered to maintain constant current

in the external MOSFET. See Applications Information for

further details. If the port is unused, the SENSE4 pin must

be tied to V_EE.

V

_EE(Pin 28): –48V Supply Input. Connect to a –48V to

–57V supply, relative to AGND.

SENSE2(Pin29):Port2CurrentSenseInput.SeeSENSE4.

GATE2 (Pin 30): Port 2 Gate Drive. See GATE4.

OUT2 (Pin 31): Port 2 Output Voltage Monitor. See OUT4.

SENSE1(Pin32):Port1CurrentSenseInput.SeeSENSE4.

GATE1 (Pin 33): Port 1 Gate Drive. See GATE 4.

OUT1 (Pin 34): Port 1 Output Voltage Monitor. See OUT4.

GATE4 (Pin 23): Port 4 Gate Drive. GATE4 should be

connected to the gate of the external MOSFET for port 4.

When the MOSFET is turned on, a 50µA pull-up current

sourceisconnectedtothepin.Thegatevoltageisclamped

to 13V (typ) above V_EE. During a current limit condition,

the voltage at GATE4 will be reduced to maintain constant

current through the external MOSFET. If the fault timer

expires, GATE4 is pulled down with 50µA, turning the

MOSFET off and recording a t_ICUTor t_STARTevent. If the

port is unused, float the GATE4 pin or tie it to V_EE.

AUTO (Pin 35): Auto Mode Input. Auto mode is intended

to allow the LTC4259A to detect and power up a PD even

if there is no host controller present on the I²C bus. The

voltage of the AUTO pin determines the state of the

internal registers when the LTC4259A is reset or comes

out of V_DDUVLO (see the Register map in Table 1). The

states of these register bits can subsequently be changed

via the I²C interface if desired. The real-time state of the

AUTO pin can be read at bit 0 in the Pin Status register

(11h). Pull AUTO high or low with ≤10k or tie to V_DDor

DGND.

OUT4 (Pin 24): Port 4 Output Voltage Monitor. OUT4

should be connected to the output port through a 10k

series resistor. A current limit foldback circuit limits the

power dissipation in the external MOSFET by reducing the

current limit threshold when the port voltage is within 18V

ofAGND.Theport4PowerGoodbitissetwhenthevoltage

from OUT4 to V_EEdrops below 2V (typ). A 2.5MΩ resistor

is connected internally from OUT4 to AGND. If the port is

unused, the OUT4 pin can be tied to AGND or allowed to

float.

OSCIN (Pin 36): Oscillator Input. Connect to an oscillating

signal source, preferably a sine wave, of approximately

100Hz with 2V peak-to-peak amplitude, negative peaks

above –0.3V and positive peaks below 2.5V. When a port

is powered and AC disconnect is enabled, this signal is

amplified and driven onto the appropriate DETECT pin to

determine the AC impedance of the PD.

4259Af

8

LTC4259A

W

TABLE 1. REGISTER AP

4259Af

9

LTC4259A

U

REGISTER FU CTIO S

Interrupt Registers

theLTC4259Aisawaitingfurtherinstructions.InSemiauto

or Auto modes, these bits indicate that the Detect Status

and Class Status bits in the Port Status registers are valid.

The Detect Event bits latch high and will remain high until

cleared by reading from address 05h.

Interrupt (Address 00h): Interrupt Register, Read Only. A

transition to logical 1 of any bit in this register will assert

the INT pin (Pin 3) if the corresponding bit in the Int Mask

registerisset. EachbitisthelogicalORofthecorrespond-

ingbitsintheEventregisters.TheInterruptregisterisRead

Only and its bits cannot be cleared directly. To clear a bit

intheInterruptregister, clearthecorrespondingbitsinthe

appropriateStatusorEventregistersorsetbit7intheReset

Pushbutton register (1Ah).

Detect Event CoR (Address 05h): Detect Event Register,

Clear on Read. Read this address to clear the Detect Event

register.Address05hreturnsthesamedataasaddress04h,

and reading address 05h clears all bits at both addresses.

FaultEvent(Address06h):FaultEventRegister,ReadOnly.

IntMask(Address01h):InterruptMask,Read/Write.Alogic

1 in any bit of the Int Mask register allows the correspond-

ing Interrupt register bit to assert the INT pin if it is set. A

logic 0 in any bit of the Int Mask register prevents the cor-

responding Interrupt bit from affecting the INT pin. The

actual Interrupt register bits are unaffected by the state of

the Int Mask register.

The lower four bits in this register indicate that a

t_ICUTfaulthasoccurredatthecorrespondingport;thelogi-

cal OR of these four bits appears in the Interrupt register

asthet_ICUTFaultbit. TheupperfourbitsindicatethataDis-

connect event has occurred at the corresponding port; the

logical OR of these four bits appears in the Interrupt reg-

ister as the Disconnect bit. The Fault Event bits latch high

and will remain high until cleared by reading from address

07h.

Event Registers

Power Event (Address 02h): Power Event Register, Read

Only. The lower four bits in this register indicate that the

corresponding port Power Enable status bit has changed;

the logical OR of these four bits appears in the Interrupt

register as the Pwr Enable Event bit. The upper four bits

indicatethatthecorrespondingportPowerGoodstatusbit

has changed; the logical OR of these four bits appears in

theInterruptregisterasthePwrGoodEventbit.ThePower

Event bits latch high and will remain high until cleared by

reading from address 03h.

FaultEventCoR(Address07h):FaultEventRegister,Clear

on Read. Read this address to clear the Fault Event regis-

ter.Address07hreturnsthesamedataasaddress06hand

reading address 07h clears all bits at both addresses.

t_STARTEvent (Address 08h): t_STARTEvent Register, Read

Only.Thelowerfourbitsinthisregisterindicatethatat_START

faulthasoccurredatthecorrespondingport;thelogicalOR

of these four bits appears in the Interrupt register as the

t_STARTFault bit. The t_STARTEvent bits latch high and will

remainhighuntilclearedbyreadingfromaddress09h.The

upper four bits in this register are reserved and will always

read as 0.

Power Event CoR (Address 03h): Power Event Register,

Clear on Read. Read this address to clear the Power Event

register.Address03hreturnsthesamedataasaddress02h

and reading address 03h clears all bits at both addresses.

t

_STARTEvent CoR (Address 09h): t_STARTEvent Register,

Clear on Read. Read this address to clear the Fault Event

register.Address09hreturnsthesamedataasaddress08h

and reading address 09h clears all bits at both addresses.

Detect Event (Address 04h): Detect Event Register, Read

Only.Thelowerfourbitsinthisregisterindicatethatatleast

one detection cycle for the corresponding port has com-

pleted; the logical OR of these four bits appears in the In-

terrupt register as the Detect Complete bit. The upper four

bits indicate that at least one classification cycle for the

correspondingporthascompleted;thelogicalORofthese

fourbitsappearsintheInterruptregisterastheClassCom-

plete bit. In Manual mode, this register indicates that the

requesteddetection/classificationcyclehascompletedand

SupplyEvent(Address0Ah):SupplyEventRegister,Read

Only. Bit 1, Osc Fail, sets when the signal at Pin 36, OSCIN,

is absent or does not have the required amplitude and AC

disconnectcannotoperateproperly.TheOscFailbitlatches

high and will remain high until cleared by reading at 0Bh.

TheOscFailbitissetafterpoweronorresetunlesstheV_EE

supply is not present. Power is removed on ports with AC

4259Af

10

LTC4259A

U

REGISTER FU CTIO S

disconnect enabled independently of the state of the Osc

Failbit.SeeACDisconnectunderApplicationsInformation

for more details. Bit 4 indicates that V_EEhas dropped be-

low the V_EEUVLO level (typically –28V). Bit 5 signals that

the V_DDsupply has dropped below the V_DDUVLO thresh-

old. Bit 7 indicates that the LTC4259A die temperature has

exceeded its thermal shutdown limit (see Note 5 under

ElectricalCharacteristics).ThelogicalORofbits1,4,5and

7 appears in the Interrupt register as the Supply Fault bit.

SeetheMiscConfigregisterforinformationonmaskingthe

OscFailbitoutoftheSupplyFaultinterrupt.Theremaining

bits in the register are reserved and will always read as 0.

The Supply Event bits latch high and will remain high until

cleared by reading from address 0Bh.

powergoodbitsarelatchedhighandareonlyclearedwhen

a port is turned off or the LTC4259A is reset.

Pin Status (Address 11h): External Pin Status, Read Only.

This register reports the real time status of the AUTO

(Pin 35) and AD0-AD3 (Pins 7-10) digital input pins. The

logicstateoftheAUTOpinappearsatbit 0andtheAD0-AD3

pins at bits 2-5. The remaining bits are reserved and will

read as 0. AUTO affects the initial states of some of the

LTC4259A configuration registers at start-up but has no

effect after start-up and can be used as a general purpose

input if desired, as long as it is guaranteed to be in the

appropriate state at start-up.

Configuration Registers

Supply Event CoR (Address 0Bh): Supply Event Register,

Clear on Read. Read this address to clear the Fault Event

register.Address0Bhreturnsthesamedataasaddress0Ah,

and reading address 0Bh clears all bits at both addresses.

OperatingMode(Address12h):OperatingModeConfigu-

ration,Read/Write.Thisregistercontainsthemodebitsfor

eachofthefourportsintheLTC4259A.SeeTable1formode

bitencoding.Atpower-up,allbitsinthisregisterwillbeset

to the logic state of the AUTO pin (Pin 35). See Operating

Modes in the Applications Information section.

Status Registers

Port 1 Status (Address 0Ch): Port 1 Status Register, Read

Only. This register reports the most recent detection and

classification results for port 1. Bits 0-2 report the status

ofthemostrecentdetectionattemptattheportandbits4-6

report the status of the most recent classification attempt

at the port. If power is on, these bits report the detection/

classification status present just before power was turned

on. If power is turned off at the port for any reason, all bits

inthisregisterwillbecleared.SeeTable1fordetectionand

classification status bit encoding.

Disconnect Enable (Address 13h): Disconnect Enable

Register, Read/Write. The lower four bits of this register

enable or disable DC disconnect detection circuitry at the

corresponding port. If the DC Discon Enable bit is set the

port circuitry will turn off power if the current draw at the

portfallsbelowI_MINformorethant_DIS.I_MINisequaltoV_MIN

/

R_S, where R_Sis the sense resistor and should be 0.5Ω for

IEEE 802.3af compliance. If the bit is clear the port will not

remove power due to low current.

The upper four bits enable or disable AC disconnect on the

correspondingport.Whenaport’sACdisconnectbitisset,

the LTC4259A senses the impedance of that port by forc-

ing an AC voltage on the port’s DETECT pin and measuring

the AC current. If the DETECT pin sinks less than I_ACDMIN

for more than t_DIS, the port will turn off power. If the bit is

clear, the port will not remove power due to high port

impedance (AC current below I_ACDMIN).

Port 2 Status (Address 0Dh):Port 2 Status Register, Read

Only. See Port 1 Status.

Port 3 Status (Address 0Eh): Port 3 Status Register, Read

Only. See Port 1 Status.

Port 4 Status (Address 0Fh): Port 4 Status Register, Read

Only. See Port 1 Status.

PowerStatus(Address10h):PowerStatusRegister,Read

Only. The lower four bits in this register report the switch

on/off state for the corresponding ports. The upper four

bits(thepowergoodbits)indicatethatthedropacrossthe

powerswitchandsenseresistorforthecorrespondingports

is less than 2V (typ) and power start-up is complete. The

The DC and AC disconnect signals that reset t_DISare ORed

together and either sensing method (if they are both en-

abled) will keep the port powered. A port with neither DC

or AC disconnect enabled will not power off automatically

when the PD is removed.

4259Af

11

LTC4259A

U

REGISTER FU CTIO S

Detect/Class Enable (Address 14h): Detection and Clas-

sificationEnable,Read/Write.Thelowerfourbitsofthisreg-

isterenablethedetectioncircuitryatthecorrespondingport

ifthatportisinAutoorSemiautomode.Theupperfourbits

enabletheclassificationcircuitryatthecorrespondingport

if that port is in Auto or Semiauto mode. In manual mode,

settingabitinthisregisterwillcausetheLTC4259Atoper-

form one classification or detection cycle on the corre-

spondingport.WritingtotheDetect/ClassRestartPB(18h)

has the same effect without disturbing the Detect/Class

Enable bits for other ports.

involves reading the register to determine its status, set-

ting the appropriate bit in software and writing back the

entire register, a pushbutton register allows a single bit to

be written without knowing or affecting the status of the

other bits in the register. Pushbutton registers are write-

only and will return 00h if read.

Det/Class Restart PB (Address 18h): Detection/Classifi-

cation Restart Pushbutton Register, Write Only. Writing a

1 to any bit in this register will start or restart a single

detection or classification cycle at the corresponding port

inManualmode. Itcanalsobeusedtosetthecorrespond-

ing bits in the Detect/Class Enable register (address 14h)

for ports in auto or semiauto mode. The lower 4 bits affect

detection on each port while the upper 4 bits affect

classification.

TimingConfig(Address16h):GlobalTimingConfiguration,

Read/Write.Bits0-1programt_DIS,thetimedurationbefore

a port is automatically tuned off after the PD is removed.

TheLTC4259Acanbeprogrammedtomonitorwhetherport

currentisbelowI_MIN(DCconnect)orportimpedanceishigh

(AC disconnect). Bits 2-3 program t_ICUT, the time during

which a port’s current can exceed I_CUTwithout it being

turned off. If the current is still above I_CUTafter t_ICUT, the

LTC4259A will indicate a t_ICUTfault and turn the port off.

Bits 4-5 program t_START, the time duration before an over-

current condition during port power-on is considered a

t_STARTfault and the port is turned off. Note that using the

t_ICUTand t_STARTtimes other than the default is not compli-

ant with IEEE 802.3af and may double or quadruple the

energydissipatedbytheexternalMOSFETsduringfaultcon-

ditions. Bits 6-7 are reserved and should be read/written

as 0. See Electrical Characteristics for timer bit encoding.

Also see the Applications Information for descriptions of

PowerEnablePB(Address19h):PowerEnablePushbutton

Register, WriteOnly. Thelowerfourbitsofthisregisterset

thePowerEnablebitinthecorrespondingPortStatusreg-

ister; the upper four bits clear the corresponding Power

Enablebit.SettingorclearingthePowerEnablebitsviathis

register will turn on or off the power in any mode except

shutdown, regardless of the state of detection or classifi-

cation. Note that t_ICUT, t_STARTand disconnect events (if

enabled) will still turn off power if they occur.

The Power Enable bit cannot be set if the port has turned

off due to a t_ICUTor t_STARTfault and the t_ICUTtimer has not

yet counted back to zero. See Applications Information for

more information on t_ICUTtiming.

t_START, t_ICUT, DC and AC disconnect timing.

Clearing the Power Enable bits with this register also

clears the detect and fault event bits, the Port Status

register, and the Detection and Classification Enable bits

for the affected port(s).

MiscConfig(Address17h):MiscellaneousConfiguration,

Read/Write. Bit 5 is the Osc Fail Mask; it is set by default.

When the Osc Fail Mask bit is clear, it prevents a failure on

the OSCIN pin from setting the Osc Fail bit and causing a

Supply Event Interrupt. Setting bit 7 enables the INT pin.

If this bit is reset, the LTC4259A will not pull down the INT

pininanyconditionnorwillitrespondtotheAlertResponse

Address. This bit is set by default.

Reset PB (Address 1Ah): Reset Pushbutton, Write Only.

Bits0-3resetthecorrespondingportbyclearingthepower

enable bit, the detect and fault event bits, the status regis-

ter and the detection and classification enable bits for that

port. Bit 4 returns the entire LTC4259A to the power-on

reset state; all ports are turned off, the AUTO pin is reread

and all registers are returned to their power-on defaults,

exceptV_DDUVLO,whichremainscleared.Bit5isreserved;

setting it has no effect. Setting bit 6 releases the Interrupt

pin if it is asserted without affecting the Event registers or

the Interrupt register. When the INT pin is released in this

4259Af

Pushbutton Registers

NoteRegardingPushbuttonRegisters:“Pushbutton”reg-

isters are specialized registers that trigger an event when

a1iswrittentoabit;writinga0toabitwilldonothing.Unlike

a standard read/write register, where setting a single bit

12

LTC4259A

U

REGISTER FU CTIO S

way, the condition causing the LTC4259A to pull the INT

pin down must be removed before the LTC4259A will be

able to pull INT down again. This can be done by reading

and clearing the event registers or by writing a 1 into bit 7

of this register. Setting bit 7 releases the Interrupt pin,

clears all the Event registers and clears all the bits in the

Interrupt register.

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APPLICATIO S I FOR ATIO

OVERVIEW

equipment that is commonly found in the wiring closets

where cables converge. PDs can take many forms: digital

IP telephones, wireless network access points, PDA or

notebook computer docking stations, cell phone charg-

ers, and HVAC thermostats are examples of devices that

can draw power from the network.

Overtheyears,twisted-pairEthernethasbecomethemost

commonly used method for local area networking. The

IEEE 802.3 group, the originator of the Ethernet standard,

has defined an extension to the standard, known as

802.3af, which allows DC power to be delivered simulta-

neously over the same cable used for data communica-

tion. This promises a whole new class of Ethernet devices,

including IP telephones, wireless access points, and PDA

charging stations, which do not require additional AC

wiring or external power transformers, a.k.a. “wall warts.”

Withabout13Wofpoweravailable, smalldatadevicescan

be powered by their Ethernet connections, free from AC

wall outlets. Sophisticated detection and power monitor-

ing techniques prevent damage to legacy data-only de-

vices, while still supplying power to newer, Ethernet-

powered devices over the twisted-pair cable.

A PSE is required to provide a nominal 48V DC between

either the signal pairs or the spare pairs (but not both) as

shown in Figure 11. The power is applied as a voltage

between two of the pairs, typically by powering the center-

taps of the isolation transformers used to couple the

differential data signals to the wire. Since Ethernet data is

transformercoupledatbothendsandissentdifferentially,

a voltage difference between the transmit pairs and the

receive pairs does not affect the data. A 10base-T/

100base-TXEthernetconnectiononlyuses2ofthe4pairs

in the cable. The unused or spare pairs can be powered

directly, as shown in Figure 11, without affecting the data.

However, 1000base-T uses all 4 pairs and power must be

connected to the transformer center taps if compatibility

with 1000base-T is required.

A device that supplies power is called Power Sourcing

Equipment (PSE); a device that draws power from the

wire is called a Powered Device (PD). A PSE is typically an

Ethernet switch, router, hub, or other network switching

CAT 5

20Ω MAX

PSE

PD

ROUNDTRIP

RJ45

4

RJ45

0.05µF MAX

4

5

1N4002

SPARE PAIR

GND

×4

0.1µF

100V

0.1µF

1

DGND BYP

AGND

DETECT

CMPD3003

5µF ≤ C

IN

≤ 300µF

SMAJ58A

58V

Tx

Rx

Tx

3.3V

INTERRUPT

V

DD

INT

SCL

SDAIN

SDAOUT

2

3

2

3

DATA PAIR

1k

1/4

LTC4259A

2

0.47µF

100V

X7R

I C

0.1µF

1N4002

×4

Rx

V

SENSE GATE OUT

EE

GND

6

DC/DC

CONVERTER

R

PWRGD

+

OUT

CLASS

SMAJ58A

58V

10k

V

0.5Ω

LTC4257

–48V

7

6

7

IRFM120A

–48V

IN

–48V

OUT

–

S1B

6

SPARE PAIR

4259A F11

Figure 11. System Diagram

4259Af

13

LTC4259A

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APPLICATIO S I FOR ATIO

The LTC4259A provides a complete solution for detection

and powering of PD devices in an IEEE 802.3af compliant

system. The LTC4259A consists of four independent

ports, each with the ability to detect, classify, and provide

isolated –48V power to a PD device connected to it. The

LTC4259A senses removal of a PD with IEEE 802.3af

compliant AC or DC methods and turns off –48V power

when the PD is removed. An internal control circuit takes

care of system configuration and timing, and uses an I²C

interface to communicate with the host system.

Regardless of which mode it is in, the LTC4259A will

remove power automatically from any port that generates

a t_STARTor t_ICUTovercurrent fault event (see t_ICUTTiming

and t_STARTTiming sections). It will also automatically

remove power from any port that generates a disconnect

event if the appropriate Disconnect Enable bit is set in the

Disconnect Enable register. The host controller may also

remove power at any time by setting the appropriate

Power Off bit in the Power Enable PB register.

Power-On RESET

OPERATING MODES

At turn-on or any time the LTC4259A is reset (either by

pulling the RESET pin low or writing to the global Reset All

bit), all the ports turn off and all internal registers go to a

predefined state, shown in Table 1.

Each LTC4259A port can operate in one of four modes:

Manual, Semiauto, Auto or Shutdown. The operating

mode for a port is set by the appropriate bits in the

Operating Mode register. The LTC4259A will power up

with all ports in Shutdown mode if the external AUTO pin

is tied low; if AUTO is high, all ports will wake up in Auto

mode. The operating mode can be changed at any time via

the I²C interface, regardless of the state of the AUTO pin.

Several of the registers assume different states based on

the state of the AUTO pin at reset. The default states with

AUTO high allow the LTC4259A to detect and power up a

PD in Automatic mode, even if nothing is connected to the

I²C interface.

•

In Manual mode, a port will wait for instructions from

the host system before taking any action. It will run

single detection or classification cycles when com-

manded, and will report results in the Port Status

registers. When the host system decides it is time to

turn on or off power to a port, it can do so by setting

the appropriate Power On/Off bits in the Power Enable

PB register regardless of the current status of detec-

tion or classification.

SIGNATURE DETECTION

The IEEE defines a specific pair-to-pair PD signature

resistance that identifies a device that can accept Power

over Ethernet in accordance with the 802.3af specifica-

tion. When the port voltage is below 10V, an 802.3af

compliant PD will have a 25k signature resistance. Figure

12 illustrates the relationship between the PD signature

resistance(whiteboxfrom23.75kto26.25k)andrequired

resistance ranges the PSE must accept (white box) and

reject (gray boxes). According to the 802.3af specifica-

tion, the PSE may or may not accept resistances in the two

ranges of 15k to 19k and 26.5k to 33k. Note that the black

boxinFigure12representsthe150Ωpair-to-pairtermina-

tion used in legacy 802.3 devices like a computer’s net-

work interface card (NIC) that cannot accept power.

• In Semiauto mode, the port will repeatedly attempt to

detect and classify a PD device attached to the link. It

will report this information in its Port Status register,

and wait for the host system to set the appropriate

Power On bit in the Power Enable PB register before

applying power to the port.

• In Auto mode, the port will detect and classify a PD

device connected to it, then immediately turn on the

power if detection was successful regardless of the

result of classification.

RESISTANCE 0Ω

10k

20k

30k

150Ω (NIC)

23.75k

26.25k

26.5k

PD

PSE

15k 19k

33k

• InShutdownmode,theportisdisabledandwillnotdetect

orpoweraPD.Also,thedetectandfaulteventbits,status

bits and enable bits for the port are reset to zero.

4259A F12

Figure 12. IEEE 802.3af Signature Resistance Ranges

4259Af

14

LTC4259A

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APPLICATIO S I FOR ATIO

U

The LTC4259A checks for the signature resistance by

forcing two test currents on the port (via the DETECTn

pins) in sequence and measuring the resulting voltages. It

thensubtractsthetwoV-Ipointstodeterminetheresistive

slope while removing voltage offset caused by any series

diodes or current offset caused by leakage at the port (see

Figure 13). The LTC4259A will typically accept any PD

resistance between 17k and 29k as a valid PD and report

Detect Good (100 binary) in the Detect Status bits (bits 2

through 0) of the corresponding Port Status register.

Values outside this range, including open and short cir-

cuits, are also reported in the Detect Status bits. Refer to

Table 1 for a complete decoding of the Detect Status bits.

The LTC4259A will not report Detect Good if the PD has

more than 5µF in parallel with its signature resistor.

The port’s operating mode controls if and when the

LTC4259A runs a detection cycle. In manual mode, the

port will sit idle until a Restart Detection (register 18h)

command is received. It will then run a complete 200ms

detection cycle on the selected port, report the results in

the Detect Status bits in the corresponding Port Status

register and return to idle until another command is

received.InSemiautomode,theLTC4259Aautonomously

tests valid PDs connected to the ports but it will not apply

power until instructed to do so by the host controller. It

repeatedly queries the port every 320ms and updates the

Detect Status bits at the end of each cycle. If a Detect Good

is reported, it will advance to the classification phase and

report that result in the Port Status register. Until in-

structed to do otherwise, the LTC4259A will continue to

repeat detection on the port. Behavior in Auto mode is

similar to Semiauto; however, after a Detect Good is

reported, the LTC4259A performs the classification phase

and then powers up the port without further intervention.

The first test point is taken by forcing a test current into

the port, waiting a short time to allow the line to settle and

measuring the resulting voltage. This result is stored and

the second current is applied to the port, allowed to settle

and the voltage measured. Each point takes 100ms to

measure, and an entire detection cycle takes 200ms.

The signature detection circuitry is disabled when the port

is in Shutdown mode, powered up or the corresponding

Detect Enable bit is cleared.

275

FIRST

DETECTION

POINT

25kΩ SLOPE

CLASSIFICATION

165

SECOND

A PD has the option of presenting a “classification signa-

ture” to the PSE to indicate how much power it will draw

when powered up. This signature consists of a specific

constantcurrentdrawwhenthePSEportvoltageisbetween

15.5Vand20.5V,withthecurrentlevelindicatingthepower

class to which the PD belongs. Per the IEEE 802.3af speci-

fication,theLTC4259AidentifiesthefiveclassesofPDlisted

inTable2.Duringclassification,theLTC4259Acontrolsand

DETECTION

POINT

VALID PD

0V-2V

OFFSET

VOLTAGE

4259A F13

Figure 13. PD Detection

Table 2. IEEE 802.3af Powered Device Classes

IEEE 802.3af

CLASS

CLASSIFICATION

CURRENT AT PSE

MAXIMUM

PD POWER

MINIMUM PSE

OUTPUT POWER

CLASS DESCRIPTION

0

1

2

3

4

0mA to 5mA

8mA to 13mA

16mA to 21mA

25mA to 31mA

35mA to 45mA

12.95W

3.84W

15.4W

PD Does Not Implement Classification, Unknown Power

Low Power PD

4W

6.49W

7W

Medium Power PD

12.95W

15.4W

High or Full Power PD

15.4W

Reserved, Power as Class O

4259Af

15

LTC4259A

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APPLICATIO S I FOR ATIO

measures the port voltage through the DETECTn pin. Note

that class 4 is presently specified by the IEEE as reserved

forfutureuse.Figure14showsaPDloadline,startingwith

the shallow slope of the 25k signature resistor below 10V,

thendrawingtheclassificationcurrent(inthiscase,class 3)

between 14.5V and 20.5V. The LTC4259A’s load line for

classification is also shown in Figure 14. It has low imped-

ance until current limit at 65mA (typ).

Gate Currents

Once the decision has been made to turn on power to a

port, the LTC4259A uses a 50µA current source to pull up

on the GATE pin. Under normal power-up circumstances,

theMOSFETgatewillchargeuprapidlytoV_T(theMOSFET

threshold voltage), the MOSFET current will rise quickly to

the current limit level and the GATE pin will be servoed to

maintain the proper I_INRUSHcharging current. When out-

put charging is complete, the MOSFET current will fall and

the GATE pin will be allowed to continue rising to fully

enhance the MOSFET and minimize its on resistance. The

final V_GSis nominally 13V. When a port is turned off, a

50µA current source pulls down on the GATE pin, turning

the MOSFET off in a controlled manner.

The LTC4259A will classify a port immediately after a

successful detection cycle in Semiauto or Auto modes, or

when commanded to in Manual mode. It measures the PD

classification signature current by applying 18V (typ) to

theportandmeasuringtheresultingcurrent. Itreportsthe

detected class in the Class Status bits in the correspond-

ing Port Status register. Note that in Auto mode, the port

will power up regardless of which class is detected.

No External Capacitors

No external capacitors are required on the GATE pins for

active current limit stability, lowering part count and cost.

This also allows the fastest possible turn-off under severe

overcurrent conditions, providing maximum safety and

protectionfortheMOSFETs,loaddevicesandboardtraces.

Connecting capacitors to the external MOSFET gates can

adversely affect the LTC4259A’s ability to respond to a

shorted port.

The classification circuitry is disabled when the port is in

Shutdown mode, powered up, or the corresponding Class

Enable bit is cleared.

60

PSE LOAD LINE

OVER

CURRENT

50

40

30

20

10

0

48mA

CLASS 4

CLASS 3

33mA

23mA

Inrush Control

The 802.3af standard lists two separate maximum current

limits, I_LIMand I_INRUSH. Because they have identical val-

ues, the LTC4259A implements both as a single current

limit using V_LIM(described below). Their functions are

differentiated through the use of t_ICUTand t_START, respec-

tively (see t_ICUTTiming and t_STARTTiming sections). To

maintain consistency with the standard, the I_INRUSHterm

is used when referring to an initial t_STARTpower-up event.

CLASS 2

TYPICAL

CLASS 3

PD LOAD

LINE

14.5mA

6.5mA

CLASS 1

CLASS 0

0

5

10

15

20

25

VOLTAGE (V

CLASS

)

4259A F14

Figure 14. PD Classification

When the LTC4259A turns on a port, it turns on the

MOSFET by pulling up on the gate. The LTC4259A is

designed to power up the port in current limit, limiting the

POWER CONTROL

The primary function of the LTC4259A is to control the

delivery of power to the PSE port. It does this by control-

ling the gate drive voltage of an external power MOSFET

while monitoring the current via a sense resistor and the

output voltage at the OUT pin. This circuitry serves to

couple the raw isolated –48V input supply to the port in a

controlled manner that satisfies the PD’s power needs

while minimizing disturbances on the –48V backplane.

inrush current to I_INRUSH

.

The port voltage will quickly rise to the point where the PD

reaches its input turn-on threshold and begins to draw

current to charge its bypass capacitance, slowing the rate

of port voltage increase.

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Dual-Level Current Limit

Ifthet_ICUTtimerexpiresandcausestheporttoshutoff,the

timer will continue to run, counting down at the slow

1/16th rate and preventing the port from being repowered

until the count returns to zero. This protects the MOSFET

from damage due to a faulty PD that may still have a valid

signature,orfromerrantsoftwarethatrepeatedlywritesto

the Power On bit.

A PD is permitted to draw up to 15.4W continuously and

upto400mAfor50ms.TheLTC4259Ahastwocorrespond-

ing current limit thresholds, I_CUT(375mA typ) and I_LIM

(425mA typ). These are given by the equations:

I_CUT= V_CUT/R_S, I_LIM= V_LIM/R_S

R_Sis the sense resistor and should be 0.5Ω for IEEE

802.3af compliance. While the LTC4259A allows the port

current to exceed I_CUTfor a limited time period (see t_ICUT

The port will not repower until after the t_ICUTcounter

returns to zero. In manual and semiauto modes the power

enable command must be received after the t_ICUTcounter

reaches zero. In auto mode the LTC4259A must complete

a valid detection cycle after the t_ICUTcounter reaches zero.

timingbelow), itdoesnotallowthecurrenttoexceedI_LIM

.

The current limit circuit monitors the port current by

monitoring the voltage across the sense resistor and re-

duces the MOSFET gate voltage as needed to keep the

current at or below I_LIM. When the current drops below

I_LIM, the gate voltage is restored to the full value to keep

the MOSFET resistance to a minimum.

t_STARTTiming

To distinguish between normal turn-on current limit be-

havior and current limit faults which occur after power-up

iscomplete,theLTC4259Astartsatimer(thet_STARTtimer)

whenever a power-up sequence begins.

t_ICUTTiming

The t_STARTtimer serves three functions. First and fore-

most, it allows the user to specify a different current limit

timeout (t_STARTinstead of t_ICUT) during turn-on (current

limit duty cycle protection remains functional). Second,

the DC disconnect timer is disabled during this period and

can only begin counting up after the t_STARTtimer has

expired. Together, these two features let the PD draw the

maximum current I_INRUSHto charge its input capacitance,

boot up and begin drawing power without triggering a

t_STARTfault. Finally, if the device is in current limit for the

entire t_STARTperiod, a t_STARTfault will be generated

insteadofat_ICUTfault.Thiscanbeusefulfortrackingdown

the cause of a current fault.

Whenever more than I_CUT= V_CUT/R_Sflows through a port,

the port’s sense voltage is above V_CUTand the t_ICUTtimer

counts up. If the sense voltage is still above V_CUTwhen the

t_ICUTtimer expires, the LTC4259A will turn off the power

to the port immediately and set the appropriate t_ICUTFault

bitinregister06h/07h.Thet_ICUTtimerdurationcanbepro-

grammed via register 16h, bits 3 and 2 (Table 1).

The t_ICUTtimer is an up/down counter that is designed to

protect the external MOSFET from thermal stress caused

by repeatedly operating in current limit. The counter

counts up whenever the current is above I_CUTand counts

down at 1/16th the rate when it is not. The counter will

bottom out at zero to prevent underflow. Full count indi-

cates that the t_ICUTtimer has expired and the port will be

turned off.

As long as the PD draws less than I_CUTat the end of t_START

and begins drawing the minimum current within t_DISafter

t_STARTexpires (if DC disconnect is enabled), no faults will

be indicated.

Thiscountup/countdownbehaviorimplementsdutycycle

protection,preventingintermittentcurrentlimitfaultsfrom

causingcumulativethermalstressintheMOSFET.Iftheport

enters current limit but then exits before the timer expires,

the count will decrease slowly, giving the I_CUTtimer the

ability to turn off sooner in the case of a repetitive fault. If

theovercurrentdutycycleislessthan6.3%thet_ICUTtimer

will be fully reset.

The t_STARTtimer also implements the duty cycle protec-

tion described under t_ICUTtiming and its duration can be

programmed via register 16h, bits 5 and 4 (Table 1).

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Foldback

30V or more before the PD turns on. The port voltage can

then drop to 0V as the PD’s bypass capacitor is charged.

AccordingtotheIEEE, thePDcandirectlyconnecta180µF

capacitor to the port and the PSE must charge that

capacitor with a current limit of 400mA to 450mA for at

least 50ms.

Foldback is designed to limit power dissipation in the

MOSFET during power-up and momentary short-circuit

conditions. Atlowportoutputvoltages, thevoltageacross

the MOSFET is high, and power dissipation will be large if

significant current is flowing. Foldback monitors the port

output voltage and reduces the V_LIMcurrent limit level

linearly from its full value (212.5mV typ) at a port voltage

of 18V to approximately 1/7th of the full value (30mV typ)

at a port voltage of 0V. With 0.5Ω sense resistors, this

limitstheshort-circuitcurrentto60mA(typ)insteadofthe

full 425mA (typ) current limit. When the LTC4259A is in

foldback, the t_ICUTtimer is active.

An even more extreme example is a noncompliant PD that

provides the proper signature during detection but then

behaveslikealowvaluedresistor,say50Ω,inparallelwith

a 1µF capacitor. When the PSE has charged this

noncompliant PD up to 20V, the 50Ω resistor will draw

400mA (the minimum IEEE prescribed I_LIMcurrent limit)

keepingtheportvoltageat20Vfortheremainderoft_START

.

The external MOSFET sees 24V to 37V V_DSat 400mA to

450mA, dissipating 9.6W to 16.7W for 60ms (typ).

Short-Circuit Protection

If a port is suddenly shorted out, the MOSFET power

dissipation can rise to very high levels, jeopardizing the

MOSFET even before the normal current limit circuit can

respond. A separate short-circuit current limit circuit

watches for significant overcurrent events (V_SENSE

>275mV, >550mA with a 0.5Ω sense resistor) and pulls

the GATE pin down immediately if such an event occurs,

shutting off the MOSFET in less than 1µs (with no external

capacitor on GATE). Approximately 100µs later, GATE is

allowed to rise back up and the normal current limit circuit

willtakeover, allowingI_LIMcurrenttoflowandcausingthe

t_ICUTtimer to count up. During a short circuit, I_LIMwill be

reduced by the foldback feature to 1/7th of the nominal

value.

The LTC4259A implements foldback to reduce the current

limit when the MOSFET V_DSis high; see the Foldback

section. Withoutfoldback, theMOSFETcouldseeasmuch

as 25.7W for 60ms (typ) when powering a shorted or a

noncompliantPDwithonlyafewohmsofresistance. With

foldback, the MOSFET sees a maximum of 18W for the

duration of t_START

.

The LTC4259A’s duty cycle protection enforces 15 times

longer off time than on time, preventing successive at-

tempts to power a defective PD from damaging the

MOSFET. System software can enforce even longer wait

times. When the LTC4259A is operated in semiauto or

manual mode—described in more detail under Operating

Modes—itwillnotpoweronaportuntilcommandedtodo

so by the host controller. By keeping track of t_STARTand

t_ICUTfaults, the host controller can delay turning on the

port again after one of these faults even if the LTC4259A

reports a Detect Good. In this way the host controller

implements a MOSFET cooling off period which may be

programmed to protect smaller MOSFETs from repeated

thermal cycling. The LTC4259A has built-in duty cycle

protectionfort_ICUTandt_START(seet_ICUTTimingandt_START

Timing sections) that is sufficient to protect the MOSFETs

shown in Figure 1.

Choosing External MOSFETs

Power delivery to the ports is regulated with external

power MOSFETs. These MOSFETs are controlled as previ-

ously described to meet the IEEE 802.3af specification.

Under normal operation, once the port is powered and the

PD’s bypass capacitor is charged to the port voltage, the

external MOSFET dissipates very little power. This sug-

gests that a small MOSFET is adequate for the job. Unfor-

tunately, other requirements of the IEEE 802.3af mandate

a MOSFET capable of dissipating significant power. When

the port is being powered up, the port voltage must reach

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Before designing a MOSFET into your system, carefully

compare its safe operating area (SOA) with the worst case

conditions(likepoweringupadefectivePD)thedevicewill

face. Using transient suppressors, polyfuses and ex-

tended wait times after disconnecting a PD are effective

strategies to reduce the extremes applied to the external

MOSFETs.

A short—hence low inductance—piece of CAT-5 will not

limittherapidincreaseofcurrentwhentheportisshorted.

EventhoughtheLTC4259Ashort-circuitshutdownisfast,

the cable may have many amps flowing through it before

the MOSFET can be turned off. Due to the high current,

this short piece of cable flies back with significant energy

behinditandmustbecontrolledbythetransientsuppres-

sor. Choosing a surge suppressor that will not develop

more than a few volts of forward voltage while passing

more than 10A is important. A positive port voltage may

forward bias the detect diode (D_DETn), bringing the

LTC4259A’s DETECTn pin positive as well and engaging

the DETECTn clamps. This will generally not damage the

LTC4259A but extreme cases can cause the LTC4259A to

reset. When it resets, the LTC4259A signals an interrupt,

alerting the host controller which can then return the

LTC4259A to normal operating mode.

Surge Suppressors and Circuit Protection

IEEE802.3afPoweroverEthernetisachallengingHotSwap

application because it must survive the (probably unin-

tentional) abuse of everyone in the building. While hot

swapping boards in a networking or telecom card cage is

done by a trained technician or network administrator,

anyone in the building can plug a device into the network.

Moreover, in a card cage the physical domain being pow-

ered is confined to the card cage. With Power over Ether-

net, the PSE supplies power to devices up to 100 meters

away. Ethernet cables could potentially be cut, shorted

together, and so on by all kinds of events from a contrac-

tor cutting into walls to someone carelessly sticking a

screwdriver where it doesn’t belong. Consequently, the

PoweroverEthernetpowersource(PSE)mustbedesigned

to handle these events.

A substantial transient surge suppressor can typically

protect the LTC4259A and the rest of the PSE from these

faults. Placing a polyfuse between the RJ-45 connector

and the LTC4259A and its associated circuitry can provide

additional protection. To meet safety requirements, place

the polyfuse in the ground leg of the PSE’s output.

The most dramatic of these is shorting a powered port.

What the PSE sees depends on how much CAT-5 cable is

between it and the short. If the short occurs on the far end

of a long cable, the cable inductance will prevent the cur-

rent in the cable from increasing too quickly and the

LTC4259A’s built-in short-circuit protection will take con-

trol of the situation and turn off the port. Some energy is

stored in the cable, but the transient suppressor on the

port clamps the port voltage when the cable inductance

causes the voltage to fly back after the MOSFET is turned

off.Becausethecableonlyhad600mAorsogoingthrough

it, an SMAJ58A or equivalent device can easily control the

portvoltageduringflyback. Withnocableconnectedatall,

a powered port shorted at the PSE’s RJ-45 connector can

reachhighcurrentlevelsbeforetheportisshutdown.There

is no cable inductance to store energy so once the port is

shut down the situation is under control.

DC DISCONNECT

DC disconnect monitors the sense resistor voltage when-

ever the power is on to make sure that the PD is drawing

the minimum specified current. The disconnect timer

counts up whenever port current is below 7.5mA (typ). If

the t_DIStimer runs out, the corresponding port will be

turnedoffandthedisconnectbitinthefaultregisterwillbe

set. If the undercurrent condition goes away before the

t

_DIStimer runs out, the timer will reset. The timer will start

countingfromthebeginningiftheundercurrentcondition

occurs again. The undercurrent circuit includes a glitch

filter to filter out noise.

The DC disconnect feature can be disabled by clearing the

corresponding DC Discon Enable bits in the Disconnect

register(13h).Thet_DIStimerdurationcanbeprogrammed

by bits 1 and 0 of register 16h.

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Unlike DC disconnect, AC disconnect has no continuous

time output to the timer. Rather, AC disconnect will reset

the timer once every cycle, 1/f_OSCIN, of the OSCIN signal if

the port draws more than I_ACDMINduring that period.

Because of this behavior, the time to turn off the port after

PD removal, t_DIS, may vary by up to one cycle of OSCIN

(1/f_OSCIN) from the delay programmed with the t_DIS1and

t_DIS0bits. Note that AC disconnect and DC disconnect

signalsthatresetthet_DIStimerareORedtogether.Thuson

a port where both disconnect modes are enabled, either

disconnect sensing method can keep the port

powered even if the other reports that there is no PD

connected.

CURRENT LIMIT

300mV

250mV

200mV

150mV

100mV

50mV

600mA

500mA

400mA

300mA

200mA

100mA

IN 1µs

PORT OFF IN t

ICUT

OR t

START

CURRENT

LIMIT

NORMAL

OPERATION

PORT OFF IN t

EFFECT

DIS

0mV

SENSEn

VOLTAGE

0mA

CURRENT DC DIS-

CUT

LIMIT SHORT

(I CIRCUIT

4259A F15

R

S

= 0.5Ω CONNECT (I

)

LIM

Figure 15. LTC4259A Current Sense and Limits

TheLTC4259Aimplementsavarietyofcurrentsenseand

limit thresholds to control current flowing through the

port. Figure 15 is a graphical representation of these

thresholds and the action the LTC4259A takes when

currrent crosses the thresholds.

The AC disconnect circuitry senses the port and Power

over Ethernet connection from the DETECT pins. Connect

a 0.47µF 100V X7R capacitor (C_DET) and a 1k resistor

(R_DET) from the port’s DETECT pin to the port’s output as

shown in Figure 16. This provides an AC path for sensing

the port impedance. The 1k resistor, R_DET, limits current

flowing through this path during port power on and power

off.

AC DISCONNECT

AC disconnect is an alternate method of sensing the pres-

enceorabsenceofaPDbymonitoringtheportimpedance.

The LTC4259A forces a signal, amplified from the OSCIN

pin, out of the DETECT pins and onto the Power over Eth-

ernet connection. It calculates the connection impedance

from ohm’s law, Z_PORT= V_AC/I_AC. Like DC disconnect, the

AC disconnect sensing circuitry controls the disconnect

timer. When the connection impedance rises (AC current

falls below I_ACDMIN) due to the removal of the PD, the dis-

connect timer counts up. If the impedance remains high

(AC current remains below I_ACDMIN), the disconnect timer

counts to t_DIS, the port is turned off and the port’s discon-

nect bit in the Fault Register is set. If the impedance falls

(AC current rises above I_ACDMIN) before the maximum

countofthedisconnecttimer,thetimerresetsandtheport

remains powered.

Sizingofcapacitorsiscriticaltoensureproperfunctionof

AC disconnect. C_PSE(Figure 16) controls the connection

impedance on the PSE side. Its capacitance must be kept

low enough for AC disconnect to be able to sense the PD.

For operation near 100Hz, use a C_PSEof 0.1µF. On the

otherhand, C_DEThastobelargeenoughtopassthesignal

atthefrequencyofOSCIN. Forf_OSCIN≈100Hz, useatleast

a 0.47µF 100V X7R capacitor. The sizes of C_PSE, C_DET

,

R_DETand the frequency, f_OSCIN, are chosen to create an

economical, physically compact and functionally

robustsystem. Moreover, thecompletePoweroverEther-

net AC disconnect system (PSE, transformers, cabling,

PD, etc.) is complex; deviating from the recommended

values of C_DET, R_DETand C_PSEis discouraged. Contact the

LTC Applications department for additional support.

LikeDCdisconnect, ACdisconnectcanalsobedisabledby

clearing the corresponding AC Discon Enable bits in the

Disconnect register (13h). AC disconnect is also affected

by the t_DISduration programmed in register 16h.

When choosing C_DETand C_PSE, carefully consider voltage

derating of the capacitors. Capacitors built around an X7R

dielectric will have about 60% of the specified capacitance

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at their rated voltage. Operated at half their rated voltage,

X7R capacitors exhibit more than 80% of their specified

capacitance. With other ceramic dielectrics commonly

used in 50V and 100V chip capacitors, capacitance falls

much more dramatically with voltage. At their rated volt-

age, Y5V or Z5U capacitors exhibit less than 30% of their

zero-bias capacitance. Ceramic capacitors can also have

significantly less capacitance at elevated temperatures. In

order to produce the desired capacitance at the operating

bias, 100V or 250V X7R capacitors should be used with

the LTC4259A.

be placed between the PSE and PD, pair-to-pair capaci-

tance is a pretty nebulous quantity. Consequently, the

cable’s contribution to the port impedance (at the fre-

quency used for AC disconnect) can be a concern.

Assumimg that f_OSCINis 100Hz, the 0.1µF of C_PSEplus

0.05µF of cable capacitance gives a port impedance of 10k

at 100Hz. The PD AC signature resistance is about 25k.

Connecting a PD with the maximum allowed resistance of

26.25k brings the connection impedance to about 8k. The

presence of a PD only makes a 20% reduction in the port

impedance requiring the AC disconnect circuitry to be

quite sensitive. When the OSCIN pin is driven with a sine

wave,theLTC4259Aisabletodistinguishbetweencapaci-

tiveimpedanceandresistiveimpedanceonthePowerover

Ethernet connection. AC disconnect is reliable for cable

capacitance up to about 0.2µF, nearly an order of magni-

tude greater than worst case for a long CAT-3 or CAT-5

cable.

As illustrated in Figure 17, the Power over Ethernet con-

nection between the PSE and PD includes a large amount

of capacitance. Cable capacitance is particularly troubling

because CAT-3 and CAT-5 pair-to-pair capacitance is not

tightly specified by the IEEE 802.3 standard or well con-

trolled by cable manufacturers. Considering that patch

panels, additional connectors, old wiring, etc. are likely to

PD

GND

C

PSE4

OSCIN

DGND AGND

DETECT4

0.1µF

100V X7R

LEVEL

SHIFT

1/4

Rpd_d

≤26.25k

Cpd_d

≥0.05µF

LTC4259A

R

1k

DET4

D

V

EE

DET4

SENSE4 GATE4 OUT4

R

CMPD3003

C

DET4

OUT4

10k

0.47µF

–48V

100V X7R

Q4

R

S4

D

4259A F16

AC4

0.5Ω 1%

S1B

Figure 16. AC Disconnect Single Port Application Circuit (Port 4 Shown)

OSCILLATOR

INPUT

R

DET

CURRENT

SENSE

1k

~7k

C

DET

Z

LINK

< 14k

Z

< 14k

PD

0.47µF

C

PSE

C

≤ 0.05µF

C

pd_d

≥ 0.05µF

R

pd_d

< 26.25k

CABLE

0.10µF

<32k

~16k

Z

< 32k

CABLE

4259A F17

Figure 17. Simplified AC Disconnect Circuit with Impedances at 100Hz

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OSCIN Input and Oscillator Requirements

OSCIN voltage greater than 2.2V will cause the amplifier’s

output to clip against DGND. Clipping will not affect the

performance of AC disconnect until the clipping becomes

so severe that even the midrange (where the controlled

slewrateoccurs)ofthesignalisclipped.Keepthemidrange

or average voltage of the OSCIN signal between 0.9V and

1.5V to avoid severe clipping. OSCIN signals below DGND

can interact with the ESD protection circuitry on the pin

andarenotrecommended. Also, meetingtheIEEE802.3af

specification for maximum AC amplitude on the port just

after the PD is removed depends on the OSCIN input peak-

to-peak amplitude. Clipping by LTC4259A’s OSCIN input

circuitry will generally ensure that this specification is not

exceeded. Note that under normal operation, the AC dis-

connectoutputontheDETECTn pinwillhaveanamplitude

near 6V peak-to-peak. The combination of R_DET, C_DETand

C_PSEattenuate the signal so roughly half this amplitude is

seen at the port when the port is powered and the PD has

just been removed. When the PD is still connected there

will be almost no AC signal at the port.

AC disconnect depends on an external oscillator source

applied to the OSCIN pin. The LTC4259A measures port

impedance by applying an amplified version of the OSCIN

signal to the port’s DETECT pin (see Figure 16). The

oscillator should be well-controlled because errors in this

signalbecomeerrorsinthemeasuredportimpedance.As

shown in Figure 17, the load being sensed by AC discon-

nect has a resistive and a large reactive component.

Current through the PD’s signature resistor depends on

the amplitude of the AC signal while current into the

capacitors depends on the slew rated: I = C • dV/dt.

Consequently, theLTC4259Aissensitivetotheamplitude

and slew rate of the OSCIN signal, but is more tolerant of

frequency and offset errors. Internal limits prevent the

LTC4259A from being adversely affected by OSCIN sig-

nals with excessive amplitude.

There are many ways to build oscillators with controlled

amplitudes and slew rates, especially since the frequency

of the oscillator does not have to be well-controlled.

Contact the LTC Applications department for oscillator

circuits.

The LTC4259A monitors Pin 36 for the presence of an

oscillating signal. If no signal is present and the Osc Fail

Mask bit is set, then Osc Fail (bit 1 of the Supply Event

register) is set, triggering an interrupt. As the LTC4259A’s

AC disconnect circuitry self-checks the OSCIN signal, the

Osc Fail bit is intended as a fault indicator to alert the PSE

host controller. The Osc Fail bit has no effect beyond

triggering the interrupt. A clear Osc Fail bit indicates that

the OSCIN signal goes below 0.6V and above 1.8V at least

once every 250ms. It does not necessarily guarantee that

ACdisconnectwillfunctionproperly.However,ACdiscon-

nect itself is a more thorough test of the OSCIN signal.

When the OSCIN signal is either absent or corrupted,

powered ports with AC disconnect enabled (and DC dis-

connect not enabled) will automatically disconnect. After

the LTC4259A is reset (by power on, Reset All bit or the

RESET pin) the Osc Fail bit is set. Once the Osc Fail bit is

cleared, it will only be set by an invalid signal on the OSCIN

pin or another reset.

As alluded to previously, AC disconnect is complicated

and redesigning for different component sizes is a difficult

task. For optimum performance, use the recommended

component values and drive OSCIN with a 100Hz 2V_P-P

,

1.2V offset sine wave. Keep in mind that the IEEE 802.3af

specification places upper limits of 100V/ms on the slew

rate and 500Hz on the frequency of the AC signal at the

port. Voltage gain, A_VACD, from OSCIN to DETECTn in-

creases the slew rate by the voltage gain. Since A_VACDhas

a maximum absolute value of 3.3V/V (±3V typ), the slew

rate at the OSCIN pin must be less than 30V/ms. A slew

rate around 0.6V/ms at OSCIN will work with the recom-

mended values of C_DET, R_DETand C_PSE

.

The LTC4259A’s OSCIN input amplifier will accept signals

between DGND – 0.3V and V_DD+ 0.5V. This amplifier has

a gain of –1 and is referenced to 1.2V above DGND. An

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SERIAL DIGITAL INTERFACE

ernet. In this case, the SDAIN and SDAOUT pins of the

LTC4259Acanbeconnectedtogethertoactasastandard

I²C/SMBus SDA pin.

The LTC4259A communicates with a host (master) using

the standard 2-wire interface as described in the SMBus

Specification Version 2.0 (available at http://smbus.org).

The SMBus is an extension of the I²C bus, and the

LTC4259A is also compatible with the I²C bus standard.

The Timing Diagrams (Figures 6 through 10) show the

timing relationship of the signals on the bus. The two bus

lines, SDA and SCL, must be high when the bus is not in

use. External pull-up resistors or current sources, such as

the LTC1694 SMBus accelerator, are required on these

lines. If the SDA and SCL pull-ups are absent, not con-

nectedtothesamepositivesupplyastheLTC4259A’sV_DD

pin, or are not activated when the power is applied to the

LTC4259A, it is possible for the LTC4259A to see a START

condition on the I²C bus. The interrupt pin (INT) is only

updated between I²C transactions. Therefore if the

LTC4259A sees a START condition when it powers up

becausetheSCLandSDAlineswereleftfloating, itwillnot

assert an interrupt (pull INT low) until it sees a STOP

condition on the bus. In a typical application the I²C bus

will immediately have traffic and the LTC4259A will see a

STOP so soon after power up that this momentary condi-

tion will go unnoticed.

If the device is part of a larger system, contains serial

ports, or must be referenced to protective ground for

some other reason, the Power over Ethernet subsystem

including the LTC4259As must be electrically isolated

from the rest of the system. The LTC4259A includes

separate pins (SDAIN and SDAOUT) for the input and

output functions of the bidirectional data line. This eases

the use of optocouplers to isolate the data path between

the LTC4259As and the system controller. Figure 18

shows one possible implementation of an isolated inter-

face. The SDAOUT pin of the LTC4259A is designed to

drivetheinputsofanoptocouplerdirectly, butastandard

I²C device typically cannot. U1 is used to buffer I²C

signals into the optocouplers from the system controller

side. Schmitt triggers must be used to prevent extra

edges on transitions of SDA and SCL.

Bus Addresses and Protocols

The LTC4259A is a read-write slave device. The master

can communicate with the LTC4259A using the Write

Byte, Read Byte and Receive Byte protocols. The

LTC4259A’s primary serial bus address is

(010A₃A₂A₁A₀)b, as designated by pins AD3-AD0. All

LTC4259As also respond to the address (0110000)b,

allowing the host to write the same command into all of

the LTC4259As on a bus in a single transaction. If the

LTC4259A is asserting (pulling low) the INT pin, it will

alsoacknowledgetheAlertResponseAddress(0001100)b

using the receive byte protocol.

Isolating the Serial Digital Interface

IEEE 802.3af requires that network segments be electri-

cally isolated from the chassis ground of each network

interface device. However, the network segments are not

required to be isolated from each other provided that the

segments are connected to devices residing within a

single building on a single power distribution system.

For simple devices such as small powered Ethernet

switches, the requirement can be met by using an iso-

lated power supply to power the entire device. This

implementation can only be used if the device has no

electrically conducting ports other than twisted-pair Eth-

The START and STOP Conditions

When the bus is idle, both SCL and SDA must be high. A

bus master (typically the host controller) signals the

beginning of communication with a slave device (like the

4259Af

23

LTC4259A

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APPLICATIO S I FOR ATIO

0.1µF

2

I C ADDRESS

V

DD

INT

SCL

SDAIN

SDAOUT

AD0 LTC4259A

AD1

AD2

AD3

0100000

0100001

0100010

DGND

AGND

0.1µF

BYP

0.1µF

V

DD

INT

SCL

2k

U2

SDAIN

SDAOUT

AD0 LTC4259A

AD1

AD2

AD3

200Ω

V

DD

CPU

SCL

U1

2k

DGND

200Ω

AGND

BYP

0.1µF

SDA

0.1µF

HCPL-063L

V

DD

TO

INT

SCL

CONTROLLER

U3

200Ω

SDAIN

SDAOUT

AD0 LTC4259A

AD1

AD2

AD3

DGND

SMBALERT

AGND

BYP

0.1µF

•

0.1µF

GND CPU

HCPL-063L

U1: FAIRCHILD NC7WZ17

U2, U3: AGILENT HCPL-063L

V

INT

DD

SCL

SDAIN

SDAOUT

AD0 LTC4259A

0101110

AD1

AD2

AD3

DGND

AGND

BYP

0.1µF

ISOLATED

3.3V

V

INT

DD

SCL

SDAIN

SDAOUT

AD0 LTC4259A

AD1

+

10µF

0101111

AD2

AD3

DGND

AGND

ISOLATED

GND

BYP

4258A F18

0.1µF

Figure 18. Optoisolating the I²C Bus

4259Af

24

LTC4259A

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APPLICATIO S I FOR ATIO

U

LTC4259A) by transmitting a START condition. A START

condition is generated by transitioning SDA from high to

low while SCL is high. When the master has finished

communicating with the slave, it issues a STOP condition.

A STOP condition is generated by transitioning SDA from

low to high while SCL is high. The bus is then free for

communication with another SMBus or I²C device.

Read Byte Protocol

The master initiates communication from the LTC4259A

with a START condition and the same 7-bit bus address

followed by the Write Bit (Wr) = 0. If the LTC4259A

recognizes its own address, it acknowledges and the

master delivers the command byte, signifying which

internal LTC4259A register it wishes to read from. The

LTC4259A acknowledges and latches the lower five bits

ofthecommandbyteintoitsRegisterAddressregister. At

this time the master sends a REPEATED START condition

and the same 7-bit bus address followed by the Read Bit

(Rd) = 1. The LTC4259A acknowledges and sends the

contents of the requested register. Finally, the master

declines to acknowledge and terminates communication

with a STOP condition. Upon reception of the STOP

condition, the Register Address register is cleared (see

Figure 8).

Acknowledge

The Acknowledge signal is used for handshaking between

the master and the slave. An Acknowledge (active LOW)

generated by the slave lets the master know that the latest

byte of information was received. The corresponding SCL

clock pulse is always generated by the master. The master

releases the SDA line (HIGH) during the Acknowledge

clock pulse. The slave must pull down the SDA line during

the Acknowledge clock pulse so that it remains a stable

LOW during the HIGH period of this clock pulse. When the

master is reading from a slave device, it is the master’s

responsibility to acknowledge receipt of the data byte in

the bit that follows unless the transaction is complete. In

that case the master will decline to acknowledge and issue

the STOP condition to terminate the communication.

Receive Byte Protocol

Since the LTC4259A clears the Register Address register

on each STOP condition, the interrupt register (register 0)

may be read with the Receive Byte Protocol as well as with

the Read Byte Protocol. In this protocol, the master

initiates communication with the LTC4259A with a START

condition and a 7-bit bus address followed by the Read Bit

(Rd) = 1. The LTC4259A acknowledges and sends the

contents of the interrupt register. The master then de-

clines to acknowledge and terminates communication

with a STOP condition (see Figure 9).

Write Byte Protocol

ThemasterinitiatescommunicationtotheLTC4259Awith

a START condition and a 7-bit bus address followed by the

Write Bit (Wr) = 0. If the LTC4259A recognizes its own

address,itacknowledgesandthemasterdeliversthecom-

mandbyte, signifyingtowhichinternalLTC4259Aregister

the master wishes to write. The LTC4259A acknowledges

andlatchesthelowerfivebitsofthecommandbyteintoits

Register Address register. Only the lower five bits of the

command byte are checked by the LTC4259A; the upper

three bits are ignored. The master then delivers the data

byte.TheLTC4259Aacknowledgesoncemoreandlatches

the data into the appropriate control register. Finally, the

master terminates the communication with a STOP condi-

tion. Upon reception of the STOP condition, the Register

Address register is cleared (see Figure 7).

Alert Response Address and the INT Pin

InasystemwhereseveralLTC4259AsshareacommonINT

line,themastercanusetheAlertResponseAddress(ARA)

to determine which LTC4259A initiated the interrupt.

The master initiates the ARA procedure with a START

condition and the 7-bit ARA bus address (0001100)b

followed by the Read Bit (Rd) = 1. If an LTC4259A is

asserting the INT pin, it acknowledges and sends its 7-bit

bus address (010A₃A₂A₁A₀)b and a 1 (see Figure 10).

4259Af

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APPLICATIO S I FOR ATIO

While it is sending its address, it monitors the SDAIN pin

to see if another device is sending an address at the same

time using standard I²C bus arbitration. If the LTC4259A

is sending a 1 and reads a 0 on the SDAIN pin on the rising

edge of SCL, it assumes another device with a lower

address is sending and the LTC4259A immediately aborts

its transfer and waits for the next ARA cycle to try again.

If transfer is successfully completed, the LTC4259A will

stoppullingdowntheINTpin.WhentheINTpinisreleased

in this way or if a 1 is written into the Clear Interrupt pin bit

(bit6ofregister1Ah),theconditioncausingtheLTC4259A

to pull the INT pin down must be removed before the

LTC4259A will be able to pull INT down again. This can be

done by reading and clearing the event registers or by

writing a 1 into the Clear All Interrupts bit (bit 7 of register

1Ah). ThestateoftheINTpincanonlychangebetweenI²C

transactions, so an interrupt is cleared or new interrupts

are generated after a transaction completes and before

newI²Cbuscommunicationcommences.Periodicpolling

of the alert response address can be used instead of the

INT pin if desired. If any device acknowledges the alert

response address, then the INT line, if connected, would

have been low.

each PD’s power consumption. In order for a PSE to

implement power allocation, the PSE’s processor/con-

troller must control whether ports are powered—the

LTC4259A cannot be allowed to operate in Auto mode.

Semiauto mode fits the bill as the LTC4259A automati-

cally detects and classifies PDs, then makes this informa-

tion available to the host controller, which decides to

apply power or not. Operating the LTC4259A in Manual

mode also lets the controller decide whether to power the

ports but the controller must also control detection and

classification. Ifthehostcontrolleroperatesnearthelimit

of its computing resources, it may not be able to guide a

Manual mode LTC4259A through detect, class and port

turn-on in less than the IEEE mandated maximum of

950ms.

In a typical PSE, the LTC4259As will operate in Semiauto

mode as this allows the controller to decide to power a

port without unduly burdening the controller. With an

interrupt mask of F4h, the LTC4259A will signal to the

host after it has successfully detected and classed a PD,

at which point the host can decide whether enough power

is available and command the LTC4259A to turn that port

on.Similarly,theLTC4259Awillgenerateinterruptswhen

a port’s power is turned off. By reading the LTC4259A’s

interrupt register, the host can determine if a port was

turned off due to overcurrent (t_STARTor t_ICUTfaults) or

because the PD was removed (Disconnect event). The

hostthenupdatestheamountofavailablepowertoreflect

the power no longer consumed by the disconnected PD.

SettingtheMSBoftheinterruptmaskcausestheLTC4259A

tocommunicatefaultconditionscausedbyfailureswithin

thePSE, sothehostdoesnotneedtopolltocheckthatthe

LTC4259As are operating properly. This interrupt driven

system architecture provides the controller with the final

say on powering ports at the same time, minimizing the

controller’s computation requirements because inter-

rupts are only generated when a PD is detected or on a

fault condition.

System Software Strategy

Control of the LTC4259A hinges on one decision, the

LTC4259A’s operating mode. The three choices are de-

scribed under Operating Modes. In Auto mode the

LTC4259A can operate autonomously without direction

from a host controller. Because LTC4259As running in

Auto mode will power every valid PD connected to them,

the PSE must have 15.4W/port available. To reduce the

power requirements of the –48V supply, PSE systems

can track power usage, only turning on ports when

sufficient power is available. The IEEE describes this as a

powerallocationalgorithmandplacestwolimitations:the

PSE shall not power a PD unless it can supply the

guaranteed power for that PD’s class (see Table 2) and

power allocation may not be based solely on a history of

4259Af

26

LTC4259A

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APPLICATIO S I FOR ATIO

U

The LTC4259A can also be used to power older powered

Ethernet devices that are not 802.3af compliant and may

be detected with other methods. Although the LTC4259A

does not implement these older detection methods auto-

matically, if software or external circuitry can detect the

noncompliant devices, the host controller may command

the LTC4259A to power the port, bypassing IEEE compli-

ant detection and classification and sending power to the

noncompliant device.

voltage to the –48V rail, improving the regulation toler-

ance over the more traditional large resistor voltage

divider. This approach achieves high accuracy with a

transformerless design.

IEEE 802.3af COMPLIANCE AND EXTERNAL

COMPONENT SELECTION

The LTC4259A is designed to control power delivery in

IEEE802.3afcompliantPowerSourcingEquipment(PSE).

Because proper operation of the LTC4259A may depend

on external signals and power sources, like the –48V

supply (V_EE) or the OSCIN oscillator source, external

components such as the sense resistors (R_S), and possi-

bly software running on an external microprocessor,

using the LTC4259A in a PSE does not guarantee 802.3af

compliance. Using an LTC4259A does get you most of the

way there. This section discusses the rest of the elements

that go along with the LTC4259A to make an 802.3af

complaint PSE. Each paragraph below addresses a com-

ponent which is critical for PSE compliance as well as

LOGIC LEVEL SUPPLY

In additon to the 48V used to source power to each port,

alogiclevelsupplyisrequiredtopowerthedigitalportion

of the LTC4259A. To simplify design and meet voltage

isolation requirements, the logic level supply can be

generated from the isolated –48V supply. Figure 19

shows an example method using an LT^®1619 to control

a –48V to 3.3V current mode supply. This boost con-

verter topology uses the LT1619 current mode controller

and a current mirror which reflects the 3.3V output

B1100

4.7µH

100µH

V

DD

3.3V

ISOLATED

300mA

510Ω

910k

GND

+

47µF

3.32k

1%

+

10V

1µF

Si2328DS

100V

100Ω

Si2328DS

ISOLATED

GND

10µF

16V

8

7

6

CMPZ4702B

V

DRV GATE

SENSE

FMMT593

100k

FMMT593

IN

5

2

LT1619

FB

S/S GND

V

C

0.100Ω

1%

1W

1.24k

1%

1

4

3

47k

4700pF

100pF

V

EE

10Ω

ISOLATED

–48V

4259A F19

Figure 19. –48V to 3.3V Boost Converter

4259Af

27

LTC4259A

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APPLICATIO S I FOR ATIO

fer and EMI) when a common mode choke is used on each

port. In the name of cost reduction, some designs share a

common mode choke between two adjacent ports. Even

for nonpowered Ethernet, sharing a choke is not recom-

mended. With two ports passing through the choke, it

cannot limit the common mode current of either port.

Instead, the choke only controls the sum of both ports’

common mode current. Because cabling from the ports

generally connects to different devices up to 200m apart,

a current loop can form. In such a loop, common mode

current flows in one port and out the other, and the choke

will not prevent this because the sum of the currents is

zero. Another way to view this interaction between the

paired ports is that the choke acts as a transformer

coupling the ports’ common modes together. In

nonpowered Ethernet, common mode current results

from nonidealities like ground loops; it is not part of

normal operation. However, Power over Ethernet sends

power and hence significant current through the ports;

common mode current is a byproduct of normal opera-

tion. As described in the Choosing External MOSFETs

section and under the Power Supplies heading below,

large transients can occur when a port’s power is turned

on or off. When a powered port is shorted (see Surge

Suppressors and Circuit Protection), a port’s common

mode current may be excessive. Sharing a common mode

choke between two ports couples start-up, disconnect

and fault transients from one port to the other. The end

result can range from momentary noncompliance with

802.3af to intermittent behavior and even to excessive

voltages that may damage circuitry (in both the PSE and

PD) connected to the ports.

possible pitfalls that can cause a PSE to be noncompliant.

For further assistance please contact Linear Technology’s

Applications department.

Sense Resistors

The LTC4259A is designed to use a 0.5Ω sense resistor,

R_S, to monitor the current through each port. The value of

the sense resistor has been minimized in order to reduce

power loss and as a consequence, the voltage which the

LTC4259A must measure is small. Each port may be

drawingupto450mAwiththiscurrentflowingthroughthe

sense resistor and associated circuit board traces. To

prevent parasitic resistance on the circuit board from

obscuring the voltage drop across the sense resistor, the

LTC4259A must Kelvin sense the resistor voltage. One

way to achieve Kelvin sensing is “star grounding,” shown

pictorially in Figure 1. Another option is to use a –48V

power plane to connect the sense resistor and the

LTC4259A V_EEpin. Either of these strategies will prevent

voltages developed across parasitic circuit board resis-

tances from affecting the LTC4259A current measure-

mentaccuracy. Theprecisionofthesenseresistordirectly

affects the measurement of the IEEE parameters I_INRUSH

,

I_LIM, I_CUTand I_MIN. Therefore, to maintain IEEE compli-

ance, use a resistor with 0.5% or better accuracy.

Power MOSFETs

The LTC4259A controls power MOSFETs in order to

regulate current flow through the Ethernet ports. Under

certain conditions these MOSFETs have to dissipate sig-

nificant power. See the Choosing External MOSFETs sec-

tion for a detailed discussion of the requirements these

devices must meet.

Detect, AC Blocking and Transient Supressor Diodes

During detection and classification, the LTC4259A senses

the port voltage through the detect diodes D_DETin Figure

16. Excessive voltage drop across D_DETwill corrupt the

LTC4259A’s detect and classification results. Select a

Common Mode Chokes

Both nonpowered and powered Ethernet connections

achieve best performance (for data transfer, power trans-

4259Af

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LTC4259A

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APPLICATIO S I FOR ATIO

U

diodeforD_DETthatwillhavelessthan0.7Vofforwarddrop

at 0.4mA and less than 0.9V of forward drop at 50mA.

ing. See the AC Disconnect section for more information.

Also, C_PSEmay be important to the voltage stability of a

powered port. Port voltage instability is generally not a

problemifV_EE,the–48Vsupply,iswellbypassed.Forboth

of these reasons be aware that many ceramic dielectrics

have dramatic DC voltage and temperature coefficients. A

0.22µF ceramic capacitor is often nowhere near 0.22µF

when operating at 50VDC or 100VDC. Use 100V or higher

rated X7R capacitors for C_DETand C_PSEas these have re-

ducedvoltagedependancewhilealsobeingrelativelysmall

and inexpensive.

When the port is powered, the detect diode is reverse bi-

ased. Any leakage through the detect diode prevents the

LTC4259Afromsensingallthecurrentcoupledthroughthe

C

_DETcapacitor. At high temperature with 70V of reverse

bias, a typical switching diode like the 1N4148 may have

morethan50µAofleakage.Suchleakagecaninterferewith

AC disconnect because it is a large fraction of the

LTC4259A’sI_ACDMINthreshold.Usingalowleakagedetect

diode like the CMPD3003 is recommended.

The AC blocking diodes can interfere with AC disconnect

sensingiftheybecomeleaky.IftheACblockingdiode(D_AC

in Figure 16) begins leaking, it contributes to the Ethernet

port impedance, potentially bringing the impedance low

enoughtodrawI_ACDMINfromtheDETECTpinandkeepthe

port powered. More likely, leakage through the AC block-

ing diode will cause shifts in the AC disconnect threshold

that are not large enough to make the PSE noncompliant.

Generally, diode leakage is caused by voltage or tempera-

ture stress. Diodes that are rated to 100V or more and can

handle dissipating at least 0.5W should be acceptable in

this application. Other component leakages can have a

similaraffectonACdisconnectandevenaffectDCdiscon-

nect if the leakage becomes severe. Among components

to be wary of are the transient surge suppressors. The

devices shown in Figure 1 are rated for less than 5µA of

leakage at 58V. However there is a potential for stress

induced leakage, so healthy margins should be used when

selecting diodes for these applications.

Power Supplies

The LTC4259A must be supplied with 3.3V (V_DD) and

–48V (V_EE). Poor regulation on either of these supplies

can lead to noncompliance. The IEEE requires a PSE

outputvoltagebetween44Vand57V. WhentheLTC4259A

begins powering an Ethernet port, it controls the current

through the port to minimize disturbances on V_EE. How-

ever, if the V_EEsupply is underdamped or otherwise

unstable, its voltage could go outside of the IEEE specified

limits, causing all ports in the PSE to be noncompliant.

This scenario can be even worse when a PD is unplugged

because the current can drop immediately to zero. In both

cases the port voltage must always stay between –44V

and –57V. In addition, the 802.3af specification places

specific ripple, noise and load regulation requirements on

the PSE. Among other things, disturbances on either V_DD

orV_EEcanadverselyaffectdetection,classificationandthe

AC disconnection sensing. Proper bypassing and stability

of the V_DDand V_EEsupplies is important.

Capacitors

Another problem that can affect the V_EEsupply is insuffi-

cient power, leading to the supply voltage drooping out of

the specified range. The 802.3af specification states that

Sizing of both the C_DETand C_PSEcapacitors is critical to

proper operation of the LTC4259A’s AC disconnect sens-

4259Af

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APPLICATIO S I FOR ATIO

if a PSE powers a PD it must be able to provide the

maximum power level requested by the PD based on the

PD’s classification. The specification does allow a PSE to

choose not to power a port because the PD requires more

power than the PSE has left to deliver. If a PSE is built with

a V_EEsupply capable of less than 15.4W • (number of

PSE’s Ethernet ports), it must implement a power alloca-

tion algorithm that prevents ports from being powered

when there is insufficient power. Because the specifica-

tion also requires the PSE to supply 400mA at up to a 5%

duty cycle, the V_EEsupply capability should be at least a

few percent more than the maximum total power the PSE

will supply to PDs. Finally, the LTC4259As draw current

from V_EE. If the V_DDsupply is generated from V_EE, that

power divided by the switcher efficiency must also be

added to the V_EEsupply’s capability.

OSCIN Input

AC disconnect also relies on an oscillating signal applied

to the OSCIN pin. Requirements for this signal are pro-

vided in the OSCIN Input and Oscillator Requirements

section. Out-of-band noise on the OSCIN pin will disrupt

the LTC4259A’s ability to sense the absence of a PD. Any

noisepresentattheOSCINpinisamplifiedbytheLTC4259A

and driven out of the DETECT pins (of powered ports with

ACdisconnectenabled). Duetotheamountofcapacitance

connected to the DETECT pins, driving this noise can

easily require more than I_ACDMIN, tripping the DETECT pin

current sense and keeping the port powered. During

circuit board layout, keep wiring from the oscillator to the

OSCIN pin away from noise sources like digital clock and

data lines. A single-stage RC lowpass filter (shown in

Figure 20) will attenuate out-of-band noise.

4259Af

30

LTC4259A

U

PACKAGE DESCRIPTIO

GW Package

36-Lead Plastic SSOP (Wide .300 Inch)

(Reference LTC DWG # 05-08-1642)

15.290 – 15.544*

(.602 – .612)

1.143 ±0.127

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19

10.668 MIN

7.416 – 7.747

10.160 – 10.414

(.400 – .410)

0.520 ±0.0635

0.800 TYP

RECOMMENDED SOLDER PAD LAYOUT

7.417 – 7.595**

(.292 – .299)

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

2.286 – 2.387

(.090 – .094)

2.463 – 2.641

(.097 – .104)

0.254 – 0.406

(.010 – .016)

× 45°

0° – 8° TYP

0.127 – 0.305

(.005 – .0115)

0.610 – 1.016

(.024 – .040)

0.800

(.0315)

BSC

0.231 – 0.3175

(.0091 – .0125)

0.304 – 0.431

(.012 – .017)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.152mm (0.006") PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

GW36 SSOP 0502

4259Af

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

31

LTC4259A

U

TYPICAL APPLICATIO

2V , 100Hz

P-P

1.2V OFFSET

OSCILLATOR

ISOLATED

3.3V

1k

ISOLATED

GND

0.1µF

1µF

0.1µF

100V

X7R

OSCIN DGND AGND

0.1µF

2k

V

DD

BYP

DETECT

U2

200Ω

R

SCL

DET

V

CPU

1/4

LTC4259A

DD

1k

SDAIN

SDAOUT

INT

L1

U1

C

DET

SCL

0.47µF

100V

X7R

V

EE

SENSE GATE OUT

D

DET

200Ω

CMPD3003

0.1µF

D

TSS

58V

SMAJ58A

R

S

10k

0.5Ω

SDA

Q1

IRFM120A

D

HCPL-063L

AC

–48V

ISOLATED

S1B

RJ45

U3

CONNECTOR

1/2 PULSE

H2009

200Ω

1

2

0.01µF

200V

3

4

5

6

7

8

200V

75Ω

SMBALERT

GND CPU

PHY

0.1µF

(NETWORK

PHYSICAL

LAYER

T1

1:1

HCPL-063L

CHIP)

0.01µF

D

: DIODES INC OR FAIRCHILD S1B

AC

200V

75Ω

: CENTRAL SEMI CMPD3003

DET

: DIODES INC SMAJ58A

TSS

: TDK C3225X7R2A474K

DET

C

L1: PULSE ENG PO473

Q1: FAIRCHILD IRFM120A

4258 F20A

R : VISHAY WSL2010 0.5Ω 0.5%

S

T1

1:1

T1: PULSE ENG H2009

1000pF

2000V

U1: FAIRCHILD NC7WZ17

U2, U3: AGILENT HCPL-063L

Figure 20. One Complete Isolated Powered Ethernet Port

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LT1619

Low Voltage Current Mode PWM Controller

–48V to 3.3V at 300mA, MSOP Package

2

LTC1694

SMBus/I C Accelerator

Improved I C Rise Time, Ensures Data Integrity

Non-IEEE 802.3af Compliant Current Levels

LTC4255

Quad Network Power Controller

LTC4257

IEEE 802.3af PD Interface Controller

Quad IEEE 802.3af Power Over Ethernet Controller

100V 400mA Internal Switch, Programmable Classification

100V 400mA Dual Current Limit

LTC4257-1

LTC4258

DC Disconnect Only

4259Af

LT/TP 0204 1K • PRINTED IN USA

32 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

LINEAR TECHNOLOGY CORPORATION 2003


型号：	LTC4259ACGW
厂家：	Linear
描述：	Quad IEEE 802.3af Power over Ethernet Controller with AC Disconnect 四IEEE 802.3af以太网供电控制器， AC断开连接电源电路电源管理电路光电二极管控制器以太网
文件：	总32页 (文件大小：326K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC4259ACGW [Linear]

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