LTC4263IDE-PBF [Linear]
Single IEEE 802.3af Compliant PSE Controller with Internal Switch; 单符合IEEE 802.3af标准的PSE控制器，内置开关
| 型号： | LTC4263IDE-PBF |
| 厂家： | 
Linear |
| 描述： | Single IEEE 802.3af Compliant PSE Controller with Internal Switch |
| 文件： | 总24页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4263
Single IEEE 802.3af
Compliant PSE Controller
with Internal Switch
DESCRIPTION
The LTC®4263 is an autonomous single-channel PSE
controller for use in IEEE 802.3af compliant Power over
Ethernet systems. It includes an onboard power MOSFET,
internal inrush, current limit, and short-circuit control,
IEEE 802.3af compliant PD detection and classification
circuitry, and selectable AC or DC disconnect sensing.
OnboardcontrolalgorithmsprovidecompleteIEEE802.3af
compliant operation without the need of a microcontroller.
The LTC4263 simplifies PSE implementation, needing
only a single 48V supply and a small number of passive
support components.
FEATURES
IEEE 802®.3af Compliant
n
n
Operation from a Single 48V Supply
n
Fully Autonomous Operation without
Microcontroller
n
Internal MOSFET with Thermal Protection
n
Power Management Works Across Multiple Ports
with Simple RC Network
n
Precision Inrush Control with Internal Sense Resistor
n
Powered Device (PD) Detection and Classification
n
AC and DC Disconnect Sensing
Robust Short-Circuit Protection
n
n
Pin-Selectable Detection Backoff for Midspan PSEs
Programmable onboard power management circuitry
permits multiple LTC4263s to allocate and share power
in multi-port systems, allowing maximum utilization of
the 48V power supply—all without the intervention of a
host processor. The port current limit can be configured
to automatically adjust to the detected PD class. Detec-
tion backoff timing is configurable for either Endpoint or
Midspanoperation.Built-infoldbackandthermalprotection
provide comprehensive fault protection.
n
Classification Dependent I
Current Threshold
CUT
n
n
LED Driver Indicates Port On and Blinks
Status Codes
Available in 14-Pin SO and 4mm × 3mm DFN
Packages
APPLICATIONS
n
IEEE 802.3af Compliant Endpoint/Midspan PSEs
n
Single-Port or Multi-Port Power Injectors
An LED pin indicates the state of the port controlled by
the LTC4263. When run from a single 48V supply, the LED
pin can operate as a simple switching current source to
reduce power dissipation in the LED drive circuitry.
n
Power Forwarders
n
Low-Port Count PSEs
n
Environment B PSEs
n
Standalone PSEs
The LTC4263 is available in 14-pin 4mm × 3mm DFN and
14-pin SO packages.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Single-Port Fully Autonomous PSE
1A
+
0.1μF
100V
0.1μF
100V
LTC4263
LED
V
DD5
ISOLATED
48V SUPPLY
0.1μF
TO PORT
LEGACY
ENFCLS
SMAJ58A
MAGNETICS
MIDSPAN
PWRMGT
SD
V
–
DD48
OUT
OUT
V
V
SS
SS
ACOUT
OSC
4263 TA01
4263fd
1
LTC4263
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
Supply Voltages
Operating Ambient Temperature Range
V
V
– V
........................................... 0.3V to –80V
LTC4263C................................................ 0°C to 70°C
LTC4263I.............................................–40°C to 85°C
Junction Temperature (Note 4) ............................. 125°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
SS
DD5
DD48
........................................ V – 0.3V to V + 6V
SS
SS
Pin Voltages and Currents
LEGACY, MIDSPAN, ENFCLS, PWRMGT
SD, OSC.................................. V – 0.3V to V + 6V
SS
SS
LED....................................... V – 0.3V to V + 80V
OUT, ACOUT............................................ (See Note 3)
SO..................................................................... 300°C
SS
SS
PIN CONFIGURATION
TOP VIEW
TOP VIEW
LED
LEGACY
1
2
3
4
5
6
7
14
13
12
11
10
9
V
LED
LEGACY
1
2
3
4
5
6
7
14 V
DD5
DD5
13 ENFCLS
ENFCLS
MIDSPAN
PWRMGT
12 SD
MIDSPAN
PWRMGT
SD
15
11
V
DD48
V
DD48
V
SS
V
SS
10 OUT
V
OUT
SS
9
8
OUT
V
SS
OUT
OSC
ACOUT
OSC
8
ACOUT
DE14 PACKAGE
S PACKAGE
14-LEAD PLASTIC SO
14-LEAD (4mm s 3mm) PLASTIC DFN
T
= 125°C, θ = 43°C/W, θ = 4.3°C/W
JA JC
JMAX
T
= 125°C, θ = 90°C/W, θ = 37°C/W
JA JC
EXPOSED PAD (PIN 15) IS V , MUST BE SOLDERED TO PCB
JMAX
SS
ORDER INFORMATION
LEAD FREE FINISH
LTC4263CDE#PBF
LTC4263IDE#PBF
LTC4263CS#PBF
LTC4263IS#PBF
TAPE AND REEL
PART MARKING*
4263
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC4263CDE#TRPBF
LTC4263IDE#TRPBF
LTC4263CS#TRPBF
LTC4263IS#TRPBF
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead Plastic SO
4263
–40°C to 85°C
0°C to 70°C
4263CS
4263IS
14-Lead Plastic SO
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD48 – VSS = 48V and VDD5 not driven externally. All voltages are
relative to VSS unless otherwise noted. (Notes 2, 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supplies
l
l
V
48V Supply Voltage
V
– V
SS
33
46
48
31
66
57
V
V
SUPPLY
DD48
To Maintain IEEE Compliant Output
l
l
V
V
UVLO Turn-Off Voltage
UVLO Hysteresis
V
DD48
– V Decreasing
29
33
1
V
V
UVLO_OFF
UVLO_HYS
SS
0.1
4263fd
2
LTC4263
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD48 – VSS = 48V and VDD5 not driven externally. All voltages are
relative to VSS unless otherwise noted. (Notes 2, 5)
SYMBOL
PARAMETER
CONDITIONS
– V Increasing
MIN
66
TYP
MAX
74
UNITS
l
l
l
l
V
V
V
OVLO Turn-Off Voltage
OVLO Hysteresis
V
DD48
70
V
V
V
V
OVLO_OFF
OVLO_HYS
DD5
SS
0.2
4.5
4.3
2
V
V
V
Supply Voltage
Internal Supply
Driven Externally
Driven Internally
5
5.5
4.5
DD5
DD5
DD48
4.4
l
l
I
I
Supply Current
V
– V = 5V
1
2
2
4
mA
mA
DD48
DD5
SS
Internal V
DD5
l
V
DD5
Supply Current
V
DD5
– V = 5V
1
2
mA
DD5
SS
Power MOSFET
R
On-Resistance
I = 350mA, Measured From OUT to V
1.5
2.4
3.0
Ω
Ω
ON
SS
l
l
l
I
OUT Pin Leakage
V
OUT
– V = V
– V = 57V
1
10
μA
OUT_LEAK
SS
DD48
SS
R
OUT Pin Pull-Up Resistance to V
0V ≤ (V
– V ) ≤ 5V
360
500
640
kΩ
PU
DD48
DD48
OUT
Current Control
l
l
l
I
Overload Current Threshold
Class 0, Class 3, Class 4 (Note 6)
Class 2
Class 1
355
165
95
375
175
100
395
185
105
mA
mA
mA
CUT
l
l
I
I
Short-Circuit Current Limit
Foldback Current Limit
V
V
– V = 5V
405
405
425
425
445
445
mA
mA
LIM
OUT
SS
– V
= 30V
DD48
OUT
l
l
V
V
– V
– V
= 0V (Note 7)
= 10V
30
110
60
140
120
180
mA
mA
FB
DD48
DD48
OUT
OUT
l
l
I
I
DC Disconnect Current Threshold
High Speed Fault Current Limit
5.2
7.5
9.8
mA
mA
MIN
(Note 8)
500
650
800
FAULT
Detection
l
l
I
Detection Current
First Point, V
– V = 10V
OUT
DD48
235
160
255
180
275
200
μA
μA
DET
DD48
Second Point, V
– V
= 3.5V
OUT
l
V
DET
Detection Voltage Compliance
V
DD48
V
DD48
– V , Open Port
21
V
OUT
– V = 57V
SS
l
l
l
R
R
R
Minimum Valid Signature Resistance
Maximum Valid Signature Resistance
Open Circuit Threshold
15.5
27.5
500
17
18.5
32
kΩ
kΩ
kΩ
DETMIN
DETMAX
OPEN
29.7
2000
Classification
l
l
V
Classification Voltage
V
V
– V , 0mA ≤ I
≤ 50mA
16.5
55
20.5
75
V
CLASS
CLASS
DD48
OUT
CLASS
I
I
Classification Current Compliance
Classification Threshold Current
= V
60
mA
OUT
DD48
l
l
l
Class 0 – 1
5.5
13.5
21.5
6.5
14.5
23
7.5
15.5
24.5
mA
mA
mA
TCLASS
Class 1 – 2
Class 2 – 3 (Note 9)
Power Management
l
V
Power Management Pin Threshold
0.98
1
1.02
V
PWRMGT
PWRMGT
l
l
l
I
Power Management Pin Output Current
Class 0, Class 3, Class 4
Class 1
Class 2
–75.6
–19.6
–34.3
–72.3
–18.8
–32.8
–69
–17.9
–31.3
μA
μA
μA
AC Disconnect
l
l
l
R
OSC Pin Input Impedance
2V ≤ (V
– V ) ≤ 3V
175
–140
103
250
110
325
140
115
kΩ
μA
Hz
OSC
OSC
OSC
OSC
SS
I
f
OSC Pin Output Current
OSC Pin Frequency
V
V
– V = 2V
SS
OSC
OSC
– V = 2V
SS
4263fd
3
LTC4263
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD48 – VSS = 48V and VDD5 not driven externally. All voltages are
relative to VSS unless otherwise noted. (Notes 2, 5)
SYMBOL
PARAMETER
CONDITIONS
2V ≤ (V – V ) ≤ 3V
MIN
0.95
–1
TYP
MAX
1.05
1
UNITS
V/V
mA
μA
l
l
l
l
A
VACD
Voltage Gain OSC to ACOUT
AC Disconnect Output Current
Remain Connected AC Pin Current
AC Disconnect Enable Signal
1.0
OSC
SS
I
I
V
OSC
V
OSC
V
OSC
– V = 2V, 0V ≤ (V
– V ) ≤ 4V
ACOUT SS
ACDMAX
ACDMIN
SS
– V = 2V
130
1.5
160
1.1
190
SS
V
– V , Port On
V
ACDEN
SS
Digital Interface (Note 10)
l
V
OLED
V
ILD
LED Output Low Voltage
Digital Input Low Voltage
I
= 10mA
2.2
V
LED
l
l
MIDSPAN, PWRMGT, ENFCLS, SD LEGACY
0.8
0.4
V
V
l
l
V
Digital Input High Voltage
MIDSPAN, PWRMGT, ENFCLS, SD LEGACY
2.2
2.2
V
IHD
l
l
l
V
Voltage of Legacy Pin if Left Floating
Current In/Out of Legacy Pin
1.1
–60
–10
1.25
1.4
60
10
V
μA
μA
OZ
I
I
0V ≤ (V – V ) ≤ 5V
LEGACY SS
OLEG
FLT
Maximum Allowed Leakage of External Components
at Legacy Pin in Force Power-On Mode
Timing Characteristics
l
l
l
l
l
t
t
t
t
t
Detection Time
Beginning to End of Detection
270
300
34
290
310
620
39
ms
ms
ms
ms
μs
DET
Detection Delay
PD Insertion to Detection Complete
DETDLY
PDC
Classification Duration
Power Turn-On Delay
Turn-On Rise Time
37
End of Valid Detect to Application of Power
135
40
145
170
155
PON
V
C
– V : 10% to 90%
OUT
RISE
DD48
PSE
= 0.1μF
l
l
l
l
t
t
t
t
Overload/Short-Circuit Time Limit
Error Delay
52
3.8
320
62
4.0
350
72
4.2
380
20
ms
s
OVLD
I
Fault to Next Detect
ED
CUT
Maintain Power Signature (MPS) Disconnect Delay PD Removal to Power Removal
ms
ms
MPDO
MPS
MPS Minimum Pulse Width
PD Minimum Current Pulse Width
Required to Stay Connected (Note 11)
l
l
t
t
Midspan Mode Detection Backoff
Power Removal Detection Delay
3.0
0.8
3.2
3.4
1.1
s
s
R
PORT
= 15.5kΩ
DBO
0.95
DISDLY
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 6: If the ENFCLS pin is high, I
classification. If ENFCLS pin is low, I
Note 7: In order to reduce power dissipated in the switch while charging
the PD, the LTC4263 reduces the current limit when V – V is large.
Refer to the Typical Performance Characteristics for more information.
depends on the result of
CUT
reverts to its Class 0 specification.
CUT
OUT
SS
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to V unless otherwise
SS
Note 8: The LTC4263 includes a high speed current limit circuit intended to
protect against faults. The fault protection is activated for port current
specified.
Note 3: 80mA of current may be pulled from the OUT or ACOUT pin
without damage whether the LTC4263 is powered or not. These pins will
in excess of I
. After the high speed current limit activates, the short-
FAULT
circuit current limit (I ) engages and restricts current to IEEE 802.3af
levels.
LIM
also withstand a positive voltage of V + 80V.
SS
Note 9: Class 4 or higher classification current is treated as Class 3.
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 5: The LTC4263 operates with a negative supply voltage. To avoid
confusion, voltages in this data sheet are referred to in terms of absolute
magnitude.
Note 10: The LTC4263 digital interface operates with respect to V . All
SS
logic levels are measured with respect to V
.
SS
Note 11: The IEEE 802.3af specification allows a PD to present its
Maintain Power Signature (MPS) on an intermittent basis without being
disconnected. In order to stay powered, the PD must present the MPS for
t
within any t
time window.
MPS
MPDO
4263fd
4
LTC4263
TYPICAL PERFORMANCE CHARACTERISTICS
Classification Transient
Response to 40mA Load Step
Powering a Legacy PD with
220μF Bypass Capacitor
Powering an IEEE 802.3af PD
V
– V = 48V
SS
= 25°C
DD48
V
V
DD48
DD48
T
A
V
POWER
ON
OUT
V
OUT
2V/DIV
20V/DIV
DETECTION DETECTION
V
V
– 18V
DD48
DD48
V
SS
V
PHASE 1
PHASE 2
OUT
– 19V
LOAD
10V/DIV
425mA CURRENT LIMIT
FULLY
CLASSIFICATION
40mA
I
20mA/DIV
0mA
400mA
CHARGED
FOLDBACK
CLASSIFICATION
I
OUT
OUT
V
SS
200mA/DIV
0mA
4263 G01
4263 G06
4263 G02
100ms/DIV
100μs/DIV
25ms/DIV
Overload Restart Delay
Midspan Backoff with Invalid PD
Overcurrent Response Time
V
V
V
DD48
DD48
DD48
t
DBO
V
OUT
t
ED
20V/DIV
PORT OFF
V
OUT
V
SS
V
OUT
10V/DIV
2V/DIV
400mA
I
t
OUT
OVLD
V
SS
PORT
200mA/DIV
0mA
I
LOAD
500mA/
DIV
R
PORT
= 15.5kΩ
APPLIED
4263 G11
4263 G10
4263 G12
500ms/DIV
500ms/DIV
10ms/DIV
Response to PD Removal with
AC Disconnect Enabled
Rapid Response to
Momentary 50Ω Short
Rapid Response to 1Ω Short
V
DD48
V
V
DD48
DD48
V
V
OUT
OUT
20V/DIV
20V/DIV
V
OUT
I
= CURRENT IN
V
V
PORT
SS
SS
10V/DIV
50Ω SHORT APPLIED
SHORT
1Ω RESISTOR APPLIED
TO OUTPUT OF CIRCUIT
ON FRONT PAGE
PD REMOVAL
PORT OFF
CURRENT
LIMIT ACTIVE
REMOVED
800mA
PORT
400mA/DIV
0mA
I
1Ω SHORT
APPLIED
V
I
SS
PORT
20A/
DIV
20A
0A
t
MPDO
FOLDBACK CURRENT LIMIT
100μs/DIV
4263 G13
4263 G14
4263 G15
50ms/DIV
1μs/DIV
I
= CURRENT IN 50Ω RESISTOR APPLIED
PORT
TO OUTPUT OF CIRCUIT ON FRONT PAGE
4263fd
5
LTC4263
TYPICAL PERFORMANCE CHARACTERISTICS
LED Pin Pulldown
vs Load Current
Current Limit and Foldback
Classification Current Compliance
80
70
60
50
40
30
20
10
0
450
400
350
300
250
200
150
100
50
4
3
2
1
0
T
= 25°C
V
T
– V = 48V
DD48 SS
A
INTERNAL V
= 25°C
DD5
A
0
0
5
10 15 20 25
50
0
10
20
30
40
50
0
4
8
12
(V)
16
20
30 35 40 45
OUT
V
DD48
– V
I
LOAD CURRENT (mA)
V
DD48
– V
LED
OUT
4263 G03
4263 G04
4263 G05
IDD48 DC Supply Current vs Supply
Voltage with Internal VDD5
IDD48 DC Supply Current vs
Supply Voltage with VDD5 = 5.0V
IDD5 DC Supply Current
vs Supply Voltage
2.5
2.0
1.5
1.0
0.5
0
1.2
1.0
0.8
0.6
0.4
0.2
0
2
1
25k LOAD WITH
AC ENABLED
T
A
= 25°C
T
= 25°C
V
DD48
= 48V
A
25k LOAD WITH
AC ENABLED
25k LOAD WITH
AC ENABLED
NO LOAD
0
NO LOAD
NO LOAD
–1
–2
–3
0
10
20
30
40
50
60
0
10
20
30
40
50
60
4.0
4.5
5.0
5.5
6.0
V
(V)
V
DD48
(V)
V
DD5
DD48
4263 G07
4263 G08
4263 G09
RON vs Temperature
Legacy Pin Current vs Voltage
2.0
1.8
1.6
1.4
1.2
1.0
40
20
LEGACY MODE
FORCE POWER ON MODE
COMPLIANT MODE
0
–20
–40
0
1
2
3
4
5
–40 –20
0
20
40
60
80 100
TEMPERATURE (°C)
V
(V)
LEGACY
4263 G17
4263 G16
4263fd
6
LTC4263
TEST TIMING
Detect, Class and Turn-On Timing
Current Limit Timing
PD
INSERTED
V
DD48
I
LIM
I
CUT
I
OUT
OUT
t
DET
t
OVLD
V
OUT
V
PORT
TURN-ON
DD48
V
CLASS
V
t
V
SS
PDC
t
t
PON
4263 TT02
DETDLY
4263 TT01
DC Disconnect Timing
AC Disconnect Timing
V
V
I
I
OSC
MIN
OUT
V
DD48
V
DD48
V
V
OUT
OUT
SS
t
t
MPDO
V
SS
MPS
4263 TT03
I
ACDMIN
I
ACOUT
PD REMOVED
t
MPDO
4263 TT04
4263fd
7
LTC4263
PIN FUNCTIONS (DFN/SO)
LED(Pin1):PortStateLEDDrive. Thispinisanopendrain
outputthatpullsdownwhentheportispowered.Underport
fault conditions, the LED will flash in patterns to indicate
the nature of the port fault. See the Applications Informa-
tion section for a description of these patterns. When the
LTC4263 is operated from a single 48V supply, this pin is
pulsed low with a 6% duty cycle during the periods when
theLEDshouldbeon. Thisallowsuseofasimpleinductor,
diode, and resistor circuit to avoid excess heating due to
OSC (Pin 7) Oscillator for AC Disconnect. If AC discon-
nect is used, connect a 0.1μF X7R capacitor from OSC to
V . Tie OSC to V to disable AC disconnect and enable
SS
SS
DC disconnect.
ACOUT (Pin 8): AC Disconnect Sense. Senses the port
to determine whether a PD is still connected when in AC
disconnect mode. If port capacitance drops below about
0.15μF for longer than T
the port is turned off. If
MPDO
AC disconnect is used, connect this pin to the port with
a series combination of a 1k resistor and a 0.47μF 100V
X7R capacitor. See the Applications Information section
for more information.
the large voltage drop from V
. See the Applications
DD48
Information section for details on this circuit.
LEGACY (Pin 2): Legacy Detect. This pin controls whether
legacy detect is enabled. If held at V , legacy detect is
DD5
OUT (Pins 9, 10): Port Output. If DC disconnect is used,
these pins are connected to the port. If AC disconnect is
used,thesepinsareconnectedtotheportthroughaparallel
combination of a 1A diode and a 500k resistor. Pins 9 and
10shouldbetiedtogetheronthePCB.SeetheApplications
Information section for more information.
enabled and testing for a large capacitor is performed to
detect the presence of a legacy PD on the port. See the
ApplicationsInformationsectionfordescriptionsoflegacy
PDs that can be detected. If held at V , only IEEE 802.3af
SS
compliant PDs are detected. If left floating, the LTC4263
enters force-power-on mode and any PD that generates
between 1V and 10V when biased with 270μA of detection
current will be powered as a legacy device. This mode is
useful if the system uses a differential detection scheme
to detect legacy devices. Warning: Legacy modes are not
IEEE 802.3af compliant.
V
(Pin 11): 48V Return. Must be bypassed with a
DD48
0.1μF capacitor to V .
SS
SD (Pin 12): Shutdown. If held low, the LTC4263 is pre-
vented from performing detection or powering the port.
Pulling SD low will turn off the port if it is powered. When
released, a 4-second delay will occur before detection is
attempted.
MIDSPAN(Pin3):MidspanEnable.Ifthispinisconnected
to V , Midspan backoff is enabled and a 3.2 second
DD5
delay occurs after every failed detect cycle unless the
ENFCLS (Pin 13): Enforce Class Current Limits. If held
result is open circuit. If held at V , no delay occurs after
SS
at V , the LTC4263 will reduce the I
threshold for
DD5
CUT
failed detect cycles.
class 1 or class 2 PDs. If ENFCLS is held at V , I
SS CUT
remains at 375mA (typ) for all classes.
PWRMGT (Pin 4): Power Management. The LTC4263
sources current at the PWRMGT pin proportional to the
class of the PD that it is powering. The voltage of this pin
is checked before powering the port. The port will not
V
(Pin 14): Logic Power Supply. Apply 5V referenced
SS
DD5
to V , if such a supply is available, or place a 0.1μF
bypass capacitor to V to enable the internal regulator.
SS
turn on if this pin is more than 1V above V . Connect the
SS
When the internal regulator is used, this pin should only
PWRMGTpinsofmultipleLTC4263stogetherwitharesistor
be connected to the bypass capacitor and to any logic pins
and capacitor to V to implement power management. If
SS
of the LTC4263 that are being held at V
.
DD5
power management is not used, tie this pin to V .
SS
Exposed Pad (Pin 15, DE Package Only): V . Must be
SS
V
(Pins 5, 6): Negative 48V Supply. Pins 5 and 6 should
SS
connected to V on the PCB. The Exposed Pad acts as a
SS
be tied together on the PCB.
heatsink for the internal MOSFET.
4263fd
8
LTC4263
BLOCK DIAGRAM
1A
V
DD48
11
SD
12
13
2
14
ENFCLS
LEGACY
MIDSPAN
0.1μF
V
DD5
5V REG
INT5 EXT5
V
DD5
R
LED
3
+
48V
–
1
4
4
LED
TO PORT
MAGNETICS
500k
CONTROL
TO OTHER LTC4263s
PWRMGT
+
5V
–
SMAJ58A
I
DET
HOT SWAP
C
PM
500k
R
PM
9
5
6
10
V
OUT
SS
0.47μF
0.1μF
1k
7
8
OSC
ACOUT
4263 BD
BOLD LINES INDICATE HIGH CURRENT
4263fd
9
LTC4263
APPLICATIONS INFORMATION
POE OVERVIEW
and HVAC thermostats are examples of devices that can
draw power from the network.
Overtheyears,twisted-pairEthernethasbecomethemost
commonly used method for local area networking. The
IEEE 802.3 group, the originator of the Ethernet standard,
has defined an extension to the standard, IEEE 802.3af,
which allows DC power to be delivered simultaneously
over the same cable used for data communication. This
has enabled a whole new class of Ethernet devices, in-
cluding IP telephones, wireless access points, and PDA
charging stations which do not require additional AC
wiringorexternalpowertransformers, a.k.a. “wallwarts.”
With about 13W of power available, small data devices
can be powered by their Ethernet connections, free from
AC wall outlets. Sophisticated detection and power mon-
itoring techniques prevent damage to legacy data-only
devices while still supplying power to newer, Ethernet-
powered devices over the twisted-pair cable.
A PSE is required to provide a nominal 48V DC between
either the signal pairs or the spare pairs (but not both)
as shown in Figure 1. The power is applied as a voltage
between two of the pairs, typically by powering the cen-
ter taps of the isolation transformers used to couple the
differential data signals to the wire. Since Ethernet data
is transformer coupled at both ends and is sent differen-
tially, a voltage difference between the transmit pairs and
the receive pairs does not affect the data. A 10Base-T/
100Base-TXEthernetconnectiononlyusestwoofthefour
pairs in the cable. The unused or spare pairs can option-
ally be powered directly, as shown in Figure 1, without
affecting the data. 1000Base-T uses all four pairs and
power must be connected to the transformer center taps
if compatibility with 1000Base-T is required.
The LTC4263 provides a complete PSE solution for de-
tection and powering of PD devices in an IEEE 802.3af
compliant system. The LTC4263 controls a single PSE
port that will detect, classify, and provide isolated 48V
power to a PD device connected to the port. The LTC4263
senses removal of a PD with IEEE 802.3af compliant AC
or DC methods and turns off 48V power when the PD is
disconnected. An internal control circuit takes care of
system configuration and timing.
The device that supplies power is called the Power Sourc-
ing Equipment (PSE). A device that draws power from the
wire is called a Powered Device (PD). A PSE is typically an
Ethernet switch, router, hub, or other network switching
equipment that is commonly found in the wiring closets
where cables converge. PDs can take many forms. Digital
IP telephones, wireless network access points, PDA or
notebookcomputerdockingstations,cellphonechargers,
CAT 5
20Ω MAX
ROUNDTRIP
0.05μF MAX
PSE
PD
RJ45
4
RJ45
4
5
5
–48V RETURN
1N4002
SPARE PAIR
s4
0.1μF
0.1μF
1
1
V
DD48
SMAJ58A
58V
Tx
Rx
Tx
5mF ≤ C
≤ 300μF
IN
2
3
2
3
DATA PAIR
DATA PAIR
LTC4263
DD5
0.1μF
V
1N4002
s4
Rx
GND
CLASS
–48V
OUT
6
6
0.1μF
R
+
SMAJ58A
58V
LTC4267-BASED
PD/SWITCHER
OUT
V
OUT
V
SS
OUT
7
6
7
–48V SUPPLY
–48V
–
IN
6
SPARE PAIR
4263 F01
Figure 1. System Diagram
4263fd
10
LTC4263
APPLICATIONS INFORMATION
60
50
40
30
20
10
0
LTC4263 OPERATION
PSE LOAD
OVER
LINE
CURRENT
Signature Detection
48mA
CLASS 4
CLASS 3
The IEEE 802.3af specification defines a specific pair-to-
pair signature resistance used to identify a device that
can accept power via its Ethernet connection. When the
port voltage is below 10V, an IEEE 802.3af compliant
PD will have an input resistance of approximately 25kΩ.
Figure 2 illustrates the relationship between the PD sig-
nature resistance and the required resistance ranges the
PSE must accept and reject. According to the IEEE 802.3af
specification, the PSE must accept PDs with signatures
between 19kΩ and 26.5kΩ and may or may not accept
resistancesinthetworangesof15kΩto19kΩand26.5kΩ
to 33kΩ. The black box in Figure 2 represents the typical
150Ω pair-to-pair termination used in Ethernet devices
like a computer’s network interface card (NIC) that cannot
accept power.
33mA
23mA
CLASS 2
TYPICAL
CLASS 3
PD LOAD
LINE
14.5mA
6.5mA
CLASS 1
CLASS 0
0
5
10
V
15
– V
OUT
20
25
DD48
4263 F04
Figure 3. PD 2-Point Detection
the line to settle and measuring the resulting voltage. This
result is stored and the second current is applied to the
port, allowed to settle and the voltage measured.
The LTC4263 will not power the port if the PD has more
than5μFinparallelwithitssignatureresistorunlesslegacy
mode is enabled.
RESISTANCE 0Ω
10k
20k
30k
23.75k 26.25k
TheLTC4263autonomouslytestsforavalidPDconnected
to the port. It repeatedly queries the port every 580ms, or
every 3.2s if midspan backoff mode is active (see below).
If detection is successful, it performs classification and
power management and then powers up the port.
150Ω (NIC)
REJECT
PD
PSE
ACCEPT
REJECT
33k
15k 19k
26.5k
4263 F02
Figure 2. IEEE 802.3af Signature Resistance Ranges
Midspan Backoff
TheLTC4263checksforthesignatureresistancebyforcing
two test currents on the port in sequence and measuring
the resulting voltages. It then subtracts the two V-I points
to determine the resistive slope while removing voltage
offsetcausedbyanyseriesdiodesorcurrentoffsetcaused
by leakage at the port (see Figure 3). The LTC4263 will
typically accept any PD resistance between 17kΩ and
29.7kΩ as a valid PD. Values outside this range (exclud-
ing open and short-circuits) are reported to the user by a
code flashed via the LED pin.
IEEE802.3afrequiresthemidspanPSEtowaittwoseconds
after a failed detection before attempting to detect again
unless the port resistance is greater than 500kΩ. This
requirementistopreventtheconditionofanendpointPSE
andamidspanPSE, connectedtothesamePDatthesame
time, from each corrupting the PD signature and prevent-
ing power-on. After the first corrupted detection cycle, the
midspan PSE waits while the endpoint PSE completes
detection and turns the port on. If the midspan mode of
the LTC4263 is enabled by connecting the MIDSPAN pin
The LTC4263 uses a force-current detection method in
ordertoreducenoisesensitivityandprovideamorerobust
detection algorithm. The first test point is taken by forcing
a test current into the port, waiting a short time to allow
toV , a3.2seconddelayoccursaftereveryfaileddetect
DD5
cycle unless the result is an open circuit.
4263fd
11
LTC4263
APPLICATIONS INFORMATION
Classification
indicating the power class to which the PD belongs. Per
the IEEE 802.3af specification, there are five classes and
three power levels for a PD as shown in Table 1. Note that
class 4 is presently reserved by the IEEE for future use.
Figure 4 shows an example PD load line, starting with the
shallowslopeofthe25ksignatureresistorbelow10V,then
drawing the classification current (in this case, class 3)
between 15.5V and 20.5V. Also shown is the load line for
the LTC4263. It maintains a low impedance until reaching
current limit at 60mA (typ).
An IEEE 802.3af PD has the option of presenting a clas-
sificationsignaturetothePSEtoindicatehowmuchpower
it will draw when operating. This signature consists of a
specific constant-current draw when the PSE port volt-
age is between 15.5V and 20.5V, with the current level
60
PSE LOAD
OVER
LINE
CURRENT
50
40
30
20
10
0
48mA
The LTC4263 will classify a port immediately after a
successful detection. It measures the PD classification
signature current by applying 18V (typ) to the port and
measuring the resulting current. The LTC4263 identifies
the three IEEE power levels and stores the detected class
internally for use by the power management circuitry. In
addition, the LTC4263 allows selectable enforcement of
IEEE classification power levels. With the ENFCLS pin
CLASS 4
CLASS 3
33mA
23mA
CLASS 2
TYPICAL
CLASS 3
PD LOAD
LINE
14.5mA
6.5mA
CLASS 1
CLASS 0
0
5
10
15
20
25
V
DD48
– V
OUT
4263 F04
high, the LTC4263 reduces the I
current threshold if it
CUT
Figure 4. Classification Load Lines
detects class 1 or class 2, thereby insuring that PDs which
violate their advertised class are shut down.
Table 1. IEEE 802.3af Classification, PD Power Consumption, and LTC4263 Enforced Power Output
MAXIMUM
IEEE ALLOWABLE
PD POWER
LTC4263
IEEE 802.3af
CLASS
CLASSIFICATION
CURRENT
ENFORCED I
CUT
THRESHOLD*
375mA (typ)
100mA (typ)
175mA (typ)
375mA (typ)
375mA (typ)
CLASS DESCRIPTION
PD Does Not Implement Classification, Unknown Power
Low Power PD
0
1
2
3
4
0mA to 5mA
8mA to 13mA
16mA to 21mA
25mA to 31mA
35mA to 45mA
12.95W
3.84W
6.49W
Medium Power PD
12.95W
12.95W
Full Power PD
Reserved, Power as Class 0
*Enforced I
active if ENFCLS pin is high. Otherwise, I
is 375mA (typ).
CUT
CUT
4263fd
12
LTC4263
APPLICATIONS INFORMATION
Power Management
FormultipleLTC4263simplementingpowermanagement,
the PWRMGT pins are connected together and to a RC
The LTC4263 includes a power management feature
allowing simple implementation of power management
across multiple ports driven by a single power supply. The
PWRMGT pins of all LTC4263 devices are tied together
along with an RC network to prevent over-allocation of
power in a multi-port system.
networkconnectedtoV asshowninFigure5.Thevalueof
SS
R
PM
representsthefullloadoutputcapabilityofthesystem
power supply (P ). Select a 1% resistor to set the
FULL_LOAD
full load output power using the following formula:
213kΩ • W
PFULL_LOAD
RPM
=
Immediatelyfollowingclassification,theLTC4263performs
a power management check to ensure power is available
to supply the newly classed PD. The allocated power is
represented by the voltage on the shared PWRMGT node
and the LTC4263 checks the allocated power by measur-
ing this voltage. If the PWRMGT voltage is less than 1V,
there is power available and the power needs of the new
PD are added to the already allocated power on the node.
To allocate power, a current proportional to the power
needs for the new PD is sourced out of the PWRMGT pin
(Table 2).
The LTC4263 power management uses pulse width
modulation to set the power requirements of each PD.
Capacitor C is used as a lowpass filter to generate the
PM
average power requirement for all PDs in the system. Set
C
to 1μF.
PM
If power management is not used, tie PWRMGT to V .
SS
PWRMGT
LTC4263
Table 2. LTC4263 Power Management
V
SS
IEEE 802.3af
CLASS
PSE OUTPUT
POWER REQUIRED
LTC4263 PWRMGT
CURRENT
PWRMGT
LTC4263
0, 3, 4
15.4W
7W
–72.3μA
–32.8μA
–18.8μA
2
1
V
SS
4W
PWRMGT
LTC4263
When additional current is added to the PWRMGT node,
the voltage rises toward the 1V threshold. After adding
current, the LTC4263 verifies that the power supply is not
over-allocatedbyverifyingthenodevoltageremainsbelow
1V. If the voltage is below 1V, the LTC4263 proceeds to
power the port. If over 1V, the current is removed from
the node, port powering is aborted, and the LTC4263 goes
back into detection mode.
V
SS
PWRMGT
LTC4263
R
PM
C
PM
1μF
V
SS
V
SS
4263 F05
Figure 5. PWRMGT Pin Connections
4263fd
13
LTC4263
APPLICATIONS INFORMATION
Power Control
I referstocurrentatportturn-onandI isthemaxi-
INRUSH LIM
mumallowablecurrentinthecaseofashortaftertheportis
powered.BecausetheIEEEspecificationcallsoutidentical
values, the LTC4263 implements both as a single current
The primary function of the LTC4263 is to control the
delivery of power to the PSE port. In order to meet IEEE
802.3af requirements and provide a robust solution, a
variety of current limit and current monitoring functions
are needed, as shown in Figure 6. All control circuitry
is integrated and the LTC4263 requires no external
MOSFET, sense resistor, or microcontroller to achieve
IEEE compliance.
limitreferredtoasI
.
LIM
When 48V power is applied to the port, the LTC4263 is
designedtopower-upthePDinacontrolledmannerwithout
causingtransientsontheinputsupply.Toaccomplishthis,
the LTC4263 implements inrush current limit. At turn-on,
current limit will allow the port voltage to quickly rise
until the PD reaches its input turn-on threshold. At this
point, the PD begins to draw current to charge its bypass
capacitance, slowing the rate of port voltage increase.
The LTC4263 includes an internal MOSFET for driving
the PSE port. The LTC4263 drives the gate of the internal
MOSFET while monitoring the current and the output volt-
age at the OUT pin. This circuitry couples the 48V input
supply to the port in a controlled manner that satisfies
the PD’s power needs while minimizing disturbances on
the 48V backplane.
If at any time the port is shorted or an excessive load is
applied, the LTC4263 limits port current to avoid a haz-
ardous condition. The current is limited to I
for port
LIM
voltages above 30V and is reduced for lower port voltages
(see the Foldback section). Inrush and short-circuit cur-
rent limit are allowed to be active for 62ms (typ) before
the port is shut off.
500mA
CURRENT LIMIT
PORT OFF IN t
400mA
300mA
200mA
100mA
0mA
OVLD
Port Fault
NORMAL
OPERATION
Iftheportissuddenlyshorted, theinternalMOSFETpower
dissipationcanrisetoveryhighlevelsuntiltheshort-circuit
current limit circuit can respond. A separate high speed
DC DISCONNECT
current limit circuit detects severe fault conditions
(
I
>
OUT
PORT OFF IN t
MPDO
DC DISCONNECT CUT
(I (I
LIMIT
(I
650mA (typ)
)
and quickly turns off the internal MOSFET if
)
)
)
LIM
4263 F07
MIN
CUT
suchaneventoccurs.ThecircuitthenlimitscurrenttoI
LIM
Figure 6. Current Thresholds and Current Limits
while the t
LIM
timer increments. During a short-circuit,
OVLD
I
will be reduced by the foldback circuitry.
Port Overload
APSEportispermittedtosupplyupto15.4Wcontinuously
and up to 400mA (I ) for up to 75ms (t ) when in
overload. Per the IEEE 802.3af specification, the PSE is
required to remove power if a port stays in an overload
condition.TheLTC4263monitorsportcurrentandremoves
portpowerifportcurrentexceeds375mA(typ)forgreater
than 62ms (typ).
t
Timing
OVLD
CUT
OVLD
For overload, inrush, and short-circuit conditions, the
IEEE 802.3af standard limits the duration of these events
to 50ms-75ms. The LTC4263 includes a 62ms (typ) t
OVLD
timer to monitor overload conditions. The timer is incre-
mented whenever current greater than I flows through
CUT
the port. If the current is still above I
when the t
CUT
OVLD
Port Inrush and Short-Circuit
timer expires, the LTC4263 will turn off power to the port
and flash the LED. In this situation, the LTC4263 waits
four seconds and then restarts detection. If the overload
The IEEE 802.3af standard lists two separate maximum
currentlimits,I
andI ,thataPSEmustimplement.
INRUSH
LIM
4263fd
14
LTC4263
APPLICATIONS INFORMATION
condition is removed before the t
timer expires, the
power and shuts down all functions including the internal
5V regulator. Once the die cools, the LTC4263 waits four
seconds, then restarts detection.
OVLD
port stays powered and the timer is reset.
Foldback
DC Disconnect
Foldback is designed to limit power dissipation in the
LTC4263 during power-up and momentary short-circuit
conditions. At low port output voltages, the voltage
across the internal MOSFET is high, and power dissipa-
tion will be large if significant current is flowing. Foldback
TheDCdisconnectcircuitmonitorsportcurrentwhenever
power is on to detect continued presence of the PD. IEEE
802.3af mandates a minimum current of 10mA that the
PD must draw for periods of at least 75ms with optional
monitors the port output voltage and reduces the I
dropouts of no more than 250ms. The t
disconnect
LIM
MPDO
current limit level for port voltages of less than 28V, as
timer increments whenever port current is below 7.5mA
(typ). If the timer expires, the port is turned off and the
LTC4263 waits 1.5 seconds before restarting detection.
shown in Figure 7.
If the undercurrent condition goes away before t
500
400
300
MPDO
(
350ms (typ)), the timer is reset to zero. The DC discon-
nect circuit includes a glitch filter to prevent noise from
falsely resetting the timer. The current must be present for
a period of at least 20ms to guarantee reset of the timer.
To enable DC disconnect, tie the OSC pin to V .
SS
200
100
0
AC Disconnect
AC disconnect is an alternate method of sensing the pres-
enceorabsenceofaPDbymonitoringtheportimpedance.
TheLTC4263forcesanACsignalfromaninternalsinewave
generator on to the port. The ACOUT pin current is then
0
5
10 15 20 25 30 35 40 45 50
– V (V)
V
DD48
OUT
4263 F07
sampled once per cycle and compared to I
. Like DC
ACDMIN
Figure 7. Current Limit Foldback
disconnect,theACdisconnectsensingcircuitrycontrolsthe
disconnect timer. When the connection impedance
t
MPDO
Thermal Protection
rises due to the removal of the PD, AC peak current falls
below I and the disconnect timer increments. If the
The LTC4263 includes thermal overload protection in
order to provide full device functionality in a miniature
package while maintaining safe operating temperatures.
Several factors create the possibility for very large power
dissipation within the LTC4263. At port turn-on, while
ACDMIN
impedance remains high (AC peak current remains below
I
), the disconnect timer counts to t and the
ACDMIN
MPDO
port is turned off. If the impedance falls, causing AC peak
current to rise above I for two consecutive samples
ACDMIN
I
is active, the instantaneous power dissipated by the
before the maximum count of the disconnect timer, the
timer resets and the port remains powered.
LIM
LTC4263 can be as high as 12W. This can cause 40ºC or
moreofdieheatinginasingleturn-onsequence.Similarly,
excessive heating can occur if an attached PD repeatedly
The AC disconnect circuitry senses the port via the ACOUT
pin. Connect a 0.47μF 100V X7R capacitor (C ) and
DET
pushes the LTC4263 into I
by drawing too much cur-
LIM
a 1kΩ resistor (R ) from the DETECT pin to the port
DET
rent. Excessive heating can also occur if the V
shorted or overloaded.
pin is
DD5
output as shown in Figure 8. This provides an AC path for
sensing the port impedance. The 1kΩ resistor, R , limits
DET
The LTC4263 protects itself from thermal damage by
monitoringdietemperature.Ifthedietemperatureexceeds
the overtemperature trip point, the LTC4263 removes port
currentflowingthroughthispathduringportpower-onand
power-off. AnACblockingdiode(D )isinsertedbetween
AC
the OUT pin and the port to prevent the AC signal from
4263fd
15
LTC4263
APPLICATIONS INFORMATION
1A
+
C
0.1μF
100V
PSE
LTC4263
0.1μF
NC
LED
V
DD5
ISOLATED
48V SUPPLY
X7R, 100V
0.1μF
500k
LEGACY
ENFCLS
SMAJ58A
MIDSPAN
PWRMGT
SD
D
AC
V
–
DD48
CMLSH05-4
OUT
OUT
V
V
SS
SS
4263 F08
C
DET
0.1μF
0.47μF
R
DET
X7R, 100V
1k
OSC
ACOUT
Figure 8. LTC4263 Using AC Disconnect
being shorted by the LTC4263’s power control MOSFET.
detection,orwait3.2secondsbeforeattemptingdetection
again if in midspan mode.
The 500k resistor across D allows the port voltage to
AC
decay after disconnect occurs.
The LTC4263 may be reset by pulling the SD pin low. The
port is turned off immediately and the LTC4263 sits idle.
After SD is released there will be a 4-second delay before
the next detection cycle begins.
Sizing of capacitors is critical to ensure proper function
of AC disconnect. C (Figure 8) controls the connection
PSE
impedance on the PSE side. Its capacitance must be kept
low enough for AC disconnect to be able to sense the PD.
V
DD5
Logic-Level Supply
On the other hand, C
has to be large enough to pass
DET
the signal at 110Hz. The recommended values are 0.1μF
for C and 0.47μF for C . The sizes of C , C
The V
supply for the LTC4263 can either be supplied
DD5
externally or generated internally from the V
supply.
,
PSE DET
DD48
PSE
DET
If supplied externally, a voltage between 4.5V and 5.5V
should be applied to the V
regulator to shut down. If V
nally, the voltage will be 4.4V (typ) and a 0.1μF capacitor
should be connected between V
connect the internally generated V
than a bypass capacitor and the logic control pins of the
same LTC4263.
and R
are chosen to create an economical, physically
DET
pin to cause the internal
is to be generated inter-
compact and functionally robust system. Moreover, the
completePoweroverEthernetACdisconnectsystem(PSE,
transformers,cabling,PD,etc.)iscomplex;deviatingfrom
DD5
DD5
and V . Do not
DD5
DD5
SS
therecommendedvaluesofC ,R andC isstrongly
DET DET
PSE
to anything other
discouraged. Contact the Linear Technology Applications
department for additional support.
Internal 110Hz AC Oscillator
LED Flash Codes
The LTC4263 includes onboard circuitry to generate a
TheLTC4263includesamulti-functionLEDdrivertoinform
the user of the port status. The LED is turned on when the
port is connected to a PD and power is applied. If the port
is not connected or is connected to a non-powered device
with a 150Ω or shorted termination, the port will not be
powered and the LED will be off. For other port conditions,
the LTC4263 blinks a code to communicate the status
to the user as shown in Table 3. One flash indicates low
signatureresistance,twoflashesindicateshighresistance,
five flashes indicates an overload fault, and nine flashes
indicates that power management is preventing the port
110Hz (typ), 2V
0.1μF capacitor is connected between the OSC pin and
sine wave on its OSC pin when a
P-P
V . This sine wave is synchronized to the controller
SS
inside the LTC4263 and should not be externally driven.
Tying the OSC pin to V shuts down the oscillator and
enables DC disconnect.
SS
Power-On Reset and Reset/Backoff Timing
Upon start-up, the LTC4263 waits four seconds before
starting its first detection cycle. Depending on the re-
sults of this detection it will either power the port, repeat
from turning on.
4263fd
16
LTC4263
APPLICATIONS INFORMATION
When active, the LED flash codes are repeated every 1.2
seconds. The duration of each LED flash is 75ms. Multiple
LED flashes occur at a 300ms interval.
2.2μs. During the 2.2μs that the LED pin is pulled low, cur-
rent ramps up in the inductor, limited by R . Diode D2
LED
completes the circuit by allowing current to circulate while
the LED pin is open circuit. Since current is only drawn
from the power supply 6% of the time, power dissipation
is substantially reduced.
The LTC4263 includes a feature for efficiently driving the
LED from a 48V power supply without the wasted power
caused by having to drop over 45V in a current limit
resistor. When operating the V
supply internally, the
When V
is powered from an external supply, the PWM
DD5
DD5
LTC4263 drives the LED pin with a 6% duty cycle PWM
signal. This allows use of the simple LED drive circuit in
Figure 9 to minimize power dissipation. The modulation
frequency of the LED drive is 28kHz, making the on period
signal is disabled and the LED pin will pull down continu-
ouslywhenon.Inthismode,theLEDcanbepoweredfrom
the 5V supply with a simple series resistor.
IEEE 802.3af COMPLIANCE AND EXTERNAL
COMPONENT SELECTION
V
DD48
D1
This section discusses the other elements that go along
with the LTC4263 to make an IEEE 802.3af compliant PSE.
The LTC4263 is designed to control power delivery in IEEE
802.3af compliant Power Sourcing Equipment. Because
proper operation of the LTC4263 also depends on external
componentsandpowersourceslikethe48Vsupply, using
the LTC4263 in a PSE does not in itself guarantee IEEE
802.3af compliance. To ensure a compliant PSE design,
it is recommended to adhere closely to the example ap-
plication circuits provided. For further assistance contact
the Linear Technology Applications department.
10mH, 21mA
COILCRAFT
DS1608C-106
D2
BAS19
R
1k
LED
LED
V
DD48
LTC4263
V
DD5
0.1μF
V
SS
4263 F09
Figure 9. LED Drive Circuit with Single 48V Supply
Table 3. Port Status and LED Flash Codes
PORT STATUS
LED FLASH CODE
FLASH PATTERN
Non-Powered Device
Off
LED Off
0Ω < R
< 200Ω
PORT
Port Open
> 1MΩ
Off
LED Off
LED On
R
PORT
Port On
25kΩ
On
Low Signature Resistance
300Ω < R < 15kΩ
1 Flash
2 Flashes
5 Flashes
9 Flashes
PORT
High Signature Resistance
33kΩ < R < 500kΩ
PORT
Port Overload Fault
Power Management
Allocation Exceeded
4263fd
17
LTC4263
APPLICATIONS INFORMATION
Common Mode Chokes
a large flyback voltage to appear across the port when the
MOSFET is turned off. In the case of a short occurring
with a minimum length cable, the instantaneous current
can be extremely high due to the lower inductance. The
LTC4263 has a high speed fault current limit circuit that
shuts down the port in 20μs (typ). In this case, there is
lower inductance but higher current so the event is still
severe.Atransientsuppressorisrequiredtoclamptheport
voltageandpreventdamagetotheLTC4263. AnSMAJ58A
or equivalent device works well to maintain port voltages
within a safe range. A bidirectional transient suppressor
shouldnotbeused.Goodboardlayoutplacesthetransient
suppressor between the port and the LTC4263 to enhance
the protective function.
Both non-powered and powered Ethernet connections
achievebestperformancefordatatransferandEMIwhena
commonmodechokeisusedoneachport.Forcostreduc-
tion reasons, some designs share a common mode choke
between two adjacent ports. This is not recommended.
Sharingacommonmodechokebetweentwoportscouples
start-up, disconnect and fault transients from one port
to the other. The end result can range from momentary
noncompliance with IEEE 802.3af to intermittent behavior
and even to excessive voltages that may damage circuitry
in both the PSE and PD connected to the port.
Transient Suppressor Diode
If the port voltage reverses polarity and goes positive, the
OUTpincanbeoverstressedbecausethisvoltageisstacked
on top of the 48V supply. In this case, the transient sup-
pressor must clamp the voltage to a small positive value
to protect the LTC4263 and the PSE capacitor.
IEEE 802.3af Power over Ethernet is a challenging Hot
Swap™ application because it must survive unintentional
abuse by repeated plugging in and out of devices at the
port. Ethernet cables could potentially be cut or shorted
together. Consequently, the PSE must be designed to
handle these events without damage.
Component leakages across the port can have an adverse
affect on AC disconnect and even affect DC disconnect if
theleakagebecomessevere. TheSMAJ58Aisratedatless
than 5μA leakage at 58V and works well in this applica-
tion. There is a potential for stress induced leakage, so
sufficientmarginsshouldbeusedwhenselectingtransient
suppressors for these applications.
The most severe of these events is a sudden short on a
powered port. What the PSE sees depends on how much
CAT-5 cable is between it and the short. If the short oc-
curs on the far end of a long cable, the cable inductance
will prevent the current in the cable from increasing too
quickly and the LTC4263 built-in short-circuit protection
will control the current and turn off the port. However,
the high current along with the cable inductance causes
Hot Swap is a trademark of Linear Technology Corporation.
4263fd
18
LTC4263
APPLICATIONS INFORMATION
Capacitors
Power Supply
Sizing of both the C
and C
capacitors is critical for
PSE
Poor regulation on the 48V supply can lead to noncompli-
ance. TheIEEEspecificationrequiresaPSEoutputvoltage
between44Vand57V.WhentheLTC4263beginspowering
an Ethernet port, it controls the current through the port to
DET
proper operation of the LTC4263 AC disconnect sensing.
See the AC Disconnect section for more information. Note
that many ceramic capacitors have dramatic DC voltage
and temperature coefficients. Use 100V or higher rated
minimize disturbances on V . However, if the V supply
SS
SS
X7R capacitors for C and C , as these have reduced
is underdamped or otherwise unstable, its voltage could
go outside of the IEEE-specified limits, causing the PSE
to be noncompliant. This scenario can be even worse
when a PD is unplugged because the current can drop
immediately to zero. In both cases the port voltage must
always stay between 44V and 57V. Beyond this, the IEEE
802.3afspecificationplacesspecificripple, noiseandload
DET
PSE
voltage dependence while also being relatively small and
inexpensive. Bypass the 48V supply with a 0.1μF, 100V
capacitor located close to the LTC4263. The V
also requires a 0.1μF bypass capacitor.
supply
DD5
Fuse
regulation requirements on the PSE. Disturbances on V
SS
While the LTC4263 does not require a fuse for proper
operation or for compliance with IEEE 802.3af, some
safety requirements state that the output current must be
limited to less than 2A in less than 60 seconds if any one
component fails or is shorted. Since the LTC4263 is the
primary current limiter, its failure could result in excess
current to the port. To meet these safety requirements, a
fuse can be placed in the positive leg of the port. The fuse
mustbelargeenoughthatitwillpassatleast450mAwhen
derated for high temperature but small enough that it will
fuse at less than 2A at cold temperature. This requirement
can usually be satisfied with a 1A fuse or PTC. Placing the
fuse between the RJ-45 connector and the LTC4263 and
its associated circuitry provides additional protection for
this circuitry. Consult a safety requirements expert for the
application specific requirements.
can also adversely affect detection, classification and AC
disconnect sensing. For these reasons, proper bypassing
and stability of the V supply is important.
SS
Another problem that can affect the V supply is insuf-
SS
ficient power, leading to the supply voltage dropping out
of the specified range. The 802.3af specification states
that if a PSE powers a PD it must be able to provide the
maximum power level requested by the PD based on the
PD’s classification. The specification does allow a PSE
to choose not to power a port, typically because the PD
requires more power than the PSE has available to deliver.
If a PSE is built with a V supply not capable of deliver-
SS
ing full power to all ports, it is recommended to use the
LTC4263 power management feature to prevent ports
from being turned on when there is insufficient power.
Because the specification also requires the PSE to sup-
ply an inrush current of 400mA at up to a 5% duty cycle,
the V supply capability should be at least a few percent
SS
higher than the maximum total power the PSE needs to
supply to the PDs.
4263fd
19
LTC4263
APPLICATIONS INFORMATION
Isolation
several LTC4263 ports. Environment B, the stricter isola-
tion requirement, is for networks that cross an AC power
distribution boundary. In this case, electrical isolation
must be maintained between each port in the PSE. The
LTC4263 can be used to build a multi-port Environment B
PSE by powering each LTC4263 from a separate, isolated
48V supply. In all PSE applications, there should be no
user accessible connections to the LTC4263 other than
the RJ-45 port.
The IEEE 802.3af standard requires Ethernet ports to be
electricallyisolatedfromallotherconductorsthatareuser
accessible. This includes the metal chassis, other connec-
tors, and the AC power line. Environment A isolation is
the most common and applies to wiring within a single
building serviced by a single AC power system. For this
type of application, the PSE isolation requirement can be
met with the use of a single, isolated 48V supply powering
4263fd
20
LTC4263
TYPICAL APPLICATIONS
Three Port Midspan PSE with Power Management Set for 30W
MIDSPAN
IN
MIDSPAN
OUT
ISOLATED
48V
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
0.1μF
100V
LTC4263
14
12
2
11
1
V
V
DD5
DD48
LED
1k
SD
0.1μF
0.1μF
0.1μF
4
LEGACY PWRMGT
3
7
RJ45
RJ45
MIDSPAN
ENFCLS
OSC
ACOUT
OUT
13
5
8
0.1μF
100V
10
9
SMAJ58A
V
SS
6
OUT
V
SS
MIDSPAN
IN
MIDSPAN
OUT
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
0.1μF
100V
LTC4263
14
12
2
11
1
V
DD5
V
DD48
LED
1k
SD
4
LEGACY PWRMGT
3
7
RJ45
RJ45
MIDSPAN
ENFCLS
OSC
ACOUT
OUT
13
5
8
0.1μF
100V
10
9
SMAJ58A
V
SS
6
OUT
V
SS
MIDSPAN
IN
MIDSPAN
OUT
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
0.1μF
100V
LTC4263
14
12
2
11
1
V
V
DD5
DD48
LED
1k
SD
4
LEGACY PWRMGT
3
7
RJ45
RJ45
MIDSPAN
ENFCLS
OSC
ACOUT
OUT
13
5
8
0.1μF
100V
10
9
SMAJ58A
V
SS
6
OUT
V
SS
4263 TA02
R
7.15k
1%
PM
C
PM
1μF
4263fd
21
LTC4263
PACKAGE DESCRIPTION
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev B)
0.70 ±0.05
3.30 ±0.05
1.70 ± 0.05
3.60 ±0.05
2.20 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
3.00 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
0.40 ± 0.10
4.00 ±0.10
(2 SIDES)
8
14
R = 0.05
TYP
3.30 ±0.10
3.00 ±0.10
(2 SIDES)
1.70 ± 0.10
PIN 1 NOTCH
R = 0.20 OR
PIN 1
TOP MARK
(SEE NOTE 6)
0.35 × 45°
CHAMFER
(DE14) DFN 0806 REV B
7
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.50 BSC
3.00 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
4263fd
22
LTC4263
PACKAGE DESCRIPTION
S Package
14-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.337 – .344
.045 ±.005
(8.560 – 8.738)
.050 BSC
NOTE 3
13
12
11
10
8
14
N
9
N
.245
MIN
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
1
2
3
N/2
N/2
7
.030 ±.005
TYP
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0° – 8° TYP
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
.016 – .050
(0.406 – 1.270)
S14 0502
NOTE:
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
1. DIMENSIONS IN
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
4263fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC4263
TYPICAL APPLICATION
Complete Single-Port Endpoint PSE with Integrated RJ45
J1
+
+
1 TD
TX
TX
1
ISOLATED
48V
7 CT
8 TD
LED1
C3
LN1351C-TR
GRN
0.1μF
100V
–
+
–
+
2
3
D1
BAS19
PHY
1:1
2 RD
RX
L1
U1
V
10mH, 21mA
DS1608C-106
COILCRAFT
LTC4263
11
R2
1k
V
DD48
1
4
7
14
12
2
LED
–
–
DD5
9 RD
RX
PWRMGT
OSC
6
4
SD
C1
0.1μF
1:1
LEGACY
MIDSPAN
ENFCLS
F1
1A
C7, 0.47μF
100V, X7R
C5
5 VC1A
10 VC1B
6 VC2A
3
R6
1k
0.1μF
13
5
8
5
7
ACOUT
OUT
C4
0.1μF
100V
D2
10
9
11 VC2B
V
SS
SMAJ58A
22nF 22nF 22nF 22nF
75Ω 75Ω 75Ω 75Ω
D5 CMLSHO5-4
6
V
SS
8
OUT
2kV
1000pF
R5
510k
4263 TA03
JKO-0044
PULSE
RELATED PARTS
PART NUMBER
LTC1737
DESCRIPTION
COMMENTS
High Power Isolated Flyback Controller
Sense Output Voltage Directly from Primary-Side Winding
LTC3803
Current Mode Flyback DC/DC Controller in ThinSOTTM
200kHz Constant-Frequency, Adjustable Slope Compensation,
Optimized for High Input Voltage Applications
LTC4257
IEEE 802.3af PD Interface Controller
100V 400mA Internal Switch, Programmable Classification
100V 400mA Dual Current Limit
DC Disconnect Only
LTC4257-1
LTC4258
IEEE 802.3af PD Interface Controller
Quad IEEE 802.3af Power Over Ethernet Controller
Quad IEEE 802.3af Power Over Ethernet Controller
IEEE 802.3af PD Interface with Switcher
LTC4259A-1
LTC4267
With AC Disconnect
Integrated Current Mode Switching Regulator
ThinSOT is a trademark of Linear Technology Corporation.
4263fd
LT 0708 REV D • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2006
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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