LTC4264IDE#PBF [Linear]
LTC4264 - High Power PD Interface Controller with 750mA Current Limit; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C;
| 型号： | LTC4264IDE#PBF |
| 厂家： | 
Linear |
| 描述： | LTC4264 - High Power PD Interface Controller with 750mA Current Limit; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C 光电二极管 控制器 |
| 文件： | 总24页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4264
High Power PD Interface
Controller with 750mA
Current Limit
FEATURES
DESCRIPTION
The LTC®4264 is an integrated Powered Device (PD) in-
terface controller intended for IEEE 802.3af Power over
Ethernet(PoE)andhighpowerPoEapplicationsupto35W.
By including a precision dual current limit, the LTC4264
keeps inrush below the IEEE802.3af current limit levels
to ensure interoperability success while allowing for high
power PD operation. The LTC4264 includes a field-proven
powerMOSFETdeliveringupto750mAtothePDloadwhile
maintaining compliance with the IEEE802.3af standard.
ComplementarypowergoodoutputsallowtheLTC4264to
interfacedirectlywithahostofDC/DCconverterproducts.
The LTC4264 provides a complete signature and power
interface solution for PD designs by incorporating the 25k
signature resistor, classification circuitry, input current
limit, undervoltage lockout, thermal overload protection,
signature disable and power good signaling.
■
Complete High Power PD Interface Controller
IEEE 802.3af® Compliant
■
■
Onboard 750mA Power MOSFET
■
Complementary Power Good Outputs
■
Flexible Auxiliary Power Options
■
Precision Dual Current Limit with Disable
■
Programmable Classification Current to 75mA
■
Onboard 25k Signature Resistor with Disable
■
Undervoltage Lockout
■
Complete Thermal Overload Protection
■
Available in Low Profile (4mm × 3mm) DFN Package
APPLICATIONS
■
802.11n Access Points
■
High Power VoIP Video Phones
■
RFID Reader Systems
PTZ Security Cameras and Surveillance Equipment
■
TheLTC4264PDinterfacecontrollercanbeusedalongwith
a variety of Linear Technology DC/DC converter products
to provide a complete, cost effective power solution for
high power PD applications.
The LTC4264 is available in the space-saving low profile
(4mm × 3mm) DFN package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Turn On vs Time
C
= 100µF
V
LOAD
IN
50V/DIV
~
+
LTC4264
SHDN
–54V FROM
DATA PAIR
V
0.1µF
IN
DF1501S
+
GND
V
OUT
5µF
MIN
SWITCHING
POWER
SUPPLY
SMAJ58A
~
–
50V/DIV
PWRGD
PWRGD
R
CLASS
+
R
RUN
CLASS
PWRGD – V
~
+
OUT
3.3V
RTN
–54V FROM
SPARE PAIR
50V/DIV
I
DF1501S
TO LOGIC
LIM_EN
V
V
~
–
–
IN
OUT
4264 TA01a
I
IN
200mA/DIV
TIME (5ms/DIV)
4264 TA01b
4264f
1
LTC4264
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Notes 1, 2)
TOP VIEW
V Voltage................................................. 0.3V to –90V
IN
OUT
V
Voltage......... V + 90V (and ≤ GND) to V – 0.3V
SHDN
NC
1
2
3
4
5
6
12 GND
11 NC
IN IN
SHDN Voltage ............................ V + 90V to V – 0.3V
IN
IN
IN
R
10 PWRGD
R
, I
Voltage ............... V + 7V to V – 0.3V
CLASS
CLASS LIM_EN
IN
13
I
9
8
7
PWRGD
PWRGD Voltage (Note 3)
LIM_EN
V
V
Low Impedance Source ....V
+ 11V to V
– 0.3V
OUT
IN
OUT
OUT
V
V
OUT
IN
Current Fed..........................................................5mA
PWRGD Voltage......................... V + 80V to V – 0.3V
IN
IN
DE12 PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
PWRGD Current.....................................................10mA
T
= 150°C, θ = 43°C/W, θ = 4.3°C/W
JA JC
JMAX
R
CLASS
Current.....................................................100mA
EXPOSED PAD (PIN 13) MUST BE SOLDERED TO
AN ELECTRICALLY ISOLATED HEAT SINK
Operating Ambient Temperature Range
LTC4264C ................................................ 0°C to 70°C
LTC4264I ............................................. –40°C to 85°C
Junction Temperature ........................................... 150°C
Storage Temperature Range................... –65°C to 150°C
ORDER PART NUMBER
DE PART MARKING*
LTC4264CDE
LTC4264IDE
4264
4264
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Supply Voltage
Voltage with Respect to GND Pin
(Notes 5, 6, 7, 8)
IN
●
●
●
●
●
IEEE 802.3af System
Signature Range
–57
–10.1
–21
–40.2
–31.5
V
V
V
V
V
–1.5
–12.5
–37.7
–29.8
Classification Range
UVLO Turn-On Voltage
UVLO Turn-Off Voltage
–38.9
–30.6
●
●
●
I
I
IC Supply Current when On
V
V
= –54V
3
mA
mA
%
IN_ON
IN
IC Supply Current During Classification
= –17.5V (Note 9)
0.55
0.62
0.70
3.5
IN_CLASS
IN
ΔI
Current Accuracy During Classification 10mA < I
< 75mA, –12.5V ≤ V ≤ –21V
CLASS
CLASS IN
(Notes 10,11)
Stepped 0V to –17.5V, I ≤3.5% of
IN_CLASS
●
●
●
●
t
Classification Stability Time
Signature Resistance
V
1
ms
kΩ
kΩ
V
CLASSRDY
IN
Ideal, 10mA < I
< 75mA (Notes 10, 11)
CLASS
R
R
–1.5V ≤ V ≤ –10.1V, IEEE 802.3af 2-Point
23.25
3
26.00
11.8
57
SIGNATURE
INVALID
IN
Measurement, SHDN Tied to V (Notes 6, 7)
IN
Invalid Signature Resistance
SHDN High Level Input Voltage
–1.5V ≤ V ≤ –10.1V, IEEE 802.3af 2-Point
10
IN
Measurement, SHDN Tied to GND (Notes 6, 7)
V
With Respect to V , High Level = Shutdown
IH_SHDN
IN
(Note 12)
●
●
●
V
SHDN Low Level Input Voltage
SHDN Input Resistance
With Respect to V
With Respect to V
0.45
V
kΩ
V
IL_SHDN
IN
R
100
4
INPUT_SHDN
IN
V
I
High Level Input Voltage
With Repect to V , High Level Enables Current
IH_ILIM
LIM_EN
IN
Limit (Note 13)
4264f
2
LTC4264
ELECTRICAL CHARACTERISTICS The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
Low Level Input Voltage
CONDITIONS
With Respect to V (Note 13)
MIN
TYP
MAX
1
UNITS
●
●
V
V
I
V
V
IL_ILIM
LIM_EN
IN
Active Low Power Good
Output Low Voltage
I
= 1mA, V = –54V, PWRGD
0.5
PWRGD_OUT
PWRGD
IN
Referenced to V
IN
●
●
I
Active Low Power Good Leakage
V
= 0V, V
= 57V
1
µA
V
PWRGD_LEAK
IN
PWRGD
V
Active High Power Good
Output Low Voltage
I
= 0.5mA, V = –52V, V = –4V,
OUT
0.35
PWRGD_OUT
PWRGD_VCLAMP
PWRGD_LEAK
PWRGD
IN
PWRGD Referenced to V
(Note 14)
OUT
●
●
V
Active High Power Good
Voltage-Limiting Clamp
I
= 2mA, V
= 0V,
OUT
12.0
700
14.0
16.5
1
V
PWRGD
OUT
With Respect to V
(Note 3)
I
Active High Power Good Leakage
V
V
= 11V, with Respect to V
,
µA
PWRGD
OUT
OUT
= V = –54V
IN
R
On Resistance
I = 700mA, V = –54V
Measured from V to V
0.5
0.6
0.8
Ω
Ω
ON
IN
●
●
●
(Note 11)
OUT
IN
I
I
V
Leakage
V
IN
= –57V, GND = SHDN = V = 0V
OUT
1
µA
OUT_LEAK
OUT
Input Current Limit During Normal
Operation
V
IN
= –54V, V
= –53V, I Floating
LIM_EN
750
800
mA
LIMIT_HIGH
OUT
(Notes 15, 16)
●
I
I
Inrush Current Limit
V
= –54V, V
= –53V (Notes 15, 16)
250
300
350
mA
A
LIMIT_LOW
IN
OUT
Safeguard Current Limit when
V
IN
= –54V, V
= –52.5V, I
Tied to V
1.20
1.45
1.65
LIMIT_DISA
OUT
LIM_EN
IN
I
Disabled
(Notes 15, 16, 17)
LIMIT_HIGH
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
causepermanentdamagetothedevice. ExposuretoanyAbsoluteMaximum
Ratingconditionforextendedperiodsmayaffectdevicereliabilityand
lifetime.
t
isthetimeforI
to settle to within 3.5% of ideal. The current
CLASS
CLASSRDY
accuracy specification does not include variations in R
total classification current for a PD also includes the IC quiescent current
(I ). SeeApplicationsInformation.
resistance. The
CLASS
IN_CLASS
Note2: All voltages are with respect to GND pin unless otherwise noted.
Note3: Active high PWRGD pin internal clamp circuit self-regulates to 14V
Note 11:Thisparameterisassuredbydesignandwaferleveltesting.
Note 12:To disable the 25k signature, tie SHDN to GND ( 0.1V) or hold SHDN
with respect to V
.
pin high with respect to V . SeeApplicationsInformation.
OUT
IN
Note 4:TheLTC4264operateswithanegativesupplyvoltageintherangeof
–1.5Vto–57V. Toavoidconfusion, voltagesinthisdatasheetarereferredto
intermsofabsolutemagnitude.
Note13:I
pinispulledhighinternallyandfornormaloperationshould
LIM_EN
be left floating. To disable high level current limit, tie I
ApplicationsInformation.
to V . See
IN
LIM_EN
Note5: In IEEE 802.3af systems, the maximum voltage at the PD jack is
defined to be –57V. See Applications Information.
Note 14:ActivehighpowergoodisreferencedtoV
andisvalidfor
OUT
GND-V
≥ 4V. Measured at –52V due to test hardware limitations.
OUT
Note 6:TheLTC4264isdesignedtoworkwithtwopolarityprotection
diodes in series with the input. Parameter ranges specified in the Electrical
CharacteristicsarewithrespecttoLTC4264pinsandaredesignedtomeet
IEEE 802.3af specifications when the drop from the two diodes is included.
SeeApplicationsInformation.
Note7: Signatureresistanceismeasuredviathetwo-pointΔV/ΔImethod
as defined by IEEE 802.3af. The LTC4264 signature resistance is offset
from25ktoaccountfordioderesistance. Withtwoseriesdiodes, thetotal
PDresistancewillbebetween23.75kand26.25kandmeetIEEE802.3af
specifications. The minimum probe voltages measured at the LTC4264 pins
are – 1.5V and – 2.5V. The maximum probe voltages are –9.1V and –10.1V.
Note 15:TheLTC4264includesadualcurrentlimit. Atturn-on, beforeC1is
charged, theLTC4264currentlevelissettoI . AfterC1ischarged
LIMIT_LOW
andwithI
pintiedlow, theLTC4264switchestoI
floating, the LTC4264 switches to I
. WithI
LIM_EN
LIMIT_HIGH LIM_EN
. TheLTC4264staysin
LIMIT_DISA
I
or I
until the input voltage drops below the UVLO turn-
LIMIT_HIGH
LIMIT_DISA
offthresholdorathermaloverloadoccurs.
Note 16:TheLTC4264featuresthermaloverloadprotection. Intheeventof
an overtemperature condition, the LTC4264 will turn off the power MOSFET,
disable the classification load current and present an invalid power good
signal. OncetheLTC4264coolsbelowtheovertemperaturelimit, the
LTC4264currentlimitswitchestoI
andnormaloperationresumes.
LIMIT_LOW
Thermal overload protection is intended to protect the device during
momentary fault conditions and continuous operation in thermal overload
shouldbeavoidedasitmayimpairdevicereliability.
Note8: The LTC4264 includes hysteresis in the UVLO voltages to preclude
anystart-uposcillation. PerIEEE802.3afrequirements, theLTC4264will
powerupfromavoltagesourcewith20Ω series resistance on the first trial.
Note 17:I
normalinputcurrentlimit(I
CurrentsatornearI
requireareducedmaximumambientoperatingtemperatureinordertoavoid
trippingthethermaloverloadprotection. SeeApplicationsInformation.
isasafeguardcurrentlimitthatisactivatedwhenthe
LIMIT_DISA
Note 9:I
does not include classification current programmed at
IN_CLASS
)isdefeatedusingtheI
pin.
LIMIT_HIGH
LIM_EN
Pin 3. Total supply current in classification mode will be I
(see Note 10).
Note 10:I
+ I
IN_CLASS CLASS
will cause significant package heating and may
LIMIT_DISA
is the measured current flowingthroughR
. ΔI
=1.237/R
CLASS
CLASS CLASS
accuracyiswithrespecttotheidealcurrentdefinedasI
.
CLASS
CLASS
4264f
3
LTC4264
TYPICAL PERFORMANCE CHARACTERISTICS
Input Current vs Input Voltage
25k Detection Range
Input Current vs Input Voltage
Input Current vs Input Voltage
100
80
0.5
0.4
0.3
0.2
12.0
11.5
T
= 25°C
CLASS 1 OPERATION
T
= 25°C
A
A
CLASS 5*
11.0
60
85°C
10.5
10.0
CLASS 4
CLASS 3
–40°C
40
CLASS 2
CLASS 1
20
0
0.1
0
9.5
9.0
CLASS 0
0
–20
–30
–40
–50
–60
–10
0
–4
–6
–8
–10
–12
–14
–20
–22
–2
–16
–18
INPUT VOLTAGE (V)
*OPTIONAL CLASS CURRENT
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
4264 G01
4264 G03
4264 G02
Signature Resistance
vs Input Voltage
Class Operation vs Time
On Resistance vs Temperature
1.0
0.8
0.6
0.4
28
27
T
= 25°C
∆V V2 – V1
A
RESISTANCE =
DIODES: HD01
=
INPUT
VOLTAGE
10V/DIV
∆I
I – I
2 1
T
= 25°C
A
IEEE UPPER LIMIT
26
25
24
LTC4264 + 2 DIODES
CLASS
CURRENT
20mA/DIV
LTC4264 ONLY
IEEE LOWER LIMIT
0.2
0
23
22
4264 G05
TIME (10µs/DIV)
–50
0
25
50
75
100
–25
V1: –1
V2: –2
–3
–4
–5
–6
–7
–8
–9
–10
JUNCTION TEMPERATURE (°C)
INPUT VOLTAGE (V)
4264 G06
4264 G04
Active Low PWRGD
Output Low Voltage vs Current
Active High PWRGD
Output Low Voltage vs Current
Current Limit vs Input Voltage
1.0
0.8
0.6
0.4
0.2
0
800
600
400
200
4
3
2
1
0
–40°C
85°C
T
= 25°C
T
= 25°C
A
A
GND – V
= 4V
OUT
HIGH CURRENT MODE
LOW CURRENT MODE
–40°C
85°C
0
0.5
1
1.5
2
–40
–45
–50
–55
–60
0
2
4
6
8
10
INPUT VOLTAGE (V)
I
(mA)
IN
CURRENT (mA)
4264 G08
4264 G09
4264 G07
4264f
4
LTC4264
PIN FUNCTIONS
SHDN (Pin 1): Shutdown Input. Used to command the
LTC4264 to present an invalid signature. Connecting
SHDNtoGNDlowersthesignatureresistancetoaninvalid
value and disables other LTC4264 operations. If unused,
PWRGD (Pin 9): Active High Power Good Output, Open
Collector.SignalstotheDC/DCconverterthattheLTC4264
MOSFET is on and that the converter can start operation.
High impedance indicates power is good. PWRGD is ref-
tie SHDN to V .
erenced to V
and is low impedance during inrush and
IN
OUT
in the event of a thermal overload. PWRGD is clamped
14V above V
NC (Pin 2): No Internal Connection.
.
OUT
R
(Pin 3): Class Select Input. Used to set the current
CLASS
PWRGD (Pin 10): Active Low Power Good Output, Open-
Drain. Signals to the DC/DC converter that the LTC4264
MOSFET is on and that the converter can start operation.
Low impedance indicates power is good. PWRGD is
the LTC4264 maintains during classification. Connect a
resistor between R and V . (See Table 2.)
CLASS
IN
I
(Pin4):InputCurrentLimitEnable.Usedtocontrol
LIM_EN
LTC4264currentlimitbehaviorduringpoweredoperation.
referenced to V and is high impedance during detec-
IN
For normal operation, float I to enable I
current. Tie I
tion, classification and in the event of a thermal overload.
LIM_EN
LIMIT_HIGH
to V to disable input current limit.
PWRGD has no internal clamps.
LIM_EN
IN
Note that the inrush current limit does not change with
selection. See Applications Information.
NC (Pin11): No Internal Connection.
I
LIM_EN
GND (Pin 12): Ground. Tie to system ground and power
return through the input diode bridge.
V (Pins 5, 6): Power Input. Tie to the PD input through
IN
the diode bridge. Pins 5 and 6 must be electrically tied
together.
Exposed Pad (Pin 13): Must be soldered to electrically
isolated heat sink.
V
(Pins 7, 8): Power Output. Supplies power to the
OUT
PD load through the internal power MOSFET. V
is high
OUT
impedance until the input voltage rises above the UVLO
turn-on threshold. The output is then connected to V
IN
through a current-limited internal MOSFET switch. Pins 7
and 8 must be electrically tied together.
4264f
5
LTC4264
BLOCK DIAGRAM
CLASSIFICATION
CURRENT LOAD
SHDN
NC
1
2
3
12 GND
11 NC
+
1.237V
16k 25k
–
R
CLASS
10 PWRGD
CONTROL
CIRCUITS
I
4
LIM_EN
INPUT
CURRENT
LIMIT
1400mA
750mA
300mA
9
PWRGD
+
14V
–
V
V
5
6
8
7
V
V
IN
OUT
BOLD LINE INDICATES
HIGH CURRENT PATH
OUT
IN
4264 BD
4264f
6
LTC4264
APPLICATIONS INFORMATION
OVERVIEW
using four conductors (2-pair) or all eight conductors
(4-pair). Each method provides advantages and the
system vendor needs to decide which method best suits
their application.
Power over Ethernet (PoE) continues to gain popularity as
more products are taking advantage of having DC power
and high speed data available from a single RJ45 connec-
tor. As PoE is becoming established in the marketplace,
Powered Device (PD) equipment vendors are running into
the 12.95W power limit established by the IEEE 802.3af
standard.Tosolvethisproblemandexpandtheapplication
of PoE, the LTC4264 breaks the power barrier by allowing
custom PoE applications to deliver up to 35W for power-
hungry PoE applications such as dual band and 802.11n
access points, RFID readers and PTZ security cameras.
2-pair power is used today in 802.3af systems (see
Figure 1). One pair of conductors is used to deliver the
current and a second pair is used for the return while two
conductor pairs are not powered. This architecture offers
the simplest implementation method but suffers from
higher cable loss than an equivalent 4-pair system.
4-pair power delivers current to the PD via two conductor
pairsinparallel(Figure2).Thislowersthecableresistance
but raises the issue of current balance between each con-
ductor pair. Differences in resistance of the transformer,
cableandconnectorsalongwithdifferencesindiodebridge
forward voltage in the PD can cause an imbalance in the
currents flowing through each pair. The 4-pair system in
Figure 2 solves this problem by using two independent
DC/DCconvertersinthePD. Usingthisarchitecturesolves
the balancing issue and allows the PD to be driven by two
independent PSEs, for example an Endpoint PSE and a
Midspan PSE. Contact Linear Technology applications
support for detailed information on implementing 2-pair
and 4-pair PoE systems.
The LTC4264 is designed to interface with custom Power
Sourcing Equipment (PSE) to deliver higher power levels
tothePDload. Off-the-shelfhighpowerPSEsareavailable
today from a variety of vendors for use with the LTC4264
to allow quick implementation of a custom system. Alter-
nately, the system vendor can choose to build their own
high power PSE. Linear Technology provides complete
application information for high power PSE solutions
delivering up to 35W for 2-pair systems and as much as
70W when used in 4-pair systems.
One of the basic architectural decisions associated with
a high power PoE system is whether to deliver power
PSE
PD
RJ45
4
RJ45
CAT 5
4
5
5
SPARE PAIR
GND
DF1501S
0.1µF
100V
0.1µF
1
1
DGND BYP
AGND
DETECT
5µF
MIN
SMAJ58A
58V
Tx
Rx
Tx
3.3V
V
DD
2
3
2
3
DATA PAIR
DATA PAIR
1k
CMPD3003
1/4
LTC4259A-1
0.47µF
100V
0.1µF
Rx
V
SENSE GATE OUT
EE
GND
6
6
DC/DC
CONVERTER
R
PWRGD
+
OUT
CLASS
SMAJ58A
58V
10k
V
0.25Ω
LTC4264
–54V
7
8
7
IRLR3410
V
V
–
IN
OUT
S1B
8
DF1501S
SPARE PAIR
4264 F01
Figure 1. 2-Pair High Power PoE System Diagram
4264f
7
LTC4264
APPLICATIONS INFORMATION
PSE
RJ45
PD
GND
RJ45
1
0.1µF
AGND
DETECT
0.1µF
CAT5
1
DGND BYP
5µF
SMAJ58A
R
Tx1
Rx1
Tx1
0.1µF
DF1501S
3.3V
V
MIN
DD
2
3
2
3
AUTO
CMPD3003
1k
0.47µF
GND
PWRGD
1/4
LTC4259A
DC/DC
CONVERTER
CLASS
LTC4264
Rx1
V
SENSE GATE OUT
10k
V
V
OUT
EE
IN
6
4
6
+
–
–
SMAJ58A
S1B
+
0.25Ω
V
–54V
GND
OUT
IRLR3410
–
+
5µF
0.1µF
SMAJ58A
R
MIN
0.1µF
GND
PWRGD
4
DC/DC
CONVERTER
AGND
CLASS
Tx2
Rx2
Tx2
DETECT
LTC4264
5
7
5
7
CMPD3003
1k
0.47µF
1/4
LTC4259A
V
V
OUT
IN
DF1501S
Rx2
V
SENSE GATE OUT
10k
EE
8
8
SMAJ58A
S1B
0.25Ω
4264 F02
–54V
IRLR3410
Figure 2. 4-Pair High Power PoE Gigabit Ethernet System Diagram
The LTC4264 is specifically designed to implement the
front end of a high power PD for power-hungry PoE ap-
plications that must operate beyond the power limits of
IEEE 802.3af. LTC4264 uses a precision, dual current limit
that keeps inrush below IEEE 803.2af levels to ensure
interoperability with any PSE. After inrush is complete,
OPERATION
The LTC4264 high power PD interface controller has sev-
eral modes of operation depending on the applied input
voltage as shown in Figure 3 and summarized in Table 1.
These various modes satisfy the requirements defined
in the IEEE 802.3af specification. The input voltage is
applied to the V pin with reference to the GND pin and
is always negative.
theLTC4264inputcurrentlimitswitchestotheI
LIMIT_HIGH
IN
level, using an onboard, 750mA power MOSFET. This al-
lows a PD (supplied by a custom PSE) to deliver power
above the IEEE 802.3af 12.95W maximum, sending up
to 35W to the PD load. The LTC4264 uses established
IEEE 802.3af detection and classification methods to
maintain compliance and includes an extended program-
mable Class 5 range for use in custom PoE applications.
The LTC4264 features both active-high and active-low
powergoodsignalingforsimplifiedinterfacetoanyDC/DC
converter. The SHDN pin on the LTC4264 can be used to
provide a seamless interface for external wall adapter or
Table 1. LTC4264 Operational Mode as a Function
of Input Voltage
INPUT VOLTAGE
0V to –1.4V
LTC4264 MODE OF OPERATION
Inactive
–1.5V to –10.1V
–10.3V to –12.4V
25k Signature Resistor Detection
Classification Load Current Ramps Up from 0% to
100%
–12.5V to UVLO*
UVLO* to –57V
Classification Load Current Active
Power Applied to PD Load
*UVLO includes hysteresis.
Rising input threshold ≅ –38.9V
Falling input threshold ≅ –30.6V
otherauxiliarypoweroptions.TheI
pinprovidesthe
LIMIT_HIGH
LIM_EN
option to remove the high current limit, I
. The
LTC4264includesanonboardsignatureresistor,precision
UVLO, thermal overload protection and is available in a
thermally-enhanced 12-lead 4mm × 3mm DFN package
for superior high current performance.
4264f
8
LTC4264
APPLICATIONS INFORMATION
DETECTION V1
TIME
SERIES DIODES
DETECTION V2
–10
–20
–30
–40
–50
CLASSIFICATION
The IEEE 802.3af-defined operating modes for a PD refer-
ence the input voltage at the RJ45 connector on the PD.
The PD must be able to handle power received in either
polarity. For this reason, it is common to install diode
bridges BR1 and BR2 between the RJ45 connector and
the LTC4264 (Figure 4). The diode bridges introduce an
offset that affects the threshold points for each range of
operation. The LTC4264 meets the IEEE 802.3af-defined
operating modes by compensating for the diode drops
in the threshold points. For the signature, classification,
and the UVLO thresholds, the LTC4264 extends two diode
drops below the IEEE 802.3af specifications. Note that
the voltage ranges specified in the LTC4264 Electrical
Specifications are referenced with respect to the IC pins.
The LTC4264 threshold points support the use of either
traditional or Schottky diode bridges.
UVLO
TURN-OFF
UVLO
TURN-ON
TIME
C1
τ = R
LOAD
–10
–20
–30
–40
–50
UVLO
OFF
UVLO
ON
UVLO
OFF
I
LIMIT_LOW
C1
dV
dt
=
TIME
–10
–20
–30
–40
–50
POWER
BAD
POWER
GOOD
POWER
BAD
PWRGD TRACKS
V
IN
DETECTION
During detection, the PSE will apply a voltage in the range
of –2.8V to –10V on the cable and look for a 25k signature
resistor. This identifies the device at the end of the cable
as a PD. With the PSE voltage in the detection range, the
LTC4264presentsaninternal25kresistorbetweentheGND
20
10
POWER
BAD
POWER
GOOD
POWER
BAD
TIME
and V pins. This precision, temperature-compensated
IN
I
LOAD, I
LOAD
(UP TO I
LIMIT_HIGH
resistorprovidesthepropercharacteristicstoalertthePSE
that a PD is present and requests power to be applied.
)
LIMIT_HIGH
I
LIMIT_LOW
I
The IEEE 802.3af specification requires the PSE to use
a ΔV/ΔI measurement technique to keep the DC offset
voltage of the diode bridge from affecting the signature
resistance measurement. However, the diode resistance
appears in series with the signature resistor and must
be included in the overall signature resistance of the PD.
The LTC4264 compensates for the two series diodes in
the signature path by offsetting the internal resistance so
that a PD built with the LTC4264 meets the IEEE 802.3af
specification.
CLASS
CLASSIFICATION
TIME
DETECTION I
2
DETECTION I
1
V1 – 2 DIODE DROPS
V2 – 2 DIODE DROPS
I
=
I
=
1
2
25kΩ
25kΩ
I
I
DEPENDENT ON R
SELECTION
CLASS
CLASS
= 300mA, I
= 750mA
LIMIT_LOW
LIMIT_HIGH
V
IN
I
=
LOAD
R
LOAD
GND
OUT
LTC4264
GND
R
I
LOAD
C1
IN
R
CLASS
In some designs that include an auxiliary power option,
such as an external wall adapter, it is necessary to control
whether or not the PD is detected by a PSE. With the
LTC4264, the 25k signature resistor can be enabled or
disabled with the SHDN pin (Figure 5). Taking the SHDN
PSE
V
R
PWRGD
PWRGD
CLASS
V
V
OUT
IN
4264 F03
Figure 3. Output Voltage, PWRGD, PWRGD and
PD Current as a Function of Input Voltage
4264f
9
LTC4264
APPLICATIONS INFORMATION
RJ45
+
T1
TX
1
BR1
–
TX
2
3
+
TO PHY
RX
–
RX
POWERED
DEVICE (PD)
INTERFACE
6
GND
+
–
AS DEFINED
SPARE
BR2
4
5
BY IEEE 802.3af
LTC4264
0.1µF
100V
D3
V
IN
4264 F04
7
8
SPARE
Figure 4. PD Front End Using Diode Bridges on Main and Spare Inputs
LTC4264
GND
25k SIGNATURE
RESISTOR
TO
PSE
16k
SHDN
V
IN
4264 F05
SIGNATURE DISABLE
Figure 5. 25k Signature Resistor with Disable
pin high will reduce the signature resistor to 10k which is
an invalid signature per the IEEE 802.3af specifications.
This will prevent a PSE from detecting and powering the
PD. This invalid signature is present in the PSE probing
range of –2.8V to –10V. When the input rises above –10V,
the signature resistor reverts to 25k to minimize power
dissipation in the LTC4264. To disable the signature, tie
SHDN to GND. Alternately, the SHDN pin can be driven
to identify lower-power PDs and assign the appropriate
power level to these devices. For each class, there is an
associated load current that the PD asserts onto the line
during classification probing. The PSE measures the PD
load current in order to assign the proper PD classifica-
tion. Class 0 is included in the IEEE 802.3af specification
to cover PDs that do not support classification. Class 1-3
partition PDs into three distinct power ranges as shown in
Table 2. Class 4 is reserved by the IEEE 802.3af committee
for future use. The new Class 5 defined here is available
for system vendors to implement a unique classification
for use in closed systems and is not defined or supported
by the IEEE 802.3af. With the extended classification
range available in the LTC4264, it is possible for system
designers to define multiple classes using load currents
between 40mA and 75mA.
high with respect to V . When SHDN is high, all functions
IN
are disabled. For normal operation tie SHDN to V .
IN
CLASSIFICATION
Once the PSE has detected a PD, the PSE may option-
ally classify the PD. Classification provides a method for
more efficient allocation of power by allowing the PSE
4264f
10
LTC4264
APPLICATIONS INFORMATION
During classification, the PSE presents a fixed voltage
between –15.5V and –20.5V to the PD (Figure 6). With
the input voltage in this range, the LTC4264 asserts a load
from power cycling or getting “stuck” during signature
or classification probing. In the event a PSE overshoots
beyond the classification voltage range, the available load
currentaidsinreturningthePDbackintotheclassification
voltage range. (The PD input may otherwise be “trapped”
by a reverse-biased diode bridge and the voltage held by
the 0.1µF capacitor.) By gently ramping the classification
current on and maintaining a positive I-V slope until UVLO
turn-on, the LTC4264 provides a well behaved load, as-
suring interoperability with any PSE.
current from the GND pin through the R
resistor. The
CLASS
magnitude of the load current is set with the selection of
the R
resistor. The resistor value associated with
CLASS
each class is shown in Table 2.
Table 2. Summary of IEEE 802.3af Power Classifications and
LTC4264 R
Resistor Selection
MAXIMUM
CLASS
NOMINAL
LTC4264
RCLASS
POWER LEVELS CLASSIFICATION
AT INPUT OF PD LOAD CURRENT RESISTOR
CLASS
USAGE
Default
(W)
(mA)
(Ω, 1%)
Open
124
CURRENT PATH
0
1
2
3
4
5
0.44 to 12.95
0.44 to 3.84
3.84 to 6.49
6.49 to 12.95
<5
PSE
LTC4264
PROBING
Optional
Optional
Optional
10.5
18.5
28
VOLTAGE
SOURCE
R
CLASS
69.8
GND
–15.5V TO –20.5V
45.3
CONSTANT
LOAD
R
CLASS
Reserved by IEEE. See Apps
Undefined IEEE. See Apps
40
30.9
CURRENT
INTERNAL
TO LTC4264
V
IN
56
22.1
4264 F06a
V
PSE CURRENT MONITOR
AsubstantialamountofpowerisdissipatedintheLTC4264
duringclassification. TheIEEE802.3afspecificationlimits
the classification time to 75ms in order avoid excessive
heating. The LTC4264 is designed to handle the power
dissipation during the probe period. If the PSE probing
exceeds 75ms, the LTC4264 may overheat. In this situa-
tion, the thermal protection circuit will engage and disable
the classification current source, protecting the LTC4264
from damage. When the die cools, classification is auto-
matically resumed.
PSE
PD
Figure 6a. PSE Probing PD During Classification
Classification presents a challenging stability problem
for the PSE due to the wide range of loads possible. The
LTC4264 has been designed to avoid PSE interoperability
problems by maintaining a positive I-V slope throughout
the signature and classification ranges up to UVLO turn-
on as shown in Figure 6b. The positive I-V slope avoids
areas of negative resistance and helps prevent the PSE
–20
–30
0
–40
–10
INPUT VOLTAGE (V)
4264 F06b
Figure 6b. LTC4264 Positive I-V Slope
4264f
11
LTC4264
APPLICATIONS INFORMATION
UNDERVOLTAGE LOCKOUT
INPUT CURRENT LIMIT
The IEEE 802.3af specification dictates a maximum turn-
on voltage of 42V and a minimum turn-off voltage of 30V
for the PD. In addition, the PD must maintain large on-off
hysteresis to prevent current-resistance (I-R) drops in the
wiring between the PSE and the PD from causing start-up
oscillation. The LTC4264 incorporates an undervoltage
IEEE802.3afspecifiesamaximuminrushcurrentandalso
specifies a minimum load capacitor between the GND and
OUT
theLTC4264integratesadualcurrentlimitcircuitusingan
onboard power MOSFET and sense resistor to provide a
complete inrush control circuit without additional external
components.
V
pins. Tocontrolturn-onsurgecurrentsinthesystem
lockout (UVLO) circuit that monitors line voltage at V to
IN
determine when to apply power to the PD load (Figure 7).
At turn-on, the LTC4264 will limit the inrush current to
Before power is applied to the load, the V
pin is high
OUT
I
,allowingtheloadcapacitortorampuptotheline
impedance and there is no charge on capacitor C1. When
the input voltage rises above the UVLO turn-on thresh-
old, the LTC4264 removes the classification load current
and turns on the internal power MOSFET. C1 charges up
LIMIT_LOW
voltage in a controlled manner without interference from
thePSEcurrentlimit.BykeepingthePDcurrentlimitbelow
the PSE current limit, PD power up characteristics are well
controlled and independent of PSE behavior. This ensures
interoperability regardless of PSE output characteristics.
under LTC4264 inrush current limit control and the V
OUT
pin transitions from 0V to V as shown in Figure 3. The
IN
LTC4264 includes a hysteretic UVLO circuit on V that
IN
AfterloadcapacitorC1ischargedup,theLTC4264switches
keeps power applied to the load until the magnitude of the
to the high input current limit, I
. This allows the
LIMIT_HIGH
inputvoltagefallsbelowtheUVLOturn-offthreshold.Once
LTC4264todeliverupto35WtothePDloadforhighpower
applications. To maintain compatibility with IEEE 802.3af
power levels, it is necessary for the PD designer to ensure
the PD steady-state power consumption remains below
the limits shown in Table 2. The LTC4264 maintains the
high input current limit until the port voltage drops below
the UVLO turn-off threshold.
V falls below UVLO turn-off, the internal power MOSFET
IN
disconnects V
from V and the classification current
OUT
IN
is re-enabled. C1 will discharge through the PD circuitry
and the V
pin will go to a high impedance state.
OUT
+
C1
LTC4264
PD
LOAD
GND
5µF
MIN
TO
PSE
UNDERVOLTAGE
LOCKOUT
CIRCUIT
V
IN
V
OUT
4264 F07
CURRENT-LIMITED
TURN ON
INPUT
LTC4264
VOLTAGE
0V TO UVLO*
>UVLO*
POWER MOSFET
OFF
ON
*UVLO INCLUDES HYSTERESIS
RISING INPUT THRESHOLD ≅ –38.9V
FALLING INPUT THRESHOLD ≅ –30.6V
Figure 7. LTC4264 Undervoltage Lockout
4264f
12
LTC4264
APPLICATIONS INFORMATION
During the inrush event as C1 is being charged, a large
amountofpowerisdissipatedintheMOSFET.TheLTC4264
is designed to accept this load and is thermally protected
to avoid damage to the onboard power MOSFET. If a
thermal overload does occur, the power MOSFET turns
off, allowing the die to cool. Once the die has returned to
a safe temperature, the LTC4264 automatically switches
Table 3. Current Limit as a Function of I
INRUSH CURRENT
LIM_EN
OPERATING INPUT
CURRENT LIMIT
STATE OF I
LIMT
LIM_EN
Floating
I
I
I
LIMIT_LOW
LIMIT_LOW
LIMT_HIGH
Tied to V
I
IN
LIMIT_DISA
POWER GOOD
to I
, and load capacitor C1 charging resumes.
LIMIT_LOW
TheLTC4264includescomplementarypowergoodoutputs
(Figure 8) to simplify connection to any DC/DC converter.
PowerGoodisassertedattheendoftheinrusheventwhen
loadcapacitorC1isfullychargedandtheDC/DCconverter
can safely begin operation. The power good signal stays
activeduringnormaloperationandisde-assertedatpower
off when the port drops below the UVLO threshold or in
the case of a thermal overload event.
TheLTC4264hastheoptionofdisablingthenormaloperat-
ing input current limit, I , for custom high power
LIMIT_HIGH
PoE applications. To disable the current limit, connect
to V . To protect the LTC4264 from damage when
I
LIM_EN
IN
the normal current limit is disabled, a safeguard current
limit, I keeps the current below destructive
LIMIT_DISA
levels, typically 1.4A. Note that continuous operation at
or near the safeguard current limit will rapidly overheat
the LTC4264, engaging the thermal protection circuit. For
For PD designs that use a large load capacitor and also
consume a lot of power, it is important to delay activa-
tion of the DC/DC converter with the power good signal.
If the converter is not disabled during the current-limited
turn-on sequence, the DC/DC converter will rob current
intended for charging up the load capacitor and create a
slow rising input, possibly causing the LTC4264 to go into
thermal shutdown.
normal operations, float the I
pin. The LTC4264
LIM_EN
maintains the I
inrush current limit for charging
LIMIT_LOW
the load capacitor regardless of the state of I
. The
LIM_EN
operation of the I
pin is summarized in Table 3.
LIM_EN
LTC4264
10 PWRGD
UVLO
THERMAL SD
CONTROL
CIRCUIT
INRUSH COMPLETE
AND NOT IN THERMAL SHUTDOWN
POWER
POWER
NOT
GOOD
9
PWRGD
REF
GOOD
V
V
5
6
8
7
V
V
IN
OUT
V
< UVLO OFF
IN
OR THERMAL SHUTDOWN
OUT
IN
4264 BD
BOLD LINE INDICATES HIGH CURRENT PATH
Figure 8. LTC4264 Power Good Functional and State Diagram
4264f
13
LTC4264
APPLICATIONS INFORMATION
The active high PWRGD pin features an internal, open-
the instantaneous power dissipated by the LTC4264 can
be as high as 16W.
collector output referenced to V . During inrush, the
OUT
active high PWRGD pin pulls low until the load capacitor
is fully charged. At that point, PWRGD becomes high
impedance, indicating the converter may begin running.
The active high PWRGD pin can interface directly with the
“Run”pinofconverterproducts. ThePWRGDpinfeatures
The LTC4264 protects itself from damage by monitoring
die temperature. If the die exceeds the overtemperature
trip point, the power MOSFET and classification transis-
tors are disabled until the part cools down. Once the die
cools below the overtemperature trip point, all functions
are enabled automatically.
an internal 14V clamp to V
which protects the DC/DC
OUT
converter from excessive voltage. During a power supply
During classification, excessive heating of the LTC4264
can occur if the PSE violates the 75ms probing time limit.
In addition, the IEEE 802.3af specification requires a PD
to withstand application of any voltage from 0V to 57V
indefinitely. To protect the LTC4264 in these situations,
the thermal protection circuitry disables the classification
circuit if the die temperature exceeds the overtemperature
trip point. When the die cools down, classification current
is enabled.
rampdownevent, PWRGDbecomeslowimpedancewhen
V drops below the UVLO turn-off threshold, then goes
IN
high impedance when the V voltages fall to within the
IN
detection voltage range.
The active low PWRGD pin connects to an internal, open
drain MOSFET referenced to V which can sink 1mA.
IN
During inrush, PWRGD is high impedance. Once the load
capacitorisfullycharged,PWRGDispulledlowandDC/DC
converter operation can begin. The active low PWRGD
pin can connect directly to the shutdown pin of converter
Once the LTC4264 has charged up the load capacitor
and the PD is powered and running, there will be some
residual heating due to the DC load current of the PD
flowing through the internal MOSFET. In some high cur-
rent applications, the LTC4264 power dissipation may be
significant.TheLTC4264usesathermallyenhancedDFN12
package that includes an Exposed Pad which should be
soldered to an electrically isolated heat sink on the printed
circuit board.
products. PWRGD is referenced to the V pin and when
IN
active will be near the V potential. The converter will
IN
typically be referenced to V
and care must be taken to
OUT
ensure that the difference in potential of the PWRGD pin
does not cause a problem for the DC/DC converter. The
use of diode clamp D9 and R , as shown in Figure 11,
S
alleviates any problems.
THERMAL PROTECTION
MAXIMUM AMBIENT TEMPERATURE
The LTC4264 includes thermal overload protection in
order to provide full device functionality in a miniature
package while maintaining safe operating temperatures.
At turn-on, before load capacitor C1 has charged up, the
instantaneous power dissipated by the LTC4264 can be
as high as 20W. As the load capacitor charges, the power
dissipation in the LTC4264 will decrease until it reaches
a steady-state value dependent on the DC load current.
The LTC4264 can also experience device heating after
turn-on if the PD experiences a fast input voltage rise. For
example, if the PD input voltage steps from –37V to –57V,
TheLTC4264I
pinallowsthePDdesignertodisable
LIM_EN
the normal operating current limit. With the normal cur-
rent limit disabled, it is possible to pass currents as high
as 1.4A through the LTC4264. In this mode, significant
package heating may occur. Depending on the current,
voltage, ambient temperature, and waveform character-
istics, the LTC4264 may shut down. To avoid nuisance
trips of the thermal shutdown, it may be necessary to
limit the maximum ambient temperature. Limiting the die
temperature to 125°C will keep the LTC4264 from hitting
4264f
14
LTC4264
APPLICATIONS INFORMATION
suchasBelFuse, Coilcraft, Halo, Pulse, andTyco(Table 4)
can provide assistance with selection of an appropriate
isolation transformer and proper termination methods.
These vendors have transformers specifically designed
for use in high power PD applications.
thermal shutdown. For DC loads the maximum ambient
temperature can be calculated as:
T
= 125 – θ • PWR (°C)
MAX
JA
where T
is the maximum ambient operating tempera-
MAX
ture, θ is the junction-to-ambient thermal resistance
JA
(43°C/W), and PWR is the power dissipation for the
LTC4264 in Watts (I R ).
Table 4. Power over Ethernet Transformer Vendors
2
VENDOR
CONTACT INFORMATION
PD ON
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
www.belfuse.com
EXTERNAL INTERFACE AND COMPONENT SELECTION
Transformer
Coilcraft Inc.
1102 Silver Lake Road
Gary, IL 60013
Nodes on an Ethernet network commonly interface to
the outside world via an isolation transformer (Figure 9).
For powered devices, the isolation transformer must
include a center tap on the media (cable) side. Proper
termination is required around the transformer to provide
correct impedance matching and to avoid radiated and
conductedemissions.Forhighpowerapplicationsbeyond
IEEE 802.3af limits, the increased current levels increase
the current imbalance in the magnetics. This imbalance
reduces the perceived inductance and can interfere with
data transmission. Transformers specifically designed for
highcurrentapplicationsarerequired.Transformervendors
Tel: 847-639-6400
www.coilcraft.com
Halo Electronics
Pulse Engineering
Tyco Electronics
1861 Landings Drive
Mountain View, CA 94043
Tel: 650-903-3800
www.haloelectronics.com
12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
www.pulseeng.com
308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
www.circuitprotection.com
RJ45
+
1
TX
16 T1
15
1
2
BR1
HD01
–
TX
14
11
3
6
2
3
+
TO PHY
RX
10
9
7
8
–
RX
6
PULSE H2019
GND
+
–
SPARE
4
5
7
8
BR2
HD01
C1
LTC4264
C14
D3
SMAJ58A
TVS
0.1µF
100V
SPARE
V
V
OUT
V
IN
OUT
4264 F09
Figure 9. PD Front-End with Isolation Transformer, Diode Bridges, Capacitors and TVS
4264f
15
LTC4264
APPLICATIONS INFORMATION
Diode Bridge
bridgeswhilemaintainingproperthresholdpointsforIEEE
802.3af compliance.
IEEE 802.3af allows power wiring in either of two configu-
rations on the TX/RX wires, and power can be applied to
the PD via the spare wire pair in the RJ45 connector. The
PD is required to accept power in either polarity on both
the data and spare inputs; therefore it is common to install
diode bridges on both inputs in order to accommodate
the different wiring configurations. Figure 9 demonstrates
an implementation of the diode bridges. The IEEE 802.3af
specification also mandates that the leakage back through
the unused bridge be less than 28µA when the PD is
powered with 57V.
Figure 4 shows how two diode bridges are typically con-
nected in a PD application. One bridge is dedicated to the
data pair while the second bridge is dedicated to the spare
pair. For high power applications, a diode bridge typically
used in an IEEE 802.3af system cannot handle the higher
currents because the operating current is derated at the
upper temperature range. To solve this problem, the PD
application can utilize larger diode bridges, use discrete
diodes or consider the following alternative option.
Realizing that the two diode bridges do not need to be
exclusive to the data and spare pairs, the bridges may
be reconnected so that current is shared between them.
The new configuration extends the maximum operating
current while maintaining the smaller package profiles.
Figure 9 shows an example of how the two diode bridges
may be reconnected. Consult the diode bridge vendors for
operating current derating curves when only one of four
diodes is in operation.
The PD may be configured to handle 2-pair or 4-pair
power delivery over the Ethernet cable. In a 2-pair power
delivery system, one of the two pairs is delivering power
to the PD—either the main pair or the spare pair, but not
both. In a 4-pair system, both the main and spare pairs
deliver power to the PD simultaneously (see Figures 1
and 2). In either case, a diode bridge is needed on the
front end to accept power in either polarity. Contact LTC
applications for more information about implementing a
4-pair PoE system.
Auxiliary Power Source
In some applications, it may be necessary to power the PD
from an auxiliary power source such as a wall adapter. The
auxiliary power can be injected into the PD at several loca-
tions and various trade-offs exist. Figure 10 demonstrates
four methods of connecting external power to a PD.
The IEEE standard includes an AC impedance requirement
in order to implement the AC disconnect function. Capaci-
tor C14 in Figure 9 is used to meet this AC impedance
requirement. A 0.1µF capacitor is recommended for this
application.
Option 1 in Figure 10 inserts power before the LTC4264
interface controller. In this configuration, it is necessary
for the wall adapter to exceed the LTC4264 UVLO turn-
on requirement. This option provides input current limit
for the adapter, provides a valid power good signal and
simplifies power priority issues. As long as the adapter
applies power to the PD before the PSE, it will take priority
and the PSE will not power up the PD because the external
power source will corrupt the 25k signature. If the PSE
is already powering the PD, the adapter power will be in
parallel with the PSE. In this case, priority will be given to
the higher supply voltage. If the adapter voltage is higher,
the PSE should remove the port voltage since no current
The LTC4264 has several different modes of operation
based on the voltage present between the V and GND
IN
pins. The forward voltage drop of the input diodes in a
PD design subtracts from the input voltage and will af-
fect the transition point between modes. When using the
LTC4264, it is necessary to pay close attention to this
forward voltage drop. Selection of oversized diodes will
help keep the PD thresholds from exceeding IEEE 802.3af
specifications.
The input diode bridge of a PD can consume over 4% of
the available power in some applications. Schottky diodes
can be used in order to reduce power loss. The LTC4264 is
designed to work with both standard and Schottky diode
4264f
16
LTC4264
APPLICATIONS INFORMATION
OPTION 1: AUXILIARY POWER INSERTED BEFORE LTC4264
RJ45
1
+
T1
TX
D3
SMAJ58A
TVS
~
~
+
–
–
C14
0.1µF
100V
TX
2
3
+
C1
TO PHY
RX
BR1
BR2
PD
LOAD
–
RX
6
GND
• 42V ≤ V
WW
≤ 57V
+
–
SPARE
4
5
7
8
~
~
+
–
• NO POWER PRIORITY ISSUES
LTC4264
• LTC4264 CURRENT LIMITS FOR BOTH PoE AND V
WW
SPARE
V
V
OUT
IN
+
D8
S1B
ISOLATED
WALL
TRANSFORMER
V
WW
–
OPTION 2: AUXILIARY POWER INSERTED AFTER LTC4264 WITH SIGNATURE DISABLED
RJ45
1
+
T1
TX
D3
SMAJ58A
TVS
~
~
+
–
–
C14
0.1µF
100V
TX
2
3
+
C1
TO PHY
RX
BR1
BR2
PD
LOAD
–
RX
6
GND
100k
+
–
SPARE
BSS63
4
5
7
8
~
~
+
–
LTC4264
SHDN
D9
S1B
100k
SPARE
V
IN
V
OUT
• V
WW
ANY VOLTAGE BASED ON PD LOAD
+
V
D10
S1B
ISOLATED
WALL
TRANSFORMER
• REQUIRES EXTRA DIODE
• SEE APPS REGARDING POWER PRIORITY
WW
–
OPTION 3: AUXILIARY POWER APPLIED TO LTC4264 AND PD LOAD
RJ45
1
+
T1
TX
D3
SMAJ58A
TVS
~
~
+
–
–
C14
0.1µF
100V
TX
2
3
+
C1
TO PHY
RX
BR1
BR2
PD
LOAD
–
RX
6
GND
• 42V ≤ V
WW
≤ 57V
+
–
SPARE
4
5
7
8
• NO POWER PRIORITY ISSUES
~
~
+
–
LTC4264
• NO LTC4264 CURRENT LIMITS FOR V
WW
SPARE
V
IN
V
OUT
+
D10
S1B
ISOLATED
WALL
TRANSFORMER
V
WW
–
OPTION 4: AUXILIARY POWER APPLIED TO ISOLATED LOAD
RJ45
1
+
T1
TX
D3
SMAJ58A
TVS
C14
0.1µF
100V
C1
~
~
+
–
–
TX
ISOLATED DC/DC CONVERTER
2
3
+
TO PHY
RX
BR1
BR2
–
DRIVE
LOAD
RX
6
GND
+
–
SPARE
4
5
7
8
~
~
+
–
LTC4264
SHDN
• V
WW
ANY VOLTAGE BASED ON PD LOAD
• SEE APPS REGARDING POWER PRIORITY
• BEST ISOLATION
SPARE
V
IN
V
OUT
+
V
ISOLATED
WALL
TRANSFORMER
WW
–
Figure 10. Interfacing Auxiliary Power Source to the PD
4264f
17
LTC4264
APPLICATIONS INFORMATION
will be drawn from the PSE. On the other hand, if the
adapter voltage is lower, the PSE will continue to supply
power to the PD and the adapter will not be used. Proper
operation will occur in either scenario.
Option 4 bypasses the entire PD interface and injects
power at the output of the low voltage power supply. If
the adapter output is below the low voltage output there
are no power priority issues. However, if the adapter is
above the internal supply, then option 4 suffers from the
same power priority issues as option 2 and the signature
should be disabled or a minimum load should be installed.
Showninoption4isonemethodtodisabletothesignature
while maintaining isolation.
Option 2 applies power directly to the DC/DC converter.
In this configuration the adapter voltage does not need to
exceed the LTC4264 turn-on UVLO requirement and can
be selected based solely on the PD load requirements. It
is necessary to include diode D9 to prevent the adapter
from applying power to the LTC4264. Power priority is-
sues require more intervention. If the adapter voltage is
below the PSE voltage, then the priority will be given to the
PSE power. The PD will draw power from the PSE while
the adapter will remain unused. This configuration is ac-
ceptable in a typical PoE system. However, if the adapter
voltage is higher than the PSE voltage, the PD will draw
power from the adapter. In this situation, it is necessary
to address the issue of power cycling that may occur if
a PSE is present. The PSE will detect the PD and apply
power. If the PD is being powered by the adapter, then
the PD will not meet the minimum load requirement and
the PSE may subsequently remove power. The PSE will
again detect the PD and power cycling will start. With an
adapter voltage above the PSE voltage, it is necessary to
either disable the signature as shown in option 2, or install
a minimum load on the output of the LTC4264 to prevent
power cycling. A 3k, 1W resistor connected between GND
If employing options 1 through 3, it is necessary to ensure
that the end-user cannot access the terminals of the aux-
iliary power jack on the PD since this would compromise
IEEE 802.3af isolation requirements and may violate local
safety codes. Using option 4 along with an isolated power
supply addresses the isolation issue and it is no longer
necessary to protect the end-user from the power jack.
The above power cycling scenarios have assumed the
PSE is using DC disconnect methods. For a PSE using
AC disconnect, a PD with less than minimum load will
continue to be powered.
Walladaptershavebeenknowntogeneratevoltagespikes
outside their expected operating range. Care should be
taken to ensure no damage occurs to the LTC4264 or any
support circuitry from extraneous spikes at the auxiliary
power interface.
Classification Resistor Selection (R
)
CLASS
and V
will present the required minimum load.
OUT
The IEEE 802.3af specification allows classifying PDs
into four distinct classes with class 4 being reserved
for future use (Table 2). The LTC4264 supports all IEEE
classes and implements an additional Class 5 for use in
custom PoE applications. An external resistor connected
Option 3 applies power directly to the DC/DC converter
bypassing the LTC4264 and omitting diode D9. With the
diodeomitted,theadaptervoltageisappliedtotheLTC4264
in addition to the DC/DC converter. For this reason, it is
necessary to ensure that the adapter maintain the voltage
between 42V and 57V to keep the LTC4264 in its normal
operating range. The third option has the advantage of
corrupting the 25k signature resistance when the external
voltage exceeds the PSE voltage and thereby solving the
power priority issue.
from R
to V (Figure 6) sets the value of the load
CLASS
IN
current. The designer should determine which class the
PD is to advertise and then select the appropriate value of
4264f
18
LTC4264
APPLICATIONS INFORMATION
Power Good Interface
R
from Table 2. If a unique load current is required,
CLASS
the value of R
can be calculated as:
CLASS
TheLTC4264providescomplimentarypowergoodsignals
tosimplifytheDC/DCconverterinterface.Usingthepower
good signal to delay converter operation until the load
capacitorisfullychargedisrecommendedasthiswillhelp
ensure trouble free start up. The active high PWRGD pin
is controlled by an open collector transistor referenced to
R
= 1.237V/(I
– I
)
CLASS
LOAD
IN_CLASS
I
is the LTC4264 IC supply current during clas-
IN_CLASS
sification given in the electrical specifications. The R
CLASS
resistormustbe1%orbettertoavoiddegradingtheoverall
accuracyoftheclassificationcircuit.Resistorpowerdissi-
pationwillbe100mWmaximumandistransientsoheating
is typically not a concern. In order to maintain loop stabil-
V
while the active low PWRGD pin is controlled by a
OUT
high voltage, open-drain MOSFET referenced to V . The
IN
designer has the option of using either of these signals to
enabletheDC/DCconverterandexampleinterfacecircuits
are shown in Figure 11. When using PWRGD, diode D9
ity, the layout should minimize capacitance at the R
CLASS
node. The classification circuit can be disabled by floating
the R
pin. The R
pin should not be shorted to
CLASS
CLASS
and resistor R protects the converter shutdown pin from
S
V as this would force the LTC4264 classification circuit
IN
excessive reverse voltage.
to attempt to source very large currents. In this case, the
LTC4264 will quickly go into thermal shutdown.
ACTIVE-HIGH ENABLE
GND
PD
LTC4264
PWRGD
TO
PSE
LOAD
RUN
–54V
V
V
OUT
IN
ACTIVE-LOW ENABLE
R9
GND
100k
PD
R
S
LTC4264
PWRGD
TO
PSE
LOAD
10k
SHDN
D9
5.1V
MMBZ5231B
–54V
V
V
OUT
IN
ACTIVE-LOW ENABLE
R10
GND
100k
R
S
LTC4264
PWRGD
TO
PSE
+
V
10k
Q1
PD
LOAD
FMMT2222
D9
MMBD4148
–54V
V
V
OUT
IN
4264 F11
Figure 11. Power Good Interface Examples
4264f
19
LTC4264
APPLICATIONS INFORMATION
and the DC load of the PD, the PD will not draw any power
from the PSE for a period of time. If this period of time
exceeds the IEEE 802.3af 300ms disconnect delay, the
PSE will remove power from the PD. For this reason, it is
necessary to evaluate the load current and capacitance to
ensure that inadvertent shutdown cannot occur.
Shutdown Interface
To disable the 25k signature resistor, connect SHDN to
the GND pin. Alternately, the SHDN pin can be driven
high with respect to V . Examples of interface circuits
IN
that disable the signature and all LTC4264 functions are
shown in Figure 10, options 2 and 4. Note that the SHDN
input resistance is relatively large and the threshold volt-
age is fairly low. Because of high voltages present on the
printed circuit board, leakage currents from the GND pin
couldinadvertentlypullSHDNhigh.Toensuretrouble-free
operation,usehighvoltagelayouttechniquesinthevicinity
Refer also to Thermal Protection in this data sheet for
further discussion on load capacitor selection.
MAINTAIN POWER SIGNATURE
In an IEEE 802.3af system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically
draw at least 10mA and also have an AC impedance less
than 26.25kΩ in parallel with 0.05µF. If either the DC
current is less than 10mA or the AC impedance is above
26.25kΩ, the PSE may disconnect power. The DC current
must be less than 5mA and the AC impedance must be
above 2MΩ to guarantee power will be removed. The PD
application circuits shown in this data sheet present the
required AC impedance necessary to maintain power.
of SHDN. If unused, connect SHDN directly to V .
IN
Load Capacitor
TheIEEE802.3afspecificationrequiresthatthePDmaintain
a minimum load capacitance of 5µF. It is permissible to
have a much larger load capacitor and the LTC4264 can
charge very large load capacitors before thermal issues
become a problem. However, the load capacitor must not
be too large or the PD design may violate IEEE 802.3af
requirements. The LTC4264 maintains IEEE 802.3af com-
pliance when the load capacitor is 180µF or less. A larger
capacitor can be employed in a proprietary, close-system
high power application.
LAYOUT CONSIDERATIONS FOR THE LTC4264
The LTC4264 is relatively immune to layout problems.
If the load capacitor is too large, there can be a prob-
lem with inadvertent power shutdown by the PSE. For
example, if the PSE is running at –57V (IEEE 802.3af
maximum allowed) and the PD is detected and powered
up, the load capacitor will be charged to nearly –57V. If
for some reason the PSE voltage is suddenly reduced to
–44V (IEEE 802.3af minimum allowed), the input bridge
will reverse bias and the PD power will be supplied by the
load capacitor. Depending on the size of the load capacitor
Excessive parasitic capacitance on the R
pin should
CLASS
be avoided. Include an electrically isolated heat sink to
which the exposed pad on the bottom of the package can
be soldered. For optimum thermal performance, make the
heat sink as large as possible. Voltages in a PD can be as
large as –57V for PoE applications, so high voltage layout
techniques should be employed. The SHDN pin should
be separated from other high voltage pins, like GND and
4264f
20
LTC4264
APPLICATIONS INFORMATION
OUT
V
, to avoid the possibility of leakage shutting down the
peak voltages in excess of 10kV. To protect the LTC4264,
itishighlyrecommendedthattheSMAJ58Aunidirectional
58V transient voltage suppressor be installed between the
diode bridge and the LTC4264 (D3 in Figure 4).
LTC4264. If not used, tie SHDN to V .
IN
The load capacitor connected between GND and V
OUT
of the LTC4264 can store significant energy when fully
charged. The design of a PD must ensure that this en-
ergy is not inadvertently dissipated in the LTC4264. The
polarity-protection diodes prevent an accidental short
ISOLATION
The802.3standardrequiresEthernetportstobeelectrically
isolatedfromallotherconductorsthatareuseraccessible.
This includes the metal chassis, other connectors and
any auxiliary power connection. For PDs, there are two
common methods to meet the isolation requirement. If
there will be any user accessible connection to the PD,
then an isolated DC/DC converter is necessary to meet
the isolation requirements. If user connections can be
avoided, then it is possible to meet the safety requirement
by completely enclosing the PD in an insulated housing.
In all PD applications, there should be no user accessible
electrical connections to the LTC4264 or support circuitry
other than the RJ-45 port.
on the cable from causing damage. However, if the V
IN
pin is shorted to GND inside the PD while the capacitor
is charged, current will flow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4264.
ELECTRO STATIC DISCHARGE AND SURGE
PROTECTION
The LTC4264 is specified to operate with an absolute
maximumvoltageof–90Vandisdesignedtotoleratebrief
over-voltageevents.However,thepinsthatinterfacetothe
outside world (primarily V and GND) can routinely see
IN
4264f
21
LTC4264
APPLICATIONS INFORMATION
4264f
22
LTC4264
PACKAGE DESCRIPTION
DE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev C)
0.70 0.05
3.60 0.05
2.20 0.05 (2 SIDES)
1.70 0.05
PACKAGE OUTLINE
0.25 0.05
0.50
BSC
3.30 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.40 0.10
4.00 0.10
(2 SIDES)
R = 0.115
TYP
7
12
R = 0.05
TYP
3.00 0.10 1.70 0.05
(2 SIDES)
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
(UE12/DE12) DFN 0905 REV C
6
0.25 0.05
1
0.75 0.05
0.200 REF
0.50
BSC
3.30 0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4264f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC4264
TYPICAL APPLICATION
LTC4264 with Auxiliary Supply
+
V
OUT
+
AC ADAPTER
24V
OUT TO DC/DC
CONVERTER
D1
SMAJ58A
–
30W
C8
0.1µF
100V
B2100 4 PLCS
D3
D4
D5
D2
PD IN
36V TO 57V
T3 ETH1-230LD
14
1
1
2
3
6
•
•
•
•
•
•
C5
+
13
12
11
10
2
3
4
5
IN
FROM
HIGH
POWER
PSE
12µF
100V
TO
PHY
4
5
7
8
R14
100k
•
•
•
•
•
•
Q5
LTC4264
SHDN
NC
FMMT23
9
6
D7
D6
D8
D9
1
2
3
4
5
6
12
11
10
9
8
7
GND
NC
R12
J1
100k
R18
100k
SS-6488-NF-K1
R
PWRGD
PWRGD
CLASS
R
CLASS
PWRGD
–
I
R21
100k
LIM_EN
22.1Ω
D15 B2100
D12 B2100
V
V
V
V
IN
IN
OUT
OUT
1%
R4
75Ω
R5
R6
R7
V
OUT
75Ω
75Ω
75Ω
B2100 4 PLCS
NC
13
C13
0.01µF
200V
C14
C15
C16
0.01µF 0.01µF
0.01µF
200V
200V
200V
C17
1000pF
2kV
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Burst Mode is a registered trademark of Linear Technology Corporation. No R
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SENSE
4264f
LT 0307 • PRINTED IN USA
24 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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