LTC4265CDE-TRPBF [Linear]
IEEE 802.3at High Power PD Interface Controller with 2-Event Classifi cation Recognition; 符合IEEE 802.3at高功率PD接口控制器， 2级事件群分类识别
| 型号： | LTC4265CDE-TRPBF |
| 厂家： | 
Linear |
| 描述： | IEEE 802.3at High Power PD Interface Controller with 2-Event Classifi cation Recognition |
| 文件： | 总20页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4265
IEEE 802.3at High Power PD
Interface Controller with
2-Event Classification Recognition
FEATURES
DESCRIPTION
The LTC®4265 is a 3rd generation Powered Device (PD)
Interface controller intended for IEEE 802.3at high power
Power-over-Ethernet (PoE) applications up to 25.5W. By
supporting 1-event and 2-event classification signaling as
defined by IEEE 802.3, the LTC4265 can be used in a wide
range of product configurations. A 100V MOSFET isolates
the DC/DC converter during detection and classification,
and provides 100mA inrush current for a smooth power-
up transition. The LTC4265 also includes complementary
power good outputs, an on-board signature resistor,
undervoltage/overvoltage lockout and comprehensive
thermal protection. All Linear Technology PD solutions
include a shutdown pin with signature corrupt to provide
flexible auxiliary power options.
n
IEEE 802.3af/at Powered Device (PD) Controller
IEEE 802.3at 2-event Classification Signaling
Programmable Classification Current
Flexible Auxiliary Power Support Using SHDN Pin
Rugged 100V Onboard MOSFET with 100mA Inrush
Current Limit.
Complementary Power Good Outputs
Onboard Signature Resistor
Comprehensive Thermal Protection
n
n
n
n
n
n
n
n
n
Undervoltage and Overvoltage Lockout
12-Lead, 4mm × 3mm DFN Package
APPLICATIONS
n
802.11n Access Points
The LTC4265 PD interface controller can be used along
with a variety of DC/DC converter products to provide a
complete, cost effective power solution for high power
PD applications.
n
High Power VoIP Video Phones
n
RFID Reader Systems
PTZ Security Cameras and Surveillance Equipment
n
The LTC4265 is available in the space-saving low profile
(4mm × 3mm) DFN package and is drop-in compatible
with the LTC4264.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Turn-On vs Time
C
= 100μF
GND – V
IN
50V/DIV
LOAD
~
~
~
~
+
–
+
–
+
LTC4265
GND
54V FROM
DATA PAIR
V
0.1μF
+
5μF
MIN
SWITCHING
POWER
SUPPLY
GND – V
OUT
PWRGD
R
CLASS
50V/DIV
+
R
CLASS
PWRGD
RUN
3.3V
RTN
54V FROM
SPARE PAIR
SHDN
TO LOGIC
PWRGD – V
OUT
50V/DIV
V
V
–
IN
OUT
T2PSE
TO AUX
TO LOGIC
I
PD
100mA/DIV
4265 TA01a
TIME
25ms/DIV
4265 TA01b
4265f
1
LTC4265
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2, 3)
TOP VIEW
GND Voltage ............................................ –0.3V to 100V
SHDN
T2PSE
1
2
3
4
5
6
12 GND
11 NC
V
V
Voltage........................–0.3V to 100V (and ≤ GND)
Pull-Up Current ..................................................1A
OUT
OUT
R
10 PWRGD
CLASS
NC
SHDN....................................................... –0.3V to 100V
13
9
8
7
PWRGD
R
R
, Voltage............................................ –0.3V to 7V
Current.......................................................50mA
CLASS
CLASS
V
V
V
V
IN
IN
OUT
OUT
PWRGD Voltage (Note 4)
Low Impedance Source .....V
– 0.3V to V
+11V
OUT
DE PACKAGE
12-LEAD (4mm s 3mm) PLASTIC DFN
OUT
Pull-Up Current....................................................5mA
PWRGD, T2PSE Voltage........................... –0.3V to 100V
PWRGD, T2PSE Pull-Up Current............................10mA
Junction Temperature ........................................... 125°C
Operating Ambient Temperature Range
T
= 125°C, θ = 43°C/W
JA
JMAX
EXPOSED PAD (PIN 13) TO BE SOLDERED TO PCB HEAT SINK
LTC4265C ................................................ 0°C to 70°C
LTC4265I.............................................. –40°C to 85°C
ORDER INFORMATION
LEAD FREE FINISH
LTC4265CDE#PBF
LTC4265IDE#PBF
TAPE AND REEL
PART MARKING*
4265
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4265CDE#TRPBF
LTC4265IDE#TRPBF
0°C to 70°C
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
4265
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4265f
2
LTC4265
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Input Voltage
Signature Range
At GND Pin (Note 5)
60
9.8
21
V
V
V
V
V
V
l
l
l
l
1.5
Classification Range
Turn-On Voltage
12.5
37.2
Undervoltage Lock Out
Overvoltage Lock Out
30.0
71
l
l
l
ON/UVLO Hysteresis Window
Signature/Class Hysteresis Window
Reset Threshold
4.1
1.4
V
V
V
State Machine Reset for 2-event Classification
Measured at GND Pin
2.57
5.40
SUPPLY CURRENT
l
l
Supply Current at 60V
Class 0 Current
1.35
0.40
mA
mA
GND = 17.5V, No R
Resistor
CLASS
SIGNATURE
l
l
l
Signature Resistance
1.5V ≤ GND ≤ 9.8V (Note 6)
1.5V ≤ GND ≤ 9.8V, V = 3V (Note 6)
23.25
26
11
11
kΩ
kΩ
kΩ
Invalid Signature Resistance, SHDN Invoked
SHDN
Invalid Signature Resistance During Mark Event (Notes 6, 7)
CLASSIFICATION
l
l
Class Accuracy
10mA < I
< 40mA, 12.5V < GND < 21V (Note 8, 9)
%
3.5
1
CLASS
Classification Stability Time
GND Pin Step to 17.5V, R
3.5% of Ideal Value (Notes 8, 9)
= 30.9, I
Within
CLASS
ms
CLASS
NORMAL OPERATION
l
l
l
Inrush Current
GND = 54, V
= 3V
60
100
180
1.0
1
mA
Ω
OUT
Power FET On Resistance
Power FET Leakage Current at V
DIGITAL INTERFACE
Tested at 600mA into V , GND = 54V
0.70
OUT
GND = SHDN = V
= 57V
OUT
μA
OUT
l
l
l
l
SHDN Input High Level Voltage
SHDN Input Low Level Voltage
SHDN Input Resistance
3
V
V
0.45
0.15
GND = 9.8V, SHDN = 9.65V
100
kΩ
V
PWRGD, T2PSE Voltage Output Low
Tested at 1mA, GND = 54V. For T2PSE, Must Complete
2-event Classification to See Active Low.
l
l
PWRGD, T2PSE Leakage Current
Pin Voltage Pulled 57V, GND = V = 0
1
μA
V
IN
PWRGD Voltage Output Low
Tested at 0.5mA, GND = 52V, V
is with Respect to V
= 48V, Output Voltage
0.4
OUT
OUT
l
l
PWRGD Voltage Clamp
PWRGD Leakage Current
Tested at 2mA, V
= 0V, Voltage with Respect to V
12
16.5
1
V
OUT
OUT
OUT
V
= 11V, V
= V = 0V, GND = 54V
μA
PWRGD
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 6: Signature resistance is measured via the ΔV/ΔI method with a
minimum ΔV of 1V. The LTC4265 signature resistance accounts for the
additional series resistance in the input diode bridge.
Note 2: All voltages are with respect to V pin unless otherwise noted.
Note 7: An invalid signature after the 1st classification event is mandated
IN
by IEEE 802.3at standard. See Applications Information.
Note 3: Pins with 100V absolute maximum guaranteed for T ≥ 0ºC, otherwise 90V.
Note 8: Class accuracy is with respect to the ideal current defined as
Note 4: PWRGD voltage clamps at 14V with respect to V
.
OUT
1.237/R
and does not include variations in R
resistance.
CLASS
CLASS
Note 5: Input voltage specifications are defined with respect to LTC4265
pins and meet IEEE 802.3af/at specifications when the input diode bridge
is included.
Note 9: This parameter is assured by design and wafer level testing.
4265f
3
LTC4265
TYPICAL PERFORMANCE CHARACTERISTICS
Input Current vs Input Voltage
25k Detection Range
Input Current vs Input Voltage
Input Current vs Input Voltage
50
40
30
20
0.5
0.4
0.3
0.2
11.0
10.5
T
= 25°C
CLASS 1 OPERATION
T
= 25°C
A
A
CLASS 4
CLASS 3
CLASS 2
CLASS 1
CLASS 0
85°C
–40°C
10.0
9.5
10
0
0.1
0
0
20
30
40
50
60
10
0
4
6
8
10
2
12
14
16
18
20
22
GND VOLTAGE (V)
(RISING)
GND VOLTAGE (V)
GND VOLTAGE (V)
4265 G01
4265 G03
4265 G02
Signature Resistance
vs Input Voltage
Class Operation vs Time
On Resistance vs Temperature
28
27
$V V2 – V1
RESISTANCE =
DIODES: HD01
=
T
= 25°C
INPUT
VOLTAGE
10V/DIV
A
$I
I – I
2 1
1.0
0.8
0.6
0.4
0.2
T
= 25°C
A
IEEE UPPER LIMIT
LTC4265 + 2 DIODES
26
25
24
CLASS
CURRENT
10mA/DIV
LTC4265 ONLY
IEEE LOWER LIMIT
23
22
4265 G05
TIME (10μs/DIV)
–50
0
25
50
75
100
–25
V1:
V2:
1
2
3
4
5
6
7
8
9
10
JUNCTION TEMPERATURE (°C)
GND VOLTAGE (V)
4265 G06
4265 G04
PWRGD, T2PSE Output Low
Voltage vs Current
Active High PWRGD
Output Low Voltage vs Current
Inrush Current vs Input Voltage
1.0
0.8
0.6
0.4
0.2
0
0.8
115
110
105
T
= 25°C
T
= 25°C
A
A
GND – V
= 4V
OUT
0.6
0.4
0.2
0
100
95
90
85
0
2
4
6
8
10
1
2
0
0.5
1.5
40
45
50
55
60
CURRENT (mA)
GND VOLTAGE (V)
CURRENT (mA)
4265 G07
4265 G08
4265 G09
4265f
4
LTC4265
PIN FUNCTIONS
SHDN (Pin 1): Shutdown Input. Use this pin for auxiliary
power application. Drive SHDN high to disable LTC4265
operation and corrupt the signature resistance. If unused,
V
OUT
(Pins 7, 8): Output Voltage Negative Rail. Connects
OUT
V
to V through an internal power MOSFET. Pins 7
IN
and 8 must be electrically tied together at the package.
tie SHDN to V .
IN
PWRGD (Pin 9): Power Good Output, Open Collector.
T2PSE (Pin 2): Type-2 PSE Indicator, Open-Drain. Low
impedance indicates the presence of a Type-2 PSE.
High impedance signals power-up completion. PWRGD
is referenced to V
and features a 14V clamp.
OUT
R
(Pin 3): Class Select Input. Connect a resistor
PWRGD (Pin 10): Complementary Power Good Output,
CLASS
between R
and V to set the classification load
Open-Drain.Lowimpedancesignalspowerupcompletion.
CLASS
IN
current. (See Table 2.)
PWRGD is referenced to V .
IN
NC (Pin 4, 11): No Connect.
GND (Pin 12): Input Voltage, Positive Rail. This pin is
connected to the PD positive rail.
V (Pins 5, 6): Input Voltage, Negative Rail. Pins 5 and 6
IN
must be electrically tied together at the package.
Exposed Pad (Pin 13): Tie to V and PCB heat sink.
IN
BLOCK DIAGRAM
SHDN
1
12 GND
CLASSIFICATION
CURRENT LOAD
+
–
REF
T2PSE
2
EN
25k
14k
11 NC
R
3
4
CLASS
NC
10 PWRGD
CONTROL
CIRCUITS
9
8
7
PWRGD
V
V
5
6
V
IN
OUT
IN
BOLD LINE INDICATES
HIGH CURRENT PATH
V
EXPOSED PAD
13
OUT
4265 BD
4265f
5
LTC4265
APPLICATIONS INFORMATION
OVERVIEW
50
40
30
20
10
Power over Ethernet (PoE) continues to gain popularity
as more products are taking advantage of having DC
power and high speed data available from a single RJ45
connector. As PoE continues to grow in the marketplace,
Powered Device (PD) equipment vendors are running into
the 12.95W power limit established by the IEEE 802.3af
standard.
ON
UVLO
CLASSIFICATION
DETECTION V2
TIME
DETECTION V1
50
40
30
20
10
dV
dt
INRUSH
C1
=
TheIEE802.3atstandardestablishesahigherpoweralloca-
tionforPower-over-Ethernetwhilemaintainingbackwards
compatibilitywiththeexistingIEEE802.3afsystems.Power
Sourcing Equipments (PSE) and Powered Devices are
distinguished as Type-1 complying with the IEEE 802.3af
power levels, or Type-2 complying with the IEEE 802.3at
power levels. The maximum available power of a Type-2
PD is 25.5W.
UVLO
ON
UVLO
T = R
C1
LOAD
TIME
TIME
–10
–20
–30
–40
–50
POWER
POWER
BAD
BAD
POWER
GOOD
PWRGD
TRACKS
GND
PWRGD
TRACKS
GND
TheIEEE802.3atstandardalsoestablishesanewmethodof
acquiringpowerclassificationfromaPDandcommunicat-
ing the presence of a Type-2 PSE. A Type-2 PSE has the
option of acquiring PD power classification by performing
2-event classification (Layer 1) or by communicating with
the PD over the data line (Layer 2). In turn, a Type-2 PD
must be able to recognize both layers of communications
and identify a Type-2 PSE.
PWRGD TRACKS
V
IN
20
10
POWER
BAD
POWER
GOOD
POWER
BAD
IN DETECTION
RANGE
TIME
LOAD, I
LOAD
The LTC4265 is specifically designed to support the front
end of a PD that must operate under the IEEE802.3at
standard. In particular, the LTC4265 provides the T2PSE
indicator bit which recognizes 2-event classification. This
indicator bit may be used to alert the LTC4265 output load
that a Type-2 PSE is present. With an internal signature
resistor, classification circuitry, inrush control, and ther-
mal shutdown, the LTC4265 is a complete PD Interface
solution capable of supporting in the next generation PD
applications.
INRUSH
CLASSIFICATION
TIME
DETECTION I
2
DETECTION I
V1 – 2 DIODE DROPS
1
V2 – 2 DIODE DROPS
25kΩ
SELECTION
CLASS
I
I
=
I
=
1
2
25kΩ
DEPENDENT ON R
CLASS
INRUSH = 100mA
V
IN
I
=
LOAD
R
LOAD
GND
OUT
MODES OF OPERATION
LTC4265
GND
R
I
LOAD
IN
R
CLASS
PWRGD
TheLTC4265hasseveralmodesofoperationdependingon
the input voltage applied between the GND and V pins.
Figure 1 presents an illustration of voltage and current
waveforms the LTC4265 may encounter with the various
modes of operation summarized in Table 1.
PSE
V
R
C1
CLASS
PWRGD
IN
V
V
IN
OUT
4265 F01
Figure 1. Output Voltage, PWRGD, PWRGD and
PD Current as a Function of Input Voltage
4265f
6
LTC4265
APPLICATIONS INFORMATION
These modes satisfy the requirements defined in the IEEE
802.3af/at specification.
The input diode bridge introduces a voltage drop that
affectstherangeforeachmodeofoperation. TheLTC4265
compensatesforthesevoltagedropssothataPDbuiltwith
theLTC4265meetstheIEEE802.3af/at-establishedvoltage
ranges. Note that the Electrical Specifications reference
with respect to the LTC4265 package pins.
Table 1. LTC4265 Modes of Operation as a Function
of Input Voltage
GND (V)
LTC4265 MODES OF OPERATION
0V to 1.4V
Inactive (Reset After 1st Classification Event)
1.5V to 9.8V
(5.4V to 9.8V)
25k Signature Resistor Detection Before 1st
Classification Event (Mark, 11k Signature
Corrupt After 1st Classification Event)
DETECTION
During detection, the PSE looks for a 25k signature resis-
tor which identifies the device as a PD. The PSE will apply
two voltages in the range of 2.8V to 10V and measures
the corresponding currents. Figure 1 shows the detection
voltagesV1andV2andthecorrespondingPDcurrent.The
PSE calculates the signature resistance using the ΔV/ΔI
measurement technique.
12.5V to ON/UVLO* Classification Load Current Active
ON/UVLO* to 60V
>71V
Inrush and Power Applied To PD Load
Overvoltage Lockout, 4265 Operations are Disabled
*ON/UVLO includes hysteresis. Rising input threshold, 37.2V Max.
Falling input threshold, 30V Min.
INPUT DIODE BRIDGE
TheLTC4265presentsitsprecision,temperature-compen-
In the IEEE 802.3af/at standard, the modes of operation
reference the input voltage at the PD’s RJ45 connector.
SincethePDmusthandlepowerreceivedineitherpolarity
from either the data or the spare pair, input diode bridges
BR1 and BR2 are connected between the RJ45 connector
and the LTC4265 (Figure 2).
sated 25k resistor between the GNDand V pins, alerting
IN
the PSE that a PD is present and requests power to be
applied.TheLTC4265signatureresistoralsocompensates
for the additional series resistance introduced by the input
diode bridge. Thus a PD built with the LTC4265 conforms
to the IEEE 802.3af/at detection specifications.
RJ45
+
1
T1
TX
BR1
–
TX
2
3
+
TO PHY
RX
–
RX
POWERED
DEVICE (PD)
INPUT
6
GND
+
–
SPARE
BR2
4
5
LTC4265
0.1μF
D3
100V
V
IN
4265 F02
7
8
SPARE
Figure 2. PD Front End Using Diode Bridges on Main and Spare Inputs
4265f
7
LTC4265
APPLICATIONS INFORMATION
SIGNATURE CORRUPT OPTION
During classification probing, the PSE presents a fixed
voltage between 15.5V and 20.5V to the PD (Figure 2).
The LTC4265 asserts a load current representing the PD
power classification. The classification load current is
In some designs that include an auxiliary power option,
it is necessary to prevent a PD from being detected by a
PSE. The LTC4265 signature resistance can be corrupted
with the SHDN pin (Figure 3). Taking the SHDN pin high
will reduce the signature resistor below 11k which is an
invalidsignaturepertheIEEE802.3af/atspecification, and
alerts the PSE not to apply power. Invoking the SHDN pin
also ceases operation for classification and disconnects
the LTC4265 load from the PD input. If this feature is not
programmed with a resistor R
Table 2.
that is chosen from
CLASS
Table 2. Summary of Power Classifications and LTC4265
RCLASS Resistor Selection
CLASS
USAGE
MAXIMUM
NOMINAL
LTC4265
POWER LEVELS CLASSIFICATION
R
CLASS
AT INPUT OF PD
(W)
LOAD CURRENT RESISTOR
used, connect SHDN to V .
(mA)
< 0.4
10.5
18.5
28
(Ω, 1%)
Open
124
IN
0
1
2
3
4
Default
Optional
Optional
Optional
Optional
0.44 to 12.95
0.44 to 3.84
3.84 to 6.49
6.49 to 12.95
12.95 to 25.5
LTC4265
GND
69.8
25k SIGNATURE
RESISTOR
TO
PSE
14k
45.3
SHDN
40
30.9
V
IN
2-EVENT CLASSIFICATION AND THE T2PSE PIN
4265 F03
TO AUX
A Type-2 PSE may declare the availability of high power by
performing 2-event classification (Layer 1) or by commu-
nicating over the high speed data line (Layer 2). A Type-2
PD must recognize both layers of communication. Since
Layer 2 communications takes place directly between the
PSE and the LTC4265 load, the LTC4265 concerns itself
only with recognizing 2-event classification.
Figure 3. 25k Signature Resistor with Disable
CLASSIFICATION
Classification provides a method for more efficient power
allocation by allowing the PSE to identify a PD power clas-
sification. Class 0 is included in the IEEE specification for
PDs that don’t support classification. Class 1-3 partitions
PDs into 3 distinct power ranges. Class 4 includes the new
power range under IEEE802.3at (See Table 2).
4265f
8
LTC4265
APPLICATIONS INFORMATION
In 2-event classification, a Type-2 PSE probes for power
classification twice. Figure 4 presents an example of a
2-event classification. The 1st classification event occurs
when the PSE presents an input voltage between 14.5V to
20.5V and the LTC4265 presents a class 4 load current.
The PSE then drops the input voltage into the mark volt-
age range of 6.9V to 10V, signaling the 1st mark event.
The PD in the mark voltage range presents a load current
between 0.25mA to 4mA.
50
40
30
20
10
1st CLASS
2nd CLASS
ON
UVLO
DETECTION V1
DETECTION V2
1st MARK 2nd MARK
INRUSH
LOAD, I
LOAD
1st CLASS
2nd CLASS
The PSE repeats this sequence, signaling the 2nd Clas-
sification and 2nd mark event occurrence. This alerts the
LTC4265 that a Type-2 PSE is present. The Type-2 PSE
then applies power to the PD and the LTC4265 charges
up the reservoir capacitor C1 with a controlled inrush cur-
rent. When C1 is fully charged, and the LTC4265 declares
power good, the T2PSE pin presents an active low signal,
40mA
TIME
DETECTION V1
DETECTION V2
1st MARK 2nd MARK
50
40
30
20
10
dV
dt
INRUSH
C1
=
or low impedance output with respect to V . The T2PSE
IN
output becomes inactive when the LTC4265 input voltage
UVLO
ON
UVLO
falls outside the normal operating range.
T = R
C1
LOAD
SIGNATURE CORRUPT DURING MARK
TIME
TIME
As a member of the IEEE802.3at working group, Linear
notes that it is possible for a Type-2 PD to receive a
false indication of a 2-event classification if a PSE port
is pre-charged to a voltage above the detection voltage
range before the first detection cycle. The IEEE working
group modified the standard to prevent this possibility by
requiring a Type-2 PD to corrupt the signature resistance
duringthemarkevent, alertingthePSEnottoapplypower.
The LTC4265 conforms to this standard by internally
corrupting the signature resistance. This also discharges
the port before the PSE begins the next detection cycle.
–10
–20
–30
–40
–50
TRACKS
V
IN
INRUSH = 100mA
R
= 30.9Ω
CLASS
V
IN
I
=
LOAD
R
LOAD
GND
LTC4265
GND
R
I
LOAD
IN
R
CLASS
PSE
V
OUT
R
CLASS
C1
T2PSE
V
V
OUT
IN
4265 F04
Figure 4. VOUT, T2PSE, and PD Current
as a Result of 2-event Classification
4265f
9
LTC4265
APPLICATIONS INFORMATION
PD STABILITY DURING CLASSIFICATION
characteristic that is independent of the PSE behavior.
This ensures a PD using the LTC4265 interoperability
with any PSE.
Classificationpresentsachallengingstabilityproblemdue
to the wide range of possible classification load current.
The onset of the classification load current introduces a
voltage drop across the cable and increases the forward
voltage of the input diode bridge. This may cause the PD
to oscillate between detection and classification with the
onset and removal of the classification load current.
UNDERVOLTAGE LOCKOUT
The IEEE 802.3af/at specification for the PD dictates a
maximum turn-on voltage of 42V and a minimum turn-off
voltage of 30V. This specification provides an adequate
voltage to begin PD operation, and to discontinue PD op-
eration when the input voltage is too low. In addition, this
specification allows PD designs to incorporate an on-off
hysteresis window to prevent start-up oscillations.
The LTC4265 prevents this oscillation by introducing a
voltagehysteresiswindowbetweenthedetectionandclas-
sification ranges. The hysteresis window accommodates
the voltage changes a PD encounters at the onset of the
classification load current, thus providing a trouble-free
transition between detection and classification modes.
TheLTC4265featuresanON-undervoltagelockout(UVLO)
hysteresis window (See Figure 5) that conforms with the
IEEE 802.3af/at specifications and accommodates the
voltage drop in the cable and input diode bridge at the
onset of the inrush current.
TheLTC4265alsomaintainsapositiveI-Vslopethroughout
the classification ranges up to the ON voltage. In the event
a PSE overshoots beyond the classification voltage range,
the available load current aids in returning the PD back
into the classification voltage range. (The PD input may
otherwise be “trapped” by a reverse-biased diode bridge
and the voltage held by the 0.1ꢁF capacitor.)
+
C1
5μF
MIN
LTC4265
PD
LOAD
GND
TO
PSE
UNDERVOLTAGE
OVERVOLTAGE
LOCKOUT
CIRCUIT
INRUSH CURRENT
V
IN
V
OUT
4265 F05
Once the PSE detects and optionally classifies the PD, the
PSE then applies powers on the PD. When the LTC4265
input voltage rises above the ON voltage threshold,
CURRENT-LIMITED
TURN ON
INPUT
LTC4265
VOLTAGE
0V TO ON*
>ON*
POWER MOSFET
OFF
ON
OFF
OFF
LTC4265 connects V
MOSFET.
to V through the internal power
OUT
IN
<UVLO*
>OVLO
To control the power-on surge currents in the system, the
LTC4265 provides a fixed inrush current, allowing C1 to
ramp up to the line voltage in a controlled manner.
*INCLUDES ON-UVLO HYSTERESIS
ON THRESHOLD ≅ 36.1V
UVLO THRESHOLD ≅ 30.7V
OVLO THRESHOLD ≅ 71.0V
The LTC4265 keeps the PD inrush current below the
PSE current limit to provide a well-controlled power-up
Figure 5. LTC4265 Undervoltage and Overvoltage Lockout
4265f
10
LTC4265
APPLICATIONS INFORMATION
Once C1 is fully charged, the LTC4265 turns on is internal
MOSFET and passes power to the PD load. The LTC4265
continues to power the PD load as long as the input volt-
age does not fall below the UVLO threshold. When the
LTC4265 input voltage falls below the UVLO threshold, the
PDloadisdisconnected,andclassificationmoderesumes.
C1 discharges through the LTC4265 circuitry.
PWRGD PIN WHEN SHDN IS INVOKED
InPDapplicationswhereanauxiliarypowersupplyinvokes
the SHDN feature, the PWRGD pin becomes high imped-
ance. This prevents the PWRGD pin that is connected to
the “Run” pin of the DC/DC converter from interfering
with the DC/DC converter operations when powered by
an auxiliary power supply.
COMPLEMENTARY POWERGOOD
LTC4265
10 PWRGD
WhenLTC4265fullychargestheloadcapacitor(C1),power
good is declared and the LTC4265 load can safely begin
operation. The LTC4265 provides complementary power
good signals that remain active during normal operation
and are de-asserted when the input voltage falls below
the UVLO threshold, when the input voltage exceeds the
over-voltage lockout (OVLO) threshold, or in the event of
a thermal shutdown. See Figure 6.
OVLO
ON
UVLO
TSD
CONTROL
CIRCUIT
9
PWRGD
V
V
5
6
8
7
V
V
IN
OUT
OUT
IN
The PWRGD pin features an open collector output refer-
BOLD LINE INDICATES HIGH CURRENT PATH
enced to V
which can interface directly with the “Run”
OUT
pin of a DC/DC converter product. When power good is
declared and active, the PWRGD pin is high impedance
INRUSH COMPLETE
ON < GND < OVLO
AND NOT IN THERMAL SHUTDOWN
with respect to V . An internal 14V clamp protects the
OUT
DC/DC converter from an excessive voltage.
POWER
POWER
NOT
GOOD
GOOD
The active low PWRGD pin connects to an internal, open
drain MOSFET referenced to V and can interface directly
IN
to the shutdown pin of a DC/DC converter product. When
GND < UVLO
GND > OVLO
OR THERMAL SHUTDOWN
power good is declared and active, the PWRGD pin is low
impedance with respect to V .
IN
4265 F06
Figure 6. LTC4265 Power Good Functional and State Diagram
4265f
11
LTC4265
APPLICATIONS INFORMATION
OVERVOLTAGE LOCKOUT
The LTC4265 includes a Thermal Protection feature which
protects the LTC4265 from excessive heating. If the
LTC4265 junction temperature exceeds the over-tempera-
ture threshold, the LTC4265 discontinues PD operations
and power-good becomes inactive. Normal operation
resumes when the junction temperature falls below the
over-temperature threshold and when C1 is charged up.
The LTC4265 includes an overvoltage lockout (OVLO)
feature (Figure 5) which protects the LTC4265 and its load
fromanovervoltageevent. Iftheinputvoltageexceedsthe
OVLO threshold, the LTC4265 discontinues PD operation.
Normal operations resume when the input voltage falls
below the OVLO threshold and when C1 is charged up.
EXTERNAL INTERFACE AND COMPONENT SELECTION
Transformer
THERMAL PROTECTION
TheIEEE802.3af/atspecificationrequiresaPDtowithstand
any applied voltage from 0V to 57V indefinitely. However,
there are several possible scenarios where a PD may
encounter excessive heating.
Nodes on an Ethernet network commonly interface to the
outside world via an isolation transformer. For PDs, the
isolation transformer must also include a center tap on
the RJ45 connector side (See Figure 7).
During classification, excessive heating may occur if the
PSEexceedsthe75msprobingtimelimit.Atturn-on,when
the load capacitor begins to charge, the instantaneous
power dissipated by the PD Interface can be large before
it reaches the line voltage. And if the PD experiences a
fast input positive voltage step in its operational mode
(for example, from 37V to 57V), the instantaneous power
dissipated by the PD Interface can be large.
The increased current levels in a Type-2 PD over a Type-1
increase the current imbalance in the magnetics which
can interfere with data transmission. In addition, proper
termination is also required around the transformer to
providecorrectimpedancematchingandtoavoidradiated
and conducted emissions. Transformer vendors such as
RJ45
+
1
TX
14 T1
12
1
3
BR1
HD01
–
TX
13
10
2
5
2
3
+
TO PHY
RX
11
9
4
6
–
RX
6
COILCRAFT
ETHI - 230LD
GND
+
–
SPARE
4
5
7
8
BR2
HD01
C1
LTC4265
C14
0.1μF
100V
D3
SMAJ58A
TVS
SPARE
V
V
V
OUT
IN
OUT
4265 F07
Figure 7. PD Front-End with Isolation Transformer, Diode Bridges,
Capacitors, and a Transient Voltage Suppressor (TVS).
4265f
12
LTC4265
APPLICATIONS INFORMATION
Bel Fuse, Coilcraft, Halo, Pulse, and Tyco (Table 4) can
assist in selecting an appropriate isolation transformer
and proper termination methods.
An input diode bridge must exceed the maximum current
the PD application will encounter at the temperature the
PD will operate. Diode bridge vendors typically call out
the operating current at room temperature, but derate the
maximum current with increasing temperature. Consult
the diode bridge vendors for the operating current derat-
ing curve.
Table 4. Power-over-Ethernet Transformer Vendors
VENDOR
CONTACT INFORMATION
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
www.belfuse.com
Asilicondiodebridgecanconsumeover4%oftheavailable
power in some PD applications. Using Schottky diodes can
help reduce the power loss with a lower forward voltage.
Coilcraft Inc.
1102 Silver Lake Road
Gary, IL 60013
Tel: 847-639-6400
www.coilcraft.com
A Schottky bridge may not be suitable for some high
temperature PD application. The leakage current has a
voltagedependencythatcanreducetheperceivedsignature
resistance. In addition, the IEEE 802.3af/at specification
mandates the leakage back-feeding through the unused
bridge cannot generate more than 2.8V across a 100k
resistor when a PD is powered with 57V.
Halo Electronics
Pulse Engineering
1861 Landings Drive
Mountain View, CA 94043
Tel: 650-903-3800
www.haloelectronics.com
12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
www.pulseeng.com
Tyco Electronics
308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
Sharing Input Diode Bridges
At higher temperatures, a PD design may be forced to
consider larger bridges in a bigger package because the
maximum operating current for the input diode bridge is
drastically de-rated. The larger package may not be ac-
ceptable in some space-limited environments.
www.circuitprotection.com
Input Diode Bridge
Figure 2 shows how two diode bridges are typically con-
nected in a PD application. One bridge is dedicated to the
data pair while the other bridge is dedicated to the spare
pair. The LTC4265 supports the use of either silicon or
Schottkyinputdiodebridges. However, therearetradeoffs
in the choice of diode bridges.
One solution to consider is to reconnect the diode bridges
so that only one of the four diodes conducts current in
each package. This configuration extends the maximum
operating current while maintaining a smaller package
profiles. Figure 7 shows how to reconnect the two diode
bridges.Consultthediodebridgevendorsforthede-rating
curve when only one of four diodes is in operation.
4265f
13
LTC4265
APPLICATIONS INFORMATION
Input Capacitor
ThisoccurswhenthePSEvoltagedropsquickly. Theinput
diode bridge reverses bias, and the PD load momentarily
powers off the load capacitor. If the PD does not draw
power within the PSE’s 300ms disconnection delay, the
PSE may remove power from the PD. Thus, it is necessary
to evaluate the load current and capacitance to ensure that
an inadvertent shutdown cannot occur.
The IEEE 802.3af/at standard includes an impedance
requirement in order to implement the AC disconnect
function. A 0.1μF capacitor (C14 in Figure 7) is used to
meet this AC impedance requirement.
Transient Voltage Suppressor
The load capacitor can store significant energy when fully
charged. The PD design must ensure that this energy is
not inadvertently dissipated in the LTC4265. For example,
The LTC4265 specifies an absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events.
However, the pins that interface to the outside world can
routinely see excessive peak voltages. To protect the
LTC4265, install a transient voltage suppressor (D3) be-
tween the input diode bridge and the LTC4265 as shown
in Figure 7.
if the GND pin shorts to V while the capacitor is charged,
IN
current will flow through the parasitic body diode of the
internal MOSFET and may cause permanent damage to
the LTC4265.
Power Good Interface
Classification Resistor (R
)
CLASS
The LTC4265 provides complementary power good sig-
nals to simplify the DC/DC converter interface. Using the
power good signal to delay converter operation until the
load capacitor is fully charged is highly recommended to
ensure trouble free start up.
The R
resistor sets the classification load current,
CLASS
corresponding to the PD power classification. Select the
value of R from Table 2 and connect the resistor
CLASS
between the R
or float the R
and V pins as shown in Figure 4,
CLASS
IN
pin if the classification load current is
CLASS
not required. The resistor tolerance must be 1% or better
to avoid degrading the overall accuracy of the classifica-
tion circuit.
Figure 8 presents examples of power good interface cir-
cuits. The active high PWRGD pin has an open collector
transistorreferencedtoVOUTwhiletheactivelowPWRGD
pin has a high voltage, open-drain MOSFET referenced
Load Capacitor
to V . The designer can choose either signal to enable
IN
the DC/DC converter. When using PWRGD, diode D9 and
The IEEE 802.3af/at specification requires that the PD
maintains a minimum load capacitance of 5ꢁF and does
not specify a maximum load capacitor. However, if the
load capacitor is too large, there may be a problem with
inadvertent power shutdown by the PSE.
resistor R protects the converter shutdown pin from
S
excessive reverse voltage.
4265f
14
LTC4265
APPLICATIONS INFORMATION
ACTIVE-HIGH ENABLE
Figure 9 shows two interface options using the T2PSE
pin and the opto-isolator. The T2PSE pin is active low and
connects to an opt-isolater to communicate across the
GND
PD
LTC4265
DC/DC converter isolation barrier. The pull up resistor R
TO
PSE
LOAD
P
RUN
PWRGD
is sized according to the requirements of the opto-isolator
operating current, the pull-down capability of the T2PSE
+
+
–54V
pin, and the choice of V . V for example can come from
the PoE supply rail (which the LTC4265 GND is tied to), or
from the voltage source that supplies power to the DC/DC
converter.Option1hastheadvantageofnotdrawingpower
unless T2PSE is declared active.
V
V
OUT
IN
ACTIVE-LOW ENABLE
R9
GND
100k
PD
R
S
LTC4265
PWRGD
TO
PSE
LOAD
10k
SHDN
D9
5.1V
MMBZ5231B
+
V
GND
–54V
V
IN
V
OUT
R
P
TO
PSE
LTC4265
ACTIVE-LOW ENABLE
R10
TO PD LOAD
V
IN
–54V
T2PSE
GND
100k
OPTION 1: SERIES CONFIGURATION FOR ACTIVE LOW/LOW IMPEDANCE OUTPUT
R
S
LTC4265
TO
PSE
+
V
10k
Q1
PWRGD
PD
LOAD
FMMT2222
+
V
D9
MMBD4148
GND
–54V
V
V
R
P
IN
OUT
4265 F08
LTC4265
TO
PSE
T2PSE
Figure 8. Power Good Interface Examples
TO PD LOAD
V
IN
V
OUT
–54V
4265 F09
T2PSE Interface
OPTION 2: SHUNT CONFIGURATION FOR ACTIVE HIGH/OPEN COLLECTOR OUTPUT
When a 2-event Classification sequence successfully
completes, the LTC4265 recognizes this sequence, and
provides an indicator bit, declaring the presence of a
Type-2 PSE. The open drain output provides the option
to use this signal to communicate to the LTC4265 load,
or to leave the pin unconnected.
Figure 9. T2PSE Interface Examples
4265f
15
LTC4265
APPLICATIONS INFORMATION
Shutdown Interface
PD applications may also opt for a seamless transition
— that is, without power disruption — between PoE and
auxiliary power.
To corrupt the signature resistance, the SHDN pin can be
driven high with respect to V or connected to GND. If
IN
unused, connect SHDN directly to V .
The most common auxiliary power option injects power
between the LTC4265 and the DC/DC converter. Figure 10
presents an example of this application.
IN
Exposed Pad
The LTC4265 uses a thermally enhanced DFN12 package
that includes an Exposed Pad. The exposed may be elec-
In this example, the auxiliary port injects 48V onto the line
via diode D1. The components surrounding the SHDN pin
are selected so that the LTC4265 disconnects power to the
output when the auxiliary supply reaches 36V.
trically connected to V and must connect to a printed
IN
circuit board heat sink.
This configuration is an auxiliary-dominant configuration.
Thatis,theauxiliarypowersourcesuppliesthepowereven
if PoE power is already present. This configuration also
providesaseamlesstransitionfromPoEtoauxiliarypower
when auxiliary power is applied, however, the removal of
auxiliary power to PoE power is not seamless.
Auxiliary Power Source
In some applications, it is desirable to power the PD from
an auxiliary power source such as a wall adapter.
AuxiliarypowercanbeinjectedintoanLTC4265-basedPD
at the input of the LTC4265, the output of the LTC4265, or
even the output of the DC/DC converter. In addition, some
PD application may desire auxiliary supply dominance
or may be configured for PoE dominance. Furthermore,
Contact Linear Technology applications support for detail
information on implementing a custom auxiliary power
supply.
RJ45
+
1
TX
T1
TVS
+
–
–
0.1μF
TX
C1
2
3
100V
+
TO PHY
RX
BR1
BR2
PD
–
LOAD
RX
6
36V
GND
LTC4265
SHDN
100k
10k
+
–
SPARE
+
–
4
5
7
8
10k
SPARE
V
V
OUT
IN
+
ISOLATED
WALL
TRANSFORMER
D1
–
4265 F10
Figure 10. Auxiliary Power Dominant PD Interface
4265f
16
LTC4265
APPLICATIONS INFORMATION
IEEE 802.3at SYSTEM POWER-UP REQUIREMENT
LAYOUT CONSIDERATION FOR THE LTC4265
UndertheIEEE802.3atstandard,aPDmustoperateunder
12.95 Watts in accordance with IEEE 802.3af standards
until it recognizes a Type-2 PSE. Initializing PD operation
in 12.95-Watt mode eliminates interoperability issue in
case a Type-2 PD is connects to a Type-1 PSE. Once the
PD recognizes a Type-2 PSE, the IEEE 802.3at standard
requires the PD to wait 80ms in 12.95W operation before
25.5W operation can commence.
The LTC4265 is relatively immune to layout problems.
Here are some recommendations.
Avoid excessive parasitic capacitance on the R
pin
CLASS
close to the LTC4265.
and place resistor R
CLASS
Connect the LTC4265 exposed pad to a PC board heat
sink. Make the heat sink as large as possible.
Place the input capacitor and transient voltage suppres-
sor (C14 and D3 in Figure 7) as close to the LTC4265 as
possible.
MAINTAIN POWER SIGNATURE
In an IEEE 802.3af/at system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
requirepower.TheMPSrequiresthePDtoperiodicallydraw
at least 10mA and also have an AC impedance less than
26.25k in parallel with 0.05ꢁF. If one of these conditions
is not met, the PSE may disconnect power to the PD.
If using the SHDN pin for auxiliary power application,
separate the SHDN pin from other high voltage connec-
tions, like GND and V , to avoid leakage and capacitive
OUT
coupling shutting down the LTC4265.
4265f
17
LTC4265
APPLICATIONS INFORMATION
O U T P U T ( V )
E F F I C I E N C Y ( % )
4265f
18
LTC4265
PACKAGE DESCRIPTION
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev C)
0.70 p0.05
3.30 p0.05
3.60 p0.05
2.20 p0.05
1.70 p 0.05
PACKAGE OUTLINE
0.25 p 0.05
0.50 BSC
2.50 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.40 p 0.10
4.00 p0.10
(2 SIDES)
R = 0.115
TYP
7
12
R = 0.05
TYP
3.30 p0.10
3.00 p0.10
(2 SIDES)
1.70 p 0.10
PIN 1
TOP MARK
(NOTE 6)
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
CHAMFER
(UE12/DE12) DFN 0806 REV D
6
1
0.25 p 0.05
0.75 p0.05
0.200 REF
0.50 BSC
2.50 REF
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4265f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC4265
TYPICAL APPLICATION
PoE-Based Self-Driven Synchronous Forward Power Supply
1mH
DO1608C-105
BAS516
PA2431NL
•
6.8μH
PG0702.682
18V
PDZ18B
BAS516
5V
5A
GND
•
10μH
+
220μF
6.3V
5.1ꢀ
•
+
4.7nF
250V
2.2μF
100V
10μF
100V
PSLVOJ227M(12)
33k
B1100 s 8 PLCS
IRF6217
V
CC
0.1μF
1nF
1nF
FDS2582
–54V
FROM
DATA
PAIR
10μF
16V
FDS8880
FDS8880
5.1ꢀ
5.1ꢀ
10k
BAS516
133ꢀ
2.2nF
2kV
BAS516
50mΩ
237k
V
S
OUT
OUT
IN
4.7nF
10nF
2k
OC
1.5k
33k
–54V
FROM
SPARE
PAIR
LTC4265
ISENSE
COMP
V
CC
PS2801-1-L
22k
GND
SMAJ58A
30.9ꢀ
BC857BF
0.1μF
LT1952
R
CLASS
SHDN
FB
0.1μF
100V
SD_VSEC
VREF
V
V
OUT
IN
SS_MAXDC
ROSC
1.2k
11.3k
3.65k
22.1k
PGND GND BLANK
DELAY
T2PSE
TLV431A
10.0k
82k
158k
332k
158k
0.22μF
GND
100pF
Efficiency vs Load Current
95
90
85
5V
51k
20k
T2P (TO MICROCONTROLLER)
80
75
PS22801-1-L
4265 TA03a
42V
50V
57V
70
65
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
LOAD (A)
4265 TA03b
RELATED PARTS
PART NUMBER
DESCRIPTION
Single Switch Synchronous Forward Controller
COMMENTS
LT1952
LT1952-1
Adjustable Switching Frequency, Programmable Undervoltage Lockout,
Optional Burst Mode® Operation at Light Load
LTC3805
LTC3825
Adjustable Frequency Current Mode Flyback Controller
Slope Comp Overcurrent Protect, Internal/External Clock
Isolate No-Opto Synchronous Flyback Controller with
Wide Input Supply Range
Adjustable Switching Frequency, Programmable Undervoltage Lockout,
Accurate Regulation without Trim, Synchronous for High Efficiency.
LTC4257-1
LTC4258
IEEE 802.3af PD Interface Controller
100V 400mA Internal Switch, Programmable Classification Current Limit
Quad IEEE 802.3af Power over Ethernet Controller
DC Disconnect Only, IEEE-Compliant PD Detection and Classification,
2
Autonomous Operation or I C Control
LTC4259A-1
Quad IEEE 802.3af Power over Ethernet PSE Controller
with AC Disconnect
AC or DC Disconnect IEEE-Compliant PD Detection and Classification,
2
Autonomous Operation or I C Control
2
LTC4263/LTC4263-1 Single IEEE 802.3af Power over Ethernet Controller
Internal Switch, Autonomous Operation or I C Control. 15.4W or 30W.
LTC4264
High Power PD Interface Controller with 750mA
Current Limit
750mA Internal Switch, Programmable Classification Current Limit
with disable, Complementary Power Good
LTC4267
LTC4267-1
LTC4267-3
IEEE 802.3af PD Interface with Integrated Switching
Regulator
100V 400mA Internal Switch, Programmable Classification, 200KHz
or 300KHz Constant Frequency PWM, Interface and Switcher Optimized
for IEEE-Compliant PD System.
LTC4268-1
High Power PD with Synchronous No Opto Flyback
Controller
750mA Internal Switch, Programmable Class, Current Limit, Synchronous
Programmable Switching Frequency and UVLO, High Efficiency
ThinSOT is a trademark of Linear Technology Corporation.
4265f
LT 1208 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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