LTC4266AIUHF-2#PBF [Linear]
LTC4266A/LTC4266C - Quad PoE/PoE+/LTPoE++ PSE Controller; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C;型号: | LTC4266AIUHF-2#PBF |
厂家: | Linear |
描述: | LTC4266A/LTC4266C - Quad PoE/PoE+/LTPoE++ PSE Controller; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C |
文件: | 总32页 (文件大小:380K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC4266A/LTC4266C
++
+
Quad PoE/PoE /LTPoE
PSE Controller
FeAtures
Description
n
Four Independent PSE Channels
The LTC®4266A is a quad power sourcing equipment (PSE)
n
++
controller capable of delivering up to 90W of LTPoE
++
Compliant with IEEE 802.3at Type 1 and 2
n
power to a compatible LTPoE powered device (PD). A
Low Power Dissipation
n
proprietary detection/classification scheme allows mutual
0.25Ω Sense Resistance Per Channel
++
++
n
identification between a LTPoE PSE and LTPoE PD
while remaining compatible and interoperable with exist-
ing Type 1 (13W) and Type 2 (25.5W) PDs. The LTC4266A
feature set is a superset of the popular LTC4266. These
Very High Reliability 4-Point PD Detection
n
2-Point Forced Voltage
2-Point Forced Current
n
n
n
n
n
n
High Capacitance Legacy Device Detection
2
PSE controllers feature low R external MOSFETs and
ON
1MHz I C Compatible Serial Control Interface
0.25Ω sense resistors which are especially important at
Midspan Backoff Timer
++
the LTPoE current levels to maintain the lowest possible
Supports 2-Pair and 4-Pair Output Power
heat dissipation.
Available in Multiple Power Grades
n
++™
++
++
LTC4266A-1: LTPoE
38.7W
The LTC4266C targets fully automatic PSE systems pow-
ering Type 1 (up to 13W) PDs.
n
n
n
n
LTC4266A-2: LTPoE 52.7W
LTC4266A-3: LTPoE 70W
Advanced power management features include: 14-bit
current monitoring ADCs, DAC-programmable current
limit, and versatile quick shutdown of preselected ports.
Advanced power management host software is available
under a no-cost license. PD discovery uses a proprietary
dual-mode 4-point detection mechanism ensuring excel-
lent immunity from false PD detection. The LTC4266
++
LTC4266A-4: LTPoE 90W
LTC4266C: PoE 13W
n
Available in 38-Lead 5mm × 7mm QFN Package
ApplicAtions
n
++
LTPoE PSE Switches/Routers
2
includes an I C serial interface operable up to 1MHz.
n
n
n
++
LTPoE PSE Midspans
IEEE 802.3at Type 1 PSE Switches/Routers
IEEE 802.3at Type 1 PSE Midspans
The LTC4266 is available in multiple power grades allow-
ing delivered PD power of 13W, 25.5W, 38.7W, 52.7W,
70W and 90W. These controllers are available in a 38-lead
5mm × 7mm QFN package.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
++
LTPoE and ThinSOT are trademarks of Analog Devices, Inc. All other trademarks are the
property of their respective owners.
typicAl ApplicAtion
Complete 4-Port Ethernet High Power Source
10Ω
AD0 AD1 AD2 AD3 SHDN1 SHDN2 SHDN3 SHDN4 AUTO MSD RESET MID SDAIN SCL
3.3V
V
DD
0.1µF
SDAOUT
SMAJ5.0A
10µF
+
+
INT
DGND
AGND
LTC4266
0.22µF 100V
S1B
×4
S1B
×4
10Ω
×4
–54V
V
SENSE1 GATE1 OUT1 SENSE2 GATE2 OUT2 SENSE3 GATE3 OUT3 SENSE4 GATE4 OUT4
EE
SMAJ58A
1µF
C
BULK
–54V
100V
TVS
BULK
PORT1
PORT2
PORT3
PORT4
4266AC TA01
4266acfe
1
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
Absolute MAxiMuM rAtings
pin conFigurAtion
Supply Voltages (Note 1)
TOP VIEW
AGND – V ........................................... –0.3V to 80V
EE
DGND – V ........................................... –0.3V to 80V
EE
V
– DGND ......................................... –0.3V to 5.5V
DD
38 37 36 35 34 33 32
Digital Pins
SDAOUT
NC
1
2
3
4
5
6
7
8
9
31 GATE1
SCL, SDAIN, SDAOUT, INT, SHDNn, MSD, ADn,
RESET, AUTO, MID........... DGND –0.3V to V + 0.3V
30 SENSE1
SDAIN
AD3
OUT2
29
28
DD
GATE2
Analog Pins
AD2
27 SENSE2
GATEn, SENSEn, OUTn .......... V –0.3V to V + 80V
EE
EE
AD1
V
V
26
25
EE
EE
Operating Temperature Range
V
EE
AD0
39
LTC4266I .............................................–40°C to 85°C
Junction Temperature (Note 2) ............................. 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
DNC
NC
24 OUT3
23 GATE3
22 SENSE3
21 OUT4
DGND 10
NC 11
20
NC 12
GATE4
13 14 15 16 17 18 19
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
EXPOSED PAD IS V (PIN 39) MUST BE SOLDERED TO PCB
EE
JMAX
T
= 125°C, θ = 34°C/W
JA
orDer inForMAtion http://www.linear.com/product/LTC4266A#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
4266C 38-Lead (5mm × 7mm) Plastic QFN
MAX PWR TEMPERATURE RANGE
LTC4266CIUHF#PBF
LTC4266CIUHF#TRPBF
13W
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
LTC4266AIUHF-1#PBF LTC4266AIUHF-1#TRPBF 4266A1
LTC4266AIUHF-2#PBF LTC4266AIUHF-2#TRPBF 4266A2
LTC4266AIUHF-3#PBF LTC4266AIUHF-3#TRPBF 4266A3
LTC4266AIUHF-4#PBF LTC4266AIUHF-4#TRPBF 4266A4
38-Lead (5mm × 7mm) Plastic QFN
38-Lead (5mm × 7mm) Plastic QFN
38-Lead (5mm × 7mm) Plastic QFN
38-Lead (5mm × 7mm) Plastic QFN
38.7W
52.7W
70W
90W
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
4266acfe
2
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
electricAl chArActeristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V
unless otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
EE
Main PoE Supply Voltage
AGND – V
EE
l
l
l
For IEEE Type 1 Compliant Output
For IEEE Type 2 Compliant Output
45
51
54.75
57
57
57
V
V
V
++
For LTPoE Compliant Output
l
l
l
l
l
l
Undervoltage Lockout
AGND – V
20
25
3.3
2.2
30
V
V
EE
V
V
DD
Supply Voltage
V – DGND
DD
3.0
4.3
DD
Undervoltage Lockout
V
Allowable Digital Ground Offset
DGND – V
25
57
–5
3
V
EE
I
I
V
V
Supply Current
Supply Current
(AGND – V ) = 55V
–2.4
1.1
mA
mA
EE
EE
EE
(V – DGND) = 3.3V
DD
DD
DD
Detection
l
l
Detection Current – Force Current
Detection Voltage – Force Voltage
First Point, AGND – V
= 9V
OUTn
220
140
240
160
260
180
µA
µA
OUTn
Second Point, AGND – V
= 3.5V
AGND – V
, 5µA ≤ I
OUTn
≤ 500µA
OUTn
l
l
First Point
Second Point
7
3
8
4
9
5
V
V
l
l
l
l
l
Detection Current Compliance
Detection Voltage Compliance
Detection Voltage Slew Rate
AGND – V
= 0V
0.8
0.9
12
mA
V
OUTn
V
OC
AGND – V
AGND – V
, Open Port
, C = 0.15µF
10.4
OUTn
0.01
18.5
32
V/µs
kΩ
kΩ
OUTn PORT
Minimum Valid Signature Resistance
Maximum Valid Signature Resistance
15.5
27.5
17
29.7
Classification
l
l
V
Classification Voltage
AGND – V
, 0mA ≤ I ≤ 50mA
CLASS
16.0
53
20.5
67
V
CLASS
OUTn
Classification Current Compliance
Classification Threshold Current
V
OUTn
= AGND
61
mA
l
l
l
l
l
Class 0 – 1
Class 1 – 2
Class 2 – 3
Class 3 – 4
Class 4 – Overcurrent
AGND – V , 0.1mA ≤ I ≤ 10mA
CLASS
5.5
6.5
14.5
23
33
48
7.5
mA
mA
mA
mA
mA
13.5
21.5
31.5
45.2
15.5
24.5
34.9
50.8
l
l
V
MARK
Classification Mark State Voltage
Mark State Current Compliance
7.5
53
9
10
67
V
OUTn
V
OUTn
= AGND
61
mA
Gate Driver
l
l
GATE Pin Pull-Down Current
Port Off, V
Port Off, V
= V + 5V
0.4
mA
mA
GATEn
GATEn
EE
= V + 1V
0.08
0.12
30
EE
GATE Pin Fast Pull-Down Current
GATE Pin On Voltage
V
GATEn
GATEn
= V + 5V
mA
V
EE
l
V
– V , I
= 1µA
8
12
14
EE GATEn
Output Voltage Sense
l
l
V
PG
Power Good Threshold Voltage
V
– V
EE
2
2.4
2.8
V
OUTn
OUT Pin Pull-Up Resistance to AGND
0V ≤ (AGND – V
) ≤ 5V
OUTn
300
500
700
kΩ
4266acfe
3
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
electricAl chArActeristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V
unless otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Current Sense
V
CUT
Overcurrent Sense Voltage
V
– V
SENSEn EE
hpen = 0Fh, cutn[5:0] ≥ 4 (Note 12)
cutrng = 0
l
l
9
4.5
9.38
4.69
9.75
4.88
mV/LSB
mV/LSB
cutrng = 1
l
l
l
l
Overcurrent Sense in AUTO Pin Mode
Class 0, Class 3
Class 1
90
26
94
28
98
30
mV
mV
mV
mV
Class 2
49
52
55
Class 4
152
159
166
V
LIM
V
LIM
V
LIM
Active Current Limit in 802.3af Compliant
Mode
V
EE
– V , hpen = 0Fh, limn = 80h,
SENSEn EE
V
= 55V (Note 12)
l
l
V
< V
< AGND – 29V
OUT
102
20
106
110
50
mV
mV
EE
OUT
AGND – V
= 0V
Active Current Limit in High Power Mode
Active Current Limit in AUTO Pin Mode
hpen = 0Fh, limn = C0h, V = 55V
EE
l
l
l
V
V
– V = 0V to 10V
204
100
20
212
106
221
113
50
mV
mV
mV
OUT
EE
EE
+ 23V < V
< AGND – 29V
OUT
AGND – V
= 0V
OUT
V
OUT
– V = 0V to 10V, V = 55V
EE EE
Class 0 to Class 3
Class 4
l
l
102
204
106
212
110
221
mV
mV
l
l
V
V
DC Disconnect Sense Voltage
Short-Circuit Sense
V
V
– V , rdis = 0
2.6
1.3
3.8
1.9
4.8
mV
mV
MIN
SENSEn
SENSEn
EE
– V , rdis = 1
2.41
EE
l
l
V
V
– V – V , rdis = 0
160
75
200
100
255
135
mV
mV
SC
SENSEn
SENSEn
EE
LIM
– V – V , rdis = 1
EE
LIM
Port Current ReadBack
Resolution
No Missing Codes, fast_iv = 0
V – V
SENSEn
14
30.5
30
Bits
µV/LSB
dB
LSB Weight
EE
50Hz to 60Hz Noise Rejection
(Note 7)
Port Voltage ReadBack
Resolution
No Missing Codes, fast_iv = 0
14
5.835
30
bits
mV/LSB
dB
LSB Weight
AGND – V
(Note 7)
OUTn
50Hz to 60Hz Noise Rejection
Digital Interface
l
V
Digital Input Low Voltage
ADn, RESET, MSD, SHDNn, AUTO, MID
0.8
0.8
V
ILD
(Note 6)
2
l
l
I C Input Low Voltage
SCL, SDAIN (Note 6)
(Note 6)
V
V
V
Digital Input High Voltage
Digital Output Low Voltage
2.2
IHD
l
l
I
I
= 3mA, I = 3mA
0.4
0.7
V
V
SDAOUT
SDAOUT
INT
= 5mA, I = 5mA
INT
Internal Pull-Up to V
ADn, SHDNn, RESET, MSD
50
50
kΩ
kΩ
DD
Internal Pull-Down to DGND
AUTO, MID
4266acfe
4
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
electricAl chArActeristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V
unless otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Timing Characteristics
l
l
t
t
Detection Time
Detection Delay
Beginning to End of Detection (Note 7)
270
300
290
310
470
ms
ms
DET
From PD Connected to Port to Detection
Complete (Note 7)
DETDLY
l
l
l
l
l
t
t
t
t
t
Class Event Duration
(Note 7)
12
ms
ms
ms
ms
ms
CLE
Class Event Turn-On Duration
Mark Event Duration
C
PORT
= 0.6µF (Note 7)
0.1
60
CLEON
ME
(Notes 7, 11)
(Notes 7, 11)
8.6
22
Last Mark Event Duration
Power On Delay in AUTO Pin Mode
16
15
MEL
PON
From End of Valid Detect to Application of
Power to Port (Note 7)
l
Turn On Rise Time
(AGND – V ): 10% to 90% of (AGND – V ),
24
µs
OUT
EE
C
PORT
= 0.15µF (Note 7)
l
l
l
l
Turn On Ramp Rate
C
= 0.15µF (Note 7)
10
V/µs
PORT
Fault Delay
From I
Fault to Next Detect
1.0
2.3
1.0
1.1
2.5
1.3
s
s
s
CUT
Midspan Mode Detection Backoff
Power Removal Detection Delay
Rport = 15.5kΩ (Note 7)
2.7
2.5
From Power Removal After t to Next
Detect (Note 7)
DIS
l
l
l
t
t
t
Maximum Current Limit Duration During Port (Note 7)
Start-Up
52
62.5
11.9
62.5
6.3
66
ms
ms
ms
START
Maximum Current Limit Duration After Port
Start-Up
t
Enable = 1 (Notes 7, 12)
LIM
LIM
Maximum Overcurrent Duration After Port
Start-Up
(Note 7)
52
66
CUT
l
l
Maximum Overcurrent Duty Cycle
(Note 7)
5.8
1.6
6.7
3.6
%
t
Maintain Power Signature (MPS) Pulse Width Current Pulse Width to Reset Disconnect
Sensitivity Timer (Notes 7, 8)
ms
MPS
l
l
l
l
l
l
l
t
t
t
Maintain Power Signature (MPS) Dropout Time (Note 7)
320
350
2
380
6.5
6.5
3
ms
µs
µs
s
DIS
Masked Shut Down Delay
(Note 7)
(Note 7)
MSD
SHDN
Port Shut Down Delay
2
I C Watchdog Timer Duration
1.5
3
Minimum Pulse Width for Masked Shut Down (Note 7)
µs
µs
µs
Minimum Pulse Width for SHDN
Minimum Pulse Width for RESET
(Note 7)
(Note 7)
3
4.5
4266acfe
5
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
electricAl chArActeristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless
otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C Timing
l
l
l
l
l
Clock Frequency
Bus Free Time
Start Hold Time
SCL Low Time
SCL High Time
Data Hold Time
(Note 7)
1
MHz
ns
t
1
t
2
t
3
t
4
t
5
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
480
240
480
240
60
ns
ns
ns
l
l
Figure 5 (Notes 7, 9) Data into Chip
Data Out of Chip
ns
ns
120
l
l
l
l
l
l
l
l
l
t
t
t
t
t
Data Set-Up Time
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
(Notes 7, 9, 10)
80
ns
ns
ns
ns
ns
ns
µs
µs
ns
6
7
8
r
Start Set-Up Time
240
240
Stop Set-Up Time
SCL, SDAIN Rise Time
SCL, SDAIN Fall Time
Fault Present to INT Pin Low
Stop Condition to INT Pin Low
ARA to INT Pin High Time
SCL Fall to ACK Low
120
60
f
150
1.5
1.5
120
(Notes 7, 9, 10)
(Notes 7, 9)
(Notes 7, 9)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 140°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative.
Note 4: The LTC4266A/LTC4266C operates with a negative supply voltage
(with respect to ground). To avoid confusion, voltages in this data sheet
are referred to in terms of absolute magnitude.
Note 6: The LTC4266A/LTC4266C digital interface operates with respect to
DGND. All logic levels are measured with respect to DGND.
Note 7: Guaranteed by design, not subject to test.
Note 8: The IEEE 802.3af specification allows a PD to present its
Maintain Power Signature (MPS) on an intermittent basis without being
disconnected. In order to stay powered, the PD must present the MPS for
t
within any t
time window.
MPS
MPDO
Note 9: Values measured at V
Note 10: If fault condition occurs during an I C transaction, the INT pin
will not be pulled down until a stop condition is present on the I C bus.
and V
.
ILD(MAX)
IHD(MIN)
2
2
Note 11: Load Characteristic of the LTC4266A/LTC4266C during Mark:
7V < (AGND – V
) < 10V or I
< 50µA
OUTn
OUT
Note 12: See the LTC4266A/LTC4266C Software Programming
documentation for information on serial bus usage and device
configuration and status registers.
Note 5: t is the same as t
defined by IEEE 802.3at.
DIS
MPDO
4266acfe
6
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
typicAl perForMAnce chArActeristics
Power-On Sequence in
802.3af Classification in
AUTO Pin Mode
AUTO Pin Mode
Powering Up into a 180µF Load
10
0
GND
GND
FORCED CURRENT DETECTION
GND
V
DD
V
EE
= 3.3V
= –54V
PORT
VOLTAGE
20V/DIV
LOAD
FULLY
–10
–20
–30
CHARGED
–18.4
FORCED VOLTAGE
DETECTION
V
EE
PORT
CURRENT
802.3af
PORT 1
PORT 1
FOLDBACK
PORT
VOLTAGE
10V/DIV
425mA
CURRENT LIMIT
CLASSIFICATION
V
DD
V
EE
= 3.3V
= –54V
200 mA/DIV
V
DD
V
EE
= 3.3V
= –55V
–40
–50
–60
–70
POWER ON
0mA
PD IS CLASS 1
FET ON
GATE
VOLTAGE
10V/DIV
V
EE
V
V
EE
EE
4266AC G02
4266AC G03
5ms/DIV
5ms/DIV
100ms/DIV
4266AC G01
2-Event Classification in
AUTO Pin Mode
Classification Transient Response
to 40mA Load Step
Classification Current Compliance
0
V
DD
V
EE
= 3.3V
= –54V
GND
V
DD
V
EE
= 3.3V
= –54V
–2
–4
40mA
0mA
PORT
CURRENT
20mA/DIV
T
A
= 25°C
–6
–17.6
1ST CLASS EVENT
–8
2ND CLASS EVENT
–10
–12
–14
–16
–18
–20
PORT
VOLTAGE
10V/DIV
PORT 1
V
DD
V
EE
= 3.3V
= –55V
PORT
VOLTAGE
1V/DIV
PD IS CLASS 4
–20V
V
EE
4266AC G05
4266AC G04
0
10
20
30
40
50
60
70
50µs/DIV
10ms/DIV
CLASSIFICATION CURRENT (mA)
4266AC G06
802.3at ILIM Threshold
vs Temperature
V
DD Supply Current vs Voltage
VEE Supply Current vs Voltage
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
215
214
213
212
211
210
860
856
852
848
844
840
2.4
2.3
2.2
2.1
V
V
= 3.3V
= –54V
SENSE
DD
EE
R
= 0.25Ω
REG 48h = C0h
25°C
85°C
–40°C
25°C
85°C
–40°C
2.0
–40
0
40
–80
120
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3
SUPPLY VOLTAGE (V)
–60 –55 –50 –45 –40 –35 –30 –25 –20
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
V
DD
V
EE
4266AC G09
4266AC G07
4266 G08
4266acfe
7
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
typicAl perForMAnce chArActeristics
802.3af ILIM Threshold
vs Temperature
802.3at ICUT Threshold
vs Temperature
108.00
107.25
106.50
432
429
163
162
652
648
644
640
V
V
= 3.3V
= –54V
SENSE
V
V
= 3.3V
= –54V
SENSE
DD
EE
DD
EE
R
= 0.25Ω
R
= 0.25Ω
REG 48h = 80h
PORT 1
REG 47h = E2h
PORT 1
161
160
159
158
426
423
420
105.75
105.00
636
630
–40
0
40
80
120
–40
0
40
80
120
TEMPERATURE (°C)
TEMPERATURE (°C)
4266AC G10
4266AC G11
802.3af ICUT Threshold
vs Temperature
DC Disconnect Threshold
vs Temperature
8.00
7.75
7.50
7.25
7.00
96.00
95.25
94.50
93.75
93.00
384
381
2.0000
1.9375
V
V
= 3.3V
= –54V
SENSE
V
V
= 3.3V
= –54V
SENSE
DD
EE
DD
EE
R
= 0.25Ω
R
= 0.25Ω
REG 47h = D4h
PORT 1
REG 47h = E2h
PORT 1
378
375
372
1.8750
1.8125
1.7500
–40
0
40
80
120
–40
0
40
80
120
TEMPERATURE (°C)
TEMPERATURE (°C)
4266AC G12
4266AC G13
ADC Noise Histogram
Current Readback in Fast Mode
ADC Integral Nonlinearity
Current Limit Foldback
Current Readback in Fast Mode
1.0
0.5
900
800
700
600
500
400
300
200
100
0
225
400
350
300
250
200
V
– V = 110.4mV
EE
V
EE
R
= 3.3V
SENSEn
DD
V
= –54V
200
175
150
125
100
75
= 0.25Ω
SENSE
REG 48h = C0h
0
150
100
50
–0.5
–1.0
50
25
0
0
0
50 100 150 200 250 300 350 400 450 500
CURRENT SENSE RESISTOR INPUT VOLTAGE (mV)
4266AC G16
–54
–45
–36
–9
0
191
192
193
ADC OUTPUT
196
–27
–18
194
195
V
OUTn
(V)
4266AC G14
4266AC G15
4266acfe
8
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
typicAl perForMAnce chArActeristics
ADC Noise Histogram
ADC Integral Nonlinearity
ADC Noise Histogram Port
Voltage Readback in Fast Mode
600
Current Readback in Slow Mode
Current Readback in Slow Mode
300
250
200
150
100
50
1.0
0.5
V
– V = 110.4mV
EE
AGND – V
= 48.3V
SENSEn
OUTn
500
400
300
200
100
0
0
–0.5
–1.0
0
6139
0
50 100 150 200 250 300 350 400 450 500
CURRENT SENSE RESISTOR INPUT VOLTAGE (mV)
4266AC G18
260
261
262
ADC OUTPUT
6141
6143
6145
6147
263
264
265
ADC OUTPUT
4266AC G17
4266AC G19
ADC Integral Nonlinearity
Voltage Readback in Fast Mode
ADC Noise Histogram Port
ADC Integral Nonlinearity
Voltage Readback in Slow Mode
Voltage Readback in Slow Mode
1.0
0.5
600
500
400
300
200
100
0
1.0
0.5
AGND – V
= 48.3V
OUTn
0
0
–0.5
–1.0
–0.5
–1.0
0
10
20
30
40
50
60
0
10
20
30
40
50
60
8532
8533
8534
ADC OUTPUT
8535
8536
PORT VOLTAGE (V)
PORT VOLTAGE (V)
4266AC G20
4266AC G22
4266AC G21
INT and SDAOUT Pull-Down
Voltage vs Load Current
MOSFET Gate Drive with Fast
Pull-Down
3
2.5
2
GND
V
V
= 3.3V
DD
EE
= –54V
PORT
VOLTAGE
20V/DIV
V
V
EE
EE
FAST PULL-DOWN
1.5
1
GATE
VOLTAGE
10V/DIV
CURRENT LIMIT
50Ω
FAULT
APPLIED
PORT
CURRENT
500mA/DIV
0.5
0
50Ω FAULT REMOVED
0mA
4266AC G24
0
5
10
LOAD CURRENT (mA)
15 20 25 30 35 40
100µs/DIV
4266AC G23
4266acfe
9
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
test tiMing DiAgrAMs
t
CLASSIFICATION
DET
FORCED-
VOLTAGE
FORCED-CURRENT
0V
t
ME
V
t
PORTn
MEL
V
OC
V
MARK
15.5V
20.5V
V
CLASS
t
CLE
t
CLE
PD
CONNECTED
t
CLEON
t
PON
V
EE
INT
4266AC F01
Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-Auto Modes
V
LIM
V
CUT
V
TO V
EE
SENSEn
0V
t
, t
START ICUT
INT
4266AC F02
Figure 2. Current Limit Timing
V
SENSEn
V
MIN
TO V
EE
INT
t
t
DIS
MPS
4266AC F03
Figure 3. DC Disconnect Timing
4266acfe
10
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
test tiMing DiAgrAMs
V
GATEn
t
MSD
V
EE
t
SHDN
MSD or
SHDNn
4266AC F04
Figure 4. Shut Down Delay Timing
t
3
t
r
t
4
t
f
SCL
SDA
t
5
t
t
7
t
t
6
8
2
t
1
4266AC F05
Figure 5. I2C Interface Timing
4266acfe
11
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
i2c tiMing DiAgrAMs
4266acfe
12
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
i2c tiMing DiAgrAMs
SCL
SDA
0
1
0
AD3 AD2 AD1 AD0 R/W
FRAME 1
ACK
D7 D6 D5 D4 D3 D2 D1 D0
ACK
STOP BY
MASTER
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 2
DATA BYTE
SERIAL BUS ADDRESS BYTE
4266AC F08
Figure 8. Reading the Interrupt Register (Short Form)
SCL
SDA
0
0
0
1
1
0
0
R/W
ACK
0
1
0
AD3 AD2 AD1 AD0
1
ACK
STOP BY
MASTER
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 1
ALERT RESPONSE ADDRESS BYTE
FRAME 2
SERIAL BUS ADDRESS BYTE
4266AC F09
Figure 9. Reading from Alert Response Address
4266acfe
13
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
pin Functions
RESET: Chip Reset, Active Low. When the RESET pin is
low, the LTC4266A/LTC4266C is held inactive with all
ports off and all internal registers reset to their power-
up states. When RESET is pulled high, the LTC4266A/
LTC4266C begins normal operation. RESET can be con-
nected to an external capacitor or RC network to provide
a power turn-on delay. Internal filtering of the RESET pin
prevents glitches less than 1µs wide from resetting the
AD3: Address Bit 3. Tie the address pins high or low to set
2
the I C serial address to which the LTC4266A/LTC4266C
responds. This address will be 010A A A A b. Internally
3 2 1 0
pulled up to V .
DD
AD2: Address Bit 2. See AD3.
AD1: Address Bit 1. See AD3.
AD0: Address Bit 0. See AD3.
LTC4266A/LTC4266C. Internally pulled up to V .
DD
NC, DNC: All pins identified with “NC” or “DNC” must be
left unconnected.
MID: Midspan Mode Input. When high, the LTC4266A/
LTC4266C acts as a midspan device. Internally pulled
down to DGND.
DGND: Digital Ground. DGND is the return for the V
supply.
DD
INT: Interrupt Output, Open Drain. INT will pull low
when any one of several events occur in the LTC4266A/
LTC4266C. It will return to a high impedance state when
bits 6 or 7 are set in the Reset PB register (1Ah). The INT
signal can be used to generate an interrupt to the host
processor, eliminating the need for continuous software
polling. Individual INT events can be disabled using the
Int Mask register (01h). See the LTC4266A/LTC4266C
Software Programming documentation for more informa-
tion. The INT pin is only updated between I2C transactions.
VDD: Logic Power Supply. Connect to a 3.3V power supply
relative to DGND. V must be bypassed to DGND near
DD
the LTC4266A/LTC4266C with at least a 0.1µF capacitor.
SHDN1: Shutdown Port 1, Active Low. When pulled low,
SHDN1 shuts down port 1, regardless of the state of
the internal registers. Pulling SHDN1 low is equivalent
to setting the Reset Port 1 bit in the Reset Pushbutton
register (1Ah). Internal filtering of the SHDN1 pin pre-
vents glitches less than 1µs wide from resetting the port.
Internally pulled up to V .
DD
SCL: Serial Clock Input. High impedance clock input for
2
the I C serial interface bus. SCL must be tied high if not
SHDN2: Shutdown Port 2, Active Low. See SHDN1.
SHDN3: Shutdown Port 3, Active Low. See SHDN1.
SHDN4: Shutdown Port 4, Active Low. See SHDN1.
used.
SDAOUT: Serial Data Output, Open Drain Data Output for
the I2C Serial Interface Bus. The LTC4266A/LTC4266C
uses two pins to implement the bidirectional SDA function
AGND: Analog Ground. AGND is the return for the V
EE
2
to simplify opto-isolation of the I C bus. To implement a
supply.
standard bidirectional SDA pin, tie SDAOUT and SDAIN
together. SDAOUT should be grounded or left floating if
not used. See the Applications Information section for
more information.
SENSE4: Port 4 Current Sense Input. SENSE4 monitors
the external MOSFET current via a 0.5Ω or 0.25Ω sense
resistor between SENSE4 and V . Whenever the voltage
EE
across the sense resistor exceeds the overcurrent detec-
SDAIN: Serial Data Input. High impedance data input for
the I2C serial interface bus. The LTC4266A/LTC4266C
uses two pins to implement the bidirectional SDA function
tion threshold V , the current limit fault timer counts up.
CUT
If the voltage across the sense resistor reaches the cur-
rent limit threshold V , the GATE4 pin voltage is lowered
to maintain constantLcIMurrent in the external MOSFET. See
the Applications Information section for further details. If
2
to simplify opto-isolation of the I C bus. To implement a
standard bidirectional SDA pin, tie SDAOUT and SDAIN
together. SDAIN must be tied high if not used. See the
Applications Information section for more information.
the port is unused, the SENSE4 pin must be tied to V .
EE
4266acfe
14
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
pin Functions
GATE4: Port 4 Gate Drive. GATE4 should be connected
to the gate of the external MOSFET for port 4. When the
MOSFET is turned on, the gate voltage is driven to 12V
(typ) above VEE. During a current limit condition, the
voltage at GATE4 will be reduced to maintain constant
current through the external MOSFET. If the fault timer
expires, GATE4 is pulled down, turning the MOSFET off
SENSE2: Port 2 Current Sense Input. See SENSE4.
GATE2: Port 2 Gate Drive. See GATE4.
OUT2: Port 2 Output Voltage Monitor. See OUT4.
SENSE1: Port 1 Current Sense Input. See SENSE4.
GATE1: Port 1 Gate Drive. See GATE 4.
and recording a t
or t
event. If the port is unused,
OUT1: Port 1 Output Voltage Monitor. See OUT4.
CUT
START
float the GATE4 pin.
AUTO: AUTO Pin Mode Input. AUTO pin mode allows
the LTC4266A/LTC4266C to detect and power up a PD
even if there is no host controller present on the I2C
bus. The voltage of the AUTO pin determines the state
of the internal registers when the LTC4266A/LTC4266C
OUT4: Port 4 Output Voltage Monitor. OUT4 should be
connected to the output port. A current limit foldback
circuit limits the power dissipation in the external MOSFET
by reducing the current limit threshold when the drain-to-
source voltage exceeds 10V. The port 4 Power Good bit is
is reset or comes out of V UVLO (see the LTC4266A/
DD
set when the voltage from OUT4 to V drops below 2.4V
LTC4266C Software Programming documentation). The
states of these register bits can subsequently be changed
EE
(typ). A 500k resistor is connected internally from OUT4
to AGND when the port is idle. If the port is unused, OUT4
pin must be floated.
2
via the I C interface. The real-time state of the AUTO pin
is read at bit 0 in the Pin Status register (11h). Internally
pulled down to DGND. Must be tied locally to either V
or DGND.
DD
SENSE3: Port 3 Current Sense Input. See SENSE4.
GATE3: Port 3 Gate Drive. See GATE4.
MSD: Maskable Shutdown Input. Active low. When pulled
low, all ports that have their corresponding mask bit set
in the Misc Config register (17h) will be reset, equivalent
to pulling the SHDN pin low. Internal filtering of the MSD
pin prevents glitches less than 1µs wide from resetting
OUT3: Port 3 Output Voltage Monitor. See OUT4.
VEE: Main Supply Input. Connect to a –45V to –57V
supply, relative to AGND.
ports. Internally pulled up to V .
DD
4266acfe
15
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
operAtion
Overview
LTC4266 Product Family
The LTC4266 is a third-generation quad PSE controller
that implements four PSE ports in either an end-point
or midspan design. Virtually all necessary circuitry is
included to implement an IEEE 802.3at compliant PSE
design, requiring only an external power MOSFET and
sense resistor per channel; these minimize power loss
compared to alternative designs with on-board MOSFETs
and increase system reliability in the event a single chan-
nel fails.
Power over Ethernet, or PoE, is a standard protocol for
sending DC power over copper Ethernet data wiring.
The IEEE group that administers the 802.3 Ethernet data
standards added PoE powering capability in 2003. This
original PoE spec, known as 802.3af, allowed for 48V DC
power at up to 13W. This initial spec was widely popular,
but 13W was not adequate for some requirements. In
2009, the IEEE released a new standard, known as 802.3at
+
or PoE , increasing the voltage and current requirements
to provide 25W of power.
The LTC4266 comes in three grades which support dif-
ferent PD power levels.
The IEEE standard also defines PoE terminology. A device
that provides power to the network is known as a PSE,
or power sourcing equipment, while a device that draws
power from the network is known as a PD, or powered
device. PSEs come in two types: Endpoints (typically net-
work switches or routers), which provide data and power;
and Midspans, which provide power but pass through
data. Midspans are typically used to add PoE capabil-
ity to existing non-PoE networks. PDs are typically IP
phones, wireless access points, security cameras, and
similar devices.
The A-grade LTC4266 extends PoE power delivery capa-
++
++
bilities to LTPoE levels. LTPoE is a Linear Technology
proprietary specification allowing for the delivery of up
++
++
to 90W to LTPoE compliant PDs. The LTPoE archi-
tecture extends the IEEE physical power negotiation to
include 38.7W, 52.7W, 70W and 90W power levels. The
A-grade LTC4266 also incorporates all B- and C-grade
features.
The B-grade LTC4266 is a fully IEEE-compliant Type 2
PSE supporting autonomous detection, classification
and powering of Type 1 and Type 2 PDs. The B-grade
LTC4266 also incorporates all C-grade features. The
B-grade LTC4266 is marketed and numbered without the
B suffix for legacy reasons; the absence of power grade
suffix infers a B-grade part.
++
PoE Evolution
+
Even during the process of creating the IEEE PoE 25.5W
specification, it became clear that there was a significant
and increasing need for more than 25.5W of delivered
power. The LTC4266A family responds to this market by
allowing a reliable means of providing up to 90W of deliv-
The C-grade LTC4266 is a fully autonomous 802.3at Type 1
PSE solution. Intended for use only in AUTO pin mode,
the C-grade chipset autonomously supports detection,
classification and powering of Type 1 PDs. As a Type 1
PSE, 2-event classification is prohibited and Class 4 PDs
are automatically treated as Class 0 PDs.
++
++
ered power to a LTPoE PD. The LTPoE specification
provides reliable detection and classification extensions to
the existing IEEE PoE technique that are backward com-
patible and interoperable with existing Type 1 and Type 2
++
PDs. Unlike other proprietary PoE solutions, Linear’s
++
LTPoE solution provides mutual identification between
PoE Basics
++
the PSE and PD. This ensures that the LTPoE PD knows
it may use the requested power at start-up because it has
Common Ethernet data connections consist of two or four
twisted pairs of copper wire (commonly known as CAT-5
cable), transformer-coupled at each end to avoid ground
loops. PoE systems take advantage of this coupling
arrangement by applying voltage between the center-taps
of the data transformers to transmit power from the PSE
++
++
detected a LTPoE PSE. LTPoE PSEs can differentiate
++
between a LTPoE PD and all other types of IEEE compli-
++
ant PDs allowing LTPoE PSEs to remain compliant and
interoperable with existing equipment.
4266acfe
16
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
operAtion
CAT 5
20Ω MAX
PSE
PD
ROUNDTRIP
0.05µF MAX
RJ45
4
RJ45
4
5
5
GND
SPARE PAIR
1
1
AGND
Tx
Rx
Tx
2
3
2
3
DATA PAIR
DATA PAIR
1/4
2
LTC4266
I C
Rx
V
EE
GATE
GND
6
6
DC/DC
CONVERTER
PWRGD
LTC4265
–54V –54V
+
OUT
V
–54V
7
8
7
–
IN
OUT
8
SPARE PAIR
4266AC F10
Figure 10. Power Over Ethernet System Diagram
to the PD without affecting data transmission. Figure 10
shows a high-level PoE system schematic.
New in 802.3at
The newer 802.3at standard supersedes 802.3af and
brings several new features:
To avoid damaging legacy data equipment that does not
expect to see DC voltage, the PoE spec defines a protocol
that determines when the PSE may apply and remove
power. Valid PDs are required to have a specific 25k com-
mon-mode resistance at their input. When such a PD is
connected to the cable, the PSE detects this signature
resistance and turns on the power. When the PD is later
disconnected, the PSE senses the open circuit and turns
power off. The PSE also turns off power in the event of a
current fault or short-circuit.
•
A PD may draw as much as 25.5W. Such PDs (and
the PSEs that support them) are known as Type 2.
Older 13W 802.3af equipment is classified as Type 1.
Type 1 PDs will work with all PSEs; Type 2 PDs may
require Type 2 PSEs to work properly. The LTC4266A/
LTC4266C is designed to work in both Type 1 and
Type 2 PSE designs, and also supports non-standard
configurations at higher power levels.
•
The Classification protocol is expanded to allow Type
2 PSEs to detect Type 2 PDs, and to allow Type 2 PDs
to determine if they are connected to a Type 2 PSE.
Two versions of the new Classification protocol are
available: an expanded version of the 802.3af Class
Pulse protocol, and an alternate method integrated
with the existing LLDP protocol (using the Ethernet
data path). The LTC4266A/LTC4266C fully supports
the new Class Pulse protocol and is also compatible
with the LLDP protocol (which is implemented in the
data communications layer, not in the PoE circuitry).
When a PD is detected, the PSE optionally looks for a
classification signature that tells the PSE the maximum
power the PD will draw. The PSE can use this information
to allocate power among several ports, police the current
consumption of the PD, or to reject a PD that will draw
more power that the PSE has available. For a 802.3af PSE,
the classification step is optional; if a PSE chooses not to
classify a PD, it must assume that the PD is a 13W (full
802.3af power) device.
4266acfe
17
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
operAtion
++
•
Fault protection current levels and timing are adjusted
to reduce peak power in the MOSFET during a fault;
this allows the new 25.5W power levels to be reached
using the same MOSFETs as older 13W designs.
The higher levels of LTPoE delivery impose addi-
tional layout and component selection constraints. The
LTC4266A is offered in 4 power levels (-1, -2, -3, and -4)
which allows the AUTO pin mode LTC4266A to autono-
mously power up to supported power levels. If the AUTO
pin is high, internal circuitry determines the maximum
deliverable power. PDs requesting more than the available
power limits are not powered.
++
Extended Power LTPoE
The LTC4266A adds the capability to autonomously
++
deliver up to 90W of power to the PD. LTPoE PDs
may forgo 802.3 LLDP support and rely solely on the
++
Table 1. LTPoE Auto Pin Mode Maximum Delivered
++
LTPoE Physical Classification to negotiate power with
Power Capabilities
++
LTPoE PSEs; this greatly simplifies high-power PD
PART
PAIRS
PD POWER
38.7W
52.7W
70W
implementations.
LTC4266A-1
LTC4266A-2
LTC4266A-3
LTC4266A-4
4
4
4
4
++
LTPoE classification may be optionally enabled for the
LTC4266A by setting both the High Power Enable and
90W
++
LTPoE Enable bits.
4266acfe
18
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
ApplicAtions inForMAtion
Operating Modes
Regardless of which mode it is in, the LTC4266A/
LTC4266C will remove power automatically from any
port that generates a current limit fault. It will also auto-
matically remove power from any port that generates a
disconnect event if disconnect detection is enabled. The
host controller may also command the port to remove
power at any time.
The LTC4266A/LTC4266C include four independent ports,
each of which can operate in one of four modes: manual,
semi-auto, AUTO pin, or shutdown.
Table 2. Operating Modes
AUTOMATIC
AUTO
PIN OPMD
DETECT/
CLASS
I
/I
CUT LIM
MODE
POWER-UP ASSIGNMENT
Reset and the AUTO/MID Pins
AUTO Pin
1
11b
Enabled at Automatically
Reset
Yes
The initial LTC4266A/LTC4266C configuration depends
on the state of the AUTO and MID pins during reset. Reset
occurs at power-up, or whenever the RESET pin is pulled
low or the global Reset All bit is set. Changing the state
of AUTO or MID after power-up will not properly change
the port behavior of the LTC4266A/LTC4266C until a reset
occurs.
Reserved
Semi-auto
0
0
11b
10b
N/A
N/A
N/A
No
Host
Enabled
Upon
Request
Manual
0
0
01b Once Upon
Request
Upon
No
No
Request
Shutdown
00b
Disabled
Disabled
•
In manual mode, the port waits for instructions from
the host system before taking any action. It runs a
single detection or classification cycle when com-
manded to by the host, and reports the result in its
Port Status register. The host system can command
the port to turn on or off the power at any time. This
mode should only be used for diagnostic and test
purposes.
Although typically used with a host controller, the
LTC4266A/LTC4266C can also be used in a standalone
mode with no connection to the serial interface. If there is
no host present, the AUTO pin must be tied high so that, at
reset, all ports will be configured to operate automatically.
Each port will detect and classify repeatedly until a PD is
discovered, set I
and I according to the classifica-
CUT
LIM
tion results, apply power after successful detection, and
•
•
•
In semi-auto mode, the port repeatedly attempts to
detect and classify any PD attached to it. It reports
the status of these attempts back to the host, and
waits for a command from the host before turning
on power to the port. The host must enable detec-
tion (and optionally classification) for the port before
detection will start.
remove power when a PD is disconnected.
Table 3 shows the I
and I
values that will be auto-
LIM
CUT
matically set in standalone (AUTO pin) mode, based on
the discovered class.
Table 3. ICUT and ILIM Values in Standalone AUTO Pin Mode
CLASS
I
I
LIM
CUT
Class 1
112mA
206mA
375mA
638mA
425mA
425mA
425mA
850mA
AUTO pin mode operates the same as semi-auto
mode except that it will automatically turn on the
power to the port if detection is successful. In AUTO
Class 2
Class 3 or Class 0
Class 4
pin mode, I
and I
values are set automatically
CUT
LIM
by the LTC4266A/LTC4266C. This operational mode
is only valid if the AUTO pin is high at reset or power-
up and remains high during operation.
The automatic setting of the I
and I
values only
LIM
CUT
occurs if the LTC4266A/LTC4266C is reset with the AUTO
pin high.
In shutdown mode, the port is disabled and will not
detect or power a PD.
If the standalone application is a midspan, the MID pin
must be tied high to enable correct midspan detection
timing.
4266acfe
19
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
ApplicAtions inForMAtion
DETECTION
circuitry subtracts the two V-I points to determine the
resistive slope while removing offset caused by series
diodes or leakage at the port (see Figure 12). If the forced-
current detection yields a valid signature resistance, two
test voltages are then forced onto the port and the result-
ing currents are measured and subtracted. Both methods
must report valid resistances for the port to report a valid
detection. PD signature resistances between 17k and 29k
(typically) are detected as valid and reported as Detect
Good in the corresponding Port Status register. Values
outside this range, including open and short-circuits, are
also reported. If the port measures less than 1V at the
first forced-current test, the detection cycle will abort and
Short Circuit will be reported. Table 4 shows the possible
detection results.
Detection Overview
To avoid damaging network devices that were not
designed to tolerate DC voltage, a PSE must determine
whether the connected device is a real PD before apply-
ing power. The IEEE specification requires that a valid PD
have a common-mode resistance of 25k 5% at any port
voltage below 10V. The PSE must accept resistances that
fall between 19k and 26.5k, and it must reject resistances
above 33k or below 15k (shaded regions in Figure 11).
The PSE may choose to accept or reject resistances in
RESISTANCE 0Ω
10k
20k
30k
150Ω (NIC)
23.75k
26.25k
26.5k
PD
PSE
15k 19k
33k
Table 4. Detection Status
4266AC F11
MEASURED PD SIGNATURE
Incomplete or Not Yet Tested
<2.4k
DETECTION RESULT
Detect Status Unknown
Short Circuit
Figure 11. IEEE 802.3af Signature Resistance Ranges
the undefined areas between the must-accept and must-
reject ranges. In particular, the PSE must reject standard
computer network ports, many of which have 150Ω com-
mon-mode termination resistors that will be damaged if
power is applied to them (the black region at the left of
Figure 11).
Capacitance > 2.7µF
C
Too High
Too Low
PD
2.4k < R < 17k
R
SIG
PD
17k < R < 29k
Detect Good
R Too High
SIG
PD
>29k
>50k
Open Circuit
Voltage > 10V
Port Voltage Outside Detect Range
4-Point Detection
The LTC4266A/LTC4266C uses a 4-point detection method
to discover PDs. False-positive detections are minimized
by checking for signature resistance with both forced-
current and forced-voltage measurements. Initially, two
test currents are forced onto the port (via the OUTn pin)
and the resulting voltages are measured. The detection
More On Operating Modes
The port’s operating mode determines when the
LTC4266A/LTC4266C runs a detection cycle. In manual
mode, the port will idle until the host orders a detect cycle.
It will then run detection, report the results, and return to
idle to wait for another command.
In semi-auto mode, the LTC4266A/LTC4266C autono-
mously polls a port for PDs, but it will not apply power
until commanded to do so by the host. The Port Status
register is updated at the end of each detection cycle. If
a valid signature resistance is detected and classification
is enabled, the port will classify the PD and report that
result as well. The port will then wait for at least 100ms
(or 2 seconds if midspan mode is enabled), and will repeat
the detection cycle to ensure that the data in the Port
Status register is up-to-date.
275
FIRST
DETECTION
POINT
25kΩ SLOPE
165
SECOND
DETECTION
POINT
VALID PD
0V-2V
OFFSET
VOLTAGE
4266AC F12
Figure 12. PD Detection
4266acfe
20
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
ApplicAtions inForMAtion
60
50
40
30
20
10
0
If the port is in semi-auto mode and high power opera-
tion is enabled, the port will not turn on in response to
a power-on command unless the current detect result is
PSE LOAD LINE
OVER
CURRENT
48mA
Detect Good. Any other detect result will generate a t
START
CLASS 4
fault if a power-on command is received. If the port is not
in high power mode, it will ignore the detection result and
apply power when commanded, maintaining backwards
compatibility with the LTC4259A.
33mA
CLASS 3
23mA
CLASS 2
TYPICAL
14.5mA
6.5mA
CLASS 3
PD LOAD
LINE
CLASS 1
CLASS 0
Behavior in AUTO pin mode is similar to semi-auto; how-
ever, after Detect Good is reported and the port is classi-
fied (if classification is enabled), it is automatically pow-
ered on without further intervention. In standalone (AUTO
0
5
10
15
20
25
VOLTAGE (V
)
CLASS
4266AC F13
pin) mode, the I
and I thresholds are automatically
Figure 13. PD Classification
CUT
LIM
set; see the Reset and the AUTO/MID Pin section for more
information.
a constant current draw when the PSE port voltage is in the
V
range (between 15.5V and 20.5V), with the current
leCvLeAlSiSndicating one of 5 possible PD classes. Figure 13
shows a typical PD load line, starting with the slope of the
25kΩ signature resistor below 10V, then transitioning to
the classification signature current (in this case, Class 3)
in the VCLASS range. Table 5 shows the possible clas-
sification values.
The signature detection circuitry is disabled when the port
is initially powered up with the AUTO pin low, in shutdown
mode, or when the corresponding Detect Enable bit is
cleared.
Detection of Legacy PDs
Proprietary PDs that predate the original IEEE 802.3af
standard are commonly referred to today as legacy
devices. One type of legacy PD uses a large common-
mode capacitance (>10μF) as the detection signature.
Note that PDs in this range of capacitance are defined as
invalid, so a PSE that detects legacy PDs is technically
noncompliant with the IEEE spec.
Table 5. Classification Values
CLASS
Class 0
Class 1
Class 2
Class 3
Class 4
RESULT
No Class Signature Present; Treat Like Class 3
3W
7W
13W
25.5W (Type 2)
The LTC4266A/LTC4266C can be configured to detect
this type of legacy PD. Legacy detection is disabled by
default, but can be manually enabled on a per-port basis.
When enabled, the port will report Detect Good when it
sees either a valid IEEE PD or a high-capacitance legacy
PD. With legacy mode disabled, only valid IEEE PDs will
be recognized.
If classification is enabled, the port will classify the PD
immediately after a successful detection cycle in semi-
auto or AUTO pin modes, or when commanded to in man-
ual mode. It measures the PD classification signature by
applying 18V for 12ms (both values typical) to the port via
the OUTn pin and measuring the resulting current; it then
reports the discovered class in the Port Status register.
If the LTC4266A/LTC4266C is in AUTO pin mode, it will
CLASSIFICATION
additionally use the classification result to set the I
CUT
802.3af Classification
and ILIM thresholds. See the Reset and the AUTO/MID Pin
section for more information.
A PD can optionally present a classification signature to
the PSE to indicate the maximum power it will draw while
operating. The IEEE specification defines this signature as
The classification circuitry is disabled when the port is
initially powered up with the AUTO pin low, in shutdown
4266acfe
21
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
ApplicAtions inForMAtion
mode, or when the corresponding Class Enable bit is
cleared.
presents an invalid Type 2 signature (Class 4 followed by
Class 0 to 3), the LTC4266A will not provide power and
will restart the detection process. To aid in diagnosis, the
Port Status register will always report the results of the
last class pulse, so, for example, an invalid Class 4–Class 2
combination would report a second class pulse was run
in the High Power Status register (which implies that the
first cycle found Class 4), and Class 2 in the Port Status
register.
802.3at 2-Event Classification
The 802.3at specification defines two methods of classify-
ing a Type 2 PD. The LTC4266A supports 802.3at 2-event
classification. The LTC4266C does not support 2-event
classification.
One method adds extra fields to the Ethernet LLDP data
protocol; although the LTC4266A/LTC4266C is compat-
ible with this classification method, it cannot perform
classification directly since it doesn’t have access to the
data path. LLDP classification requires the PSE to power
the PD as a standard 802.3af (Type 1) device. It then
waits for the host to perform LLDP communication with
the PD and update the PSE port data. The LTC4266A/
POWER CONTROL
External MOSFET, Sense Resistor Summary
The primary function of the LTC4266A/LTC4266C is to
control the delivery of power to the PSE port. It does
this by controlling the gate drive voltage of an external
power MOSFET while monitoring the current via an exter
-
LTC4266C supports changing the I and I
levels on
LIM
CUT
nal sense resistor and the output voltage at the OUT pin.
the fly, allowing the host to complete LLDP classification.
This circuitry serves to couple the raw V input supply
EE
The second 802.3at classification method, known as
2-event classification or ping-pong, is supported by the
LTC4266A. A Type 2 PD that is requesting more than 13W
will indicate Class 4 during normal 802.3af classification.
If the LTC4266A sees Class 4, it forces the port to a speci-
fied lower voltage (called the mark voltage, typically 9V),
pauses briefly, and then re-runs classification to verify the
Class 4 reading (Figure 1). It also sets a bit in the High
Power Status register to indicate that it ran the second
classification cycle. The second cycle alerts the PD that
it is connected to a Type 2 PSE which can supply Type 2
power levels.
to the port in a controlled manner that satisfies the PD’s
power needs while minimizing power dissipation in the
MOSFET and disturbances on the V backplane.
EE
The LTC4266A/LTC4266C is designed to use 0.25Ω sense
resistors to minimize power dissipation. It also sup-
ports 0.5Ω sense resistors, which are the default when
LTC4258/LTC4259A compatibility is desired.
Inrush Control
Once the command has been given to turn on a port,
the LTC4266A/LTC4266C ramps up the GATE pin of that
port’s external MOSFET in a controlled manner. Under
normal power-up circumstances, the MOSFET gate will
rise until the port current reaches the inrush current limit
level (typically 450mA), at which point the GATE pin will
be servoed to maintain the specified IINRUSH current.
2-event ping-pong classification is enabled by setting a bit
in the port’s High Power Mode register. Note that a ping-
pong enabled port only runs the second classification cycle
when it detects a Class 4 device; if the first cycle returns
Class 0 to 3, the port assumes it is connected to a Type 1
PD and does not run the second classification cycle.
During this inrush period, a timer (t
) runs. When
START
output charging is complete, the port current will fall and
the GATE pin will be allowed to continue rising to fully
enhance the MOSFET and minimize its on-resistance. The
Invalid Type 2 Class Combinations
The 802.3at specification defines a Type 2 PD class sig-
nature as two consecutive Class 4 results; a Class 4 fol-
lowed by a Class 0-3 is not a valid signature. In AUTO pin
mode, the LTC4266A will power a detected PD regardless
of the classification results, with one exception: if the PD
final V is nominally 12V. The inrush period is main-
GS
tained until the t
timer expires. At this time if the
START
inrush current limit level is still exceeded the port will be
turned back off and a t fault reported.
START
4266acfe
22
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
ApplicAtions inForMAtion
Current Limit
425mA for all Type 1 PDs, and 850mA if a Type 2 PD is
detected. ILIM is automatically reset to 425mA when a
port turns off.
Each LTC4266A/LTC4266C port includes two current
limiting thresholds (ICUT and ILIM), each with a corre-
sponding timer (t
and t ). Setting the I
and I
CUT
LIM
CUT LIM
I
Foldback
LIM
thresholds depends on several factors: the class of the
The LTC4266A/LTC4266C features a two-stage foldback
circuit that reduces the port current if the port voltage falls
below the normal operating voltage. This keeps MOSFET
power dissipation at safe levels for typical 802.3af
MOSFETs, even at extended 802.3at power levels. Current
limit and foldback behavior are programmable on a per-
PD, the voltage of the main supply (V ), the type of PSE
EE
(Type 1 or Type 2), the sense resistor (0.5Ω or 0.25Ω),
the SOA of the MOSFET, and whether or not the system
is required to implement class enforcement.
Per the IEEE specification, the LTC4266A/LTC4266C will
allow the port current to exceed I
for a limited period of
CUT
port basis. Table 6 gives examples of recommended I
register settings.
LIM
time before removing power from the port, whereas it will
actively control the MOSFET gate drive to keep the port cur-
Table 6. Example Current Limit Settings
INTERNAL REGISTER SETTING (hex)
rent below I . The port does not take any action to limit the
LIM
current when only the I
threshold is exceeded, but does
CUT
I
(mA)
start the t
timer. If the current drops below the I cur-
R
SENSE
= 0.5Ω
R
SENSE
= 0.25Ω
LIM
CUT
CUT
rent threshold before its timer expires, the t timer counts
53
88
CUT
back down, but at 1/16 the rate that it counts up. If the t
106
159
213
266
319
372
08
89
80
8A
09
8B
88
CUT
timer reaches 60ms (typical) the port is turned off and the
port t fault is set. This allows the current limit circuitry to
08
89
CUT
tolerate intermittent overload signals with duty cycles below
about 6%; longer duty cycle overloads will turn the port off.
The ILIM current limiting circuit is always enabled and
425
478
00
8E
92
CB
10
D2
40
4A
50
5A
60
52
80
actively limiting port current. The t
timer is enabled
LIM
only when the programmable t
field is non-zero. This
LIMn
allows t
to be set to a shorter value than t
to pro-
531
8A
LIM
CUT
vide more aggressive MOSFET protection and turn off a
port before MOSFET damage can occur. The tLIM timer
starts when the I threshold is exceeded. When the t
584
638
90
9A
C0
CA
D0
DA
E0
49
40
4A
50
5A
60
52
744
LIM
LIM
LIMn
timer reaches 1.7ms (typ) times the programmable t
850
field the port is turned off and the port t
fault is set.
LIM
956
When the t
field is zero, t
behaviors are tracked
LIMn
LIM
1063
1169
1275
1488
1700
1913
2125
2338
2550
2975
by the t
timer, which counts up during both I
events.
and
LIM
CUT
I
CUT
I
is typically set to a lower value than I to allow the
CUT
LIM
port to tolerate minor faults without current limiting.
Per the IEEE specification, the LTC4266A/LTC4266C will
automatically set I to 425mA (shown in bold in Table 6)
during inrush at LpIMort turn-on, and then switch to the
programmed ILIM setting once inrush has completed.
To maintain IEEE compliance, ILIM should be kept at
4266acfe
23
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
ApplicAtions inForMAtion
The LTC4266A/LTC4266C will support current levels well
beyond the maximum values in the 802.3at specification.
The shaded areas in Table 6 indicate settings that may
require a larger external MOSFET, additional heat sinking,
Disconnect
The LTC4266A/LTC4266C monitors the port to make sure
that the PD continues to draw the minimum specified cur-
rent. A disconnect timer counts up whenever port current
is below 7.5mA (typ), indicating that the PD has been dis-
connected. If the t timer expires, the port will be turned
off and the disconnDIeSct bit in the fault event register will be
set. If the current returns before the t timer runs out,
the timer resets and will start counting from the beginning
if the undercurrent condition returns. As long as the PD
or enabling t
.
LIM
MOSFET Fault Detection
LTC4266A/LTC4266C PSE ports are designed to tolerate
significant levels of abuse, but in extreme cases it is pos-
sible for the external MOSFET to be damaged. A failed
MOSFET may short source to drain, which will make the
port appear to be on when it should be off; this condition
may also cause the sense resistor to fuse open, turning
off the port but causing the LTC4266A/LTC4266C SENSE
pin to rise to an abnormally high voltage. A failed MOSFET
may also short from gate to drain, causing the LTC4266A/
LTC4266C GATE pin to rise to an abnormally high voltage.
The LTC4266A/LTC4266C OUT, SENSE and GATE pins
are designed to tolerate up to 80V faults without damage.
DIS
exceeds the minimum current level more often than t
it will stay powered.
,
DIS
Although not recommended, the DC disconnect fea-
ture can be disabled by clearing the corresponding DC
Disconnect Enable bits. Note that this defeats the protec-
tion mechanisms built into the IEEE spec, since a powered
port will stay powered after the PD is removed. If the still-
powered port is subsequently connected to a non-PoE
data device, the device may be damaged.
If the LTC4266A/LTC4266C sees any of these conditions
for more than 180μs, it disables all port functionality,
reduces the gate drive pull-down current for the port and
reports a FET Bad fault. This is typically a permanent fault,
but the host can attempt to recover by resetting the port,
or by resetting the entire chip if a port reset fails to clear
the fault. If the MOSFET is in fact bad, the fault will quickly
return, and the port will disable itself again. The remaining
ports of the LTC4266A/LTC4266C are unaffected.
The LTC4266A/LTC4266C does not include AC disconnect
circuitry, but includes AC Disconnect Enable bits to main-
tain compatibility with the LTC4259A. If the AC Disconnect
Enable bits are set, DC disconnect will be used.
Shutdown Pins
The LTC4266A/LTC4266C includes a hardware SHDN pin
for each port. When a SHDN pin is pulled to DGND, the
corresponding port will be shut off immediately. The port
An open or missing MOSFET will not trigger a FET Bad
fault, but will cause a tSTART fault if the LTC4266A/
LTC4266C attempts to turn on the port.
2
remains shut down until re-enabled via I C or a device
reset in AUTO pin mode.
Masked Shutdown
Voltage and Current Readback
The LTC4266A/LTC4266C provides a low latency port
shedding feature to quickly reduce the system load when
required. By allowing a pre-determined set of ports to
be turned off, the current on an overloaded main power
supply can be reduced rapidly while keeping high priority
devices powered. Each port can be configured to high or
low priority; all low-priority ports will shut down within
6.5μs after the MSD pin is pulled low. If multiple ports in a
LTC4266A/LTC4266C device are shut down via MSD, they
are staggered by at least 0.55μs to help reduce voltage
The LTC4266A/LTC4266C measures the output voltage
and current at each port with an internal A/D converter.
Port data is only valid when the port power is on. The
converter has two modes:
•
•
Slow mode: 14 samples per second, 14.5 bits resolution
Fast mode: 440 samples per second, 9.5 bits resolution
In fast mode, the least significant 5 bits of the lower byte
are zeroes so that bit scaling is the same in both modes.
4266acfe
24
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
ApplicAtions inForMAtion
transients on the main supply. If a port is turned off via
MSD, the corresponding Detection and Classification
Enable bits are cleared, so the port will remain off until
the host explicitly re-enables detection.
Register Description
For information on serial bus usage and device con-
figuration and status, refer to the LTC4266A/LTC4266C
Software Programming documentation.
SERIAL DIGITAL INTERFACE
EXTERNAL COMPONENT SELECTION
Overview
Power Supplies and Bypassing
The LTC4266A/LTC4266C communicates with the
host using a standard SMBus/I C 2-wire interface. The
The LTC4266A/LTC4266C requires two supply voltages to
2
operate. V requires 3.3V (nominally) relative to DGND.
DD
LTC4266A/LTC4266C is a slave-only device, and commu-
nicates with the host master using the standard SMBus
protocols. Interrupts are signaled to the host via the INT
pin. The Timing Diagrams (Figures 5 through 9) show
typical communication waveforms and their timing rela-
tionships. More information about the SMBus data pro-
tocols can be found at www.smbus.org.
V requires a negative voltage of between –45V and –57V
EE
for Type 1 PSEs, –51V to –57V for Type 2 PSEs or –54.75V
++
to –57V for LTPoE PSEs, relative to AGND. The relation-
ship between the two grounds is not fixed; AGND can be
referenced to any level from V to DGND, although it
DD
should typically be tied to either V or DGND.
DD
V
provides power for most of the internal LTC4266A/
DD
The LTC4266A/LTC4266C requires both the VDD and
LTC4266C circuitry, and draws a maximum of 3mA.
V
supply rails to be present for the serial interface to
EE
A ceramic decoupling cap of at least 0.1μF should be
function.
placed from V to DGND, as close as practical to each
DD
LTC4266A/LTC4266C chip.
Bus Addressing
Figure 14 shows a three component low dropout regulator
for a negative supply to DGND generated from the nega-
The LTC4266A/LTC4266C’s primary serial bus address
is 010xxxxb, with the lower four bits set by the AD3-AD0
pins; this allows up to 16 LTC4266A/LTC4266Cs on a
single bus. All LTC4266A/LTC4266Cs also respond to the
address 0110000b, allowing the host to write the same
command (typically configuration commands) to mul-
tiple LTC4266A/LTC4266Cs in a single transaction. If the
LTC4266A/LTC4266C is asserting the INT pin, it will also
respond to the alert response address (0001100b) per
the SMBus spec.
tive V supply. V is tied to AGND and DGND is nega-
EE
tive referenced toDADGND. This regulator drives a single
LTC4266A/LTC4266C device. In Figure 15, DGND is tied
to AGND in this boost converter circuit for a positive V
DD
supply of 3.3V above AGND. This circuit can drive multiple
LTC4266A/LTC4266C devices and opto couplers.
10Ω
AGND
V
DD
Interrupts and SMBAlert
CMHZ4687-4.3V
1µF
100V
0.1µF
LTC4266
DGND
Most LTC4266A/LTC4266C port events can be configured
to trigger an interrupt, asserting the INT pin and alerting
the host to the event. This removes the need for the host to
poll the LTC4266A/LTC4266C, minimizing serial bus traf-
fic and conserving host CPU cycles. Multiple LTC4266A/
LTC4266Cs can share a common INT line, with the host
using the SMBAlert protocol (ARA) to determine which
LTC4266A/LTC4266C caused an interrupt.
CMPTA92
SMAJ58A
V
EE
750k
4266AC F14
V
EE
Figure 14. Negative LDO to DGND
4266acfe
25
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
ApplicAtions inForMAtion
L3
L4
10µH
D28
B1100
100µH
SUMIDA CDRH5D28-101NC
SUMIDA CDRH4D28-100NC
3.3V AT 400mA
C74
100µF
6.3V
C73
10µF
6.3V
C75
R51
4.7k
1%
R53
R52
3.32k
1%
10µF
4.7k
16V
1%
C76
10µF
100V
C78
0.22µF
100V
+
5
Q13
Q14
FMMT723
C77
0.22µF
100V
V
FMMT723
CC
1
3
6
Q15
ITH/RUN
NGATE
SENSE
FDC2512
R58
10Ω
LTC3803
R54
56k
4
R55
806Ω
1%
R56
47.5k
1%
V
FB
R57
1k
R59
0.100Ω
1%, 1W
C79
2200pF
GND
2
R60
10Ω
V
EE
4266AC F15
Figure 15. Positive VDD Boost Converter
V
is the main supply that provides power to the PDs.
IEEE 802.3 Ethernet specifications require that network
segments (including PoE circuitry) be electrically isolated
from the chassis ground of each network interface device.
However, network segments are not required to be iso-
lated from each other, provided that the segments are
connected to devices residing within a single building on
a single power distribution system.
EE
Because it supplies a relatively large amount of power and
is subject to significant current transients, it requires more
design care than a simple logic supply. For minimum IR
loss and best system efficiency, set V near maximum
EE
amplitude (57V), leaving enough margin to account for
transient over- or undershoot, temperature drift, and the
line regulation specs of the particular power supply used.
For simple devices such as small PoE switches, the isola-
tion requirement can be met by using an isolated main
power supply for the entire device. This strategy can be
used if the device has no electrically conducting ports
other than twisted-pair Ethernet. In this case, the SDAIN
and SDAOUT pins can be tied together and will act as a
Bypass capacitance between AGND and V is very impor-
EE
tant for reliable operation. If a short-circuit occurs at one
of the output ports it can take as long as 1μs for the
LTC4266A/LTC4266C to begin regulating the current.
During this time the current is limited only by the small
impedances in the circuit and a high current spike typically
2
standard I C/SMBus SDA pin.
occurs, causing a voltage transient on the V supply and
EE
If the device is part of a larger system, contains additional
external non-Ethernet ports, or must be referenced to
protective ground for some other reason, the Power over
Ethernet subsystem (including all LTC4266A/LTC4266Cs)
must be electrically isolated from the rest of the system.
Figure 16 shows a typical isolated serial interface. The
SDAOUT pin of the LTC4266A/LTC4266C is designed to
possibly causing the LTC4266A/LTC4266C to reset due
to a UVLO fault. A 1μF, 100V X7R capacitor placed near
the V pin is recommended to minimize spurious resets.
EE
Isolating the Serial Bus
The LTC4266A/LTC4266C includes a split SDA pin (SDAIN
and SDAOUT) to ease opto-isolation of the bidirectional
SDA line.
2
drive the inputs of an opto-coupler directly. Standard I C/
SMBus devices typically cannot drive opto-couplers, so U1
is used to buffer the signals from the host controller side.
4266acfe
26
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
ApplicAtions inForMAtion
10Ω
LTC4266
V
INT
2
DD
I C ADDRESS
SCL
SDAIN
SDAOUT
AD0
0100000
AD1
0.1µF
AD2
AD3
SMAJ5.0A
0.1µF
DGND
AGND
10Ω
V
EE
1µF
100V
SMAJ58A
10Ω
LTC4266
V
DD
INT
SCL
2k
2k
U2
SDAIN
SDAOUT
AD0
AD1
AD2
AD3
DGND
AGND
200Ω
V
CPU
SCL
DD
0100001
U1
SMAJ5.0A
0.1µF
200Ω
10Ω
V
EE
1µF
100V
SMAJ58A
SDA
HCPL-063L
TO
10Ω
LTC4266
V
INT
SCL
CONTROLLER
DD
U3
200Ω
200Ω
SDAIN
SDAOUT
AD0
0100010
AD1
AD2
AD3
SMAJ5.0A
0.1µF
SMBALERT
DGND
10Ω
0.1µF
AGND
V
EE
1µF
100V
GND CPU
SMAJ58A
•
•
•
HCPL-063L
U1: FAIRCHILD NC7WZ17
U2, U3: AGILENT HCPL-063L
ISOLATED
3.3V
10Ω
LTC4266
V
DD
INT
SCL
SDAIN
SDAOUT
AD0
+
10µF
ISOLATED
GND
0101111
AD1
AD2
AD3
DGND
SMAJ5.0A
0.1µF
+
TVS
C
BULK
BULK
10Ω
AGND
V
EE
1µF
100V
4266AC F16
SMAJ58A
ISOLATED
–54V
Figure 16. Opto-Isolating the I2C Bus
4266acfe
27
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
ApplicAtions inForMAtion
External MOSFET
Port Output Cap
Careful selection of the power MOSFET is critical to system
reliability. LTC recommends either Fairchild IRFM120A,
FDT3612, FDMC3612 or Philips PHT6NQ10T for their
proven reliability in Type 1 and Type 2 PSE applications.
Non-standard applications that provide more current
than the 850mA IEEE maximum may require heat sink-
ing and other MOSFET design considerations. Contact
LTC Applications before using a MOSFET other than one
of these recommended parts.
Each port requires a 0.22μF cap across its outputs to keep
the LTC4266A/LTC4266C stable while in current limit
during startup or overload. Common ceramic capacitors
often have significant voltage coefficients; this means the
capacitance is reduced as the applied voltage increases.
To minimize this problem, X7R ceramic capacitors rated
for at least 100V are recommended.
Surge Protection
Ethernet ports can be subject to significant cable surge
events. To keep PoE voltages below a safe level and protect
the application against damage, protection components,
as shown in Figure 17, are required at the main supply, at
the LTC4266A/LTC4266C pins, and at each port.
Sense Resistor
The LTC4266A/LTC4266C is designed to use either
0.5Ω or 0.25Ω current sense resistors. For new designs
0.25Ω is recommended to reduce power dissipation; the
0.5Ω option is intended for existing systems where the
LTC4266A/LTC4266C is used as a drop-in replacement
for the LTC4258 or LTC4259A. The lower sense resistor
values reduce heat dissipation. Four commonly available
1Ω resistors (0402 or larger package size) can be used
in parallel in place of a single 0.25Ω resistor. In order
Bulk transient voltage suppression (TVS
) and bulk
capacitance (CBULK) are required acrossBUthLeK main PoE
supply and should be sized to accommodate system
level surge requirements. A large capacitance of 10μF or
greater (C3) is required across the +3.3V supply if V
is above AGND.
DD
to meet the I
and I
accuracy required by the IEEE
CUT
LIM
Each LTC4266A/LTC4266C requires a 10Ω, 0805 resis-
tor (R1) in series from supply AGND to the LTC4266A/
LTC4266C AGND pin. Across the LTC4266A/LTC4266C
AGND pin and V pin are an SMAJ58A, 58V TVS (D1) and
a 1μF, 100V byEpEass capacitor (C1). These components
must be placed close to the LTC4266A/LTC4266C pins.
specification, the sense resistors should have 1% toler-
ance or better, and no more than 200ppm/°C tempera-
ture coefficient.
R2
10Ω
V
+3.3V
DD
C2
0.1µF
D2
AUTO
SCL
SMAJ5.0A
1/4
+
+
SDAIN
DGND
AGND
LTC4266
C3
R1
TO PORT
10µF
10Ω
V
EE
SENSE GATE OUT
TVS
C
BULK
OUT
C1
0.22μF
100V
X7R
D3
S1B
1µF
D1
SMAJ58A
C
BULK
100V
X7R
R
S
–54V
OUTn
Q1
D4 S1B
4266AC F17
Figure 17. LTC4266 Surge Protection
4266acfe
28
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
ApplicAtions inForMAtion
If the VDD supply is above AGND, each LTC4266A/
LTC4266C requires a 10Ω, 0805 resistor (R2) in series
from the +3.3V supply positive rail to the LTC4266A/
LTC4266C VDD pin. Across the LTC4266A/LTC4266C VDD
pin and DGND pin are an SMAJ5.0A, 5.0V TVS (D2) and a
0.1μF capacitor (C2). These components must be placed
close to the LTC4266A/LTC4266C pins. DGND is tied
directly to the protected AGND pin. Pull-ups at the logic
pins should be to the protected side of the 10Ω resistors
Further considerations include LTC4266A/LTC4266C
applications with off-board connections, such as a daugh-
ter card to a mother board or headers to an external sup-
ply or host control board. Additional protection may be
required at the LTC4266A/LTC4266C pins to these off-
board connections.
LAYOUT GUIDELINES
Strict adherence to board layout, parts placement and
routing guidelines is critical for optimal current reading
accuracy, IEEE compliance, system robustness, and ther-
mal dissipation.
at the V pin. Pull-downs at the logic pins should be to
DD
the protected side of the 10Ω resistors at the tied AGND
and DGND pins.
Finally, each port requires a pair of S1B clamp diodes, one
from OUTn to supply AGND (D3) and one from OUTn to
supply VEE (D4). The diodes at the ports steer harmful
surges into the supply rails where they are absorbed by
Power delivery above 25.5W imposes additional com-
ponent and layout restraints. Specifically MOSFET, sense
resistor and transformer selection is crucial to safe and
reliable system operation.
the surge suppressors and the V bypass capacitance.
EE
The layout of these paths must be low impedance.
Contact LTC Applications to obtain a full set of layout
guidelines, example layouts and BOMs.
4266acfe
29
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
pAckAge Description
Please refer to http://www.linear.com/product/LTC4266A#packaging for the most recent package drawings.
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
0.70 ± 0.05
5.50 ± 0.05
5.15 0.05
4.10 ± 0.05
3.15 0.05
3.00 REF
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
5.5 REF
6.10 ± 0.05
7.50 ± 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
0.75 ± 0.05
3.00 REF
5.00 ± 0.10
37 38
0.00 – 0.05
0.40 ±0.10
PIN 1
TOP MARK
1
2
(SEE NOTE 6)
5.15 0.10
5.50 REF
7.00 ± 0.10
3.15 0.10
(UH) QFN REF C 1107
0.200 REF 0.25 ± 0.05
R = 0.125
TYP
R = 0.10
TYP
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4266acfe
30
For more information www.linear.com/LTC4266A
LTC4266A/LTC4266C
revision history
REV
DATE
DESCRIPTION
PAGE NUMBER
A
8/11
Changed Gate Typical voltage to 12V.
3, 14, 21
2
Changed SCL, SDAIN V to 1.0V (I C compliance).
4
IL
Table 4 (Class) reference and caption changed to Table 5.
20
Power Supplies and Bypassing section changed to –45 for Type 1 minimum and –51 for Type 2 minimum.
Related Parts Table CUT/LIM changed to I /I
24
.
30
CUT LIM
++
B
02/12 Change LTPoE power levels from 35W, 45W to 38.7W, 52.7W respectively
1, 2, 15, 17
2
Revised MAX value for V I C Input Low Voltage
4
ILD
Clarified AUTO pin mode relationship to reset pin
18
17
C
D
08/12 Table 1: Changed twisted pair requirement from 2-pair to 4-pair for 38.7W and 52.7W
06/15 Updated surge protection recommendations
Simplified Power over Ethernet system diagram
Added component value (Figure 15)
Power level correction
1, 24, 26, 27, 30
16
25
1
E
07/17 Revised Figures 14 and 17.
25, 28
4266acfe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
31
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC4266A/LTC4266C
typicAl ApplicAtion
One Complete 100base-t Isolated Powered Ethernet IEEE 802.3at Port
ISOLATED
3.3V
10Ω
+
10µF
0.1µF
0.1µF
SMAJ5.0A
2k
V
DD
DGND
SCL
U2
SDAIN
SDAOUT
INT
200Ω
200Ω
1/4
LTC4266
V
CPU
DD
U1
10Ω
AGND
SCL
FB1
FB2
V
SENSE GATE OUT
EE
2k
0.22µF
100V
X7R
TVS
1µF
BULK
S1B
+
100V
X7R
C
BULK
R
SENSE
0.25Ω
SMAJ58A
SDA
Q1
HCPL-063L
ISOLATED
–54V
S1B
U3
RJ45
CONNECTOR
200Ω
200Ω
T1
1
2
•
•
•
•
0.01µF
200V
0.01µF
200V
3
4
5
6
7
8
75Ω
75Ω
INTERRUPT
PHY
0.1µF
GND CPU
(NETWORK
PHYSICAL
LAYER
HCPL-063L
CHIP)
•
•
•
•
0.01µF
200V
0.01µF
200V
75Ω
75Ω
Q1: FAIRCHILD IRFM120A OR PHILIPS PHT6NQ10T
U1: FAIRCHILD NC7WZ17
U2, U3: AGILENT HCPL-063L
FB1, FB2: TDK MPZ2012S601A
T1: PULSE H6096NL OR COILCRAFT ETH1-230LD
4266AC TA02
1000pF
2000V
relAteD pArts
PART NUMBER
LTC4270/LTC4271
LTC4266
DESCRIPTION
COMMENTS
Transformer Isolation, Supports Type 1, Type 2 and LTPoE PDs
2-Event Classification, Programmable I /I
+
++
++
12-Port PoE/PoE /LTPoE PSE Controller
Quad IEEE 802.3at PoE PSE Controller
Single IEEE 802.3at PoE PSE Controller
Single IEEE 802.3at PoE PSE Controller
IEEE 802.3at PD Interface Controller
CUT LIM
LTC4274
2-Event Classification, Programmable I /I
CUT LIM
LTC4274A/LTC4274C
LTC4265
13W through 90W Support
100V, 1A Internal Switch, 2-Event Classification Recognition
LTC4267
IEEE 802.3af PD Interface with Integrated Switching
Regulator
Internal 100V, 400mA Switch, Dual Inrush Current,
Programmable Class
LTC4269-1
LTC4269-2
LTC4278
IEEE 802.3at PD Interface with Integrated Flyback
Switching Regulator
2-Event Classification, Programmable Classification, Synchronous
No-Opto Flyback Controller, 50kHz to 250kHz, Auxiliary Support
IEEE 802.3at PD Interface with Integrated Forward
Switching Regulator
2-Event Classification, Programmable Classification, Synchronous
Forward Controller, 100kHz to 500kHz, Auxiliary Support
IEEE 802.3at PD Interface with Integrated Flyback
Switching Regulator
2-Event Classification, Programmable Classification, Synchronous
No-Opto Flyback Controller, 50kHz to 250kHz, 12V Auxiliary Support
4266acfe
LT 0717 REV E • PRINTED IN USA
www.linear.com/LTC4266A
32
LINEAR TECHNOLOGY CORPORATION 2011
相关型号:
LTC4266AIUHF-3#PBF
LTC4266A/LTC4266C - Quad PoE/PoE+/LTPoE++ PSE Controller; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C
Linear
LTC4266AIUHF-3#TRPBF
LTC4266A/LTC4266C - Quad PoE/PoE+/LTPoE++ PSE Controller; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C
Linear
LTC4266CIUHF#PBF
LTC4266A/LTC4266C - Quad PoE/PoE+/LTPoE++ PSE Controller; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C
Linear
LTC4266CUHF#PBF
LTC4266 - Quad IEEE 802.3at Power Over Ethernet Controller; Package: QFN; Pins: 38; Temperature Range: 0°C to 70°C
Linear
LTC4266IUHF#PBF
LTC4266 - Quad IEEE 802.3at Power Over Ethernet Controller; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明