LTC4267-1_技术文档

LTC4267-1

Power over Ethernet

IEEE 802.3af PD Interface with

Integrated Switching Regulator

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FEATURES

DESCRIPTIO

Complete Power Interface Port for IEEE 802^®.3af

The LTC^®4267-1 combines an IEEE 802.3af compliant

PoweredDevice(PD)interfacewithacurrentmodeswitch-

ing regulator, providing a complete power solution for PD

applications. The LTC4267-1 integrates the 25k signature

resistor, classiﬁcation current source, thermal overload

protection, signaturedisableandpowergoodsignalalong

with an undervoltage lockout optimized for use with the

IEEE-required diode bridge. The LTC4267-1 provides an

increased operational current limit, maximizing power

available for class 3 applications.

■

Powered Device (PD)

■

Onboard 100V, UVLO Switch

■

Precision Dual Level Inrush Current Limit

■

Integrated Current Mode Switching Regulator

■

Onboard 25k Signature Resistor with Disable

■

Programmable Classiﬁcation Current (Class 0-4)

■

Thermal Overload Protection

Power Good Signal

■

Integrated Error Ampliﬁer and Voltage Reference

Low Proﬁle 16-Pin SSOP Package

■

The current mode switching regulator is designed for

driving a 6V rated N-channel MOSFET and features pro-

grammable slope compensation, soft-start, and constant

frequency operation, minimizing noise even with light

loads. The LTC4267-1 includes an onboard error ampliﬁer

and voltage reference allowing use in both isolated and

nonisolated conﬁgurations.

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APPLICATIO S

■

IP Phone Power Management

■

Wireless Access Points

■

Security Cameras

Power over Ethernet

■

The LTC4267-1 is available in a space saving, low proﬁle

16-pin SSOP package.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

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TYPICAL APPLICATIO

Class 2 PD with 3.3V Isolated Power Supply

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42671f

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LTC4267-1

W W U W

PIN CONFIGURATION

ABSOLUTE AXI U RATI GS

(Note 1)

501ꢏ7*&8

V

P

with Respect to V

Voltage...0.3V to –100V

PORTN

, SIGDISA, PWRGD

OUT

PORTP

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Voltage..................... V

+ 100V to V

–0.3V

PORTN

/("5&

4&/4&

P

to PGND Voltage (Note 2)

VCC

1

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Low Impedance Source ...........................–0.3V to 8V

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Current Fed..........................................5mA into P

VCC

– 0.3V

/$

R

Voltage.................V

+ 7V to V

CLASS

⎯ ⎯ ⎯ ⎯

PORTN

7

1

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⎯

PWRGD Current.....................................................10mA

Current.....................................................100mA

1(/%

R

CLASS

(/ꢏ1"$,"(&

ꢆꢃꢅ-&"%ꢏ/"3308ꢏ1-"45*$ꢏ4401

= 150°C, θ = 90°C/W

NGATE to PGND Voltage ...........................–0.3V to P

VCC

T

JMAX

JA

V , I /RUN to PGND Voltages................–0.3V to 3.5V

FB TH

SENSE to PGND Voltage ..............................–0.3V to 1V

NGATE Peak Output Current (<10μs) ..........................1A

Operating Ambient Temperature Range

LTC4267C-1............................................. 0°C to 70°C

LTC4267I-1..........................................–40°C to 85°C

Junction Temperature ........................................... 150°C

Storage Temperature Range...................–65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC4267CGN-1#PBF

LTC4267IGN-1#PBF

LTC4267CGN-1#TRPBF

LTC4267IGN-1#TRPBF

4267-1

4267I-1

16-Lead Narrow Plastic SSOP

0°C to 70°C

–40°C to 85°C

LEAD BASED FINISH

TAPE AND REEL

PART MARKING

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC4267CGN-1

LTC4267IGN-1

LTC4267CGN-1#TR

LTC4267IGN-1#TR

4267-1

4267I-1

16-Lead Narrow Plastic SSOP

0°C to 70°C

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

*For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

The ● denotes the speciﬁcations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Supply Voltage

Maximum Operating Voltage

Signature Range

Classiﬁcation Range

UVLO Turn-On Voltage

UVLO Turn-Off Voltage

Voltage with Respect to V

(Notes 4, 5, 6)

PORTP

PORTN

●

–57

–9.5

–21

–37.2

–31.5

V

–1.5

–12.5

–34.8

–29.3

–36.0

–30.5

V

P

Turn-On Voltage

Turn-Off Voltage

Hysteresis

Voltage with Respect to PGND

●

7.8

4.6

1.5

8.7

5.7

3.0

9.2

6.8

V

TURNON

TURNOFF

HYST

VCC

V

– V

V

TURNON

TURNOFF

42671f

2

LTC4267-1

The ● denotes the speciﬁcations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS

= 1mA, V /RUN = 0V, Voltage

MIN

TYP

MAX

UNITS

V

P

VCC

Shunt Regulator Voltage

I

●

8.3

9.4

10.3

V

CLAMP1mA

PVCC

ITH

with Respect to PGND

V

P

– V Margin

TURNON

●

0.05

0.6

V

MARGIN

CLAMP1mA

⎯

OUT

⎯

I

Supply Current when ON

V

= –48V, P , PWRGD, SIGDISA Floating

3

mA

VPORTN_ON

PVCC_ON

PORTN

Supply Current

(Note 7)

VCC

Normal Operation

Start-Up

V

P

/RUN – PGND = 1.3V

●

240

40

350

90

ꢀA

ITH

– PGND = V

– 100mV

VCC

TURNON

I

V

Supply Current

V

= –17.5V, P

Tied to V , R ,

PORTP CLASS

●

0.35

0.5

0.65

mA

VPORTN_CLASS

PORTN

OUT

During Classiﬁcation

SIGDISA Floating (Note 8)

ΔI

Current Accuracy

During Classiﬁcation

10mA < I

(Note 9)

< 40mA, –12.5V ≤ V

≤ –21V

3.5

%

CLASS

PORTN

R

Signature Resistance

–1.5V ≤ V

≤ – 9.5V, P

Tied to V ,

PORTP

23.25

26.00

11.8

kΩ

SIGNATURE

PORTN

OUT

IEEE 802.3af 2-Point Measurement (Notes 4, 5)

Invalid Signature Resistance

–1.5V ≤ V ≤ – 9.5V, SIGDISA and P Tied to

9

INVALID

PORTN

OUT

V

, IEEE 802.3af 2-Point Measurement

PORTP

(Notes 4, 5)

V

Signature Disable

High Level Input Voltage

With Respect to V

High Level Invalidates Signature (Note 10)

●

3

57

V

IH

PORTN

Signature Disable

Low Level Input Voltage

With Respect to V

0.45

IL

PORTN

Low Level Enables Signature

R

Signature Disable, Input Resistance With Respect to V

●

100

kΩ

INPUT

PORTN

V

Power Good Output Low Voltage

I = 1mA V

PWRGD Referenced to V

= –48V,

0.5

V

PG_OUT

PORTN

⎯

PORTN

Power Good Trip Point

V

= –48V, Voltage between V

Falling

Rising

and P

PORTN OUT

PORTN

V

P

●

1.3

2.7

1.5

3.0

1.7

3.3

V

PG _FALL

PG_RISE

OUT

⎯

I

Power Good Leakage Current

On-Resistance

V

= 0V, PWRGD FET Off, V = 57V

⎯ ⎯ ⎯ ⎯ ⎯

●

1

ꢀA

PG_LEAK

PORTN

PWRGD

R

I = 300mA, V

= –48V, Measured from

PORTN

OUT

1.0

1.6

2

Ω

ON

V

P

V

to P

●

PORTN

V

I

Shutdown Threshold (at I /RUN)

– PGND = V + 100mV

TURNON

0.15

0.2

0.28

0.3

0.45

0.4

V

ꢀA

ITHSHDN

TH

VCC

Start-Up Current Source at I /RUN

/RUN – PGND = 0V, P

ITH

– P

= 8V

VCC

– P

GND

= 8V (Note 11)

THSTART

TH

V

Regulated Feedback Voltage

Referenced to PGND, P

VCC

●

0.780

0.800

10

0.812

50

V

GND

FB

I

FB

V

Input Current

FB

P

– P

= 8V (Note 11)

VCC GND

/RUN Pin Load = 5ꢀA (Note 11)

nA

g

Error Ampliﬁer Transconductance

Output Voltage Line Regulation

Output Voltage Load Regulation

I

200

333

0.05

500

ꢀA/V

mV/V

m

TH

ΔV

V

< P

< V

(Note 11)

O(LINE)

TURNOFF

VCC

CLAMP

I

/RUN Sinking 5ꢀA, P

VCC

/RUN Sourcing 5ꢀA, P

GND

= 0V, Power MOSFET Off,

PORTN

– P

VCC

= 8V (Note 11)

3

mV/ꢀA

GND

– P = 8V (Note 11)

O(LOAD)

TH

I

TH

I

P

Leakage

V

P

●

150

ꢀA

POUT_LEAK

OUT

= 57V (Note 12)

OUT

I

f

Input Current Limit, High Level

Input Current Limit, Low Level

Oscillator Frequency

V

= –48V, P

= –43V (Note 13, 14)

●

350

90

450

205

240

8

mA

kHz

%

LIM_HI

LIM_LO

OSC

PORTN

OUT

= –48V, P

= –43V (Note 13, 14)

– P = 8V

/RUN – PGND = 1.3V, P

VCC

180

200

6

GND

ITH

DC

Minimum Switch On Duty Cycle

V

P

/RUN – PGND = 1.3V, V – PGND = 0.8V,

ON(MIN)

ITH

VCC

FB

– P

= 8V

GND

DC

Maximum Switch On Duty Cycle

V

P

/RUN – PGND = 1.3V, V – PGND = 0.8V,

70

80

90

%

ON(MAX)

ITH

FB

– P

= 8V

VCC

GND

42671f

3

LTC4267-1

The ● denotes the speciﬁcations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

40

MAX

UNITS

ns

t

NGATE Drive Rise Time

C

= 3000pF, P

– P

= 8V

VCC

GND

RISE

LOAD

t

NGATE Drive Fall Time

= 3000pF, P

40

ns

FALL

V

Peak Current Sense Voltage

Peak Slope Compensation Output Current

Soft-Start Time

R

= 0, P

– P

= 8V (Note 15)

●

90

100

5

115

mV

ꢀA

VCC

GND

IMAX

SL

I

P

– P

= 8V (Note 16)

= 8V

VCC

SLMAX

t

1.4

140

ms

°C

VCC

SFST

T

Thermal Shutdown Trip Temperature

(Notes 13, 17)

SHUTDOWN

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

R

. The current accuracy does not include variations in R

CLASS

resistance. The total classiﬁcation current for a PD also includes the IC

quiescent current (I ). See Applications Information.

Note 10: To disable the 25k signature, tie SIGDISA to V

VPORTN_CLASS

or hold

PORTP

Note 2: P

internal clamp circuit self regulates to 9.4V with respect to

SIGDISA high with respect to V

. See Applications Information.

PORTN

VCC

PGND.

Note 11: The switching regulator is tested in a feedback loop that servos

to the output of the error ampliﬁer while maintaining I /RUN at the

Note 3: The LTC4267-1 operates with a negative supply voltage in the

range of – 1.5V to – 57V. To avoid confusion, voltages for the PD interface

are always referred to in terms of absolute magnitude. Terms such as

“maximum negative voltage” refer to the largest negative voltage and

a “rising negative voltage” refers to a voltage that is becoming more

negative.

Note 4: The LTC4267-1 is designed to work with two polarity protection

diode drops between the PSE and PD. Parameter ranges speciﬁed in the

Electrical Characteristics section are with respect to this product pins and

are designed to meet IEEE 802.3af speciﬁcations when these diode drops

are included. See the Application Information section.

V

FB

TH

midpoint of the current limit range.

Note 12: I includes current drawn through P

good status circuit. This current is compensated for in the 25k signature

resistance and does not affect PD operation.

Note 13: The LTC4267-1 PD Interface includes thermal protection. In

the event of an overtemperature condition, the PD interface will turn off

the switching regulator until the part cools below the overtemperature

limit. The LTC4267-1 is also protected against thermal damage from

incorrect classiﬁcation probing by the PSE. If the LTC4267-1 exceeds the

overtemperature threshold, the classiﬁcation load current is disabled.

by the power

OUT

POUT_LEAK

Note 5: Signature resistance is measured via the two-point ΔV/ΔI method

as deﬁned by IEEE 802.3af. The PD signature resistance is offset from

the 25k to account for diode resistance. With two series diodes, the total

PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af

speciﬁcations. The minimum probe voltages measured at the LTC4267-1

pins are –1.5V and –2.5V. The maximum probe voltages are –8.5V and

–9.5V.

Note 6: The PD interface includes hysteresis in the UVLO voltages to

preclude any start-up oscillation. Per IEEE 802.3af requirements, the PD

will power up from a voltage source with 20Ω series resistance on the ﬁrst

trial.

Note 14: The PD interface includes dual level input current limit. At turn-

on, before the P

to a low level. After the load capacitor is charged and the P

load capacitor is charged, the PD current level is set

OUT

– V

OUT

PORTN

voltage difference is below the power good threshold, the PD switches to

high level current limit. The PD stays in high level current limit until the

input voltage drops below the UVLO turn-off threshold.

Note 15: Peak current sense voltage is reduced dependent on duty cycle

and an optional external resistor in series with the SENSE pin (R ). For

SL

details, refer to the programmable slope compensation feature in the

Applications Information section.

Note 16: Guaranteed by design.

Note 17: The PD interface includes overtemperature protection that is

intended to protect the device from momentary overload conditions.

Junction temperature will exceed 125°C when overtemperature protection

is active. Continuous operation above the speciﬁed maximum operating

junction temperature may impair device reliability.

Note 7: Dynamic Supply current is higher due to the gate charge being

delivered at the switching frequency.

Note 8: I

programmed at the R

does not include classiﬁcation current

VPORTN_CLASS

pin. Total current in classiﬁcation mode will be

CLASS

I

+ I

CLASS

(See note 9).

VPORTN_CLASS

Note 9: I

is the measured current ﬂowing through R

. ΔI

CLASS

CLASS CLASS

accuracy is with respect to the ideal current deﬁned as I

= 1.237/

CLASS

42671f

4

LTC4267-1

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Input Current vs Input Voltage

25k Detection Range

Input Current vs Input Voltage

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Signature Resistance vs

Input Voltage

Normalized UVLO Threshold vs

Temperature

Input Current vs Input Voltage

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Power Good Output Low Voltage

vs Current

P_OUTLeakage Current

Current Limit vs Input Voltage

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42671f

5

LTC4267-1

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Oscillator Frequency vs

Temperature

Reference Voltage vs

Temperature

Reference Voltage vs

Supply Voltage

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P_VCCUndervoltage Lockout

Thresholds vs Temperature

Oscillator Frequency vs

Supply Voltage

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_VCCShunt Regulator Voltage vs

I_PVCCSupply Current vs

Temperature

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42671f

6

LTC4267-1

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Start-Up I_PVCCSupply Current vs

Temperature

I_TH/RUN Shutdown Threshold vs

Temperature

I_TH/RUN Start-Up Current Source

vs Temperature

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Peak Current Sense Voltage vs

Temperature

Soft-Start Time vs Temperature

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42671f

7

LTC4267-1

U

PI FU CTIO S

PGND (Pin 1, 8, 9, 16): Switching Regulator Negative

is high impedance until the voltage reaches the turn-on

UVLO threshold. The output is then current limited. See

the Application Information section.

Supply.Thispinisthenegativesupplyrailfortheswitching

regulator controller and must be tied to P

.

OUT

⎯ ⎯ ⎯ ⎯ ⎯

PWRGD (Pin 11): Power Good Output, Open-Drain.

I /RUN (Pin 2): Current Threshold/Run Input. This

TH

pin performs two functions. It serves as the switching

regulator error ampliﬁer compensation point as well as

the run/shutdown control input. Nominal voltage range is

0.7V to 1.9V. Forcing the pin below 0.28V with respect to

PGND causes the controller to shut down.

Indicates that the PD MOSFET is on and the switching

regulator can start operation. Low impedance indicates

⎯

power is good. PWRGD is high impedance during detec-

tion, classiﬁcation and in the event of a thermal overload.

⎯ ⎯ ⎯ ⎯ ⎯

PWRGD is referenced to V

.

PORTN

NGATE (Pin 3): Gate Driver Output. This pin drives the

SIGDISA (Pin 12): Signature Disable Input. SIGDISA al-

regulator’s external N-Channel MOSFET and swings from

lows the PD to present an invalid signature resistance and

PGND to P

.

remain inactive. Connecting SIGDISA to V

lowers

VCC

PORTP

the signature resistance to an invalid value and disables

all functions of the LTC4267-1. If unused, tie SIGDISA to

PORTN

P

(Pin 4): Switching Regulator Positive Supply. This

VCC

pin is the positive supply rail for the switching regulator

V

.

and must be closely decoupled to PGND.

V

(Pin 13): Positive Power Input. Tie to the input

PORTP

R

(Pin 5): Class Select Input. Used to set the current

CLASS

port power return through the input diodes.

value the PD maintains during classiﬁcation. Connect a

resistor between R and V (see Table 2).

SENSE (Pin 14): Current Sense. This pin performs two

functions.Itmonitorstheregulatorswitchcurrentbyread-

ing the voltage across an external sense resistor. It also

injectsacurrentrampthatdevelopsaslopecompensation

voltageacrossanoptionalexternalprogrammingresistor.

See the Applications Information section.

CLASS

PORTN

NC (Pin 6): No Internal Connection.

(Pin 7): Negative Power Input. Tie to the –48V

V

PORTN

input port through the input diodes.

P

(Pin10):PowerOutput.Supplies–48Vtotheswitch-

OUT

ingregulatorPGNDpinandanyadditionalPDloadsthrough

V (Pin15):FeedbackInput.Receivesthefeedbackvoltage

FB

an internal power MOSFET that limits input current. P

from the external resistor divider across the output.

OUT

42671f

8

LTC4267-1

BLOCK DIAGRAM

7

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W U U

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APPLICATIO S I FOR ATIO

OVERVIEW

LTC4267-1hasbeenspeciﬁcallydesignedtointerfacewith

both IEEE compliant Power Sourcing Equipment (PSE)

and legacy PSEs which do not meet the inrush current

requirement of the IEEE 802.3af speciﬁcation. By setting

the initial inrush current limit to a low level, a PD using

the LTC4267-1 minimizes the current drawn from the PSE

duringstart-up.Afterpoweringup,theLTC4267-1switches

to the high level current limit, thereby allowing the PD to

consume up to 12.95W if an IEEE 802.3af PSE is present.

This low level current limit also allows the LTC4267-1 to

charge arbitrarily large load capacitors without exceeding

the inrush limits of the IEEE 802.3af speciﬁcation. This

dual level current limit provides the system designer with

ﬂexibility to design PDs which are compatible with legacy

PSEs while also being able to take advantage of the higher

power available in an IEEE 802.3af system.

The LTC4267-1 is partitioned into two major blocks: a

Powered Device (PD) interface controller and a current

mode ﬂyback switching regulator. The Powered Device

(PD) interface is intended for use as the front end of a

PD adhering to the IEEE 802.3af standard, and includes

a trimmed 25k signature resistor, classiﬁcation current

source, and an input current limit circuit. With these

functions integrated into the LTC4267-1, the signature

and power interface for a PD can be built that meets all

the requirements of the IEEE 802.3af speciﬁcation with a

minimum of external components.

The switching regulator portion of the LTC4267-1 is a

constant frequency current mode controller that is opti-

mized for Power over Ethernet applications. The regulator

is designed to drive a 6V N-channel MOSFET and features

soft-start and programmable slope compensation. The

integrated error ampliﬁer and precision reference give the

PD designer the option of using a nonisolated topology

withouttheneedforanexternalampliﬁerorreference. The

Using an LTC4267-1 for the power and signature inter-

face functions of a PD provides several advantages. The

LTC4267-1 current limit circuit includes an onboard 100V

power MOSFET. This low leakage MOSFET is speciﬁed to

42671f

9

LTC4267-1

W U U

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APPLICATIO S I FOR ATIO

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avoid corrupting the 25k signature resistor while also sav-

ing board space and cost. In addition, the inrush current

limit requirement of the IEEE 802.3af standard can cause

largetransientpowerdissipationinthePD.TheLTC4267-1

is designed to allow multiple turn-on sequences without

overheating the miniature 16-lead package. In the event of

excessive power cycling, the LTC4267-1 provides thermal

overload protection to keep the onboard power MOSFET

within its safe operating area.

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The LTC4267-1 PD interface has several modes of opera-

tion depending on the applied input voltage as shown in

Figure 1 and summarized in Table 1. These modes satisfy

therequirementsdeﬁnedintheIEEE802.3afspeciﬁcation.

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The input voltage is applied to the V

pin and must

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PORTN

be negative relative to the V

pin. Voltages in the data

PORTP

sheet for the PD interface portion of the LTC4267-1 are

with respect to V while the voltages for the switch-

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PORTP

7

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PGND is tied to P . Note the use of different ground

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Table 1. LTC4267-1 Operational Mode

as a Function of Input Voltage

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INPUT VOLTAGE

(V

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with RESPECT to V

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**Measured at LTC4267-1 pin. The LTC4267-1 meets the IEEE 802.3af 10V

minimum when operating with the required diode bridges.

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Figure 1. Output Voltage, PWRGD and PD

Current as a Function of Input Voltage

42671f

10

LTC4267-1

W U U

APPLICATIO S I FOR ATIO

U

Series Diodes

The signature range extends below the IEEE range to ac-

commodate the voltage drop of the two diodes. The IEEE

speciﬁcationrequiresthePSEtouseaΔV/ΔImeasurement

technique to keep the DC offset of these diodes from af-

fecting the signature resistance measurement. However,

the diode resistance appears in series with the signature

resistor and must be included in the overall signature

resistance of the PD. The LTC4267-1 compensates for

the two series diodes in the signature path by offsetting

the resistance so that a PD built using the LTC4267-1 will

meet the IEEE speciﬁcation.

The IEEE 802.3af-deﬁned operating modes for a PD refer-

ence the input voltage at the RJ45 connector on the PD.

The PD must be able to accept power of either polarity

at each of its inputs, so it is common to install diode

bridges (Figure 2). The LTC4267-1 takes this into account

by compensating for these diode drops in the threshold

points for each range of operation. A similar adjustment

is made for the UVLO voltages.

Detection

During detection, the PSE will apply a voltage in the

range of –2.8V to –10V on the cable and look for a 25k

signature resistor. This identiﬁes the device at the end of

the cable as a PD. With the terminal voltage in this range,

the LTC4267-1 connects an internal 25k resistor between

In some applications it is necessary to control whether

or not the PD is detected. In this case, the 25k signature

resistor can be enabled and disabled with the use of the

SIGDISA pin (Figure 3). Disabling the signature via the

SIGDISA pin will change the signature resistor to 9k

(typical) which is an invalid signature per the IEEE 802.3af

speciﬁcation. ThisinvalidsignatureispresentforPDinput

voltagesfrom–2.8Vto–10V.Iftheinputrisesabove–10V,

the signature resistor reverts to 25k to minimize power

dissipation in the LTC4267-1. To disable the signature,

the V

and V

pins. This precision, temperature

PORTP

PORTN

compensated resistor presents the proper signature to

alert the PSE that a PD is present and desires power to be

applied. The internal low-leakage UVLO switch prevents

the switching regulator circuitry from affecting the detec-

tion signature.

tie SIGDISA to V

. Alternately, the SIGDISA pin can

PORTP

be driven high with respect to V

. When SIGDISA is

PORTN

The LTC4267-1 is designed to compensate for the voltage

and resistance effects of the IEEE required diode bridge.

high, all functions of the PD interface are disabled.

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Figure 2. LTC4267-1 PD Front End Using

Diode Bridges on Main and Spare Inputs

42671f

11

LTC4267-1

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Figure 3. 25k Signature Resistor with Disable

14&

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Classiﬁcation

Figure 4. IEEE 802.3af Classiﬁcation Probing

Once the PSE has detected a PD, the PSE may option-

ally classify the PD. Classiﬁcation provides a method for

more efﬁcient allocation of power by allowing the PSE

to identify lower power PDs and allocate less power for

these devices. The IEEE 802.3af speciﬁcation deﬁnes ﬁve

classes (Table 2) with varying power levels. The designer

selects the appropriate classiﬁcation based on the power

consumption of the PD. For each class, there is an as-

sociated load current that the PD asserts onto the line

during classiﬁcation probing. The PSE measures the PD

load current to determine the proper classiﬁcation and

PD power requirements.

The IEEE 802.3af speciﬁcation limits the classiﬁcation

time to 75ms because a signiﬁcant amount of power is

dissipated in the PD. The LTC4267-1 is designed to handle

the power dissipation for this time period. If the PSE prob-

ing exceeds 75ms, the LTC4267-1 may overheat. In this

situation, the thermal protection circuit will engage and

disabletheclassiﬁcationcurrentsourceinordertoprotect

the part. The LTC4267-1 stays in classiﬁcation mode until

the input voltage rises above the UVLO turn-on voltage.

V

Undervoltage Lockout

PORTN

TheIEEEspeciﬁcationdictatesamaximumturn-onvoltage

of 42V and a minimum turn-off voltage of 30V for the PD.

Inaddition,thePDmustmaintainlargeon-offhysteresisto

prevent resistive losses in the wiring between the PSE and

the PD from causing start-up oscillation. The LTC4267-1

incorporates an undervoltage lockout (UVLO) circuit that

During classiﬁcation (Figure 4), the PSE presents a ﬁxed

voltage between –15.5V and –20.5V to the PD. With the

input voltage in this range, the LTC4267-1 asserts a load

current from the V

pin through the R

resistor.

PORTP

CLASS

The magnitude of the load current is set by the R

CLASS

resistor.Theresistorvaluesassociatedwitheachclassare

shown in Table 2. Note that the switching regulator will

notinterferewiththeclassiﬁcationmeasurementsincethe

LTC4267-1 has not passed power to the regulator.

monitors the line voltage at V

to determine when

PORTN

to apply power to the integrated switching regulator

(Figure 5). Before the power is applied to the switching

regulator, the P

pin is high impedance and sitting at

OUT

the ground potential since there is no charge on capacitor

C1. When the input voltage rises above the UVLO turn-on

threshold, theLTC4267-1removesthedetectionandclas-

siﬁcation loads and turns on the internal power MOSFET.

C1 charges up under the LTC4267-1 current limit control

Table 2. Summary of IEEE 802.3af Power Classiﬁcations and

LTC4267-1 R_CLASSResistor Selection

Maximum

Power Levels

at Input of PD

(W)

Nominal

Classiﬁcation

Load Current

(mA)

LTC4267-1

R

CLASS

Resistor

Class

Usage

Default

(Ω, 1%)

and the P

pin transitions from 0V to V

. This

OUT

PORTN

0

1

2

3

4

0.44 to 12.95

0.44 to 3.84

3.84 to 6.49

6.49 to 12.95

Reserved*

<5

10.5

18.5

28

Open

124

sequence is shown in Figure 1. The LTC4267-1 includes

a hysteretic UVLO circuit on V that keeps power

Optional

Reserved

PORTN

68.1

45.3

30.9

applied to the load until the input voltage falls below the

UVLO turn-off threshold. Once the input voltage drops

below –30V, the internal power MOSFET is turned off and

40

*Class 4 is currently reserved and should not be used.

42671f

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LTC4267-1

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the classiﬁcation current is reenabled. C1 will discharge

limit because the load capacitor is charged with a current

below the IEEE inrush current limit speciﬁcation.

through the PD circuitry and the P

impedance state.

pin will go to a high

OUT

As the LTC4267-1 switches from the low to high level

current limit, the current will increase momentarily. This

current spike is a result of the LTC4267-1 charging the

last 1.5V at the high level current limit. When charging a

10ꢀF capacitor, the current spike is typically 100ꢀs wide

and 125% of the nominal low level current limit.

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The LTC4267-1 stays in the high level current limit mode

until the input voltage drops below the UVLO turn-off

threshold. This dual level current limit provides the sys-

tem designer with the ﬂexibility to design PDs which are

compatible with legacy PSEs while also being able to take

advantage of the higher power allocation available in an

IEEE 802.3af system.

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During the current limited turn on, a large amount of

power is dissipated in the power MOSFET. The LTC4267-1

PD interface is designed to accept this thermal load and

is thermally protected to avoid damage to the onboard

power MOSFET. Note that in order to adhere to the IEEE

802.3af standard, it is necessary for the PD designer to

ensurethePDsteadystatepowerconsumptionfallswithin

the limits shown in Table 2. In addition, the steady state

Figure 5. LTC4267-1 V_PORTNUndervoltage Lockout

Input Current Limit

IEEE 802.3af speciﬁes a maximum inrush current and

also speciﬁes a minimum load capacitor between the

V

and P

pins. To control turn-on surge current

PORTP

OUT

in the system, the LTC4267-1 integrates a dual level cur-

rent limit circuit with an onboard power MOSFET and

sense resistor to provide a complete inrush control circuit

without additional external components. At turn-on, the

LTC4267-1 will limit the input current to the low level,

allowing the load capacitor to ramp up to the line voltage

in a controlled manner.

current must be less than I

.

LIM_HI

Power Good

TheLTC4267-1PDInterfaceincludesapowergoodcircuit

(Figure 6) that is used to indicate that load capacitor C1

is fully charged and that the switching regulator can start

operation. The power good circuit monitors the voltage

TheLTC4267-1hasbeenspeciﬁcallydesignedtointerface

with legacy PSEs which do not meet the inrush current

requirement of the IEEE 802.3af speciﬁcation. At turn-on

the LTC4267-1 current limit is set to the lower level. After

⎯

across the internal UVLO power MOSFET and PWRGD is

asserted when the voltage falls below 1.5V. The power

goodcircuitincludeshysteresistoallowtheLTC4267-1to

operate near the current limit point without inadvertently

C1 is charged up and the P – V

voltage difference

OUT

PORTN

isbelowthepowergoodthreshold,theLTC4267-1switches

to the high level current limit. The dual level current limit

allowslegacyPSEswithlimitedcurrentsourcingcapability

to power up the PD while also allowing the PD to draw full

power from an IEEE 802.3af PSE. The dual level current

limit also allows use of arbitrarily large load capacitors.

The IEEE 802.3af speciﬁcation mandates that at turn-on

the PD not exceed the inrush current limit for more than

50ms. The LTC4267-1 is not restricted to the 50ms time

⎯

⎯ ⎯ ⎯ ⎯

disabling PWRGD. The MOSFET voltage must increase to

⎯

3V before PWRGD is disabled.

If a sudden increase in voltage appears on the input line,

this voltage step will be transferred through capacitor C1

andappearacrossthepowerMOSFET.Theresponseofthe

LTC4267-1 will depend on the magnitude of the voltage

step, the rise time of the step, the value of capacitor C1

and the switching regulator load. For fast rising inputs,

42671f

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the LTC4267-1 will attempt to quickly charge capacitor C1

using an internal secondary current limit circuit. In this

scenario, the PSE current limit should provide the overall

limit for the circuit. For slower rising inputs, the 375mA

current limit in the LTC4267-1 will set the charge rate of

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⎯

the capacitor C1. In either case, the PWRGD signal may

go inactive brieﬂy while the capacitor is charged up to the

new line voltage. In the design of a PD, it is necessary

to determine if a step in the input voltage will cause the

Figure 7. Power Good Interface Examples

PD Interface Thermal Protection

The LTC4267-1 PD Interface includes thermal overload

protection in order to provide full device functionality

in a miniature package while maintaining safe operating

temperatures. Several factors create the possibility of

signiﬁcant power dissipation within the LTC4267-1. At

turn-on, before the load capacitor has charged up, the

instantaneous power dissipated by the LTC4267-1 can be

as much as 10W. As the load capacitor charges up, the

power dissipation in the LTC4267-1 will decrease until it

reaches a steady-state value dependent on the DC load

current. Thesizeoftheloadcapacitordetermineshowfast

the power dissipation in the LTC4267-1 will subside. At

roomtemperature,theLTC4267-1cantypicallyhandleload

capacitors as large as 800ꢀF without going into thermal

shutdown. With large load capacitors, the LTC4267-1 die

temperature will increase by as much as 50°C during a

single turn-on sequence. If for some reason power were

removed from the part and then quickly reapplied so that

the LTC4267-1 had to charge up the load capacitor again,

the temperature rise would be excessive if safety precau-

tions were not implemented.

⎯

PWRGD signal to go inactive and how to respond to this

event. In some designs, it may be desirable to ﬁlter the

PWRGD signal so that intermittent power bad conditions

are ignored. Figure 7 demonstrates a method to insert a

lowpass ﬁlter on the power good interface.

⎯

For PD designs that use a large load capacitor and also con-

sume a lot of power, it is important to delay activation of the

⎯

switching regulator with thePWRGD signal. If the regulator

isnotdisabledduringthecurrent-limitedturn-onsequence,

the PD circuitry will rob current intended for charging up

the load capacitor and create a slow rising input, possibly

causing the LTC4267-1 to go into thermal shutdown.

⎯

The PWRGD pin connects to an internal open drain, 100V

transistor capable of sinking 1mA. Low impedance to

⎯

V

indicates power is good. PWRGD is high imped-

PORTN

ance during signature and classiﬁcation probing and in

⎯

the event of a thermal overload. During turn-off, PWRGD

is deactivated when the input voltage drops below 30V.

⎯

In addition, PWRGD may go active brieﬂy at turn-on for

⎯

fast rising input waveforms. PWRGD is referenced to the

pin and when active, will be near the V po-

V

PORTN

The LTC4267-1 PD interface protects itself from thermal

damage by monitoring the die temperature. If the die

⎯

tential. ConnectthePWRGDpintotheswitchingregulator

circuitry as shown in Figure 7.

42671f

14

LTC4267-1

W U U

APPLICATIO S I FOR ATIO

U

temperature exceeds the overtemperature trip point, the

current is reduced to zero and very little power is dissi-

pated in the part until it cools below the overtemperature

set point. Once the LTC4267-1 has charged up the load

capacitor and the PD is powered and running, there will

be minor residual heating due to the DC load current of

the PD ﬂowing through the internal MOSFET.

In the typical application circuit (Figure 11), the isolated

topology employs an external resistive voltage divider

to present a fraction of the output voltage to an external

error ampliﬁer. The error ampliﬁer responds by pulling

an analog current through the input LED on an optoiso-

lator. The collector of the optoisolator output presents a

corresponding current into the I /RUN pin via a series

TH

diode. This method generates a feedback voltage on the

I /RUN pin while maintaining isolation.

TH

During classiﬁcation, excessive heating of the LTC4267-1

can occur if the PSE violates the 75ms probing time limit.

To protect the LTC4267-1, thermal overload circuitry will

disableclassiﬁcationcurrentifthedietemperatureexceeds

the overtemperature trip point. When the die cools down

below the trip point, classiﬁcation current is reenabled.

The voltage on the I /RUN pin controls the pulse-width

TH

modulator formed by the oscillator, current comparator,

and RS latch. Speciﬁcally, the voltage at the I /RUN pin

TH

sets the current comparator’s trip threshold. The current

comparator monitors the voltage across a sense resistor

in series with the source terminal of the external N-Chan-

nel MOSFET. The LTC4267-1 turns on the external power

MOSFET when the internal free-running 200kHz oscillator

sets the RS latch. It turns off the MOSFET when the cur-

rent comparator resets the latch or when 80% duty cycle

is reached, whichever happens ﬁrst. In this way, the peak

current levels through the ﬂyback transformer’s primary

The PD is designed to operate at a high ambient tem-

perature and with the maximum allowable supply (57V).

However, there is a limit to the size of the load capacitor

that can be charged up before the LTC4267-1 reaches the

overtemperaturetrippoint.Hittingtheovertemperaturetrip

point intermittently does not harm the LTC4267-1, but it

willdelaythecompletionofcapacitorcharging.Capacitors

up to 200ꢀF can be charged without a problem over the

full operating temperature range.

and secondary are controlled by the I /RUN voltage.

TH

In applications where a nonisolated topology is desirable

(Figure 11), an external resistive voltage divider can pres-

Switching Regulator Main Control Loop

ent a fraction of the output voltage directly to the V pin

FB

Due to space limitations, the basics of current mode

DC/DC conversion will not be discussed here. The reader

is referred to the detail treatment in Application Note 19

or in texts such as Abraham Pressman’s Switching Power

Supply Design.

of the LTC4267-1. The divider must be designed so when

the output is at its desired voltage, the V pin voltage will

FB

equal the 800mV onboard internal reference. The internal

error ampliﬁer responds by driving the I /RUN pin. The

TH

LTC4267-1 switching regulator performs in a similar

In a Power over Ethernet System, the majority of applica-

tionsinvolveanisolatedpowersupplydesign. Thismeans

that the output power supply does not have any DC elec-

trical path to the PD interface or the switching regulator

primary. The DC isolation is achieved typically through

a transformer in the forward path and an optoisolator in

the feedback path or a third winding in the transformer.

The typical application circuit shown on the front page

of the datasheet represents an isolated design using an

optoisolator.Inapplicationswhereanonisolatedtopology

is desired, the LTC4267-1 features a feedback port and

an internal error ampliﬁer that can be enabled for this

speciﬁc application.

manner as described previously.

Regulator Start-Up/Shutdown

The LTC4267-1 switching regulator has two shutdown

mechanisms to enable and disable operation: an un-

dervoltage lockout on the P

supply pin and a forced

VCC

shutdown whenever external circuitry drives the I /RUN

TH

pin low. The LTC4267-1 switcher transitions into and out

of shutdown according to the state diagram (Figure 8).

It is important not to confuse the undervoltage lockout

of the PD interface at V

with that of the switching

PORTN

regulator at P . They are independent functions.

VCC

42671f

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LTC4267-1

W U U

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APPLICATIO S I FOR ATIO

Adjustable Slope Compensation

,4#ꢀꢁꢂꢃꢄꢅ

07-

The LTC4267-1 switching regulator injects a 5ꢀA peak

current ramp out through its SENSE pin which can be

used for slope compensation in designs that require it.

This current ramp is approximately linear and begins at

zero current at 6% duty cycle, reaching peak current at

80% duty cycle. Programming the slope compensation

via a series resistor is discussed in the External Interface

and Component Selection section.

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Figure 8. LTC4267-1 Switching Regulator

Start-Up/Shutdown State Diagram

EXTERNAL INTERFACE AND COMPONENT SELECTION

Input Interface Transformer

The undervoltage lockout mechanism on P

prevents

VCC

the LTC4267-1 switching regulator from trying to drive

the external N-Channel MOSFET with insufﬁcient gate-to-

Nodes on an Ethernet network commonly interface to the

outside world via an isolation transformer (Figure 9). For

PoE devices, the isolation transformer must include a

center tap on the media (cable) side. Proper termination

is required around the transformer to provide correct

impedance matching and to avoid radiated and conducted

emissions. Transformer vendors such as Bel Fuse, Coil-

craft, PulseandTyco(Table3)canprovideassistancewith

selectionofanappropriateisolationtransformerandproper

termination methods. These vendors have transformers

speciﬁcally designed for use in PD applications.

source voltage. The voltage at the P

pin must exceed

VCC

V

(nominally 8.7V with respect to PGND) at least

TURNON

momentarily to enable operation. The P

voltage must

VCC

fall to V

(nominally 5.7V with respect to PGND)

TURNOFF

before the undervoltage lockout disables the switching

regulator. This wide UVLO hysteresis range supports

applications where a bias winding on the ﬂyback trans-

former is used to increase the efﬁciency of the LTC4267-1

switching regulator.

TheI /RUNcanbedrivenbelowV

(nominally0.28V

TH

ITHSHDN

Table 3. Power over Ethernet Transformer Vendors

with respect to PGND) to force the LTC4267-1 switching

VENDOR

CONTACT INFORMATION

regulator into shutdown. An internal 0.3ꢀA current source

Bel Fuse Inc.

206 Van Vorst Street

Jersey City, NJ 07302

Tel: 201-432-0463

always tries to pull the I /RUN pin towards P . When

TH

VCC

the I /RUN pin voltage is allowed to exceed V

and

TH

ITHSHDN

FAX: 201-432-9542

http://www.belfuse.com

P

exceedsV

,theLTC4267-1switchingregulator

TURNON

VCC

begins to operate and an internal clamp immediately pulls

the I /RUN pin to about 0.7V. In operation, the I /RUN

Coilcraft, Inc.

1102 Silver Lake Road

Cary, IL 60013

TH

Tel: 847-639-6400

FAX: 847-639-1469

http://www.coilcraft.com

pinvoltagewillvaryfromroughly0.7Vto1.9Vtorepresent

current comparator thresholds from zero to maximum.

Pulse Engineering

Tyco Electronics

12220 World Trade Drive

San Diego, CA 92128

Tel: 858-674-8100

Internal Soft-Start

An internal soft-start feature is enabled whenever the

LTC4267-1 switching regulator comes out of shutdown.

Speciﬁcally, the I /RUN voltage is clamped and is

prevented from reaching maximum until 1.4ms have

passed. This allows the input current of the PD to rise in a

smooth and controlled manner on start-up and stay within

the current limit requirement of the LTC4267-1 interface.

FAX: 858-674-8262

http://www.pulseeng.com

308 Constitution Drive

Menlo Park, CA 94025-1164

Tel: 800-227-7040

FAX: 650-361-2508

http://www.circuitprotection.com

TH

42671f

16

LTC4267-1

W U U

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APPLICATIO S I FOR ATIO

Diode Bridge

affect the transition point between modes. When using

the LTC4267-1, it is necessary to pay close attention to

this forward voltage drop. Selection of oversized diodes

will help keep the PD thresholds from exceeding IEEE

speciﬁcations.

IEEE 802.3af allows power wiring in either of two conﬁgu-

rations: on the TX/RX wires or via the spare wire pairs in

the RJ45 connector. The PD is required to accept power in

eitherpolarityoneitherthemainorspareinputs;therefore

it is common to install diode bridges on both inputs in

ordertoaccommodatethedifferentwiringconﬁgurations.

Figure 9 demonstrates an implementation of these diode

bridges. The IEEE 802.3af speciﬁcation also mandates

that the leakage back through the unused bridge be less

than 28ꢀA when the PD is powered with 57V.

The input diode bridge of a PD can consume over 4%

of the available power in some applications. It may be

desirable to use Schottky diodes in order to reduce power

loss. However, if the standard diode bridge is replaced

with a Schottky bridge, the transition points between the

modes will be affected. Figure 10 shows a technique for

usingSchottkydiodeswhilemaintainingproperthreshold

points to meet IEEE 802.3af compliance. D13 is added to

compensateforthechangeinUVLOturn-onvoltagecaused

by the Schottky diodes and consumes little power.

TheIEEEstandardincludesanACimpedancerequirement

in order to implement the AC disconnect function. Capaci-

tor C14 in Figure 9 is used to meet this AC impedance

requirement. A 0.1ꢀF capacitor is recommended for this

application.

Classiﬁcation Resistor Selection (R

)

CLASS

The LTC4267-1 has several different modes of opera-

The IEEE speciﬁcation allows classifying PDs into four

distinct classes with class 4 being reserved for future use

tion based on the voltage present between V

and

PORTN

V

pins. The forward voltage drop of the input diodes

PORTP

(Table 2). An external resistor connected from R

to

CLASS

in a PD design subtracts from the input voltage and will

V

(Figure 4) sets the value of the load current. The

PORTN

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Figure 9. PD Front End with Isolation Transformer, Diode Bridges and Capacitor

42671f

17

LTC4267-1

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Figure 10. PD Front End with Isolation Transformer, 2nd Schottky Diode Bridge

designer should determine which power category the PD

falls into and then select the appropriate value of R

Resistor power dissipation will be 50mW maximum and

is transient so heating is typically not a concern. In order

to maintain loop stability, the layout should minimize

CLASS

from Table 2. If a unique load current is required, the value

of R

can be calculated as:

capacitance at the R

node. The classiﬁcation circuit

CLASS

can be disabled by ﬂoating the R

should not be shorted to V

LTC4267-1 classiﬁcation circuit to attempt to source very

pin. The R

CLASS

R

= 1.237V/(I

– I

)

IN_CLASS

CLASS

DESIRED

as this would force the

PORTN

whereI

istheLTC4267-1ICsupplycurrentduring

IN_CLASS

classiﬁcation and is given in the electrical speciﬁcations.

large currents and quickly go into thermal shutdown.

The R

resistor must be 1% or better to avoid de-

CLASS

grading the overall accuracy of the classiﬁcation circuit.

42671f

18

LTC4267-1

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APPLICATIO S I FOR ATIO

U

Power Good Interface

Load Capacitor

⎯

The PWRGD signal is controlled by a high voltage, open-

drain transistor. The designer has the option of using this

signal to enable the onboard switching regulator through

TheIEEE802.3afspeciﬁcationrequiresthatthePDmaintain

a minimum load capacitance of 5ꢀF (provided by C1 in

Figure 11). It is permissible to have a much larger load

capacitor and the LTC4267-1 can charge very large load

capacitors before thermal issues become a problem. The

load capacitor must be large enough to provide sufﬁcient

energy for proper operation of the switching regulator.

However, the capacitor must not be too large or the PD

design may violate IEEE 802.3af requirements.

the I /RUN or the P

pins. Examples of active-high

TH

VCC

interface circuits for controlling the switching regulator

are shown in Figure 7.

In some applications, it is desirable to ignore intermittent

power bad conditions. This can be accomplished by in-

cluding capacitor C15 in Figure 7 to form a lowpass ﬁlter.

With the components shown, power bad conditions less

than about 200ꢀs will be ignored. Conversely, in other

applications it may be desirable to delay assertion of

If the load capacitor is too large, there can be a problem

with inadvertent power shutdown by the PSE. Consider

the following scenario. If the PSE is running at –57V

(maximumallowed)andthePDhasdetectedandpowered

up, the load capacitor will be charged to nearly –57V. If

for some reason the PSE voltage is suddenly reduced to

–44V (minimum allowed), the input bridge will reverse

bias and the PD power will be supplied by the load capaci-

tor. Depending on the size of the load capacitor and the

DC load of the PD, the PD will not draw any power for

a period of time. If this period of time exceeds the IEEE

802.3af 300ms disconnect delay, the PSE will remove

power from the PD. For this reason, it is necessary to

ensure that inadvertent shutdown cannot occur.

⎯

PWRGD to the switching regulator using C

as shown in Figure 7.

or C17

PVCC

It is recommended that the designer use the power

good signal to enable the switching regulator. Using

⎯

PWRGD ensures the capacitor C1 has reached within

1.5V of the ﬁnal value and is ready to accept a load. The

LTC4267-1 is designed with wide power good hysteresis

to handle sudden ﬂuctuations in the load voltage and

current without prematurely shutting off the switching

regulator. Please refer to the Power-Up Sequencing of the

Application Information section.

Very small output capacitors (≤10ꢀF) will charge very

quickly in current limit. The rapidly changing voltage at

the output may reduce the current limit temporarily, caus-

ing the capacitor to charge at a somewhat reduced rate.

Conversely, charging a very large capacitor may cause the

current limit to increase slightly. In either case, once the

output voltage reaches its ﬁnal value, the input current

limit will be restored to its nominal value.

Signature Disable Interface

Todisablethe25ksignatureresistor, connectSIGDISApin

to the V

pin. Alternately, SIGDISA pin can be driven

PORTP

high with respect to V

. An example of a signature

PORTN

disable interface is shown in Figure 16, option 2. Note that

the SIGDISA input resistance is relatively large and the

threshold voltage is fairly low. Because of high voltages

presentontheprintedcircuitboard, leakagecurrentsfrom

The load capacitor can store signiﬁcant energy when fully

charged. The design of a PD must ensure that this energy

is not inadvertently dissipated in the LTC4267-1. The po-

larity-protection diode(s) prevent an accidental short on

the V

pin could inadvertently pull SIGDISA high. To

PORTP

ensure trouble-free operation, use high voltage layout

techniques in the vicinity of SIGDISA. If unused, connect

SIGDISA to V

.

PORTN

42671f

19

LTC4267-1

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APPLICATIO S I FOR ATIO

the cable from causing damage. However, if the V

Choose resistance values for R1 and R2 to be as large as

possible to minimize any efﬁciency loss due to the static

PORTN

pin is shorted to V

inside the PD while the capacitor

PORTP

is charged, current will ﬂow through the parasitic body

diode of the internal MOSFET and may cause permanent

damage to the LTC4267-1.

current drawn from V , but just small enough so that

OUT

whenV isinregulation,theerrorcausedbythenonzero

OUT

input current from the output of the resistor divider to the

error ampliﬁer pin is less than 1%.

Maintain Power Signature

Error Ampliﬁer and Optoisolator Considerations

In an IEEE 802.3af system, the PSE uses the maintain

power signature (MPS) to determine if a PD continues to

require power. The MPS requires the PD to periodically

draw at least 10mA and also have an AC impedance less

than 26.25kΩ in parallel with 0.05ꢀF. If either the DC

current is less than 10mA or the AC impedance is above

26.25kΩ, the PSE may disconnect power. The DC current

must be less than 5mA and the AC impedance must be

above 2MΩ to guarantee power will be removed.

In an isolated topology, the selection of the external error

ampliﬁer depends on the output voltage of the switching

regulator. Typical error ampliﬁers include a voltage refer-

ence of either 1.25V or 2.5V. The output of the ampliﬁer

and the ampliﬁer upper supply rail are often tied together

internally. The supply rail is usually speciﬁed with a wide

upper voltage range, but it is not allowed to fall below the

reference voltage. This can be a problem in an isolated

switcher design if the ampliﬁer supply voltage is not prop-

erly managed. When the switcher load current decreases

and the output voltage rises, the error ampliﬁer responds

by pulling more current through the LED. The LED voltage

Selecting Feedback Resistor Values

The regulated output voltage of the switching regulator is

determined by the resistor divider across V

(R1 and

OUT

can be as large as 1.5V, and along with R , reduces the

LIM

R2 in Figure 11) and the error ampliﬁer reference voltage

. The ratio of R2 to R1 needed to produce the desired

supply voltage to the error ampliﬁer. If the error amp does

V

REF

not have enough headroom, the voltage drop across the

voltage can be calculated as:

LED and R

may shut the ampliﬁer off momentarily,

LIM

R2 = R1 • (V – V )/V

OUT

REF REF

causing a lock-up condition in the main loop. The switcher

will undershoot and not recover until the error ampliﬁer

releases its sink current. Care must be taken to select the

Inanisolatedpowersupplyapplication,V isdetermined

REF

by the designer’s choice of an external error ampliﬁer.

Commercially available error ampliﬁers or programmable

shunt regulators may include an internal reference of

1.25V or 2.5V. Since the LTC4267-1 internal reference

and error ampliﬁer are not used in an isolated design, tie

referencevoltageandR valuesothattheerrorampliﬁer

LIM

always has enough headroom. An alternate solution that

avoids these problems is to utilize the LT1431 or LT4430

wheretheoutputoftheerrorampliﬁerandampliﬁersupply

rail are brought out to separate pins.

the V pin to PGND.

FB

The PD designer must also select an optoisolator such

that its bandwidth is sufﬁciently wider than the bandwidth

of the main control loop. If this step is overlooked, the

main control loop may be difﬁcult to stabilize. The output

In a nonisolated power supply application, the LTC4267-1

onboard internal reference and error ampliﬁer can be

used. The resistor divider output can be tied directly to

the V pin. The internal reference of the LTC4267-1 is

FB

0.8V nominal.

42671f

20

LTC4267-1

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APPLICATIO S I FOR ATIO

U

collector resistor of the optoisolator can be selected for

an increase in bandwidth at the cost of a reduction in gain

of this stage.

the maximum load current allowable at the power sup-

ply output based on the class of the PD. Choose R

SENSE

such that I /RUN approaches 1.9V. Finally, exercise the

TH

output load current over the entire operating range and

Output Transformer Design Considerations

ensure that I /RUN voltage remains within the 0.7V to

TH

1.9V range. Layout is critical around the R

resistor.

SENSE

Since the external feedback resistor divider sets the

output voltage, the PD designer has relative freedom in

selecting the transformer turns ratio. The PD designer

can use simple ratios of small integers (i.e. 1:1, 2:1, 3:2)

which yields more freedom in setting the total turns and

mutual inductance and may allow the use of an off the

shelf transformer.

For example, a 0.020Ω sense resistor, with one milliohm

(0.001Ω)ofparasiticresistancewillcausea5%reduction

in peak switch current. The resistance of printed circuit

copper traces cannot necessarily be ignored and good

layout techniques are mandatory.

Programmable Slope Compensation

Transformer leakage inductance on either the primary or

secondarycausesavoltagespiketooccuraftertheoutput

switch (Q1 in Figure 11) turns off. The input supply volt-

age plus the secondary-to-primary referred voltage of the

ﬂyback pulse (including leakage spike) must not exceed

theallowedexternalMOSFETbreakdownrating.Thisspike

is increasingly prominent at higher load currents, where

more stored energy must be dissipated. In some cases,

a “snubber” circuit will be required to avoid overvoltage

breakdown at the MOSFET’s drain node. Application

Note 19 is a good reference for snubber design.

The LTC4267-1 switching regulator injects a ramping

current through its SENSE pin into an external slope

compensation resistor (R in Figure 11). This current

SL

ramp starts at zero after the NGATE pin has been high for

the LTC4267-1’s minimum duty cycle of 6%. The current

rises linearly towards a peak of 5ꢀA at the maximum duty

cycle of 80%, shutting off once the NGATE pin goes low.

A series resistor (R ) connecting the SENSE pin to the

SL

current sense resistor (R

) develops a ramping volt-

SENSE

age drop. From the perspective of the LTC4267-1 SENSE

pin, this ramping voltage adds to the voltage across the

senseresistor,effectivelyreducingthecurrentcomparator

threshold in proportion to duty cycle. This stabilizes the

controlloopagainstsubharmonicoscillation. Theamount

Current Sense Resistor Consideration

The external current sense resistor (R

in Figure 11)

SENSE

allows the designer to optimize the current limit behavior

for a particular application. As the current sense resistor

is varied from several ohms down to tens of milliohms,

peak swing current goes from a fraction of an ampere to

several amperes. Care must be taken to ensure proper

circuit operation, especially for small current sense resis-

tor values.

ofreductioninthecurrentcomparatorthreshold(ΔV

can be calculated using the following equation:

)

SENSE

ΔV

= 5ꢀA • R • [(Duty Cycle – 6%)/74%]

SL

SENSE

Note: The LTC4267-1 enforces 6% < Duty Cycle < 80%.

Designs not needing slope compensation may replace

R

SL

with a short-circuit.

Choose R

such that the switching current exercises

SENSE

theentirerangeoftheI /RUNvoltage.Thenominalvoltage

TH

Applications Employing a Third Transformer Winding

range is 0.7V to 1.9V and R

can be determined by

SENSE

A standard operating topology may employ a third wind-

ing on the transformer’s primary side that provides power

experiment. The main loop can be temporarily stabilized

byconnectingalargecapacitoronthepowersupply.Apply

42671f

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LTC4267-1

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APPLICATIO S I FOR ATIO

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Figure 11. Typical LTC4267-1 Application Circuits

42671f

22

LTC4267-1

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APPLICATIO S I FOR ATIO

to the LTC4267-1 switching regulator via its P

CapacitorC

shouldthenbemadelargeenoughtoavoid

VCC

PVCC

(Figure 11). However, this arrangement is not inherently

self-starting.Start-upisusuallyimplementedbytheuseof

the relaxation oscillation behavior described previously.

This is difﬁcult to determine theoretically as it depends on

the particulars of the secondary circuit and load behavior.

Empirical testing is recommended.

an external “trickle-charge” resistor (R

) in conjunc-

START

tionwiththeinternalwidehysteresisundervoltagelockout

circuit that monitors the P

pin voltage.

VCC

The third transformer winding should be designed so

that its output voltage, after accounting for the forward

R

is connected to V

and supplies a current,

START

PORTP

typically 100ꢀA, to charge C

. After some time, the

turn-on threshold. The

VCC

diode voltage drop, exceeds the maximum P

turn-off

PVCC

VCC

voltage on C

reaches the P

threshold.Also,thethirdwinding’snominaloutputvoltage

should be at least 0.5V below the minimum rated P

PVCC

LTC4267-1switchingregulatorthenturnsonabruptlyand

draws its normal supply current. The NGATE pin begins

switching and the external MOSFET (Q1) begins to deliver

VCC

clamp voltage to avoid running up against the LTC4267-1

shunt regulator, needlessly wasting power.

power. The voltage on C

begins to decline as the

PVCC

P

Shunt Regulator

switchingregulatordrawsitsnormalsupplycurrent,which

exceedsthedeliveryfromR .Aftersometime,typically

VCC

START

In applications including a third transformer winding,

the internal P shunt regulator serves to protect the

tens of milliseconds, the output voltage approaches the

desired value. By this time, the third transformer winding

is providing virtually all the supply current required by the

LTC4267-1 switching regulator.

VCC

LTC4267-1switchingregulatorfromovervoltagetransients

as the third winding is powering up.

If a third transformer winding is undesirable or unavail-

able, the shunt regulator allows the LTC4267-1 switching

regulatortobepoweredthroughasingledroppingresistor

One potential design pitfall is under-sizing the value of

capacitor C

. In this case, the normal supply current

PVCC

drawnthroughP willdischargeC

rapidlybeforethe

VCC

PVCC

from V

as shown in Figure 12. This simplicity comes

PORTP

third winding drive becomes effective. Depending on the

particular situation, this may result in either several off-on

cycles before proper operation is reached or permanent

at the expense of reduced efﬁciency due to static power

dissipation in the R dropping resistor.

START

The shunt regulator can sink up to 5mA through the P

VCC

must be

relaxation oscillation at the P

node.

VCC

pin to PGND. The values of R

and C

START

PVCC

Resistor R

should be selected to yield a worst-case

START

selected for the application to withstand the worst-case

load conditions and drop on P , ensuring that the P

minimumchargingcurrentgreaterthatthemaximumrated

VCC

LTC4267-1 start-up current to ensure there is enough cur-

turn-off threshold is not reached. C

should be sized

PVCC

renttochargeC

totheP turn-onthreshold. R

VCC START

PVCC

sufﬁcientlytohandletheswitchingcurrentneededtodrive

NGATE while maintaining minimum switching voltage.

should also be selected large enough to yield a worst-case

maximum charging current less than the minimum-rated

P

supply current, so that in operation, most of the

current is delivered through the third winding. This

External Preregulator

VCC

The circuit in Figure 13 shows a third way to power the

LTC4267-1 switching regulator circuit. An external series

results in the highest possible efﬁciency.

42671f

23

LTC4267-1

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APPLICATIO S I FOR ATIO

virtually all the supply current required by the LTC4267-1

ꢎ

switching regulator. C

should be sized sufﬁciently to

PVCC

handle the switching current needed to drive NGATE while

maintaining minimum switching voltage.

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previously. R can be selected so that it provides a small

B

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current necessary to maintain the zener diode voltage and

themaximumpossiblebasecurrentQ1willencounter.The

actual current needed to power the LTC4267-1 switching

1(/%

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Figure 12. Powering the LTC4267-1 Switching

Regulator via the Shunt Regulator

regulator goes through Q1 and P

sources current on

VCC

an “as-needed” basis. The static current is then limited

only to the current through R and D1.

B

ꢎ

Compensating the Main Loop

3

#

3

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chosenbythecomponentsconﬁguredaroundtheexternal

error ampliﬁer. Shown in Figure 14, a series RC network

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Figure 13. Powering the LTC4267-1 Switching

Regulator with an External Preregulator

3ꢆ

ꢁꢂꢃꢄꢆꢏ'ꢆꢁ

preregulator consists of a series pass transistor Q1, zener

Figure 14. Main Loop Compensation for an Isolated Design

diode D1, and a bias resistor R . The preregulator holds

B

P

at7.6Vnominal, wellabovethemaximumratedP

VCC

momentarily

turn-on threshold,

is connected from the compare voltage of the error am-

pliﬁer to the error ampliﬁer output. In PD designs where

turn-off threshold of 6.8V. Resistor R

START

charges the P

node up to the P

VCC

transient load response is not critical, replace R with a

Z

enabling the switching regulator. The voltage on C

PVCC

short.TheproductofR2andC shouldbesufﬁcientlylarge

C

begins to decline as the switching regulator draws its

to ensure stability. When fast settling transient response

normal supply current, which exceeds the delivery of

is critical, introduce a zero set by R C . The PD designer

Z C

R

. After some time, the output voltage approaches

START

must ensure that the faster settling response of the output

the desired value. By this time, the pass transistor Q1

voltage does not compromise loop stability.

catchesthedecliningvoltageontheP pin,andprovides

VCC

42671f

24

LTC4267-1

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APPLICATIO S I FOR ATIO

U

In a nonisolated design, the LTC4267-1 incorporates an

Auxiliary Power Source

internal error ampliﬁer where the I /RUN pin serves as

TH

In some applications, it may be desirable to power the

PD from an auxiliary power source such as a wall trans-

former. The auxiliary power can be injected into the PD

at several locations and various trade-offs exist. Power

can be injected at the 3.3V or 5V output of the isolated

power supply with the use of a diode ORing circuit. This

method accesses the internal circuits of the PD after the

isolation barrier and therefore meets the 802.3af isola-

tion safety requirements for the wall transformer jack on

the PD. Power can also be injected into the PD interface

portion of the LTC4267-1. In this case, it is necessary to

ensure the user cannot access the terminals of the wall

transformer jack on the PD since this would compromise

the 802.3af isolation safety requirements.

a compensation point. In a similar manner, a series RC

network can be connected from I /RUN to PGND as

TH

shown in Figure 15. C and R are chosen for optimum

C

Z

load and line transient response.

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Figure 15. Main Loop Compensation for a Nonisolated Design

Figure 16 demonstrates three methods of diode ORing

external power into a PD. Option 1 inserts power before

the LTC4267-1 interface controller while options 2 and

3 bypass the LTC4267-1 interface controller section and

power the switching regulator directly.

Selecting the Switching Transistor

With the N-channel power MOSFET driving the primary of

the transformer, the inductance will cause the drain of the

MOSFET to traverse twice the voltage across V

and

PORTP

PGND. The LTC4267-1 operates with a maximum supply

of – 57V; thus the MOSFET must be rated to handle 114V

or more with sufﬁcient design margin. Typical transis-

tors have 150V ratings while some manufacturers have

developed 120V rated MOSFETs speciﬁcally for Power-

over-Ethernet applications.

If power is inserted before the LTC4267-1 interface con-

troller, it is necessary for the wall transformer to exceed

the LTC4267-1 UVLO turn-on requirement and include a

transient voltage suppressor (TVS) to limit the maximum

voltage to 57V. This option provides input current limit

for the transformer, provides a valid power good signal,

and simpliﬁes power priority issues. As long as the wall

transformer applies power to the PD before the PSE, it

will take priority and the PSE will not power up the PD

because the wall power will corrupt the 25k signature. If

the PSE is already powering the PD, the wall transformer

power will be in parallel with the PSE. In this case, prior-

ity will be given to the higher supply voltage. If the wall

transformer voltage is higher, the PSE should remove the

line voltage since no current will be drawn from the PSE.

On the other hand, if the wall transformer voltage is lower,

the PSE will continue to supply power to the PD and the

walltransformerwillnotbeused. Properoperationshould

occur in either scenario.

The NGATE pin of the LTC4267-1 drives the gate of the

N-channel MOSFET. NGATE will traverse a rail-to-rail volt-

age from PGND to P . The designer must ensure the

VCC

MOSFET provides a low “ON” resistance when switched

to P

as well as ensure the gate of the MOSFET can

VCC

handle the P

supply voltage.

VCC

For high efﬁciency applications, select an N-channel

MOSFET with low total gate charge. The lower total gate

charge improves the efﬁciency of the NGATE drive circuit

and minimizes the switching current needed to charge

and discharge the gate.

42671f

25

LTC4267-1

W U U

U

APPLICATIO S I FOR ATIO

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Figure 16. Auxiliary Power Source for PD

42671f

26

LTC4267-1

W U U

APPLICATIO S I FOR ATIO

U

If auxiliary power is applied directly to the LTC4267-1

switching regulator (bypassing the LTC4267-1 PD inter-

face), a different set of tradeoffs arise. In the conﬁguration

shown in option 2, the wall transformer does not need

to exceed the LTC4267-1 turn-on UVLO requirement;

however, it is necessary to include diode D9 to prevent

the transformer from applying power to the LTC4267-1

interface controller. The transformer voltage requirement

will be governed by the needs of the onboard switching

regulator. However, power priority issues require more

intervention. If the wall transformer voltage is below

the PSE voltage, then priority will be given to the PSE

power.TheLTC4267-1interfacecontrollerwilldrawpower

from the PSE while the transformer will sit unused. This

conﬁguration is not a problem in a PoE system. On the

other hand, if the wall transformer voltage is higher than

the PSE voltage, the LTC4267-1 switching regulator will

draw power from the transformer. In this situation, it is

necessary to address the issue of power cycling that may

occur if a PSE is present. The PSE will detect the PD and

apply power. If the switcher is being powered by the wall

transformer, then the PD will not meet the minimum load

requirementandthePSEwillsubsequentlyremovepower.

The PSE will again detect the PD and power cycling will

start. With a transformer voltage above the PSE voltage,

it is necessary to either disable the signature, as shown

in option 2, or install a minimum load on the output of the

LTC4267-1 interface to prevent power cycling.

Power-Up Sequencing the LTC4267-1

The LTC4267-1 consists of two functional cells, the PD

interface and the switching regulator, and the power up

sequencingofthesetwocellsmustbecarefullyconsidered.

ThePDdesignershouldensurethattheswitchingregulator

doesnotbeginoperationuntiltheinterfacehascompleted

charging up the load capacitor. This will ensure that the

switcher load current does not compete with the load

capacitor charging current provided by the PD interface

current limit circuit. Overlooking this consideration may

resultinslowpowersupplyrampup,power-uposcillation,

and possibly thermal shutdown.

The LTC4267-1 includes a power good signal in the PD

interface that can be used to indicate to the switching

regulator that the load capacitor is fully charged and ready

to handle the switcher load. Figure 7 shows two examples

⎯

of ways the PWRGD signal can be used to control the

switchingregulator.TheﬁrstexampleemploysanN-chan-

nelMOSFETtodrivetheI /RUNportbelowtheshutdown

TH

threshold (typically 0.28V). The second example drives

P

VCC

below the P

turn-off threshold. Employing the

VCC

second example has the added advantage of adding delay

to the switching regulator start-up beyond the time the

power good signal becomes active. The second example

ensures additional timing margin at start-up without the

needforaddeddelaycomponents.Inapplicationswhereit

is not desirable to utilize the power good signal, sufﬁcient

timing margin can be achieved with R

and C

.

START

PVCC

The third option also applies power directly to the

LTC4267-1switchingregulator, bypassingtheLTC4267-1

interface controller and omitting diode D9. With the

diode omitted, the transformer voltage is applied to the

LTC4267-1interfacecontrollerinadditiontotheswitching

regulator. Forthisreason, itisnecessarytoensurethatthe

transformer maintain the voltage between 38V and 57V

to keep the LTC4267-1 interface controller in its normal

operating range. The third option has the advantage of

automatically disabling the 25k signature resistor when

the external voltage exceeds the PSE voltage.

R

and C

should be set to a delay of two to three

START

PVCC

times longer than the duration needed to charge up C1.

Layout Considerations for the LTC4267-1

The most critical layout considerations for the LTC4267-1

are the placement of the supporting external components

associatedwiththeswitching regulator.Efﬁciency,stability,

and load transient response can deteriorate without good

layout practices around critical components.

42671f

27

LTC4267-1

W U U

U

APPLICATIO S I FOR ATIO

For the LTC4267-1 switching regulator, the current loop

as close as possible to the V pin of the LTC4267-1

FB

through C1, T1 primary, Q1, and R

must be given

and C should be placed close to the I /RUN pin of the

SENSE

C

TH

careful layout attention. (Refer to Figure 11.) Because of

the high switching current circulating in this loop, these

components should be placed in close proximity to each

other. In addition, wide copper traces or copper planes

should be used between these components. If vias are

necessary to complete the connectivity of this loop,

placing multiple vias lined perpendicular to the ﬂow of

currentisessentialforminimizingparasiticresistanceand

reducing current density. Since the switching frequency

and the power levels are substantial, shielding and high

frequency layout techniques should be employed. A low

current, low impedance alternate connection should be

employed between the PGND pins of the LTC4267-1 and

LTC4267-1.

In essence, a tight overall layout of the high current loop

and careful attention to current density will ensure suc-

cessful operation of the LTC4267-1 in a PD.

The PD interface section of the LTC4267-1 is relatively im-

mune to layout problems. Excessive parasitic capacitance

CLASS

adjacenttotheV

tive or capacitive may inadvertently disable the signature

resistance. To ensure consistent behavior, the SIGDISA

pin should be electrically connected and not left ﬂoating.

Voltages in a PD can be as large as –57V, so high voltage

layout techniques should be employed.

on the R

pin should be avoided. The SIGDISA pin is

pinandanycoupling,whetherresis-

PORTP

thePGNDsideofR

,awayfromthehighcurrentloop.

SENSE

ThisKelvinsensingwillensureanaccuraterepresentation

Electro Static Discharge and Surge Protection

of the sense voltage is measured by the LTC4267-1.

The LTC4267-1 is speciﬁed to operate with an absolute

maximum voltage of –100V and is designed to tolerate

brief overvoltage events. However, the pins that interface

The placement of the feedback resistors R1 and R2 as

well as the compensation capacitor C is very important

C

in the accuracy of the output voltage, the stability of the

to the outside world (primarily V

and V

) can

PORTN

PORTP

main control loop, and the load transient response. In

routinely see peak voltages in excess of 10kV. To protect

the LTC4267-1, it is highly recommended that a transient

voltage suppressor be installed between the diode bridge

and the LTC4267-1 (D3 in Figure 2).

an isolated design application, R1, R2, and C should be

C

placed as close as possible to the error ampliﬁer’s input

with minimum trace lengths and minimum capacitance.

In a nonisolated application, R1, and R2 should be placed

42671f

28

LTC4267-1

U

TYPICAL APPLICATIO S

Class 3 PD with 5V Nonisolated Power Supply

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42671f

29

LTC4267-1

U

TYPICAL APPLICATIO S

42671f

30

LTC4267-1

U

PACKAGE DESCRIPTIO

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.189 – .196*

(4.801 – 4.978)

.045 .005

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 .0015

.0250 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 .004

(0.38 0.10)

× 45°

.0532 – .0688

(1.35 – 1.75)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

GN16 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

42671f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

31

LTC4267-1

TYPICAL APPLICATION

High-Efﬁciency Class 3 PD with 3.3V Isolated Power Supply

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42671f

LT 0207 • PRINTED IN USA

32 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC4267-1
厂家：	Linear
描述：	Power over Ethernet IEEE 802.3af PD Interface with Integrated Switching Regulator 权力与集成开关稳压器的以太网IEEE 802.3af PD接口稳压器开关光电二极管以太网
文件：	总32页 (文件大小：904K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC4267-1 [Linear]

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