LTC4268-1_12_技术文档

LTC4268-1

High Power PD With

Synchronous No-Opto

Flyback Controller

FeaTures

DescripTion

The LTC^®4268-1 is an integrated Powered Device (PD)

controllerandswitchingregulatorintendedforIEEE802.3af

and high power PoE applications up to 35W. By including

a precisiondualcurrent limit, the LTC4268-1 keepsinrush

below IEEE 802.3af current limit levels to ensure interop-

erability success while enabling high power applications

with a 750mA operational current limit.

n

Robust 35W PD Front End

n

IEEE 802.3af Compliant

n

Rugged 750mA Power MOSFET With Precision Dual

Level Current Limit

n

High Performance Synchronous Flyback Controller

n

IEEE Isolation Obtained Without an Opto-Isolator

n

Adjustable Frequency from 50kHz to 250kHz

n

Tight Multi-Output Regulation With Load

The LTC4268-1 synchronous, current-mode, flyback

controller generates multiple supply rails in a single

conversion providing for the highest system efficiency

while maintaining tight regulation across all outputs. The

LTC4268-1includesLinearTechnology’spatentedNo-Opto

feedback topology to provide full IEEE 802.3af isolation

without the need of opto-isolator circuitry.

Compensation

Onboard 25k Signature Resistor

n

Programmable Classification Current to 75mA

n

Complete Thermal and Over-Current Protection

n

Available in Compact 32-Pin 7mm × 4mm DFN

Package

applicaTions

The oversized power path and high performance flyback

controller of the LTC4268-1 combine to make the ultimate

solutionforpowerhungryPoEapplicationssuchasWAPs,

PTZ security cameras, RFID readers and ultra-efficient

802.3af applications running near the 12.95W limit.

n

VoIP Phones With Advanced Display Options

n

Dual-Radio Wireless Access Points

n

PTZ Security Cameras

n

RFID Readers

Industrial Controls

n

The LTC4268-1 is available in a space saving 32-pin DFN

package.

n

Magnetic Card Readers

n

High Power PoE Systems

++

L, LT, LTC, LTM and SwitcherCAD are registered trademarks and LTPoE and ThinSOT are

trademarks of Linear Technology Corporation. All other trademarks are the property of their

respective owners. Protected by U.S. Patents including 5841643.

Typical applicaTion

35W High Efficiency PD Solution

3.3V

+

470µF

×4

•

≥5µF

100pF

56Ω

28.7k

1%

BAS21

20Ω

T1

47k

47Ω

•

T1

SMAJ58A

100k

B0540W

•

3.01k

1%

DF1501S

FMMT618

47µF

Si4490DY

Si7336ADP

~ +

–54V FROM

DATA PAIR

~ –

FMMT718

0.1µF

+

V

PWRGD PWRGD UVLO I

V

CC

FB PG

SENSE

PORTP

LIM_EN

DF1501S

~ +

~ –

1µF

0.02Ω

330Ω

SHDN

–54V FROM

SPARE PAIR

–

SENSE

15Ω

LTC4268-1

R

CLASS

SG

2.2nF

0.1µF

10nF

20k

V

CMP

T2

V

PGDLY

t

SYNC

R

ENDLY

OSC GND SFST C

CMP

PORTN

NEG

ON

CMP

•

R

CLASS

10k

12k

169k

100k

47pF

BAT54

T1: PA1477NL

T2: PA0184

42681 TA01a

0.033µF

42681fc

1

LTC4268-1

absoluTe MaxiMuM raTings

pin conFiguraTion

(Notes 1, 2)

TOP VIEW

V

Voltage .......................................... 0.3V to –90V

PORTN

SHDN

NC

1

2

32 V

PORTP

Voltage..................V

+ 90V to V

–0.3V

NEG

PORTN

31 NC

to GND Voltage (Note 3)

Low Impedance Source ......................... –0.3V to 18V

Current Fed..........................................30mA into V

CC

R

3

30 PWRGD

29 PWRGD

CLASS

I

4

LIM_EN

CC

V

5

28

27

26

V

PORTN

NEG

R

, I

Voltage..V

+ 7V to V

– 0.3V

CLASS LIM_EN

PORTN

+ 90V to V

PORTN

6

SHDN Voltage ...............V

PWRGD Voltage (Note 3)

PORTN

7

PORTN

NC

8

25 NC

33

Low Impedance Source .... V

+ 11V to V

– 0.3V

NEG

SG

9

24 PG

Current Fed..........................................................5mA

V

t

10

11

23 PGDLY

CC

PWRGD Voltage ............V

+ 80V to V

– 0.3V

22

21

R

PORTN

ON

CMP

PWRGD Current .....................................................10mA

Current ....................................................100mA

ENDLY 12

SYNC 13

SFST 14

OSC 15

FB 16

C

20 SENSE+

19 SENSE–

18 UVLO

R

CLASS

–

+

SENSE , SENSE Voltage........................ –0.5V to +0.5V

UVLO, SYNC Voltage...................................–0.3V to V

CC

17

V

CMP

FB Current.............................................................. 2mA

V

CMP

Current ......................................................... 1mA

DKD32 PACKAGE

32-LEAD (7mm × 4mm) PLASTIC DFN

Operating Ambient Temperature Range (Notes 4, 5)

LTC4268-1C ............................................. 0°C to 70°C

LTC4268-1I ..........................................–40°C to 85°C

Junction Temperature (Note 5) ............................. 150°C

Storage Temperature Range .................. –65°C to 150°C

T

= 150°C,θ = 49°C/W, θ = 4.7°C/W

JA JC

JMAX

EXPOSED PAD (PIN 33) MUST BE SOLDERED TO

HEAT SINKING PLANE THAT IS ELECTRICALLY CONNECTED TO GND

orDer inForMaTion

LEAD FREE FINISH

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC4268CDKD-1#PBF

LTC4268IDKD-1#PBF

LTC4268CDKD-1#TRPBF 42681

LTC4268IDKD-1#TRPBF 42681

32-Lead (7mm × 4mm) Plastic DFN

0°C to 70°C

–40°C to 85°C

LEAD BASED FINISH

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC4268CDKD-1

LTC4268IDKD-1

LTC4268CDKD-1#TR

LTC4268IDKD-1#TR

42681

32-Lead (7mm × 4mm) Plastic DFN

0°C to 70°C

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

42681fc

2

LTC4268-1

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 14V, SG open, V_CMP= 1.5V, V_SENSE= 0V, R_CMP= 1k, R_tON= 90k,

R_PGDLY= 27.4k, R_ENDLY= 90k, unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

PORT

Supply Voltage

Voltage With Respect to V

PORTP

(Notes 6, 7, 8, 9, 10)

l

IEEE 802.3af System

Signature Range

–57

–10.1

–21

–40.2

–31.5

V

–1.5

–12.5

–37.7

–29.8

Classification Range

UVLO Turn-On Voltage

UVLO Turn-Off Voltage

–38.9

–30.6

l

V

CC

V

CC

V

CC

V

CC

Turn-On Voltage

Turn-Off Voltage

Hysteresis

Voltage With Respect to GND

14

8

15.3

9.7

16.6

11

V

TURNON

TURNOFF

HYST

V

– V

4

5.6

7.2

TURNON

TURNOFF

Shunt Regulator Voltage

I

= 15mA, V = 0V, Voltage With

UVLO

19.5

20.2

CLAMP

VCC

Respect to GND

l

I

V

Supply Current

V

= Open (Note 11)

CMP

4

6.4

180

10

mA

µA

V

VCC

CC

Start-Up Current

= 10V

CC

400

VCC_START

CC

V

Feedback Regulation Voltage

1.22

1.237

200

1.251

FB

I

Feedback Pin Input Bias Current

R

Open

nA

A/V

FB_BIAS

CMP

l

g

Feedback Amplifier

Transconductance

700

25

1000

1400

90

m

I

FB

Feedback Amplifier Source or Sink

Current

55

µA

V

Feedback Amplifier Clamp Voltage

V

FB

V

FB

= 0.9V

= 1.4V

2.56

0.84

V

FBCLAMP

l

%V

Reference Voltage Line Regulation

Feedback Amplifier Voltage Gain

Soft-Start Charging Current

Soft-Start Discharge Current

Control Pin Threshold (VCMP)

PG, SG, Output High Level

12V ≤ V ≤ 18V

0.005

1500

20

0.02

25

%/V

V/V

µA

mA

V

REF

CC

A

V

CMP

V

SFST

V

SFST

= 1.2V to 1.7V

= 1.5V

I

16

SFST

= 1.5V, V

= 0V

0.8

1.3

1

UVLO

V

Duty Cycle = Min

CMP_THLD

l

V

,

6.6

7.4

8

V

PG_HIGH

SG_HIGH

V

,

PG, SG, Output Low Level

0.01

0.05

V

PG_LOW

SG_LOW

l

V

,

PG, SG, Output Shutdown Strength

PG, SG Rise Time

V

C

= 0V; I , I = 20mA

1.4

15

2.3

V

ns

PG_SHDN

SG_SHDN

UVLO

PG SG

t

,

, C = 1nF

PG SG

PG_RISE

SG_RISE

t

,

PG, SG Fall Time

, C = 1nF

PG SG

15

ns

PG_FALL

SG_FALL

l

V

Switch Current Threshold at Maximum

CMP

Measured at V

88

3

100

110

mV

SENSE_LIM

SENSE+

V

Sense Threshold vs V

0.07

205

V/V

mV

V

DV

/DV

SENSE CMP

CMP

l

V

Sense Pin Overcurrent Fault Voltage

Shutdown High Level Input Voltage

V , V < 1V

SENSE+ SFST

230

57

SENSE_OC

IH_SHDN

V

With Respect to V

High Level = Shutdown (Note 12)

PORTN

l

V

Shutdown Low Level Input Voltage

With Respect to V

0.45

V

IL_SHDN

PORTN

42681fc

3

LTC4268-1

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 14V, SG open, V_CMP= 1.5V, V_SENSE= 0V, R_CMP= 1k, R_tON= 90k,

R_PGDLY= 27.4k, R_ENDLY= 90k, unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

100

4

TYP

MAX

UNITS

kW

l

R

Shutdown Input Resistance

With Respect to V

INPUT_SHDN

PORTN

V

I

High Level Input Voltage

With Respect to V

High Level Enables Current Limit

(Note 13)

V

IH_ILIM

LIM_EN

l

V

I

Low Level Input Voltage

Supply Current

With Respect to V (Note 13)

1

3

V

mA

IL_ILIM

VPORTN

IN_CLASS

LIM_EN

PORTN

I

V

= –54V

PORTN

IC Supply Current During Classification

Current Accuracy During Classification

Signature Resistance

= –17.5V, V

(Note 14)

Tied to V

0.55

0.62

0.70

PORTN

NEG

PORTP

l

10mA < I

< 75mA

PORTN

3.5

26

%

DI

CLASS

–12.5V ≤ V

≤ –21V (Notes 15, 16)

R

–1.5V ≤ V

≤ –10.1V, SHDN Tied

PORTN

23.25

kW

SIGNATURE

to V

, IEEE 802.3af Two-Point

PORTN

Measurement (Notes 8, 9)

R

Invalid Signature Resistance

–1.5V ≤ V

≤ –10.1V, SHDN Tied

10

11.8

0.5

kW

INVALID

PORTN

to V

, IEEE 802.3af Two-Point

PORTP

Measurement (Notes 8, 9)

l

V

Active Low Power Good Output Voltage I = 1mA, V

= –54V, PWRGD

V

PWRGD_OUT

PORTN

Referenced to V

PORTN

l

I

Active Low Power Good Output Leakage

V

= 0V, V

= 57V

PWRGD

1

µA

V

PWRGD_LEAK

PORT

V

Active High Power Good Output Voltage I = 0.5mA, V

= –52V, V = –4V

NEG

0.35

PWRGD_OUT

PWRGD_VCLAMP

PWRGD_LEAK

PORTN

PWRGD Referenced to V

(Note 17)

NEG

l

V

Active High Power Good Voltage

Limiting Clamp

I = 2mA, V

to V

= 0V, PWRGD Referenced

12

14

16.5

1

V

NEG

(Note 3)

NEG

I

Active High Power Good Output Leakage V

V

= 11V With Respect to V

,

µA

PWRGD

NEG

= V

= –54V

PORTN

R

On-Resistance

I = 700mA, V

from V

= –48V, Measured

(Note 16)

NEG

0.5

0.6

0.8

W

ON

PORTN

to V

PORTN

I

V

Leakage

V

= –57V, V

= SHDN = V =

NEG

1

µA

mA

A

OUT_LEAK

LIM_HI

LIM_LO

LIM_DISA

OUT

PORTN

PORTP

0V (Note 15)

Input Current Limit, High Level

Input Current Limit, Low Level

V

= –54V, V

= –53V I

LIM_EN

700

250

1.2

750

300

1.45

800

350

1.65

PORTN

NEG

Floating (Notes 18, 19)

V

= –54V, V

= –53V

PORTN

NEG

(Notes 18, 19)

Safeguard Current Limit When I is

V

= –54V,

PORTN

NEG

LIM

Disabled

V

= –52.5V I

Tied to V

LIM_EN PORTN

(Notes 18, 19, 20)

l

f

Oscillator Frequency

C

= 100pF

84

33

100

110

200

kHz

pF

ns

%

OSC

C

Oscillator Capacitor Value

Minimum Switch on Time

Flyback Enable Delay Time

PG Turn-On Delay Time

Maximum Switch Duty Cycle

SYNC Pin Threshold

(Note 21)

OSC

t

200

265

200

88

ON(MIN)

ENDLY

PGDLY

l

DC

85

ON(MAX)

V

1.53

40

2.1

V

SYNC

R

SYNC Pin Input Resistance

kW

SYNC

42681fc

4

LTC4268-1

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 14V, SG open, V_CMP= 1.5V, V_SENSE= 0V, R_CMP= 1k, R_tON= 90k,

R_PGDLY= 27.4k, R_ENDLY= 90k, unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

I

Feedback Pin Load Compensation

Current

V

RCMP

With V = 0V

SENSE

20

µA

LCOMP

V

Load Comp to V

Offset Voltage

V

= 20mV, V = 1.23V

1

mV

V

LCOMP

UVLO

SENSE

SENSE+

FB

l

UVLO Pin Threshold

1.215

1.237

1.265

I

UVLO Pin Bias Current

V

UVLO

V

UVLO

= 1.2V

= 1.3V

–0.25

–4.50

0

–3.4

0.25

–2.5

µA

UVLOL

UVLOH

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 11: Supply current does not include gate charge current to the

MOSFETs. See Application Information.

Note 12: To disable the 25k signature, tie SHDN to V

( 0.1V) or hold

PORTP

SHDN high with respect to V . See Applications Information.

IN

Note 2: All voltages are with respect to V

pin unless otherwise noted.

PORTP

Note13: I

pin is pulled high internally and for normal operation

LIM_EN

Note 3: Active High PWRGD internal clamp circuit self-regulates to 14V

should be left floating. To disable current limit, tie I

Applications Information.

to V . See

LIM_EN IN

with respect to V . V has internal 20V clamp with respect to GND.

NEG CC

Note 4: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 14: I

does not include classification current programmed at

IN_CLASS

Pin 3. Total supply current in classification mode will be I

(See Note 15).

+ I

CLASS

IN_CLASS

Note 15: I

is the measured current flowing through R

. ∆I

= 1.237/

CLASS

CLASS CLASS

accuracy is with respect to the ideal current defined as I

CLASS

Note 5: T is calculated from the ambient temperature T and power

R

. T

is the time for I

to settle to within 3.5% of ideal.

J

A

CLASS CLASSRDY

CLASS

dissipation P according to the formula:

The current accuracy specification does not include variations in R

DIS

CLASS

resistance. The total classification current for a PD also includes the IC

quiescent current (I ). See Applications Information.

T = T + (P • 49°C/W)

J

A

DIS

IN_CLASS

Note 6: The LTC4268-1 operates with a negative supply voltage in the

range of –1.5V to –57V. To avoid confusion, voltages in this data sheet

are referred to in terms of absolute magnitude. Terms such as “maximum

negative voltage” refer to the largest negative voltage and a “rising

negative voltage” refers to a voltage that is becoming more negative.

Note 16: This parameter is assured by design and wafer level testing.

Note 17: Active high power good is referenced to V and is valid for

NEG

V

– V

≥ 4V.

PORTP

NEG

Note 18: The LTC4268-1 includes a dual current limit. At turn on, before

C1 is charged, the LTC4268-1 current level is set to I . After C1 is

Note 7: In IEEE 802.3af systems, the maximum voltage at the PD jack is

LIMIT_LOW

defined to be –57V.

charged and with I

floating, the LTC4268-1 switches to I

.

LIM_EN

LIMIT_HIGH

. The

With I

pin tied low, the LTC4268-1 switches to I

LIM_EN

LIMIT_DISA

Note 8: The LTC4268-1 is designed to work with two polarity protection

diodes in series with the input. Parameter ranges specified in the Electrical

Characteristics are with respect to LTC4268-1 pins and are designed to

meet IEEE 802.3af specifications when the drop from the two diodes is

included. See Applications Information.

Note 9: Signature resistance is measured via the two-point DV/DI method

as defined by IEEE 802.3af. The LTC4268-1 signature resistance is offset

from 25k to account for diode resistance. With two series diodes, the total

PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af

specifications. The minimum probe voltages measured at the LTC4268-1

pins are –1.5V and –2.5V. The maximum probe voltages are –9.1V and

–10.1V.

LTC4268-1 stays in I

below the UVLO turn-off threshold or a thermal overload occurs.

or I

until the input voltage drops

LIMIT_HIGH

LIMIT_DISA

Note 19: The LTC4268-1 features thermal overload protection. In the event

of an over temperature condition, the LTC4268-1 will turn off the power

MOSFET, disable the classification load current, and present an invalid

power good signal. Once the LTC4268-1 cools below the over temperature

limit, the LTC4268-1 current limit switches to I

operation resumes.

and normal

LIMIT_LOW

Note 20: I

is a safeguard current limit that is activated when the

LIMIT_DISA

normal input current limit (I

Currents at or near I

) is defeated using the I

pin.

LIMIT_HIGH

LIM_EN

will cause significant package heating and

LIMIT_DISA

may require a reduced maximum ambient operating temperature in order

to avoid tripping the thermal overload protection.

Note 21: Component value range guaranteed by design.

Note 10: The LTC4268-1 includes hysteresis in the UVLO voltages to

preclude any start-up oscillation. Per IEEE 802.3af requirements, the

LTC4268-1 will power up from a voltage source with 20Ω series resistance

on the first trial.

42681fc

5

LTC4268-1

Typical perForMance characTerisTics

Input Current vs Input Voltage

25k Detection Range

Input Current vs Input Voltage

0.5

0.4

0.3

0.2

12.0

11.5

100

80

T

= 25°C

CLASS 1 OPERATION

T

= 25°C

A

CLASS 5*

11.0

60

85°C

10.5

10.0

CLASS 4

CLASS 3

–40°C

40

CLASS 2

CLASS 1

0.1

0

20

0

9.5

9.0

CLASS 0

0

–4

–6

–8

–10

–2

0

–20

–30

–40

–50

–60

–12

–14

–16

–18

–20

–22

–10

INPUT VOLTAGE (V)

*OPTIONAL CLASS 5 CURRENT

42681 G01

42681 G03

42681 G02

Signature Resistance

vs Input Voltage

Class Operation vs Time

On Resistance vs Temperature

1.0

0.8

0.6

0.4

28

27

∆V V2 – V1

T

= 25°C

A

RESISTANCE =

=

INPUT

VOLTAGE

10V/DIV

∆I

DIODES: DF1501S

= 25°C

I – I

2 1

T

A

IEEE UPPER LIMIT

26

25

24

LTC4268-1 + 2 DIODES

CLASS

CURRENT

20mA/DIV

LTC4268-1 ONLY

IEEE LOWER LIMIT

0.2

0

23

22

–50

0

25

50

75

100

–25

TIME (10µs/DIV)

V1: –1

V2: –2

–3

–4

–5

–6

–7

–8

–9

–10

JUNCTION TEMPERATURE (°C)

INPUT VOLTAGE (V)

42681 G06

42681 G04

42681 G05

Active Low PWRGD: Output Low

Voltage vs Current

Active High PWRGD: Output Low

Voltage vs Current

Current Limit vs Input Voltage

1.0

0.8

0.6

0.4

0.2

0

800

600

400

200

4

3

2

1

0

–40°C

85°C

T

= 25°C

T

= 25°C

A

GND – V

= 4V

NEG

HIGH CURRENT MODE

LOW CURRENT MODE

–40°C

85°C

0

0.5

1

1.5

2

0

2

4

6

8

10

–40

–45

–50

–55

–60

INPUT CURRENT (mA)

INPUT VOLTAGE (V)

INPUT CURRENT (mA)

42681 G08

42681 G07

42681 G09

42681fc

6

LTC4268-1

Typical perForMance characTerisTics

V_CC(ON)and V_CC(OFF)

vs Temperature

V_CCStart-Up Current

vs Temperature

V_CCCurrent vs Temperature

10

9

16

15

14

13

12

11

10

9

300

250

200

150

V

CC(ON)

DYNAMIC CURRENT C = 1nF,

PG

C

= 1nF, f

= 100kHz

OSC

SG

8

7

6

STATIC PART CURRENT

= 14V

100

50

0

V

CC(OFF)

5

4

V

CC

3

8

–25

0

50

75 100 125

50

TEMPERATURE (°C)

100 125

–50

25

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

–50 –25

0

25

75

TEMPERATURE (°C)

42681 G10

42681 G12

42681 G11

SENSE Fault Voltage

vs Temperature

Oscillator Frequency

vs Temperature

SENSE Voltage vs Temperature

110

108

106

104

102

100

98

110

108

106

104

102

100

98

220

215

210

205

200

195

190

185

180

+

FB = 1.1V

+

SENSE = V

WITH V

C

= 100pF

OSC

SENSE

–

SENSE = V

SENSE

= 0V

–

WITH V

= 0V

SENSE

96

94

92

90

–50

0

25

50

75 100 125

50

TEMPERATURE (°C)

125

–25

–50 –25

0

25

50

75 100 125

–50

0

25

75 100

–25

TEMPERATURE (°C)

42681 G13

42681 G14

42681 G15

Feedback Pin Input Bias

vs Temperature

V

_FBvs Temperature

V_FBReset vs Temperature

1.240

1.239

1.238

1.237

1.236

1.235

1.234

1.233

1.232

1.231

1.230

300

250

200

150

1.04

1.03

1.02

1.01

1.00

0.99

0.98

0.97

0.96

R

CMP

OPEN

100

50

0

–50

0

25

50

75 100 125

–25

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

–25

0

50

75 100 125

–50

25

TEMPERATURE (°C)

42681 G16

42681 G17

42681 G18

42681fc

7

LTC4268-1

Typical perForMance characTerisTics

Feedback Amplifier Output

Current vs V_FB

Feedback Amplifier Source and

Sink Current vs Temperature

Feedback Amplifier g_m

vs Temperature

70

50

70

65

60

55

1100

1050

1000

950

SOURCE CURRENT

125°C

V

FB

= 1.1V

25°C

–40°C

SINK

30

CURRENT

V

= 1.4V

FB

10

–10

–30

–50

–70

50

45

40

900

0.9

1

1.1

1.2

(V)

1.3

1.4

1.5

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

V

FB

42681 G19

42681 G20

42681 G21

Feedback Amplifier Voltage Gain

vs Temperature

UVLO vs Temperature

I_UVLOHysteresis vs Temperature

1700

1650

1600

1550

1500

1450

1400

1350

1300

1250

1200

1150

1100

1.250

1.245

1.240

1.235

3.7

3.6

3.5

3.4

3.3

3.2

3.1

1.230

1.225

1.220

3.0

–25

0

50

75 100 125

50

TEMPERATURE (°C)

100 125

50

TEMPERATURE (°C)

100 125

–50

25

–50 –25

0

25

75

–50 –25

0

25

75

TEMPERATURE (°C)

42681 G22

42681 G23

42681 G24

Soft-Start Charge Current

vs Temperature

PG, SG Rise and Fall Times

vs Load Capacitance

80

70

60

50

40

30

20

10

0

23

22

21

20

19

18

17

16

15

T

= 25°C

A

FALL TIME

RISE TIME

–25

0

50

75 100 125

0

1

2

3

4

5

6

7

8

9

10

–50

25

CAPACITANCE (nF)

TEMPERATURE (°C)

42681 G26

42681 G25

42681fc

8

LTC4268-1

Typical perForMance characTerisTics

V_CCClamp Voltage

vs Temperature

Minimum PG On Time

vs Temperature

21.5

21.0

20.5

20.0

19.5

19.0

340

330

320

310

300

290

280

270

260

I

= 10mA

R

= 158k

tON(MIN)

CC

50

75 100 125

–50

–25

0

25

50

75 100 125

–50 –25

0

25

TEMPERATURE (°C)

42681 G27

42681 G28

Enable Delay Time

vs Temperature

PG Delay Time vs Temperature

325

305

285

265

300

250

R

ENDLY

= 90k

R

= 27.4k

= 16.9k

PGDLY

200

150

100

R

245

225

205

50

0

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

–50 –25

0

25

75

50

100 125

TEMPERATURE (°C)

42681 G30

42681 G29

42681fc

9

LTC4268-1

pin FuncTions

SHDN (Pin 1): Shutdown Input. Used to command the

SYNC (Pin 13): External Sync Input. This pin is used to

synchronize the internal oscillator with an external clock.

The positive edge of the clock causes the oscillator to dis-

charge causing PG to go low (off) and SG high (on). The

sync threshold is typically 1.5V. Tie to ground if unused.

See Applications Information for details.

LTC4268-1 to present an invalid signature and remain

inactive.ConnectingSHDNtoV

lowersthesignature

PORTP

resistance to an invalid value and disables the LTC4268-1

PD interface operations. If unused, tie SHDN to V

.

PORTN

NC (Pin 2): No Internal Connection.

SFST (Pin 14): Soft-Start. This pin, in conjunction with a

R

(Pin 3): Class Select Input. Used to set the current

CLASS

capacitor (C

) to GND, controls the ramp-up of peak

SFST

the LTC4268-1 maintains during classification. Connect a

primary current through the sense resistor. It is also used

resistor between R and V . (See Table 2.)

CLASS

PORTN

to control converter inrush at start-up. The SFST clamps

I

(Pin 4): Input Current Limit Enable. Used for

the V

voltage and thus limits peak current until soft-

LIM_EN

CMP

controlling the LTC4268-1 current limit behavior during

start is complete. The ramp time is approximately 70ms

per µF of capacitance. Leave SFST open if not using the

soft-start function.

powered operation. For normal operation, float I to

enableI

LIM_EN

todisable

current.TieI

toV

LIMIT_HIGH

LIM_EN

PORTN

input current limit. Note that the inrush current limit will

always be active. See Applications Information.

OSC (Pin 15): Oscillator. This pin in conjunction with an

external capacitor (C ) to GND defines the controller

OSC

V

(Pins 5, 6, 7): Power Input. Tie to the PD Input

oscillator frequency. The frequency is approximately

PORTN

through the diode bridge. Pins 5, 6 and 7 must be electri-

100kHz • 100/C

(pF).

OSC

cally tied together.

FB(Pin16):FeedbackAmplifierInput. Feedbackisusually

sensed via a third winding and enabled during the flyback

period.Thispinalsosinksadditionalcurrenttocompensate

NC (Pin 8): No Internal Connection.

SG (Pin 9): Secondary Gate Driver Output. This pin pro-

vides an output signal for a secondary-side synchronous

switch. Large dynamic currents may flow during voltage

transitions. See the Applications Information for details.

for load current variation as set by the R

pin. Keep the

CMP

Thevenin equivalent resistance of the feedback divider at

roughly 3k.

V

(Pin 17): Frequency Compensation Control. V

is

CMP

V

(Pin 10): Converter Voltage Supply. Bypass this pin

CC

used for frequency compensation of the switcher control

loop. Itistheoutputofthefeedbackamplifierandtheinput

tothecurrentcomparator.Switcherfrequencycompensa-

tion components are normally placed on this pin to GND.

The voltage on this pin is proportional to the peak primary

switch current. The feedback amplifier output is enabled

during the synchronous switch on time.

to GND with 4.7µF or greater. This pin has a 20V clamp

to ground. V has an undervoltage lockout function that

CC

turns on when V is approximately 15.3V and off at 9.7V.

CC

Inaconventional“trickle-charge”bootstrappedconfigura-

tion, the V supply current increases significantly during

CC

turn-on causing a benign relaxation oscillation action on

the V pin if the part does not start normally.

CC

UVLO (Pin 18): Undervoltage Lockout. A resistive divider

t

(Pin 11): Primary Switch Minimum On Time Control.

ON

from V to this pin sets an undervoltage lockout based

IN

A programming resistor (R ) to GND sets the minimum

Ton

upon V level (not V ). When the UVLO pin is below its

IN

CC

timeforeachcycle.SeeApplicationsInformationfordetails.

threshold, the gate drives are disabled, but the part draws

ENDLY (Pin 12): Enable Delay Time Control. The enable

delaytimeissetbyaprogrammingresistor(R

and disables the feedback amplifier for a fixed time after

the turn-off of the primary-side MOSFET. This allows the

leakage inductance voltage spike to be ignored for flyback

voltage sensing. See Applications Information for details.

its normal quiescent current from V . The V undervolt-

CC

)toGND

ENDLY

agelockoutsupersedesthisfunctionsoV mustbegreat

CC

enough to start the part. The bias current on this pin has

hysteresissuchthatthebiascurrentissourcedwhenUVLO

threshold is exceeded. This introduces a hysteresis at the

pin equivalent to the bias current change times the imped-

42681fc

10

LTC4268-1

pin FuncTions

ance of the upper divider resistor. The user can control

NC (Pin 25): No Internal Connection.

(Pins 26, 27, 28): System Negative Rail. Tie to the

the amount of hysteresis by adjusting the impedance of

V

NEG

the divider. Tie the UVLO pin to V if you are not using

CC

GND pin to supply power to the flyback controller through

this function. See the Applications Information for details.

This pin is used for the UVLO function of the switching

regulator. The PD interface section has an UVLO defined

by the IEEE 802.3af specification.

the internal power MOSFET. V is high impedance until

NEG

the input voltage rises above the UVLO turn-on threshold.

TheoutputisthenconnectedtoV throughacurrent-

PORTN

limited internal MOSFET switch. Pins 26, 27 and 28 must

SENSE–, SENSE+ (Pins 19, 20): Current Sense Inputs.

These pins are used to measure primary side switch cur-

rent through an external sense resistor. Peak primary side

current is used in the converter control loop. Make Kelvin

be electrically tied together.

PWRGD (Pin 29): Active High Power Good Output,

Open-Collector. Signals to the flyback controller that the

LTC4268-1 MOSFET is on and that the flyback controller

can start operation. High impedance indicates power is

connections to the sense resistor R

to reduce noise

SENSE

problems.SENSE–connectstotheGNDside.Atmaximum

current (V at its maximum voltage) SENSE pins have

good. PWRGD is referenced to V

and is low imped-

NEG

CMP

ance during inrush and in the event of a thermal overload.

PWRGD is clamped to 14V above V

100mV threshold. The signal is blanked (ignored) during

the minimum turn-on time.

.

NEG

PWRGD (Pin 30): Active Low Power Good Output, Open-

Drain. Signals to the DC/DC converter that the LTC4268-1

MOSFET is on and that the converter can start operation.

Low impedance indicates power is good. PWRGD is ref-

C

(Pin 21): Load Compensation Capacitive Control.

CMP

Connect a capacitor from C

to GND in order to reduce

CMP

the effects of parasitic resistances in the feedback sensing

path. A 0.1µF ceramic capacitor suffices for most applica-

tions.ShortthispintoGNDinlessdemandingapplications.

erenced to V

and is high impedance during detec-

PORTN

tion, classification and in the event of a thermal overload.

R

(Pin 22): Load Compensation Resistive Control.

PWRGD has no internal clamps.

CMP

Connect a resistor from R

to GND in order to com-

CMP

NC (Pin 31): No Internal Connection.

pensate for parasitic resistances in the feedback sensing

path. In less demanding applications, this resistor is not

needed and this pin can be left open. See Applications

Information for details.

V

(Pin 32): Positive Power Input. Tie to the input

PORTP

port power return through the input diode bridge.

GND (Pin 33): Ground. This is the negative rail connec-

tion for both signal ground and gate driver grounds. This

PGDLY (Pin 23): Primary Gate Delay Control. Connect an

external programming resistor (R

synchronous gate turn-off to primary gate turn-on. See

Applications Information for details.

pin should be connected to V . Careful attention must

) to set delay from

NEG

PGDLY

be paid to layout. See the Applications Information for

details.

PG (Pin 24): Primary Gate Drive. PG is the gate drive pin

for the primary side MOSFET Switch. Large dynamic cur-

rents flow during voltage transitions. See the Applications

Information for details.

42681fc

11

LTC4268-1

block DiagraM

CLASSIFICATION

CURRENT LOAD

SHDN

1

V

PORTP

1.237V

+

–

32

31

16k 25k

2

3

NC

R

CLASS

NC

PWRGD

30

I

LIM_EN

CONTROL

CIRCUITS

4

INPUT

CURRENT

LIMIT

PWRGD

1400mA

750mA

300mA

29

V

PORTN

+

5

6

7

14V

V

NEG

–

28

27

26

NEG

BOLD LINE INDICATES

HIGH CURRENT PATH

V

CC

10

CLAMPS

V

CC

UVLO

20V

0.7

+

–

+

–

FB

16

17

1.3

ERROR AMP

–

+

1.237V

REFERENCE

(V

V

15.3V

CMP

3V

)

FB

INTERNAL

REGULATOR

S

R

Q

COLLAPSE DETECT

–

+

UVLO

+

UVLO

–

SFST

1V

18

14

19

CURRENT

COMPARATOR

OVERCURRENT

FAULT

I

UVLO

–

+

–

TSD

–

SENSE

CURRENT

SENSE AMP

+

CURRENT TRIP

+

SENSE

SLOPE COMPENSATION

ENABLE

20

21

R

CMPF

50k

OSC

15

OSCILLATOR

C

CMP

SET

+

–

SYNC

13

11

23

12

LOAD

COMPENSATION

t

ON

LOGIC

BLOCK

R

CMP

PG

PGDLY

ENDLY

TO FB

22

24

V

CC

GATE DRIVE

PGATE

SGATE

+

3V

–

V

CC

GATE DRIVE

SG

9

GND

33

42681 BD

42681fc

12

LTC4268-1

applicaTions inForMaTion

OVERVIEW

OPERATION

Power over Ethernet (PoE) continues to gain popularity

as an increasing number of products are taking advantage

of having DC power and high speed data available from a

single RJ45 connector. As PoE is becoming established in

themarketplace,PoweredDevice(PD)equipmentvendors

arerunningintothe12.95Wpowerlimitestablishedbythe

IEEE 802.3af standard. To solve this problem and expand

the application of PoE, the LTC4268-1 breaks the power

barrierbyallowingcustomPoEapplicationstodeliverupto

35WforpowerhungryPoEapplicationssuchasdualband

access points, RFID readers and PTZ security cameras.

Note: Please refer to the simplified application circuit

(Figure 1) for voltage naming conventions used in this

data sheet.

The LTC4268-1 high power PD interface controller and

switchingregulatorhasseveralmodesofoperationdepend-

ing on the applied V

voltage as shown in Figure 2 and

PORT

summarized in Table 1. These various modes satisfy the

requirementsdefinedintheIEEE802.3afspecification.The

input voltage is applied to the V

pin with reference

PORTN

to the V

pin and is always negative.

PORTP

The LTC4268-1 is designed to be a complete solution for

PD applications with power requirements up to 35W. The

LTC4268-1interfaceswithcustomPowerSourcingEquip-

ment (PSE) using a high efficiency flyback topology for

maximumpowerdeliverywithouttheneedforopto-isolator

feedback.Off-the-shelfhighpowerPSEsareavailabletoday

from a variety of vendors for use with the LTC4268-1 to

allow quick implementation of a custom system.

SERIES DIODES

The IEEE 802.3af-defined operating modes for a PD refer-

ence the input voltage at the RJ45 connector on the PD.

In this data sheet port voltage is normally referenced to

the pins of the LTC4268-1. Note that the voltage ranges

specified in the LTC4268-1 Electrical Specifications are

referenced with respect to the IC pins.

RJ45

+

1

TX

16 T1

15

1

2

•

+

~

+

–

TX

14

11

3

6

•

2

3

+

V

OUT

TO PHY

RX

PORT

IN

10

9

7

8

–

RX

6

V

PORTP

V

CC

+

–

SPARE

PG

LTC4268-1

4

5

7

8

~

+

–

GND

SPARE

V

NEG

PORTN

PD FRONT END

SWITCHING REGULATOR

ISOLATED OUTPUT

42681 F01

Figure 1. Simplified Application Circuit With Voltage Naming Conventions

42681fc

13

LTC4268-1

applicaTions inForMaTion

DETECTION V1

TIME

The PD must be able to handle power received in either

polarity. For this reason, it is common to install diode

bridges between the RJ45 connector and the LTC4268-1

(Figure 3). The diode bridges introduce an offset that

affects the threshold points for each range of operation.

The LTC4268-1 meets the IEEE 802.3af-defined operating

modesbycompensatingforthediodedropsinthethreshold

points. For the signature, classification, and the UVLO

thresholds,theLTC4268-1extendstwodiodedropsbelow

the IEEE 802.3af specifications. The LTC4268-1 threshold

points support the use of either traditional or Schottky

diode bridges.

DETECTION V2

–10

–20

–30

–40

–50

CLASSIFICATION

UVLO

TURN-OFF

UVLO

TURN-ON

TIME

C1

τ = R

LOAD

–10

–20

–30

–40

–50

UVLO

OFF

UVLO

ON

UVLO

OFF

I

LIMIT_LOW

dV

dt

=

C1

TIME

RJ45

+

1

T1

TX

–10

–20

–30

–40

–50

POWER

BAD

POWER

GOOD

POWER

BAD

BR1

–

TX

2

3

+

TO PHY

RX

PWRGD TRACKS

IN

–

V

RX

POWERED

DEVICE (PD)

INTERFACE

6

V

PORTP

+

–

AS DEFINED

BY IEEE 802.3af

SPARE

20

10

BR2

4

5

LTC4268-1

D3

0.1µF

100V

POWER

BAD

POWER

GOOD

POWER

BAD

V

PORTN

7

8

42681 F03

SPARE

TIME

I

LOAD, I

LOAD

LIMIT_HIGH

Figure 3. PD Front End Using Diode Bridges on

Main and Spare Inputs

(UP TO I

)

LIMIT_HIGH

I

LIMIT_LOW

I

CLASS

CLASSIFICATION

DETECTION

TIME

DETECTION I

2

During detection, the PSE will apply a voltage in the range

of –2.8V to –10V on the cable and look for a 25k signature

resistor. This identifies the device at the end of the cable

as a PD. With the PSE voltage in the detection range, the

LTC4268-1 presents an internal 25k resistor between the

DETECTION I

1

V1 – 2 DIODE DROPS

25kΩ

V2 – 2 DIODE DROPS

25kΩ

SELECTION

I

=

I

=

1

2

I

DEPENDENT ON R

CLASS

= 300mA, I

= 750mA

LIMIT_LOW

LIMIT_HIGH

V

IN

I

=

LOAD

R

LOAD

V

and V

pins. This precision, temperature-

PORTP

PORTN

compensated resistor provides the proper characteristics

to alert the PSE that a PD is present and requests power

to be applied.

LTC4268-1

R

I

LOAD

IN

R

V

PORTP

CLASS

PSE

V

IN

PORT

+

R

PWRGD

CLASS

C1

PWRGD

V

NEG

PORTN

42681 F02

Figure 2. V_INVoltage, PWRGD, PWRGD and PD Current

as a Function of Port Voltage

42681fc

14

LTC4268-1

applicaTions inForMaTion

Table 1. LTC4268-1 Operational Mode as a Function

of V_PORTVoltage

tie SHDN to V_PORTP. Alternately, the SHDN pin can be

driven high with respect to V

. When SHDN is high,

PORTN

V

MODE OF OPERATION

PORT

all functions are disabled. For normal operation tie SHDN

0V to –1.4V

Inactive

to V

.

PORTN

–1.5V to –10.1V

–10.3V to –12.4V

25k Signature Resistor Detection

Classification Load Current Ramps Up from 0%

to 100%

CLASSIFICATION

–12.5V to UVLO*

UVLO* to –57V

Classification Load Current Active

Power Applied to PD Load

Once the PSE has detected a PD, the PSE may optionally

classify the PD. Classification provides a method for more

efficientallocationofpowerbyallowingthePSEtoidentify

lower-power PDs and assign the appropriate power level

to these devices. For each class, there is an associated

load current that the PD asserts onto the line during clas-

sification probing. The PSE measures the PD load current

in order to assign the proper PD classification. Class 0 is

included in the IEEE 802.3af specification to cover PDs

that do not support classification. Class 1-3 partition PDs

into three distinct power ranges as shown in Table 2.

*UVLO includes hysteresis.

Rising input threshold @ –38.9V

Falling input threshold @ –30.6V

The IEEE 802.3af specification requires the PSE to use

a DV/DI measurement technique to keep the DC offset

voltage of the diode bridge from affecting the signature

resistance measurement. However, the diode resistance

appears in series with the signature resistor and must

be included in the overall signature resistance of the PD.

Table 2. Summary of IEEE 802.3af Power Classifications and

LTC4268-1 R_CLASSResistor Selection

The LTC4268-1 compensates for the two series diodes

in the signature path by offsetting the internal resistance

so that a PD built with the LTC4268-1 meets the IEEE

802.3af specification.

MAXIMUM

NOMINAL

LTC4268-1

RCLASS

POWER LEVELS CLASSIFICATION

AT INPUT OF PD LOAD CURRENT RESISTOR

CLASS USAGE

(W)

(mA)

(W, 1%)

Open

124

In some designs that include an auxiliary power option,

such as an external wall adapter, it is necessary to con-

trol whether or not the PD is detected by a PSE. With the

LTC4268-1, the 25k signature resistor can be enabled or

disabled with the SHDN pin (Figure 4). Taking the SHDN

pin high will reduce the signature resistor to 10k which is

an invalid signature per the IEEE 802.3af specifications.

This will prevent a PSE from detecting and powering the

PD. This invalid signature is present in the PSE probing

range of –2.8V to –10V. When the input rises above –10V,

the signature resistor reverts to 25k to minimize power

dissipation in the LTC4268-1. To disable the signature,

0

1

2

3

4

5

Default

Optional

0.44 to 13.0

0.44 to 3.84

3.84 to 6.49

6.49 to 13.0

<5

10.5

18.5

28

69.8

45.3

Reserved by IEEE. See Apps

Undefined by IEEE. See Apps

40

30.9

56

22.1

Class 4 was reserved by the IEEE 802.3af committee

for future use and has been reassigned as a high power

indicator by IEEE 802.3at. The new Class 5 defined here

is available for system vendors to implement a unique

LTC4268-1

V

PORTP

25k SIGNATURE

RESISTOR

TO

PSE

16k

SHDN

V

PORTN

42681 F04

SIGNATURE DISABLE

Figure 4. 25k Signature Resistor With Disable

42681fc

15

LTC4268-1

applicaTions inForMaTion

classification for use in closed systems and is not defined

or supported by the IEEE 802.3af. With the extended clas-

sification range available in the LTC4268-1, it is possible

for system designers to define multiple classes using load

currents between 40mA and 75mA.

the LTC4268-1 from damage. When the die cools, clas-

sification is automatically resumed.

Classification presents a challenging stability problem

for the PSE due to the wide range of loads possible. The

LTC4268-1hasbeendesignedtoavoidPSEinteroperability

problems by maintaining a positive I-V slope throughout

the signature and classification ranges up to UVLO turn

on as shown in Figure 6. The positive I-V slope avoids

areas of negative resistance and helps prevent the PSE

from power cycling or getting “stuck” during signature

or classification probing. In the event a PSE overshoots

beyond the classification voltage range, the available load

currentaidsinreturningthePDbackintotheclassification

voltage range. (The PD input may otherwise be “trapped”

by a reverse-biased diode bridge and the voltage held by

the 0.1µF capacitor.) By gently ramping the classification

current on and maintaining a positive I-V slope until UVLO

turn-on, the LTC4268-1 provides a well behaved load,

assuring interoperability with any PSE.

During classification, the PSE presents a fixed voltage

between –15.5V and –20.5V to the PD (Figure 5). With the

input voltage in this range, the LTC4268-1 asserts a load

current from the V

pin through the R

resistor.

PORTP

CLASS

The magnitude of the load current is set with the selection

of the R

resistor. The resistor value associated with

each class is shown in Table 2.

CLASS

A substantial amount of power is dissipated in the

LTC4268-1duringclassification.TheIEEE802.3afspecifi-

cation limits the classification time to 75ms in order avoid

excessive heating. The LTC4268-1 is designed to handle

the power dissipation during the probe period. If the PSE

probing exceeds 75ms, the LTC4268-1 may overheat. In

this situation, the thermal protection circuit will engage

and disable the classification current source, protecting

CURRENT PATH

PSE

LTC4268-1

PROBING

VOLTAGE

SOURCE

V

PORTP

R

CLASS

–15.5V TO –20.5V

CONSTANT

LOAD

R

CLASS

CURRENT

INTERNAL

TO LTC4268-1

V

PORTN

42681 F05

V

PSE CURRENT MONITOR

–20

–30

0

–40

–10

PSE

PD

V

(V)

PORT

42681 F06

Figure 5. PSE Probing PD During Classification

Figure 6. LTC4268-1 Positive I-V Slope

42681fc

16

LTC4268-1

applicaTions inForMaTion

UNDERVOLTAGE LOCKOUT

INPUT CURRENT LIMIT

IEEE802.3afspecifiesamaximuminrushcurrentandalso

specifies a minimum load capacitor between the V

TheIEEE802.3afspecificationdictatesamaximumturn-on

voltage of 42V and a minimum turn-off voltage of 30V for

the PD. In addition, the PD must maintain large on-off

hysteresis to prevent current-resistance (I-R) drops in the

wiring between the PSE and the PD from causing start-up

oscillation. The LTC4268-1 incorporates an undervoltage

PORTP

and V

pins. To control turn-on surge currents in the

NEG

systemtheLTC4268-1integratesadualcurrentlimitcircuit

using an onboard power MOSFET and sense resistor to

provideacompleteinrushcontrolcircuitwithoutadditional

external components. At turn-on, the LTC4268-1 will limit

lockout(UVLO)circuitthatmonitorslinevoltageatV

PORTN

to determine when to apply power to the PD load (Figure

the inrush current to I , allowing the load capaci-

LIMIT_LOW

7). Before power is applied to the load, the V pin is

tor to ramp up to the line voltage in a controlled manner

withoutinterferencefromthePSEcurrentlimit.Bykeeping

thePDcurrentlimitbelowthePSEcurrentlimit, PDpower

up characteristics are well controlled and independent of

PSE behavior. This ensures interoperability regardless of

PSE output characteristics.

NEG

high impedance and there is no charge on capacitor C1.

When the input voltage rises above the UVLO turn-on

threshold, the LTC4268-1 removes the classification

load current and turns on the internal power MOSFET. C1

charges up under LTC4268-1 inrush current limit control

and the V

pin transitions from 0V to V

as shown

NEG

PORTN

After load capacitor C1 is charged up, the LTC4268-1

in Figure 2. The LTC4268-1 includes a hysteretic UVLO

circuit on V that keeps power applied to the load

switches to the high input current limit, I

. This

LIMIT_HIGH

PORTN

allows the LTC4268-1 to deliver up to 35W to the PD load

for high power applications. To maintain compatibility

with IEEE 802.3af power levels, it is necessary for the PD

designertoensurethePDsteady-statepowerconsumption

remainsbelowthelimitsshowninTable2.TheLTC4268-1

maintainsthehighinputcurrentlimituntiltheportvoltage

drops below the UVLO turn-off threshold.

until the magnitude of the input voltage falls below the

UVLO turn-off threshold. Once V falls below UVLO

PORTN

turn-off, the internal power MOSFET disconnects V

NEG

from V

and the classification current is re-enabled.

PORTN

C1 will discharge through the PD circuitry and the V

pin will go to a high impedance state.

+

C1

LTC4268-1

V

PORTP

5µF

MIN

TO

PSE

V

IN

UNDERVOLTAGE

LOCKOUT

CIRCUIT

V

NEG

PORTN

42681 F07

CURRENT-LIMITED

TURN ON

V

LTC4268-1

PORT

VOLTAGE

0V TO UVLO*

>UVLO*

POWER MOSFET

OFF

ON

*UVLO INCLUDES HYSTERESIS

RISING INPUT THRESHOLD ≅ –38.9V

FALLING INPUT THRESHOLD ≅ –30.6V

Figure 7. LTC4268-1 Undervoltage Lockout

42681fc

17

LTC4268-1

applicaTions inForMaTion

During the inrush event as C1 is being charged, a large

amount of power is dissipated in the MOSFET. The

LTC4268-1isdesignedtoacceptthisloadandisthermally

protectedtoavoiddamagetotheonboardpowerMOSFET.

Ifathermaloverloaddoesoccur, thepowerMOSFETturns

off, allowing the die to cool. Once the die has returned to

asafetemperature,theLTC4268-1automaticallyswitches

I

. The operation of the I

pin is summarized

LIM_EN

in Table 3.

Table 3. Summary of IEEE 802.3af Power Classifications and

LTC4268-1 R_CLASSResistor Selection

INRUSH CURRENT

LIMIT

OPERATING INPUT

CURRENT LIMIT

STATE OF I

LIM_EN

Floating

Tied to V

I

LIMIT_LOW

LIMT_HIGH

LIMIT_DISA

I

PORTN

to I

, and load capacitor C1 charging resumes.

LIMIT_LOW

The LTC4268-1 has the option of disabling the normal

operating input current limit, I , for custom

LIMIT_HIGH

POWER GOOD

high power PoE applications. To disable the current limit,

The LTC4268-1 includes complementary power good

outputs (Figure 8) to simplify connection to any DC/DC

converter. Power Good is asserted at the end of the inrush

event when load capacitor C1 is fully charged and the

DC/DC converter can safely begin operation. The power

good signal stays active during normal operation and is

de-asserted at power off when the port drops below the

UVLO threshold or in the case of a thermal overload event.

For PD designs that use a large load capacitor and also

connect I to V . To protect the LTC4268-1

LIM_EN

PORTN

from damage when the normal current limit is disabled, a

safeguardcurrentlimit,I keepsthecurrentbelow

LIMIT_DISA

destructive levels, typically 1.4A. Note that continuous

operation at or near the safeguard current limit will rapidly

overheat the LTC4268-1, engaging the thermal protection

circuit. For normal operations, float the I

pin. The

LIM_EN

inrush current limit

LTC4268-1 maintains the I

LIMIT_LOW

for charging the load capacitor regardless of the state of

LTC4268-1

30 PWRGD

UVLO

CONTROL

THERMAL SD

CIRCUIT

INRUSH COMPLETE

AND NOT IN THERMAL SHUTDOWN

POWER

NOT

GOOD

29 PWRGD

REF

GOOD

V

5

28

V

NEG

PORTN

V

< UVLO OFF

PORT

OR THERMAL SHUTDOWN

V

6

7

27

26

V

PORTN

NEG

PORTN

42681 F08

BOLD LINE INDICATES HIGH CURRENT PATH

Figure 8. LTC4268-1 Power Good Functional and State Diagram

42681fc

18

LTC4268-1

applicaTions inForMaTion

consume a lot of power, it is important to delay activation

of the DC/DC converter with the power good signal. If

the converter is not disabled during the current-limited

turn-on sequence, the DC/DC converter will rob current

intended for charging up the load capacitor and create a

slow rising input, possibly causing the LTC4268-1 to go

into thermal shutdown.

be as high as 16W. The LTC4268-1 protects itself from

damage by monitoring die temperature. If the die exceeds

the overtemperature trip point, the power MOSFET and

classification transistors are disabled until the part cools

down. Once the die cools below the overtemperature trip

point, all functions are enabled automatically. During

classification, excessive heating of the LTC4268-1 can

occur if the PSE violates the 75ms probing time limit.

In addition, the IEEE 802.3af specification requires a PD

to withstand application of any voltage from 0V to 57V

indefinitely. To protect the LTC4268-1 in these situations,

the thermal protection circuitry disables the classification

circuit and the input current if the die temperature exceeds

the overtemperature trip point. When the die cools down,

classification and input current are enabled.

The active high PWRGD pin features an internal,

open-collector output referenced to V . During inrush,

NEG

theactivehighPWRGDpinbecomesvalidwhenC1reaches

–4V and pulls low until the load capacitor is fully charged.

Atthatpoint,PWRGDbecomeshighimpedance,indicating

the switching regulator may begin running. The active

high PWRGD pin interfaces directly to the UVLO pin of

the LTC4268-1 with the aid of an external pull-up resistor

to Vcc. The PWRGD pin includes an internal 14V clamp to

OncetheLTC4268-1haschargeduptheloadcapacitorand

thePDispoweredandrunning,therewillbesomeresidual

heatingduetotheDCloadcurrentofthePDflowingthrough

the internal MOSFET. In some high current applications,

the LTC4268-1 power dissipation may be significant. The

LTC4268-1 uses a thermally enhanced DFN package that

includes an exposed pad which should be soldered to the

GND plane for heat sinking on the printed circuit board.

V

. During a power supply ramp down event, PWRGD

NEG

becomeslowimpedancewhenV

dropsbelowthe30V

PORT

PD UVLO turn-off threshold, then goes high impedance

whentheV voltagesfalltowithinthedetectionvoltage

PORT

range. Figure 11 shows a typical connection scheme for

the active high PWRGD pin.

The LTC4268-1 also includes an active low PWRGD pin

for system level use. PWRGD is referenced to the V

PORTN

MAXIMUM AMBIENT TEMPERATURE

pin and when active will be near the V

potential. The

PORTN

negative rail (GND) of the internal switching regulator will

The LTC4268-1 I

pin allows the PD designer to

LIM_EN

typically be referenced to V

and care must be taken to

NEG

disablethenormaloperatingcurrentlimit.Withthenormal

current limit disabled, it is possible to pass currents

as high as 1.4A through the LTC4268-1. In this mode,

significant package heating may occur. Depending on

the current, voltage, ambient temperature, and waveform

characteristics, the LTC4268-1 may shut down. To avoid

nuisancetripsofthethermalshutdown,itmaybenecessary

to limit the maximum ambient temperature. Limiting the

die temperature to 125°C will keep the LTC4268-1 from

hitting thermal shutdown. For DC loads the maximum

ambient temperature can be calculated as:

ensure that the difference in potential of the PWRGD pin

does not cause a problem for the switcher.

THERMAL PROTECTION

The LTC4268-1 includes thermal overload protection in

order to provide full device functionality in a miniature

package while maintaining safe operating temperatures.

At turn-on, before load capacitor C1 has charged up, the

instantaneous power dissipated by the LTC4268-1 can be

as high as 20W. As the load capacitor charges, the power

dissipation in the LTC4268-1 will decrease until it reaches

a steady-state value dependent on the DC load current.

The LTC4268-1 can also experience device heating after

turn-on if the PD experiences a fast input voltage rise. For

example, if the PD input voltage steps from –37V to –57V,

theinstantaneouspowerdissipatedbytheLTC4268-1can

T

MAX

= 125 – θ • PWR (°C)

JA

where T

is the maximum ambient operating tempera-

MAX

ture, θ is the junction-to-ambient thermal resistance

JA

(49°C/W), and PWR is the power dissipation for the

LTC4268-1 in Watts (I

2

• R ).

PD

ON

42681fc

19

LTC4268-1

applicaTions inForMaTion

EXTERNAL INTERFACE AND COMPONENT SELECTION

Table 4. Power over Ethernet Transformer Vendors

MODE OF OPERATION

206 Van Vorst Street

V

PORT

Transformer

Bel Fuse Inc.

Jersey City, NJ 07302

Tel: 201-432-0463

www.belfuse.com

Nodes on an Ethernet network commonly interface to

the outside world via an isolation transformer (Figure

9). For powered devices, the isolation transformer must

include a center tap on the media (cable) side. Proper

termination is required around the transformer to pro-

vide correct impedance matching and to avoid radiated

and conducted emissions. For high power applications

beyond IEEE 802.3af limits, the increased current levels

increase the current imbalance in the magnetics. This

imbalance reduces the perceived inductance and can

interfere with data transmission. Transformers specifi-

cally designed for high current applications are required.

Transformer vendors such as Bel Fuse, Coilcraft, Halo,

Pulse, and Tyco (Table 4) can provide assistance with

selection of an appropriate isolation transformer and

proper termination methods. These vendors have trans-

formers specifically designed for use in high power PD

applications.

Coilcraft Inc.

1102 Silver Lake Road

Gary, IL 60013

Tel: 847-639-6400

www.coilcraft.com

Halo Electronics

Pulse Engineering

Tyco Electronics

1861 Landings Drive

Mountain View, CA 94043

Tel: 650-903-3800

www.haloelectronics.com

12220 World Trade Drive

San Diego, CA 92128

Tel: 858-674-8100

www.pulseeng.com

308 Constitution Drive

Menlo Park, CA 94025-1164

Tel: 800-227-7040

www.circuitprotection.com

IEEE 802.3af allows power wiring in either of two configu-

rations on the TX/RX wires, and power can be applied to

the PD via the spare wire pair in the RJ45 connector. The

RJ45

+

1

TX

16 T1

15

1

2

BR1

HD01

–

TX

14

11

3

6

2

3

+

TO PHY

RX

10

9

7

8

–

RX

6

PULSE H2019

10Ω

8

C1

V

+

–

V

SPARE

PORTP

4

5

7

8

BR2

HD01

C14

D3

SMAJ58A

TVS

LTC4268-1

0.1µF

100V

SPARE

4

5

V

PORTN

NEG

OUT

42681 F09

Figure 9. PD Front-End Isolation Transformer, Diode Bridges, Capacitors and TVS

42681fc

20

LTC4268-1

applicaTions inForMaTion

PD is required to accept power in either polarity on both

the data and spare inputs; therefore it is common to install

diode bridges on both inputs in order to accommodate the

different wiring configurations. Figure 9 demonstrates an

implementation of the diode bridges to minimize heating.

The IEEE 802.3af specification also mandates that the

leakagebackthroughtheunusedbridgebelessthan28µA

when the PD is powered with 57V.

Transient Voltage Suppressor

The LTC4268-1 specifies and absolute maximum volt-

age of 100V and is designed to tolerate brief overvoltage

events. However, the pins that interface to the outside

world can routinely see excessive peak voltages. To pro-

tect the LTC4268-1, install a transient voltage suppressor

(D3) between the input diode bridge and the LTC4268-1,

as shown in Figure 9. An SMAJ58A is recommended for

typical PD applications. However, an SMBJ58A may be

preferred in applications where the PD front end must

absorb higher energy discharge events.

The LTC4268-1 has several different modes of operation

based on the voltage present between the V

PORTP

and

PORTN

V

pins. The forward voltage drop of the input diodes

in a PD design subtracts from the input voltage and will

affect the transition point between modes.

Auxiliary Power Source

In some applications, it may be necessary to power the

PD from an auxiliary power source such as a wall adapter.

The auxiliary power can be injected into the PD at several

locations and various trade-offs exist. Figure 10 demon-

stratesfourmethodsofconnectingexternalpowertoaPD.

The input diode bridge of a PD can consume over 4% of

the available power in some applications. Schottky diodes

canbeusedinordertoreducepowerloss. TheLTC4268-1

is designed to work with both standard and Schottky

diode bridges while maintaining proper threshold points

for IEEE 802.3af compliance.

Option 1 in Figure 10 inserts power before the LTC4268-1

interface controller. In this configuration, it is necessary

for the wall adapter to exceed the LTC4268-1 UVLO turn-

on requirement. This option provides input current limit

for the adapter, provides a valid power good signal and

simplifies power priority issues. As long as the adapter

applies power to the PD before the PSE, it will take priority

and the PSE will not power up the PD because the external

power source will corrupt the 25k signature. If the PSE

is already powering the PD, the adapter power will be in

parallel with the PSE. In this case, priority will be given to

the higher supply voltage. If the adapter voltage is higher,

the PSE may remove the port voltage since no current will

be drawn from the PSE. On the other hand, if the adapter

voltage is lower, the PSE will continue to supply power to

the PD and the adapter will not be used. Proper operation

will occur in either scenario.

Input Capacitor

The IEEE 802.3af/at standard includes an impedance

requirement in order to implement the AC disconnect

function. A 0.1µF capacitor (C14 in Figure 9) is used to

meet the AC impedance requirement.

Input Series Resistance

LinearTechnologyhasseenthecustomercommunitycable

discharge requirements increase by nearly 500,000 times

the original test levels. The PD must survive and operate

reliably not only when an initially charged cable connects

and dissipates the energy through the PD front end, but

alsowhentheelectricalpowersystemgroundsaresubject

to very high energy events (e.g., lightning strikes).

In these high energy events, adding 10Ω series resistance

Option 2 applies power directly to the DC/DC converter.

In this configuration the adapter voltage does not need

to exceed the LTC4268-1 turn-on UVLO requirement and

can be selected based solely on the PD load requirements.

It is necessary to include diode D9 to prevent the adapter

from applying power to the LTC4268-1. Power priority

issues require more intervention. If the adapter voltage

is below the PSE voltage, then the priority will be given

42681fc

into the V

pin greatly improves the robustness of

PORTP

the LTC4268-1 based PD (see Figure 9). The TVS limits

the voltage across the port while the 10Ω and 0.1µF ca-

pacitance reduces the edge rate the LT4268-1 encounters

across its pin. The added 10Ω series resistance does not

operationally affect the LTC4268-1 PD Interface, nor does

it affect its compliance with the IEEE 802.3 standard.

21

LTC4268-1

applicaTions inForMaTion

OPTION 1: AUXILIARY POWER INSERTED BEFORE LTC4268-1

RJ45

1

+

T1

TX

D3

SMAJ58A

TVS

~

+

–

C14

0.1µF

100V

TX

+

2

3

+

–

C1

TO PHY

RX

BR1

BR2

RX

V

IN

6

V

PORTP

• 42V ≤ V

WW

≤ 57V

+

–

SPARE

4

5

7

8

~

+

–

• NO POWER PRIORITY ISSUES

LTC4268-1

• LTC4268-1 CURRENT LIMITS FOR BOTH PoE AND V

WW

SPARE

V

PORTN NEG

+

D8

S1B

ISOLATED

WALL

TRANSFORMER

V

WW

–

OPTION 2: AUXILIARY POWER INSERTED AFTER LTC4268-1 WITH SIGNATURE DISABLED

RJ45

1

+

T1

TX

D3

SMAJ58A

TVS

~

+

–

C14

0.1µF

100V

+

2

3

+

C1

TO PHY

RX

BR1

BR2

–

RX

V

IN

6

V

4.7k

PORTP

+

–

SPARE

BSS63

4

5

7

8

~

+

–

LTC4268-1

D9

S1B

100k

SHDN

V

SPARE

V

PORTN NEG

• V

ANY VOLTAGE BASED ON PD LOAD

WW

+

V

D10

S1B

ISOLATED

WALL

TRANSFORMER

• REQUIRES EXTRA DIODE

• SEE APPS REGARDING POWER PRIORITY

WW

–

OPTION 3: AUXILIARY POWER APPLIED TO LTC4268-1 AND PD LOAD

RJ45

1

+

T1

TX

D3

SMAJ58A

~

+

–

TVS

+

C14

0.1µF

100V

2

3

+

C1

TO PHY

RX

BR1

BR2

–

RX

V

IN

6

V

PORTP

• 42V ≤ V

WW

≤ 57V

+

–

SPARE

4

5

7

8

• NO POWER PRIORITY ISSUES

~

+

–

LTC4268-1

• NO LTC4268-1 CURRENT LIMITS FOR V

WW

SPARE

V

PORTN NEG

+

D10

S1B

ISOLATED

WALL

TRANSFORMER

V

WW

–

OPTION 4: AUXILIARY POWER APPLIED TO ISOLATED LOAD

RJ45

1

+

T1

TX

D3

SMAJ58A

TVS

C14

0.1µF

100V

+

C1

~

+

–

ISOLATED DC/DC CONVERTER

2

3

+

TO PHY

RX

BR1

BR2

–

DRIVE

LOAD

RX

6

V

PORTP

+

–

PG

SPARE

4

5

7

8

~

+

–

LTC4268-1

• V

WW

ANY VOLTAGE BASED ON PD LOAD

• SEE APPS REGARDING POWER PRIORITY

• BEST ISOLATION

SHDN GND

SPARE

V

PORTN NEG

+

V

ISOLATED

WALL

TRANSFORMER

WW

–

Figure 10. Interfacing Auxiliary Power Source to the PD

42681fc

22

LTC4268-1

applicaTions inForMaTion

to the PSE power. The PD will draw power from the PSE

whiletheadapterwillremainunused. Thisconfigurationis

acceptableinatypicalPoEsystem.However,iftheadapter

voltage is higher than the PSE voltage, the PD will draw

power from the adapter. In this situation, it is necessary to

address the issue of power cycling that may occur if a PSE

is present. The PSE will detect the PD and apply power. If

the PD is being powered by the adapter, then the PD will

not meet the minimum load requirement and the PSE may

subsequentlyremovepower. ThePSEwillagaindetectthe

PD and power cycling will start. With an adapter voltage

above the PSE voltage, it is necessary to either disable the

signature as shown in option 2, or install a minimum load

on the output of the LTC4268-1 to prevent power cycling.

safety codes. Using option 4 along with an isolated power

supply addresses the isolation issue and it is no longer

necessary to protect the end-user from the power jack.

The above power cycling scenarios have assumed the

PSE is using DC disconnect methods. For a PSE using

AC disconnect, a PD with less than minimum load will

continue to be powered.

Walladaptershavebeenknowntogeneratevoltagespikes

outside their expected operating range. Care should be

taken to ensure no damage occurs to the LTC4268-1

or any support circuitry from extraneous spikes at the

auxiliary power interface.

Classification Resistor Selection (R

)

CLASS

A 3k, 1W resistor connected between V

will present the required minimum load.

and V

PORTP

NEG

The IEEE 802.3af specification allows classifying PDs into

four distinct classes with class 4 being reserved for future

use (Table 2). The LTC4268-1 supports all IEEE classes

and implements an additional Class 5 for use in custom

PoE applications. An external resistor connected from

Option 3 applies power directly to the DC/DC converter

bypassing the LTC4268-1 and omitting diode D9. With

the diode omitted, the adapter voltage is applied to the

LTC4268-1 in addition to the DC/DC converter. For this

reason, it is necessary to ensure that the adapter maintain

the voltage between 42V and 57V to keep the LTC4268-1

in its normal operating range. The third option has the

advantageofcorruptingthe25ksignatureresistancewhen

the external voltage exceeds the PSE voltage and thereby

solving the power priority issue.

R

CLASS

to V

(Figure 6) sets the value of the load

PORTN

current. The designer should determine which class the

PD is to advertise and then select the appropriate value of

R

from Table 2. If a unique load current is required,

CLASS

the value of R

can be calculated as:

CLASS

R

CLASS

= 1.237V/(I

– I

)

LOAD

IN_CLASS

Option 4 bypasses the entire PD interface and injects

power at the output of the low voltage power supply. If

the adapter output is below the low voltage output there

are no power priority issues. However, if the adapter is

above the internal supply, then option 4 suffers from the

same power priority issues as option 2 and the signature

should be disabled or a minimum load should be installed.

Showninoption4isonemethodtodisabletothesignature

while maintaining isolation.

I

is the LTC4268-1 IC supply current during

IN_CLASS

classification given in the electrical specifications. The

resistor must be 1% or better to avoid degrading

R

CLASS

the overall accuracy of the classification circuit. Resis-

tor power dissipation will be 100mW maximum and is

transient so heating is typically not a concern. In order

to maintain loop stability, the layout should minimize

capacitance at the R

node. The classification circuit

CLASS

can be disabled by floating the R

pin. The R

CLASS

should not be shorted to V

as this would force the

PORTN

If employing options 1 through 3, it is necessary to ensure

that the end-user cannot access the terminals of the aux-

iliary power jack on the PD since this would compromise

IEEE 802.3af isolation requirements and may violate local

LTC4268-1 classification circuit to attempt to source very

large currents. In this case, the LTC4268-1 will quickly go

into thermal shutdown.

42681fc

23

LTC4268-1

applicaTions inForMaTion

Power Good Interface

the pin voltage and thus creating hysteresis. As the pin

voltagedropsbelowthisthreshold,thecurrentisdisabled,

further dropping the UVLO pin voltage. If not used, the

The LTC4268-1 provides complimentary power good

signals to simplify the DC/DC converter interface. Using

the power good signal to delay converter operation until

the load capacitor is fully charged is recommended as this

will help ensure trouble free start-up.

UVLO pin can be disabled by tying to V .

CC

Shutdown Interface

To disable the 25k signature resistor, connect SHDN to

The active high PWRGD pin is controlled by an open col-

the V

pin. Alternately, the SHDN pin can be driven

PORTP

highwithrespecttoV

lector transistor referenced to V

while the active low

NEG

. Examplesofinterfacecircuits

PORTN

PWRGD pin is controlled by a high voltage, open-drain

MOSFET referenced to V . The PWRGD pin is de-

that disable the signature and all LTC4268-1 functions are

shown in Figure 10, options 2 and 4. Note that the SHDN

input resistance is relatively large and the threshold volt-

age is fairly low. Because of high voltages present on the

PORTN

signed to interface directly to the UVLO pin with the aid

of a pull-up resistor to Vcc. An example interface circuit

is shown in Figure 11.

printedcircuitboard,leakagecurrentsfromtheV

PORTP

couldinadvertentlypullSHDNhigh.To ensuretrouble-free

ACTIVE-HIGH ENABLE

operation,usehighvoltagelayouttechniquesinthevicinity

of SHDN. If unused, connect SHDN directly to V

.

PORTN

4k

V

PORTP

V

CC

TO

PSE

Load Capacitor

LTC4268-1

100k

TheIEEE802.3afspecificationrequiresthatthePDmaintain

a minimum load capacitance of 5µF. It is permissible to

have a much larger load capacitor and the LTC4268-1 can

charge very large load capacitors before thermal issues

become a problem. However, the load capacitor must not

be too large or the PD design may violate IEEE 802.3af

requirements. If the load capacitor is too large, there can

beaproblemwithinadvertentpowershutdownbythePSE.

For example, if the PSE is running at –57V (IEEE 802.3af

maximum allowed) and the PD is detected and powered

up, the load capacitor will be charged to nearly –57V. If

for some reason the PSE voltage is suddenly reduced to

–44V (IEEE 802.3af minimum allowed), the input bridge

will reverse bias and the PD power will be supplied by the

load capacitor. Depending on thesize of the load capacitor

and the DC load of the PD, the PD will not draw any power

from the PSE for a period of time. If this period of time

exceeds the IEEE 802.3af 300ms disconnect delay, the

PSE will remove power from the PD. For this reason, it

is necessary to evaluate the load current and capacitance

to ensure that inadvertent shutdown cannot occur. Refer

also to Thermal Protection in this data sheet for further

discussion on load capacitor selection.

PWRGD

–54V

V

UVLO

PORTN

42681 F11

Figure 11. Power Good Interface Example

Port Voltage Lockout

PoE applications require the PD interface to turn on below

42V and turn off above 30V. The LTC4268-1 includes an

internalportvoltagelockoutcircuittoimplementthisbasic

chip on/off control. Additionally, the LTC4268-1 includes

an enable/lockout function for the DC/DC converter that

is controlled by the UVLO pin and is intended to be driven

by PWRGD to ensure proper start-up. (Refer to Power

Good Interface.) Users have the ability to implement

higher turn-on voltages if necessary by connecting the

UVLO pin to an external resistive divider between V

PORTP

and V

. The UVLO pin also includes a bias current

PORTN

allowing implementation of hysteresis. When UVLO is

below 1.24V, gate drivers are disabled and the converter

sits idle. When the pin rises above the lockout threshold

a small current is sourced out of the UVLO pin, increasing

42681fc

24

LTC4268-1

applicaTions inForMaTion

MAINTAIN POWER SIGNATURE

transformerwindingvoltageduringtheflybackperiodand

uses that voltage to control output voltage. The internal

blocks are similar to many current mode controllers.

The differences lie in the feedback amplifier and load

compensation circuitry. The logic block also contains

circuitry to control the special dynamic requirements of

flyback control. For more information on the basics of

current mode switcher/controllers and isolated flyback

converters see Application Note 19.

In an IEEE 802.3af system, the PSE uses the maintain

power signature (MPS) to determine if a PD continues to

require power. The MPS requires the PD to periodically

draw at least 10mA and also have an AC impedance less

than 26.25k in parallel with 0.05µF. If either the DC current

is less than 10mA or the AC impedance is above 26.25k,

the PSE may disconnect power. The DC current must be

less than 5mA and the AC impedance must be above 2M

to guarantee power will be removed. The PD application

circuits shown in this data sheet present the required AC

impedance necessary to maintain power.

Feedback Amplifier—Pseudo DC Theory

ForthefollowingdiscussionrefertothesimplifiedFlyback

Amplifier diagram(Figure 12). When the primary side

MOSFET switch MP turns off, its drain voltage rises above

IEEE 802.3at Interoperability

the V

rail. Flyback occurs when the primary MOSFET

PORTP

In anticipation of the IEEE 802.3at standard release, the

LTC4268-1 can be combined with a simple external circuit

to be fully interoperable with an IEEE 802.3at-compliant

PSE.Formoreinformation,pleasecontactLinearTechnol-

ogy’s Application Engineering.

is off and the synchronous secondary MOSFET is on.

During flyback the voltage on nondriven transformer pins

is determined by the secondary voltage. The amplitude of

this flyback pulse as seen on the third winding is given as:

V

+ I

• ESR + R

(

)

OUT

SEC

DS(ON)

SWITCHING REGULATOR OVERVIEW

V

=

FLBK

N

SF

TheLTC4268-1includesacurrentmodeconverterdesigned

specificallyforuseinanisolatedflybacktopologyemploying

synchronous rectification. The LTC4268-1 operation is

similar to traditional current mode switchers. The major

difference is that output voltage feedback is derived via

sensing the output voltage through the transformer. This

precludes the need of an opto-isolator in isolated designs

greatly improving dynamic response and reliability. The

LTC4268-1hasauniquefeedbackamplifierthatsamplesa

R

= on resistance of the synchronous MOSFET MS

DS(ON)

I

= transformer secondary current

SEC

ESR = impedance of secondary circuit capacitor, winding

and traces

N = transformer effective secondary-to-flyback winding

SF

turns ratio (i.e., N /N

)

S

FLBK

T1

V

FLBK

FLYBACK

LTC4268-1 FEEDBACK AMP

R1

R2

•

FB

16

–

V

CMP

1V

17

V

IN

V

FB

•

C

VC

+

C

ISOLATED

OUTPUT

1.237V

–

+

PRIMARY

SECONDARY

MS

OUT

•

MP

COLLAPSE

DETECT

R

S

ENABLE

Q

42681 F12

Figure 12. LTC4268-1 Switching Regulator Feedback Amplifier

42681fc

25

LTC4268-1

applicaTions inForMaTion

The flyback voltage is scaled by an external resistive

divider R1/R2 and presented at the FB pin. The feedback

amplifier compares the voltage to the internal bandgap

reference.Thefeedbackampisactuallyatransconductance

Feedback Amplifier Dynamic Theory

So far, this has been a pseudo-DC treatment of flyback

feedback amplifier operation. But the flyback signal is a

pulse, not a DC level. Provision is made to turn on the

flyback amplifier only when the flyback pulse is present

using the enable signal as shown in the timing diagram

(Figure 13).

amplifier whose output is connected to V

only during

CMP

a period in the flyback time. An external capacitor on

the V pin integrates the net feedback amp current to

CMP

provide the control voltage to set the current mode trip

point. The regulation voltage at the FB pin is nearly equal

Minimum Output Switch On Time (t

)

ON(MIN)

to the bandgap reference V because of the high gain in

FB

The LTC4268-1 affects output voltage regulation via

flyback pulse action. If the output switch is not turned on,

there is no flyback pulse and output voltage information

is not available. This causes irregular loop response and

start-up/latch-up problems. The solution is to require

the primary switch to be on for an absolute minimum

time per each oscillator cycle. To accomplish this the

the overall loop. The relationship between V

and V

FLBK

FB

is expressed as:

R1+R2

V

=

• V

FB

FLBK

R2

Combining this with the previous V

expression yields

FLBK

current limit feedback is blanked each cycle for t

.

an expression for V

in terms of the internal reference,

ON(MIN)

OUT

If the output load is less than that developed under these

conditions, forced continuous operation normally occurs.

See Applications Information for further details.

programming resistors and secondary resistances:

R1+R2





V_OUT

=

• V •N

−I • ESR+R

(

)





_SF



FB

SEC

DS(ON)

R2

Enable Delay Time (ENDLY)

The effect of nonzero secondary output impedance is

discussedinfurtherdetail;seeLoadCompensationTheory.

The flyback pulse appears when the primary side switch

shutsoff.However,ittakesafinitetimeuntilthetransformer

primary side voltage waveform represents the output

voltage. This is partly due to rise time on the primary

The practical aspects of applying this equation for V

are found in the Applications Information.

OUT

V

FLBK

0.8 • V

PRIMARY SIDE

MOSFET DRAIN

VOLTAGE

FLBK

V

IN

PG VOLTAGE

SG VOLTAGE

42681 F13

t

MIN ENABLE

PG DELAY

ON(MIN)

ENABLE

DELAY

FEEDBACK

AMPLIFIER

ENABLED

Figure 13. LTC4268-1 Switching Regulator Timing Diagram

42681fc

26

LTC4268-1

applicaTions inForMaTion

side MOSFET drain node but, more importantly, is due

to transformer leakage inductance. The latter causes a

voltage spike on the primary side, not directly related to

output voltage. Some time is also required for internal

settling of the feedback amplifier circuitry. In order to

maintain immunity to these phenomena, a fixed delay is

introduced between the switch turn-off command and the

enabling of the feedback amplifier. This is termed “enable

delay.” In certain cases where the leakage spike is not

sufficiently settled by the end of the enable delay period,

regulation error may result. See Applications Information

for further details.

through the synchronous MOSFET R

and real life

DS(ON)

nonzero impedances of the transformer secondary and

output capacitor. This was represented previously by

the expression “I

• (ESR + R

).” However, it is

SEC

DS(ON)

generallymoreusefultoconvertthisexpressiontoeffective

output impedance. Because the secondary current only

flows during the off portion of the duty cycle (DC), the

effective output impedance equals the lumped secondary

impedance divided by off time DC.

Since the off time duty cycle is equal to 1 – DC then:

ESR+R_DS(ON)

R_S(OUT)

=

1−DC

Collapse Detect

where:

Once the feedback amplifier is enabled, some mechanism

is then required to disable it. This is accomplished by a

collapse detect comparator, which compares the flyback

R

S(OUT)

= effective supply output impedance

DC = duty cycle

and ESR are as defined previously

voltage (FB) to a fixed reference, nominally 80% of V .

FB

When the flyback waveform drops below this level, the

feedback amplifier is disabled.

R

DS(ON)

This impedance error may be judged acceptable in less

critical applications, or if the output load current remains

relatively constant. In these cases the external FB resistive

divider is adjusted to compensate for nominal expected

error. Inmoredemandingapplications, outputimpedance

error is minimized by the use of the load compensation

function. Figure 14 shows the block diagram of the load

compensation function. Switch current is converted to

a voltage by the external sense resistor, averaged and

Minimum Enable Time

The feedback amplifier, once enabled, stays on for a fixed

minimum time period termed “minimum enable time.”

This prevents lockup, especially when the output voltage

is abnormally low; e.g., during start-up. The minimum

enable time period ensures that the V

node is able to

CMP

“pump up” and increase the current mode trip point to

the level where the collapse detect system exhibits proper

operation. This time is set internally.

V

T1

FLBK

Effects of Variable Enable Period

R1

R2

•

FB

16

The feedback amplifier is enabled during only a portion of

thecycletime.Thiscanvaryfromthefixedminimumenable

time described to a maximum of roughly the “off” switch

time minus the enable delay time. Certain parameters of

feedbackampbehavioraredirectlyaffectedbythevariable

enable period. These include effective transconductance

Q1 Q2

V

FB

V

PORTP

LOAD

COMP I

•

MP

+

R

CMPF

50k

+

Q3

A1

SENSE

20

–

and V

node slew rate.

CMP

22

R

CMP

21

C

R

SENSE

CMP

Load Compensation Theory

The LTC4268-1 uses the flyback pulse to obtain

information about the isolated output voltage. An error

source is caused by transformer secondary current flow

42681 F13

Figure 14. Load Compensation Diagram

42681fc

27

LTC4268-1

applicaTions inForMaTion

lowpass filtered by the internal 50k resistor R

and

Nominal output impedance cancellation is obtained by

equating this expression with R

CMPF

the external capacitor on C . This voltage is impressed

:

CMP

S(OUT)

across the external R

resistor by op amp A1 and

CMP

ESR+R_DS(ON)

1−DC

R_SENSE

R_CMP

transistorQ3producingacurrentatthecollectorofQ3that

is subtracted from the FB node. This effectively increases

the voltage required at the top of the R1/R2 feedback

divider to achieve equilibrium.

K1•

•R1•N_SF

=

Solving for R

gives:

CMP

R_SENSE• 1−DC

ESR+R_DS(ON)

(

)

•R1•N_SF

The average primary side switch current increases to

maintain output voltage regulation as output loading

R_CMP=K1•

increases. TheincreaseinaveragecurrentincreasesR

CMP

resistor current which affects a corresponding increase

in sensed output voltage, compensating for the IR drops.

Assuming relatively fixed power supply efficiency, Eff,

power balance gives:

Thepracticalaspectsofapplyingthisequationtodetermine

an appropriate value for the R

Applications Information.

resistor are found in the

CMP

Transformer Design

P

V

= Eff • P

IN

OUT

Transformerdesign/specificationisthemostcriticalpartof

a successful application of the LTC4268-1. The following

sections provide basic information about designing the

transformer and potential trade-offs. If you need help, the

LTC Applications group is available to assist in the choice

and/or design of the transformer.

• I

= Eff • V • I

IN IN

OUT OUT

Average primary side current is expressed in terms of

output current as follow:

I_IN=K1•I_OUT

where:

Turns Ratios

V_OUT

K1=

V •Eff

The design of the transformer starts with determining

dutycycle(DC). DCimpactsthecurrentandvoltagestress

on the power switches, input and output capacitor RMS

currents and transformer utilization (size vs power). The

ideal turns ratio is:

IN

So the effective change in V

target is:

OUT

R_SENSE

DV_OUT=K1•

•R1•N_SF

R_CMP

V_OUT

1−DC

DC

thus:

N_DEAL

=

•

V

IN

DV_OUT

DI_OUT

R_SENSE

R_CMP

=K1•

•R1•N_SF

Avoid extreme duty cycles as they, in general, increase

currentstresses. Areasonabletargetfordutycycleis50%

at nominal input voltage.

where:

K1 = dimensionless variable related to V ,

IN

For instance, if we wanted a 48V to 5V converter at 50%

DC then:

V

and efficiency as explained above

OUT

R

SENSE

= external sense resistor

5 1− 0.5

• =

1

9.6

N_DEAL

=

48 0.5

42681fc

28

LTC4268-1

applicaTions inForMaTion

In general, better performance is obtained with a lower

turns ratio. A DC of 45.5% yields a 1:8 ratio. Note the

use of the external feedback resistive divider ratio to set

output voltage provides the user additional freedom in

selecting a suitable transformer turns ratio. Turns ratios

that are the simple ratios of small integers; e.g., 1:1, 2:1,

3:2 help facilitate transformer construction and improve

performance. When building a supply with multiple

outputs derived through a multiple winding transformer,

lower duty cycle can improve cross regulation by keeping

the synchronous rectifier on longer, and thus, keep

secondary windings coupled longer. For a multiple output

transformer, the turns ratio between output windings is

critical and affects the accuracy of the voltages. The ratio

theenabledelaytime,outputvoltageregulationisaffected.

Thefeedbacksystemhasadeliberatelylimitedinputrange,

roughly 50mVreferredtotheFBnode.Thisrejectshigher

voltage leakage spikes because once a leakage spike is

several volts in amplitude; a further increase in amplitude

has little effect on the feedback system. Therefore, it is

advisable to arrange the snubber circuit to clamp at as

highavoltageaspossible,observingMOSFETbreakdown,

such that leakage spike duration is as short as possible.

ApplicationNote19providesagoodreferenceonsnubber

design.

As a rough guide, leakage inductance of several percent

(of mutual inductance) or less may require a snubber, but

exhibit little to no regulation error due to leakage spike

behavior. Inductances from several percent up to perhaps

ten percent cause increasing regulation error.

between two output voltages is set with the formula V

OUT2

= V

• N21 where N21 is the turns ratio between the

OUT1

two windings. Also keep the secondary MOSFET R

DS(ON)

Avoid double digit percentage leakage inductances. There

isapotentialforabruptlossofcontrolathighloadcurrent.

Thiscuriousconditionpotentiallyoccurswhentheleakage

spikebecomessuchalargeportionoftheflybackwaveform

that the processing circuitry is fooled into thinking that

the leakage spike itself is the real flyback signal! It then

reverts to a potentially stable state whereby the top of the

leakage spike is the control point, and the trailing edge of

theleakagespiketriggersthecollapsedetectcircuitry.This

typically reduces the output voltage abruptly to a fraction,

roughly one-third to two-thirds of its correct value. Once

load current is reduced sufficiently, the system snaps

back to normal operation. When using transformers with

considerableleakageinductance,exercisethisworst-case

check for potential bistability:

small to improve cross regulation. The feedback winding

usually provides both the feedback voltage and power for

the LTC4268-1. Set the turns ratio between the output and

feedback winding to provide a rectified voltage that under

worst-case conditions is greater than the 11V maximum

V

turn-off voltage.

CC

V_OUT

11+ V_F

N_SF

>

where:

V =Diode Forward Voltage

F

5

1

For our example: N_SF>

=

11+ 0.7 2.34

1

3

We will choose

1. Operate the prototype supply at maximum expected

load current.

Leakage Inductance

2. Temporarily short-circuit the output.

Transformer leakage inductance (on either the primary or

secondary) causes a spike after the primary side switch

turn-off. This is increasingly prominent at higher load

currents, where more stored energy is dissipated. Higher

flyback voltage may break down the MOSFET switch if it

3. Observe that normal operation is restored.

If the output voltage is found to hang up at an abnormally

lowvalue,thesystemhasaproblem.Thisisusuallyevident

bysimultaneouslyviewingtheprimarysideMOSFETdrain

voltage to observe firsthand the leakage spike behavior.

has too low a BV

rating. One solution to reducing this

DSS

spike is to use a snubber circuit to suppress the voltage

excursion. However, suppressing the voltage extends the

flyback pulse width. If the flyback pulse extends beyond

A final note—the susceptibility of the system to bistable

behavior is somewhat a function of the load current/

voltage characteristics. A load with resistive—i.e., I = V/R

42681fc

29

LTC4268-1

applicaTions inForMaTion

behavior—is the most apt to be bistable. Capacitive loads

As a general rule, keep X in the range of 20% to 40%

(i.e., X = 0.2 to 0.4). Higher values of ripple will increase

conduction losses, while lower values will require larger

cores.

2

that exhibit I = V /R behavior are less susceptible.

Secondary Leakage Inductance

Leakage inductance on the secondary forms an inductive

divider on the transformer secondary, reducing the size

of the flyback pulse. This increases the output voltage

target by a similar percentage. Note that unlike leakage

spike behavior; this phenomenon is independent of load.

Since the secondary leakage inductance is a constant

percentage of mutual inductance (within manufacturing

variations), the solution is to adjust the feedback resistive

divider ratio to compensate.

Ripplecurrentandpercentagerippleislargestatminimum

duty cycle; in other words, at the highest input voltage.

P

L is calculated from:

2

V

_IN(MAX)•DC_MIN

V

_IN(MAX)•DC_MIN²•Eff

(

)

(

)

L_P=

=

f_OSC• X_MAX•P

f_OSC• X_MAX•P_OUT

IN

where:

f

is the oscillator frequency

OSC

Winding Resistance Effects

DC

is the DC at maximum input voltage

MIN

Primary or secondary winding resistance acts to reduce

X

is ripple current ratio at maximum input voltage

MAX

overallefficiency(P /P ).Secondarywindingresistance

OUT IN

Using common high power PoE values a 48V (41V < V

increases effective output impedance, degrading load

regulation. Load compensation can mitigate this to some

extent but a good design keeps parasitic resistances low.

IN

< 57V) to 5V/5.3A Converter with 90% efficiency, P

=

OUT

26.5W and P = 29.5W Using X = 0.4 N = 1/8 and f

IN

OSC

= 200kHz:

Bifilar Winding

1

DC_MIN

=

= 41.2%

A bifilar or similar winding is a good way to minimize

troublesome leakage inductances. Bifilar windings also

improve coupling coefficients and thus improve cross

regulation in multiple winding transformers. However,

tight coupling usually increases primary-to-secondary

capacitance and limits the primary-to-secondary

breakdown voltage, so it isn’t always practical.

N• V

1 57

IN(MAX)

1+ •

1+

8 5

V_OUT

2

57V •0.412

200kHz •0.4•26.5W

(

)

L_P=

= 260µH

Optimization might show that a more efficient solution

is obtained at higher peak current but lower inductance

and the associated winding series resistance. A simple

spreadsheet program is useful for looking at trade-offs.

Primary Inductance

The transformer primary inductance, L , is selected

P

based on the peak-to-peak ripple current ratio (X) in the

transformer relative to its maximum value.

42681fc

30

LTC4268-1

applicaTions inForMaTion

Transformer Core Selection

activityonallthesecondarywindings.Thusloadregulation

is affected by each winding’s load. Take care to minimize

cross regulation effects.

Once L is known, the type of transformer is selected.

P

High efficiency converters use ferrite cores to minimize

core loss. Actual core loss is independent of core size for

afixedinductance,butdecreasesasinductanceincreases.

Sinceincreasedinductanceisaccomplishedthroughmore

turns of wire, copper losses increase. Thus transformer

design balances core and copper losses. Remember that

increasedwindingresistancewilldegradecrossregulation

and increase the amount of load compensation required.

Setting Feedback Resistive Divider

TheexpressionforV developedintheOperationsection

OUT

is rearranged to yield the following expression for the

feedback resistors:















V_OUT+I_SEC• ESR+R

(

)

DS(ON)



R1=R2

−1

V_FB•N_SF







The main design goals for core selection are reducing

copper losses and preventing saturation. Ferrite core

material saturates hard, rapidly reducing inductance

when the peak design current is exceeded. This results

in an abrupt increase in inductor ripple current and,

consequently, output voltage ripple. Do not allow the core

to saturate! The maximum peak primary current occurs



Continuing the example, if ESR + R

3.32k, then:

= 8mW, R2 =

DS(ON)

5+ 5.3•0.008

1.237 •1/ 3







R1= 3.32k

−1 = 37.28k







at minimum V :

IN

choose 37.4k.

P

X



_MIN



IN

I_PK

=

• 1+

It is recommended that the Thevenin impedance of the

resistive divider (R1||R2) is roughly 3k for bias current

cancellation and other reasons.







V

_IN(MIN)•DC_MAX

2

now:

1

DC_MAX

=

= 49.4%

Current Sense Resistor Considerations

N• V

1 41

1+ •

8 5

IN MIN

(

)

1+

The external current sense resistor is used to control peak

primary switch current, which controls a number of key

converter characteristics including maximum power and

external component ratings. Use a noninductive current

sense resistor (no wire-wound resistors). Mounting the

resistordirectlyaboveanunbrokengroundplaneconnected

with wide and short traces keeps stray resistance and

inductance low.

V_OUT

2

V

_IN(MIN)•DC_MAX

(

)

41• 49.4%

(

)

X_MIN

=

f_OSC•L_P•P

200kHz •260µH•29.5W

IN

= 0.267

Using the example numbers leads to:

29.5W

41•0.494

0.267

2







ThedualsensepinsallowforafullKelvinconnection.Make

sure that SENSE+ and SENSE– are isolated and connect

close to the sense resistor.

I_PK

=

• 1+

=1.65A







Peakcurrentoccursat100mVofsensevoltageV

. So

Multiple Outputs

SENSE

/I . For example, a

the nominal sense resistor is V

SENSE PK

One advantage that the flyback topology offers is that

additionaloutputvoltagescanbeobtainedsimplybyadding

windings. Designing a transformer for such a situation is

beyondthescopeofthisdocument.Formultiplewindings,

realize that the flyback winding signal is a combination of

peakswitchcurrentof10Arequiresanominalsenseresistor

of 0.010W Note that the instantaneous peak power in the

sense resistor is 1W, and that it is rated accordingly. The

use of parallel resistors can help achieve low resistance,

low parasitic inductance and increased power capability.

42681fc

31

LTC4268-1

applicaTions inForMaTion

Size R

SENSE

using worst-case conditions, minimum L ,

The suggested empirical method is as follows:

SENSE

P

V

and maximum V . Continuing the example, let us

IN

1. Build a prototype of the desired supply including the

actual secondary components.

assumethatourworst-caseconditionsyieldanI of40%

PK

above nominal so I = 2.3A. If there is a 10% tolerance

PK

2. Temporarily ground the C

pin to disable the load

on R

and minimum V

= 88mV, then R

•

CMP

SENSE

compensation function. Measure output voltage while

sweeping output current over the expected range.

Approximate the voltage variation as a straight line.

110% = 88mV/2.3A and nominal R

= 35mW. Round

SENSE

to the nearest available lower value, 33mW.

Selecting the Load Compensation Resistor

ꢀ DV /DI

= R

.

OUT OUT

S(OUT)

The expression for R

section as:

was derived in the Operation

CMP

3. CalculateavaluefortheK1constantbasedonV , V

IN OUT

and the measured efficiency.

R_SENSE• 1−DC

ESR+R_DS(ON)

(

)

4. Compute:

R_CMP=K1•

•R1•N_SF

R_SENSE

R_S(OUT)

R_CMP=K1•

•R1•N_SF

Continuing the example:





V_OUT

5

5. Verify this result by connecting a resistor of this value

from the R pin to ground.

K1=

DC=

=

= 0.116





V •Eff

48 •90%





CMP

IN

1

N•V

1

6. DisconnectthegroundshorttoC

andconnecta0.1µF

CMP

=

= 45.5%

1 48

1+ •

8 5

filter capacitor to ground. Measure the output imped-

anceR =DV /DI withthenewcompensation

IN(NOM)

1+

S(OUT)

OUT OUT

V_OUT

in place. R

should have decreased significantly.

S(OUT)

If ESR+R_DS(ON)= 8mW

Fine tuning is accomplished experimentally by slightly

altering R . A revised estimate for R is:

33mW • 1− 0.455

(

)

1

3

CMP

R_CMP= 0.116 •

= 3.25k

•37.4kW •

8mW





R_S(OUT)CMP

R′_CMP=R_CMP• 1+





R_S(OUT)





This value for R

is a good starting point, but empirical

CMP

methodsarerequiredforproducingthebestresults.Thisis

becauseseveraloftherequiredinputvariablesaredifficult

to estimate precisely. For instance, the ESR term above

includesthatofthetransformersecondary,butitseffective

ESRvaluedependsonhighfrequencybehavior,notsimply

DC winding resistance. Similarly, K1 appears as a simple

where R′ is the new value for the load compensation

CMP

resistor.R

istheoutputimpedancewithR

S(OUT)CMP

CMP

in place and R

is the output impedance with no

S(OUT)

load compensation (from step 2).

ratio of V to V

times efficiency, but theoretically

IN

OUT

estimating efficiency is not a simple calculation.

42681fc

32

LTC4268-1

applicaTions inForMaTion

Setting Frequency

Selecting Timing Resistors

The switching frequency of the LTC4268-1 is set by an

external capacitor connected between the OSC pin and

ground. Recommended values are between 200pF and

33pF, yielding switching frequencies between 50kHz and

250kHz.Figure15showsthenominalrelationshipbetween

external capacitance and switching frequency. Place the

capacitor as close as possible to the IC and minimize OSC

trace length and area to minimize stray capacitance and

potential noise pickup.

There are three internal “one-shot” times that are

programmedbyexternalapplicationresistors:minimumon

time,enabledelaytimeandprimaryMOSFETturn-ondelay.

These are all part of the isolated flyback control technique,

and their functions are previously outlined in the Theory

of Operation section. The following information should

help in selecting and/or optimizing these timing values.

Minimum Output Switch On Time (t

)

ON(MIN)

Minimumontimeistheprogrammableperiodduringwhich

current limit is blanked (ignored) after the turn on of the

primarysideswitch.Thisimprovesregulatorperformance

by eliminating false tripping on the leading edge spike in

the switch, especially at light loads. This spike is due to

boththegate/sourcechargingcurrentandthedischargeof

drain capacitance. The isolated flyback sensing requires a

pulse to sense the output. Minimum on time ensures that

the output switch is always on a minimum time and that

there is always a signal to close the loop. The LTC4268-1

does not employ cycle skipping at light loads. Therefore,

You cansynchronizetheoscillatorfrequencytoanexternal

frequency. This is done with a signal on the SYNC pin. Set

the LTC4268-1 frequency 10% slower than the desired

external frequency using the OSC pin capacitor, then use

a pulse on the SYNC pin of amplitude greater than 2V

and with the desired frequency. The rising edge of the

SYNC signal initiates an OSC capacitor discharge forcing

primaryMOSFEToff(PGvoltagegoeslow).Iftheoscillator

frequency is much different from the sync frequency,

problemsmayoccurwithslopecompensationandsystem

stability. Keep the sync pulse width greater than 500ns.

300

200

100

50

30

100

(pF)

200

C

OSC

42681 F15

Figure 15. f_OSCvs OSC Capacitor Values

42681fc

33

LTC4268-1

applicaTions inForMaTion

minimum on time along with synchronous rectification

setstheswitchovertoforcedcontinuousmodeoperation.

Primary Gate Delay Time (PGDLY)

Primary gate delay is the programmable time from the

turn-off of the synchronous MOSFET to the turn-on of

the primary side MOSFET. Correct setting eliminates

overlap between the primary side switch and secondary

side synchronous switch(es) and the subsequent current

spike in the transformer. This spike will cause additional

component stress and a loss in regulator efficiency.

The t

resistor is set with the following equation

ON(MIN)

t_ON(MIN)ns −104

( )

R_tON(MIN)kW =

(

)

1.063

Keep R

greater than 70k. A good starting value

tON(MIN)

is 160k.

The primary gate delay resistor is set with the following

equation:

Enable Delay Time (ENDLY)

Enable delay time provides a programmable delay between

turn-off of the primary gate drive node and the subsequent

enablingofthefeedbackamplifier.Asdiscussedearlier,this

delay allows the feedback amplifier to ignore the leakage

inductancevoltagespikeontheprimaryside.Theworst-case

leakage spike pulse width is at maximum load conditions.

So set the enable delay time at these conditions.

t_PGDLYns + 47

( )

R_PGDLYkW =

(

)

9.01

A good starting point is 27k.

Soft-Start Function

TheLTC4268-1containsanoptionalsoft-startfunctionthat

is enabled by connecting an external capacitor between

the SFST pin and ground. Internal circuitry prevents the

While the typical applications for this part use forced

continuous operation, it is conceivable that a secondary

side controller might cause discontinuous operation at

light loads. Under such conditions the amount of energy

stored in the transformer is small. The flyback waveform

becomes “lazy” and some time elapses before it indicates

theactualsecondaryoutputvoltage.Theenabledelaytime

should be made long enough to ignore the “irrelevant”

portion of the flyback waveform at light loads.

control voltage at the V

pin from exceeding that on

CMP

the SFST pin. There is an initial pull-up circuit to quickly

bringtheSFSTvoltagetoapproximately0.8V.Fromthereit

chargestoapproximately2.8Vwitha20µAcurrentsource.

The SFST node is discharged to 0.8V when a fault occurs.

AfaultoccurswhenV istoolow(undervoltagelockout),

CC

current sense voltage is greater than 200mV or the IC’s

thermal (over temperature) shutdown is tripped. When

Even though the LTC4268-1 has a robust gate drive, the

gate transition time slows with very large MOSFETs. In-

crease delay time as required when using such MOSFETs.

SFST discharges, the V

node voltage is also pulled low

CMP

to below the minimum current voltage. Once discharged

and the fault removed, the SFST charges up again. In this

manner, switch currents are reduced and the stresses in

the converter are reduced during fault conditions.

Theenabledelayresistorissetwiththefollowingequation:

t_ENDLYns − 30

( )

R_ENDLYkW =

(

)

2.616

The time it takes to fully charge soft-start is:

C_SFST•1.4V

KeepR

greaterthan40k.Agoodstartingpointis56k.

ENDLY

t_ss=

= 70kW •C_SFSTµF

(

)

20µA

42681fc

34

LTC4268-1

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Converter Start-Up

IfC isundersized,V reachestheV turn-offthreshold

TR

CC

before stabilization and the LTC4268-1 turns off. The V

CC

The standard topology for the LTC4268-1 utilizes a third

transformer winding on the primary side that provides

node then begins to charge back up via R to the turn-on

TR

threshold, where the part again turns on. Depending upon

the circuit, this may result in either several on-off cycles

beforeproperoperationisreached,orpermanentrelaxation

both feedback information and local V power for the

CC

LTC4268-1 (see Figure 16). This power “bootstrapping”

improves converter efficiency but is not inherently self-

starting.Start-upisaffectedwithanexternal“tricklecharge”

oscillation at the V node.

CC

resistor and the LTC4268-1’s internal V undervoltage

R

TR

is selected to yield a worst-case minimum charging

CC

lockout circuit. The V undervoltage lockout has wide

current greater than the maximum rated LTC4268-1 start-

up current, and a worst-case maximum charging current

less than the minimum rated LTC4268-1 supply current.

CC

hysteresis to facilitate start-up.

Inoperation,the“tricklecharge”resistorR isconnected

TR

to V and supplies a small current, typically on the order

V

_IN(MIN)− V_{CC(ON_MAX)}

IN

R_TR(MAX)

and

<

of 1mA to charge C . Initially the LTC4268-1 is off and

TR

I_{CC(ST _MAX)}

draws only its start-up current. When C reaches the

TR

V

CC

turn-on threshold voltage the LTC4268-1 turns on

abruptly and draws its normal supply current.

V

_IN(MAX)− V_{CC(ON_MIN)}

R_TR(MIN)

>

Switching action commences and the converter begins to

deliver power to the output. Initially the output voltage is

I_CC(MIN)

low and the flyback voltage is also low, so C supplies

Make C large enough to avoid the relaxation oscillatory

TR

most of the LTC4268-1 current (only a fraction comes

behavior described above. This is complicated to deter-

mine theoretically as it depends on the particulars of the

secondary circuit and load behavior. Empirical testing is

recommended. Note that the use of the optional soft-start

function lengthens the power-up timing and requires a

from R .) V voltage continues to drop until after some

TR

CC

time, typically tens of milliseconds, the output voltage

approaches its desired value. The flyback winding then

provides the LTC4268-1 supply current and the V

CC

voltage stabilizes.

correspondingly larger value for C .

TR

V

IN

R

TR

•

V

IN

+

•

C

TR

I

VCC

•

V

CC

LTC4268-1 PG

GND

V

THRESHOLD

ON

V

I

VCC

0

V

PG

42681 F16

Figure 16. Typical Power Bootstrapping

42681fc

35

LTC4268-1

applicaTions inForMaTion

The LTC4268-1 has an internal clamp on V of approxi-

Slope Compensation

CC

mately 20V. This provides some protection for the part

TheLTC4268-1incorporatescurrentslopecompensation.

Slope compensation is required to ensure current loop

stabilitywhentheDCisgreaterthan50%.Insomeswitching

regulators,slopecompensationreducesthemaximumpeak

current at higher duty cycles. The LTC4268-1 eliminates

this problem by having circuitry that compensates for

the slope compensation so that maximum current sense

voltage is constant across all duty cycles.

in the event that the switcher is off (UVLO low) and the

V

node is pulled high. If R is sized correctly the part

TR

CC

should never attain this clamp voltage.

Control Loop Compensation

Loop frequency compensation is performed by connect-

ing a capacitor network from the output of the feedback

amplifier (V

pin) to ground as shown in Figure 17.

CMP

Becauseofthesamplingbehaviorofthefeedbackamplifier,

Minimum Load Considerations

compensation is different from traditional current mode

controllers. Normally only C

At light loads, the LTC4268-1 derived regulator goes into

forced continuous conduction mode. The primary side

switch always turns on for a short time as set by the

is required. R

can

VCMP

be used to add a “zero” but the phase margin improve-

ment traditionally offered by this extra resistor is usually

already accomplished by the nonzero secondary circuit

t

resistor. If this produces more power than the

ON(MIN)

loadrequires, powerwillflowbackintotheprimaryduring

the “off” period when the synchronization switch is on.

This does not produce any inherently adverse problems,

although light load efficiency is reduced.

impedance. C

can be used to add an additional high

VCMP2

frequency pole and is usually sized at 0.1 times C

.

VCMP

In further contrast to traditional current mode switchers,

pinrippleisgenerallynotanissuewiththeLTC4268-1.

V

CMP

Maximum Load Considerations

The dynamic nature of the clamped feedback amplifier

forms an effective track/hold type response, whereby the

The current mode control uses the V

node voltage and

CMP

V

voltage changesduring theflyback pulse, butis then

CMP

amplified sense resistor voltage as inputs to the current

comparator.Whentheamplifiedsensevoltageexceedsthe

“held” during the subsequent “switch on” portion of the

next cycle. This action naturally holds the V voltage

CMP

V

node voltage, the primary side switch is turned off.

CMP

stableduringthecurrentcomparatorsenseaction(current

mode switching).

In normal use, the peak switch current increases while

FB is below the internal reference. This continues until

Application Note 19 provides a method for empirically

tweaking frequency compensation. Basically it involves

introducing a load current step and monitoring the

response.

V

reaches its 2.56V clamp. At clamp, the primary side

CMP

MOSFET will turn off at the rated 100mV V

level. This

SENSE

repeatsonthenextcycle.Itispossibleforthepeakprimary

switch currents as referred across R

to exceed the

SENSE

V

CMP

17

R

VCMP

C

VCMP2

C

VCMP

42681 F17

Figure 17. V_CMPCompensation Network

42681fc

36

LTC4268-1

applicaTions inForMaTion

max 100mV rating because of the minimum switch on

Output Voltage Error Sources

time blanking. If the voltage on V

exceeds 205mV

SENSE

The LTC4268-1’s feedback sensing introduces additional

minor sources of errors. The following is a summary list.

after the minimum turn-on time, the SFST capacitor is

discharged, causing the discharge of the V capacitor.

CMP

• Theinternalbandgapvoltagereferencesetsthereference

voltage for the feedback amplifier. The specifications

detail its variation.

This then reduces the peak current on the next cycle and

will reduce overall stress in the primary switch.

Short-Circuit Conditions

• The external feedback resistive divider ratio directly

Loss of current limit is possible under certain conditions

such as an output short circuit. If the duty cycle exhibited

by the minimum on time is greater than the ratio of

secondary winding voltage (referred-to-primary) divided

by input voltage, then peak current is not controlled at

the nominal value. It ratchets up cycle-by-cycle to some

higher level. Expressed mathematically, the requirement

to maintain short-circuit control is

affects regulated voltage. Use 1% components.

• Leakage inductance on the transformer secondary

reduces the effective secondary-to-feedback winding

turns ratio (NS/NF) from its ideal value. This increases

the output voltage target by a similar percentage. Since

secondary leakage inductance is constant from part to

part (within a tolerance) adjust the feedback resistor

ratio to compensate.

I

• R

+ R

SEC DS(ON)

(

)

• The transformer secondary current flows through the

SC

DC

= t

• f

<

MIN

ON(MIN) OSC

impedances of the winding resistance, synchronous

V •N

IN

SP

MOSFET R

and output capacitor ESR. The DC

DS(ON)

equivalent current for these errors is higher than the

load current because conduction occurs only during

the converter’s “off” time. So divide the load current

by (1 – DC).

where:

t

I

is the primary side switch minimum on-time

ON(MIN)

is the short-circuit output current

SC

N

is the secondary-to-primary turns ratio (N /N

)

Iftheoutputloadcurrentisrelativelyconstant,thefeedback

resistive divider is used to compensate for these losses.

Otherwise,usetheLTC4268-1loadcompensationcircuitry.

(See Load Compensation.) If multiple output windings are

used, theflybackwindingwillhaveasignalthatrepresents

an amalgamation of all these windings impedances. Take

carethatyouexamineworst-caseloadingconditionswhen

tweaking the voltages.

SP

SEC PRI

(Other variables as previously defined)

Trouble is typically encountered only in applications with a

relatively high product of input voltage times secondary to

primaryturnsratioand/orarelativelylongminimumswitch

on time. Additionally, several real world effects such as

transformer leakage inductance, AC winding losses, and

output switch voltage drop combine to make this simple

theoretical calculation a conservative estimate. Prudent

design evaluates the switcher for short-circuit protection

and adds any additional circuitry to prevent destruction

for these losses.

42681fc

37

LTC4268-1

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Power MOSFET Selection

Choose the primary side MOSFET R

gate drive voltage (7.5V). The secondary side MOSFET

gate drive voltage depends on the gate drive method.

at the nominal

DS(ON)

ThepowerMOSFETsareselectedprimarilyonthecriteriaof

“on”resistanceR

,inputcapacitance,drain-to-source

DS(ON)

breakdown voltage (BV ), maximum gate voltage (V )

Primary side power MOSFET RMS current is given by:

DSS

GS

and maximum drain current (ID

).

(MAX)

P

IN

I_RMS(PRI)

=

For the primary-side power MOSFET, the peak current is:

V

DC_MAX

IN(MIN)

P

X



_MIN



IN

I_PK(PRI)

=

• 1+





For each secondary-side power MOSFET RMS current is

given by:



V

_IN(MIN)•DC_MAX

2

where X

is peak-to-peak current ratio as defined

I_OUT

MIN

I_RMS(SEC)

=

earlier. For each secondary-side power MOSFET, the peak

current is:

1−DC_MAX

Calculate MOSFET power dissipation next. Because the

I_OUT

1−DC_MAX

X



_MIN



I_PK(SEC)

=

• 1+





primary-side power MOSFET operates at high V , a

DS



2

transitionpowerlosstermisincludedforaccuracy.C

MILLER

is the most critical parameter in determining the transition

loss, but is not directly specified on the data sheets.

Selectaprimary-sidepowerMOSFETwithaBV

than:

greater

DSS

C

is calculated from the gate charge curve included

MILLER

V_OUT(MAX)

L_LKG

C_P

BV_DSS≥I_PK

+ V

+

on most MOSFET data sheets (Figure 17).

IN(MAX)

N_SP

The flat portion of the curve is the result of the Miller

(gate-to-drain) capacitance as the drain voltage drops.

The Miller capacitance is computed as:

where N reflects the turns ratio of that secondary-to

SP

primary winding. L

is the primary-side leakage induc-

LKG

tanceandC istheprimary-sidecapacitance(mostlyfrom

P

Q_B−Q_A

C_MILLER

=

the drain capacitance (C ) of the primary-side power

OSS

V_DS

MOSFET). A snubber may be added to reduce the leakage

inductance as discussed.

The curve is done for a given V . The Miller capacitance

for different V voltages are estimated by multiplying the

computed C

the curve specified V .

DS

Foreachsecondary-sidepowerMOSFET,theBV should

DSS

DS

be greater than:

by the ratio of the application V to

MILLER DS

DS

BV

≥ V

+ V

• N

DSS

OUT

IN(MAX) SP

MILLER EFFECT

V

GS

a

b

42681 F18

Q

A

Q

B

GATE CHARGE (Q )

G

Figure 18. Gate Charge Curve

42681fc

38

LTC4268-1

applicaTions inForMaTion

WithC

determined,calculatetheprimary-sidepower

ringing at the expense of slightly slower rise and fall times

and poorer efficiency.

MILLER

MOSFET power dissipation:

P_D(PRI)=I_RMS(PRI)²•R_DS(ON)1+ d +

TheLTC4268-1gatedriveswillclampthemaxgatevoltage

to roughly 7.5V, so you can safely use MOSFETs with

(

)

P

C_MILLER

^IN(MAX)•R_DR

DC_MIN

•

• f_OSC

maximum V of 10V and larger.

GS

V

•

IN(MAX)

V_GATE(MAX)− V_TH

Synchronous Gate Drive

where:

There are several different ways to drive the synchronous

gateMOSFET.Fullconverterisolationrequiresthesynchro-

nousgatedrivetobeisolated.Thisisusuallyaccomplished

by way of a pulse transformer. Usually the pulse driver is

used to drive a buffer on the secondary as shown in the

application on the front page of this data sheet.

R

is the gate driver resistance (≈10W)

is the MOSFET gate threshold voltage

is the operating frequency

DR

TH

V

f

OSC

V

= 7.5V for this part

GATE(MAX)

However,otherschemesarepossible.Therearegatedrivers

andsecondarysidesynchronouscontrollersavailablethat

provide the buffer function as well as additional features.

(1 + d) is generally given for a MOSFET in the form of a

normalizedR vstemperaturecurve.Ifyoudon’thave

a curve, use d = 0.005/°C • DT for low voltage MOSFETs.

DS(ON)

Capacitor Selection

The secondary-side power MOSFETs typically operate

In a flyback converter, the input and output current flows

in pulses, placing severe demands on the input and output

filter capacitors. The input and output filter capacitors are

selected based on RMS current ratings and ripple voltage.

at substantially lower V , so you can neglect transition

losses. The dissipation is calculated using:

DS

2

P

= I

• R (1 + d)

DS(ON)

DIS(SEC)

RMS(SEC)

With power dissipation known, the MOSFETs’ junction

temperatures are obtained from the equation:

Select an input capacitor with a ripple current rating

greater than:

T = T + P • θ

JA

J

A

DIS

P

1−DC_MAX

DC_MAX

IN

I_RMS(PRI)

=

whereT istheambienttemperatureandθ istheMOSFET

A

JA

V

IN(MIN)

junction to ambient thermal resistance.

Continuing the example:

29.5W 1− 49.4%

Once you have T iterate your calculations recomputing

d and power dissipations until convergence.

J

I_RMS(PRI)

=

= 0.728A

41V

49.4%

Gate Drive Node Consideration

The PG and SG gate drivers are strong drives to minimize

gate drive rise and fall times. This improves efficiency

but the high frequency components of these signals can

cause problems. Keep the traces short and wide to reduce

parasitic inductance.

Keep input capacitor series resistance (ESR) and

inductance (ESL) small, as they affect electromagnetic

interferencesuppression.Insomeinstances,highESRcan

alsoproducestabilityproblemsbecauseflybackconverters

exhibit a negative input resistance characteristic. Refer

to Application Note 19 for more information. The output

capacitorissizedtohandletheripplecurrentandtoensure

acceptable output voltage ripple.

The parasitic inductance creates an LC tank with the

MOSFET gate capacitance. In less than ideal layouts, a

series resistance of 5W or more may help to dampen the

42681fc

39

LTC4268-1

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The output capacitor should have an RMS current rating

greater than:

to the total ripple voltage, the ESR of the output capacitor

is determined by:

V_OUT• 1−DC

(

)

DC_MAX

1−DC_MAX

MAX

ESR_COUT≤1%•

I_RMS(SEC)=I_OUT

I_OUT

Continuing the example:

The other 1% is due to the bulk C component, so use:

49.4%

1− 49.4%

I_OUT

1%• V_OUT• f_OSC

I_RMS(SEC)= 5.3A

= 5.24A

C_OUT

≥

In many applications the output capacitor is created from

multiple capacitors to achieve desired voltage ripple,

reliability and cost goals. For example, a low ESR ceramic

capacitor can minimize the ESR step, while an electrolytic

capacitor satisfies the required bulk C.

This is calculated for each output in a multiple winding

application.

ESRandESLalongwithbulkcapacitancedirectlyaffectthe

output voltage ripple. The waveforms for a typical flyback

converter are illustrated in Figure 19.

Continuing our example, the output capacitor needs:

The maximum acceptable ripple voltage (expressed as a

percentage of the output voltage) is used to establish a

starting point for the capacitor values. For the purpose

of simplicity we will choose 2% for the maximum output

ripple, divided equally between the ESR step and the

charging/dischargingDV.Thispercentageripplechanges,

depending on the requirements of the application. You

can modify the equations below. For a 1% contribution

5V • 1− 49.4%

(

)

= 4mW

ESR_COUT≤1%•

5.3A

1%•5•200kHz

5.3A

= 600µF

C_OUT

≥

These electrical characteristics require paralleling several

low ESR capacitors possibly of mixed type.

I

PRI

PRIMARY

CURRENT

SECONDARY

CURRENT

I

PRI

N

RINGING

DUE TO ESL

∆V

COUT

OUTPUT VOLTAGE

RIPPLE WAVEFORM

∆V

ESR

42681 F19

Figure 19. Typical Flyback Converter Waveforms

42681fc

40

LTC4268-1

applicaTions inForMaTion

Most capacitor ripple current ratings are based on 2000

hour life. This makes it advisable to derate the capacitor

or to choose a capacitor rated at a higher temperature

than required.

there will be any user accessible connection to the PD,

then an isolated DC/DC converter is necessary to meet

the isolation requirements. If user connections can be

avoided, then it is possible to meet the safety requirement

by completely enclosing the PD in an insulated housing.

In all PD applications, there should be no user accessible

electricalconnectionstotheLTC4268-1orsupportcircuitry

other than the RJ-45 port.

Onewaytoreducecostandimproveoutputrippleistouse

a simple LC filter. Figure 20 shows an example of the filter.

The design of the filter is beyond the scope of this data

sheet. However, as a starting point, use these general

guidelines. Start with a C

1/4 the size of the nonfilter

OUT

pole independent of C . C1 may be best implemented

OUT

LAYOUT CONSIDERATIONS FOR THE LTC4268-1

solution. Make C1 1/4 of C

to make the second filter

The LTC4268-1’s PD front end is relatively immune to

layoutproblems.PlaceC14(Figure9)ascloseasphysically

possible to the LTC4268-1. Place the series 10Ω resistor

OUT

with multiple ceramic capacitors. Make L1 smaller than

the output inductance of the transformer. In general, a

0.1µH filter inductor is sufficient. Add a small ceramic

closetoC14.ExcessiveparasiticcapacitanceontheR

CLASS

pin should be avoided. Include a PCB heat sink to which

the exposed pad on the bottom of the package can be

soldered. This heat sink should be electrically connected

to GND. For optimum thermal performance, make the

heat sink as large as possible. Voltages in a PD can be

as large as –57V for PoE applications, so high voltage

layout techniques should be employed. The SHDN pin

should be separated from other high voltage pins, like

capacitor (C

) for high frequency noise on V . For

OUT2

OUT

those interested in more details refer to “Second-Stage

LC Filter Design,” Ridley, Switching Power Magazine, July

2000 p8-10.

Circuit simulation is a way to optimize output capacitance

and filters, just make sure to include the component

parasitic. LTC SwitcherCAD^®is a terrific free circuit

simulation tool that is available at www.linear.com. Final

optimization of output ripple must be done on a dedicated

PC board. Parasitic inductance due to poor layout can

significantly impact ripple. Refer to the PC Board Layout

section for more details.

V

, V , to avoid the possibility of leakage shutting

PORTP OUT

down the LTC4268-1. If not used, tie SHDN to V

.

PORTN

The load capacitor connected between V

and V

PORTP

OUT

of the LTC4268-1 can store significant energy when fully

charged. The design of a PD must ensure that this energy

is not inadvertently dissipated in the LTC4268-1. The

polarity-protection diodes prevent an accidental short

ISOLATION

on the cable from causing damage. However if, V

The802.3standardrequiresEthernetportstobeelectrically

isolatedfromallotherconductorsthatareuseraccessible.

This includes the metal chassis, other connectors and

any auxiliary power connection. For PDs, there are two

common methods to meet the isolation requirement. If

PORTN

is shorted to V

inside the PD while capacitor C1

PORTP

is charged, current will flow through the parasitic body

diode of the internal MOSFET and may cause permanent

damage to the LTC4268-1.

L1

0.1µH

V

OUT

FROM

+

C1

C

OUT2

1µF

OUT

R

LOAD

SECONDARY

WINDING

47µF

470µF

×3

42681 F20

Figure 20. LC Filter

42681fc

41

LTC4268-1

applicaTions inForMaTion

In order to minimize switching noise and improve output

the MOSFET node voltages with an oscilloscope. If it is

breaking down either choose a higher voltage device, add

a snubber or specify an avalanche-rated MOSFET.

load regulation, connect the GND pin of the LTC4268-1

directly to the ground terminal of the V decoupling

CC

capacitor,thebottomterminalofthecurrentsenseresistor

Place the small-signal components away from high

frequencyswitchingnodes.Thisallowstheuseofapseudo-

Kelvin connection for the signal ground, where high di/

dt gate driver currents flow out of the IC ground pin in

and the ground terminal of the input capacitor, using a

ground plane with multiple vias. Place the V capacitor

CC

immediately adjacent to the V and GND pins on the IC

CC

package. This capacitor carries high di/dt MOSFET gate

drivecurrents. UsealowESRceramiccapacitor. Takecare

inPCBlayouttokeepthetracesthatconducthighswitching

currents short, wide and with minimal overall loop area.

Thesearetypicallythetracesassociatedwiththeswitches.

This reduces the parasitic inductance and also minimizes

magneticfieldradiation.Figure21outlinesthecriticalpaths.

Keep electric field radiation low by minimizing the length

andareaoftraces(keepstraycapacitanceslow). Thedrain

of the primary side MOSFET is the worst offender in this

category. Always use a ground plane under the switcher

circuitry to prevent coupling between PCB planes. Check

one direction (to the bottom plate of the V decoupling

CC

capacitor) and small-signal currents flow in the other

direction. Keep the trace from the feedback divider tap

to the FB pin short to preclude inadvertent pickup. For

applications with multiple switching power converters

connected to the same input supply, make sure that the

input filter capacitor for the LTC4268-1 is not shared with

other converters. AC input current from another converter

could cause substantial input voltage ripple and this could

interferewiththeLTC4268-1operation.AfewinchesofPC

traceorwire(L@100nH)betweentheC oftheLTC4268-1

IN

and the actual source V is sufficient to prevent current

IN

that the maximum BV

ratings of the MOSFETs are not

DSS

sharing problems.

exceeded due to inductive ringing. This is done by viewing

T1

•

V

CC

V

IN

C

VCC

•

GATE

TURN-ON

V

•

CC

+

PG

C

MP

VIN

GATE

TURN-OFF

OUT

R

SENSE

+

V

C

CC

OUT

+

GATE

C

R

TURN-ON

Q4

Q3

V

CC

T2

SG

MS

•

GATE

TURN-OFF

42681 F21

Figure 21. Layout Critical High Current Paths

42681fc

42

LTC4268-1

Typical applicaTion

42681fc

43

LTC4268-1

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

DKD Package

32-Lead Plastic DFN (7mm × 4mm)

(Reference LTC DWG # 05-08-1734 Rev A)

0.70 0.05

4.50 0.05

6.43 0.05

2.65 0.05

3.10 0.05

PACKAGE

OUTLINE

0.20 0.05

0.40 BSC

6.00 REF

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

R = 0.115

TYP

7.00 0.10

17

32

R = 0.05

TYP

0.40 0.10

6.43 0.10

2.65 0.10

4.00 0.10

PIN 1 NOTCH

R = 0.30 TYP OR

0.35 × 45° CHAMFER

PIN 1

TOP MARK

(SEE NOTE 6)

16

1

0.20 0.05

0.40 BSC

6.00 REF

BOTTOM VIEW—EXPOSED PAD

0.75 0.05

(DKD32) QFN 0707 REV A

0.200 REF

NOTE:

0.00 – 0.05

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)

IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

42681fc

44

LTC4268-1

revision hisTory ^{(Revision history begins at Rev C)}

REV

DATE

DESCRIPTION

PAGE NUMBER

C

08/12 Simplified Overview section, including removal of Figure 1A and 1B which caused renumbering of all figures in

data sheet

13, 14

Changed maximum power levels for class 0 and class 3 to 13.0W

15

20, 43

21

Added 10Ω resistor to V

pin on schematic to make solution more robust to current surges

PORTP

Added Input Capacitor, Input Series Resistance and Transient Voltage Supressor sections

Added C14 and 10Ω resistor layout recommendation

41

42681fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

45

LTC4268-1

relaTeD parTs

PART NUMBER DESCRIPTION

COMMENTS

LTC4257-1

LTC4258

IEEE 802.3af PD Interface Controller

100V 400mA Internal Switch, Programmable Classification Dual

Current Limit

Quad IEEE 802.3af Power over Ethernet Controller

Single IEEE 802.3af Power over Ethernet Controller

High Power Single PSE Controller

DC Disconnect Only, IEEE-Compliant PD Detection and Classification,

2

Autonomous Operation or I C Control

LTC4259A-1

LTC4263

AC or DC Disconnect IEEE-Compliant PD Detection and Classification,

2

Autonomous Operation or I C Control

AC or DC Disconnect IEEE-Compliant PD Detection and Classification,

2

Autonomous Operation or I C Control

LTC4263-1

LTC4264

Internal Switch, Autonomous Operation, 30W

High Power PD Interface Controller With 750mA

Current Limit

750mA Internal Switch, Programmable Classification Current to 75mA.

Precision Dual Current Limit With Disable.

LTC4266

Quad IEEE 802.3at PoE PSE Controller

With Programmable I /I , 2-Event Classification, and Port Current and

CUT LIM

Voltage Monitoring

LTC4266A

Quad LTPoE++ PSE Controller

Provides Up to 90W. Backwards Compatible with IEEE 802.3af and IEEE

802.3at PDs. With Programmable I /I , 2-Event Classification, and Port

CUT LIM

Current and Voltage Monitoring

LTC4266C

LTC4267

Quad IEEE 802.3af PSE Controller

With Programmable I /I , 1-Event Classification, and Port Current and

CUT LIM

Voltage Monitoring

IEEE 802.3af PD Interface With an Integrated

Switching Regulator

100V 400mA Internal Switch, Programmable Classification, 200kHz Constant-

Frequency PWM, Interface and Switcher Optimized for IEEE-Compliant

PD System

LTC4267-1

LTC4267-3

IEEE 802.3af PD Interface with Integrated Switching Internal 100V, 400mA Switch, Programmable Class, 200kHz Constant-

Regulator

Frequency PWM

IEEE 802.3af PD Interface With an Integrated

Switching Regulator

100V 400mA Internal Switch, Programmable Classification, 300kHz Constant-

Frequency PWM, Interface and Switcher Optimized for IEEE-Compliant

PD System

LTC4269-1

LTC4269-2

IEEE 802.3af PD Interface with Integrated Flyback

Switching Regulator

2-Event Classification, Programmable Classification, Synchronous No-Opto

Flyback Controller, 50kHz to 250kHz, Aux Support

IEEE 802.3af PD Interface with Integrated Forward

Switching Regulator

2-Event Classification, Programmable Classification, Synchronous Forward

Controller, 100kHz to 500kHz, Aux Support

LTC4270/

LTC4271

12-Port PoE/PoE+/LTPoE++™ PSE Controller

Single IEEE 802.3at PoE PSE Controller

Single LTPoE++ PSE Controller

Transformer Isolation, Supports Type 1,Type 2 and LTPoE++ PDs

LTC4274

With Programmable I /I , 2-Event Classification, and Port Current and

CUT LIM

Voltage Monitoring

LTC4274A

Provides Up to 90W. Backwards Compatible with IEEE 802.3af and IEEE

802.3at PDs. With Programmable I /I , 2-Event Classification, and Port

CUT LIM

Current and Voltage Monitoring

LTC4274C

LTC4278

Single IEEE 802.3af PSE Controller

With Programmable I /I , 1-Event Classification, and Port Current and

CUT LIM

Voltage Monitoring

IEEE 802.3af PD Interface with Integrated Flyback

Switching Regulator

2-Event Classification, Programmable Classification, Synchronous No-Opto

Flyback Controller, 50kHz to 250kHz, 12V Auxiliary Support

42681fc

LT 0812 REV C • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

46

l

ꢀLINEAR TECHNOLOGY CORPORATION 2007

(408)432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC4268-1_12
厂家：	Linear
描述：	High Power PD With Synchronous No-Opto Flyback Controller 高功率PD具有同步无光电反激式控制器光电光电二极管控制器
文件：	总46页 (文件大小：424K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC4268-1_12 [Linear]

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