LTC4269CDKD-2-TR [Linear]
IEEE 802.3at High Power PD and Synchronous Forward Controller with AUX Support; 符合IEEE 802.3at高功率PD和同步正向控制器,支持AUX型号: | LTC4269CDKD-2-TR |
厂家: | Linear |
描述: | IEEE 802.3at High Power PD and Synchronous Forward Controller with AUX Support |
文件: | 总34页 (文件大小:383K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC4269-2
IEEE 802.3at High Power PD
and Synchronous Forward
Controller with AUX Support
DescripTion
FeaTures
The LTC®4269-2 is an integrated Powered Device (PD)
interfaceandpowersupplycontrollerfeaturing2-event
classification signaling, flexible auxiliary power op-
tions, and a power supply controller suitable for syn-
chronously rectified forward supplies. These features
make the LTC4269-2 ideally suited for an IEEE802.3at
PD application.
n
25.5W IEEE 802.3at Compliant (Type-2) PD
+
n
PoE 2-Event Classification
n
IEEE 802.3at High Power Available Indicator
n
Integrated State-of-the-Art Synchronous Forward
Controller
– Isolated Power Supply Efficiency >94%
n
Flexible Auxiliary Power Interface
Superior EMI Performance
n
n
The PD controller features a 100V MOSFET that isolates
the power supply during detection and classification, and
provides 100mA inrush current limit. Also included are
power good outputs, an undervoltage/overvoltage lock-
out and thermal protection. The current mode forward
controller allows for synchronous rectification, resulting
in an extremely high efficiency, green product. Soft-start
for controlled output voltage start-up and fault recovery is
included.Programmablefrequencyover100kHzto500kHz
allows flexibility in efficiency vs size and low EMI.
Robust 100V 0.7Ω (Typ) Integrated Hot Swap™
MOSFET
n
Integrated Signature Resistor, Programmable Class
Current, UVLO, OVLO and Thermal Protection
n
Short-Circuit Protection with Auto-Restart
n
Programmable Switching Frequency from
100kHz to 500kHz
n
Thermally Enhanced 7mm × 4mm DFN Package
applicaTions
n
IP Phones with Large Color Screens
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Hot Swap, ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
n
Dual Radio 802.11n Access Points
n
PTZ Security Cameras
Typical applicaTion
PoE-Based Self-Driven Synchronous Forward Power Supply
1mH
•
6.8µH
5V
5A
•
+
10µH
10µF
5.1Ω
220µF
•
+
33k
4.7nF
2.2µF
237k
0.1µF
V
CC
+
10.0k
10µF
~ +
~ –
54V FROM
DATA PAIR
10k
133Ω
4.7nF
SD_V
SEC
PORTP
V
S
OUT
PWRGD
IN
OUT
V
CC
2k
~ +
~ –
V
OC
54V FROM
SPARE PAIR
11.3k
1.5k
33k
50mΩ
0.1µF
I
SENSE
10nF
22k
LTC4269-2
R
CLASS
COMP
FB
0.1µF
30.9Ω
SHDN
V
1.2k
V
REF
PORTN
T2P V
NEG
PGND GND BLANK DELAY
R
SS_MAXDC
22.1k
OSC
TLV431
3.65k
0.22µF
82k
332k 158k
158k
TO
42692 TA01
MICRO-
CONTROLLER
42692fb
ꢀ
LTC4269-2
absoluTe MaxiMuM raTings
pin conFiguraTion
(Notes 1, 2)
TOP VIEW
Pins with Respect to V
PORTN
V
V
V
Voltage ........................................ –0.3V to 100V
PORTP
SHDN 1
T2P 2
32 V
PORTP
31 NC
30 NC
29 PWRGD
28 PWRGD
Voltage.........................................–0.3V to V
Pull-Up Current..................................................1A
NEG
NEG
PORTP
R
V
3
NC 4
5
CLASS
SHDN....................................................... –0.3V to 100V
PORTN
V
6
27 V
26 V
PORTN
NEG
NEG
R
R
, Voltage ........................................... –0.3V to 7V
Source Current ..........................................50mA
CLASS
CLASS
NC 7
NC 8
COMP 9
FB 10
25 NC
24 SOUT
33
PWRGD Voltage (Note 3)
23 V
IN
R
11
22 OUT
21 PGND
20 DELAY
19 OC
OSC
Low Impedance Source .... V
– 0.3V to V
+ 11V
NEG
NEG
SYNC 12
Sink Current.........................................................5mA
PWRGD, T2P Voltage ............................... –0.3V to 100V
PWRGD, T2P Sink Current .....................................10mA
SS_MAXDC 13
V
14
15
REF
SD_V
18 I
SEC
SENSE
GND 16
17 BLANK
Pins with Respect to GND
IN
SYNC, SS_MAXDC, SD_V
DKD PACKAGE
32-LEAD (7mm s 4mm) PLASTIC DFN
V (Note 4)................................................ –0.3V to 25V
T
= 125°C, θ = 34°C/W, θ = 2°C/W
JA JC
EXPOSED PAD (PIN 33) MUST BE SOLDERED TO
HEAT SINKING PLANE THAT IS CONNECTED TO GND
JMAX
,
SEC
I
, OC.................................................... –0.3V to 6V
SENSE
COMP, BLANK, DELAY.............................. –0.3V to 3.5V
FB ................................................................ –0.3V to 3V
R
Current........................................................ –50µA
Source Current ..............................................10mA
OSC
REF
V
Operating Ambient Temperature Range
LTC4269C-2............................................. 0°C to 70°C
LTC4269I-2..........................................–40°C to 85°C
orDer inForMaTion
LEAD FREE FINISH
LTC4269CDKD-2#PBF
LTC4269IDKD-2#PBF
LEAD BASED FINISH
LTC4269CDKD-2
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4269CDKD-2#TRPBF 42692
0°C to 70°C
32-Lead (7mm × 4mm) Plastic DFN
32-Lead (7mm × 4mm) Plastic DFN
PACKAGE DESCRIPTION
LTC4269IDKD-2#TRPBF
TAPE AND REEL
42692
–40°C to 85°C
TEMPERATURE RANGE
0°C to 70°C
PART MARKING*
42692
LTC4269CDKD-2#TR
LTC4269IDKD-2#TR
32-Lead (7mm × 4mm) Plastic DFN
32-Lead (7mm × 4mm) Plastic DFN
LTC4269IDKD-2
42692
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
42692fb
ꢁ
LTC4269-2
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Interface Controller (Note 5)
Operating Input Voltage
Signature Range
At V
(Note 6)
60
V
V
V
V
V
V
PORTP
l
l
l
l
1.5
9.8
Classification Range
On Voltage
12.5
21.0
37.2
Undervoltage Lockout
Overvoltage Lockout
30.0
71.0
l
l
l
ON/UVLO Hysteresis Window
Signature/Class Hysteresis Window
Reset Threshold
4.1
1.4
V
V
V
State Machine Reset for 2-Event Classification
2.57
5.40
Supply Current
l
l
Supply Current at 57V
Class O Current
Measured at V
Pin
1.35
0.40
mA
mA
PORTP
V
= 17.5V, No R
Resistor
PORTP
CLASS
Signature
l
l
l
Signature Resistance
1.5V ≤ V
1.5V ≤ V
≤ 9.8V (Note 7)
23.25
26.00
11
kΩ
kΩ
kΩ
PORTP
PORTP
Invalid Signature Resistance, SHDN Invoked
Invalid Signature Resistance During Mark Event
Classification
≤ 9.8V, V
= 3V (Note 7)
SHDN
(Notes 7, 8)
11
l
l
Class Accuracy
10mA < I
< 40mA, 12.5V < V
< 21V
3.5
1
%
CLASS
PORTP
(Notes 9, 10)
Classification Stability Time
V
Pin Step to 17.5V, R
within 3.5% of Ideal Value (Notes 9, 10)
= 30.9Ω,
ms
PORTP
CLASS
CLASS
I
Normal Operation
Inrush Current
l
l
l
V
= 54V, V
= 3V
NEG
60
100
0.7
180
1.0
1
mA
Ω
PORTP
Power FET On-Resistance
Tested at 600mA into V , V
= 54V
NEG PORTP
Power FET Leakage Current at V
Digital Interface
V
= SHDN = V = 57V
NEG
µA
NEG
PORTP
l
l
l
l
SHDN Input High Level Voltage
SHDN Input Low Level Voltage
SHDN Input Resistance
3
V
V
0.45
0.15
V
= 9.8V, SHDN = 9.65V
= 57V, For T2P, Must
100
kΩ
V
PORTP
PWRGD, T2P Output Low Voltage
Tested at 1mA, V
Complete 2-Event Classification to See Active Low
PORTP
l
l
PWRGD, T2P Leakage Current
Pin Voltage Pulled 57V, V = V = 0V
1
µA
V
PORTP
PORTN
PWRGDP Output Low Voltage
Tested at 0.5mA, V
= 52V, V
= 4V, Output
0.4
PORTP
NEG
Voltage is with Respect to V
NEG
l
l
PWRGDP Clamp Voltage
PWRGDP Leakage Current
Tested at 2mA, V
= 0V, Voltage is with Respect
= 0V, Voltage is with Respect
12.0
16.5
1
V
NEG
NEG
to V
NEG
V
= 11V, V
µA
PWRGD
NEG
to V
PWM Controller (Note 11)
l
Operational Input Voltage
I
I
= 0µA
V
25
6.5
V
mA
VREF
IN(OFF)
V
V
V
Quiescent Current
Start-Up Current
Shutdown Current
= 0µA, I
= OC = Open
SENSE
5.2
460
240
1.32
IN
IN
IN
VREF
l
l
FB = 0V, SS_MAXDC = 0V (Notes 12, 13)
SD_V = 0V (Notes 12, 13)
700
350
1.379
µA
µA
SEC
SD_V
Threshold
10V < SD < 25V
1.261
V
SEC
42692fb
ꢂ
LTC4269-2
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
0
MAX
UNITS
SD_V
SD_V
Current
Current
SD_V
SD_V
= SD_V
= SD_V
Threshold +100mV
Threshold – 100mV
µA
µA
V
SEC(ON)
SEC(OFF)
SEC
SEC
SEC
8.3
10
11.7
15.75
9.25
7.0
SEC
l
l
l
V
V
V
V
14.25
8.75
5.5
IN(ON)
V
IN(OFF)
IN(HYST)
REF
3.75
V
l
Output Voltage
Line Regulation
Load Regulation
Oscillator
I
I
= 0
2.425
2.5
1
2.575
10
V
mV
mV
VREF
= 0, 10V < V < 25V
VREF
IN
0mA < I
< 2.5mA
1
10
VREF
l
Frequency, f
R
R
R
= 178k, FB = 1V, SS_MAXDC = 1.84V
= 365k, FB = 1V
165
80
200
100
500
18
240
120
560
kHz
kHz
kHz
kΩ
V
OSC
OSC
OSC
OSC
f
f
OSC(MIN)
OSC(MAX)
= 64.9k, COMP = 2.5V, SD_V
= 2.64V
440
SEC
SYNC Input Resistance
SYNC Switching Threshold
FB = 1V
1.5
1.25
0.05
1
2.2
1.5
SYNC Frequency/f
FB = 1V (Note 14)
OSC
f
Line Regulation
R
OSC
R
OSC
= 178k; 10V < V < 25V, SS_MAXDC = 1.84V
0.33
%/V
V
OSC
IN
V
ROSC
Pin Voltage
Error Amplifier
l
FB Reference Voltage
FB Input Bias Current
Open-Loop Voltage Gain
Unity-Gain Bandwidth
COMP Source Current
COMP Sink Current
10V < V < 25V, V + 0.2V < COMP < V – 0.2
1.201
65
1.226
-75
85
1.250
-200
V
nA
dB
MHz
mA
mA
µA
V
IN
OL
OH
FB = FB Reference Voltage
+ 0.2V < COMP < V – 0.2
V
OL
OH
(Note 15)
3
FB = 1V, COMP = 1.6V
COMP = 1.6V
–4
4
–9
10
COMP Current (Disabled)
FB = V , COMP = 1.6V
18
2.7
0.7
23
28
REF
COMP High Level V
FB = 1V, I
= –250µA
3.2
0.8
0.15
OH
COMP
COMP Active Threshold
FB = 1V, SOUT Duty Cycle > 0%
= 250µA
V
COMP Low Level V
I
0.4
V
OL
COMP
Current Sense
I
I
I
Maximum Threshold
COMP = 2.5V, FB =1V
197
98
220
–8
243
mV
µA
µA
mV
nA
ns
ns
V
SENSE
SENSE
SENSE
Input Current (Duty Cycle = 0%)
Input Current (Duty Cycle = 80%)
COMP = 2.5V, FB = 1V (Note 12)
COMP = 2.5V, FB = 1V (Note 12)
COMP = 2.5V, FB = 1V
–35
107
–50
180
540
1
OC Threshold
116
OC Input Current
(OC = 100mV)
–100
Default Blanking Time
Adjustable Blanking Time
COMP = 2.5V, FB = 1V, R
COMP = 2.5V, FB = 1V, R
= 40k (Note 16)
= 120k
BLANK
BLANK
V
BLANK
SOUT Driver
SOUT Clamp Voltage
SOUT Low Level
I
I
= 0µA, COMP = 2.5V, FB = 1V
10.54
12
13.5
0.75
V
V
GATE
= 25mA
0.5
GATE
42692fb
ꢃ
LTC4269-2
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
I = –25mA, V = 12V COMP = 2.5V, FB = 1V
GATE
MIN
10
1
TYP
MAX
UNITS
V
SOUT High Level
IN
SOUT Active Pull-Off in Shutdown
V
= 5V, SD_V = 0V, SOUT = 1V
mA
IN
SEC
SOUT to OUT (Rise) DELAY (t
)
COMP = 2.5V, FB = 1V (Note 16)
= 120k
40
120
ns
ns
DELAY
R
DELAY
V
DELAY
0.9
V
OUT Driver
OUT Rise Time
OUT Fall Time
OUT Clamp Voltage
OUT Low Level
FB = 1V, C = 1nF (Notes 15, 16)
50
30
13
ns
ns
V
L
FB = 1V, C = 1nF (Notes 15, 16)
L
I
= 0µA, COMP = 2.5V, FB = 1V
11.5
14.5
GATE
I
I
= 20mA
= 200mA
0.45
1.25
0.75
1.8
V
V
GATE
GATE
OUT High Level
I
I
= –20mA, V = 12V COMP = 2.5V, FB = 1V
9.9
9.75
V
V
GATE
GATE
IN
= –200mA, V = 12V COMP = 2.5V, FB = 1V
IN
OUT Active Pull-Off in Shutdown
OUT Max Duty Cycle
V
= 5V, SD_V
= 0V, OUT = 1V
20
83
mA
%
IN
SEC
COMP = 2.5V, FB = 1V, R
V
= 10k (f
= 200kHz),
90
DELAY
OSC
= 10V, SD_V
= 1.4V, SS_MAXDC = V
IN
SEC REF
OUT Max Duty Cycle Clamp
COMP = 2.5V, FB = 1V, R
= 10k (f
= 200kHz),
DELAY
OSC
V
= 10V
IN
SD_V
= 1.32V, SS_MAXDC = 1.84V
= 2.64V, SS_MAXDC = 1.84V
63.5
25
72
33
80.5
41
%
%
SEC
SEC
SD_V
Soft-Start
SS_MAXDC Low Level: V
I
= 150µA, OC = 1V
0.2
0.45
0.8
V
V
OL
SS_MAXDC
SS_MAXDC Soft-Start Reset Threshold
SS_MAXDC Active Threshold
SS_MAXDC Input Current
Measured on SS_MAXDC
FB + 1V, DC > 0%
V
SS_MAXDC = 1V, SD_V
= 1.4V, OC = 1V
800
µA
SEC
(Soft-Start Pull-Down: I
)
DIS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 8: An invalid signature after the 1st classification event is mandated
by IEEE 802.3at standard. See the Applications Information section.
Note 9: Class accuracy is respect to the ideal current defined as
1.237/R
and does not include variations in R
resistance.
CLASS
CLASS
Note 2: Pins with 100V absolute maximum guaranteed for T ≥ 0°C,
otherwise 90V.
Note 10: This parameter is assured by design and wafer level testing.
Note 11: Voltages are with respect to GND unless otherwise specified.
Note 3: PWRGD voltage clamps at 14V with respect to V
.
NEG
Tested with COMP open, V = 1.4V, R
= 178k, V
= 0.1µF, V
= 0V, V
FB
ROSC
SYNC
= 2V, R
SD_VSEC BLANK
SS(MAXDC)
Note 4: In applications where the V pin is supplied via an external RC
set to V (but electrically isolated), C
IN
REF
VREF
network from a system V > 25V, an external Zener with clamp voltage
= 121k, R
= 121k, V
= 0V, V = 0V, C
= 1nF, V = 15V,
OUT IN
IN
DELAY
ISENSE
OC
V
< V < 25V should be connected from the V pin to GND.
SOUT open, unless otherwise specified.
IN ON(MAX)
Z
IN
Note 5: All voltages are with respect to V
pin unless otherwise noted.
Note 12: Guaranteed by correlation to static test.
PORTN
Note 6: Input voltage specifications are defined with respect to LTC4269-2
pins and meet IEEE 802.3af/at specifications when the input diode bridge
is included.
Note 7: Signature resistance is measured via the ∆V/∆I method with the
minimum ∆V of 1V. The LTC4269-2 signature resistance accounts for the
additional series resistance in the input diode bridge.
Note 13: V start-up current is measured at V = V
– 0.25V and
IN(ON)
IN
IN
scaled by × 1.18 (to correlate to worst-case V start-up current at V
.
IN
IN(ON)
Note 14: Maximum recommended SYNC frequency = 500kHz.
Note 15: Guaranteed but not tested.
Note 16: Timing for R = 40k derived from measurement with R = 240k.
42692fb
ꢄ
LTC4269-2
Typical perForMance characTerisTics
Input Current vs Input Voltage
25k Detection Range
Input Current vs Input Voltage
Input Current vs Input Voltage
50
40
30
20
0.5
0.4
0.3
0.2
11.0
10.5
T
= 25°C
T
= 25°C
A
CLASS 1 OPERATION
A
CLASS 4
CLASS 3
CLASS 2
CLASS 1
CLASS 0
85°C
–40°C
10.0
9.5
10
0
0.1
0
0
20
30
40
50
60
0
4
6
8
10
10
V
2
12
14
16
18
20
22
VOLTAGE RISING (V)
V
VOLTAGE (V)
V
VOLTAGE (V)
PORTP
PORTP
PORTP
42692 G01
42692 G03
42692 G02
Signature Resistance
vs Input Voltage
Class Operation vs Time
On-Resistance vs Temperature
1.2
1.0
0.8
0.6
0.4
0.2
28
27
$V V2 – V1
RESISTANCE =
DIODES: HD01
=
V
T
= 25°C
PORTP
A
$I
I – I
2 1
INPUT
VOLTAGE
10V/DIV
T
= 25°C
A
IEEE UPPER LIMIT
26
LTC4269-2 + 2 DIODES
25
24
CLASS
CURRENT
10mA/DIV
LTC4269-2 ONLY
IEEE LOWER LIMIT
23
22
42692 G05
–50
0
25
50
75
100
TIME (10µs/DIV)
–25
V1:
V2:
1
2
3
4
5
6
7
8
9
10
JUNCTION TEMPERATURE (°C)
V
VOLTAGE (V)
PORTP
42692 G06
42692 G04
PWRGD, T2P Output Low Voltage
vs Current
Active High PWRGD Output Low
Voltage vs Current
FB Voltage vs Temperature
1.0
0.8
0.6
0.4
0.2
0
1.25
1.24
1.23
1.22
1.21
1.20
0.8
T
= 25°C
T = 25°C
A
PORTP
A
V
– V
= 4V
NEG
0.6
0.4
0.2
0
0
0.5
1
1.5
2
–50
0
25
50
75 100 125
–25
0
2
4
6
8
10
CURRENT (mA)
TEMPERATURE (°C)
CURRENT (mA)
42692 G08
42692 G09
42692 G07
42692fb
ꢅ
LTC4269-2
Typical perForMance characTerisTics
Switching Frequency
vs Temperature
VIN Shutdown Current
vs Temperature
VIN Start-Up Current
vs Temperature
245
230
215
200
185
170
155
500
450
400
350
300
250
200
150
100
600
550
500
450
400
350
300
250
200
V
= 15V
SEC
SD_V
= 1.4V
IN
SEC
SD_V
= 0V
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–25
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
42692 G10
42692 G11
42692 G12
SD_VSEC Turn On Threshold
vs Temperature
SD_VSEC Pin Current
vs Temperature
IQ (VIN) vs Temperature
6.5
6.0
5.5
5.0
4.5
4.0
3.5
1.42
1.37
1.32
1.27
1.22
15
10
5
OC = OPEN
PIN CURRENT BEFORE
PART TURN ON
0mA PIN CURRENT AFTER
PART TURN ON
0
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
42692 G13
42692 G14
42692 G15
V
IN Turn On/Off Voltage
COMP Active Threshold
vs Temperature
COMP Source Current
vs Temperature
vs Temperature
18
16
14
12
10
8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
12.5
10.0
7.5
R
= 0k
FB = 1V
ISENSE
COMP = 1.6V
V
TURN ON VOLTAGE
TURN OFF VOLTAGE
IN
V
IN
CURRENT OUT OF PIN
6
5.0
–50
0
25
50
75 100 125
50
50
–25
–50
0
25
75 100 125
–50
0
25
75 100 125
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
42692 G16
42692 G17
42692 G18
42692fb
ꢆ
LTC4269-2
Typical perForMance characTerisTics
COMP Sink Current
vs Temperature
(Disabled) COMP Pin Current
vs Temperature
ISENSE Maximum Threshold
vs COMP
50
40
30
20
10
0
240
200
160
120
80
12.5
10.0
7.5
FB = V
REF
COMP = 1.6V
T = 25°C
A
FB = 1.4V
COMP = 1.6V
R
= 0k
ISENSE
OC THRESHOLD
40
0
5.0
–50
0
25
50
75 100 125
0
1.0
1.5
2.0
2.5
3.0
–25
0.5
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
COMP (V)
TEMPERATURE (°C)
42692 G20
42692 G21
42692 G19
I
SENSE Maximum Threshold
vs Duty Cycle (Programming
Slope Compensation)
ISENSE Maximum Threshold
vs Temperature
ISENSE Pin Current (Out of Pin)
vs Duty Cycle
240
230
220
210
200
40
30
20
10
0
225
215
205
195
185
175
COMP = 2.5V
ISENSE
T = 25°C
A
R
= 0k
R
= 0Ω
SLOPE
R
= 470Ω
SLOPE
R
= 1k
SLOPE
T
= 25°C
A
COMP = 2.5V
–50
0
25
50
75 100 125
0
20 30 40 50 60 70 80 90 100
10
–25
0
20 30 40 50 60 70
DUTY CYCLE (%)
100
10
80 90
TEMPERATURE (°C)
DUTY CYCLE (%)
42692 G22
42692 G23
42692 G24
OC (Overcurrent) Threshold
vs Temperature
BLANK Duration vs RBLANK
Blank Duration vs Temperature
120
110
100
90
1000
800
600
400
200
0
800
600
400
200
0
PRECISION OVERCURRENT THRESHOLD
INDEPENDENT OF DUTY CYCLE
T = 25°C
A
R
= 120k
BLANK
R
= 40k
50
BLANK
25
80
–50
0
25
50
75 100 125
0
40 60 80 100 120 140 160
(k)
–25
–50
0
75
125
20
–25
100
TEMPERATURE (°C)
R
TEMPERATURE (°C)
BLANK
42692 G25
42692 G27
42692 G26
42692fb
ꢇ
LTC4269-2
Typical perForMance characTerisTics
tDELAY: SOUT Rise to OUT Rise
vs Temperature
tDELAY: SOUT Rise to OUT Rise
vs RDELAY
OUT Rise/Fall Time vs OUT Load
Capacitance
240
160
80
200
150
100
50
125
100
75
50
25
0
T
= 25°C
T
= 25°C
A
A
t
R
DELAY
= 120k
r
t
f
R
= 40k
50
DELAY
25
0
0
0
80
120
160
(k)
200
240
–50
0
75 100 125
40
0
1000
2000
3000
4000
5000
–25
R
TEMPERATURE (°C)
OUT LOAD CAPACITANCE (pF)
DELAY
42692 G29
42692 G28
42692 G30
OUT: Max Duty Cycle CLAMP
vs SD_VSEC
OUT: Max Duty Cycle CLAMP
vs SS_MAXDC
OUT: Max Duty Cycle vs fOSC
100
90
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
10
0
T
OSC
R
= 25°C
A
f
= 200kHz
= 10k
DELAY
SD_V
= 1.32V
SEC
SD_V
SD_V
= 1.98V
= 2.64V
SEC
80
T
= 25°C
A
T
= 25°C
SEC
SS_MAXDC = 1.84V
A
SS_MAXDC = 2.5V
f
= 200kHz
= 10k
OSC
SD_V
= 1.4V
R
SEC
DELAY
70
100
200
300
(kHz)
400
500
1.60
1.84
SS_MAXDC (V)
2.08
1.32
1.65
1.98
SD_V
2.31
2.64
f
(V)
OSC
SEC
42692 G31
42692 G33
42692 G32
SS_MAXDC Setting vs fOSC
(for OUT DC = 72%)
SS_MAXDC Reset and Active
Thresholds vs Temperature
2.32
2.20
2.08
1.96
1.84
1.72
1.60
1.2
T
= 25°C
A
SD_V
R
= 1.32V
SEC
= 10k
1.0
0.8
0.6
0.4
0.2
0
DELAY
ACTIVE THRESHOLD
RESET THRESHOLD
100
200
300
(kHz)
400
500
–50
0
25
50
75 100 125
–25
f
TEMPERATURE (°C)
OSC
42692 G34
42692 G35
42692fb
ꢈ
LTC4269-2
pin FuncTions
SHDN (Pin 1): Shutdown Input. Use this pin for auxiliary
power application. Drive SHDN high to disable LTC4269-2
operation and corrupt the signature resistance. If unused,
SYNC (Pin 12): Used to synchronize the internal oscillator
to an external signal. It is directly logic compatible and
can be driven with any signal between 10% and 90% duty
cycle. If unused, the pin should be connected to GND.
tie SHDN to V
.
PORTN
T2P (Pin 2): Type-2 PSE Indicator, Open-Drain. Low
SS_MAXDC (Pin 13): The external resistor divider from
REF
impedance indicates the presence of a Type-2 PSE.
V
sets the maximum duty cycle clamp (SS_MAXDC =
1.84V, SD_V = 1.32V gives 72% duty cycle). Capacitor
SEC
R
CLASS
(Pin 3): Class Select Input. Connect a resistor
on SS_MAXDC pin in combination with external resistor
between R
and V
to set the classification load
CLASS
PORTN
divider sets soft-start timing.
current.
V
(Pin 14): The output of an internal 2.5V reference
REF
V
(Pins5,6):PowerInput.TietothePDinputthrough
PORTN
whichsuppliesinternalcontrolcircuitry.Capableofsourc-
ing up to 2.5mA drive for external use. Bypass to GND
with a 0.1µF ceramic capacitor.
the diode bridge. Pins 5 and 6 must be electrically tied
together at the package.
NC (Pins 4, 7, 8, 25, 30, 31): No Connect.
SD_V
(Pin 15): The SD_V
pin, when pulled below
SEC
SEC
COMP (Pin 9): Output Pin of the Error Amplifier. The error
amplifier is an op amp, allowing various compensation
networks to be connected between the COMP pin and
FB pin for optimum transient response in a nonisolated
supply. The voltage on this pin corresponds to the peak
current of the external FET. Full operating voltage range is
between 0.8V and 2.5V corresponding to 0mV to 220mV
its accurate 1.32V threshold, is used to turn off the IC and
reduce current drain from V . The SD_V pin is con-
IN
SEC
nectedtosysteminputvoltagethrougharesistordividerto
define undervoltage lockout (UVLO) for the power supply
and to provide a volt-second clamp on the OUT pin. An
11µA pin current hysteresis allows external programming
of UVLO hysteresis.
at the I
pin. For applications using the 100mV OC
SENSE
GND (Pin 16): Analog Ground. Tie to V
.
NEG
pin for overcurrent detection, typical operating range for
the COMP pin is 0.8V to 1.6V. For isolated applications
where COMP is controlled by an opto-coupler, the COMP
BLANK (Pin 17): A resistor to GND adjusts the extended
blanking period of the overcurrent and current sense
amplifier outputs during FET turn-on—to prevent false
current limit trip. Increasing the resistor value increases
the blanking period.
pin output drive can be disabled with FB = V , reducing
the COMP pin current to (COMP – 0.7)/40k.
REF
FB(Pin10):Inanonisolatedsupply,FBmonitorstheoutput
voltage via an external resistor divider and is compared
with an internal 1.23V reference by the error amplifier. FB
I
(Pin 18): The Current Sense Input for the Control
SENSE
Loop. Connect this pin to the sense resistor in the source
connected to V disables error amplifier output.
of the external power MOSFET. A resistor in series with
REF
the I
pin programs slope compensation.
SENSE
R
(Pin11): A resistor to GND programs the operating
OSC
frequency of the IC between 100kHz and 500kHz. Nominal
voltage on the R
pin is 1.0V.
OSC
42692fb
ꢀ0
LTC4269-2
pin FuncTions
OC(Pin19):OCisanaccurate107mVthreshold, indepen-
dent of duty cycle, for overcurrent detection and trigger of
soft-start. Connect this pin directly to the sense resistor
in the source of the external power MOSFET.
V
(Pins 26, 27): Power Output. Connects the PoE
NEG
return line to the power supply through the internal Hot
Swap power MOSFET. Pins 26 and 27 must be electrically
tied together at the package.
DELAY(Pin20):AresistortoGNDadjuststhedelayperiod
between SOUT rising edge and OUT rising edge. Used to
maximize efficiency in forward converter applications by
adjustingthetiming.Increasingtheresistorvalueincreases
the delay period.
PWRGD (Pin 28): Active High Power Good Output, Open
Collector. Signals that the internal Hot Swap MOSFET is
on. High Impedance indicates power is good. PWRGD is
referenced to V
and is low impedance during inrush
NEG
and in the event of thermal overload. PWRGD is clamped
14V above V
.
NEG
PGND (Pin 21): Power Ground. Carries the gate driver’s
return current. Tie to V
.
PWRGD (Pin 29): Active Low Power Good Output, Open
Drain. Signals that the internal Hot Swap MOSFET is
on. Low Impedance indicates power is good. PWRGD
NEG
OUT (Pin 22): Drives the gate of an N-channel MOSFET
between 0V and V with a maximum limit of 13V on
IN
is referenced to V
and is high impedance during
PORTN
OUT pin set by an internal clamp. Active pull-off exists in
inrush and in the event of thermal overload. PWRGD has
shutdown (see electrical specification).
no internal clamps.
V (Pin23):InputSupplyforthePowerSupplyController.It
IN
V
(Pin 32): Input Voltage Positive Rail. This pin is
PORTP
mustbecloselydecoupledtoGND.Aninternalundervoltage
connected to the PD’s positive rail.
lockout threshold exists for V at approximately 14.25V
IN
on and 8.75V off.
Exposed Pad (Pin 33): Tie to GND and PCB heat sink.
SOUT (Pin 24): Switched Output in Phase with OUT Pin.
Provides sync signal for control of secondary-side FETs
inforwardconverterapplicationsrequiringhighlyefficient
synchronous rectification. SOUT is actively clamped to
12V. Active pull-off exists in shutdown (see electrical
specification). Can also be used to drive the active clamp
FET of an active clamp forward supply.
42692fb
ꢀꢀ
LTC4269-2
block DiagraMs
SHDN
1
32 V
PORTP
CLASSIFICATION
CURRENT LOAD
+
–
REF
T2P
2
EN
25k
16k
R
3
CLASS
29 PWRGD
CONTROL
CIRCUITS
28 PWRGD
27
26
V
V
NEG
V
V
5
6
PORTN
NEG
BOLD LINE INDICATES
HIGH CURRENT PATH
PORTN
42692 BD1
V
V
REF
14
SS_MAXDC
13
IN
23
START-UP
INPUT CURRENT (ISTART)
V
V
ON
IN
IN
V
REF
OFF
0.45V
+
–
>90%
SOFT-START CONTROL
+
–
2.5V
R
S
SOURCE
2.5mA
Q
–
+
p50mA
1.23V
ADAPTIVE
MAXIMUM
DUTY CYCLE
CLAMP
24
SOUT
–
+
12V
I
HYST
10µA SD_V
= 1.32V
SEC
> 1.32V
0µA SD_V
SEC
+
–
(TYPICAL 200kHz)
OSC
ON
DELAY
DRIVER
p1A
SD_V
R
15
11
S
R
Q
SEC
22
OUT
1.32V
(LINEAR)
OSC
(100 TO 500)kHz
SLOPE COMP
8µA 0% DC
RAMP
21 PGND
35µA 80% DC
SYNC
12
13V
BLANK
(VOLTAGE)
ERROR AMPLIFIER
+
–
1.23V
SENSE
CURRENT
OVER
CURRENT
–
+
–
+
19
18
OC
0mV TO 220mV
107mV
EXPOSED PAD
33
I
SENSE
10
FB
9
16
17
20
42692 BD2
COMP
GND
BLANK
DELAY
42692fb
ꢀꢁ
LTC4269-2
applicaTions inForMaTion
OVERVIEW
50
40
30
20
10
Power over Ethernet (PoE) continues to gain popularity
as more products are taking advantage of having DC
power and high speed data available from a single RJ45
connector. As PoE continues to grow in the marketplace,
Powered Device (PD) equipment vendors are running into
the 12.95W power limit established by the IEEE 802.3af
standard.
ON
UVLO
CLASSIFICATION
DETECTION V2
TIME
DETECTION V1
50
40
30
20
10
dV
dt
INRUSH
C1
=
The IEE802.3at standard establishes a higher power
allocation for Power over Ethernet while maintaining
backwards compatibility with the existing IEEE 802.3af
systems. Power Sourcing Equipment (PSE) and Powered
Devices are distinguished as Type 1 complying with the
IEEE 802.3af power levels, or Type 2 complying with the
IEEE 802.3at power levels. The maximum available power
of a Type 2 PD is 25.5W.
UVLO
ON
UVLO
T = R
C1
TIME
LOAD
TIME
–10
–20
–30
–40
–50
POWER
POWER
BAD
BAD
POWER
GOOD
PWRGD
PWRGD
TRACKS
TRACKS
V
V
PORTP
PORTP
The IEEE 802.3at standard also establishes a new method
ofacquiringpowerclassificationfromaPDandcommuni-
cating the presence of a Type 2 PSE. A Type 2 PSE has the
option of acquiring PD power classification by performing
2-event classification (Layer 1) or by communicating with
the PD over the data line (Layer 2). In turn, a Type 2 PD
must be able to recognize both layers of communications
and identify a Type 2 PSE.
PWRGD TRACKS
V
PORTN
20
10
POWER
BAD
POWER
GOOD
POWER
BAD
IN DETECTION
RANGE
TIME
INRUSH
The LTC4269-2 is specifically designed to support a PD
that must operate under the IEEE 802.3at standard. In
particular, the LTC4269-2 provides the T2P indicator bit
which recognizes 2-event classification. This indicator
bit may be used to alert the LTC4269-2 output load that
a Type 2 PSE is present. With an internal signature resis-
tor, classification circuitry, inrush control, and thermal
shutdown, the LTC4269-2 is a complete PD interface
solution capable of supporting in the next generation PD
applications.InadditiontothePDfrontend,theLTC4269-2
also incorporates a high efficiency synchronous forward
controllerthatminimizescomponentsizeswhilemaximiz-
ing output power.
LOAD, I
LOAD
CLASSIFICATION
I
CLASS
TIME
DETECTION I
DETECTION I
2
1
V1 – 2 DIODE DROPS
25kΩ
V2 – 2 DIODE DROPS
25kΩ
SELECTION
I
I
=
I
2
=
1
DEPENDENT ON R
CLASS
CLASS
INRUSH = 100mA
V
R
PORTP
I
=
LOAD
LOAD
LTC4269-2
R
I
LOAD
IN
R
V
V
CLASS PORTP
PSE
R
PWRGD
PWRGD
V
C1
CLASS
MODES OF OPERATION
The LTC4269-2 has several modes of operation depend-
PORTN
NEG
42692 F01
and
ing on the input voltage applied between the V
PORTN
PORTP
Figure 1. Output Voltage, PWRGD, PWRGD and
PD Current as a Function of Input Voltage
V
pins. Figure 1 presents an illustration of voltage
42692fb
ꢀꢂ
LTC4269-2
applicaTions inForMaTion
andcurrentwaveformstheLTC4269-2mayencounterwith
the various modes of operation summarized in Table 1.
voltage ranges. Note that the Electrical Specifications are
referenced with respect to the LTC4269-2 package pins.
Table 1. LTC4269-2 Modes of Operation as a Function
of Input Voltage
DETECTION
V
– V
(V) LTC4269-2 MODES OF OPERATION
PORTN
PORTP
During detection, the PSE looks for a 25k signature resis-
tor which identifies the device as a PD. The PSE will apply
two voltages in the range of 2.8V to 10V and measures
the corresponding currents. Figure 1 shows the detection
voltagesV1andV2andthecorrespondingPDcurrent.The
PSE calculates the signature resistance using the ∆V/∆I
measurement technique.
0V to 1.4V
Inactive (Reset after 1st Classification Event)
1.5V to 9.8V
25k Signature Resistor Detection Before 1st
Classification Event
(Mark, 11k Signature Corrupt After 1st
Classification Event)
(5.4V to 9.8V)
12.5V to On/UVLO
On/UVLO to 60V
>71V
Classification Load Current Active
Inrush and Power Applied to PD Load
Overvoltage Lockout, Classification and Hot Swap
are Disabled.
The LTC4269-2 presents its precision, temperature-com-
pensated 25k resistor between the V
and V
PORTP
PORTN
On/UVLO includes hysteresis. Rising input threshold: 37.2V max.
Falling input threshold: 30.0V min.
pins, alerting the PSE that a PD is present and requests
power to be applied. The LTC4269-2 signature resistor
also compensates for the additional series resistance
introduced by the input diode bridge. Thus a PD built with
the LTC4269-2 conforms to the IEEE 802.3af/at detection
specifications.
These modes satisfy the requirements defined in the
IEEE 802.3af/at specification.
INPUT DIODE BRIDGE
In the IEEE 802.3af/at standard, the modes of operation
reference the input voltage at the PD’s RJ45 connector.
SincethePDmusthandlepowerreceivedineitherpolarity
from either the data or the spare pair, input diode bridges
BR1 and BR2 are connected between the RJ45 connector
and the LTC4269-2 (Figure 2).
SIGNATURE CORRUPT OPTION
In some designs that include an auxiliary power option,
it is necessary to prevent a PD from being detected by a
PSE.TheLTC4269-2signatureresistancecanbecorrupted
with the SHDN pin (Figure 3). Taking the SHDN pin high
will reduce the signature resistor below 11k which is an
invalidsignaturepertheIEEE802.3af/atspecifications,and
alerts the PSE not to apply power. Invoking the SHDN pin
The input diode bridge introduces a voltage drop that af-
fectstherangeforeachmodeofoperation.TheLTC4269-2
compensates for these voltage drops so that a PD built
withtheLTC4269-2meetstheIEEE802.3af/at-established
RJ45
+
1
T1
TX
BR1
–
TX
2
3
+
TO PHY
RX
–
RX
POWERED
DEVICE (PD)
INPUT
6
V
PORTP
+
–
SPARE
BR2
4
5
LTC4269-2
0.1µF
100V
D3
V
PORTN
7
8
42692 F02
SPARE
Figure 2. PD Front End Using Diode Bridge on Main and Spare Inputs
42692fb
ꢀꢃ
LTC4269-2
applicaTions inForMaTion
Layer 2 communications takes place directly between the
PSE and the PD, the LTC4269-2 concerns itself only with
recognizing 2-event classification.
LTC4269-2
V
PORTP
25k SIGNATURE
RESISTOR
TO
PSE
14k
SHDN
In 2-event classification, a Type 2 PSE probes for power
classification twice. Figure 4 presents an example of a
2-event classification. The 1st classification event occurs
V
PORTN
42692 F03
SIGNATURE DISABLE
50
40
Figure 3. 25k Signature Resistor with Disable
1ST CLASS
30
2ND CLASS
ON
also ceases operation for classification and turns off the
internal Hot Swap FET. If this feature is not used, connect
UVLO
20
10
SHDN to V
.
PORTN
2ND MARK
1ST MARK
DETECTION V1
DETECTION V2
CLASSIFICATION
INRUSH
1ST CLASS
2ND CLASS
Classification provides a method for more efficient power
allocation by allowing the PSE to identify a PD power clas-
sification. Class 0 is included in the IEEE specification for
PDs that don’t support classification. Class 1-3 partitions
PDs into three distinct power ranges. Class 4 includes the
new power range under IEEE 802.3at (see Table 2).
LOAD, I
LOAD
40mA
TIME
2ND MARK
1ST MARK
DETECTION I
1
DETECTION I
2
During classification probing, the PSE presents a fixed
voltage between 15.5V and 20.5V to the PD (Figure 1).
The LTC4269-2 asserts a load current representing the
PD power classification. The classification load current
50
40
30
20
10
dV
dt
INRUSH
C1
=
UVLO
ON
UVLO
is programmed with a resistor R
from Table 2.
that is chosen
T = R
C1
CLASS
LOAD
TIME
TIME
Table 2. Summary of Power Classifications and LTC4269-2
RCLASS Resistor Selection
–10
–20
–30
–40
–50
MAXIMUM
NOMINAL
LTC4269-2
POWER LEVELS CLASSIFICATION
AT INPUT OF PD LOAD CURRENT
R
CLASS
RESISTOR
(Ω, 1%)
Open
124
CLASS USAGE
(W)
(mA)
<0.4
10.5
18.5
28
TRACKS
PORTN
0
1
2
3
4
Type 1
Type 1
Type 1
Type 1
Type 2
0.44 to 12.95
0.44 to 3.84
3.84 to 6.49
6.49 to 12.95
12.95 to 25.5
V
INRUSH = 100mA R
CLASS
= 30.9Ω
69.8
45.3
30.9
V
R
PORTP
I
=
LOAD
LOAD
40
LTC4269-2
R
I
LOAD
IN
R
V
CLASS PORTP
2-EVENT CLASSIFICATION AND THE T2P PIN
PSE
R
CLASS
C1
T2P
A Type 2 PSE may declare the availability of high power by
performing a 2-event classification (Layer 1) or by com-
municating over the high speed data line (Layer 2). A Type
2 PD must recognize both layers of communication. Since
V
V
NEG
PORTN
42692 F04
Figure 4. VNEG, T2P and PD Current as a
Result of 2-Event Classification
42692fb
ꢀꢄ
LTC4269-2
applicaTions inForMaTion
when the PSE presents an input voltage between 15.5V
to 20.5V and the LTC4269-2 presents a Class 4 load cur-
rent. The PSE then drops the input voltage into the mark
voltage range of 7V to 10V, signaling the 1st mark event.
The PD in the mark voltage range presents a load current
between 0.25mA to 4mA.
the voltage changes a PD encounters at the onset of the
classification load current, thus providing a trouble-free
transition between detection and classification modes.
TheLTC4269-2alsomaintainsapositiveI-Vslopethrough-
out the classification range up to the on voltage. In the
event a PSE overshoots beyond the classification voltage
range, the available load current aids in returning the PD
back into the classification voltage range. (The PD input
may otherwise be “trapped” by a reverse-biased diode
bridge and the voltage held by the 0.1µF capacitor.)
The PSE repeats this sequence, signaling the 2nd Clas-
sification and 2nd mark event occurrence. This alerts the
LTC4269-2 that a Type 2 PSE is present. The Type 2 PSE
then applies power to the PD and the LTC4269-2 charges
up the reservoir capacitor C1 with a controlled inrush
current. When C1 is fully charged, and the LTC4269-2
declares power good, the T2P pin presents an active low
INRUSH CURRENT
Once the PSE detects and optionally classifies the PD, the
PSEthenappliespowertothePD.WhentheLTC4269-2port
voltage rises above the on voltage threshold, LTC4269-2
signal, or low impedance output with respect to V
.
PORTN
The T2P output becomes inactive when the LTC4269-2
input voltage falls below the PoE undervoltage lockout
threshold.
connects V
MOSFET.
to V
through the internal power
NEG
PORTN
To control the power-on surge currents in the system, the
LTC4269-2 provides a fixed inrush current, allowing C1 to
ramp up to the line voltage in a controlled manner.
SIGNATURE CORRUPT DURING MARK
As a member of the IEEE 802.3at working group, Linear
noted that it is possible for a Type 2 PD to receive a false
indication of a 2-event classification if a PSE port is pre-
charged to a voltage above the detection voltage range
before the first detection cycle. The IEEE working group
modified the standard to prevent this possibility by requir-
ing a Type 2 PD to corrupt the signature resistance during
the mark event, alerting the PSE not to apply power. The
LTC4269-2 conforms to this standard by internally cor-
rupting the signature resistance. This also discharges the
port before the PSE begins the next detection cycle.
The LTC4269-2 keeps the PD inrush current below the
PSE current limit to provide a well-controlled power-up
characteristic that is independent of the PSE behavior.
This ensures a PD using the LTC4269-2 interoperability
with any PSE.
POE UNDERVOLTAGE LOCKOUT
The IEEE 802.3af/at specification for the PD dictates a
maximum turn-on voltage of 42V and a minimum turn-off
voltage of 30V. This specification provides an adequate
voltage to begin PD operation, and to discontinue PD op-
eration when the port voltage is too low. In addition, this
specification allows PD designs to incorporate an on-off
hysteresis window to prevent start-up oscillations.
PD STABILITY DURING CLASSIFICATION
Classificationpresentsachallengingstabilityproblemdue
to the wide range of possible classification load current.
The onset of the classification load current introduces a
voltage drop across the cable and increases the forward
voltage of the input diode bridge. This may cause the PD
to oscillate between detection and classification with the
onset and removal of the classification load current.
The LTC4269-2 features a PoE undervoltage lockout
(UVLO) hysteresis window (See Figure 5) that conforms
with the IEEE 802.3af/at specification and accommodates
the voltage drop in the cable and input diode bridge at the
onset of the inrush current.
The LTC4269-2 prevents this oscillation by introducing a
voltagehysteresiswindowbetweenthedetectionandclas-
sification ranges. The hysteresis window accommodates
Once C1 is fully charged, the LTC4269-2 turns on its inter-
nal MOSFET and passes power to the PD. The LTC4269-2
42692fb
ꢀꢅ
LTC4269-2
applicaTions inForMaTion
LTC4269-2
29 PWRGD
+
C1
5µF
MIN
LTC4269-2
OVLO
ON
UVLO
TSD
PD
LOAD
V
PORTP
CONTROL
CIRCUIT
TO
PSE
UNDERVOLTAGE
OVERVOLTAGE
LOCKOUT
28 PWRGD
CIRCUIT
V
V
NEG
PORTN
V
V
5
6
27
V
42692 F05
PORTN
NEG
NEG
CURRENT-LIMITED
TURN ON
26
V
PORTN
LTC4269-2
POWER MOSFET
V
– V
PORTN
PORTP
42692 F06
BOLD LINE INDICATES HIGH CURRENT PATH
INRUSH COMPLETE
0V TO ON*
>ON*
<UVLO*
>OVLO
*INCLUDES ON-UVLO HYSTERESIS
ON THRESHOLD 36.1V
UVLO THRESHOLD 30.7V
OVLO THRESHOLD 71.0V
OFF
ON
OFF
OFF
ON < V
< OVLO
PORTP
AND NOT IN THERMAL SHUTDOWN
POWER
POWER
GOOD
NOT
Figure 5. LTC4269-2 Undervoltage and Overvoltage Lockout
GOOD
continues to power the PD load as long as the port volt-
age does not fall below the UVLO threshold. When the
LTC4269-2 port voltage falls below the UVLO threshold,
the PD is disconnected, and classification mode resumes.
C1 discharges through the LTC4269-2 circuitry.
V
V
< UVLO
> OVLO
PORTP
PORTP
OR THERMAL SHUTDOWN
Figure 6. LTC4269-2 Power Good Functional and State Diagram
When power good is declared and active, the PWRGD pin
COMPLEMENTARY POWER GOOD
is low impedance with respect to V
.
PORTN
When LTC4269-2 fully charges the load capacitor (C1),
power good is declared and the LTC4269-2 load can safely
beginoperation. The LTC4269-2 providescomplementary
power good signals that remain active during normal
operation and are deasserted when the port voltage falls
below the PoE UVLO threshold, when the voltage exceeds
the overvoltage lockout (OVLO) threshold, or in the event
of a thermal shutdown. See Figure 6.
PWRGD PIN WHEN SHDN IS INVOKED
InPDapplicationswhereanauxiliarypowersupplyinvokes
the SHDN feature, the PWRGD pin becomes high imped-
ance. This prevents the PWRGD pin that is connected to
the “RUN” pin of the DC/DC converter from interfering
with the DC/DC converter operations when powered by
an auxiliary power supply.
The PWRGD pin features an open-collector output refer-
encedtoV whichcaninterfacedirectlywiththeSD_V
NEG
SEC
OVERVOLTAGE LOCKOUT
pin. When power good is declared and active, the PWRGD
The LTC4269-2 includes an Overvoltage Lockout (OVLO)
feature (Figure 5) which protects the LTC4269-2 and its
load from an overvoltage event. If the input voltage ex-
ceeds the OVLO threshold, the LTC4269-2 discontinues
PD operation. Normal operations resume when the input
voltage falls below the OVLO threshold and when C1 is
charged up.
pin is high impedance with respect to V . An internal
NEG
14V clamp limits the PWRGD pin voltage. Connecting
the PWRGD pin to the SD_V
pin prevents the DC/DC
SEC
converter from commencing operation before the PDI
interface completely charges the reservoir capacitor, C1.
The active low PWRGD pin connects to an internal, open-
drain MOSFET referenced to V
and can interface
PORTN
directlytotheshutdownpinofaDC/DCconverterproduct.
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ꢀꢆ
LTC4269-2
applicaTions inForMaTion
THERMAL PROTECTION
The increased current levels in a Type 2 PD over a Type 1
increase the current imbalance in the magnetics which
can interfere with data transmission. In addition, proper
termination is also required around the transformer to
providecorrectimpedancematchingandtoavoidradiated
and conducted emissions. Transformer vendors such as
Bel Fuse, Coilcraft, Halo, Pulse and Tyco (Table 4) can
assist in selecting an appropriate isolation transformer
and proper termination methods.
TheIEEE802.3af/atspecificationrequiresaPDtowithstand
any applied voltage from 0V to 57V indefinitely. However,
there are several possible scenarios where a PD may
encounter excessive heating.
During classification, excessive heating may occur if the
PSEexceedsthe75msprobingtimelimit.Atturn-on,when
the load capacitor begins to charge, the instantaneous
power dissipated by the PD interface can be large before
it reaches the line voltage. And if the PD experiences a
fast input positive voltage step in its operational mode
(for example, from 37V to 57V), the instantaneous power
dissipated by the PD Interface can be large.
Table 4. Power over Ethernet Transformer Vendors
VENDOR
CONTACT INFORMATION
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
www.belfuse.com
TheLTC4269-2includesathermalprotectionfeaturewhich
protects the LTC4269-2 from excessive heating. If the
LTC4269-2junctiontemperatureexceedstheovertempera-
turethreshold,theLTC4269-2discontinuesPDoperations.
Normaloperationresumeswhenthejunctiontemperature
falls below the overtemperature threshold and when C1 is
charged up and power good becomes inactive.
Coilcraft Inc.
1102 Silver Lake Road
Gary, IL 60013
Tel: 847-639-6400
www.coilcraft.com
Halo Electronics
PCA Electronics
Pulse Engineering
Tyco Electronics
1861 Landings Drive
Mountain View, CA 94043
Tel: 650-903-3800
www.haloelectronics.com
16799 Schoenborn Street
North Hills, CA 91343
Tel: 818-892-0761
www.pca.com
EXTERNAL INTERFACE AND COMPONENT SELECTION
Transformer
12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
Nodes on an Ethernet network commonly interface to the
outside world via an isolation transformer. For PDs, the
isolation transformer must also include a center tap on
the RJ45 connector side (see Figure 7).
www.pulseeng.com
308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
www.circuitprotection.com
RJ45
+
1
Input Diode Bridge
TX
14 T1
12
1
3
BR1
HD01
Figure 2 shows how two diode bridges are typically con-
nected in a PD application. One bridge is dedicated to the
data pair while the other bridge is dedicated to the spare
pair. The LTC4269-2 supports the use of either silicon or
Schottkyinputdiodebridges.However,therearetrade-offs
in the choice of diode bridges.
–
TX
13
10
2
5
2
3
+
TO PHY
RX
11
9
4
6
–
RX
6
COILCRAFT ETH1-230LD
+
V
PORTP
SPARE
4
5
7
8
BR2
HD01
C1
LTC4269-2
C14
0.1µF
100V
D3
SMAJ58A
TVS
An input diode bridge must be rated above the maximum
current the PD application will encounter at the tempera-
ture the PD will operate. Diode bridge vendors typically
call out the operating current at room temperature, but
derate the maximum current with increasing temperature.
Consultthediodebridgevendorsfortheoperatingcurrent
–
SPARE
V
V
PORTN
NEG
42692 F07
Figure 7. PD Front End with Isolation Transformer, Diode
Bridges, Capacitors and a Transient Voltage Suppressor (TVS)
de-rating curve.
42692fb
ꢀꢇ
LTC4269-2
applicaTions inForMaTion
Asilicondiodebridgecanconsumeover4%oftheavailable
powerinsomePDapplications.UsingSchottkydiodescan
help reduce the power loss with a lower forward voltage.
Classification Resistor (R
)
CLASS
The R
resistor sets the classification load current,
corresponding to the PD power classification. Select the
value of R from Table 2 and connect the resistor
pinsasshowninFigure 4,
pin if the classification load current is
not required. The resistor tolerance must be 1% or better
to avoid degrading the overall accuracy of the classifica-
tion circuit.
CLASS
A Schottky bridge may not be suitable for some high
temperature PD applications. The leakage current has
a temperature and voltage dependency that can reduce
the perceived signature resistance. In addition, the IEEE
802.3af/atspecificationmandatestheleakageback-feeding
throughtheunusedbridgecannotgeneratemorethan2.8V
across a 100k resistor when a PD is powered with 57V.
CLASS
betweentheR
andV
CLASS
PORTN
or float the R
CLASS
Load Capacitor
Sharing Input Diode Bridges
The IEEE 802.3af/at specification requires that the PD
maintains a minimum load capacitance of 5µF and does
not specify a maximum load capacitor. However, if the
load capacitor is too large, there may be a problem with
inadvertent power shutdown by the PSE.
At higher temperatures, a PD design may be forced to
consider larger bridges in a bigger package because the
maximum operating current for the input diode bridge is
drasticallyderated. The largerpackage maynot beaccept-
able in some space-limited environments.
ThisoccurswhenthePSEvoltagedropsquickly. Theinput
diode bridge reverses bias, and the PD load momentarily
powers off the load capacitor. If the PD does not draw
power within the PSE’s 300ms disconnection delay, the
PSE may remove power from the PD. Thus, it is necessary
to evaluate the load current and capacitance to ensure that
an inadvertent shutdown cannot occur.
One solution to consider is to reconnect the diode bridges
so that only one of the four diodes conducts current in
each package. This configuration extends the maximum
operating current while maintaining a smaller package
profile. Figure 7 shows how the reconnect the two diode
bridges.Consultthediodebridgevendorsforthede-rating
curve when only one of four diodes is in operation.
The load capacitor can store significant energy when fully
charged.ThePDdesignmustensurethatthisenergyisnot
inadvertently dissipated in the LTC4269-2. For example,
Input Capacitor
The IEEE 802.3af/at standard includes an impedance
requirement in order to implement the AC disconnect
function. A 0.1µF capacitor (C14 in Figure 7) is used to
meet this AC impedance requirement. Place this capacitor
as close to the LTC4269-2 as possible.
if the V
pin shorts to V
while the capacitor
PORTP
PORTN
is charged, current will flow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4269-2.
T2P Interface
Transient Voltage Suppressor
When a 2-event classification sequence successfully
completes, the LTC4269-2 recognizes this sequence,
and provides an indicator bit, declaring the presence of
a Type 2 PSE. The open-drain output provides the option
to use this signal to communicate to the LTC4269-2 load,
or to leave the pin unconnected.
The LTC4269-2 specifies an absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events.
However, the pins that interface to the outside world can
routinely see excessive peak voltages. To protect the
LTC4269-2, install a transient voltage suppressor (D3)
betweentheinputdiodebridgeandtheLTC4269-2asclose
to the LTC4269-2 as possible as shown in Figure 7.
Figure 8 shows two interface options using the T2P
pin and the opto-isolator. The T2P pin is active low and
connects to an optoisolater to communicate across the
42692fb
ꢀꢈ
LTC4269-2
applicaTions inForMaTion
These options come with various trade-offs and design
considerations. Contact Linear Technology applications
support for detailed information on implementing custom
auxiliary power sources.
+
V
V
PORTP
LTC4269-2
R
P
TO
PSE
TO PD’s
MICROPROCESSOR
V
–54V
T2P
PORTN
IEEE 802.3AT SYSTEM POWER-UP REQUIREMENT
OPTION 1: SERIES CONFIGURATION FOR ACTIVE LOW/LOW IMPEDANCE OUTPUT
Under the IEEE 802.3at standard, a PD must operate
under 12.95W in accordance with IEEE 802.3at standard
until it recognizes a Type 2 PSE. Initializing PD operation
in 12.95W mode eliminates interoperability issue in case
a Type 2 PD connects to a Type 1 PSE. Once the PD rec-
ognizes a Type 2 PSE, the IEEE 802.3at standard requires
the PD to wait 80ms in 12.95W operation before 25.5W
operation can commence.
+
V
V
PORTP
R
LTC4269-2
T2P
P
TO
PSE
TO PD’s
MICROPROCESSOR
V
V
NEG
–54V
PORTN
42692 F08
OPTION 2: SHUNT CONFIGURATION FOR ACTIVE HIGH/OPEN COLLECTOR OUTPUT
MAINTAIN POWER SIGNATURE
Figure 8. T2P Interface Examples
In an IEEE 802.3af/at system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
requirepower.TheMPSrequiresthePDtoperiodicallydraw
at least 10mA and also have an AC impedance less than
26.25k in parallel with 0.05µF. If one of these conditions
is not met, the PSE may disconnect power to the PD.
DC/DC converter isolation barrier. The pull-up resistor R
P
is sized according to the requirements of the opto-isola-
tor operating current, the pull-down capability of the T2P
+
+
pin, and the choice of V . V for example can come from
the PoE supply rail (which the LTC4269-2 V
is tied
PORTP
to), or from the voltage source that supplies power to
the DC/DC converter. Option 1 has the advantage of not
drawing power unless T2P is declared active.
Isolation
The802.3standardrequiresEthernetportstobeelectrically
isolatedfromallotherconductorsthatareuseraccessible.
Thisincludesthemetalchassis,otherconnectors,andany
auxiliary power connection. For PDs, there are two com-
mon methods to meet the isolation requirement. If there
are any user-accessible connections to the PD, then an
isolatedDC/DCconverterisnecessarytomeettheisolation
requirements. If user connections can be avoided, then it
is possible to meet the safety requirement by completely
enclosing the PD in an insulated housing.
Shutdown Interface
To corrupt the signature resistance, the SHDN pin can be
driven high with respect to V
. If unused, connect
PORTN
SHDN directly to V
.
PORTN
Exposed Pad
TheLTC4269-2usesathermallyenhancedDFN12package
that includes an Exposed Pad. The Exposed Pad should
be electrically connected to the GND pin’s PCB copper
plane. This plane should be large enough to serve as the
heat sink for the LTC4269-2.
Switcher Controller Operation
The LTC4269-2 has a current mode synchronous PWM
controller optimized for control of a forward converter
topology. The LTC4269-2 is ideal for power systems
where very high efficiency and reliability, low complexity
and cost are required in a small space. Key features of the
LTC4269-2includeanadaptivemaximumdutycycleclamp.
Auxiliary Power Source
In some applications, it is desirable to power the PD from
an auxiliary power source such as a wall adapter. Auxiliary
power can be injected into the PD at several locations with
priority chosen between PoE or auxiliary power sources.
42692fb
ꢁ0
LTC4269-2
applicaTions inForMaTion
An additional output signal is included for synchronous
rectifiercontroloractiveclampcontrol.Aprecision107mV
thresholdsensesovercurrentconditionsandtriggerssoft-
start for low stress short-circuit protection and control.
The key functions of the LTC4269-2 PWM controller are
shown in the Block Diagrams.
(1) MOSFET peak current sense at I
pin
SENSE
(2) Adaptive maximum duty cycle clamp reached during
load/line transients
(3) Maximum duty cycle reset of the PWM latch
During any of the following conditions—low V , low
IN
SD_V
or overcurrent detection at the OC pin—a soft-
SEC
Part Start-Up
start event is latched and both SOUT and OUT turn off
In normal operation, the SD_V pin must exceed 1.32V
immediately (Figure 11).
SEC
and the V pin must exceed 14.25V to allow the part
IN
Leading Edge Blanking
to turn on. This combination of pin voltages allows the
2.5V V pin to become active, supplying the LTC4269-2
REF
To prevent MOSFET switching noise causing premature
turn-off of SOUT or OUT, programmable leading edge
blanking exists. This means both the current sense com-
parator and overcurrent comparator outputs are ignored
during MOSFET turn-on and for an extended period after
the OUT leading edge (Figure 12). The extended blanking
period is programmable by adjusting a resistor from the
BLANK pin to GND.
control circuitry and providing up to 2.5mA external drive.
SD_V thresholdcanbeusedforexternallyprogramming
SEC
the power supply undervoltage lockout (UVLO) threshold
on the input voltage to the forward converter. Hysteresis
on the UVLO threshold can also be programmed since
the SD_V pin draws 11µA just before part turn-on and
SEC
0µA after part turn-on.
With the LTC4269-2 turned on, the V pin can drop as
IN
Adaptive Maximum Duty Cycle Clamp
(Volt-Second Clamp)
low as 8.75V before part shutdown occurs. This V pin
IN
hysteresis(5.5V)combinedwithlow460µAstart-upinput
current allows low power start-up using a resistor/capaci-
tor network from power supply input voltage to supply
the V pin (Figure 10). The V capacitor value is chosen
For forward converter applications, a maximum switch
duty cycle clamp which adapts to transformer input volt-
age is necessary for reliable control of the MOSFET. This
volt-second clamp provides a safeguard for transformer
reset that prevents transformer saturation. Instantaneous
load changes can cause the converter loop to demand
maximum duty cycle. If the maximum duty cycle of the
switch is too great, the transformer reset voltage can ex-
ceed the voltage rating of the primary-side MOSFETs with
catastrophicdamage.Manyconverterssolvethisproblem
by limiting the operational duty cycle of the MOSFET to
50%orless—orbyusingafixed(non-adaptive)maximum
duty cycle clamp with very large voltage rated MOSFETs.
The LTC4269-2 provides a volt-second clamp to allow
MOSFET duty cycles well above 50%. This gives greater
power utilization for the MOSFETs, rectifiers and trans-
former resulting in less space for a given power output.
In addition, the volt-second clamp can allow a reduced
IN
IN
to prevent V falling below its turn-off threshold before
IN
a bias winding in the converter takes over supply to the
V pin.
IN
Output Drivers
The LTC4269-2 has two outputs, SOUT and OUT. The OUT
pin provides a 1A peak MOSFET gate drive clamped to
13V. The SOUT pin has a 50mA peak drive clamped to
12V and provides sync signal timing for synchronous
rectification control or active clamp control.
For SOUT and OUT turn-on, a PWM latch is set at the
start of each main oscillator cycle. OUT turn-on is delayed
from SOUT turn-on by a time, t
(Figure 14). t
DELAY
DELAY
is programmed using a resistor from the DELAY pin to
GND and is used to set the timing control of the secondary
synchronous rectifiers for optimum efficiency.
voltage rating on the MOSFET resulting in lower R
DS(ON)
for greater efficiency. The volt-second clamp defines a
SOUT and OUT turn off at the same time each cycle by
one of three methods:
maximum duty cycle ‘guard rail’ which falls when power
supply input voltage increases.
42692fb
ꢁꢀ
LTC4269-2
applicaTions inForMaTion
An increase of voltage at the SD_V
pin causes the
Aresistordividerfromtheapplication’soutputvoltagegen-
erates a voltage at the inverting FB input of the LTC4269-2
erroramplifier(ortotheinputofanexternalopto-coupler)
and is compared to an accurate reference (1.23V for
LTC4269-2).Theerroramplifieroutput(COMP)definesthe
SEC
maximum duty cycle clamp to decrease. If SD_V
is
SEC
resistively divided down from power supply input volt-
age, a volt-second clamp is realized. To adjust the initial
maximum duty cycle clamp, the SS_MAXDC pin voltage
is programmed by a resistor divider from the 2.5V V
input threshold (I
) of the current sense comparator.
REF
SENSE
pin to GND. An increase of programmed voltage on
SS_MAXDC pin provides an increase of switch maximum
duty cycle clamp.
COMP voltages between 0.8V (active threshold) and 2.5V
define a maximum I threshold from 0mV to 220mV.
SENSE
By connecting I
to a sense resistor in series with the
SENSE
source of an external power MOSFET, the MOSFET peak
current trip point (turn off) can be controlled by COMP
levelandhencebytheoutputvoltage.Anincreaseinoutput
load current causing the output voltage to fall, will cause
Soft-Start
The LTC4269-2 provides true PWM soft-start by using the
SS_MAXDC pin to control soft-start timing. The propor-
tionalrelationshipbetweenSS_MAXDCvoltageandswitch
maximum duty cycle clamp allows the SS_MAXDC pin
to slowly ramp output voltage by ramping the maximum
switch duty cycle clamp—until switch duty cycle clamp
seamlessly meets the natural duty cycle of the converter.
COMP to rise, increasing I
threshold, increasing the
SENSE
current delivered to the output. For isolated applications,
the error amplifier COMP output can be disabled to allow
theopto-couplertotakecontrol.SettingFB=V disables
REF
the error amplifier COMP output, reducing pin current to
(COMP – 0.7)/40k.
A soft-start event is triggered whenever V is too low,
IN
SD_V
is too low (power supply UVLO), or a 107mV
SEC
Slope Compensation
overcurrent threshold at OC pin is exceeded. Whenever a
soft-start event is triggered, switching at SOUT and OUT
is stopped immediately.
Thecurrentmodearchitecturerequiresslopecompensation
to be added to the current sensing loop to prevent subhar-
monic oscillations which can occur for duty cycles above
50%. Unlike most current mode converters which have a
slope compensation ramp that is fixed internally, placing a
constraint on inductor value and operating frequency, the
LTC4269-2 has externally adjustable slope compensation.
Slope compensation can be programmed by inserting an
The SS_MAXDC pin is discharged and only released for
charging when it has fallen below its reset threshold
of 0.45V and all faults have been removed. Increasing
voltage on the SS_MAXDC pin above 0.8V will increase
switch maximum duty cycle. A capacitor to GND on the
SS_MAXDCpinincombinationwitharesistordividerfrom
externalresistor(R
)inserieswiththeI
pin.The
SLOPE
SENSE
V
, defines the soft-start timing.
REF
LTC4269-2 has a linear slope compensation ramp which
sourcescurrentoutoftheI
pinofapproximately8µA
SENSE
Current Mode Topology (I
Pin)
SENSE
at 0% duty cycle to 35µA at 80% duty cycle.
The LTC4269-2 current mode topology eases frequency
compensation requirements because the output induc-
tor does not contribute to phase delay in the regulator
loop. This current mode technique means that the error
amplifier (nonisolated applications) or the opto-coupler
(isolatedapplications)commandscurrent(ratherthanvolt-
age) to be delivered to the output. This makes frequency
compensation easier and provides faster loop response
to output load transients.
Overcurrent Detection and Soft-Start (OC Pin)
An added feature to the LTC4269-2 is a precise 107mV
sense threshold at the OC pin used to detect overcurrent
conditions in the converter and set a soft-start latch. The
OC pin is connected directly to the source of the primary-
side MOSFET to monitor peak current in the MOSFET (Fig-
ure 13). The 107mV threshold is constant over the entire
duty cycle range of the converter because it is unaffected
by the slope compensation added to the I
pin.
SENSE
42692fb
ꢁꢁ
LTC4269-2
applicaTions inForMaTion
Synchronizing
POWER SUPPLY
INPUT VOLTAGE (V )
S
ASYNCpinallowstheLTC4269-2oscillatortobesynchro-
nized to an external clock. The SYNC pin can be driven
from a logic-level output, requiring less than 0.8V for a
logic-level low and greater than 2.2V for a logic-level high.
Duty cycle should run between 10% and 90%. To avoid
lossofslopecompensationduringsynchronization,thefree
R1
LTC4269-2
SD_V
SEC
–
11µA
1.32V
R2
+
PWRGD
runningoscillatorfrequency,f ,shouldbeprogrammed
OSC
to80%oftheexternalclockfrequency(f
).TheR
SYNC
SLOPE
resistor chosen for nonsynchronized operation should be
increased by 1.25x (= f /f ).
42692 F09
SYNC OSC
Figure 9. Programming Power Supply
Undervoltage Lockout (UVLO)
Shutdown and Programming the Power Supply
Undervoltage Lockout
POWER SUPPLY
INPUT VOLTAGE (V )
S
TheLTC4269-2hasanaccurate1.32Vshutdownthreshold
FROM AUXILIARY WINDING
at the SD_V
pin. This threshold can be used in con-
R
SEC
START
V
LTC4269-2
IN
junction with a resistor divider to define the power supply
undervoltagelockoutthreshold(UVLO)ofthepowersupply
D1*
–
+
inputvoltage(V )(Figure9).Apincurrenthysteresis(11µA
S
before part turn-on, 0µA after part turn-on) allows power
supplyUVLOhysteresistobeprogrammed. Calculationof
the on/off thresholds for the power supply input voltage
can be made as follows:
1.32V
C
START
V
S(OFF)
V
S(ON)
Threshold = 1.32[1 + (R1/R2)]
42692 F10
*FOR V > 25V, ZENER D1 RECOMMENDED
S
Threshold = V
+ (11µA • R1)
S(OFF)
(V
< V < 25V)
Z
IN ON(MAX)
Connect the PWRGD pin to the resistive divider network
at the SD_V pin to prevent the DC/DC converter from
Figure 10. Low Power Start-Up
SEC
starting before the PD interface completely charges the
increases to drive the IC (5.2mA) and the output drivers
(I ). A large enough capacitor is chosen at the V pin
to prevent V falling below its turn-off threshold before
a bias winding in the converter takes over supply to V .
This technique allows a simple resistor/capacitor for
start-up which draws low power from the system supply
to the converter.
reservoir capacitor, C1 (Figure 9).
DRIVE
IN
IN
The SD_V
pin must not be left open since there must
SEC
IN
be an external source current >11µA to lift the pin past its
1.32V threshold for part turn-on.
Micropower Start-Up: Selection of Start-Up Resistor
and Capacitor for V
IN
Forsysteminputvoltagesexceedingtheabsolutemaximum
rating of the LTC4269-2 V pin, an external Zener should
The LTC4269-2 uses turn-on voltage hysteresis at the V
IN
IN
be connected from the V pin to GND. This covers the
pin and low start-up current to allow micropower start-up
IN
conditionwhereV chargespastV
butthepartdoes
(Figure 10). The LTC4269-2 monitors V pin voltage to
IN
IN(ON)
IN
not turn on because SD_V
< 1.32V. In this condition,
allow the part to turn-on at 14.25V and the part to turn-
off at 8.75V. Low start-up current (460µA) allows a large
resistor to be connected between the power supply input
SEC
V will continue to charge towards system V , possibly
IN
IN
exceeding the rating for the V pin. The Zener voltage
IN
should obey V
< V < 25V.
supply and V . Once the part is turned on, input current
IN(ONMAX)
Z
IN
42692fb
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Programming Oscillator Frequency
timescanvarydependingonMOSFETtype.Forthisreason
the LTC4269-2 performs true ‘leading edge blanking’ by
The oscillator frequency (f ) of the LTC4269-2 is pro-
OSC
automatically blanking OC and I
comparator outputs
SENSE
grammed using an external resistor, R , connected
OSC
until OUT rises to within 0.5V of V or reaches its clamp
IN
between the R
pin and GND. Figure 11 shows typical
resistor values. The LTC4269-2 free-run-
OSC
level of 13V. The second phase of blanking starts after
the leading edge of OUT has been completed. This phase
is programmable by the user with a resistor connected
from the BLANK pin to GND. Typical durations for this
f
vs R
OSC
OSC
ning oscillator frequency is programmable in the range
of 100kHz to 500kHz.
Stray capacitance and potential noise pickup on the R
portion of the blanking period are from 45ns at R
OSC
BLANK
pin should be minimized by placing the R
resistor as
= 10k to 540ns at R
= 120k. Blanking duration can
OSC
BLANK
be approximated as:
close as possible to the R
pin and keeping the area of
OSC
the R
node as small as possible. The ground side of
OSC
Blanking (extended) = [45(R /10k)]ns
BLANK
theR
resistorshouldbereturneddirectlytothe(analog
OSC
ground) GND pin. R
can be calculated by:
(See graph in the Typical Performance Characteristics
section).
OSC
R
OSC
= 9.125k [(4100k/f ) – 1]
OSC
Programming Leading Edge Blank Time
Programming Current Limit (OC Pin)
For PWM controllers driving external MOSFETs, noise
can be generated at the source of the MOSFET during
gate rise time and some time thereafter. This noise can
The LTC4269-2 uses a precise 107mV sense threshold
at the OC pin to detect overcurrent conditions in the
converter and set a soft-start latch. It is independent of
duty cycle because it is not affected by slope compensa-
potentially exceed the OC and I
pin thresholds of the
SENSE
LTC4269-2 to cause premature turn-off of SOUT and OUT
pinsinadditiontofalsetriggerofsoft-start.TheLTC4269-2
provides a programmable leading edge blanking of the
tion programmed at the I
pin. The OC pin monitors
SENSE
the peak current in the primary MOSFET by sensing the
voltage across a sense resistor (R ) in the source of the
S
OC and I
comparator outputs to avoid false current
MOSFET. The overcurrent limit for the converter can be
SENSE
sensing during MOSFET switching.
programmed by:
Blanking is provided in two phases (Figure 12): The first
phaseautomaticallyblanksduringgaterisetime. Gaterise
Overcurrent limit = (107mV/R )(N /N ) – (½)(I )
RIPPLE
S
P
S
(AUTOMATIC)
LEADING
EDGE
(PROGRAMMABLE)
CURRENT
SENSE
500
450
400
350
300
250
200
150
EXTENDED
BLANKING
BLANKING
DELAY
OUT
R
BLANK
10k < R
b 240k
100ns
BLANK
(MIN)
= 10k
42692 F12
BLANKING
100
50 100 150 200 250 300 350 400
42692 F11
R
(kΩ)
OSC
0
Xns
X + 45ns
[X + 45(R
/10k)]ns
BLANK
Figure 11. Oscillator Frequency, fOSC, vs ROSC
Figure 12. Leading Edge Blank Timing
42692fb
ꢁꢃ
LTC4269-2
applicaTions inForMaTion
where:
Programming Synchronous Rectifier Timing:
SOUT to OUT delay (‘t ’)
DELAY
R = sense resistor in source of primary MOSFET
S
The LTC4269-2 has an additional output SOUT which pro-
vides a ±50mA peak drive clamped to 12V. In applications
requiring synchronous rectification for high efficiency,
the LTC4269-2 SOUT provides a sync signal for second-
ary side control of the synchronous rectifier MOSFETs
(Figure 14). Timing delays through the converter can
cause non-optimum control timing for the synchronous
rectifier MOSFETs. The LTC4269-2 provides a program-
I
= I ripple current in the output inductor L1
P-P
RIPPLE
N = number of transformer secondary turns
S
N = number of transformer primary turns
P
Programming Slope Compensation
TheLTC4269-2usesacurrentmodearchitecturetoprovide
fast response to load transients and to ease frequency
compensation requirements. Current mode switching
regulators which operate with duty cycles above 50%
and have continuous inductor current must add slope
compensation to their current sensing loop to prevent
subharmonic oscillations. (For more information on slope
compensation, see Application Note 19.) The LTC4269-2
has programmable slope compensation to allow a wide
range of inductor values, to reduce susceptibility to PCB
generated noise and to optimize loop bandwidth. The
LTC4269-2 programs slope compensation by inserting a
mable delay (t
, Figure 14) between SOUT rising
DELAY
edge and OUT rising edge to optimize timing control for
the synchronous rectifier MOSFETs to achieve maximum
efficiency gains. A resistor R
connected from the
DELAY
DELAY pin to GND sets the value of t
. Typical values
DELAY
for t
range from 10ns with R
= 160k (see graph in the Typical Performance
= 10k to 160ns
DELAY
DELAY
with R
DELAY
Characteristics section).
t
DELAY
resistor, R
, in series with the I
pin (Figure 13).
SENSE
SLOPE
SENSE
LTC4269-2
SOUT
OUT
TheLTC4269-2generatesacurrentattheI
pinwhich
is linear from 0% duty cycle to the maximum duty cycle
of the OUT pin. A simple calculation of I • R
DELAY
42692 F14
R
DELAY
SENSE
SENSE
SLOPE
pin for
gives an added ramp to the voltage at the I
programmable slope compensation. (See both graphs
Pin Current vs Duty Cycle and I Maximum
Figure 14. Programming SOUT and OUT Delay: tDELAY
I
SENSE
SENSE
Threshold vs Duty Cycle in the Typical Performance
Characteristics section.)
Programming Maximum Duty Cycle Clamp
For forward converter applications, a maximum switch
duty cycle clamp which adapts to transformer input volt-
age is necessary for reliable control of the MOSFETs. This
volt-second clamp provides a safeguard for transformer
resetthatpreventstransformersaturation.TheLTC4269-2
CURRENT SLOPE = 35µA • DC
LTC4269-2
V
I
= V
+ (I
• R
)
(ISENSE)
SENSE
SOURCE
SENSE
SLOPE
= 8µA + 35DC µA
OUT
OC
V
SOURCE
DC = DUTY CYCLE
R
SLOPE
FOR SYNC OPERATION
SD_V
and SS_MAXDC pins provide a capacitor-less,
SEC
I
SENSE
I
= 8µA + (k • 35DC)µA
SENSE(SYNC)
programmable volt-second clamp solution using simple
resistor ratios (Figure 15).
k = f /f
OSC SYNC
R
S
42692 F13
An increase of voltage at the SD_V
pin causes the
SEC
maximumdutycycleclamptodecrease.DerivingSD_V
Figure 13. Programming Slope Compensation
SEC
from a resistor divider connected to system input voltage
42692fb
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LTC4269-2
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(3) The maximum duty cycle clamp calculated in (2)
should be programmed to be 10% greater than the
maximum operational duty cycle calculated in (1).
Simple adjustment of maximum duty cycle can be
achieved by adjusting SS_MAXDC.
POWER SUPPLY
INPUT VOLTAGE
R1
R2
LTC4269-2
ADAPTIVE
DUTY CYCLE
CLAMP INPUT
SD_V
SEC
SS_MAXDC
R *
T
Example calculation for (2):
V
REF
42692 F15
For R = 35.7k, R = 100k, V = 2.5V,
R
T
B
REF
B
MAX DUTY CYCLE
CLAMP ADJUST INPUT
R
= 40k, f
= 200kHz and SD_V
= 1.32V,
= 40ns
DELAY
OSC
SEC
DELAY
this gives SS_MAXDC(DC) = 1.84V, t
and k = 1
*MINIMUM ALLOWABLE R IS 10k TO
T
GUARANTEE SOFT-START PULL-OFF
Maximum Duty Cycle Clamp
Figure 15. Programming Maximum Duty Cycle Clamp
= 1 • 0.522(1.84/1.32) – (40ns • 200kHz)
= 0.728 – 0.008 = 0.72 (Duty Cycle Clamp = 72%)
creates the volt-second clamp. The maximum duty cycle
clamp can be adjusted by programming voltage on the
Note 1: To achieve the same maximum duty cycle clamp at
100kHz as calculated for 200kHz, the SS_MAXDC voltage
should be reprogrammed by,
SS_MAXDC pin using a resistor divider from V . An
REF
increase of voltage at the SS_MAXDC pin causes the
maximum duty cycle clamp to increase.
SS_MAXDC(DC) (100kHz)
= SS_MAXDC(DC) (200kHz) • k (200kHz)/k (100kHz)
= 1.84 • 1.0/1.055 = 1.74V (k = 1.055 for 100kHz)
To program the volt-second clamp, the following steps
should be taken:
(1) The maximum operational duty cycle of the converter
should be calculated for the given application.
Note 2 : To achieve the same maximum duty cycle clamp
while synchronizing to an external clock at the SYNC pin,
the SS_MAXDC voltage should be reprogrammed as,
(2) An initial value for the maximum duty cycle clamp
should be calculated using the equation below with a
first pass guess for SS_MAXDC.
SS_MAXDC (DC) (fsync)
= SS_MAXDC (DC) (200kHz) • [(fosc/fsync) +
0.09(fosc/200kHz)0.6]
Note: Since maximum operational duty cycle occurs at
minimum system input voltage (UVLO), the voltage at the
For SS_MAXDC (DC) (200kHz) = 1.84V for 72%
duty cycle
SD_V
pin = 1.32V.
SEC
Max Duty Cycle Clamp (OUT Pin) =
k • 0.522(SS_MAXDC(DC)/SD_V ) – (t
SS_MAXDC (DC) (fsync = 250kHz) for 72%
duty cycle
• f )
DELAY OSC
SEC
= 1.84 • [(200kHz/250kHz) + 0.09(1)0.6]
= 1.638V
where:
SS_MAXDC(DC) = V (R /(R + R )
REF
B
T
B
Programming Soft-Start Timing
SD_V
= 1.32V at minimum system input voltage
SEC
The LTC4269-2 has built-in soft-start capability to provide
low stress controlled start-up from a list of fault condi-
tions that can occur in the application (see Figures 16
and 17). The LTC4269-2 provides true PWM soft-start by
t
= programmed delay between SOUT and OUT
DELAY
k = 1.11 – 5.5e–7 • (f
)
OSC
42692fb
ꢁꢅ
LTC4269-2
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t
: PROGRAMMABLE SYNCHRONOUS DELAY
DELAY
using the SS_MAXDC pin to control soft-start timing. The
proportionalrelationshipbetweenSS_MAXDCvoltageand
switch maximum duty cycle clamp allows the SS_MAXDC
pintoslowlyrampoutputvoltagebyrampingthemaximum
switch duty cycle clamp—until switch duty cycle clamp
seamlessly meets the natural duty cycle of the converter.
SOUT
OUT
SS_MAXDC
A capacitor C on the SS_MAXDC pin and the resistor
FAULTS TRIGGERING SOFT-START
< 8.75V
SS
V
IN
OR
SD_V
OR
divider from V used to program maximum switch duty
REF
0.8V (ACTIVE THRESHOLD)
< 1.32V (UVLO)
SEC
cycle clamp, determine soft-start timing (Figure 18).
0.45V (RESET THRESHOLD)
0.2V
OC > 107mV (OVERCURRENT)
A soft-start event is triggered for the following faults:
SOFT-START LATCH RESET:
SOFT-START
LATCH SET
V
> 14.25V
IN
(1) V < 8.75V, or
IN
(> 8.75V IF LATCH SET BY OC)
AND
SD_V
AND
> 1.32V
SEC
(2) SD_V
< 1.32V (UVLO), or
SEC
OC < 107mV
AND
SS_MAXDC < 0.45V
(3) OC > 107mV (overcurrent condition)
42692 F16
When a soft-start event is triggered, switching at SOUT
and OUT is stopped immediately. A soft-start latch is set
andSS_MAXDCpinisdischarged.TheSS_MAXDCpincan
only recharge when the soft-start latch has been reset.
Figure 16. Timing Diagram
SS_MAXDC
Note: A soft-start event caused by (1) or (2) above, also
causes V to be disabled and to fall to GND.
SOFT-START
EVENT TRIGGERED
0.8V (ACTIVE THRESHOLD)
0.45V (RESET THRESHOLD)
TIMING (A): SOFT START FAULT REMOVED
REF
Soft-start latch reset requires all of the following:
BEFORE SS_MAXDC FALLS TO 0.45V
(A) V > 14.25V*, and
IN
SS_MAXDC
(B) SD_V
> 1.32V, and
SEC
(C) OC < 107mV, and
0.8V (ACTIVE THRESHOLD)
(D) SS_MAXDC < 0.45V (SS_MAXDC reset threshold)
0.45V (RESET THRESHOLD)
0.2V
*V > 8.75V is okay for latch reset if the latch was only
42692 F17
IN
TIMING (B): SOFT-START FAULT REMOVED
AFTER SS_MAXDC FALLS PAST 0.45V
set by overcurrent condition in (3) above.
SS_MAXDC Discharge Timing
Figure 17. Soft-Start Timing
It can be seen in Figure 17 that two types of discharge
can occur for the SS_MAXDC pin. In timing (A) the fault
that caused the soft-start event has been removed be-
fore SS_MAXDC falls to 0.45V. This means the soft-start
latch will be reset when SS_MAXDC falls to 0.45V and
SS_MAXDCwillbegincharging.Intiming(B),thefaultthat
caused the soft-start event is not removed until some time
after SS_MAXDC has fallen past 0.45V. The SS_MAXDC
pin continues to discharge to 0.2V and remains low until
all faults are removed.
SS_MAXDC(DC)
LTC4269-2
LTC4269-2
SS_MAXDC
R
CHARGE
SS_MAXDC
R
C
SS
T
V
REF
C
SS
R
B
42692 F18
SS_MAXDC CHARGING MODEL
SS_MAXDC(DC) = V [R /(R + R )]
REF
B
T
B
R
= [R • R /(R + R )]
CHARGE
T
B
T
B
Figure 18. Programming Soft-Start Timing
42692fb
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LTC4269-2
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The time for SS_MAXDC to fall to a given voltage can be
approximated as:
The calculation of charging time for the SS_MAXDC pin
between any two voltage levels can be approximated as
an RC charging waveform using the model shown in
Figure 16.
SS_MAXDC(t
)=
FALL
(C /I ) • [SS_MAXDC(DC) – V
]
SS DIS
SS(MIN)
TheabilitytopredictSS_MAXDCrisetimebetweenanytwo
voltages allows prediction of several key timing periods:
where:
I
= net discharge current on C
DIS
SS
(1) No Switching Period (time from SS_MAXDC(DC) to
C
SS
= capacitor value at SS_MAXDC pin
V
+ time from V
to V
)
SS(MIN)
SS(MIN)
SS(ACTIVE)
(2) Converter Output Rise Time (time from V
) to
SS_MAXDC(DC) = programmed DC voltage
SS(ACTIVE
is the level of SS_MAXDC where
V
; V
SS(REG) SS(REG)
maximum duty cycle clamp equals the natural duty
cycle of the switch)
V
= minimum SS_MAXDC voltage before
SS(MIN)
recharge
–4
I
≅ 8e + (V – V
)[(1/2R ) – (1/R )]
SS(MIN) B T
DIS
REF
(3) Time For Maximum Duty Cycle Clamp within X% of
Target Value
For faults arising from (1) and (2):
= 100mV.
V
REF
The time for SS_MAXDC to charge to a given voltage V
SS
is found by re-arranging:
For a fault arising from (3):
= 2.5V.
V
(–t/RC)
REF
V (t) = SS_MAXDC(DC) (1 – e
SS
)
SS_MAXDC(DC) = V [R /(R + R )]
REF
B
T
B
to give,
t = RC • (–1) • ln(1 – V /SS_MAXDC(DC))
V
= SS_MAXDC reset threshold = 0.45V
SS(MIN)
(if fault removed before t
SS
)
FALL
where,
Example
For an overcurrent fault (OC > 100mV), V = 2.5V,
V
SS
= SS_MAXDC voltage at time t
REF
SS_MAXDC(DC) = programmed DC voltage setting
maximum duty cycle clamp = V (R /(R + R )
R = 35.7k, R = 100k, C = 0.1µF and assume
T
B
SS
REF
B
T
B
V
I
= 0.45V,
SS(MIN)
DIS
–4
R = R
(Figure 16) = R • R /(R + R )
T B T B
CHARGE
≅ 8e + (2.5 – 0.45)[(½ • 100k) – (1/35.7k)]
–4
–4
–4
= 8e + (2.05)(–0.23e ) = 7.5e
SS_MAXDC(DC) = 1.84V
C = C (Figure 16)
SS
Example (1) No Switching Period
SS_MAXDC(t
)
The period of no switching for the converter, when a soft-
start event has occurred, depends on how far SS_MAXDC
can fall before recharging occurs and how long a fault ex-
ists. It will be assumed that a fault triggering soft-start is
removed before SS_MAXDC can reach its reset threshold
(0.45V).
FALL
–7
–4
–4
= (1e /7.5e ) • (1.84 – 0.45)=1.85e s
IftheOCfaultisnotremovedbefore185µsthenSS_MAXDC
will continue to fall past 0.45V towards a new V
.
SS(MIN)
The typical V for SS_MAXDC at 150µA is 0.2V.
OL
SS_MAXDC Charge Timing
No Switching Period = t
+ t
CHARGE
DISCHARGE
When all faults are removed and the SS_MAXDC pin
has fallen to its reset threshold of 0.45V or lower, the
SS_MAXDC pin will be released and allowed to charge.
t
= discharge time from SS_MAXDC(DC) to
DISCHARGE
0.45V
t
= charge time from 0.45V to V
SS(ACTIVE)
CHARGE
SS_MAXDC will rise until it settles at its programmed DC
voltage—setting the maximum switch duty cycle clamp.
t
was already calculated earlier as 185µs.
DISCHARGE
42692fb
ꢁꢇ
LTC4269-2
applicaTions inForMaTion
CHARGE
t
is calculated by assuming the following:
Also assume that the maximum duty cycle clamp pro-
grammed for this condition is 72% for SS_MAXDC(DC)
V
V
= 2.5V, R = 35.7k, R = 100k, C = 0.1µF and
SS(MIN)
REF
T
B
SS
= 1.84V, f
= 200kHz and R
= 40k.
OSC
DELAY
= 0.45V.
Step 2: Calculate V
SS(REG)
t
= t(V = 0.8V) – t(V = 0.45V)
SS SS
CHARGE
To calculate the level of SS_MAXDC (V
) that no
SS(REG)
Step 1:
SS_MAXDC(DC) = 2.5[100k/(35.7k + 100k)] = 1.84V
= (35.7k • 100k/135.7k) = 26.3k
longer clamps the natural duty cycle of the converter, the
equation for maximum duty cycle clamp must be used
(seeprevioussectionProgrammingMaximumDutyCycle
Clamp).
R
CHARGE
Step 2:
t(V = 0.45V) is calculated from:
The point where the maximum duty cycle clamp meets
DC(REG) during soft-start is given by:
SS
t = R
• C • (–1) • ln(1 – V /SS_MAXDC(DC))
SS
CHARGE
SS
–7
DC(REG) = Max Duty Cycle Clamp
0.6 = k • 0.522(SS_MAXDC(DC)/SD_V ) – (t
4
= 2.63e • 1e • (–1) • ln(1 – 0.45/1.84)
SEC
DELAY
–3
–4
= 2.63e • (–1) • ln(0.755) = 7.3e
Step 3:
t(V = 0.8V) is calculated from:
s
• f
)
OSC
For SD_V
= 1.32V, f
= 200kHz and
OSC
SEC
= 40k
R
DELAY
SS
This gives k = 1 and t
= 40ns.
DELAY
t = R
• C • (–1) • ln(1 – V /SS–MAXDC(DC))
SS SS
CHARGE
4
–7
= 2.63e • 1e • (–1) • ln(1 – 0.8/1.84)
Rearranging the above equation to solve for SS_MAXDC
= V
–3
–3
= 2.63e • (–1) • ln(0.565) = 1.5e
s
SS(REG)
From Step 1 and Step 2
= [0.6 + (t • f )(SD_V )]/(k • 0.522)
DELAY OSC SEC
= [0.6 + (40ns • 200kHz)(1.32V)]/(1 • 0.522)
= (0.608)(1.32)/0.522 = 1.537V
–3
–4
t
= (1.5 – 0.73)e s = 7.7e
s
CHARGE
The total time of no switching for the converter due to a
soft-start event
Step 3: Calculate t(V
)) – t(V
)
SS(REG
SS(ACTIVE)
Recall the time for SS_MAXDC to charge to a given volt-
age V is given by:
–4
–4
–4
= t
+ t
= 1.85e + 7.7e = 9.55e
s
DISCHARGE
CHARGE
SS
Example (2) Converter Output Rise Time
t = R
• C • (–1) • ln(1 – V /SS_MAXDC(DC))
SS SS
CHARGE
The rise time for the converter output to reach regulation
can be closely approximated as the time between the start
(Figure 16 gives the model for SS_MAXDC charging)
For R = 35.7k, R = 100k, R = 26.3k
ofswitching(SS_MAXDC=V
)andthetimewhere
SS(ACTIVE)
T
B
CHARGE
converter duty cycle is in regulation (DC(REG)) and no
longercontrolledbySS_MAXDC(SS_MAXDC=V
Converter output rise time can be expressed as:
For C = 0.1µF, this gives t(V
)
SS
SS(ACTIVE)
).
SS(REG)
4
–7
= t(V
) = 2.63e • 1e • (–1) • ln(1 – 0.8/1.84)
SS(0.8V)
–3
–3
= 2.63e • (–1) • ln(0.565) = 1.5e
s
Output Rise Time = t(V
) – t(V
)
SS(REG)
SS(ACTIVE)
t(V
) = t(V
) = 26.3k • 0.1µF • –1 •
SS(REG)
SS(1.537V)
Step1:DetermineconverterdutycycleDC(REG)foroutput
in regulation.
–3
–3
ln(1 – 1.66/1.84) = 2.63e • (–1) • ln(0.146) = 5e
s
The rise time for the converter output:
The natural duty cycle DC(REG) of the converter depends
on several factors. For this example it is assumed that
DC(REG) = 60% for power supply input voltage near the
–3
= t(V
= 3.5e
) – t(V ) = (5 – 1.5)e
SS(ACTIVE)
s
SS(REG)
–3
s
power supply UVLO. This gives SD_V
= 1.32V.
SEC
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ꢁꢈ
LTC4269-2
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Example (3) Time For Maximum Duty Cycle Clamp to
Reach Within X% of Target Value
–4
From previous calculations, t(0.45) = 7.3e s.
Using previous values for R , R and C ,
T
B
SS
–4
–7
Amaximumdutycycleclampof72%wascalculatedprevi-
ously in the section ‘Programming Maximum Duty Cycle
Clamp’. The programmed value used for SS_MAXDC(DC)
was 1.84V.
t(1.803) = 2.63e • 1e • (–1) • ln(1 – 1.803/1.84)
–3
–2
= 2.63e • (–1) • ln(0.02) = 1.03e
s
Hence the time for SS_MAXDC to charge from its mini-
mum reset threshold of 0.45V to within 2% of its target
value is given by:
ThetimeforSS_MAXDCtochargefromitsminimumvalue
V
to within X% of SS_MAXDC(DC) is given by:
SS(MIN)
–2
–4
–3
t(1.803) – t(0.45) = 1.03e – 7.3e = 9.57e s
t(SS_MAXDC charge time within X% of target)
= t[(1 – (X/100) • SS_MAXDC(DC)] – t(V
)
SS(MIN)
For X = 2 and V
= 0.45V, t(0.98 • 1.84) – t(0.45)
SS(MIN)
= t(1.803) – t(0.45)
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ꢂ0
LTC4269-2
Typical applicaTion
E F F I C I E N C Y ( % )
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ꢂꢀ
LTC4269-2
package DescripTion
DKD Package
32-Lead Plastic DFN (7mm × 4mm)
(Reference LTC DWG # 05-08-1734 Rev A)
0.70 p 0.05
4.50 p 0.05
6.43 p0.05
2.65 p0.05
3.10 p 0.05
PACKAGE
OUTLINE
0.20 p 0.05
0.40 BSC
6.00 REF
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
7.00 p0.10
17
32
R = 0.05
TYP
0.40 p 0.10
6.43 p0.10
2.65 p0.10
4.00 p0.10
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 s 45o CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
16
1
0.20 p 0.05
0.40 BSC
0.75 p0.05
6.00 REF
BOTTOM VIEW—EXPOSED PAD
(DKD32) QFN 0707 REV A
0.200 REF
NOTE:
0.00 – 0.05
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
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ꢂꢁ
LTC4269-2
revision hisTory (Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
04/10 Connected PWRGD Pin to SD_V
Pin in Typical Applications Circuits.
1, 23, 31
SEC
Added Text Clarifying Connecting PWRGD Pin to SD_V
Pin in Shutdown and Programming the Power Supply
23
SEC
Undervoltage Lockout Section of Applications Information.
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ꢂꢂ
LTC4269-2
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
LT®1952
Single Switch Synchronous Forward Controller
Synchronous Controller, Programmable Volt-Sec Clamp, Low Start Current
LTC3803
Current Mode Flyback DC/DC Controller in ThinSOT™
200kHz Constant Frequency, Adjustable Slope Compensation, Optimized for
High Input Voltage Applications
LTC3805
LTC3825
Adjustable Frequency Current Mode Flyback Controller
Slope Comp Overcurrent Protect, Internal/External Clock
Isolate No-Opto Synchronous Flyback Controller with
Wide Input Supply Range
Adjustable Switching Frequency, Programmable Undervoltage Lockout,
Accurate Regulation Without Trim, Synchronous for High Efficiency.
LTC4257-1
LTC4258
IEEE 802.3af PD Interface Controller
100V 400mA Internal Switch, Programmable Classification Dual
Current Limit
Quad IEEE 802.3af Power over Ethernet Controller
Quad IEEE 802.3af Power over Ethernet Controller
Single IEEE 802.3af Power over Ethernet Controller
DC Disconnect Only, IEEE-Compliant PD Detection and Classification,
2
Autonomous Operation or I C Control
LTC4259A-1
LTC4263
AC or DC Disconnect IEEE-Compliant PD Detection and Classification,
2
Autonomous Operation or I C Control
AC or DC Disconnect IEEE-Compliant PD Detection and Classification,
Autonomous Operation
LTC4263-1
LTC4265
High Power Single PSE Controller
IEEE 802.3at PD Interface Controller
Internal Switch, Autonomous Operation, 30W
2-Event Classification Signaling, Programmable Classification,
Auxiliary Support
LTC4266
Quad IEEE 802.3at PSE Controller
Type 1 and 2 Compliant, 180mW/Port at 720mA, Advanced Power
Management, 4-Point PD Detection
LTC4267-1/
LTC4267-3
IEEE 802.3af PD Interface with Integrated Switching
Regulator
100V 400mA Internal Switch, Programmable Classification, 200KHz
or 300kHz Constant Frequency PWM, Interface and Switcher Optimized
for IEEE-Compliant PD System.
LTC4268-1
LTC4269-1
35W High Power PD Interface with Integrated Switching 750mA MOSFET, Programmable Classification, Synchronous No-Opto
Regulator Flyback Controller, 50kHz to 250kHz
IEEE 802.3at PD Interface Integrated Switching Regulator 2-Event Classification, Programmable Classification, Synchronous No-Opto
Flyback Controller, 50kHz to 250kHz
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LT 0409 REV B • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
ꢂꢃ
●
●
LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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