LTC4274IUHF#PBF_技术文档

LTC4274

+

Single PoE PSE Controller

FeAtures

Description

n

Compliant with IEEE 802.3at Type 1 and 2

The LTC^®4274 is a single power sourcing equipment con-

troller designed for use in IEEE 802.3 Type 1 and Type 2

(high power) compliant Power over Ethernet systems.

External power MOSFETs enhance system reliability and

minimizechannelresistance,cuttingpowerdissipationand

eliminating the need for heatsinks even at Type 2 power

levels. External power components also allow use at very

high power levels while remaining otherwise compatible

withtheIEEEstandard. 80V-ratedportpinsproviderobust

protection against external faults.

n

0.34Ω Total Channel Resistance

n

130mW/Port at 600mA

n

Advanced Power Management

n

8-Bit Programmable Current Limit (I

)

LIM

n

7-Bit Programmable Overload Currents (I

)

CUT

Fast Shutdown

14.5-Bit Port Current/Voltage Monitoring

2-Event Classiﬁcation

n

Very High Reliability 4-Point PD Detection

n

2-Point Forced Voltage

2-Point Forced Current

The LTC4274 includes advanced power management

features, including current and voltage readback and pro-

n

High Capacitance Legacy Device Detection

grammable I

and I thresholds. Available C libraries

CUT

LIM

LTC4259A-1 and LTC4266 SW Compatible

simplifysoftwaredevelopment;anoptionalAUTOpinmode

provides fully IEEE-compliant standalone operation with

no software required. Proprietary 4-point PD detection

circuitry minimizes false PD detection while supporting

legacy phone operation. Midspan operation is supported

with built-in 2-event classification and backoff timing.

2

1MHz I C Compatible Serial Control Interface

Midspan Backoff Timer

Supports Proprietary Power Levels Above 25W

Available in 38-Pin 5mm × 7mm QFN Package

2

ApplicAtions

Host communication is via a 1MHz I C serial interface.

n

PSE Switches/Routers

PSE Midspans

The LTC4274 is available in a 5mm × 7mm QFN package

that significantly reduces board space compared with

competing solutions.

n

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

++

ThinSOT and LTPoE are trademarks of Analog Devices, Inc. All other trademarks are the

property of their respective owners.

typicAl ApplicAtion

Complete Ethernet High Power Source

10Ω

AD0 AD1 AD2 AD3

SCL SDAIN SDAOUT INT

3.3V

V

DD

AUTO

MSD

RESET

MID

SHDN

0.1µF

SMAJ5.0A

10µF

+

DGND

AGND

LTC4274

10Ω

V

EE

SENSE GATE OUT

SMAJ58A

1µF

C

BULK

0.22µF

100V

S1B

TVS

BULK

PORT

–54V

4274 TA01

–54V

4274ff

1

For more information www.linear.com/LTC4274

LTC4274

Absolute MAxiMuM rAtings

Supply Voltages (Note 1)

Operating Temperature Range

AGND – V ........................................... –0.3V to 80V

LTC4274C ................................................ 0°C to 70°C

LTC4274I..............................................–40°C to 85°C

Junction Temperature (Note 2) ............................. 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)...................300°C

EE

DGND – V ............................................... –0.3V to 80V

EE

V

– DGND.............................................. –0.3V to 5.5V

Digital Pins

DD

SCL, SDAIN, SDAOUT, INT, SHDN, MSD, ADn,

RESET, AUTO, MID........... DGND –0.3V to V + 0.3V

DD

Analog Pins

GATE, SENSE, OUT................ V –0.3V to V + 80V

EE

pin conFigurAtion

TOP VIEW

38 37 36 35 34 33 32

SDAOUT

NC

1

2

3

4

5

6

7

8

9

31 GATE

30 SENSE

SDAIN

AD3

NC

29

28

27

26

25

AD2

V

EE

V

AD1

EE

39

AD0

DNC

NC

24 NC

23 NC

DGND 10

NC 11

22

21 NC

20

V

EE

NC 12

NC

13 14 15 16 17 18 19

UHF PACKAGE

38-LEAD (5mm × 7mm) PLASTIC QFN

EXPOSED PAD IS V (PIN 39) MUST BE SOLDERED TO PCB

EE

JMAX

T

= 125°C, θ = 34°C/W

JA

orDer inForMAtion

http://www.linear.com/product/LTC4274#orderinfo

LEAD FREE FINISH

LTC4274CUHF#PBF

LTC4274IUHF#PBF

TAPE AND REEL

PART MARKING*

4274

PACKAGE DESCRIPTION

38-Lead (5mm × 7mm) Plastic QFN

TEMPERATURE RANGE

0°C to 70°C

–40°C to 85°C

LTC4274CUHF#TRPBF

LTC4274IUHF#TRPBF

4274

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

4274ff

2

For more information www.linear.com/LTC4274

LTC4274

electricAl chArActeristics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. AGND – V_EE= 54V, AGND = DGND, and V_DD– DGND = 3.3V unless

otherwise noted. (Notes 3, 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main PoE Supply Voltage

AGND – V

For IEEE Type 1 Complaint Output

For IEEE Type 2 Complaint Output

EE

l

45

51

57

V

l

Undervoltage Lock-out Level

20

25

3.3

2.2

30

V

Supply Voltage

V – DGND

DD

3.0

4.3

DD

Undervoltage Lock-out

V

Allowable Digital Ground Offset

DGND – V

25

57

–5

3

V

EE

I

V

Supply Current

(AGND – V ) = 55V

–2.4

1.1

mA

EE

(V – DGND) = 3.3V

DD

Detection

l

Detection Current – Force Current

Detection Voltage – Force Voltage

First Point, AGND – V

Second Point, AGND – V

= 9V

220

140

240

160

260

180

µA

OUT

= 3.5V

OUT

AGND – V , 5µA ≤ I

≤ 500µA

OUT

l

First Point

Second Point

7

3

8

4

9

5

V

l

Detection Current Compliance

Detection Voltage Compliance

Detection Voltage Slew Rate

Min. Valid Signature Resistance

Max. Valid Signature Resistance

AGND – V

= 0V

0.8

0.9

12

mA

V

OUT

V

OC

AGND – V , Open Port

10.4

OUT

AGND – V , C

= 0.15µF

0.01

18.5

32

V/µs

kΩ

OUT PORT

15.5

27.5

17

29.7

Classification

l

V

CLASS

Classification Voltage

AGND – V , 0mA ≤ I ≤ 50mA

CLASS

16.0

53

20.5

67

V

OUT

Classification Current Compliance

Classification Threshold Current

V

= AGND

61

mA

OUT

l

Class 0 – 1

Class 1 – 2

Class 2 – 3

Class 3 – 4

5.5

6.5

14.5

23

33

48

7.5

mA

13.5

21.5

31.5

45.2

15.5

24.5

34.9

50.8

Class 4 – Overcurrent

l

V

MARK

Classification Mark State Voltage

Mark State Current Compliance

AGND – V , 0.1mA ≤ I ≤ 10mA

CLASS

7.5

53

9

10

67

V

OUT

V

OUT

= AGND

61

mA

Gate Driver

l

GATE Pin Pull-Down Current

Port Off, V

= V + 5V

0.4

0.08

mA

GATE

EE

= V + 1V

0.12

30

EE

GATE Pin Fast Pull-Down Current

GATE Pin On Voltage

V

= V + 5V

mA

V

GATE

EE

l

– V , I

= 1µA

8

2

12

14

EE GATE

Output Voltage Sense

Power Good Threshold Voltage

V

PG

V

OUT

– V

EE

2.4

2.8

V

4274ff

3

For more information www.linear.com/LTC4274

LTC4274

electricAl chArActeristics The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. AGND – V_EE= 54V, AGND = DGND, and V_DD– DGND = 3.3V unless

otherwise noted. (Notes 3, 4)

SYMBOL

PARAMETER

CONDITIONS

0V ≤ (AGND – V ) ≤ 5V

MIN

TYP

MAX

UNITS

l

OUT Pin Pull-Up Resistance to AGND

300

500

700

kΩ

OUT

Current Sense

V

CUT

Overcurrent Sense Voltage

V

SENSE

– V , icut1 = hpen = 00h

180

188

196

mV

EE

hpen = 01h, cut[5:0] ≥ 4 (Note 12)

cutrng = 0

cutrng = 1

l

9

4.5

9.38

4.69

9.75

4.88

mV/LSB

l

Overcurrent Sense in AUTO Pin Mode

Class 0, Class 3

Class 1

Class 2

90

26

49

94

28

52

98

30

55

mV

Class 4

152

159

166

V

LIM

V

LIM

V

LIM

Active Current Limit in 802.3af Compliant

Mode

V

– V , dblpwr = hpen = 00h

SENSE EE

= 55V (Note 12)

V

EE

l

V

A

< V

– V

< A – 29V

204

40

212

220

100

mV

EE

GND

OUT

GND

= 0V

OUT

Active Current Limit in High Power Mode

Active Current Limit in AUTO Pin Mode

hpen = 01h, lim1 = C0h, V = 55V

EE

l

V

– V = 0V to 10V

204

100

20

212

106

221

113

50

mV

OUT

EE

+ 23V < V

< AGND – 29V

= 0V

EE

OUT

AGND – V

OUT

V

OUT

– V = 0V to 10V, V = 55V

EE EE

Class 0 to Class 3

Class 4

l

102

204

106

212

110

221

mV

l

V

DC Disconnect Sense Voltage

Short-Circuit Sense

V

– V , rdis = 0

2.6

1.3

3.8

1.9

4.8

2.41

mV

MIN

SENSE

EE

– V , rdis = 1

EE

l

V

SENSE

V

SENSE

– V – V , rdis = 0

160

75

200

100

255

135

mV

SC

EE

LIM

– V – V , rdis = 1

EE

LIM

Port Current ReadBack

Resolution

No missing codes, fast_iv = 0

V – V

SENSE

14

30.5

30

bits

µV/LSB

dB

LSB Weight

EE

50-60Hz Noise Rejection

(Note 7)

Port Voltage ReadBack

Resolution

No missing codes, fast_iv = 0

14

5.835

30

bits

mV/LSB

dB

LSB Weight

AGND – V

(Note 7)

OUT

50-60Hz noise rejection

Digital Interface

l

V

Digital Input Low Voltage

ADn, SHDN, RESET, MSD, AUTO, MID

(Note 6)

0.8

V

ILD

2

l

I C Input Low Voltage

SCL, SDAIN (Note 6)

(Note 6)

V

Digital Input High Voltage

Digital Output Low Voltage

2.2

IHD

l

I

= 3mA, I = 3mA

0.4

0.7

V

SDAOUT

INT

= 5mA, I = 5mA

INT

4274ff

4

For more information www.linear.com/LTC4274

LTC4274

electricAl chArActeristics The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. AGND – V_EE= 54V, AGND = DGND, and V_DD– DGND = 3.3V unless

otherwise noted. (Notes 3, 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

50

MAX

UNITS

kΩ

Internal Pull-Up to V

ADn, SHDN, RESET, MSD

AUTO, MID

DD

Internal Pull-Down to DGND

Timing Characteristics

50

kΩ

l

t

Detection Time

Detection Delay

Beginning to End of Detection (Note 7)

270

300

290

310

470

ms

DET

t

From PD Connected to Port to Detection

Complete (Note 7)

DETDLY

l

t

First Class Event Duration

(Note 7)

11

6.8

11

19

12

8.6

12

22

13

10.3

13

ms

CLE1

ME1

CLE2

ME2

CLE3

PON

First Mark Event Duration

(Notes 7, 11)

(Note 7)

Second Class Event Duration

Second Mark Event Duration

Third Class Event Duration

Power On Delay in AUTO Pin Mode

(Note 7)

C

PORT

= 0.6µF (Note 7)

0.1

60

From End of Valid Detect to Application of

Power to Port (Note 7)

l

Turn On Rise Time

(AGND – V ): 10% to 90% of (AGND – V ),

15

24

µs

OUT

EE

C

PORT

= 0.15µF (Note 7)

l

Turn On Ramp Rate

C

= 0.15µF (Note 7)

10

V/µs

PORT

Fault Delay

From I

Fault to Next Detect

1.0

2.3

1.0

1.1

2.5

1.3

s

CUT

Midspan Mode Detection Backoff

Power Removal Detection Delay

Rport = 15.5kΩ (Note 7)

2.7

2.5

From Power Removal After t to Next

DIS

Detect (Note 7)

l

t

Maximum Current Limit Duration During Port

Startup

t

= 0, t = 0 (Notes 7, 12)

START0

52

62.5

6.3

66

ms

START

START1

Maximum Current Limit Duration After Port

Startup

= 0, t

= 0, t = 0h (Notes 7, 12)

LIM

CUT1

CUT0

LIM

Maximum Overcurrent Duration After Port

Startup

= 0, t

= 0 (Notes 7, 12)

CUT0

CUT

l

Maximum Overcurrent Duty Cycle

(Note 7)

5.8

1.6

6.7

3.6

%

t

Maintain Power Signature (MPS) Pulse Width Current Pulse Width to Reset Disconnect

Sensitivity

ms

MPS

Timer (Notes 7, 8)

l

Maintain Power Signature (MPS) Dropout

Time

t

[1:0] = 00b (Notes 5, 7, 12)

320

350

2

380

ms

DIS

conf

l

t

Masked Shut Down Delay

(Note 7)

6.5

3

µs

s

MSD

Port Shut Down Delay

SHDN

2

I C Watchdog Timer Duration

1.5

4274ff

5

For more information www.linear.com/LTC4274

LTC4274

electricAl chArActeristics The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. AGND – V_EE= 54V, AGND = DGND, and V_DD– DGND = 3.3V unless

otherwise noted. (Notes 3, 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

Minimum Pulse Width for Masked Shut

Down

(Note 7)

3

µs

l

Minimum Pulse Width for SHDN

Minimum Pulse Width for RESET

(Note 7)

3

µs

4.5

2

I C Timing

l

Clock Frequency

Bus Free Time

Start Hold Time

SCL Low Time

SCL High Time

Data Hold Time

(Note 7)

1

MHz

ns

t

1

t

2

t

3

t

4

t

5

Figure 5 (Notes 7, 9)

480

240

480

240

60

ns

l

Figure 5 (Notes 7, 9) Data into chip

Data out of chip

ns

120

l

t

Data Set-Up Time

Figure 5 (Notes 7, 9)

(Notes 7, 9, 10)

80

ns

µs

ns

6

7

8

r

Start Set-Up Time

240

Stop Set-Up Time

SCL, SDAIN Rise Time

SCL, SDAIN Fall Time

Fault Present to INT Pin Low

Stop Condition to INT Pin Low

ARA to INT Pin High Time

SCL Fall to ACK Low

120

60

f

150

1.5

120

(Notes 7, 9, 10)

(Notes 7, 9)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 140°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 3: All currents into device pins are positive; all currents out of device

pins are negative.

Note 4: The LTC4274 operates with a negative supply voltage (with

respect to ground). To avoid confusion, voltages in this data sheet are

referred to in terms of absolute magnitude.

Note 6: The LTC4274 digital interface operates with respect to DGND. All

logic levels are measured with respect to DGND.

Note 7: Guaranteed by design, not subject to test.

Note 8: The IEEE 802.3af specification allows a PD to present its

Maintain Power Signature (MPS) on an intermittent basis without being

disconnected. In order to stay powered, the PD must present the MPS for

t

within any t

time window.

MPS

MPDO

Note 9: Values measured at V

Note 10: If fault condition occurs during an I C transaction, the INT pin

will not be pulled down until a stop condition is present on the I C bus.

and V

.

ILD(MAX)

IHD(MIN)

2

Note 11: Load Characteristic of the LTC4274 during Mark:

7V < (AGND – V ) < 10V or I

< 50µA

OUT

Note 12: See the LTC4274 Software Programming documentation for

information on serial bus usage and device configuration and status

registers.

Note 5: t is the same as t

defined by IEEE 802.3at.

DIS

MPDO

4274ff

6

For more information www.linear.com/LTC4274

LTC4274

typicAl perForMAnce chArActeristics

Power On Sequence in AUTO

802.3af Classification in

AUTO Pin Mode

Pin Mode

Powering Up into a 180µF Load

GND

10

0

GND

FORCED CURRENT DETECTION

GND

V

DD

V

EE

= 3.3V

= –54V

PORT

VOLTAGE

20V/DIV

LOAD

FULLY

–10

–20

–30

–18.4

CHARGED

FORCED VOLTAGE

DETECTION

V

EE

PORT

CURRENT

200 mA/DIV

802.3af

PORT 1

V

DD

V

EE

= 3.3V

= –55V

PORT

VOLTAGE

10V/DIV

FOLDBACK

425mA

CURRENT LIMIT

CLASSIFICATION

V

DD

V

EE

= 3.3V

= –54V

–40

–50

–60

–70

PD IS CLASS 1

POWER ON

0mA

FET ON

GATE

VOLTAGE

10V/DIV

V

EE

V

EE

V

EE

5ms/DIV

100ms/DIV

4274 G02

4274 G01

4274 G03

2-Event Classification in

AUTO Pin Mode

Classification Transient Response

to 40mA Load Step

Classification Current Compliance

0

GND

V

DD

V

EE

= 3.3V

= –54V

V

DD

V

EE

= 3.3V

= –54V

40mA

0mA

–2

–4

–6

–8

PORT

CURRENT

20mA/DIV

T

A

= 25°C

–17.6

1ST CLASS EVENT

2ND CLASS EVENT

–10

–12

–14

–16

–18

–20

PORT

VOLTAGE

10V/DIV

V

= 3.3V

= –55V

DD

EE

PORT

VOLTAGE

1V/DIV

PD IS CLASS 4

–20V

V

EE

0

10

20

30

40

50

60

70

50µs/DIV

10ms/DIV

CLASSIFICATION CURRENT (mA)

4274 G05

4274 G04

4274 G06

802.3at I_LIMThreshold vs

Temperature

V

_DDSupply Current vs Voltage

V_EESupply Current vs Voltage

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

2.4

2.3

2.2

2.1

215

214

213

212

211

210

860

–40°C

25°C

85°C

V

= 3.3V

= –54V

SENSE

DD

EE

R

= 0.25Ω

856

852

848

844

840

REG 48h = C0h

–40°C

25°C

85°C

2.0

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3

SUPPLY VOLTAGE (V)

–60 –55 –50 –45 –40 –35 –30 –25 –20

SUPPLY VOLTAGE (V)

–40

0

40

–80

120

V

TEMPERATURE (°C)

DD

EE

4274 G07

4274 G08

4274 G09

4274ff

7

For more information www.linear.com/LTC4274

LTC4274

typicAl perForMAnce chArActeristics

802.3af I_LIMThreshold

vs Temperature

802.3at I_CUTThreshold

vs Temperature

108.00

107.25

106.50

432

429

163

162

652

648

644

640

V

= 3.3V

= –54V

SENSE

V

= 3.3V

= –54V

SENSE

DD

EE

DD

EE

R

= 0.25Ω

R

= 0.25Ω

REG 48h = 80h

REG 47h = E2h

161

160

159

158

426

423

420

105.75

105.00

636

630

–40

0

40

80

120

–40

0

40

80

120

TEMPERATURE (°C)

4274 G10

4274 G11

802.3af I_CUTThreshold

vs Temperature

DC Disconnect Threshold

vs Temperature

8.00

7.75

7.50

7.25

7.00

2.0000

1.9375

96.00

95.25

94.50

93.75

93.00

384

381

V

= 3.3V

= –54V

SENSE

V

= 3.3V

= –54V

SENSE

DD

EE

DD

EE

R

= 0.25Ω

R

= 0.25Ω

REG 47h = E2h

REG 47h = D4h

1.8750

1.8125

1.7500

378

375

372

–40

0

40

80

120

–40

0

40

80

120

TEMPERATURE (°C)

4266 G13

4274 G12

ADC Noise Histogram

Current Readback in Fast Mode

ADC Integral Nonlinearity

Current Limit Foldback

Current Readback in Fast Mode

1.0

0.5

900

800

700

600

500

400

300

200

100

0

225

400

V

– V = 110.4mV

EE

V

= 3.3V

SENSE

DD

EE

= –54V

200

175

150

125

100

75

350

300

250

200

150

100

50

R

SENSE

= 0.25Ω

REG 48h = C0h

0

–0.5

–1.0

50

25

0

50 100 150 200 250 300 350 400 450 500

–54

–45

–36

–9

0

191

192

193

ADC OUTPUT

196

–27

–18

194

195

V

(V)

CURRENT SENSE RESISTOR INPUT VOLTAGE (mV)

OUTn

4274 G16

4274 G14

4274 G15

4274ff

8

For more information www.linear.com/LTC4274

LTC4274

typicAl perForMAnce chArActeristics

ADC Noise Histogram

Current Readback in Slow Mode

ADC Integral Nonlinearity

Current Readback in Slow Mode

ADC Noise Histogram Port

Voltage Readback in Fast Mode

300

250

200

150

100

50

1.0

0.5

600

500

400

300

200

100

0

V

– V = 110.4mV

EE

AGND – V

= 48.3V

SENSE

OUT

0

–0.5

–1.0

0

50 100 150 200 250 300 350 400 450 500

CURRENT SENSE RESISTOR INPUT VOLTAGE (mV)

4274 G18

6139

6141

6143

6145

6147

260

261

262

ADC OUTPUT

263

264

265

ADC OUTPUT

4274 G17

4274 G19

ADC Integral Nonlinearity

Voltage Readback in Slow Mode

ADC Integral Nonlinearity

Voltage Readback in Fast Mode

ADC Noise Histogram Port

Voltage Readback in Slow Mode

1.0

0.5

600

500

400

300

200

100

0

1.0

0.5

AGND – V

= 48.3V

OUT

0

–0.5

–1.0

–0.5

–1.0

0

10

20

30

40

50

60

0

10

20

30

40

50

60

8532

8533

8534

8535

8536

ADC OUTPUT

PORT VOLTAGE (V)

4274 G20

4274 G22

4274 G21

MOSFET Gate Drive With Fast

Pull-Down

INTandSDAOUTPull-DownVoltage

vs Load Current

3

2.5

2

GND

V

DD

V

EE

= 3.3V

= –54V

PORT

VOLTAGE

20V/DIV

V

EE

FAST PULL DOWN

1.5

1

GATE

VOLTAGE

10V/DIV

CURRENT LIMIT

50Ω

FAULT

APPLIED

PORT

CURRENT

500mA/DIV

0.5

0

50Ω FAULT REMOVED

0mA

0

5

10

LOAD CURRENT (mA)

15 20 25 30 35 40

100µs/DIV

4274 G23

4274 G24

4274ff

9

For more information www.linear.com/LTC4274

LTC4274

test tiMing DiAgrAMs

t

CLASSIFICATION

DET

FORCED-

VOLTAGE

FORCED-CURRENT

0V

t

ME1

V

PORT

t

ME2

V

OC

V

MARK

15.5V

20.5V

V

CLASS

t

CLE1

t

CLE2

PD

CONNECTED

t

CLE3

t

PON

DETDLY

V

EE

INT

4274 F01

Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-Auto Modes

V

LIM

0V

V

CUT

V

SENSE

EE

V

TO V

EE

MIN

SENSE

TO V

t

, t

START ICUT

INT

t

DIS

MPS

4274 F03

4274 F02

Figure 2. Current Limit Timing

Figure 3. DC Disconnect Timing

t

r

3

t

f

4

V

GATE

SCL

t

MSD

V

EE

t

SHDN

t

6

t

8

t

5

7

MSD or

SHDN

2

SDA

4274 F04

4274 F05

t

1

Figure 4. Shut Down Delay Timing

Figure 5. I²C Interface Timing

4274ff

10

For more information www.linear.com/LTC4274

LTC4274

i²c tiMing DiAgrAMs

SCL

SDA

AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

0

1

0

START BY

MASTER

ACK BY

SLAVE

ACK BY

SLAVE

ACK BY

SLAVE

STOP BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

REGISTER ADDRESS BYTE

FRAME 3

DATA BYTE

4274 F06

Figure 6. Writing to a Register

SCL

SDA

AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK

AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

0

1

0

1

0

START BY

MASTER

ACK BY

SLAVE

ACK BY

SLAVE

REPEATED

START BY

MASTER

ACK BY

SLAVE

NO ACK BY

MASTER

STOP BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

REGISTER ADDRESS BYTE

FRAME 1

FRAME 2

DATA BYTE

SERIAL BUS ADDRESS BYTE

4274 F07

Figure 7. Reading from a Register

SCL

SDA

0

1

0

AD3 AD2 AD1 AD0 R/W

FRAME 1

ACK

D7 D6 D5 D4 D3 D2 D1 D0

ACK

STOP BY

MASTER

START BY

MASTER

ACK BY

SLAVE

NO ACK BY

MASTER

FRAME 2

DATA BYTE

SERIAL BUS ADDRESS BYTE

4274 F08

Figure 8. Reading the Interrupt Register (Short Form)

SCL

SDA

0

1

0

R/W

ACK

0

1

0

AD3 AD2 AD1 AD0

1

ACK

STOP BY

MASTER

START BY

MASTER

ACK BY

SLAVE

NO ACK BY

MASTER

FRAME 1

ALERT RESPONSE ADDRESS BYTE

FRAME 2

SERIAL BUS ADDRESS BYTE

4274 F09

Figure 9. Reading from Alert Response Address

4274ff

11

For more information www.linear.com/LTC4274

LTC4274

pin Functions

RESET: Chip Reset, Active Low. When the RESET pin is

low, the LTC4274 is held inactive with all ports off and all

internalregistersresettotheirpower-upstates. WhenRE-

SET is pulled high, the LTC4274 begins normal operation.

RESET can be connected to an external capacitor or RC

network to provide a power turn-on delay. Internal filter-

ing of the RESET pin prevents glitches less than 1µs wide

AD1: Address Bit 1. See AD3.

AD0: Address Bit 0. See AD3.

NC, DNC: All pins identified with “NC” or “DNC” must be

left unconnected.

DGND: Digital Ground. DGND is the return for the V

supply.

DD

from resetting the LTC4274. Internally pulled up to V .

DD

V :Logic Power Supply. Connectto a3.3V power supply

DD

MID: Midspan Mode Input. When high, the LTC4274 acts

as a midspan device. Internally pulled down to DGND.

relative to DGND. V must be bypassed to DGND near

DD

the LTC4274 with at least a 0.1µF capacitor.

INT: Interrupt Output, Open Drain. INT will pull low when

any one of several events occur in the LTC4274. It will

return to a high impedance state when bits 6 or 7 are set

in the Reset PB register (1Ah). The INT signal can be used

to generate an interrupt to the host processor, eliminating

the need for continuous software polling. Individual INT

events can be disabled using the Int Mask register (01h).

See the LTC4274 Software Programming documentation

formoreinformation.TheINTpinisonlyupdatedbetween

SHDN: Shutdown, Active Low. When pulled low, SHDN

shuts down the port, regardless of the state of the internal

registers. Pulling SHDN low is equivalent to setting the

Reset Port bit in the Reset Pushbutton register (1Ah).

Internal filtering of the SHDN pin prevents glitches less

than 1µs wide from resetting the port. Internally pulled

up to V .

DD

AGND: Analog Ground. AGND is the return for the V

supply.

EE

2

I C transactions.

SENSE: Current Sense Input. SENSE monitors the exter-

SCL:SerialClockInput.Highimpedanceclockinputforthe

2

nal MOSFET current via a 0.5Ω or 0.25Ω sense resistor

I C serial interface bus. SCL must be tied high if not used.

between SENSE and V . Whenever the voltage across

EE

SDAOUT: Serial Data Output, Open Drain Data Output for

the sense resistor exceeds the overcurrent detection

2

the I C Serial Interface Bus. The LTC4274 uses two pins

threshold V , the current limit fault timer counts up. If

CUT

to implement the bidirectional SDA function to simplify

the voltage across the sense resistor reaches the current

2

optoisolation of the I C bus. To implement a standard

limit threshold V , the GATE pin voltage is lowered to

LIM

bidirectional SDA pin, tie SDAOUT and SDAIN together.

SDAOUT should be grounded or left floating if not used.

See Applications Information for more information.

maintain constant current in the external MOSFET. See

Applications Information for further details.

GATE: Gate Drive. GATE should be connected to the gate

of the external MOSFET for the port. When the MOSFET

is turned on, the gate voltage is driven to 12V (typ) above

SDAIN: Serial Data Input. High impedance data input for

2

the I C serial interface bus. The LTC4274 uses two pins

to implement the bidirectional SDA function to simplify

V . During a current limit condition, the voltage at GATE

EE

2

optoisolation of the I C bus. To implement a standard

will be reduced to maintain constant current through the

bidirectional SDA pin, tie SDAOUT and SDAIN together.

SDAIN must be tied high if not used. See Applications

Information for more information.

external MOSFET. If the fault timer expires, GATE is pulled

down, turning the MOSFET off and recording a t

START

or

CUT

t

event.

AD3: Address Bit 3. Tie the address pins high or low to set

OUT: Output Voltage Monitor. OUT should be connected

to the output port. A current limit foldback circuit limits

2

theI CserialaddresstowhichtheLTC4274responds.This

addresswillbe010A A A A b.InternallypulleduptoV .

3 2 1 0

DD

AD2: Address Bit 2. See AD3.

4274ff

12

For more information www.linear.com/LTC4274

LTC4274

pin Functions

the power dissipation in the external MOSFET by reduc-

ing the current limit threshold when the drain-to-source

voltage exceeds 10V. The Power Good bit is set when the

(see the LTC4274 Software Programming documenta-

tion). The states of these register bits can subsequently

2

be changed via the I C interface. The real-time state of the

voltage from OUT to V drops below 2.4V (typ). A 500k

AUTO pin is read at bit 0 in the Pin Status register (11h).

Internally pulled down to DGND. Must be tied locally to

EE

resistor is connected internally from OUT to AGND when

the port is idle.

either V or DGND.

DD

V : Main Supply Input. Connect to a –45V to –57V

MSD: Maskable Shutdown Input. Active low. When pulled

low, all ports that have their corresponding mask bit set

in the Misc Config register (17h) will be reset, equivalent

to pulling the SHDN pin low. Internal filtering of the MSD

pin prevents glitches less than 1µs wide from resetting

EE

supply, relative to AGND.

AUTO: AUTO Pin Mode Input. AUTO pin mode allows the

LTC4274 to detect and power up a PD even if there is no

2

host controller present on the I C bus. The voltage of the

ports. Internally pulled up to V .

DD

AUTO pin determines the state of the internal registers

when the LTC4274 is reset or comes out of V UVLO

DD

4274ff

13

For more information www.linear.com/LTC4274

LTC4274

operAtion

Overview

The LTC4274 is a third-generation single PSE controller

in either an endpoint or midspan design. Virtually all nec-

essary circuitry is included to implement a IEEE 802.3at

compliant PSE design, requiring only an external power

MOSFET and sense resistor; these minimize power loss

compared to alternative designs with on-board MOSFETs

and increase system reliability in the event a single chan-

nel is damaged.

Power over Ethernet, or PoE, is a standard protocol for

sending DC power over copper Ethernet data wiring.

The IEEE group that administers the 802.3 Ethernet data

standards added PoE powering capability in 2003. This

original PoE spec, known as 802.3af, allowed for 48V DC

power at up to 13W. This initial spec was widely popular,

but 13W was not adequate for some requirements. In

2009, the IEEE released a new standard, known as 802.3at

or PoE+, increasing the voltage and current requirements

to provide 25W of power.

PoE Basics

Common Ethernet data connections consist of two or four

twisted pairs of copper wire (commonly known as CAT-5

cable), transformer-coupled at each end to avoid ground

loops. PoE systems take advantage of this coupling ar-

rangement by applying voltage between the center-taps

of the data transformers to transmit power from the PSE

to the PD without affecting data transmission. Figure 10

shows a high-level PoE system schematic.

The IEEE standard also defines PoE terminology. A device

that provides power to the network is known as a PSE, or

powersourcingequipment,whileadevicethatdrawspower

from the network is known as a PD, or powered device.

PSEs come in two types: Endpoints (typically network

switches or routers), which provide data and power; and

Midspans, which provide power but pass through data.

MidspansaretypicallyusedtoaddPoEcapabilitytoexisting

non-PoE networks. PDs are typically IP phones, wireless

access points, security cameras, and similar devices, but

could be nearly anything that runs from 25W or less and

includes an RJ45-style network connector.

To avoid damaging legacy data equipment that does not

expect to see DC voltage, the PoE spec defines a protocol

that determines when the PSE may apply and remove

power. Valid PDs are required to have a specific 25k

common-mode resistance at their input. When such a PD

is connected to the cable, the PSE detects this signature

CAT 5

20Ω MAX

ROUNDTRIP

0.05µF MAX

PSE

PD

RJ45

4

RJ45

4

5

GND

SPARE PAIR

1

AGND

Tx

Rx

2

3

2

3

DATA PAIR

LTC4274

2

I C

Rx

Tx

V

EE

GATE

GND

DC/DC

6

PWRGD

+

OUT

CONVERTER

V

LTC4265

–54V –54V

–54V

7

8

7

–

IN

OUT

8

SPARE PAIR

4274 F10

Figure 10. Power Over Ethernet System Diagram

4274ff

14

For more information www.linear.com/LTC4274

LTC4274

operAtion

resistance and turns on the power. When the PD is later

disconnected, the PSE senses the open circuit and turns

power off. The PSE also turns off power in the event of a

current fault or short circuit.

BACKWARDS COMPATIBILITY

The LTC4274 is fully software and pin compatible with

the LTC4266 if only port 1 was used.

The LTC4274 is designed to be backward compatible with

earlierPSEchipsinbothsoftwareandpinfunctions. Exist-

ing systems using either the LTC4258 or LTC4259A (or

compatible) devices can be substituted with the LTC4274

without software or PCB layout changes if only port 1 was

used; only minor BOM changes are required to implement

a fully compliant 802.3at design.

When a PD is detected, the PSE optionally looks for a

classification signature that tells the PSE the maximum

power the PD will draw. The PSE can use this information

to allocate power among several ports, police the current

consumptionofthePD,ortorejectaPDthatwilldrawmore

power that the PSE has available. The classification step

is optional; if a PSE chooses not to classify a PD, it must

assume that the PD is a 13W (full 802.3af power) device.

Because of the backwards compatibility features, some of

the internal registers are redundant or unused when the

LTC4274 is operated as recommended. For more details

on usage in compatibility mode, refer to the LTC4258/

LTC4259A device data sheets.

New in 802.3at

Thenewer802.3atstandardsupersedes802.3afandbrings

several new features:

•ꢀ A PD may draw as much as 25.5W. Such PDs (and the

PSEs that support them) are known as Type 2. Older

13W 802.3af equipment is classified as Type 1. Type 1

PDs will work with all PSEs; Type 2 PDs may require

Type2PSEstoworkproperly.TheLTC4274isdesigned

to work in both Type 1 and Type 2 PSE designs, and

also supports non-standard configurations at higher

power levels.

Special Compatibility Mode Notes

•ꢀ The LTC4274 can use either 0.5Ω or 0.25Ω sense

resistors, while the LTC425x chips always used 0.5Ω.

To maintain compatibility, if the AUTO pin is low when

the LTC4274 powers up it assumes the sense resistor

is 0.5Ω; if it is high at power up, the LTC4274 assumes

0.25Ω. The resistor value setting can be reconfigured

at any time after power up. In particular, systems that

use 0.25Ω sense resistors and have AUTO tied low

must reconfigure the resistor settings after power up.

•ꢀ The Classification protocol is expanded to allow Type 2

PSEs to detect Type 2 PDs, and to allow Type 2 PDs to

determine if they are connected to a Type 2 PSE. Two

versions of the new Classification protocol are avail-

able: an expanded version of the 802.3af Class Pulse

protocol, and an alternate method integrated with the

existing LLDP protocol (using the Ethernet data path).

TheLTC4274fullysupportsthenewClassPulseprotocol

and is also compatible with the LLDP protocol (which

is implemented in the data communications layer, not

in the PoE circuitry).

•ꢀ The LTC4259A included both AC and DC disconnect

sensing circuitry, but the LTC4274 has only DC discon-

nect sensing. For the sake of compatibility, register

bits used to enable AC disconnect in the LTC4259A are

implemented in the LTC4274, but they simply mirror

the bits used for DC disconnect.

•ꢀ The LTC4258 and LTC4259A required 10k resistors

between the OUTn pins and the drains of the external

MOSFETs. These resistors must be shorted or replaced

with zero ohm jumpers when using the LTC4274.

•ꢀ Fault protection current levels and timing are adjusted

to reduce peak power in the MOSFET during a fault;

this allows the new 25.5W power levels to be reached

using the same MOSFETs as older 13W designs.

•ꢀ The LTC4258 and LTC4259A included a BYP pin,

decoupled to AGND with 0.1µF. This pin changes to

the MID pin on the LTC4274. The capacitor should be

removed for Endspan applications, or replaced with a

zero ohm jumper for Midspan applications.

4274ff

15

For more information www.linear.com/LTC4274

LTC4274

ApplicAtions inForMAtion

Operating Modes

Regardlessofwhichmodeitisin,theLTC4274willremove

power automatically from a port that generates a current

limit fault. It will also automatically remove power from a

portthatgeneratesadisconnecteventifdisconnectdetec-

tion is enabled. The host controller may also command

the port to remove power at any time.

The LTC4274 can operate in one of four modes: manual,

semi-auto, AUTO pin, or shutdown.

Table 1. Operating Modes

AUTOMATIC

AUTO

PIN OPMD

DETECT/

CLASS

I

/I

CUT LIM

MODE

POWER-UP ASSIGNMENT

Reset and the AUTO/MID Pins

AUTO Pin

1

11b

Enabled at Automatically

Reset

Yes

The initial LTC4274 configuration depends on the state

of the AUTO and MID pins during reset. Reset occurs at

power-up, or whenever the RESET pin is pulled low or

the global Reset All bit is set. Changing the state of AUTO

or MID after power-up will not properly change the port

behavior of the LTC4274 until a reset occurs.

Reserved

Semi-auto

0

11b

10b

N/A

No

Host

Enabled

Upon

Request

Manual

0

01b Once Upon

Request

Upon

Request

No

Shutdown

00b

Disabled

Althoughtypicallyusedwithahostcontroller,theLTC4274

can also be used in a standalone mode with no connec-

tion to the serial interface. If there is no host present,

the AUTO pin must be tied high so that, at reset, the port

will be configured to operate automatically. The port will

detect and classify repeatedly until a PD is discovered,

•ꢀ Inmanualmode,theportwaitsforinstructionsfromthe

host system before taking any action. It runs a single

detection or classification cycle when commanded to

by the host, and reports the result in its Port Status

register. The host system can command the port to

turn on or off the power at any time. This mode should

only be used for diagnostic and test purposes.

set I

and I

according to the classification results,

CUT

LIM

applypoweraftersuccessfuldetection,andremovepower

when a PD is disconnected. Similarly, if the standalone

application is a midspan, the MID pin must be tied high

to enable correct midspan detection timing.

•ꢀ In semi-auto mode, the port repeatedly attempts to

detect and classify any PD attached to it. It reports the

status of these attempts back to the host, and waits for

a command from the host before turning on power to

theport.Thehostmustenabledetection(andoptionally

classification) for the port before detection will start.

Table 2 shows the I

and I

values that will be

CUT

LIM

automatically set in AUTO pin mode, based on the dis-

covered class.

Table 2. I_CUTand I_LIMValues in AUTO Pin Mode

CLASS

I

LIM

CUT

•ꢀ AUTO pin mode operates the same as semi-auto mode

Class 1

112mA

206mA

375mA

638mA

425mA

850mA

except that it will automatically turn on the power to the

Class 2

port if detection is successful. In AUTO pin mode, I

CUT

Class 3 or Class 0

Class 4

and I values are set automatically by the LTC4274.

LIM

This operational mode is only valid if the AUTO pin

is high at reset or power-up and remains high during

operation.

The automatic setting of the I

occurs if the LTC4274 is reset with the AUTO pin high.

and I

values only

CUT

LIM

•ꢀ In shutdown mode, the port is disabled and will not

detect or power a PD.

4274ff

16

For more information www.linear.com/LTC4274

LTC4274

ApplicAtions inForMAtion

DETECTION

and short circuits, are also reported. If the port measures

less than 1V at the first forced-current test, the detection

cycle will abort and Short Circuit will be reported. Table 3

shows the possible detection results.

Detection Overview

Toavoiddamagingnetworkdevicesthatwerenotdesigned

to tolerate DC voltage, a PSE must determine whether the

connected device is a real PD before applying power. The

IEEEspecificationrequiresthatavalidPDhaveacommon-

mode resistance of 25k 5% at any port voltage below

10V. The PSE must accept resistances that fall between

19k and 26.5k, and it must reject resistances above 33k

or below 15k (shaded regions in Figure 11). The PSE may

choose to accept or reject resistances in the undefined

areasbetweenthemust-acceptandmust-rejectranges. In

particular,thePSEmustrejectstandardcomputernetwork

ports, manyofwhichhave150Ωcommon-modetermina-

tion resistors that will be damaged if power is applied to

them (the black region at the left of Figure 11).

Table 3. Detection Status

MEASURED PD SIGNATURE

Incomplete or Not Yet Tested

<2.4k

DETECTION RESULT

Detect Status Unknown

Short Circuit

Capacitance > 2.7µF

C

too High

too Low

PD

2.4k < R < 17k

R

SIG

PD

17k < R < 29k

Detect Good

R too High

SIG

PD

>29k

>50k

Open Circuit

Voltage > 10V

Port Voltage Outside Detect Range

Operating Modes

The port’s operating mode determines when the LTC4274

runs a detection cycle. In manual mode, the port will

idle until the host orders a detect cycle. It will then run

detection, report the results, and return to idle to wait for

another command.

RESISTANCE 0Ω

10k

20k

30k

150Ω (NIC)

23.75k

26.25k

26.5k

PD

PSE

15k 19k

33k

4274 F11

In semi-auto mode, the LTC4274 autonomously polls the

port for PDs, but it will not apply power until commanded

to do so by the host. The Port Status register is updated

at the end of each detection cycle. If a valid signature

resistance is detected and classification is enabled, the

port will classify the PD and report that result as well.

Figure 11. IEEE 802.3af Signature Resistance Ranges

4-Point Detection

The LTC4274 uses a 4-point detection method to discover

PDs. False-positive detections are minimized by check-

ing for signature resistance with both forced-current and

forced-voltage measurements. Initially, two test currents

are forced onto the port (via the OUT pin) and the resulting

voltages are measured. The detection circuitry subtracts

the two V-I points to determine the resistive slope while

removing offset caused by series diodes or leakage at

the port (see Figure 12). If the forced-current detection

yields a valid signature resistance, two test voltages are

then forced onto the port and the resulting currents are

measuredandsubtracted.Bothmethodsmustreportvalid

resistances for the port to report a valid detection. PD

signature resistances between 17k and 29k (typically) are

detected as valid and reported as Detect Good in the Port

Status register. Values outside this range, including open

275

FIRST

DETECTION

POINT

25kΩ SLOPE

165

SECOND

DETECTION

POINT

VALID PD

0V-2V

OFFSET

VOLTAGE

4274 F12

Figure 12. PD Detection

4274ff

17

For more information www.linear.com/LTC4274

LTC4274

ApplicAtions inForMAtion

The port will then wait for at least 100ms (or 2 seconds if

midspan mode is enabled), and will repeat the detection

cycle to ensure that the data in the Port Status register

is up-to-date.

CLASSIFICATION

802.3af Classification

A PD can optionally present a classification signature to

the PSE to indicate the maximum power it will draw while

operating. The IEEE specification defines this signature as

aconstantcurrentdrawwhenthePSEportvoltageisinthe

If the port is in semi-auto mode and high power opera-

tion is enabled, the port will not turn on in response to

a power-on command unless the current detect result is

V

range(between15.5Vand20.5V), withthecurrent

detect good. Any other detect result will generate a t

CLASS

START

level indicating one of 5 possible PD classes. Figure 13

shows a typical PD load line, starting with the slope of the

25kΩ signature resistor below 10V, then transitioning to

the classification signature current (in this case, Class 3)

fault if a power-on command is received. If the port is not

in high power mode, it will ignore the detection result and

apply power when commanded, maintaining backwards

compatibility with the LTC4259A.

in the V

range. Table 4 shows the possible clas-

CLASS

sification values.

Behavior in AUTO pin mode is similar to semi-auto; how-

ever,afterDetectGoodisreportedandtheportisclassified

(if classification is enabled), it is automatically powered

on without further intervention. In standalone (AUTO pin)

Table 4. Classification Values

CLASS

Class 0

Class 1

Class 2

Class 3

Class 4

RESULT

mode, the I

and I thresholds are automatically set;

No Class Signature Present; Treat Like Class 3

CUT

LIM

see the Reset and the AUTO/MID Pins section for more

3W

information.

7W

13W

The signature detection circuitry is disabled when the

port is initially powered up with the AUTO pin low, in

shutdown mode, or when the corresponding Detect

Enable bit is cleared.

25.5W (Type 2)

If classification is enabled, the port will classify the PD

immediatelyafterasuccessfuldetectioncycleinsemi-auto

or AUTO pin modes, or when commanded to in manual

mode. It measures the PD classification signature by ap-

plying 18V for 12ms (both values typical) to the port via

Detection of Legacy PDs

Proprietary PDs that predate the original IEEE 802.3af

standard are commonly referred to today as legacy de-

vices. One type of legacy PD uses a large common-mode

capacitance (>10μF) as the detection signature. Note that

PDs in this range of capacitance are defined as invalid, so

a PSE that detects legacy PDs is technically noncompliant

with the IEEE spec.

60

PSE LOAD LINE

OVER

CURRENT

50

40

30

20

10

0

48mA

CLASS 4

CLASS 3

33mA

23mA

The LTC4274 can be configured to detect this type of

legacy PD. Legacy detection is disabled by default, but

can be manually enabled. When enabled, the port will

report Detect Good when it sees either a valid IEEE PD or

ahigh-capacitancelegacyPD. Withlegacymodedisabled,

only valid IEEE PDs will be recognized.

CLASS 2

TYPICAL

CLASS 3

PD LOAD

LINE

14.5mA

6.5mA

CLASS 1

CLASS 0

0

5

10

15

20

25

VOLTAGE (V

)

CLASS

4274 F13

Figure 13. PD Classification

4274ff

18

For more information www.linear.com/LTC4274

LTC4274

ApplicAtions inForMAtion

the OUT pin and measuring the resulting current; it then

reports the discovered class in the Port Status register. If

the LTC4274 is in AUTO pin mode, it will additionally use

returns Class 0 to 3, the port assumes it is connected to a

Type1 PDanddoesnotrunthesecondclassificationcycle.

Invalid Type 2 Class Combinations

the classification result to set the I and I thresholds.

CUT

LIM

See the Reset and the AUTO/MID Pin section for more

The 802.3at spec defines a Type 2 PD class signature as

two consecutive Class 4 results; a Class 4 followed by a

Class 0-3 is not a valid signature. In AUTO pin mode, the

LTC4274 will power a detected PD regardless of the clas-

sification results, with one exception: if the PD presents

an invalid Type 2 signature (Class 4 followed by Class 0

to 3), the LTC4274 will not provide power and will restart

the detection process. To aid in diagnosis, the Port Status

registerwillalwaysreporttheresultsofthelastclasspulse,

so an invalid Class 4–Class 2 combination would report

a second class pulse was run in the High Power Status

register (which implies that the first cycle found Class 4),

and Class 2 in the Port Status register.

information.

The classification circuitry is disabled when the port is

initially powered up with the AUTO pin low, in shutdown

mode, or when the corresponding Class Enable bit is

cleared.

802.3at 2-Event Classification

The 802.3at spec defines two methods of classifying a

Type 2 PD.

One method adds extra fields to the Ethernet LLDP data

protocol; although the LTC4274 is compatible with this

classification method, it cannot perform classification

directly since it doesn’t have access to the data path.

LLDP classification requires the PSE to power the PD as

a standard 802.3af (Type 1) device. It then waits for the

host to perform LLDP communication with the PD and

update the PSE port data. The LTC4274 supports chang-

POWER CONTROL

External MOSFET, Sense R Summary

The primary function of the LTC4274 is to control the

delivery of power to the PSE port. It does this by control-

ling the gate drive voltage of an external power MOSFET

while monitoring the current via an external sense resis-

tor and the output voltage at the OUT pin. This circuitry

ing the I

and I

levels on the fly, allowing the host

LIM

CUT

to complete LLDP classification.

The second 802.3at classification method, known as

2-event classification or ping-pong, is fully supported by

the LTC4274. A Type 2 PD that is requesting more than

13WwillindicateClass4duringnormal802.3afclassifica-

tion. If the LTC4274 sees Class 4, it forces the port to a

specified lower voltage (called the mark voltage, typically

9V), pauses briefly, and then re-runs classification to

verify the Class 4 reading (Figure 1). It also sets a bit in

the High Power Status register to indicate that it ran the

second classification cycle. The second cycle alerts the

PD that it is connected to a Type 2 PSE which can supply

Type 2 power levels.

serves to couple the raw V input supply to the port in

EE

a controlled manner that satisfies the PD’s power needs

while minimizing power dissipation in the MOSFET and

disturbances on the V backplane.

EE

The LTC4274 is designed to use 0.25Ω sense resistors to

minimize power dissipation. It also supports 0.5Ω sense

resistors, which are the default when LTC4258/LTC4259A

compatibility is desired.

Inrush Control

Once the command has been given to turn on the port,

the LTC4274 ramps up the GATE pin of the port’s external

MOSFET in a controlled manner. Under normal power-up

circumstances, the MOSFET gate will rise until the port

2-event ping-pong classification is enabled by setting a

bit in the port’s High Power Mode register. Note that a

ping-pongenabledportonlyrunsthesecondclassification

cycle when it detects a Class 4 device; if the first cycle

4274ff

19

For more information www.linear.com/LTC4274

LTC4274

ApplicAtions inForMAtion

current reaches the inrush current limit level (typically

450mA), at which point the GATE pin will be servoed to

compliance, I should kept at 425mA for all Type 1 PDs,

LIM

and 850mA if a Type 2 PD is detected. I is automatically

LIM

maintain the specified I

current. During this inrush

reset to 425mA when a port turns off.

INRUSH

period, a timer (t

) runs. When output charging is

START

Table 5. Example Current Limit Settings

INTERNAL REGISTER SETTING (hex)

complete, the port current will fall and the GATE pin will

be allowed to continue rising to fully enhance the MOSFET

I

(mA)

R

SENSE

= 0.5Ω

R

SENSE

= 0.25Ω

LIM

and minimize its on-resistance. The final V is nominally

GS

53

88

12V. If the t

timer expires before the inrush period

START

106

159

213

266

319

372

08

89

80

8A

09

8B

88

completes, the port will be turned back off and a t

fault reported.

START

08

89

Current Limit

TheLTC4274portincludestwocurrentlimitingthresholds

(I and I ), each with a corresponding timer (t

CUT

LIM

425

478

00

8E

92

CB

10

D2

40

4A

50

5A

60

52

80

and t ). Setting the I

and I

thresholds depends

LIM

CUT

LIM

on several factors: the class of the PD, the voltage of the

531

8A

main supply (V ), the type of PSE (1 or 2), the sense

EE

584

resistor (0.5Ω or 0.25Ω), the SOA of the MOSFET, and

whether or not the system is required to implement class

enforcement.

638

90

9A

C0

CA

D0

DA

E0

49

40

4A

50

5A

60

52

744

850

Per the IEEE spec, the LTC4274 will allow the port cur-

956

rent to exceed I

for a limited period of time before

CUT

1063

1169

1275

1488

1700

1913

2125

2338

2550

2975

removing power from the port, whereas it will actively

control the MOSFET gate drive to keep the port current

below I . The port does not take any action to limit the

LIM

current when only the I

does start the t

threshold is exceeded and current limit is active. If

the current drops below the I

its timer expires, the t

threshold is exceeded, but

LIM

CUT

timer. The t

timer starts when the

CUT

I

LIM

current threshold before

CUT

timer counts back down, but

CUT

at 1/16 the rate that it counts up. This allows the current

limit circuitry to tolerate intermittent overload signals with

duty cycles below about 6%; longer duty cycle overloads

will turn the port off.

I

Foldback

LIM

I

is typically set to a lower value than I to allow the

LIM

The LTC4274 features a two-stage foldback circuit that

reduces the port current if the port voltage falls below

the normal operating voltage. This keeps MOSFET power

dissipation at safe levels for typical 802.3af MOSFETs,

CUT

port to tolerate minor faults without current limiting.

Per the IEEE specification, the LTC4274 will automatically

set I

to 425mA (shown in bold in Table 5) during in-

LIM

rush at port turn-on, and then switch to the programmed

setting once inrush has completed. To maintain IEEE

I

LIM

4274ff

20

For more information www.linear.com/LTC4274

LTC4274

ApplicAtions inForMAtion

even at extended 802.3at power levels. Current limit and

foldback behavior are programmable. Figure 14 shows

MOSFET power dissipation with 802.3af-style foldback

compared with a typical MOSFET SOA curve; Figure 15

demonstrates how two-stage foldback keeps the FET

within its SOA under the same conditions. Table 5 gives

MOSFET Fault Detection

The LTC4274 PSE port is designed to tolerate significant

levels of abuse, but in extreme cases it is possible for the

external MOSFET to be damaged. A failed MOSFET may

short source to drain, which will make the port appear to

be on when it should be off; this condition may also cause

the sense resistor to fuse open, turning off the port but

causing the LTC4274 SENSE pin to rise to an abnormally

high voltage. A failed MOSFET may also short from gate

to drain, causing the LTC4274 GATE pin to rise to an ab-

normallyhighvoltage.TheLTC4274SENSEandGATEpins

are designed to tolerate up to 80V faults without damage.

examples of recommended I register settings.

LIM

The LTC4274 will support current levels well beyond the

maximum values in the 802.3at specification. The shaded

areas in Table 5 indicate settings that may require a larger

external MOSFET, additional heat sinking, or a reduced

t

setting.

LIM

If the LTC4274 sees any of these conditions for more than

180μs, it disables all port functionality, reduces the gate

drive pull-down current for the port and reports a FET Bad

fault. This is typically a permanent fault, but the host can

attempt to recover by resetting the port, or by resetting

the entire chip if a port reset fails to clear the fault. If the

MOSFET is in fact bad, the fault will quickly return, and

the port will disable itself again.

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

802.3af FOLDBACK

An open or missing MOSFET will not trigger a FET Bad

fault, but will cause a t

to turn on the port.

fault if the LTC4274 attempts

START

SOA DC AT 90°C

30

0

10

PD Voltage (V) at V

40

= 58V

50

60

20

PSE

4274 F14

Voltage and Current Readback

Figure 14. Turn On Currents vs FET Safe Operating

Area at 90°C Ambient

The LTC4274 measures the output voltage and current

at the port with an internal A/D converter. Port data is

only valid when the port power is on. The converter has

two modes:

1.0

0.9

0.8

0.7

0.6

0.5

0.4

•ꢀ Slow mode: 14 samples per second, 14.5 bits resolution

•ꢀ Fast mode: 440 samples per second, 9.5 bits resolution

In fast mode, the least significant 5 bits of the lower byte

are zeroes so that bit scaling is the same in both modes.

0.3

0.2

0.1

0.0

802.3af FOLDBACK

Disconnect

SOA DC AT 90°C

30

PD Voltage (V) at V

The LTC4274 monitors the port to make sure that the PD

continues to draw the minimum specified current. A dis-

connect timer counts up whenever port current is below

7.5mA(typ),indicatingthatthePDhasbeendisconnected.

0

10

40

= 58V

50

60

20

PSE

4274 F15

Figure 15. LTC4274 Foldback vs FET Safe Operating

Area at 90°C Ambient

If the t timer expires, the port will be turned off and

DIS

the disconnect bit in the fault event register will be set.

If the current returns before the t timer runs out, the

DIS

4274ff

21

For more information www.linear.com/LTC4274

LTC4274

ApplicAtions inForMAtion

timer resets and will start counting from the beginning

if the undercurrent condition returns. As long as the PD

exceeds the minimum current level more often than t

it will stay powered.

the host via the INT pin. The Timing Diagrams (Figures 5

through 9) show typical communication waveforms and

their timing relationships. More information about the

SMBus data protocols can be found at www.smbus.org.

,

DIS

Although not recommended, the DC disconnect feature

can be disabled by clearing the DC Disconnect Enable

bit. Note that this defeats the protection mechanisms

built into the IEEE spec, since a powered port will stay

powered after the PD is removed. If the still-powered port

is subsequently connected to a non-PoE data device, the

device may be damaged.

The LTC4274 requires both the V and V supply rails

DD

EE

to be present for the serial interface to function.

Bus Addressing

The LTC4274’s primary serial bus address is 010xxxxb,

with the lower four bits set by the AD3-AD0 pins; this

allows up to 16 LTC4274s on a single bus. All LTC4274s

also respond to the address 0110000b, allowing the host

to write the same command (typically configuration com-

mands)tomultipleLTC4274sinasingletransaction. Ifthe

LTC4274isassertingtheINTpin, itwillalsorespondtothe

alert response address (0001100b) per the SMBus spec.

TheLTC4274doesnotincludeACdisconnectcircuitry,but

includes an AC disconnect enable bit to maintain compat-

ibility with the LTC4259A. If the AC Disconnect Enable bit

is set, DC disconnect will be used.

Shutdown Pin

Interrupts and SMBAlert

The LTC4274 includes a hardware SHDN pin. When the

SHDN pin is pulled to DGND, the port will be shut off im-

mediately. The port remains shut down until re-enabled

Most LTC4274 port events can be configured to trigger

an interrupt, asserting the INT pin and alerting the host

to the event. This removes the need for the host to poll

the LTC4274, minimizing serial bus traffic and conserving

host CPU cycles. Multiple LTC4274s can share a common

INT line, with the host using the SMBAlert protocol (ARA)

to determine which LTC4274 caused an interrupt.

2

via I C or a device reset in AUTO pin mode.

Masked Shutdown

The LTC4274 provides a low latency port shedding fea-

ture to quickly reduce the system load when required. By

allowing a pre-determined set of ports to be turned off,

the current on an overloaded main power supply can be

reduced rapidly while keeping high priority devices pow-

ered. Each port can be configured to high or low priority;

all low-priority ports will shut down within 6.5μs after the

MSD pin is pulled low. If a port is turned off via MSD, the

correspondingDetectionandClassificationEnablebitsare

cleared, so the port will remain off until the host explicitly

re-enables detection.

Register Description

For information on serial bus usage and device configura-

tion and status, refer to the LTC4274 Software Program-

ming documentation.

EXTERNAL COMPONENT SELECTION

Power Supplies and Bypassing

The LTC4274 requires two supply voltages to operate. V

DD

SERIAL DIGITAL INTERFACE

requires 3.3V (nominally) relative to DGND. V requires

EE

a negative voltage of between –45V and –57V for Type 1

PSEs, or –51V to –57V for Type 2 PSEs, relative to AGND.

The relationship between the two grounds is not fixed;

Overview

TheLTC4274communicateswiththehostusingastandard

2

SMBus/I C 2-wire interface. The LTC4274 is a slave-only

AGND can be referenced to any level from V to DGND,

DD

device, and communicates with the host master using

the standard SMBus protocols. Interrupts are signaled to

although it should typically be tied to either V or DGND.

DD

4274ff

22

For more information www.linear.com/LTC4274

LTC4274

ApplicAtions inForMAtion

V

provides power for most of the internal LTC4274

V

is the main supply that provides power to the PD.

EE

DD

circuitry, and draws a maximum of 3mA. A ceramic de-

Because it supplies a relatively large amount of power and

issubjecttosignificantcurrenttransients,itrequiresmore

design care than a simple logic supply. For minimum IR

coupling cap of at least 0.1μF should be placed from V

to DGND, as close as practical to each LTC4274 chip.

DD

loss and best system efficiency, set V near maximum

EE

Figure16showsathreecomponentlowdropoutregulator

foranegativesupplytoDGNDgeneratedfromthenegative

amplitude (57V), leaving enough margin to account for

transient over- or undershoot, temperature drift, and the

line regulation specs of the particular power supply used.

V

supply. V is tied to AGND and DGND is negative

EE

DD

referencedtoAGND.ThisregulatordrivesasingleLTC4274

device. In Figure 17, DGND is tied to AGND in this boost

Bypass capacitance between AGND and V is very impor-

EE

converter circuit for a positive V supply of 3.3V above

tant for reliable operation. If a short circuit occurs at the

output port it can take as long as 1μs for the LTC4274 to

begin regulating the current. During this time the current

is limited only by the small impedances in the circuit and

a high current spike typically occurs, causing a voltage

DD

AGND. This circuit can drive multiple LTC4274 devices

and opto couplers.

10Ω

transient on the V supply and possibly causing the

EE

AGND

V

DD

LTC4274 to reset due to a UVLO fault. A 1μF, 100V X7R

1µF

100V

CMHZ4687-4.3V

0.1µF

LTC4274

DGND

capacitor placed near the V pin is recommended to

EE

minimize spurious resets.

CMPTA92

SMAJ58A

V

EE

Isolating the Serial Bus

750k

4274 F16

V

The LTC4274 includes a split SDA pin (SDAIN and SD-

AOUT) to ease opto-isolation of the bidirectional SDA line.

EE

Figure 16. Negative LDO to DGND

IEEE 802.3 Ethernet specifications require that network

segments (including PoE circuitry) be electrically isolated

from the chassis ground of each network interface de-

vice. However, network segments are not required to be

L3

L4

D28

B1100

100µH

10µH

SUMIDA CDRH5D28-101NC

SUMIDA CDRH4D28-100NC

3.3V AT 400mA

C74

100µF

6.3V

C73

10µF

6.3V

C75

R51

4.7k

1%

R53

R52

3.32k

1%

10µF

4.7k

16V

1%

C76

10µF

100V

C78

0.22µF

100V

+

5

Q13

Q14

FMMT723

C77

0.22µF

100V

V

FMMT723

CC

1

3

6

Q15

ITH/RUN

NGATE

SENSE

FDC2512

R58

10Ω

LTC3803

R54

56k

4

R55

806Ω

1%

R56

47.5k

1%

V

FB

R57

1k

R59

0.100Ω

1%, 1W

C79

2200pF

GND

2

R60

10Ω

V

EE

4274 F17

Figure 17. Positive V_DDBoost Converter

4274ff

23

For more information www.linear.com/LTC4274

LTC4274

ApplicAtions inForMAtion

0.1µF

2k

U2

200Ω

V

DD

CPU

SCL

U1

10Ω

LTC4274

V

INT

SCL

DD

200Ω

SDAIN

SDAOUT

AD0

AD1

AD2

2

I C

SDA

ADDRESS

0100001

HCPL-063L

0.1µF

TO

SMAJ5.0A

AD3

CONTROLLER

U3

DGND

AGND

200Ω

10Ω

V

EE

1µF

100V

4274 F18

SMAJ58A

SMBALERT

0.1µF

GND CPU

HCPL-063L

U1: FAIRCHILD NC7WZ17

U2, U3: AGILENT HCPL-063L

ISOLATED

3.3V

+

10µF

ISOLATED

GND

+

TVS

C

BULK

ISOLATED

–54V

Figure 18. Opto-Isolating the I²C Bus

isolated from each other, provided that the segments are

connected to devices residing within a single building on

a single power distribution system.

shows a typical isolated serial interface. The SDAOUT pin

of the LTC4274 is designed to drive the inputs of an opto-

2

coupler directly. Standard I C/SMBus devices typically

cannot drive opto-couplers, so U1 is used to buffer the

signals from the host controller side.

For simple devices such as small PoE switches, the isola-

tion requirement can be met by using an isolated main

power supply for the entire device. This strategy can be

used if the device has no electrically conducting ports

other than twisted-pair Ethernet. In this case, the SDAIN

and SDAOUT pins can be tied together and will act as a

External MOSFET

CarefulselectionofthepowerMOSFETiscriticaltosystem

reliability. LTC recommends either Fairchild IRFM120A,

FDT3612, FDMC3612 or Philips PHT6NQ10T for their

proven reliability in Type 1 and Type 2 PSE applications.

Non-standard applications that provide more current than

the 850mA IEEE maximum may require heat sinking and

other MOSFET design considerations. Contact LTC Ap-

plications before using a MOSFET other than one of these

recommended parts.

2

standard I C/SMBus SDA pin.

If the device is part of a larger system, contains additional

external non-Ethernet ports, or must be referenced to

protective ground for some other reason, the Power over

Ethernet subsystem (including all LTC4274s) must be

electrically isolated from the rest of the system. Figure 18

4274ff

24

For more information www.linear.com/LTC4274

LTC4274

ApplicAtions inForMAtion

Sense Resistor

Each LTC4274 requires a 10Ω, 0805 resistor (R1) in series

from supply AGND to the LTC4274 AGND pin. Across the

TheLTC4274isdesignedtouseeither0.5Ωor0.25Ωcurrent

sense resistors. For new designs 0.25Ω is recommended to

reduce power dissipation; the 0.5Ω option is intended for

existing systems where the LTC4274 is used as a drop-in

replacementfortheLTC4258orLTC4259A.Thelowersense

resistorvaluesreduceheatdissipation.Fourcommonlyavail-

able 1Ω resistors (0402 or larger package size) can be used

inparallelinplaceofasingle0.25Ωresistor.Inordertomeet

LTC4274 AGND pin and V pin are an SMAJ58A, 58V

EE

TVS (D1) and a 1μF, 100V bypass capacitor (C1). These

components must be placed close to the LTC4274 pins.

If the V supply is above AGND, each LTC4274 requires

DD

a 10Ω, 0805 resistor (R2) in series from the +3.3V supply

positive rail to the LTC4274 V pin. Across the LTC4274

DD

V

DD

pin and DGND pin are an SMAJ5.0A, 5.0V TVS (D2)

theI andI accuracyrequiredbytheIEEEspecification,

and a 0.1μF capacitor (C2). These components must be

placed close to the LTC4274 pins. DGND is tied directly to

the protected AGND pin. Pull-ups at the logic pins should

CUT

LIM

thesenseresistorsshouldhave 1%toleranceorbetter,and

no more than 200ppm/°C temperature coefficient.

be to the protected side of the 10Ω resistors at the V

DD

Output Cap

pin. Pull-downs at the logic pins should be to the protected

side of the 10Ω resistors at the tied AGND and DGND pins.

The port requires a 0.22μF cap across its output to keep

the LTC4274 stable while in current limit during startup or

overload. Common ceramic capacitors often have significant

voltage coefficients;this means the capacitance is reduced as

the applied voltage increases. To minimize this problem, X7R

ceramic capacitors rated for at least 100V are recommended.

Finally, each port requires a pair of S1B clamp diodes,

one from OUTn to supply AGND (D3) and one from OUTn

to supply V (D4). The diodes at the ports steer harmful

EE

surges into the supply rails where they are absorbed by the

surge suppressors and the V bypass capacitance. The

EE

layout of these paths must be low impedance.

Surge Protection

Further considerations include LTC4274 applications with

off-board connections, such as a daughter card to a mother

boardorheaderstoanexternalsupplyorhostcontrolboard.

Additional protection may be required at the LTC4274 pins

to these off-board connections.

Ethernet ports can be subject to significant cable surge

events. To keep PoE voltages below a safe level and protect

theapplicationagainstdamage, protectioncomponents, as

shown in Figure 19, are required at the main supply, at the

LTC4274 pins, and at each port.

Bulk transient voltage suppression (TVS

) and bulk ca-

LAYOUT GUIDELINES

BULK

pacitance (C

) are required across the main PoE supply

BULK

Standard power layout guidelines apply to the LTC4274:

and should be sized to accommodate system level surge

place the decoupling caps for the V and V supplies

DD

EE

requirements. A large capacitance of 10μF or greater (C3)

near their respective supply pins, use ground planes, and

is required across the +3.3V supply if V is above AGND.

DD

use wide traces wherever there are significant currents.

R2

10Ω

V

+3.3V

DD

C2

0.1µF

D2

AUTO

SCL

SMAJ5.0A

+

SDAIN

DGND

AGND

LTC4274

R1

C3

TO PORT

OUTn

10Ω

10µF

V

EE

SENSE GATE OUT

TVS

C

BULK

D1

OUT

0.22μF

100V

X7R

1µF

D3

S1B

C

BULK

100V

X7R

SMAJ58A

R

S

–54V

Q1

D4 S1B

4274 F19

Figure 19. LTC4274 Surge Protection

4274ff

25

For more information www.linear.com/LTC4274

LTC4274

pAckAge Description

Please refer to http://www.linear.com/product/LTC4274#packaging for the most recent package drawings.

UHF Package

38-Lead Plastic QFN (5mm × 7mm)

(Reference LTC DWG # 05-08-1701 Rev C)

0.70 ± 0.05

5.50 ± 0.05

5.15 0.05

4.10 ± 0.05

3.15 0.05

3.00 REF

PACKAGE

OUTLINE

0.25 ± 0.05

0.50 BSC

5.5 REF

6.10 ± 0.05

7.50 ± 0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

R = 0.30 TYP OR

0.35 × 45° CHAMFER

0.75 ± 0.05

3.00 REF

5.00 ± 0.10

37

38

0.00 – 0.05

0.40 ±0.10

PIN 1

TOP MARK

1

2

(SEE NOTE 6)

5.15 0.10

5.50 REF

7.00 ± 0.10

3.15 0.10

(UH) QFN REF C 1107

0.200 REF 0.25 ± 0.05

R = 0.125

TYP

R = 0.10

TYP

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE

OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4274ff

26

For more information www.linear.com/LTC4274

LTC4274

revision history

REV

DATE

4/11

6/11

DESCRIPTION

PAGE NUMBER

A

Revised entire data sheet.

1 to 28

B

Added separate t entry and revised t

and t entries in the Electrical Characteristics section.

5

LIM

CUT

DIS

Revised curves G17, G19 and G21 in the Typical Performance Characteristics section.

Revised the AUTO pin description in the Pin Functions section.

9

13

Minor text edits in the Operating Modes, Current Limit, I Foldback and MOSFET Fault Detection sections of the

18, 20, 21

LIM

Applications Information section.

Replaced Figure 16.

23

28

3

Replaced the Typical Application and revised the Related Parts.

Changed “–48 Supply Voltage” to “Main PoE Supply Voltage.”

C

9/11

Changed GATE typ voltage to 12V.

3, 12, 20

Revised V text under Digital Interface.

4

7

ILD

Added (mA) to Class Compliance axis title.

Figure number reference corrected.

18

22

28

4

Revised power supply voltage figures under Power Supplies and Bypassing.

Specified SMAJ58A for Zener diode.

2

D

E

01/12 Revised MAX value for V I C input low voltage

ILD

Clarified AUTO Pin mode relationship to Reset pin

07/15 Updated surge protection recommendations

16

1, 23, 24, 25, 28

Simplified Power over Ethernet system diagram

14

Added component value (Figure 17)

07/17 Revised Figures 16 and 19

23

23, 25

F

4274ff

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconne tion its cinir its a scrib re ll no nfri ge n existing patent rights.

27

For more formation www.linear.com/LTC4274

c of cu s de ed he in wi t i n o

LTC4274

typicAl ApplicAtion

One Complete Isolated Powered Ethernet Port

ISOLATED

3.3V

10Ω

+

10µF

0.1µF

SMAJ5.0A

2k

V

DD

DGND

SCL

U2

SDAIN

SDAOUT

INT

200Ω

V

CPU

LTC4274

DD

U1

10Ω

AGND

SCL

FB1

FB2

V

SENSE GATE OUT

EE

2k

0.22µF

100V

X7R

200Ω

TVS

BULK

1µF

S1B

+

100V

X7R

C

BULK

R

SENSE

0.25Ω

SMAJ58A

SDA

Q1

HCPL-063L

ISOLATED

–54V

S1B

U3

RJ45

200Ω

CONNECTOR

T1

1

2

•

0.01µF

200V

0.01µF

200V

3

4

5

6

7

8

75Ω

INTERRUPT

PHY

0.1µF

GND CPU

(NETWORK

PHYSICAL

LAYER

HCPL-063L

CHIP)

•

0.01µF

200V

0.01µF

200V

75Ω

Q1: FAIRCHILD IRFM120A OR PHILIPS PHT6NQ10T

U1: FAIRCHILD NC7WZ17

U2, U3: AGILENT HCPL-063L

FB1, FB2: TDK MPZ2012S601A

T1: PULSE H6096NL OR COILCRAFT ETH1-230LD

4274 TA02

1000pF

2000V

relAteD pArts

PART NUMBER

LT1619

DESCRIPTION

COMMENTS

–48V to 3.3V at 300mA, MSOP Package

100V, 1A Internal Switch, 2-Event Classification Recognition

Low Voltage Current Mode PWM Controller

IEEE 802.3at PD Interface Controller

IEEE 802.3at Quad PSE Controller

LTC4265

LTC4266

Supports IEEE 802.3at Type 1 and 2 PDs, 0.34Ω Channel Resistance, Advanced Power

Management, High-Reliability 4-Point PD Detection, Legacy Capacitance Detect

LTC4267

IEEE 802.3af PD Interface Console with

Integrated Switching Regulator

Internal 100V, 400mA Switch, Dual Inrush Current, Programmable Class

LTC4269-1

LTC4269-2

LTC4278

IEEE 802.3at PD Interface Console with

Integrated Switching Regulator

2-Event Classification, Programmable Classification, Synchronous No-Opto Flyback

Controller, 50kHz to 250kHz, Auxiliary Support

IEEE 802.3at PD Interface Console with

Integrated Switching Regulator

2-Event Classification, Programmable Classification, Synchronous Forward Controller,

100kHz to 500kHz, Auxiliary Support

IEEE 802.3at PD Interface with Integrated

Switching Regulator

2-Event Classification, Programmable Classification, Synchronous No-Opto Flyback

Controller, 50kHz to 250kHz, 12V Auxiliary Support

+

++

LTC4270/

LTC4271

12-Port PoE/PoE /LTPoE ™ PSE Controller Transformer Isolation, Supports Type 1, Type 2 and LTPoE PDs

4274ff

LT 0717 REV F • PRINTED IN USA

www.linear.com/LTC4274

28

For more information www.linear.com/LTC4274


型号：	LTC4274IUHF#PBF
厂家：	Linear
描述：	LTC4274 - Single IEEE 802.3at Power Over Ethernet Controller; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C
文件：	总28页 (文件大小：388K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC4274IUHF#PBF [Linear]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E