LTC4274_1 [Linear]
Single PoE+ PSE Controller High Capacitance Legacy Device Detection; 单一的PoE + PSE控制器，高电容老式设备检测
| 型号： | LTC4274_1 |
| 厂家： | 
Linear |
| 描述： | Single PoE+ PSE Controller High Capacitance Legacy Device Detection |
| 文件： | 总28页 (文件大小：662K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4274
Single PoE+ PSE Controller
FEATURES
DESCRIPTION
n
Compliant with IEEE 802.3at Type 1 and 2
The LTC®4274 is a single power sourcing equipment con-
troller designed for use in IEEE 802.3 Type 1 and Type 2
(high power) compliant Power over Ethernet systems.
External power MOSFETs enhance system reliability and
minimizechannelresistance,cuttingpowerdissipationand
eliminating the need for heatsinks even at Type 2 power
levels. External power components also allow use at very
high power levels while remaining otherwise compatible
withtheIEEEstandard. 80V-ratedportpinsproviderobust
protection against external faults.
n
0.34Ω Total Channel Resistance
130mW/Port at 600mA
n
Advanced Power Management
8-Bit Programmable Current Limit (I
)
LIM
7-Bit Programmable Overload Currents (I
)
CUT
Fast Shutdown
14.5-Bit Port Current/Voltage Monitoring
2-Event Classification
n
Very High Reliability 4-Point PD Detection:
2-Point Forced Voltage
The LTC4274 includes advanced power management
features, including current and voltage readback and pro-
2-Point Forced Current
n
n
n
n
n
n
High Capacitance Legacy Device Detection
LTC4259A-1 and LTC4266 SW Compatible
grammable I
and I thresholds. Available C libraries
CUT
LIM
simplifysoftwaredevelopment;anoptionalAUTOpinmode
provides fully IEEE-compliant standalone operation with
no software required. Proprietary 4-point PD detection
circuitry minimizes false PD detection while supporting
legacy phone operation. Midspan operation is supported
with built-in 2-event classification and backoff timing.
2
1MHz I C Compatible Serial Control Interface
Midspan Backoff Timer
Supports Proprietary Power Levels Above 25W
Available in 38-Pin 5mm × 7mm QFN Package
2
APPLICATIONS
Host communication is via a 1MHz I C serial interface.
n
PSE Switches/Routers
PSE Midspans
The LTC4274 is available in a 5mm × 7mm QFN package
that significantly reduces board space compared with
competing solutions.
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
TYPICAL APPLICATION
Complete Ethernet High Power Source
3.3V 0.1μF
SCL
INT
SHDN
V
DD
SDAIN
SDAOUT
AD0
AUTO
MSD
LTC4274
RESET
MID
AD1
AD2
AD3
DGND AGND
V
SENSE GATE OUT
EE
0.22μF
100V
1μF
100V
S1B
S1B
SMAJ58A
–54V
PORT
4274 TA01
–54V
4274fa
1
LTC4274
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (Note 1)
Operating Temperature Range
AGND – V ........................................... –0.3V to 80V
LTC4274C ................................................ 0°C to 70°C
LTC4274I..............................................–40°C to 85°C
Junction Temperature (Note 2) ............................. 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
EE
DGND – V ............................................... –0.3V to 80V
EE
V
– DGND.............................................. –0.3V to 5.5V
Digital Pins
DD
SCL, SDAIN, SDAOUT, INT, SHDN, MSD, ADn,
RESET, AUTO, MID........... DGND –0.3V to V + 0.3V
DD
Analog Pins
GATE, SENSE, OUT................ V –0.3V to V + 80V
EE
EE
PIN CONFIGURATION
TOP VIEW
38 37 36 35 34 33 32
SDAOUT
NC
1
2
3
4
5
6
7
8
9
31 GATE
30 SENSE
SDAIN
AD3
NC
NC
29
28
27
26
25
AD2
V
EE
V
EE
V
EE
V
AD1
EE
39
AD0
DNC
NC
24 NC
23 NC
DGND 10
NC 11
22
21 NC
20
V
EE
NC 12
NC
13 14 15 16 17 18 19
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
EXPOSED PAD IS V (PIN 39) MUST BE SOLDERED TO PCB
EE
JMAX
T
= 125°C, V = 34°C/W
JA
ORDER INFORMATION
LEAD FREE FINISH
LTC4274CUHF#PBF
LTC4274IUHF#PBF
TAPE AND REEL
PART MARKING*
4274
4274
PACKAGE DESCRIPTION
38-Lead (5mm × 7mm) Plastic QFN
38-Lead (5mm × 7mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
LTC4274CUHF#TRPBF
LTC4274IUHF#TRPBF
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4274fa
2
LTC4274
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless
otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
–48V Supply Voltage
AGND – V
EE
l
l
For IEEE Type 1 Complaint Output
For IEEE Type 2 Complaint Output
45
51
57
57
V
V
l
l
l
l
l
l
Undervoltage Lock-out Level
20
25
3.3
2.2
30
V
V
V
V
Supply Voltage
V – DGND
DD
3.0
4.3
DD
DD
Undervoltage Lock-out
V
Allowable Digital Ground Offset
DGND – V
25
57
–5
3
V
EE
I
I
V
V
Supply Current
Supply Current
(AGND – V ) = 55V
–2.4
1.1
mA
mA
EE
EE
EE
(V – DGND) = 3.3V
DD
DD
DD
Detection
l
l
Detection Current – Force Current
Detection Voltage – Force Voltage
First Point, AGND – V
= 9V
OUT
220
140
240
160
260
180
μA
μA
OUT
Second Point, AGND – V
= 3.5V
AGND – V , 5μA ≤ I
≤ 500μA
OUT
OUT
l
l
First Point
7
3
8
4
9
5
V
V
Second Point
l
l
l
l
l
Detection Current Compliance
Detection Voltage Compliance
Detection Voltage Slew Rate
Min. Valid Signature Resistance
Max. Valid Signature Resistance
AGND – V
= 0V
0.8
0.9
12
mA
V
OUT
V
OC
AGND – V , Open Port
10.4
OUT
AGND – V , C
= 0.15μF
0.01
18.5
32
V/μs
kΩ
kΩ
OUT PORT
15.5
27.5
17
29.7
Classification
l
l
V
CLASS
Classification Voltage
AGND – V , 0mA ≤ I ≤ 50mA
CLASS
16.0
53
20.5
67
V
OUT
Classification Current Compliance
Classification Threshold Current
V
OUT
= AGND
61
mA
l
l
l
l
l
Class 0 – 1
5.5
6.5
14.5
23
33
48
7.5
mA
mA
mA
mA
mA
Class 1 – 2
13.5
21.5
31.5
45.2
15.5
24.5
34.9
50.8
Class 2 – 3
Class 3 – 4
Class 4 – Overcurrent
l
l
V
Classification Mark State Voltage
Mark State Current Compliance
AGND – V , 0.1mA ≤ I ≤ 10mA
CLASS
7.5
53
9
10
67
V
MARK
OUT
V
OUT
= AGND
61
mA
Gate Driver
l
l
GATE Pin Pull-Down Current
Port Off, V
Port Off, V
= V + 5V
0.4
mA
mA
GATE
GATE
EE
= V + 1V
0.08
0.12
30
EE
GATE Pin Fast Pull-Down Current
GATE Pin On Voltage
V
V
= V + 5V
mA
V
GATE
GATE
EE
l
– V , I
= 1μA
8
14
EE GATE
Output Voltage Sense
l
l
V
Power Good Threshold Voltage
V
– V
EE
2
2.4
2.8
V
PG
OUT
OUT Pin Pull-Up Resistance to AGND
0V ≤ (AGND – V ) ≤ 5V
300
500
700
kΩ
OUT
4274fa
3
LTC4274
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless
otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Current Sense
l
V
Overcurrent Sense Voltage
V
– V , icut1 = hpen = 00h
180
188
196
mV
CUT
SENSE
EE
hpen = 01h, cut[5:0] ≥ 4 (Note 12)
cutrng = 0
l
l
9
4.5
9.38
4.69
9.75
4.88
mV/LSB
mV/LSB
cutrng = 1
l
l
l
l
Overcurrent Sense in AUTO Pin Mode
Class 0, Class 3
Class 1
90
26
94
28
98
30
mV
mV
mV
mV
Class 2
49
52
55
Class 4
152
159
166
V
LIM
V
LIM
V
LIM
Active Current Limit in 802.3af Compliant
Mode
V
V
– V , dblpwr = hpen = 00h
SENSE EE
= 55V (Note 12)
EE
l
l
V
A
< V
< A – 29V
OUT
204
40
212
220
100
mV
mV
EE
GND
OUT
GND
– V
= 0V
Active Current Limit in High Power Mode
Active Current Limit in AUTO Pin Mode
hpen = 01h, lim1 = C0h, V = 55V
EE
l
l
l
V
V
– V = 0V to 10V
204
100
20
212
106
221
113
50
mV
mV
mV
OUT
EE
EE
+ 23V < V
< AGND – 29V
OUT
AGND – V
= 0V
OUT
V
– V = 0V to 10V, V = 55V
EE EE
OUT
l
l
Class 0 to Class 3
Class 4
102
204
106
212
110
221
mV
mV
l
l
V
V
DC Disconnect Sense Voltage
Short-Circuit Sense
V
V
– V , rdis = 0
2.6
1.3
3.8
1.9
4.8
mV
mV
MIN
SENSE
SENSE
EE
– V , rdis = 1
2.41
EE
l
l
V
SENSE
V
SENSE
– V – V , rdis = 0
160
75
200
100
255
135
mV
mV
SC
EE
LIM
– V – V , rdis = 1
EE
LIM
Port Current ReadBack
Resolution
No missing codes, fast_iv = 0
V – V
SENSE
14
30.5
30
bits
μV/LSB
dB
LSB Weight
EE
50-60Hz Noise Rejection
(Note 7)
Port Voltage ReadBack
Resolution
No missing codes, fast_iv = 0
14
5.835
30
bits
mV/LSB
dB
LSB Weight
AGND – V
(Note 7)
OUT
50-60Hz noise rejection
Digital Interface
l
l
V
Digital Input Low Voltage
Digital Input High Voltage
Digital Output Low Voltage
(Note 6)
(Note 6)
0.8
V
V
ILD
IHD
V
2.2
l
l
I
I
= 3mA, I = 3mA
0.4
0.7
V
V
SDAOUT
SDAOUT
INT
= 5mA, I = 5mA
INT
Internal Pull-Up to V
ADn, SHDN, RESET, MSD
50
50
kΩ
kΩ
DD
Internal Pull-Down to DGND
AUTO, MID
4274fa
4
LTC4274
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless
otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Timing Characteristics
l
l
t
t
Detection Time
Detection Delay
Beginning to End of Detection (Note 7)
270
300
290
310
470
ms
ms
DET
From PD Connected to Port to Detection
Complete (Note 7)
DETDLY
l
l
l
l
l
l
t
t
t
t
t
t
First Class Event Duration
(Note 7)
11
6.8
11
19
12
8.6
12
22
13
10.3
13
ms
ms
ms
ms
ms
ms
CLE1
ME1
CLE2
ME2
CLE3
PON
First Mark Event Duration
(Notes 7, 11)
(Note 7)
Second Class Event Duration
Second Mark Event Duration
Third Class Event Duration
Power On Delay in AUTO Pin Mode
(Note 7)
C
PORT
= 0.6μF (Note 7)
0.1
60
From End of Valid Detect to Application of
Power to Port (Note 7)
l
Turn On Rise Time
(AGND – V ): 10% to 90% of (AGND – V ),
PORT
15
24
μs
OUT
EE
C
= 0.15μF (Note 7)
l
l
l
l
Turn On Ramp Rate
C
= 0.15μF (Note 7)
10
V/μs
PORT
Fault Delay
From I
Fault to Next Detect
1.0
2.3
1.0
1.1
2.5
1.3
s
s
s
CUT
Midspan Mode Detection Backoff
Power Removal Detection Delay
Rport = 15.5kꢀ (Note 7)
2.7
2.5
From Power Removal After t to Next
Detect (Note 7)
DIS
l
l
t
t
Maximum Current Limit Duration During Port
Start-Up
t
= 0, t = 0 (Notes 7, 12)
START0
52
52
62.5
62.5
6.3
66
66
ms
ms
START
START1
, t
Maximum Current Limit Duration After Port
Start-Up
t
= 0, t
= 0 (Notes 7, 12)
ICUT0
LIM ICUT
ICUT1
l
l
Maximum Current Limit Duty Cycle
(Note 7)
5.8
1.6
6.7
3.6
%
t
t
Maintain Power Signature (MPS) Pulse Width Current Pulse Width to Reset Disconnect
Sensitivity
ms
MPS
DIS
Timer (Notes 7, 8)
l
Maintain Power Signature (MPS) Dropout
Time
t
[1:0] = 00b (Notes 5, 12)
320
350
2
380
ms
conf
l
l
l
l
t
t
Masked Shut Down Delay
Port Shut Down Delay
(Note 7)
(Note 7)
6.5
6.5
3
μs
μs
s
MSD
SHDN
2
I C Watchdog Timer Duration
1.5
3
Minimum Pulse Width for Masked Shut
Down
(Note 7)
μs
l
l
Minimum Pulse Width for SHDN
Minimum Pulse Width for RESET
(Note 7)
(Note 7)
3
μs
μs
4.5
4274fa
5
LTC4274
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless
otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C Timing
l
l
l
l
l
Clock Frequency
Bus Free Time
Start Hold Time
SCL Low Time
SCL High Time
Data Hold Time
(Note 7)
1
MHz
ns
t
t
t
t
t
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
480
240
480
240
60
1
2
3
4
5
ns
ns
ns
l
l
Figure 5 (Notes 7, 9) Data into chip
Data out of chip
ns
ns
120
l
l
l
l
l
l
l
l
l
t
t
t
t
t
Data Set-Up Time
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
(Notes 7, 9, 10)
80
ns
ns
ns
ns
ns
ns
μs
μs
ns
6
7
8
r
Start Set-Up Time
240
240
Stop Set-Up Time
SCL, SDAIN Rise Time
SCL, SDAIN Fall Time
Fault Present to INT Pin Low
Stop Condition to INT Pin Low
ARA to INT Pin High Time
SCL Fall to ACK Low
120
60
f
150
1.5
1.5
120
(Notes 7, 9, 10)
(Notes 7, 9)
(Notes 7, 9)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 140°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative.
Note 4: The LTC4274 operates with a negative supply voltage (with respect
to ground). To avoid confusion, voltages in this data sheet are referred to
in terms of absolute magnitude.
Note 6: The LTC4274 digital interface operates with respect to DGND. All
logic levels are measured with respect to DGND.
Note 7: Guaranteed by design, not subject to test.
Note 8: The IEEE 802.3af specification allows a PD to present its
Maintain Power Signature (MPS) on an intermittent basis without being
disconnected. In order to stay powered, the PD must present the MPS for
t
within any t
time window.
MPS
MPDO
Note 9: Values measured at V
Note 10: If fault condition occurs during an I C transaction, the INT pin
will not be pulled down until a stop condition is present on the I C bus.
and V
.
ILD(MAX)
IHD(MIN)
2
2
Note 11: Load Characteristic of the LTC4274 during Mark:
7V < (AGND – V ) < 10V or I
< 50μA
OUT
OUT
Note 12: See the LTC4274 Software Programming documentation for
information on serial bus usage and device configuration and status
registers.
Note 5: t is the same as t
defined by IEEE 802.3at.
DIS
MPDO
4274fa
6
LTC4274
TYPICAL PERFORMANCE CHARACTERISTICS
Power On Sequence in AUTO Pin
802.3af Classification in
AUTO Pin Mode
Mode
Powering Up into a 180μF Load
GND
10
0
GND
FORCED CURRENT DETECTION
GND
V
DD
V
EE
= 3.3V
= –54V
PORT
VOLTAGE
20V/DIV
LOAD
FULLY
–10
–20
–30
–18.4
CHARGED
FORCED VOLTAGE
DETECTION
V
EE
PORT
CURRENT
200 mA/DIV
802.3af
PORT 1
V
DD
V
EE
= 3.3V
= –55V
PORT
VOLTAGE
10V/DIV
FOLDBACK
425mA
CURRENT LIMIT
CLASSIFICATION
V
DD
V
EE
= 3.3V
= –54V
–40
–50
–60
–70
PD IS CLASS 1
POWER ON
0mA
FET ON
GATE
VOLTAGE
10V/DIV
V
EE
V
EE
V
EE
5ms/DIV
5ms/DIV
100ms/DIV
4274 G02
4274 G01
4274 G03
2-Event Classification in
AUTO Pin Mode
Classification Transient Response
to 40mA Load Step
Classification Current Compliance
0
V
DD
V
EE
= 3.3V
= –54V
GND
V
DD
V
EE
= 3.3V
= –54V
40mA
0mA
–2
–4
PORT
CURRENT
20mA/DIV
T
A
= 25°C
–6
–17.6
1ST CLASS EVENT
–8
2ND CLASS EVENT
–10
–12
–14
–16
–18
–20
PORT
VOLTAGE
10V/DIV
V
V
= 3.3V
= –55V
DD
EE
PORT
VOLTAGE
1V/DIV
PD IS CLASS 4
–20V
V
EE
0
10
20
30
40
50
60
70
50μs/DIV
10ms/DIV
CLASSIFICATION CURRENT
4274 G05
4274 G06
4274 G04
802.3at ILIM Threshold vs
Temperature
VDD Supply Current vs Voltage
VEE Supply Current vs Voltage
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
2.4
2.3
2.2
2.1
215
214
213
212
211
210
860
–40°C
25°C
85°C
V
V
= 3.3V
= –54V
SENSE
DD
EE
R
= 0.25Ω
856
852
848
844
840
REG 48h = C0h
–40°C
25°C
85°C
2.0
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3
SUPPLY VOLTAGE (V)
–60 –55 –50 –45 –40 –35 –30 –25 –20
SUPPLY VOLTAGE (V)
–40
0
40
–80
120
V
V
TEMPERATURE (°C)
DD
EE
4274 G07
4274 G08
4274 G09
4274fa
7
LTC4274
TYPICAL PERFORMANCE CHARACTERISTICS
802.3af ILIM Threshold vs
Temperature
802.3at ICUT Threshold vs
Temperature
108.00
107.25
106.50
432
429
163
162
652
648
644
640
V
V
= 3.3V
= –54V
SENSE
V
V
= 3.3V
= –54V
SENSE
DD
EE
DD
EE
R
= 0.25Ω
R
= 0.25Ω
REG 48h = 80h
REG 47h = E2h
161
160
159
158
426
423
420
105.75
105.00
636
630
–40
0
40
80
120
–40
0
40
80
120
TEMPERATURE (°C)
TEMPERATURE (°C)
4274 G10
4274 G11
802.3af ICUT Threshold vs
Temperature
DC Disconnect Threshold vs
Temperature
8.00
7.75
7.50
7.25
7.00
2.0000
1.9375
96.00
95.25
94.50
93.75
93.00
384
381
V
V
= 3.3V
= –54V
SENSE
V
V
= 3.3V
= –54V
SENSE
DD
EE
DD
EE
R
= 0.25Ω
R
= 0.25Ω
REG 47h = E2h
REG 47h = D4h
1.8750
1.8125
1.7500
378
375
372
–40
0
40
80
120
–40
0
40
80
120
TEMPERATURE (°C)
TEMPERATURE (°C)
4266 G13
4274 G12
ADC Noise Histogram
Current Readback in Fast Mode
ADC Integral Nonlinearity
Current Limit Foldback
Current Readback in Fast Mode
1.0
0.5
900
800
700
600
500
400
300
200
100
0
225
400
V
– V = 110.4mV
EE
V
V
= 3.3V
SENSE
DD
EE
= –54V
200
175
150
125
100
75
350
300
250
200
150
100
50
R
SENSE
= 0.25Ω
REG 48h = C0h
0
–0.5
–1.0
50
25
0
0
0
50 100 150 200 250 300 350 400 450 500
–54
–45
–36
–9
0
191
192
193
ADC OUTPUT
196
–27
–18
194
195
V
(V)
CURRENT SENSE RESISTOR INPUT VOLTAGE (mV)
OUTn
4274 G16
4274 G14
4274 G15
4274fa
8
LTC4274
TYPICAL PERFORMANCE CHARACTERISTICS
ADC Noise Histogram
Current Readback in Slow Mode
ADC Integral Nonlinearity
Current Readback in Slow Mode
ADC Noise Histogram Port
Voltage Readback in Fast Mode
300
250
200
150
100
50
1.0
0.5
600
500
400
300
200
100
0
V
– V = 110.4mV
EE
AGND – V
= 48.3V
SENSEn
OUTn
0
–0.5
–1.0
0
6139
6141
6143
6145
6147
0
50 100 150 200 250 300 350 400 450 500
260
261
262
ADC OUTPUT
263
264
265
ADC OUTPUT
CURRENT SENSE RESISTOR INPUT VOLTAGE (mV)
4274 G17
4274 G18
4274 G19
ADC Integral Nonlinearity
Voltage Readback in Slow Mode
ADC Integral Nonlinearity
Voltage Readback in Fast Mode
ADC Noise Histogram Port
Voltage Readback in Slow Mode
1.0
0.5
600
500
400
300
200
100
0
1.0
0.5
AGND – V
= 48.3V
OUTn
0
0
–0.5
–1.0
–0.5
–1.0
0
10
20
30
40
50
60
0
10
20
30
40
50
60
8532
8533
8534
ADC OUTPUT
8535
8536
PORT VOLTAGE (V)
PORT VOLTAGE (V)
4274 G20
4274 G22
4274 G21
MOSFET Gate Drive With Fast
Pull Down
INTandSDAOUTPullDownVoltage
vs Load Current
3
2.5
2
GND
V
DD
V
EE
= 3.3V
= –54V
PORT
VOLTAGE
20V/DIV
V
V
EE
EE
FAST PULL DOWN
GATE
VOLTAGE
10V/DIV
1.5
1
CURRENT LIMIT
50Ω
FAULT
APPLIED
PORT
CURRENT
500mA/DIV
50Ω FAULT REMOVED
0.5
0
0mA
0
5
10
LOAD CURRENT (mA)
15 20 25 30 35 40
100μs/DIV
4274 G23
4274 G24
4274fa
9
LTC4274
TEST TIMING DIAGRAMS
t
CLASSIFICATION
DET
FORCED-
VOLTAGE
FORCED-CURRENT
0V
t
ME1
V
t
PORT
ME2
V
OC
V
MARK
15.5V
20.5V
V
CLASS
t
CLE1
t
CLE2
PD
CONNECTED
t
CLE3
t
t
PON
DETDLY
V
EE
INT
4274 F01
Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-Auto Modes
V
LIM
0V
V
CUT
V
SENSE
EE
V
V
TO V
EE
MIN
SENSE
TO V
t
, t
START ICUT
INT
INT
t
t
DIS
MPS
4274 F03
4274 F02
Figure 2. Current Limit Timing
Figure 3. DC Disconnect Timing
t
t
3
r
t
4
t
f
V
GATE
SCL
t
MSD
V
EE
t
SHDN
t
t
t
7
t
8
t
2
5
6
MSD or
SHDN
SDA
4274 F04
4274 F05
t
1
Figure 4. Shut Down Delay Timing
Figure 5. I2C Interface Timing
4274fa
10
LTC4274
I2C TIMING DIAGRAMS
SCL
SDA
AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
0
1
0
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
ACK BY
SLAVE
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 3
DATA BYTE
4274 F06
Figure 6. Writing to a Register
SCL
SDA
AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
0
1
0
0
1
0
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
REPEATED
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 1
FRAME 2
DATA BYTE
SERIAL BUS ADDRESS BYTE
4274 F07
Figure 7. Reading from a Register
SCL
SDA
0
1
0
AD3 AD2 AD1 AD0 R/W
FRAME 1
ACK
D7 D6 D5 D4 D3 D2 D1 D0
ACK
STOP BY
MASTER
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 2
DATA BYTE
SERIAL BUS ADDRESS BYTE
4274 F08
Figure 8. Reading the Interrupt Register (Short Form)
SCL
SDA
0
0
0
1
1
0
0
R/W
ACK
0
1
0
AD3 AD2 AD1 AD0
1
ACK
STOP BY
MASTER
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 1
ALERT RESPONSE ADDRESS BYTE
FRAME 2
SERIAL BUS ADDRESS BYTE
4274 F09
Figure 9. Reading from Alert Response Address
4274fa
11
LTC4274
PIN FUNCTIONS
RESET: Chip Reset, Active Low. When the RESET pin is
low, the LTC4274 is held inactive with all ports off and all
internal registers reset to their power-up states. When
RESETispulledhigh,theLTC4274beginsnormaloperation.
RESET can be connected to an external capacitor or RC
network to provide a power turn-on delay. Internal filter-
ing of the RESET pin prevents glitches less than 1μs wide
AD2: Address Bit 2. See AD3.
AD1: Address Bit 1. See AD3.
AD0: Address Bit 0. See AD3.
NC, DNC: All pins identified with “NC” or “DNC” must be
left unconnected.
DGND: Digital Ground. DGND is the return for the V
supply.
DD
from resetting the LTC4274. Internally pulled up to V .
DD
MID: Midspan Mode Input. When high, the LTC4274 acts
as a midspan device. Internally pulled down to DGND.
V : Logic Power Supply. Connect to a 3.3V power supply
DD
relative to DGND. V must be bypassed to DGND near
DD
INT: Interrupt Output, Open Drain. INT will pull low when
any one of several events occur in the LTC4274. It will
return to a high impedance state when bits 6 or 7 are set
in the Reset PB register (1Ah). The INT signal can be used
to generate an interrupt to the host processor, eliminating
the need for continuous software polling. Individual INT
events can be disabled using the Int Mask register (01h).
See the LTC4274 Software Programming documentation
formoreinformation.TheINTpinisonlyupdatedbetween
the LTC4274 with at least a 0.1μF capacitor.
SHDN: Shutdown, Active Low. When pulled low, SHDN
shuts down the port, regardless of the state of the internal
registers. Pulling SHDN low is equivalent to setting the
Reset Port bit in the Reset Pushbutton register (1Ah).
Internal filtering of the SHDN pin prevents glitches less
than 1μs wide from reseting the port. Internally pulled
up to V .
DD
2
I C transactions.
AGND: Analog Ground. AGND is the return for the V
supply.
EE
SCL: Serial Clock Input. High impedance clock input for
2
the I C serial interface bus. SCL must be tied high if not
SENSE: Current Sense Input. SENSE monitors the exter-
used.
nal MOSFET current via a 0.5ꢀ or 0.25Ω sense resistor
between SENSE and V . Whenever the voltage across
EE
SDAOUT: Serial Data Output, Open Drain Data Output for
2
the sense resistor exceeds the overcurrent detection
the I C Serial Interface Bus. The LTC4274 uses two pins
threshold V , the current limit fault timer counts up. If
CUT
to implement the bidirectional SDA function to simplify
2
the voltage across the sense resistor reaches the current
optoisolation of the I C bus. To implement a standard
limit threshold V , the GATE pin voltage is lowered to
LIM
bidirectional SDA pin, tie SDAOUT and SDAIN together.
SDAOUT should be grounded or left floating if not used.
See Applications Information for more information.
maintain constant current in the external MOSFET. See
Applications Information for further details.
GATE: Gate Drive. GATE should be connected to the gate
of the external MOSFET for the port. When the MOSFET
is turned on, the gate voltage is driven to 13V (typ) above
SDAIN: Serial Data Input. High impedance data input for
2
the I C serial interface bus. The LTC4274 uses two pins
to implement the bidirectional SDA function to simplify
2
V . During a current limit condition, the voltage at GATE
EE
optoisolation of the I C bus. To implement a standard
will be reduced to maintain constant current through the
external MOSFET. If the fault timer expires, GATE is pulled
bidirectional SDA pin, tie SDAOUT and SDAIN together.
SDAIN must be tied high if not used. See Applications
Information for more information.
down, turning the MOSFET off and recording a t
START
or
CUT
t
event.
AD3: Address Bit 3. Tie the address pins high or low to set
2
theI CserialaddresstowhichtheLTC4274responds.This
addresswillbe010A A A A b.InternallypulleduptoV .
3 2 1 0
DD
4274fa
12
LTC4274
PIN FUNCTIONS
OUT: Output Voltage Monitor. OUT should be connected
to the output port. A current limit foldback circuit limits
the power dissipation in the external MOSFET by reduc-
ing the current limit threshold when the drain-to-source
voltage exceeds 10V. The Power Good bit is set when the
AUTO pin determines the state of the internal registers
when the LTC4274 is reset or comes out of V UVLO
DD
(see the Register map). The states of these register bits
2
can subsequently be changed via the I C interface. The
real-time state of the AUTO pin is read at bit 0 in the Pin
Status register (11h). Internally pulled down to DGND.
voltage from OUT to V drops below 2.4V (typ). A 500k
EE
resistor is connected internally from OUT to AGND when
Must be tied locally to either V or DGND.
DD
the port is idle.
MSD: Maskable Shutdown Input. Active low. When pulled
low, all ports that have their corresponding mask bit set
in the Misc Config register (17h) will be reset, equivalent
to pulling the SHDN pin low. Internal filtering of the MSD
pin prevents glitches less than 1μs wide from resetting
V : Main Supply Input. Connect to a –45V to –57V
EE
supply, relative to AGND.
AUTO: AUTO Pin Mode Input. AUTO pin mode allows the
LTC4274 to detect and power up a PD even if there is no
ports. Internally pulled up to V .
2
DD
host controller present on the I C bus. The voltage of the
4274fa
13
LTC4274
OPERATION
Overview
compared to alternative designs with on-board MOSFETs
and increase system reliability in the event a single chan-
nel is damaged.
Power over Ethernet, or PoE, is a standard protocol for
sending DC power over copper Ethernet data wiring.
The IEEE group that administers the 802.3 Ethernet data
standards added PoE powering capability in 2003. This
original PoE spec, known as 802.3af, allowed for 48V DC
power at up to 13W. This initial spec was widely popular,
but 13W was not adequate for some requirements. In
2009, the IEEE released a new standard, known as 802.3at
or PoE+, increasing the voltage and current requirements
to provide 25W of power.
PoE Basics
Common Ethernet data connections consist of two or four
twisted pairs of copper wire (commonly known as CAT-5
cable), transformer-coupled at each end to avoid ground
loops. PoE systems take advantage of this coupling ar-
rangement by applying voltage between the center-taps
of the data transformers to transmit power from the PSE
to the PD without affecting data transmission. Figure 10
shows a high-level PoE system schematic.
The IEEE standard also defines PoE terminology. A device
that provides power to the network is known as a PSE, or
powersourcingequipment,whileadevicethatdrawspower
from the network is known as a PD, or powered device.
PSEs come in two types: Endpoints (typically network
switches or routers), which provide data and power; and
Midspans, which provide power but pass through data.
MidspansaretypicallyusedtoaddPoEcapabilitytoexisting
non-PoE networks. PDs are typically IP phones, wireless
access points, security cameras, and similar devices, but
could be nearly anything that runs from 25W or less and
includes an RJ45-style network connector.
To avoid damaging legacy data equipment that does not
expect to see DC voltage, the PoE spec defines a protocol
that determines when the PSE may apply and remove
power. Valid PDs are required to have a specific 25kΩ
common-mode resistance at their input. When such a PD
is connected to the cable, the PSE detects this signature
resistance and turns on the power. When the PD is later
disconnected, the PSE senses the open circuit and turns
power off. The PSE also turns off power in the event of a
current fault or short circuit.
When a PD is detected, the PSE optionally looks for a
classification signature that tells the PSE the maximum
power the PD will draw. The PSE can use this information
to allocate power among several ports, police the current
consumption of the PD, or to reject a PD that will draw
The LTC4274 is a third-generation single PSE controller
in either an endpoint or midspan design. Virtually all nec-
essary circuitry is included to implement a IEEE 802.3at
compliant PSE design, requiring only an external power
MOSFET and sense resistor; these minimize power loss
PSE
PD
RJ45
4
RJ45
CAT 5
4
5
5
GND
1N4002
SPARE PAIR
s4
0.22μF
100V
X7R
1
1
DGND
AGND
5μF ≤ C
IN
≤ 300μF
SMAJ58A
58V
Tx
Rx
Tx
3.3V
INTERRUPT
V
DD
INT
SCL
SDAIN
SDAOUT
2
3
2
3
DATA PAIR
DATA PAIR
LTC4274
SMAJ58A
58V
2
I C
0.1μF
100V
1N4002
s4
Rx
V
SENSE GATE OUT
EE
1μF
GND
6
6
100V
X7R
DC/DC
CONVERTER
R
PWRGD
+
OUT
CLASS
S1B
V
0.25Ω
LTC4265
–54V
7
8
7
IRFM120A
V
V
–
IN
OUT
8
S1B
SPARE PAIR
4274 F10
Figure 10. Power Over Ethernet System Diagram
4274fa
14
LTC4274
OPERATION
more power that the PSE has available. The classification
step is optional; if a PSE chooses not to classify a PD, it
must assume that the PD is a 13W (full 802.3af power)
device.
compatible) devices can be substituted with the LTC4274
without software or PCB layout changes if only port 1 was
used; only minor BOM changes are required to implement
a fully compliant 802.3at design.
Because of the backwards compatibility features, some of
the internal registers are redundant or unused when the
LTC4274 is operated as recommended. For more details
on usage in compatibility mode, refer to the LTC4258/
LTC4259A device datasheets.
New in 802.3at
Thenewer802.3atstandardsupersedes802.3afandbrings
several new features:
• A PD may draw as much as 25.5W. Such PDs (and the
PSEs that support them) are known as Type 2. Older
13W 802.3af equipment is classified as Type 1. Type 1
PDs will work with all PSEs; Type 2 PDs may require
Type 2 PSEs to work properly. The LTC4274 is designed
to work in both Type 1 and Type 2 PSE designs, and
also supports non-standard configurations at higher
power levels.
Special Compatibility Mode Notes
• The LTC4274 can use either 0.5Ω or 0.25Ω sense
resistors, while the LTC425x chips always used 0.5Ω.
To maintain compatibility, if the AUTO pin is low when
the LTC4274 powers up it assumes the sense resistor
is 0.5Ω; if it is high at power up, the LTC4274 assumes
0.25Ω. The resistor value setting can be reconfigured
at any time after power up. In particular, systems that
use 0.25Ω sense resistors and have AUTO tied low
must reconfigure the resistor settings after power up.
• The Classification protocol is expanded to allow Type 2
PSEs to detect Type 2 PDs, and to allow Type 2 PDs to
determine if they are connected to a Type 2 PSE. Two
versions of the new Classification protocol are avail-
able: an expanded version of the 802.3af Class Pulse
protocol, and an alternate method integrated with the
existing LLDP protocol (using the Ethernet data path).
TheLTC4274fullysupportsthenewClassPulseprotocol
and is also compatible with the LLDP protocol (which
is implemented in the data communications layer, not
in the PoE circuitry).
• The LTC4259A included both AC and DC disconnect
sensing circuitry, but the LTC4274 has only DC discon-
nect sensing. For the sake of compatibility, register
bits used to enable AC disconnect in the LTC4259A are
implemented in the LTC4274, but they simply mirror
the bits used for DC disconnect.
• The LTC4258 and LTC4259A required 10k resistors
between the OUTn pins and the drains of the external
MOSFETs. These resistors must be shorted or replaced
with zero ohm jumpers when using the LTC4274.
• Fault protection current levels and timing are adjusted
to reduce peak power in the MOSFET during a fault;
this allows the new 25.5W power levels to be reached
using the same MOSFETs as older 13W designs.
• The LTC4258 and LTC4259A included a BYP pin, de-
coupledtoAGNDwith0.1μF.ThispinchangestotheMID
pin on the LTC4274. The capacitor should be removed
for Endspan applications, or replaced with a zero ohm
jumper for Midspan applications.
BACKWARDS COMPATIBILITY
The LTC4274 is fully software and pin compatible with the
LTC4266 if only port 1 was used.
The LTC4274 is designed to be backward compatible with
earlierPSEchipsinbothsoftwareandpinfunctions. Exist-
ing systems using either the LTC4258 or LTC4259A (or
4274fa
15
LTC4274
APPLICATIONS INFORMATION
Operating Modes
Regardlessofwhichmodeitisin,theLTC4274willremove
power automatically from a port that generates a current
limit fault. It will also automatically remove power from a
portthatgeneratesadisconnecteventifdisconnectdetec-
tion is enabled. The host controller may also command
the port to remove power at any time.
The LTC4274 can operate in one of four modes: manual,
semi-auto, AUTO pin, or shutdown.
Table 1. Operating Modes
AUTOMATIC
AUTO
PIN OPMD
DETECT/
CLASS
I
/I
CUT LIM
MODE
POWER-UP ASSIGNMENT
Reset and the AUTO/MID pins
AUTO Pin
1
11b
Enabled at Automatically
Reset
Yes
The initial LTC4274 configuration depends on the state
of the AUTO and MID pins during reset. Reset occurs at
power-up, or whenever the RESET pin is pulled low or the
global Reset All bit is set. Note that the AUTO pin is only
sampled when a reset occurs. Changing the state of AUTO
or MID after power-up will not change the port behavior
of the LTC4274 until a reset occurs.
Reserved
Semi-auto
0
0
11b
10b
N/A
N/A
N/A
No
Host
Enabled
Upon
Request
Manual
0
0
01b Once Upon
Request
Upon
No
No
Request
Shutdown
00b
Disabled
Disabled
Althoughtypicallyusedwithahostcontroller,theLTC4274
can also be used in a standalone mode with no connec-
tion to the serial interface. If there is no host present, the
AUTO pin should be tied high so that, at reset, the port
will be configured to operate automatically. The port will
detect and classify repeatedly until a PD is discovered,
• Inmanualmode,theportwaitsforinstructionsfromthe
host system before taking any action. It runs a single
detection or classification cycle when commanded to
by the host, and reports the result in its Port Status
register. The host system can command the port to turn
on or off the power at any time. This mode should only
be used for diagnostic and test purposes.
set I
and I
according to the classification results,
CUT
LIM
applypoweraftersuccessfuldetection,andremovepower
when a PD is disconnected. Similarly, if the standalone
application is a midspan, the MID pin should be tied high
to enable correct midspan detection timing.
• In semi-auto mode, the port repeatedly attempts to
detect and classify any PD attached to it. It reports the
status of these attempts back to the host, and waits for
a command from the host before turning on power to
theport.Thehostmustenabledetection(andoptionally
classification) for the port before detection will start.
Table 2 shows the I
and I
values that will be
LIM
CUT
automatically set in AUTO pin mode, based on the dis-
covered class.
• AUTO pin mode operates the same as semi-auto mode
except that it will automatically turn on the power to the
Table 2. ICUT and ILIM Values in AUTO Pin Mode
CLASS
I
I
LIM
CUT
port if detection is successful. In AUTO pin mode, I
CUT
Class 1
112mA
206mA
375mA
638mA
425mA
425mA
425mA
850mA
and I
values are set automatically by the LTC4274.
LIM
Class 2
The AUTO pin must be high at reset to ensure proper
AUTO pin mode operation.
Class 3 or Class 0
Class 4
• In shutdown mode, the port is disabled and will not
detect or power a PD.
The automatic setting of the I
and I
values only
LIM
CUT
occurs if the LTC4274 is reset with the AUTO pin high.
4274fa
16
LTC4274
APPLICATIONS INFORMATION
DETECTION
and short circuits, are also reported. If the port measures
less than 1V at the first forced-current test, the detection
cycle will abort and Short Circuit will be reported. Table 3
shows the possible detection results.
Detection Overview
Toavoiddamagingnetworkdevicesthatwerenotdesigned
to tolerate DC voltage, a PSE must determine whether the
connected device is a real PD before applying power. The
IEEEspecificationrequiresthatavalidPDhaveacommon-
moderesistanceof25k 5%atanyportvoltagebelow10V.
ThePSEmustacceptresistancesthatfallbetween19kand
26.5k, and it must reject resistances above 33k or below
15k(shadedregionsinFigure11). ThePSEmaychooseto
acceptorrejectresistancesintheundefinedareasbetween
the must-accept and must-reject ranges. In particular, the
PSE must reject standard computer network ports, many
ofwhichhave150Ωcommon-modeterminationresistors
that will be damaged if power is applied to them (the black
region at the left of Figure 11).
Table 3. Detection Status
MEASURED PD SIGNATURE
Incomplete or Not Yet Tested
<2.4k
DETECTION RESULT
Detect Status Unknown
Short Circuit
Capacitance > 2.7μF
C
too High
too Low
PD
2.4k < R < 17k
R
SIG
PD
17k < R < 29k
Detect Good
too High
PD
>29k
R
SIG
>50k
Open Circuit
Voltage > 10V
Port Voltage Outside Detect Range
Operating Modes
The port’s operating mode determines when the LTC4274
runs a detection cycle. In manual mode, the port will
idle until the host orders a detect cycle. It will then run
detection, report the results, and return to idle to wait for
another command.
RESISTANCE 0Ω
10k
20k
30k
150Ω (NIC)
23.75k
26.25k
26.5k
PD
PSE
15k 19k
33k
4274 F11
In semi-auto mode, the LTC4274 autonomously polls the
port for PDs, but it will not apply power until commanded
to do so by the host. The Port Status register is updated
at the end of each detection cycle. If a valid signature
resistance is detected and classification is enabled, the
port will classify the PD and report that result as well.
Figure 11. IEEE 802.3af Signature Resistance Ranges
4-Point Detection
The LTC4274 uses a 4-point detection method to discover
PDs. False-positive detections are minimized by check-
ing for signature resistance with both forced-current and
forced-voltage measurements. Initially, two test currents
are forced onto the port (via the OUT pin) and the resulting
voltages are measured. The detection circuitry subtracts
the two V-I points to determine the resistive slope while
removing offset caused by series diodes or leakage at
the port (see Figure 12). If the forced-current detection
yields a valid signature resistance, two test voltages are
then forced onto the port and the resulting currents are
measuredandsubtracted.Bothmethodsmustreportvalid
resistances for the port to report a valid detection. PD
signature resistances between 17k and 29k (typically) are
detected as valid and reported as Detect Good in the Port
Status register. Values outside this range, including open
275
FIRST
DETECTION
POINT
25kΩ SLOPE
165
SECOND
DETECTION
POINT
VALID PD
0V-2V
OFFSET
VOLTAGE
4274 F12
Figure 12. PD Detection
4274fa
17
LTC4274
APPLICATIONS INFORMATION
The port will then wait for at least 100ms (or 2 seconds if
midspan mode is enabled), and will repeat the detection
cycle to ensure that the data in the Port Status register
is up-to-date.
CLASSIFICATION
802.3af Classification
A PD can optionally present a classification signature to
the PSE to indicate the maximum power it will draw while
operating. The IEEE specification defines this signature as
aconstantcurrentdrawwhenthePSEportvoltageisinthe
If the port is in semi-auto mode and high power opera-
tion is enabled, the port will not turn on in response to
a power-on command unless the current detect result is
V
CLASS
range(between15.5Vand20.5V), withthecurrent
detect good. Any other detect result will generate a t
START
level indicating one of 5 possible PD classes. Figure 14
shows a typical PD load line, starting with the slope of the
25kꢀ signature resistor below 10V, then transitioning to
the classification signature current (in this case, Class 3)
fault if a power-on command is received. If the port is not
in high power mode, it will ignore the detection result and
apply power when commanded, maintaining backwards
compatibility with the LTC4259A.
in the V
range. Table 4 shows the possible clas-
CLASS
sification values.
BehaviorinAUTOpinmodeissimilartosemi-auto;however,
after Detect Good is reported and the port is classified (if
classification is enabled), it is automatically powered on
without further intervention. In standalone (AUTO pin)
Table 4. Classification Values
CLASS
Class 0
Class 1
Class 2
Class 3
Class 4
RESULT
mode,theI andI thresholdsareautomaticallyset;see
No Class Signature Present; Treat Like Class 3
CUT
LIM
the Reset and the AUTO Pin section for more information.
3W
7W
The signature detection circuitry is disabled when the
port is initially powered up with the AUTO pin low, in
shutdown mode, or when the corresponding Detect
Enable bit is cleared.
13W
25.5W (Type 2)
If classification is enabled, the port will classify the PD
immediatelyafterasuccessfuldetectioncycleinsemi-auto
or AUTO pin modes, or when commanded to in manual
mode. It measures the PD classification signature by ap-
plying 18V for 12ms (both values typical) to the port via
Detection of Legacy PDs
Proprietary PDs that predate the original IEEE 802.3af
standard are commonly referred to today as legacy de-
vices. One type of legacy PD uses a large common mode
capacitance (>10ꢁF) as the detection signature. Note that
PDs in this range of capacitance are defined as invalid, so
a PSE that detects legacy PDs is technically noncompliant
with the IEEE spec.
60
PSE LOAD LINE
OVER
CURRENT
50
40
30
20
10
0
48mA
CLASS 4
CLASS 3
33mA
23mA
The LTC4274 can be configured to detect this type of
legacy PD. Legacy detection is disabled by default, but
can be manually enabled. When enabled, the port will
report Detect Good when it sees either a valid IEEE PD or
ahigh-capacitancelegacyPD. Withlegacymodedisabled,
only valid IEEE PDs will be recognized.
CLASS 2
TYPICAL
CLASS 3
PD LOAD
LINE
14.5mA
6.5mA
CLASS 1
CLASS 0
0
5
10
15
20
25
VOLTAGE (V
)
CLASS
4274 F13
Figure 13. PD Classification
4274fa
18
LTC4274
APPLICATIONS INFORMATION
the OUT pin and measuring the resulting current; it then
reports the discovered class in the Port Status register. If
the LTC4274 is in AUTO pin mode, it will additionally use
Class 0 to 3, the port assumes it is connected to a Type
1 PD and does not run the second classification cycle.
Invalid Type 2 Class Combinations
the classification result to set the I and I thresholds.
CUT
LIM
See the Reset and the AUTO/MID Pin section for more
The 802.3at spec defines a Type 2 PD class signature as
two consecutive Class 4 results; a Class 4 followed by a
Class 0-3 is not a valid signature. In AUTO pin mode, the
LTC4274 will power a detected PD regardless of the clas-
sification results, with one exception: if the PD presents
an invalid Type 2 signature (Class 4 followed by Class 0
to 3), the LTC4274 will not provide power and will restart
the detection process. To aid in diagnosis, the Port Status
registerwillalwaysreporttheresultsofthelastclasspulse,
so an invalid Class 4–Class 2 combination would report
a second class pulse was run in the High Power Status
register (which implies that the first cycle found Class 4),
and Class 2 in the Port Status register.
information.
The classification circuitry is disabled when the port is
initially powered up with the AUTO pin low, in shutdown
mode, or when the corresponding Class Enable bit is
cleared.
802.3at 2-Event Classification
The 802.3at spec defines two methods of classifying a
Type 2 PD.
One method adds extra fields to the Ethernet LLDP data
protocol; although the LTC4274 is compatible with this
classification method, it cannot perform classification
directly since it doesn’t have access to the data path.
LLDP classification requires the PSE to power the PD as
a standard 802.3af (Type 1) device. It then waits for the
host to perform LLDP communication with the PD and
update the PSE port data. The LTC4274 supports chang-
POWER CONTROL
External MOSFET, Sense R Summary
The primary function of the LTC4274 is to control the
delivery of power to the PSE port. It does this by control-
ling the gate drive voltage of an external power MOSFET
while monitoring the current via an external sense resis-
tor and the output voltage at the OUT pin. This circuitry
ing the I
and I
levels on the fly, allowing the host
LIM
CUT
to complete LLDP classification.
The second 802.3at classification method, known as
2-event classification or ping-pong, is fully supported by
the LTC4274. A Type 2 PD that is requesting more than
13W will indicate Class 4 during normal 802.3af classifi-
cation. If the LTC4274 sees Class 4, it forces the port to a
specified lower voltage (called the mark voltage, typically
9V), pauses briefly, and then re-runs classification to
verify the Class 4 reading (Figure 1). It also sets a bit in
the High Power Status register to indicate that it ran the
second classification cycle. The second cycle alerts the
PD that it is connected to a Type 2 PSE which can supply
Type 2 power levels.
serves to couple the raw V input supply to the port in
EE
a controlled manner that satisfies the PD’s power needs
while minimizing power dissipation in the MOSFET and
disturbances on the V backplane.
EE
The LTC4274 is designed to use 0.25ꢀ sense resistors to
minimize power dissipation. It also supports 0.5ꢀ sense
resistors, which are the default when LTC4258/LTC4259A
compatibility is desired.
Inrush Control
Once the command has been given to turn on the port,
the LTC4274 ramps up the GATE pin of the port’s external
MOSFET in a controlled manner. Under normal power-up
circumstances, the MOSFET gate will rise until the port
2-event ping-pong classification is enabled by setting a bit
in the port’s High Power Mode register. Note that a ping-
pongenabledportonlyrunsthesecondclassificationcycle
when it detects a Class 4 device; if the first cycle returns
4274fa
19
LTC4274
APPLICATIONS INFORMATION
current reaches the inrush current limit level (typically
450mA), at which point the GATE pin will be servoed to
compliance, I should kept at 425mA for all Type 1 PDs,
LIM
and 850mA if a Type 2 PD is detected. I is automatically
LIM
maintain the specified I
current. During this inrush
reset to 425mA when a port turns off.
INRUSH
period, a timer (t
) runs. When output charging is
START
Table 5. Example Current Limit Settings
INTERNAL REGISTER SETTING (hex)
complete, the port current will fall and the GATE pin will
be allowed to continue rising to fully enhance the MOSFET
I
(mA)
R
= 0.5Ω
R
SENSE
= 0.25Ω
LIM
SENSE
and minimize its on-resistance. The final V is nominally
GS
53
88
13V. If the t
timer expires before the inrush period
START
106
159
213
266
319
372
08
89
80
8A
09
8B
88
completes, the port will be turned back off and a t
fault reported.
START
08
89
Current Limit
EachLTC4274portincludestwocurrentlimitingthresholds
(I and I ), each with a corresponding timer (t
CUT
CUT
LIM
425
478
00
8E
92
CB
10
D2
40
4A
50
5A
60
52
80
and t ). Setting the I
and I
thresholds depends
LIM
CUT
LIM
on several factors: the class of the PD, the voltage of the
531
8A
main supply (V ), the type of PSE (1 or 2), the sense
EE
584
resistor (0.5Ω or 0.25Ω), the SOA of the MOSFET, and
whether or not the system is required to implement class
enforcement.
638
90
9A
C0
CA
D0
DA
E0
49
40
4A
50
5A
60
52
744
850
Per the IEEE spec, the LTC4274 will allow the port cur-
956
rent to exceed I
for a limited period of time before
CUT
1063
1169
1275
1488
1700
1913
2125
2338
2550
2975
removing power from the port, whereas it will actively
control the MOSFET gate drive to keep the port current
below I . The port does not take any action to limit the
LIM
current when only the I
does start the t
threshold is exceeded and current limit is active. If
the current drops below the I
its timer expires, the t
threshold is exceeded, but
LIM
CUT
timer. The t
timer starts when the
CUT
I
LIM
current threshold before
CUT
timer counts back down, but
CUT
at 1/16 the rate that it counts up. This allows the current
limit circuitry to tolerate intermittent overload signals with
duty cycles below about 6%; longer duty cycle overloads
will turn the port off.
I
Foldback
LIM
I
is typically set to a lower value than I to allow the
LIM
The LTC4274 features a two-stage foldback circuit that
reduces the port current if the port voltage falls below
the normal operating voltage. This keeps MOSFET power
dissipation at safe levels for typical 802.3af MOSFETs,
CUT
port to tolerate minor faults without current limiting.
Per the IEEE specification, the LTC4274 will automatically
set I
to 425mA (shown in bold in Table 5) during in-
LIM
rush at port turn-on, and then switch to the programmed
setting once inrush has completed. To maintain IEEE
I
LIM
4274fa
20
LTC4274
APPLICATIONS INFORMATION
MOSFET Fault Detection
even at extended 802.3at power levels. Current limit and
foldback behavior are programmable. Figure 14 shows
MOSFET power dissipation with 802.3af-style foldback
compared with a typical MOSFET SOA curve; Figure 15
demonstrates how two-stage foldback keeps the FET
within its SOA under the same conditions. Table 4 gives
LTC4274 PSE ports are designed to tolerate significant
levels of abuse, but in extreme cases it is possible for the
external MOSFET to be damaged. A failed MOSFET may
short source to drain, which will make the port appear to
be on when it should be off; this condition may also cause
the sense resistor to fuse open, turning off the port but
causing the LTC4274 SENSE pin to rise to an abnormally
high voltage. A failed MOSFET may also short from gate
to drain, causing the LTC4274 GATE pin to rise to an ab-
normallyhighvoltage.TheLTC4274SENSEandGATEpins
are designed to tolerate up to 80V faults without damage.
examples of recommended I register settings.
LIM
The LTC4274 will support current levels well beyond the
maximum values in the 802.3at specification. The shaded
areas in Table 5 indicate settings that may require a larger
external MOSFET, additional heat sinking, or a reduced
t
setting.
LIM
If the LTC4274 sees any of these conditions for more than
180ꢁs, it disables all port functionality, reduces the gate
drive pull-down current for the port and reports a FET Bad
fault. This is typically a permanent fault, but the host can
attempt to recover by resetting the port, or by resetting
the entire chip if a port reset fails to clear the fault. If the
MOSFET is in fact bad, the fault will quickly return, and
the port will disable itself again.
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
802.3af FOLDBACK
An open or missing MOSFET will not trigger a FET Bad
fault, but will cause a t
to turn on the port.
fault if the LTC4274 attempts
START
SOA DC AT 90°C
30
0
10
PD Voltage (V) at V
40
= 58V
50
60
20
PSE
4274 F14
Voltage and Current Readback
Figure 14. Turn On Currents vs FET Safe Operating
Area at 90°C Ambient
The LTC4274 measures the output voltage and current
at each port with an internal A/D converter. Port data is
only valid when the port power is on. The converter has
two modes:
1.0
0.9
0.8
0.7
0.6
0.5
0.4
• Slow mode: 14 samples per second, 14.5 bits resolution
• Fast mode: 440 samples per second, 9.5 bits resolution
Infastmode,theleastsignificant5bitsofthelowerbyteare
zeroes so that bit scaling is the same in both modes.
0.3
0.2
0.1
0.0
802.3af FOLDBACK
Disconnect
SOA DC AT 90°C
30
PD Voltage (V) at V
The LTC4274 monitors the port to make sure that the PD
continues to draw the minimum specified current. A dis-
connect timer counts up whenever port current is below
7.5mA(typ),indicatingthatthePDhasbeendisconnected.
0
10
40
= 58V
50
60
20
PSE
4274 F15
Figure 15. LTC4274 Foldback vs FET Safe Operating
Area at 90°C Ambient
If the t timer expires, the port will be turned off and
DIS
the disconnect bit in the fault event register will be set.
If the current returns before the t timer runs out, the
DIS
4274fa
21
LTC4274
APPLICATIONS INFORMATION
timer resets and will start counting from the beginning
if the undercurrent condition returns. As long as the PD
exceeds the minimum current level more often than t
it will stay powered.
the host via the INT pin. The Timing Diagrams (Figures 5
through 9) show typical communication waveforms and
their timing relationships. More information about the
SMBus data protocols can be found at www.smbus.org.
,
DIS
Although not recommended, the DC disconnect feature
can be disabled by clearing the DC Disconnect Enable
bit. Note that this defeats the protection mechanisms
built into the IEEE spec, since a powered port will stay
powered after the PD is removed. If the still-powered port
is subsequently connected to a non-PoE data device, the
device may be damaged.
The LTC4274 requires both the V and V supply rails
DD
EE
to be present for the serial interface to function.
Bus Addressing
The LTC4274’s primary serial bus address is 010xxxxb,
with the lower four bits set by the AD3-AD0 pins; this
allows up to 16 LTC4274s on a single bus. All LTC4274s
also respond to the address 0110000b, allowing the host
to write the same command (typically configuration com-
mands) to multiple LTC4274s in a single transaction. If the
LTC4274 is asserting the INT pin, it will also respond to the
alert response address (0001100b) per the SMBus spec.
TheLTC4274doesnotincludeACdisconnectcircuitry, but
includes an AC disconnect enable bit to maintain compat-
ibility with the LTC4259A. If the AC Disconnect Enable bit
is set, DC disconnect will be used.
Shutdown Pin
Interrupts and SMBAlert
The LTC4274 includes a hardware SHDN pin. When the
SHDN pin is pulled to DGND, the port will be shut off im-
mediately. The port remains shut down until re-enabled
Most LTC4274 port events can be configured to trigger
an interrupt, asserting the INT pin and alerting the host
to the event. This removes the need for the host to poll
the LTC4274, minimizing serial bus traffic and conserving
host CPU cycles. Multiple LTC4274s can share a common
INT line, with the host using the SMBAlert protocol (ARA)
to determine which LTC4274 caused an interrupt.
2
via I C or a device reset in AUTO pin mode.
Masked Shutdown
The LTC4274 provides a low latency port shedding fea-
ture to quickly reduce the system load when required. By
allowing a pre-determined set of ports to be turned off,
the current on an overloaded main power supply can be
reduced rapidly while keeping high priority devices pow-
ered. Each port can be configured to high or low priority;
all low-priority ports will shut down within 6.5ꢁs after the
MSD pin is pulled low. If a port is turned off via MSD, the
correspondingDetectionandClassificationEnablebitsare
cleared, so the port will remain off until the host explicitly
re-enables detection.
Register Description
For information on serial bus usage and device configura-
tion and status, refer to the LTC4274 Software Program-
ming documentation.
EXTERNAL COMPONENT SELECTION
Power Supplies and Bypassing
The LTC4274 requires two supply voltages to operate. V
DD
SERIAL DIGITAL INTERFACE
requires 3.3V (nominally) relative to DGND. V requires
EE
a negative voltage of between –44V and –57V for Type 1
PSEs, or –50V to –57V for Type 2 PSEs, relative to AGND.
The relationship between the two grounds is not fixed;
Overview
TheLTC4274communicateswiththehostusingastandard
2
SMBus/I C 2-wire interface. The LTC4274 is a slave-only
AGND can be referenced to any level from V to DGND,
DD
device, and communicates with the host master using
the standard SMBus protocols. Interrupts are signaled to
although it should typically be tied to either V or DGND.
DD
4274fa
22
LTC4274
APPLICATIONS INFORMATION
V
provides power for most of the internal LTC4274 cir-
V
is the main supply that provides power to the PD.
EE
DD
cuitry,anddrawsamaximumof3mA.Aceramicdecoupling
Because it supplies a relatively large amount of power and
issubjecttosignificantcurrenttransients,itrequiresmore
design care than a simple logic supply. For minimum IR
cap of at least 0.1ꢁF should be placed from V to DGND,
as close as practical to each LTC4274 chip.
DD
loss and best system efficiency, set V near maximum
EE
Figure16showsathreecomponentlowdropoutregulator
foranegativesupplytoDGNDgeneratedfromthenegative
amplitude (57V), leaving enough margin to account for
transient over- or undershoot, temperature drift, and the
line regulation specs of the particular power supply used.
V
supply. V is tied to AGND and DGND is negative
EE
DD
referencedtoAGND.ThisregulatordrivesasingleLTC4274
device. In Figure 17, DGND is tied to AGND in this boost
Bypass capacitance between AGND and V is very impor-
EE
converter circuit for a positive V supply of 3.3V above
tant for reliable operation. If a short circuit occurs at the
output port it can take as long as 1ꢁs for the LTC4274 to
begin regulating the current. During this time the current
is limited only by the small impedances in the circuit and
a high current spike typically occurs, causing a voltage
DD
AGND. This circuit can drive multiple LTC4274 devices
and opto couplers.
1.4
1.2
1.0
0.8
0.6
0.4
transient on the V supply and possibly causing the
EE
LTC4274 to reset due to a UVLO fault. A 1ꢁF, 100V X7R
capacitor placed near the V pin is recommended to
EE
minimize spurious resets.
Isolating the Serial Bus
TheLTC4274includesasplitSDApin(SDAINandSDAOUT)
to ease opto-isolation of the bidirectional SDA line.
802.3af FOLDBACK
0.2
0.0
0
10
30
40
50
60
20
IEEE 802.3 Ethernet specifications require that network
segments (including PoE circuitry) be electrically isolated
from the chassis ground of each network interface device.
However,networksegmentsarenotrequiredtobeisolated
PD VOLTAGE (V)
4274 F16
Figure 16. Negative LDO to DGND
L3
L4
D28
B1100
100μH
10μH
SUMIDA CDRH5D28-101NC
SUMIDA CDRH4D28-100NC
3.3V AT 400mA
C74
100μF
6.3V
C73
10μF
6.3V
C75
R51
4.7k
1%
R53
R52
3.32k
1%
10μF
4.7k
16V
1%
C76
10μF
63V
C78
0.22μF
100V
+
5
Q13
Q14
FMMT723
C77
0.22μF
100V
V
FMMT723
CC
1
3
6
Q15
ITH/RUN
NGATE
SENSE
FDC2512
R58
10Ω
LTC3803
R54
56k
4
R55
806Ω
1%
R56
47.5k
1%
V
FB
R57
1k
R59
0.100Ω
1%, 1W
C79
2200pF
GND
2
R60
10Ω
V
EE
4274 F17
Figure 17. Positive VDD Boost Converter
4274fa
23
LTC4274
APPLICATIONS INFORMATION
0.1MF
2k
2k
U2
2007
V
CPU
SCL
DD
U1
ISOLATED
3.3V
0.1MF
LTC4274
V
INT
SCL
DD
2007
SDAIN
SDAOUT
AD0
SDA
AD1
AD2
AD3
DGND
AGND
HCPL-063L
+
TO
10MF
CONTROLLER
U3
2007
2007
ISOLATED
GND
SMBALERT
0.1MF
GND CPU
4274 F18
HCPL-063L
U1: FAIRCHILD NC7WZ17
U2, U3: AGILENT HCPL-063L
Figure 18. Opto-Isolating the I2C Bus
fromeachother,providedthatthesegmentsareconnected
to devices residing within a single building on a single
power distribution system.
shows a typical isolated serial interface. The SDAOUT pin
of the LTC4274 is designed to drive the inputs of an opto-
2
coupler directly. Standard I C/SMBus devices typically
cannot drive opto-couplers, so U1 is used to buffer the
signals from the host controller side.
For simple devices such as small PoE switches, the isola-
tion requirement can be met by using an isolated main
power supply for the entire device. This strategy can be
used if the device has no electrically conducting ports
other than twisted-pair Ethernet. In this case, the SDAIN
and SDAOUT pins can be tied together and will act as a
External MOSFET
CarefulselectionofthepowerMOSFETiscriticaltosystem
reliability. LTC recommends either Fairchild IRFM120A,
FDT3612, FDMC3612 or Philips PHT6NQ10T for their
proven reliability in Type 1 and Type 2 PSE applications.
Non-standard applications that provide more current than
the 850mA IEEE maximum may require heat sinking and
other MOSFET design considerations. Contact LTC Ap-
plications before using a MOSFET other than one of these
recommended parts.
2
standard I C/SMBus SDA pin.
If the device is part of a larger system, contains additional
external non-Ethernet ports, or must be referenced to
protective ground for some other reason, the Power over
Ethernet subsystem (including all LTC4274s) must be
electrically isolated from the rest of the system. Figure 18
4274fa
24
LTC4274
APPLICATIONS INFORMATION
Sense Resistor
ESD/Cable Discharge Protection
The LTC4274 is designed to use either 0.5Ω or 0.25Ω
current sense resistors. For new designs 0.25Ω is recom-
mended to reduce power dissipation; the 0.5Ω option is
intended for existing systems where the LTC4274 is used
as a drop-in replacement for the LTC4258 or LTC4259A.
The lower sense resistor values reduce heat dissipation.
Four commonly available 1Ω resistors (0402 or larger
package size) can be used in parallel in place of a single
Ethernet ports can be subject to significant ESD events
when long data cables, each potentially charged to thou-
sands of volts, are plugged into the low impedance of the
RJ45 jack. To protect against damage, the port requires a
pair of clamp diodes; one to AGND and one to V (Figure
EE
10). An additional surge suppressor is required for each
LTC4274 chip from V to AGND. The diodes at the port
EE
steer harmful surges into the supply rails, where they are
0.25Ω resistor. In order to meet the I and I accuracy
absorbed by the surge suppressor and the V bypass
CUT
LIM
EE
required by the IEEE specification, the sense resistors
should have 1% tolerance or better, and no more than
200ppm/°C temperature coefficient.
capacitance. The surge suppressor has the additional
benefit of protecting the LTC4274 from transients on the
V
supply.
EE
S1B diodes work well as port clamp diodes, and an
Output Cap
SMAJ58AorequivalentisrecommendedfortheV surge
EE
The port requires a 0.22ꢁF cap across its output to keep
the LTC4274 stable while in current limit during startup
or overload. Common ceramic capacitors often have sig-
nificant voltage coefficients; this means the capacitance
is reduced as the applied voltage increases. To minimize
this problem, X7R ceramic capacitors rated for at least
100V are recommended.
suppressor.
LAYOUT GUIDELINES
Standard power layout guidelines apply to the LTC4274:
place the decoupling caps for the V and V supplies
DD
EE
near their respective supply pins, use ground planes, and
use wide traces wherever there are significant currents.
4274fa
25
LTC4274
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
0.70 p 0.05
5.50 p 0.05
4.10 p 0.05
3.00 REF
5.15 0.05
3.15 0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
5.5 REF
6.10 p 0.05
7.50 p 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 s 45o CHAMFER
0.75 p 0.05
3.00 REF
5.00 p 0.10
37
38
0.00 – 0.05
0.40 p0.10
PIN 1
TOP MARK
1
2
(SEE NOTE 6)
5.15 0.10
5.50 REF
7.00 p 0.10
3.15 0.10
(UH) QFN REF C 1107
0.200 REF 0.25 p 0.05
R = 0.125
TYP
R = 0.10
TYP
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4274fa
26
LTC4274
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
4/11
Revised entire data sheet
1 to 28
4274fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC4274
TYPICAL APPLICATION
Autonomous Midspan PSE
0.1μF 3.3V
10k
10k
SCL
V
DD
AUTO
MID
RESET
SHDN
MSD
INT
SDAIN
SDAOUT
AD0
AD1
AD2
LTC4274
AD3
DGND AGND
V
SENSE GATE OUT
EE
0.22μF
100V
1μF
100V
S1B
SMAJ58A
–54V
PORT
4274 TA02
R
IRFM120A
SENSE
–54V
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT1619
Low Voltage Current Mode PWM Controller
IEEE 802.3af PD Interface Controller
IEEE 802.3af PD Interface Controller
Quad IEEE 802.3af PoE PSE Controller
Quad IEEE 802.3af PoE PSE Controller
Single IEEE 802.3af PSE Controller
High Power Single PoE PSE Controller
High Power PD Controller
–48V to 3.3V at 300mA, MSOP Package
100V, 400mA Internal Switch, Programmable Class
LTC4257
LTC4257-1
LTC4258
LTC4259A-1
LTC4263
LTC4263-1
LTC4264
LTC4265
LTC4266
100V, 400mA Internal Switch, Dual Current Limit, Programmable Class
DC Disconnect Sensing Only
With Both AC and DC Disconnect Sensing
Internal FET Switch, Autonomous Operation
Internal FET Switch, Autonomous Operation
Internal FET Switch With 750mA Current Limit
100V, 1A Internal Switch, 2-Event Classification Recognition
IEEE 802.3at PD Interface Controller
IEEE 802.3at Quad PSE Controller
Supports IEEE 802.3at Type 1 and 2 PDs, 0.34Ω Channel Resistance, Advanced Power
Management, High-Reliability 4-Point PD Detection, Legacy Capacitance Detect
LTC4267
IEEE 802.3af PD Interface Console with
Integrated Switching Regulator
Internal 100V, 400mA Switch, Dual Inrush Current, Programmable Class
100V, 400mA Internal Switch, Programmable Class, 200kHz Constant Frequency PWM
100V, 400mA Internal Switch, Programmable Class, 300kHz Constant Frequency PWM
No Optocoupler Required
LTC4267-1
LTC4267-3
LTC4268-1
LTC4269-1
LTC4269-2
LTC4278
IEEE 802.3af PD Interface with Integrated
Switching Regulator
IEEE 802.3af PD Interface with Integrated
Switching Regulator
High Power PD with Synchronous Flyback
Controller
IEEE 802.3at PD Interface Console with
Integrated Switching Regulator
2-Event Classification, Programmable Classification, Synchronous No-Opto Flyback
Controller, 50kHz to 250kHz, Auxiliary Support
IEEE 802.3at PD Interface Console with
Integrated Switching Regulator
2-Event Classification, Programmable Classification, Synchronous Forward Controller,
100kHz to 500kHz, Auxiliary Support
IEEE 802.3at PD Interface with Integrated
Switching Regulator
2-Event Classification, Programmable Classification, Synchronous No-Opto Flyback
Controller, 50kHz to 250kHz, 12V Auxiliary Support
2
2
LTC4311
SMBus/I C Accelerator
Improved I C Rise Time, Ensures Data Integrity
4274fa
LT 0411 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
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© LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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