LTC4278CDKD#PBF [Linear]
LTC4278 - IEEE 802.3at PD with Synchronous No-Opto Flyback Controller and 12V Aux Support; Package: DFN; Pins: 32; Temperature Range: 0°C to 70°C;
| 型号： | LTC4278CDKD#PBF |
| 厂家： | 
Linear |
| 描述： | LTC4278 - IEEE 802.3at PD with Synchronous No-Opto Flyback Controller and 12V Aux Support; Package: DFN; Pins: 32; Temperature Range: 0°C to 70°C 开关 光电二极管 |
| 文件： | 总42页 (文件大小：494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4278
IEEE 802.3at PD with
Synchronous No-Opto Flyback
Controller and 12V Aux Support
DESCRIPTION
FEATURES
The LTC®4278 is an integrated Powered Device (PD) con-
troller and switching regulator intended for high power
n
25.5W IEEE 802.3at Compliant (Type 2) PD
10V to 57V Auxiliary Power Input
n
n
Shutdown Pin for Flexible Auxiliary Power Support
Integrated State-of-the-Art No-Opto Synchronous
Flyback Controller
IEEE 802.3at and 802.3af applications. With a wide input
voltagerange,theLTC4278isspecificallydesignedtosup-
port PD applications that include a low-voltage auxiliary
power input such as a 12V wall adaptor. The inclusion of
a shutdown pin provides simple implementation of both
PoE and auxiliary dominate applications. In addition, the
LTC4278supportsboth1-eventand2-eventclassifications
as defined by the IEEE, thereby allowing the use in a wide
range of product configurations.
n
– Isolated Power Supply Efficiency >92%
– 88% Efficiency Including Diode Bridge and
Hot Swap™ FET
n
n
n
n
Superior EMI Performance
Robust 100V 0.7Ω (Typ) Integrated Hot Swap MOSFET
IEEE 802.3at High Power Available Indicator
Integrated Signature Resistor and Programmable
Class Current
Undervoltage, Overvoltage and Thermal Protection
Short-Circuit Protection with Auto-Restart
Programmable Soft-Start and Switching Frequency
Complementary Power Good Indicators
Thermally Enhanced 7mm × 4mm DFN Package
TheLTC4278synchronous,currentmode,flybackcontrol-
ler generates multiple supply rails in a single conversion
stepprovidingforthehighestsystemefficiencywhilemain-
taining tight regulation across all outputs. The LTC4278
includes Linear Technology’s patented No-Opto feedback
topology to provide full IEEE 802.3 isolation without the
need of an opto-isolator circuit. A true soft-start function
allows graceful ramp-up of all output voltages.
n
n
n
n
n
APPLICATIONS
The LTC4278 is available in a space saving 32-lead DFN
package.
L, LT, LTC, LTM, Linear Technology, SwitcherCAD and the Linear logo are registered
trademarks and Hot Swap and ThinSOT are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 5841643.
n
VoIP Phones with Advanced Display Options
n
Dual-Radio Wireless Access Points
n
PTZ Security Cameras
RFID Readers
Industrial Controls
n
n
EPC3472G-LF
TYPICAL APPLICATION
25W PD Solution with 12V Auxiliary
•
0.18µH
5V
8.2µH
4.5A
47µF +
+
•
+
100µF
AUXILIARY
•
10µF
10µF
SUPPLY
(10V TO 57V)
294k
21.5k
3.01k
BSS63
–
1µF
TO MICRO
CONTROLLER
HAT2169
46.4k
FDMS2572
12mΩ
~ +
~ –
54V FROM
DATA PAIR
PDS5100H
0.1µF
+
–
FB
V
PG SENSE
UVLO PWRGD T2P
PORTP
SHDN
CC
V
SENSE
R
CLASS
LTC4278
24k
30.9Ω
~ +
~ –
SG
CMP
54V FROM
SPARE PAIR
2.2nF
V
V
1µF
PORTN
NEG
V
SYNC GND OSC PGDLY
12k
t
ENDLY
100k
R
C
ON
CMP
CMP
•
•
38.3k 1.8k
B1100
33pF
0.1µF
4278 TA01a
4278fc
1
LTC4278
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
TOP VIEW
Pins with Respect to V
PORTN
SHDN
1
2
32 V
PORTP
V
V
V
Voltage......................................... –0.3V to 100V
PORTP
T2P
31 NC
Voltage......................................... –0.3V to V
NEG
NEG
PORTP
R
3
30 PWRGD
29 PWRGD
28 NC
CLASS
NC
Pull-Up Current ..................................................1A
SHDN....................................................... –0.3V to 100V
4
V
V
5
PORTN
R
R
, Voltage............................................ –0.3V to 7V
Source Current...........................................50mA
CLASS
CLASS
6
27
26
V
V
PORTN
NC
NEG
NEG
7
PWRGD Voltage (Note 3)
NC
SG
8
25 NC
33
Low Impedance Source ......V
–0.3V to V
+11V
9
24 PG
NEG
NEG
Sink Current.........................................................5mA
PWRGD, T2P Voltage............................... –0.3V to 100V
PWRGD, T2P Sink Current.....................................10mA
Pins with Respect to GND
V
t
10
11
23 PGDLY
CC
22
21
R
C
ON
CMP
ENDLY 12
SYNC 13
SFST 14
OSC 15
FB 16
CMP
+
20 SENSE
19 SENSE
18 UVLO
–
V
Voltage................................................ –0.3V to 22V
CC
–
+
SENSE , SENSE Voltage........................ –0.5V to +0.5V
UVLO, SYNC Voltage...................................–0.3V to V
FB Current.............................................................. 2mA
17
V
CMP
CC
DKD32 PACKAGE
32-LEAD (7mm × 4mm) PLASTIC DFN
V
Current ......................................................... 1mA
CMP
T
= 125°C,θ = 34°C/W, θ = 2°C/W
JA JC
JMAX
Operating Ambient Temperature Range
GND, EXPOSED PAD (PIN 33) MUST BE SOLDERED TO A
HEAT SINKING PLANE THAT IS CONNECTED TO V
NEG
LTC4278C ................................................ 0°C to 70°C
LTC4278I..............................................–40°C to 85°C
ORDER INFORMATION
LEAD FREE FINISH
LTC4278CDKD#PBF
LTC4278IDKD#PBF
TAPE AND REEL
PART MARKING*
4278
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC4278CDKD#TRPBF
LTC4278IDKD#TRPBF
32-Lead (7mm × 4mm) Plastic DFN
32-Lead (7mm × 4mm) Plastic DFN
4278
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4278fc
2
LTC4278
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Interface Controller (Note 4)
Operating Input Voltage
Signature Range
Classification Range
ON Voltage
At V
(Note 5)
60
9.8
21
V
V
V
V
V
V
PORTP
l
l
l
l
1.5
12.5
37.2
OFF Voltage
30.0
Overvoltage Lockout
71
l
l
l
ON/OFF Hysteresis Window
Signature/Class Hysteresis Window
Reset Threshold
4.1
1.4
V
V
V
State Machine Reset for 2-Event Classification
2.57
5.40
Supply Current
l
l
Supply Current at 57V
Class 0 Current
Measured at V
Pin
1.35
0.40
mA
mA
PORTP
V
= 17.5V, No R
Resistor
PORTP
CLASS
Signature
l
l
l
Signature Resistance
1.5V ≤ V
≤ 9.8V (Note 6)
23.25
26
11
11
kΩ
kΩ
kΩ
PORTP
Invalid Signature Resistance, SHDN Invoked 1.5V ≤ V
≤ 9.8V, V
= 3V (Note 6)
SHDN
PORTP
Invalid Signature Resistance During Mark
Event
(Notes 6, 7)
Classification
l
l
Class Accuracy
10mA < I
< 40mA, 12.5V < V
< 21V
PORTP
3.5
1
%
CLASS
(Notes 8, 9)
Classification Stability Time
V
Pin Step to 17.5V, R
= 30.9, I Within 3.5%
CLASS
ms
PORTP
CLASS
of Ideal Value (Notes 8, 9)
Normal Operation
Inrush Current
l
l
l
V
= 54V, V
= 3V
NEG
60
100
0.7
180
1.0
1
mA
Ω
PORTP
Power FET On-Resistance
Tested at 600mA into V , V
= 54V
NEG PORTP
Power FET Leakage Current at V
Digital Interface
V
= SHDN = V = 57V
NEG
µA
NEG
PORTP
l
l
l
l
SHDN Input High Level Voltage
SHDN Input Low Level Voltage
SHDN Input Resistance
3
V
V
0.45
0.15
V
= 9.8V, SHDN = 9.65V
= 54V. For T2P, Must Complete
100
kΩ
V
PORTP
PWRGD, T2P Output Low Voltage
Tested at 1mA, V
2-Event Classification to See Active Low
PORTP
l
l
PWRGD, T2P Leakage Current
Pin Voltage Pulled 57V, V = V
= 0V
PORTN
1
µA
V
PORTP
PWRGD Output Low Voltage
Tested at 0.5mA, V
= 52V, V
= 48V, Output Voltage
NEG
0.4
PORTP
Is With Respect to V
NEG
l
l
PWRGD Clamp Voltage
PWRGD Leakage Current
Tested at 2mA, V
= 0V, Voltage With Respect to V
12
16.5
1
V
NEG
NEG
V
= 11V, V
= 0V, Voltage With Respect to V
µA
PWRGD
NEG
NEG
4278fc
3
LTC4278
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PWM Controller (Note 10)
Power Supply
l
l
l
V
CC
V
CC
V
CC
Operating Range
Supply Current (I
4.5
4
20
10
V
mA
µA
)
CC
V
V
= Open (Note 11)
6.4
50
CMP
Shutdown Current
= Open, V
= 0V
150
CMP
UVLO
Feedback Amplifier
Feedback Regulation Voltage (V
l
)
FB
1.220
1.237
200
1.251
V
nA
Feedback Pin Input Bias Current
R
CMP
Open
l
l
Feedback Amplifier Transconductance
Feedback Amplifier Source or Sink Current
Feedback Amplifier Clamp Voltage
∆I = 10µA
700
25
1000
55
1400
90
µmho
µA
C
V
FB
V
FB
= 0.9V
= 1.4V
2.56
0.84
V
V
l
Reference Voltage Line Regulation
Feedback Amplifier Voltage Gain
Soft-Start Charging Current
12V ≤ V ≤ 18V
0.005
1400
20
0.05
25
%/V
V/ V
µA
CC
V
CMP
V
SFST
V
SFST
= 1.2V to 1.7V
= 1.5V
16
Soft-Start Discharge Current
= 1.5V, V
= 0V
0.7
1.3
mA
V
UVLO
Control Pin Threshold (V
)
Duty Cycle = Min
1
CMP
Gate Outputs
l
l
l
PG, SG Output High Level
PG, SG Output Low Level
6.6
7.4
0.01
1.6
11
8
V
V
0.05
2.3
PG, SG Output Shutdown Strength
PG Rise Time
V
C
C
C
= 0V; I , I = 20mA
V
UVLO
PG SG
= 1nF
ns
ns
ns
PG
SG
SG Rise Time
= 1nF
15
PG, SG Fall Time
, C = 1nF
PG SG
10
Current Amplifier
+
l
l
l
Switch Current Limit at Maximum V
V
V
C
88
98
110
230
mV
V/ V
mV
CMP
SENSE
∆V
SENSE
/∆V
0.07
206
CMP
+
Sense Voltage Overcurrent Fault Voltage
, V
< 1V
SFST
SENSE
Timing
Switching Frequency (f
)
= 100pF
OSC
84
33
100
110
200
kHz
pF
ns
ns
ns
%
OSC
Oscillator Capacitor Value (C
Minimum Switch On Time (t
)
(Note 12)
OSC
)
200
265
200
88
ON(MIN)
Flyback Enable Delay Time (t
)
ENDLY
PG Turn-On Delay Time (t
)
PGDLY
l
l
Maximum Switch Duty Cycle
SYNC Pin Threshold
85
1.53
40
2.1
V
SYNC Pin Input Resistance
kΩ
4278fc
4
LTC4278
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Load Compensation
+
Load Compensation to V
Voltage
Offset
V
V
with V = 0V
SENSE
0.8
20
mV
µA
SENSE
RCMP
+
Feedback Pin Load Compensation Current
= 20mV, V = 1.230V
FB
SENSE
UVLO Function
l
UVLO Pin Threshold (V
)
1.215
1.240
1.265
V
UVLO
UVLO Pin Bias Current
V
UVLO
V
UVLO
= 1.2V
= 1.3V
–0.25
–4.50
0.1
–3.4
0.25
–2.50
µA
µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 7: An invalid signature after the 1st classification event is mandated
by the IEEE802.3at standard. See the Applications Information section.
Note 8: Class accuracy is with respect to the ideal current defined as
1.237/R
and does not include variations in R
resistance.
CLASS
CLASS
Note 2: Pins with 100V absolute maximum guaranteed for T ≥ 0°C,
otherwise 90V.
Note 3: Active high PWRGD internal clamp self-regulates to 14V with
Note 9: This parameter is assured by design and wafer level testing.
–
Note 10: V = 14V; PG, SG Open; V
= 1.4V, V
= 0V, R
= 1k,
CC
CMP
SENSE
CMP
R
= 90k, R
= 27.4k, R
= 90k, unless otherwise specified. All
tON
PGDLY
ENDLY
respect to V
.
NEG
voltages are with respect to GND.
Note 4: All voltages are with respect to V
pin unless otherwise noted.
PORTN
Note 11: Supply current does not include gate charge current to the
Note 5: Input voltage specifications are defined with respect to LTC4278
pins and meet IEEE 802.3af/at specifications when the input diode bridge
is included.
MOSFETs. See the Applications Information section.
Note 12: Component value range guaranteed by design.
Note 6: Signature resistance is measured via the ∆V/∆I method with the
minimum ∆V of 1V. The LTC4278 signature resistance accounts for the
additional series resistance in the input diode bridge.
4278fc
5
LTC4278
TYPICAL PERFORMANCE CHARACTERISTICS
Input Current vs Input Voltage
25k Detection Range
Input Current vs Input Voltage
Input Current vs Input Voltage
50
40
30
20
0.5
0.4
0.3
0.2
11.0
10.5
T
= 25°C
CLASS 1 OPERATION
T
= 25°C
A
A
CLASS 4
CLASS 3
CLASS 2
CLASS 1
CLASS 0
85°C
–40°C
10.0
9.5
10
0
0.1
0
0
20
30
40
50
60
10
0
4
6
8
10
2
12
14
16
18
20
22
100
60
V
VOLTAGE (V)
V
VOLTAGE (V)
V
VOLTAGE (V)
PORTP
PORTP
PORTP
(RISING)
4278 G01
4278 G03
4278 G02
Signature Resistance
vs Input Voltage
Class Operation vs Time
On-Resistance vs Temperature
28
27
ΔV V2 – V1
RESISTANCE =
DIODES: HD01
=
T
= 25°C
V
A
PORTP
ΔI
I – I
2 1
VOLTAGE
10V/DIV
1.0
0.8
0.6
0.4
0.2
T
= 25°C
A
IEEE UPPER LIMIT
LTC4278 + 2 DIODES
26
25
24
CLASS
CURRENT
10mA/DIV
LTC4278 ONLY
IEEE LOWER LIMIT
23
22
4278 G05
TIME (10µs/DIV)
–50
0
25
50
75
–25
V1:
V2:
1
2
3
4
5
6
7
9
8
10
JUNCTION TEMPERATURE (°C)
V
VOLTAGE (V)
PORTP
4278 G06
4278 G04
PWRGD, T2P Output Low Voltage
vs Current
Active High PWRGD
Output Low Voltage vs Current
Inrush Current vs Input Voltage
1.0
0.8
0.6
0.4
0.2
0
0.8
115
110
105
T
= 25°C
T
= 25°C
PORTP
A
A
V
– V
= 4V
NEG
0.6
0.4
0.2
0
100
95
90
85
0
2
4
6
8
10
1
2
0
0.5
1.5
40
45
50
55
CURRENT (mA)
CURRENT (mA)
V
VOLTAGE (V)
PORTP
4278 G07
4278 G08
4278 G09
4278fc
6
LTC4278
TYPICAL PERFORMANCE CHARACTERISTICS
VCC Shutdown Current
vs Temperature
VCC Current vs Temperature
SENSE Voltage vs Temperature
10
9
110
108
106
104
102
100
98
90
80
70
60
50
40
30
20
10
0
V
= 0
FB = 1.1V
UVLO
+
SENSE = V
SENSE
DYNAMIC CURRENT C = 1nF,
PG
–
WITH V
= 0V
SENSE
C
= 1nF, f
= 100kHz
OSC
SG
8
V
= 14V
CC
7
6
STATIC PART CURRENT
= 14V
96
5
94
4
92
V
CC
3
90
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
50
TEMPERATURE (°C)
125
–50
0
25
75 100
–25
4278 G02
4278 G12
4278 G13
SENSE Fault Voltage
vs Temperature
Oscillator Frequency
vs Temperature
V
FB vs Temperature
1.240
1.239
1.238
1.237
1.236
1.235
1.234
1.233
1.232
1.231
1.230
110
108
106
104
102
100
98
220
215
210
205
200
195
190
185
180
+
SENSE = V
C
= 100pF
OSC
SENSE
–
WITH V
= 0V
SENSE
96
94
92
90
–50
0
25
50
75 100 125
50
75 100 125
–25
–25
0
50
75 100 125
–50
0
25
–50
25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4278 G16
4278 G14
4278 G15
Feedback Pin Input Bias
vs Temperature
Feedback Amplifier Output
Current vs VFB
VFB Reset vs Temperature
70
50
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
300
250
200
150
R
OPEN
125°C
CMP
25°C
–40°C
30
10
–10
–30
–50
–70
100
50
0
–25
0
50
75 100 125
–50
25
50
TEMPERATURE (°C)
100 125
0.9
1
1.3
1.4
1.5
–50 –25
0
25
75
1.1
1.2
(V)
V
TEMPERATURE (°C)
FB
4278 G18
4278 G17
4278 G19
4278fc
7
LTC4278
TYPICAL PERFORMANCE CHARACTERISTICS
Feedback Amplifier Source and
Sink Current vs Temperature
Feedback Amplifier gm
vs Temperature
Feedback Amplifier Voltage Gain
vs Temperature
1700
1650
1600
1550
1500
1450
1400
1350
1300
1250
1200
1150
1100
70
65
60
55
1100
1050
1000
950
SOURCE CURRENT
V
FB
= 1.1V
SINK
CURRENT
V
= 1.4V
FB
50
45
40
900
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
4278 G20
4278 G21
4278 G22
UVLO vs Temperature
IUVLO Hysteresis vs Temperature
1.250
1.245
1.240
1.235
3.7
3.6
3.5
3.4
3.3
3.2
3.1
1.230
1.225
1.220
3.0
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
4278 G23
4278 G24
Soft-Start Charge Current
vs Temperature
PG, SG Rise and Fall Times
vs Load Capacitance
23
22
21
20
19
18
17
16
15
80
70
60
50
40
30
20
10
0
T
= 25°C
A
FALL TIME
RISE TIME
–25
0
50
75 100 125
–50
25
0
1
2
3
4
5
6
7
8
9
10
TEMPERATURE (°C)
CAPACITANCE (nF)
4278 G25
4278 G26
4278fc
8
LTC4278
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum PG On-Time
vs Temperature
Enable Delay Time
vs Temperature
PG Delay Time vs Temperature
325
305
285
265
340
330
320
310
300
290
280
270
260
300
250
R
= 158k
R
ENDLY
= 90k
tON(MIN)
R
= 27.4k
= 16.9k
PGDLY
PGDLY
200
150
100
R
245
225
205
50
0
50
TEMPERATURE (°C)
100 125
–25
0
50
75 100 125
–50 –25
0
25
75
–50
25
–50 –25
0
25
75
50
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
4278 G30
4278 G28
4278 G29
4278fc
9
LTC4278
PIN FUNCTIONS
SHDN (Pin 1): Shutdown Input. Use this pin for auxiliary
power application. Drive SHDN high to disable LTC4278
operation and corrupt the signature resistance. If unused,
SFST (Pin 14): Soft-Start. This pin, in conjunction with a
capacitor (C ) to GND, controls the ramp-up of peak
SFST
primary current through the sense resistor. It is also used
tie SHDN to V
.
to control converter inrush at start-up. The SFST clamps
PORTN
the V
voltage and thus limits peak current until soft-
CMP
T2P(Pin2):Type2PSEIndicator,Open-Drain.Lowimped-
ance indicates the presence of a Type 2 PSE.
start is complete. The ramp time is approximately 70ms
per µF of capacitance. Leave SFST open if not using the
soft-start function.
R
(Pin 3): Class Select Input. Connect a resistor
CLASS
between R
and V
to set the classification load
CLASS
PORTN
OSC (Pin 15): Oscillator. This pin, in conjunction with an
current (see Table 2).
external capacitor (C ) to GND, defines the controller
OSC
NC (Pins 4, 7, 8, 25, 28, 31): No Connect.
oscillator frequency. The frequency is approximately
100kHz • 100/C
(pF).
OSC
V
(Pins 5, 6): Input Voltage, Negative Rail. Pin 5
PORTN
and Pin 6 must be electrically tied together at the package.
FB(Pin16):FeedbackAmplifierInput. Feedbackisusually
sensed via a third winding and enabled during the flyback
period.Thispinalsosinksadditionalcurrenttocompensate
SG (Pin 9): Synchronous Gate Drive Output. This pin
provides an output signal for a secondary-side synchro-
nous rectifier. Large dynamic currents may flow during
voltage transitions. See the Applications Information
section for details.
for load current variation as set by the R
pin. Keep the
CMP
Thevenin equivalent resistance of the feedback divider at
roughly 3k.
V
(Pin 17): Frequency Compensation Control. V
CMP
VCC (Pin 10): Supply Voltage Pin. Bypass this pin to
GND with a low ESR ceramic capacitor. See the Applica-
tions Information section for details.
CMP
is used for frequency compensation of the switcher con-
trol loop. It is the output of the feedback amplifier and
the input to the current comparator. Switcher frequency
compensation components are placed on this pin to GND.
The voltage on this pin is proportional to the peak primary
switch current. The feedback amplifier output is enabled
during the synchronous switch on time.
t
(Pin 11): Pin for external programming resistor to
ON
set the minimum time that the primary switch is on for
each cycle. Minimum turn-on facilitates the isolated feed-
back method. See the Applications Information section
for details.
UVLO (Pin 18): Undervoltage Lockout. A resistive divider
fromV
upon V
its threshold, the gate drives are disabled, but the part
draws its normal quiescent current from V .
ENDLY (Pin 12): Pin for external programming resistor to
set enable delay time. The enable delay time disables the
feedback amplifier for a fixed time after the turn-off of the
primary-side MOSFET. This allows the leakage inductance
voltage spike to be ignored for flyback voltage sensing.
See the Applications Information section for details.
tothispinsetsanundervoltagelockoutbased
PORTP
level (not V ). When the UVLO pin is below
PORTP
CC
CC
The bias current on this pin has hysteresis such that the
biascurrentissourcedwhenUVLOthresholdisexceeded.
Thisintroducesahysteresisatthepinequivalenttothebias
current change times the impedance of the upper divider
resistor. The user can control the amount of hysteresis
by adjusting the impedance of the divider. Tie the UVLO
SYNC (Pin 13): External Sync Input. This pin is used to
synchronize the internal oscillator with an external clock.
The positive edge of the clock causes the oscillator to dis-
charge causing PG to go low (off) and SG high (on). The
sync threshold is typically 1.5V. Tie to ground if unused.
See the Applications Information section for details.
pin to V if not using this function. See the Applications
CC
4278fc
10
LTC4278
PIN FUNCTIONS
Information section for details. This pin is used for the
UVLOfunctionoftheswitchingregulator. ThePDinterface
section has an internal UVLO.
PGDLY (Pin 23): Primary Gate Delay Control. Connect an
external programming resistor (R
) to set delay from
PGDLY
synchronous gate turn-off to primary gate turn-on. See
the Applications Information section for details.
–
+
SENSE , SENSE (Pins 19, 20): Current Sense Inputs.
These pins are used to measure primary-side switch cur-
rent through an external sense resistor. Peak primary-side
current is used in the converter control loop. Make Kelvin
PG (Pin 24): Primary Gate Drive. PG is the gate drive pin
for the primary-side MOSFET switch. Large dynamic cur-
rents flow during voltage transitions. See the Applications
Information section for details.
connections to the sense resistor R
to reduce noise
SENSE
–
problems.SENSE connectstotheGNDside.Atmaximum
V
(Pins 26, 27): System Negative Rail. Connects V
NEG
PORTN
NEG
to V
current (V
at its maximum voltage) SENSE pins have
CMP
through an internal power MOSFET. Pin 26 and
100mV threshold. The signal is blanked (ignored) during
Pin 27 must be electrically tied together at the package.
the minimum turn-on time.
PWRGD (Pin 29): Power Good Output, Open-Collector.
High impedance signals power-up completion. PWRGD
C
(Pin 21): Load Compensation Capacitive Control.
CMP
Connect a capacitor from C
to GND in order to reduce
CMP
is referenced to V
and features a 14V clamp.
NEG
the effects of parasitic resistances in the feedback sensing
path. A 0.1µF ceramic capacitor suffices for most applica-
tions. Short this pin to GND when load compensation is
not needed.
PWRGD (Pin 30): Complementary Power Good Output,
Open-Drain.Lowimpedancesignalspower-upcompletion.
PWRGD is referenced to V
.
PORTN
V
(Pin 32): Positive Power Input. Tie to the input
R
(Pin 22): Load Compensation Resistive Control.
PORTP
CMP
port power through the input diode bridge.
Connect a resistor from R
to GND in order to com-
CMP
pensate for parasitic resistances in the feedback sensing
path. In less demanding applications, this resistor is not
needed and this pin can be left open. See the Applications
Information section for details.
Exposed Pad (Pin 33): Ground. This is the negative rail
connectionforbothsignalgroundandgatedrivergrounds
of the flyback controller. This pin should be connected to
V
NEG
.
4278fc
11
LTC4278
BLOCK DIAGRAM
CLASSIFICATION
CURRENT LOAD
V
SHDN
1
PORTP
32
31
30
1.237V
+
–
16k 25k
T2P
2
R
CLASS
NC
3
PWRGD
PWRGD
CONTROL
CIRCUITS
4
5
NC
29
V
PORTN
PORTN
14V
V
V
NEG
6
7
27
26
V
NEG
BOLD LINE INDICATES
HIGH CURRENT PATH
NC
NC
8
V
CC
CLAMPS
10
0.7
1.3
+
FB
16
17
ERROR AMP
–
+
–
1.237V
V
CMP
REFERENCE
3V
(V )
FB
INTERNAL
REGULATOR
DISABLE
S
R
Q
Q
+
–
0.8V
COLLAPSE DETECT
–
–
+
+
–
UVLO
+
UVLO
SFST
1V
18
14
19
CURRENT
COMPARATOR
OVERCURRENT
FAULT
I
UVLO
–
+
–
TSD
–
SENSE
CURRENT
SENSE AMP
+
CURRENT TRIP
+
SENSE
SLOPE COMPENSATION
ENABLE
20
21
R
CMPF
50k
OSC
15
OSCILLATOR
C
CMP
SET
+
–
SYNC
13
11
23
12
LOAD
COMPENSATION
t
ON
LOGIC
BLOCK
R
CMP
PG
PGDLY
ENDLY
TO FB
22
24
GATE DRIVE
PGATE
SGATE
+
NC
NC
25
28
3V
–
GATE DRIVE
SG
9
GND
33
(EXPOSED PAD)
4278 BD
4278fc
12
LTC4278
APPLICATIONS INFORMATION
OVERVIEW
50
40
30
20
10
Power over Ethernet (PoE) continues to gain popularity
as more products are taking advantage of having DC
power and high speed data available from a single RJ45
connector. As PoE continues to grow in the marketplace,
powered device (PD) equipment vendors are running into
the 12.95W power limit established by the IEEE 802.3af
standard.
ON
OFF
CLASSIFICATION
DETECTION V2
TIME
DETECTION V1
50
40
30
20
10
dV
dt
INRUSH
C1
=
TheIEE802.3atstandardestablishesahigherpoweralloca-
tion for Power over Ethernet while maintaining backwards
compatibility with the existing IEEE 802.3af systems.
Powersourcingequipment(PSE)andpowereddevicesare
distinguished as Type 1 complying with the IEEE 802.3af/
IEEE 802.3at power levels, or Type 2 complying with the
IEEE 802.3at power levels. The maximum available power
of a Type 2 PD is 25.5W.
OFF
ON
OFF
τ = R
C1
LOAD
TIME
TIME
–10
–20
–30
–40
–50
POWER
BAD
POWER
BAD
POWER
GOOD
PWRGD
PWRGD
TRACKS
TRACKS
V
V
PORTP
PORTP
The IEEE 802.3at standard also establishes a new method
ofacquiringpowerclassificationfromaPDandcommuni-
cating the presence of a Type 2 PSE. A Type 2 PSE has the
option of acquiring PD power classification by performing
2-event classification (layer 1) or by communicating with
the PD over the data line (layer 2). In turn, a Type 2 PD
must be able to recognize both layers of communications
and identify a Type 2 PSE.
PWRGD TRACKS
V
PORTN
20
10
POWER
BAD
POWER
GOOD
POWER
BAD
IN DETECTION
RANGE
TIME
LOAD, I
LOAD
The LTC4278 is specifically designed to support the front
end of a PD that must operate under the IEEE 802.3at
standard. In particular, the LTC4278 provides the T2P
indicator bit which recognizes 2-event classification. This
indicator bit may be used to alert the LTC4278 output load
that a Type 2 PSE is present. With an internal signature
resistor, classification circuitry, inrush control, and ther-
mal shutdown, the LTC4278 is a complete PD Interface
solution capable of supporting in the next generation PD
applications.
INRUSH
CLASSIFICATION
TIME
DETECTION I
2
DETECTION I
V1 – 2 DIODE DROPS
1
V2 – 2 DIODE DROPS
25kΩ
SELECTION
I
I
=
I
=
1
2
25kΩ
DEPENDENT ON R
CLASS
CLASS
INRUSH = 100mA
V
R
PORTP
I
=
LOAD
LOAD
MODES OF OPERATION
LTC4278
R
I
LOAD
IN
R
V
PORTP
CLASS
The LTC4278 has several modes of operation depending
on the input voltage applied between the V
PSE
R
PWRGD
C1
CLASS
and
PORTP
PWRGD
V
pins. Figure 1 presents an illustration of voltage
V
V
NEG
PORTN
PORTN
4278 F01
and current waveforms the LTC4278 may encounter with
Figure 1. VNEG, PWRGD, PWRGD and PD
Current as a Function of Input Voltage
the various modes of operation summarized in Table 1.
4278fc
13
LTC4278
APPLICATIONS INFORMATION
Table 1. LTC4278 Modes of Operation as a Function
of Input Voltage
The input diode bridge introduces a voltage drop that
affects the range for each mode of operation. The
LTC4278 compensates for these voltage drops so that a
PD built with the LTC4278 meets the IEEE 802.3af/IEEE
802.3at-established voltage ranges. Note the Electrical
CharacteristicsarereferencedwithrespecttotheLTC4278
package pins.
V
–V
(V) LTC4278 MODES OF OPERATION
PORTP PORTN
0V to 1.4V
Inactive (Reset After 1st Classification Event)
1.5V to 9.8V
(5.4V to 9.8V)
25k Signature Resistor Detection Before 1st
Classification Event (Mark, 11k Signature
Corrupt After 1st Classification Event)
12.5V to ON/OFF*
ON/OFF* to 60V
>71V
Classification Load Current Active
Inrush and Power Applied To PD Load
DETECTION
Overvoltage Lockout,
Classification and Hot Swap Are Disabled
During detection, the PSE looks for a 25k signature resis-
tor which identifies the device as a PD. The PSE will apply
two voltages in the range of 2.8V to 10V and measures
the corresponding currents. Figure 1 shows the detection
voltages V1 and V2 and the corresponding PD current.
The PSE calculates the signature resistance using the ΔV/
ΔI measurement technique.
*ON/OFF includes hysteresis. Rising input threshold, 37.2V Max.
Falling input threshold, 30V Min.
These modes satisfy the requirements defined in the
IEEE 802.3af/IEEE 802.3at specification.
INPUT DIODE BRIDGE
TheLTC4278presentsitsprecision,temperature-compen-
In the IEEE 802.3af/IEEE 802.3at standard, the modes of
operation reference the input voltage at the PD’s RJ45
connector. Since the PD must handle power received in
either polarity from either the data or the spare pair, input
diode bridges BR1 and BR2 are connected between the
RJ45 connector and the LTC4278 (Figure 2).
sated 25k resistor between the V
and V
pins,
PORTP
PORTN
alerting the PSE that a PD is present and requests power
to be applied. The LTC4278 signature resistor also com-
pensatesfortheadditionalseriesresistanceintroducedby
the input diode bridge. Thus a PD built with the LTC4278
conforms to the IEEE 802.3af/IEEE 802.3at specifications.
RJ45
+
1
T1
TX
BR1
–
TX
2
3
+
TO PHY
RX
–
RX
POWERED
DEVICE
(PD)
6
V
PORTP
+
SPARE
INPUT
BR2
4
5
LTC4278
0.1µF
100V
D3
V
PORTN
7
8
4278 F02
–
SPARE
Figure 2. PD Front End Using Diode Bridges on Main and Spare Inputs
4278fc
14
LTC4278
APPLICATIONS INFORMATION
SIGNATURE CORRUPT OPTION
Table 2. Summary of Power Classifications and LTC4278
RCLASS Resistor Selection
In some designs that include an auxiliary power option,
it is necessary to prevent a PD from being detected by a
PSE. The LTC4278 signature resistance can be corrupted
with the SHDN pin (Figure 3). Taking the SHDN pin high
will reduce the signature resistor below 11k which is an
invalid signature per the IEEE 802.3af/IEEE 802.3at speci-
fication, and alerts the PSE not to apply power. Invoking
the SHDN pin also ceases operation for classification and
disconnects the LTC4278 load from the PD input. If this
CLASS
USAGE
MAXIMUM
NOMINAL
LTC4278
CLASS
POWER LEVELS CLASSIFICATION
R
AT INPUT OF PD LOAD CURRENT RESISTOR
(W)
(mA)
< 0.4
10.5
18.5
28
(Ω, 1%)
Open
124
0
1
2
3
4
Type 1
Type 1
Type 1
Type 1
Type 2
0.44 to 12.95
0.44 to 3.84
3.84 to 6.49
6.49 to 12.95
12.95 to 25.5
69.8
45.3
40
30.9
feature is not used, connect SHDN to V
.
PORTN
2-EVENT CLASSIFICATION AND THE T2P PIN
LTC4278
V
PORTP
A Type 2 PSE may declare the availability of high power by
performing a 2-event classification (layer 1) or by com-
municating over the high speed data line (layer 2). A Type
2 PD must recognize both layers of communication. Since
layer 2 communication takes place directly between the
PSE and the LTC4278 load, the LTC4278 concerns itself
only with recognizing 2-event classification.
25k SIGNATURE
RESISTOR
TO
16k
PSE
SHDN
V
PORTN
4278 F03
SIGNATURE DISABLE
Figure 3. 25k Signature Resistor with Disable
In 2-event classification, a Type 2 PSE probes for power
classification twice. Figure 4 presents an example of a
2-event classification. The 1st classification event occurs
when the PSE presents an input voltage between 15.5V
to 20.5V and the LTC4278 presents a class 4 load cur-
rent. The PSE then drops the input voltage into the mark
voltage range of 7V to 10V, signaling the 1st mark event.
The PD in the mark voltage range presents a load current
between 0.25mA to 4mA.
CLASSIFICATION
Classification provides a method for more efficient power
allocation by allowing the PSE to identify a PD power clas-
sification. Class 0 is included in the IEEE specification for
PDsthatdonotsupportclassification. Class1-3partitions
PDs into three distinct power ranges. Class 4 includes the
new power range under IEEE802.3at (see Table 2).
During classification probing, the PSE presents a fixed
voltage between 15.5V and 20.5V to the PD (Figure 1).
The LTC4278 asserts a load current representing the PD
power classification. The classification load current is
The PSE repeats this sequence, signaling the 2nd Clas-
sification and 2nd mark event occurrence. This alerts the
LTC4278 that a Type 2 PSE is present. The Type 2 PSE
then applies power to the PD and the LTC4278 charges
up the reservoir capacitor C1 with a controlled inrush cur-
rent. When C1 is fully charged, and the LTC4278 declares
power good, the T2P pin presents an active low signal, or
programmed with a resistor R
Table 2.
that is chosen from
CLASS
low impedance output with respect to V
. The T2P
PORTN
output becomes inactive when the LTC4278 input voltage
falls below undervoltage lockout threshold.
4278fc
15
LTC4278
APPLICATIONS INFORMATION
SIGNATURE CORRUPT DURING MARK
50
As a member of the IEEE 802.3at working group, Linear
Technology noted that it is possible for a Type 2 PD to
receive a false indication of a 2-event classification if a
PSE port is pre-charged to a voltage above the detection
voltage range before the first detection cycle. The IEEE
working group modified the standard to prevent this pos-
sibility by requiring a Type 2 PD to corrupt the signature
resistance during the mark event, alerting the PSE not to
apply power. The LTC4278 conforms to this standard by
corrupting the signature resistance. This also discharges
the port before the PSE begins the next detection cycle.
40
1st CLASS
30
2nd CLASS
ON
OFF
20
10
DETECTION V1
DETECTION V2
1st MARK 2nd MARK
INRUSH
LOAD, I
LOAD
1st CLASS
2nd CLASS
40mA
TIME
PD STABILITY DURING CLASSIFICATION
DETECTION V1
DETECTION V2
1st MARK 2nd MARK
Classificationpresentsachallengingstabilityproblemdue
to the wide range of possible classification load current.
The onset of the classification load current introduces a
voltage drop across the cable and increases the forward
voltage of the input diode bridge. This may cause the PD
to oscillate between detection and classification with the
onset and removal of the classification load current.
50
40
30
20
10
dV
dt
INRUSH
C1
=
OFF
ON
OFF
τ = R
C1
LOAD
TIME
TIME
The LTC4278 prevents this oscillation by introducing a
voltagehysteresiswindowbetweenthedetectionandclas-
sification ranges. The hysteresis window accommodates
the voltage changes a PD encounters at the onset of the
classification load current, thus providing a trouble-free
transition between detection and classification modes.
–10
–20
–30
–40
–50
TRACKS
V
PORTN
TheLTC4278alsomaintainsapositiveI-Vslopethroughout
the classification range up to the on-voltage. In the event
a PSE overshoots beyond the classification voltage range,
the available load current aids in returning the PD back
into the classification voltage range. (The PD input may
otherwise be “trapped” by a reverse-biased diode bridge
and the voltage held by the 0.1μF capacitor).
INRUSH = 100mA
R
= 30.9Ω
CLASS
V
R
PORTN
I
=
LOAD
LOAD
LTC4278
R
I
LOAD
IN
R
V
CLASS PORTP
PSE
R
C1
CLASS
T2P
V
V
NEG
PORTN
4278 F04
INRUSH CURRENT
Figure 4. VNEG, T2P and PD Current
as a Result of 2-Event Classification
Once the PSE detects and optionally classifies the PD,
the PSE then applies powers on the PD. When the
LTC4278inputvoltagerisesabovetheon-voltagethreshold,
LTC4278 connects V
power MOSFET.
to V
through the internal
NEG
PORTN
4278fc
16
LTC4278
APPLICATIONS INFORMATION
To control the power-on surge currents in the system, the
LTC4278 provides a fixed inrush current, allowing C1 to
ramp up to the line voltage in a controlled manner.
is disconnected, and classification mode resumes. C1
discharges through the LTC4278 circuitry.
COMPLEMENTARY POWER GOOD
The LTC4278 keeps the PD inrush current below the PSE
current limit to provide a well controlled power-up charac-
teristicthatisindependentofthePSEbehavior.Thisensures
a PD using the LTC4278 interoperability with any PSE.
WhenLTC4278fullychargestheloadcapacitor(C1),power
good is declared and the LTC4278 load can safely begin
operation. The LTC4278 provides complementary power
good signals that remain active during normal operation
and are de-asserted when the input voltage falls below
the OFF threshold, when the input voltage exceeds the
overvoltage lockout (OVLO) threshold, or in the event of
a thermal shutdown (see Figure 6).
TURN-ON/ TURN-OFF THRESHOLD
The IEEE 802.3af/at specification for the PD dictates a
maximum turn-on voltage of 42V and a minimum turn-off
voltage of 30V. This specification provides an adequate
voltage to begin PD operation, and to discontinue PD
operation when the input voltage is too low. In addition,
this specification allows PD designs to incorporate an ON/
OFF hysteresis window to prevent start-up oscillations.
The PWRGD pin features an open collector output refer-
enced to V
which can interface directly with the UVLO
NEG
pin. When power good is declared and active, the PWRGD
pinishighimpedancewithrespecttoV .Aninternal14V
clamp protects the UVLO pin from an excessive voltage.
NEG
The LTC4278 features an ON/OFF hysteresis window (see
Figure 5) that conforms with the IEEE 802.3af/at specifi-
cation and accommodates the voltage drop in the cable
and input diode bridge at the onset of the inrush current.
The active low PWRGD pin connects to an internal, open-
drain MOSFET referenced to V
and may be used as
PORTN
an indicator bit when power good is declared and active.
The PWRGD pin is low impedance with respect to V
.
PORTN
Once C1 is fully charged, the LTC4278 turns on is internal
MOSFET and passes power to the PD load. The LTC4278
continuestopowerthePDloadaslongastheinputvoltage
does not fall below the OFF threshold. When the LTC4278
input voltage falls below the OFF threshold, the PD load
LTC4278
30 PWRGD
OVLO
ON/OFF
TSD
CONTROL
CIRCUIT
29 PWRGD
C1
+
LTC4278
PD
LOAD
V
PORTP
5µF
V
V
5
6
27
26
V
V
PORTN
NEG
MIN
TO
PSE
ON/OFF AND
OVERVOLTAGE
LOCKOUT
NEG
PORTN
CIRCUIT
BOLD LINE INDICATES HIGH CURRENT PATH
INRUSH COMPLETE
V
V
NEG
PORTN
4278 F05
CURRENT-LIMITED
TURN ON
ON < V
< OVLO
PORTP
AND NOT IN THERMAL SHUTDOWN
V
– V
LTC4278
PORTP
PORTN
VOLTAGE
0V TO ON*
>ON*
POWER MOSFET
OFF
ON
OFF
OFF
POWER
POWER
GOOD
<OFF*
>OVLO
NOT
GOOD
*INCLUDES ON/OFF HYSTERESIS
ON THRESHOLD ≅ 36.1V
OFF THRESHOLD ≅ 30.7V
OVLO THRESHOLD ≅ 71.0V
V
< OFF
PORTP
> OVLO
V
PORTP
OR THERMAL SHUTDOWN
4278 F06
Figure 5. LTC4278 ON/OFF and Overvoltage Lockout
Figure 6. LTC4278 Power Good Functional and State Diagram
4278fc
17
LTC4278
APPLICATIONS INFORMATION
PWRGD PIN WHEN SHDN IS INVOKED
isolation transformer must also include a center tap on
the RJ45 connector side (see Figure 7).
InPDapplicationswhereanauxiliarypowersupplyinvokes
the SHDN feature, the PWRGD pin becomes high imped-
ance. This prevents the PWRGD pin that is connected to
the UVLO pin from interfering with the DC/DC converter
operations when powered by an auxiliary power supply.
The increased current levels in a Type 2 PD over a Type
1 increase the current imbalance in the magnetics which
can interfere with data transmission. In addition, proper
termination is also required around the transformer to
providecorrectimpedancematchingandtoavoidradiated
and conducted emissions. Transformer vendors such as
Bel Fuse, Coilcraft, Halo, Pulse, and Tyco (Table 4) can
assist in selecting an appropriate isolation transformer
and proper termination methods.
OVERVOLTAGE LOCKOUT
The LTC4278 includes an overvoltage lockout (OVLO)
feature (Figure 6) which protects the LTC4278 and its load
fromanovervoltageevent. Iftheinputvoltageexceedsthe
OVLO threshold, the LTC4278 discontinues PD operation.
Normal operations resume when the input voltage falls
below the OVLO threshold and when C1 is charged up.
Table 4. Power over Ethernet Transformer Vendors
VENDOR
CONTACT INFORMATION
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
www.belfuse.com
THERMAL PROTECTION
Coilcraft Inc.
1102 Silver Lake Road
Gary, IL 60013
Tel: 847-639-6400
www.coilcraft.com
TheIEEE802.3af/atspecificationrequiresaPDtowithstand
any applied voltage from 0V to 57V indefinitely. However,
there are several possible scenarios where a PD may
encounter excessive heating.
Halo Electronics
PCA Electronics
Pulse Engineering
Tyco Electronics
1861 Landings Drive
Mountain View, CA 94043
Tel: 650-903-3800
During classification, excessive heating may occur if the
PSEexceedsthe75msprobingtimelimit.Atturn-on,when
the load capacitor begins to charge, the instantaneous
power dissipated by the PD interface can be large before
it reaches the line voltage. And if the PD experiences a
fast input positive voltage step in its operational mode
(for example, from 37V to 57V), the instantaneous power
dissipated by the PD Interface can be large.
www.haloelectronics.com
16799 Schoenborn Street
North Hills, CA 91343
Tel: 818-892-0761
www.pca.com
12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
www.pulseeng.com
308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
The LTC4278 includes a thermal protection feature which
protects the LTC4278 from excessive heating. If the
LTC4278 junction temperature exceeds the over-temper-
ature threshold, the LTC4278 discontinues PD operations
and power good becomes inactive. Normal operation
resumes when the junction temperature falls below the
overtemperature threshold and when C1 is charged up.
www.circuitprotection.com
Input Diode Bridge
Figure 2 shows how two diode bridges are typically con-
nected in a PD application. One bridge is dedicated to the
data pair while the other bridge is dedicated to the spare
pair. The LTC4278 supports the use of either silicon or
Schottkyinputdiodebridges. However, therearetradeoffs
in the choice of diode bridges.
EXTERNAL INTERFACE AND COMPONENT SELECTION
Transformer
Nodes on an Ethernet network commonly interface to the
outside world via an isolation transformer. For PDs, the
4278fc
18
LTC4278
APPLICATIONS INFORMATION
An input diode bridge must be rated above the maximum
current the PD application will encounter at the tempera-
ture the PD will operate. Diode bridge vendors typically
call out the operating current at room temperature, but
derate the maximum current with increasing temperature.
Consultthediodebridgevendorsfortheoperatingcurrent
derating curve.
One solution to consider is to reconnect the diode bridges
so that only one of the four diodes conducts current in
each package. This configuration extends the maximum
operating current while maintaining a smaller package
profile. Figure 7 shows how to reconnect the two diode
bridges. Consult the diode bridge vendors for the derating
curve when only one of four diodes is in operation.
Asilicondiodebridgecanconsumeover4%oftheavailable
power in some PD applications. Using Schottky diodes can
help reduce the power loss with a lower forward voltage.
Input Capacitor
The IEEE 802.3af/at standard includes an impedance
requirement in order to implement the AC disconnect
function. A 0.1µF capacitor (C14 in Figure 7) is used to
meet this AC impedance requirement.
A Schottky bridge may not be suitable for some high
temperature PD application. The leakage current has a
voltagedependencythatcanreducetheperceivedsignature
resistance. In addition, the IEEE 802.3af/at specification
mandates the leakage back-feeding through the unused
bridge cannot generate more than 2.8V across a 100k
resistor when a PD is powered with 57V.
Transient Voltage Suppressor
The LTC4278 specifies an absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events.
However, the pins that interface to the outside world can
routinely see excessive peak voltages. To protect the
LTC4278, install a transient voltage suppressor (D3) be-
tween the input diode bridge and the LTC4278 as shown
in Figure 7.
Sharing Input Diode Bridges
At higher temperatures, a PD design may be forced to
consider larger bridges in a bigger package because the
maximum operating current for the input diode bridge is
drasticallyderated. Thelarger packagemay notbeaccept-
able in some space-limited environments.
RJ45
+
1
TX
14 T1
12
1
3
BR1
HD01
–
TX
13
10
2
5
2
3
+
TO PHY
RX
11
9
4
6
–
RX
6
COILCRAFT
ETHI - 230LD
V
PORTP
+
–
SPARE
SPARE
4
5
7
8
BR2
HD01
C1
LTC4278
C14
0.1µF
100V
D3
SMAJ58A
TVS
V
V
PORTN
NEG
4278 F07
B1100
Figure 7. PD Front-End with Isolation Transformer, Diode Bridges,
Capacitors, and a Transient Voltage Suppressor (TVS)
4278fc
19
LTC4278
APPLICATIONS INFORMATION
Classification Resistor (R
)
CLASS
+
V
V
PORTP
The R
resistor sets the classification load current,
CLASS
R
P
corresponding to the PD power classification. Select the
value of R from Table 2 and connect the resistor
TO
PSE
LTC4278
CLASS
between the R
TO PD LOAD
and V
pins as shown in Figure
CLASS
PORTN
V
–54V
T2P
PORTN
4, or float the R
pin if the classification load cur-
CLASS
rent is not required. The resistor tolerance must be 1%
or better to avoid degrading the overall accuracy of the
classification circuit.
OPTION 1: SERIES CONFIGURATION FOR ACTIVE LOW/LOW IMPEDANCE OUTPUT
+
V
Load Capacitor
V
PORTP
R
P
The IEEE 802.3af/at specification requires that the PD
maintains a minimum load capacitance of 5μF and does
not specify a maximum load capacitor. However, if the
load capacitor is too large, there may be a problem with
inadvertent power shutdown by the PSE.
LTC4278
TO
PSE
T2P
TO PD LOAD
V
V
NEG
–54V
PORTN
4278 F08
OPTION 2: SHUNT CONFIGURATION FOR ACTIVE HIGH/OPEN COLLECTOR OUTPUT
ThisoccurswhenthePSEvoltagedropsquickly. Theinput
diode bridge reverses bias, and the PD load momentarily
powers off the load capacitor. If the PD does not draw
power within the PSE’s 300ms disconnection delay, the
PSE may remove power from the PD. Thus, it is necessary
to evaluate the load current and capacitance to ensure that
an inadvertent shutdown cannot occur.
Figure 8. T2P Interface Examples
DC converter isolation barrier. The pull-up resistor R is
P
sized according to the requirements of the opto-isolator
operating current, the pull-down capability of the T2P pin,
+
+
and the choice of V . V for example can come from the
PoE supply rail (which the LTC4278 V
is tied to), or
PORTP
The load capacitor can store significant energy when fully
charged. The PD design must ensure that this energy is
not inadvertently dissipated in the LTC4278. For example,
from the voltage source that supplies power to the DC/
DC converter. Option 1 has the advantage of not drawing
power unless T2P is declared active.
if the V
pin shorts to V
while the capacitor
PORTP
PORTN
is charged, current will flow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4278.
Shutdown Interface
To corrupt the signature resistance, the SHDN pin can be
driven high with respect to V
. If unused, connect
PORTN
SHDN directly to V
.
PORTN
T2P Interface
When a 2-event classification sequence successfully
completes, the LTC4278 recognizes this sequence, and
provides an indicator bit, declaring the presence of a
Type 2 PSE. The open-drain output provides the option
to use this signal to communicate to the LTC4278 load,
or to leave the pin unconnected.
Auxiliary Power Source
In some applications, it is desirable to power the PD from
an auxiliary power source such as a wall adapter.
Auxiliary power can be injected into an LTC4278-based
PD at the input of the LTC4278 V
, at V , or even
PORTN
NEG
the power supply output. In addition, some PD applications
Figure 8 shows two interface options using the T2P pin
and the opto-isolator. The T2P pin is active low and con-
nects to an opto-isolator to communicate across the DC/
maydesireauxiliarysupplydominanceormaybeconfigured
4278fc
20
LTC4278
APPLICATIONS INFORMATION
for PoE dominance. Furthermore, PD applications may
alsooptforaseamlesstransition—thatis, withoutpower
disruption — between PoE and auxiliary power.
Type 2 PSE, the IEEE 802.3at standard requires the PD to
wait 80ms in 12.95W operation before 25.5W operation
can commence.
The most common auxiliary power option injects power at
NEG
MAINTAIN POWER SIGNATURE
V
. Figure 9 presents an example of this application. In
thisexample, theauxiliaryportinjects48Vontothelinevia
diode D1. The components surrounding the SHDN pin are
selected so that the LTC4278 does not disconnect power
to the output until the auxiliary supply exceeds 36V.
In an IEEE 802.3af/at system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically
draw at least 10mA and also have an AC impedance less
than 26.25k in parallel with 0.05μF. If one of these condi-
tions is not met, the PSE may disconnect power to the PD.
This configuration is an auxiliary-dominant configuration.
Thatis,theauxiliarypowersourcesuppliesthepowereven
if PoE power is already present. This configuration also
providesaseamlesstransitionfromPoEtoauxiliarypower
when auxiliary power is applied, however, the removal of
auxiliary power to PoE power is not seamless.
SWITCHING REGULATOR OVERVIEW
The LTC4278 includes a current mode converter designed
specificallyforuseinanisolatedflybacktopologyemploying
synchronousrectification.TheLTC4278operationissimilar
totraditionalcurrentmodeswitchers.Themajordifference
is that output voltage feedback is derived via sensing the
output voltage through the transformer. This precludes
the need of an opto-isolator in isolated designs, thus
greatly improving dynamic response and reliability. The
LTC4278 has a unique feedback amplifier that samples a
transformerwindingvoltageduringtheflybackperiodand
uses that voltage to control output voltage. The internal
blocks are similar to many current mode controllers.
The differences lie in the feedback amplifier and load
Contact Linear Technology applications support for detail
information on implementing a custom auxiliary power
supply.
IEEE 802.3at SYSTEM POWER-UP REQUIREMENT
Under the IEEE 802.3at standard, a PD must operate under
12.95W in accordance with IEEE 802.3at standard until it
recognizesaType2PSE.InitializingPDoperationin12.95W
mode eliminates interoperability issue in case a Type 2
PD connects to a Type 1 PSE. Once the PD recognizes a
RJ45
+
1
TX
T1
TVS
+
–
–
0.1µF
TX
C1
2
3
100V
+
TO PHY
RX
BR1
BR2
–
RX
6
36V
V
100k
10k
PORTP
+
–
SPARE
LTC4278
GND
+
–
4
5
7
8
SHDN
10k
SPARE
V
V
NEG
PORTN
+
ISOLATED
WALL
TRANSFORMER
D1
–
4278 F09
Figure 9. Auxiliary Power Dominant PD Interface Example
4278fc
21
LTC4278
APPLICATIONS INFORMATION
compensation circuitry. The logic block also contains
circuitry to control the special dynamic requirements of
flyback control. For more information on the basics of
current mode switcher/controllers and isolated flyback
converters see Application Note 19.
Combining this with the previous V
expression yields
FLBK
an expression for V
in terms of the internal reference,
OUT
programming resistors and secondary resistances:
R1+R2
R2
VOUT
=
• VFB •NSF −I • ESR+R
(
)
SEC
DS(ON)
Feedback Amplifier—Pseudo DC Theory
The effect of nonzero secondary output impedance is
discussed in further detail (see Load Compensation
Theory).Thepracticalaspectsofapplyingthisequationfor
OUT
Information.
For the following discussion, refer to the simplified
Switching Regulator Feedback Amplifier diagram (Figure
10A).Whentheprimary-sideMOSFETswitchMPturnsoff,
V
are found in subsequent sections of the Applications
itsdrainvoltagerisesabovetheV
rail.Flybackoccurs
PORTP
when the primary MOSFET is off and the synchronous
secondary MOSFET is on. During flyback the voltage on
nondriventransformerpinsisdeterminedbythesecondary
voltage. The amplitude of this flyback pulse, as seen on
the third winding, is given as:
Feedback Amplifier Dynamic Theory
So far, this has been a pseudo-DC treatment of flyback
feedback amplifier operation. But the flyback signal is a
pulse, not a DC level. Provision is made to turn on the
flyback amplifier only when the flyback pulse is present,
using the enable signal as shown in the timing diagram
(Figure 10b).
V
+ I
• ESR + R
(
)
OUT
SEC
DS(ON)
V
=
FLBK
N
SF
R
= on-resistance of the synchronous MOSFET MS
DS(ON)
Minimum Output Switch On Time (t
)
ON(MIN)
I
= transformer secondary current
SEC
The LTC4278 affects output voltage regulation via flyback
pulse action. If the output switch is not turned on, there
is no flyback pulse and output voltage information is
not available. This causes irregular loop response and
start-up/latchup problems. The solution is to require the
primary switch to be on for an absolute minimum time per
each oscillator cycle. To accomplish this the current limit
ESR = impedance of secondary circuit capacitor, winding
and traces
N = transformer effective secondary-to-flyback winding
SF
turns ratio (i.e., N /N
)
S
FLBK
The flyback voltage is scaled by an external resistive
divider R1/R2 and presented at the FB pin. The feedback
amplifier compares the voltage to the internal bandgap
reference.Thefeedbackampisactuallyatransconductance
feedbackisblankedeachcyclefort
.Iftheoutputload
ON(MIN)
is less than that developed under these conditions, forced
continuous operation normally occurs. See subsequent
discussions in the Applications Information section for
further details.
amplifier whose output is connected to V
only during
CMP
a period in the flyback time. An external capacitor on
the V pin integrates the net feedback amp current to
CMP
provide the control voltage to set the current mode trip
Enable Delay Time (ENDLY)
point. The regulation voltage at the FB pin is nearly equal
to the bandgap reference V because of the high gain in
FB
The flyback pulse appears when the primary-side switch
shutsoff.However,ittakesafinitetimeuntilthetransformer
primary-side voltage waveform represents the output
voltage. This is partly due to rise time on the primary-
side MOSFET drain node, but, more importantly, is due
the overall loop. The relationship between V
and V
FLBK
FB
is expressed as:
R1+ R2
V
=
• V
FB
FLBK
R2
4278fc
22
LTC4278
APPLICATIONS INFORMATION
T1
V
FLBK
FLYBACK
LTC4278 FEEDBACK AMP
R1
R2
•
•
FB
16
–
V
CMP
1V
17
V
IN
V
FB
C
VCMP
+
+
C
ISOLATED
OUTPUT
1.237V
–
+
PRIMARY
SECONDARY
MS
OUT
•
MP
COLLAPSE
DETECT
R
S
ENABLE
Q
4278 F10a
Figure 10a. LTC4278 Switching Regulator Feedback Amplifier
V
FLBK
0.8 • V
PRIMARY-SIDE
MOSFET DRAIN
VOLTAGE
FLBK
V
IN
PG VOLTAGE
SG VOLTAGE
4278 F10b
t
MIN ENABLE
PG DELAY
ON(MIN)
ENABLE
DELAY
FEEDBACK
AMPLIFIER
ENABLED
Figure 10b. LTC4278 Switching Regulator Timing Diagram
4278fc
23
LTC4278
APPLICATIONS INFORMATION
to transformer leakage inductance. The latter causes a
voltage spike on the primary side, not directly related to
output voltage. Some time is also required for internal
settling of the feedback amplifier circuitry. In order to
maintain immunity to these phenomena, a fixed delay is
introduced between the switch turn-off command and the
enabling of the feedback amplifier. This is termed “enable
delay.” In certain cases where the leakage spike is not
sufficiently settled by the end of the enable delay period,
regulation error may result. See the subsequent sections
for further details.
the synchronous MOSFET R
and real life nonzero
DS(ON)
impedances of the transformer secondary and output
capacitor. This was represented previously by the
expression, I •(ESR+R
). However, itisgenerally
SEC
DS(ON)
more useful to convert this expression to effective output
impedance. Because the secondary current only flows
during the off portion of the duty cycle (DC), the effective
outputimpedanceequalsthelumpedsecondaryimpedance
divided by off time DC.
Since the off-time duty cycle is equal to 1 – DC, then:
ESR+ RDS(ON)
RS(OUT)
=
Collapse Detect
1–DC
Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the flyback
where:
R
S(OUT)
= effective supply output impedance
voltage (FB) to a fixed reference, nominally 80% of V .
FB
DC = duty cycle
and ESR are as defined previously
When the flyback waveform drops below this level, the
feedback amplifier is disabled.
R
DS(ON)
This impedance error may be judged acceptable in less
critical applications, or if the output load current remains
relativelyconstant.Inthesecases,theexternalFBresistive
divider is adjusted to compensate for nominal expected
error. In more demanding applications, output impedance
error is minimized by the use of the load compensation
function. Figure 11 shows the block diagram of the load
compensation function. Switch current is converted to a
voltagebytheexternalsenseresistor,averagedandlowpass
Minimum Enable Time
The feedback amplifier, once enabled, stays on for a fixed
minimum time period, termed “minimum enable time.”
This prevents lockup, especially when the output voltage
is abnormally low, e.g., during start-up. The minimum
enable time period ensures that the V
node is able to
CMP
“pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. This time is set internally.
filtered by the internal 50k resistor R
and the external
CMPF
capacitor on C . This voltage is impressed across the
CMP
Effects of Variable Enable Period
external R
resistor by op amp A1 and transistor Q3
CMP
The feedback amplifier is enabled during only a portion of
thecycletime.Thiscanvaryfromthefixedminimumenable
time described to a maximum of roughly the off switch
time minus the enable delay time. Certain parameters of
feedbackampbehavioraredirectlyaffectedbythevariable
enable period. These include effective transconductance
producingacurrentatthecollectorofQ3thatissubtracted
from the FB node. This effectively increases the voltage
requiredatthetopoftheR1/R2feedbackdividertoachieve
equilibrium.
The average primary-side switch current increases to
maintain output voltage regulation as output loading
and V
node slew rate.
CMP
increases. TheincreaseinaveragecurrentincreasesR
CMP
resistor current which affects a corresponding increase
Load Compensation Theory
in sensed output voltage, compensating for the IR drops.
The LTC4278 uses the flyback pulse to obtain information
about the isolated output voltage. An error source is
caused by transformer secondary current flow through
4278fc
24
LTC4278
APPLICATIONS INFORMATION
Assuming relatively fixed power supply efficiency, Eff,
power balance gives:
Nominal output impedance cancellation is obtained by
equating this expression with R
:
S(OUT)
P
V
= Eff • P
IN
ESR+ RDS(ON)
1–DC
OUT
RSENSE
RCMP
K1•
•R1•NSF =
• I
= Eff • V • I
IN IN
OUT OUT
Average primary-side current is expressed in terms of
output current as follows:
Solving for R
gives:
CMP
RSENSE • 1–DC
ESR+ RDS(ON)
(
)
•R1•NSF
IIN = K1•IOUT
where:
RCMP = K1•
VOUT
Thepracticalaspectsofapplyingthisequationtodetermine
an appropriate value for the R resistor are discussed
K1=
V •Eff
IN
CMP
subsequently in the Applications Information section.
So, the effective change in V
target is:
OUT
Transformer Design
RSENSE
RCMP
ΔVOUT = K1•
•R1•NSF • ΔIOUT
Transformer design/specification is the most critical part
of a successful application of the LTC4278. The following
sections provide basic information about designing the
transformer and potential tradeoffs. If you need help, the
LTC Applications group is available to assist in the choice
and/or design of the transformer.
thus:
ΔVOUT
ΔIOUT
RSENSE
RCMP
= K1•
•R1•NSF
where:
Turns Ratios
K1 = dimensionless variable related to V , V
and
IN
OUT
The design of the transformer starts with determining
dutycycle(DC). DCimpactsthecurrentandvoltagestress
on the power switches, input and output capacitor RMS
currents and transformer utilization (size vs power). The
ideal turns ratio is:
efficiency, as previously explained
R
SENSE
= external sense resistor
V
FLBK
VOUT
1–DC
DC
R1
FB
•
•
NIDEAL
=
•
V
16
Q1 Q2
V
FB
IN
V
IN
R2
LOAD
COMP I
Avoid extreme duty cycles, as they generally increase cur-
rent stresses. A reasonable target for duty cycle is 50%
at nominal input voltage.
•
MP
+
R
CMPF
50k
+
Q3
A1
SENSE
20
For instance, if we wanted a 48V to 5V converter at 50%
DC then:
–
5 1– 0.5
• =
1
9.6
22
R
21
C
R
SENSE
CMP
CMP
NIDEAL
=
48 0.5
4278 F11
In general, better performance is obtained with a lower
turns ratio. A DC of 45.5% yields a 1:8 ratio.
Figure 11. Load Compensation Diagram
4278fc
25
LTC4278
APPLICATIONS INFORMATION
Note the use of the external feedback resistive divider
ratio to set output voltage provides the user additional
freedom in selecting a suitable transformer turns ratio.
Turns ratios that are the simple ratios of small integers;
e.g., 1:1, 2:1, 3:2 help facilitate transformer construction
and improve performance.
the voltage extends the flyback pulse width. If the flyback
pulse extends beyond the enable delay time, output
voltage regulation is affected. The feedback system has a
deliberately limited input range, roughly 50mV referred
to the FB node. This rejects higher voltage leakage spikes
because once a leakage spike is several volts in amplitude,
a further increase in amplitude has little effect on the
feedback system. Therefore, it is advisable to arrange the
clamp circuit to clamp at as high a voltage as possible,
observing MOSFET breakdown, such that leakage spike
duration is as short as possible. Application Note 19
provides a good reference on clamp design.
When building a supply with multiple outputs derived
through a multiple winding transformer, lower duty cycle
can improve cross regulation by keeping the synchronous
rectifier on longer, and thus, keep secondary windings
coupledlonger.Foramultipleoutputtransformer,theturns
ratio between output windings is critical and affects the
accuracy of the voltages. The ratio between two output
As a rough guide, leakage inductance of several percent
(of mutual inductance) or less may require a clamp, but
exhibit little to no regulation error due to leakage spike
behavior.Inductancesfromseveralpercentupto,perhaps,
ten percent, cause increasing regulation error.
voltagesissetwiththeformulaV
=V
•N21where
OUT2
OUT1
N21 is the turns ratio between the two windings. Also
keep the secondary MOSFET R
cross regulation.
small to improve
DS(ON)
The feedback winding usually provides both the feedback
voltage and power for the LTC4278. Set the turns ratio
between the output and feedback winding to provide a
rectifiedvoltagethatunderworst-caseconditionsisgreater
than the the preregulator maximum supply voltage. For
example if the preregulator maximum output were 7V:
Avoid double digit percentage leakage inductances. There
is a potential for abrupt loss of control at high load cur-
rent. This curious condition potentially occurs when the
leakage spike becomes such a large portion of the flyback
waveformthattheprocessingcircuitryisfooledintothink-
ing that the leakage spike itself is the real flyback signal!
It then reverts to a potentially stable state whereby the
top of the leakage spike is the control point, and the
trailing edge of the leakage spike triggers the collapse
detect circuitry. This typically reduces the output voltage
abruptly to a fraction, roughly one-third to two-thirds of
its correct value.
VOUT
NSF >
7+ VF
where:
V = Diode Forward Voltage
F
5
1
For our example: NSF >
=
7+ 0.7 1.56
Onceloadcurrentisreducedsufficiently,thesystemsnaps
back to normal operation. When using transformers with
considerableleakageinductance,exercisethisworst-case
check for potential bistability:
1
3
We will choose
Leakage Inductance
1. Operate the prototype supply at maximum expected
load current.
Transformer leakage inductance (on either the primary or
secondary) causes a spike after the primary-side switch
turn-off. This is increasingly prominent at higher load
currents, where more stored energy is dissipated. Higher
flyback voltage may break down the MOSFET switch if it
2. Temporarily short-circuit the output.
3. Observe that normal operation is restored.
If the output voltage is found to hang up at an abnormally
lowvalue,thesystemhasaproblem.Thisisusuallyevident
bysimultaneouslyviewingtheprimary-sideMOSFETdrain
voltage to observe firsthand the leakage spike behavior.
4278fc
has too low a BV
rating.
DSS
Onesolutiontoreducingthisspikeistouseaclampcircuit
to suppress the voltage excursion. However, suppressing
26
LTC4278
APPLICATIONS INFORMATION
A final note—the susceptibility of the system to bistable
behavior is somewhat a function of the load current/
voltage characteristics. A load with resistive—i.e., I =
V/R behavior—is the most apt to be bistable. Capacitive
Ripplecurrentandpercentagerippleislargestatminimum
duty cycle; in other words, at the highest input voltage.
P
L is calculated from the following equation.
2
loads that exhibit I = V /R behavior are less susceptible.
V
IN(MAX) •DCMIN
V
IN(MAX) •DCMIN 2 •Eff
2
(
)
(
)
LP =
=
fOSC • XMAX •P
fOSC • XMAX •POUT
IN
Secondary Leakage Inductance
Leakage inductance on the secondary forms an inductive
divider on the transformer secondary, reducing the size
of the flyback pulse. This increases the output voltage
target by a similar percentage. Note that unlike leakage
spike behavior, this phenomenon is independent of load.
Since the secondary leakage inductance is a constant
percentage of mutual inductance (within manufacturing
variations), the solution is to adjust the feedback resistive
divider ratio to compensate.
where:
f
is the oscillator frequency
OSC
DC
is the DC at maximum input voltage
MIN
X
MAX
is ripple current ratio at maximum input voltage
Using common high power PoE values, a 48V (41V < V
IN
< 57V) to 5V/5.3A converter with 90% efficiency, P
=
OUT
26.5W and P = 29.5W. Using X = 0.4 N = 1/8 and f
IN
OSC
= 200kHz:
Winding Resistance Effects
1
1
DCMIN
=
=
= 41.2%
N• V
1 57
Primary or secondary winding resistance acts to reduce
IN(MAX)
1+ •
1+
overallefficiency(P /P ).Secondarywindingresistance
OUT IN
8
5
VOUT
increases effective output impedance, degrading load
regulation. Load compensation can mitigate this to some
extent but a good design keeps parasitic resistances low.
2
57V •0.412
(
)
LP
=
= 260µH
200kHz •0.4•26.5W
Bifilar Winding
Optimization might show that a more efficient solution
is obtained at higher peak current but lower inductance
and the associated winding series resistance. A simple
spreadsheet program is useful for looking at tradeoffs.
A bifilar, or similar winding, is a good way to minimize
troublesome leakage inductances. Bifilar windings also
improve coupling coefficients, and thus improve cross
regulation in multiple winding transformers. However,
tight coupling usually increases primary-to-secondary
capacitance and limits the primary-to-secondary
breakdown voltage, so is not always practical.
Transformer Core Selection
Once L is known, the type of transformer is selected.
P
High efficiency converters use ferrite cores to minimize
core loss. Actual core loss is independent of core size for
afixedinductance,butdecreasesasinductanceincreases.
Sinceincreasedinductanceisaccomplishedthroughmore
turns of wire, copper losses increase. Thus, transformer
design balances core and copper losses. Remember that
increasedwindingresistancewilldegradecrossregulation
and increase the amount of load compensation required.
Primary Inductance
The transformer primary inductance, L , is selected
P
based on the peak-to-peak ripple current ratio (X) in the
transformer relative to its maximum value. As a general
rule, keep X in the range of 20% to 40% (i.e., X = 0.2 to
0.4).Highervaluesofripplewillincreaseconductionlosses,
while lower values will require larger cores.
The main design goals for core selection are reducing
copper losses and preventing saturation. Ferrite core
material saturates hard, rapidly reducing inductance
4278fc
27
LTC4278
APPLICATIONS INFORMATION
when the peak design current is exceeded. This results
in an abrupt increase in inductor ripple current and,
consequently, output voltage ripple. Do not allow the core
to saturate! The maximum peak primary current occurs
Continuing the example, if ESR + R
3.32k, then:
= 8mW, R2 =
DS(ON)
5+5.3•0.008
1.237 •1/ 3
R1=3.32k
−1 =37.28k
at minimum V :
IN
P
XMIN
2
choose 37.4k.
IN
IPK
=
• 1+
V
IN(MIN) •DCMAX
It is recommended that the Thevenin impedance of the
resistive divider (R1||R2) is roughly 3k for bias current
cancellation and other reasons.
now:
1
1
DCMAX
=
=
=49.4%
N• V
1 41
1+ •
8 5
IN MIN
(
)
Current Sense Resistor Considerations
1+
VOUT
The external current sense resistor is used to control peak
primary switch current, which controls a number of key
converter characteristics including maximum power and
external component ratings. Use a noninductive current
sense resistor (no wire-wound resistors). Mounting the
resistordirectlyaboveanunbrokengroundplaneconnected
with wide and short traces keeps stray resistance and
inductance low.
2
2
V
IN(MIN) •DCMAX
41• 49.4%
(
)
(
)
XMIN
=
=
fOSC •LP •P
=0.267
200kHz •260µH•29.5W
IN
Using the example numbers leads to:
29.5W
41•0.494
0.267
2
IPK
=
• 1+
=1.65A
ThedualsensepinsallowforafullKelvinconnection.Make
sure that SENSE and SENSE are isolated and connect
close to the sense resistor.
+
–
Multiple Outputs
Peakcurrentoccursat100mVofsensevoltageV
. So
SENSE
/I . For example, a
One advantage that the flyback topology offers is that
additionaloutputvoltagescanbeobtainedsimplybyadding
windings. Designing a transformer for such a situation is
beyondthescopeofthisdocument.Formultiplewindings,
realize that the flyback winding signal is a combination of
activityonallthesecondarywindings.Thusloadregulation
is affected by each winding’s load. Take care to minimize
cross regulation effects.
the nominal sense resistor is V
SENSE PK
peakswitchcurrentof10Arequiresanominalsenseresistor
of 0.010W Note that the instantaneous peak power in the
sense resistor is 1W, and that it is rated accordingly. The
use of parallel resistors can help achieve low resistance,
low parasitic inductance and increased power capability.
Size R
SENSE
using worst-case conditions, minimum L ,
P
SENSE
V
and maximum V . Continuing the example, let us
IN
Setting Feedback Resistive Divider
assumethatourworst-caseconditionsyieldanI of40%
PK
above nominal, so I = 2.3A. If there is a 10% tolerance
TheexpressionforV developedintheOperationsection
PK
OUT
on R
and minimum V
= 88mV, then R
•
is rearranged to yield the following expression for the
SENSE
SENSE
SENSE
110% = 88mV/2.3A and nominal R
= 35mW. Round
feedback resistors:
SENSE
to the nearest available lower value, 33mW.
V
OUT +ISEC • ESR+R
(
)
DS(ON)
R1=R2
−1
VFB •NSF
4278fc
28
LTC4278
APPLICATIONS INFORMATION
Selecting the Load Compensation Resistor
4. Compute:
RCMP = K1•
The expression for R
section as:
was derived in the Operation
RSENSE
RS(OUT)
CMP
•R1•NSF
RSENSE • 1–DC
ESR+ RDS(ON)
(
)
RCMP = K1•
•R1•NSF
5. Verify this result by connecting a resistor of this value
from the R pin to ground.
CMP
Continuing the example:
6.DisconnectthegroundshorttoC
andconnecta0.1µF
CMP
filter capacitor to ground. Measure the output imped-
anceR =ΔV /ΔI withthenewcompensation
VOUT
5
K1=
=
=0.116
S(OUT)
in place. R
OUT OUT
should have decreased significantly.
V •Eff 48 •90%
IN
S(OUT)
Fine tuning is accomplished experimentally by slightly
altering R . A revised estimate for R is:
1
1
DC=
=
=45.5%
N•V
1 48
1+ •
8 5
CMP
CMP
IN(NOM)
1+
VOUT
R
S(OUT)CMP
R′CMP =RCMP • 1+
RS(OUT)
If ESR+RDS(ON) =8mΩ
33mΩ • 1−0.455
(
)
1
3
R
CMP =0.116 •
=3.25k
•37.4kΩ •
where R′ is the new value for the load compensation
CMP
resistor. R
8mΩ
isthe outputimpedance with R
CMP
S(OUT)CMP
in place and R
is the output impedance with no
S(OUT)
load compensation (from step 2).
This value for R
is a good starting point, but empirical
CMP
methods are required for producing the best results.
This is because several of the required input variables
are difficult to estimate precisely. For instance, the ESR
term above includes that of the transformer secondary,
but its effective ESR value depends on high frequency
behavior, not simply DC winding resistance. Similarly, K1
Setting Frequency
The switching frequency of the LTC4278 is set by an
external capacitor connected between the OSC pin and
ground. Recommended values are between 200pF and
33pF, yielding switching frequencies between 50kHz and
250kHz.Figure12showsthenominalrelationshipbetween
external capacitance and switching frequency. Place the
capacitor as close as possible to the IC and minimize OSC
appears as a simple ratio of V to V
times efficiency,
IN
OUT
but theoretically estimating efficiency is not a simple
calculation.
The suggested empirical method is as follows:
300
1. Build a prototype of the desired supply including the
actual secondary components.
200
2. Temporarily ground the C
pin to disable the load
CMP
compensation function. Measure output voltage while
sweeping output current over the expected range.
Approximate the voltage variation as a straight line.
100
50
ΔV /ΔI
= R
.
OUT OUT
S(OUT)
3. Calculate a value for the K1 constant based on V , V
IN OUT
30
100
(pF)
200
C
OSC
and the measured efficiency.
4278 F12
Figure 12. fOSC vs OSC Capacitor Values
4278fc
29
LTC4278
APPLICATIONS INFORMATION
trace length and area to minimize stray capacitance and
potential noise pick-up.
The t
resistor is set with the following equation
ON(MIN)
tON(MIN) ns − 104
(
)
RtON(MIN) kW =
(
)
Youcansynchronizetheoscillatorfrequencytoanexternal
frequency. This is done with a signal on the SYNC pin.
Set the LTC4278 frequency 10% slower than the desired
external frequency using the OSC pin capacitor, then use
a pulse on the SYNC pin of amplitude greater than 2V
and with the desired frequency. The rising edge of the
SYNC signal initiates an OSC capacitor discharge forcing
primaryMOSFEToff(PGvoltagegoeslow).Iftheoscillator
frequency is much different from the sync frequency,
problemsmayoccurwithslopecompensationandsystem
stability.Also,keepthesyncpulsewidthgreaterthan500ns.
1.063
greater than 70k. A good starting value
Keep R
is 160k.
tON(MIN)
Enable Delay Time (ENDLY)
Enabledelaytimeprovidesaprogrammabledelaybetween
turn-offoftheprimarygatedrivenodeandthesubsequent
enablingofthefeedbackamplifier.Asdiscussedearlier,this
delay allows the feedback amplifier to ignore the leakage
inductance voltage spike on the primary side. The worst-
case leakage spike pulse width is at maximum load condi-
tions. So, set the enable delay time at these conditions.
Selecting Timing Resistors
There are three internal “one-shot” times that are
programmed by external application resistors: minimum
on-time, enable delay time and primary MOSFET turn-on
delay. These are all part of the isolated flyback control
technique, and their functions are previously outlined in
theTheoryofOperationsection.Thefollowinginformation
should help in selecting and/or optimizing these timing
values.
While the typical applications for this part use forced
continuous operation, it is conceivable that a secondary-
side controller might cause discontinuous operation at
light loads. Under such conditions, the amount of energy
stored in the transformer is small. The flyback waveform
becomes “lazy” and some time elapses before it indicates
theactualsecondaryoutputvoltage.Theenabledelaytime
should be made long enough to ignore the “irrelevant”
portion of the flyback waveform at light loads.
Minimum Output Switch On-Time (t
)
ON(MIN)
Even though the LTC4278 has a robust gate drive, the gate
transition time slows with very large MOSFETs. Increase
delay time as required when using such MOSFETs.
Minimumon-timeistheprogrammableperiodduringwhich
current limit is blanked (ignored) after the turn-on of the
primary-sideswitch.Thisimprovesregulatorperformance
by eliminating false tripping on the leading edge spike in
the switch, especially at light loads. This spike is due to
both the gate/source charging current and the discharge
ofdraincapacitance.Theisolatedflybacksensingrequires
a pulse to sense the output. Minimum on-time ensures
that the output switch is always on a minimum time and
that there is always a signal to close the loop.
Theenabledelayresistorissetwiththefollowingequation:
tENDLY ns − 30
2.616
greaterthan40k.Agoodstartingpointis56k.
(
)
RENDLY kW =
(
)
KeepR
ENDLY
Primary Gate Delay Time (PGDLY)
TheLTC4278doesnotemploycycleskippingatlightloads.
Therefore, minimum on-time along with synchronous
rectification sets the switch over to forced continuous
mode operation.
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of the
primary-side MOSFET. Correct setting eliminates overlap
4278fc
30
LTC4278
APPLICATIONS INFORMATION
betweentheprimary-sideswitchandsecondary-sidesyn-
chronous switch(es) and the subsequent current spike in
thetransformer.Thisspikewillcauseadditionalcomponent
stress and a loss in regulator efficiency.
UVLO is below the 1.24V UVLO threshold. An external
resistive divider between the input supply and ground is
used to set the turn-on voltage.
The bias current on this pin depends on the pin volt-
age and UVLO state. The change provides the user with
adjustable UVLO hysteresis. When the pin rises above
the UVLO threshold a small current is sourced out of the
pin, increasing the voltage on the pin. As the pin voltage
drops below this threshold, the current is stopped, further
dropping the voltage on UVLO. In this manner, hysteresis
is produced.
The primary gate delay resistor is set with the following
equation:
tPGDLY ns + 47
(
)
RPGDLY kW =
(
)
9.01
A good starting point is 15k.
Soft-Start Function
Referring to Figure 13, the voltage hysteresis at V is
IN
equal to the change in bias current times R . The design
A
The LTC4278 contains an optional soft-start function that
is enabled by connecting an external capacitor between
the SFST pin and ground. Internal circuitry prevents the
procedure is to select the desired V referred voltage
IN
hysteresis, V
. Then:
UVHYS
control voltage at the V
pin from exceeding that on
VUVHYS
IUVLO
CMP
RA
=
the SFST pin. There is an initial pull-up circuit to quickly
bringtheSFSTvoltagetoapproximately0.8V.Fromthereit
chargestoapproximately2.8Vwitha20µAcurrentsource.
where:
The SFST node is discharged to 0.8V when a fault occurs.
A fault occurs when the current sense voltage is greater
than 200mV or the IC’s thermal (overtemperature) shut-
I
= I
– I
is approximately 3.4µA
UVLOH
UVLO
UVLOL
R is then selected with the desired turn-on voltage:
B
down is tripped. When SFST discharges, the V
node
RA
CMP
RB =
voltage is also pulled low to below the minimum current
voltage. Once discharged and the fault removed, the
SFST charges up again. In this manner, switch currents
are reduced and the stresses in the converter are reduced
during fault conditions.
V
IN(ON)
–1
V
UVLO
V
IN
I
I
UVLO
UVLO
R
A1
A2
The time it takes to fully charge soft-start is:
V
V
IN
IN
R
R
CSFST •1.4V
tss
=
= 70kW •CSFST µF
R
R
(
)
A
B
A
B
C
UVLO
UVLO
UVLO
UVLO
LTC4278
20µA
B
LTC4278
R
R
4278 F13
Switcher’s UVLO Pin Function
(13a) UV Turning On
(13b) UV Turning Off
(13c) UV Filtering
The UVLO pin provides a user programming undervoltage
lockout. This is typically used to provide undervoltage
Figure 13. UVLO Pin Function and Recommended Filtering
lockout based on V . The gate drivers are disabled when
IN
4278fc
31
LTC4278
APPLICATIONS INFORMATION
If we wanted a V -referred trip point of 36V, with 1.8V
to turn off Q . If the two voltage ranges overlap, the only
IN
PR
(5%) of hysteresis (on at 36V, off at 34.2V):
disadvantage is that a small degradation in efficiency may
occur. It is also necessary to verify that the worst-case
maximum winding voltage is not high enough to damage
1.8V
3.4µA
R =
= 529k, use 523k
A
the B-E junction of Q .
PR
523k
R =
= 18.5k, use 18.7k
B
V
IN
36V
– 1
•
1.23V
•
Even with good board layout, board noise may cause
problems with UVLO. You can filter the divider but keep
large capacitance off the UVLO node because it will slow
the hysteresis produced from the change in bias current.
Figure 13c shows an alternate method of filtering by split-
Q
PR
C
VCC
ting the R resistor with the capacitor. The split should put
A
V
CC
PG
more of the resistance on the UVLO side.
•
LTC4278
GND
FB
Converter Start-Up
4278 F14
The standard topology for the LTC4278 uses a third trans-
former winding on the primary side that provides both the
Figure 14. Typical Power Bootstrapping
feedback information and local V power for the LTC4278
CC
(Figure14). Thispowerbootstrappingimprovesconverter
efficiency but is not inherently self-starting. Start-Up is
affected with an external preregulator circuit that condi-
tionstheinputlinevoltagefortheLTC4278duringstart-up.
Control Loop Compensation
Loop frequency compensation is performed by connect-
ing a capacitor network from the output of the feedback
amplifier (V
pin) to ground as shown in Figure 15.
is charged via the pre-
CMP
Upon application of power, C
VCC
Becauseofthesamplingbehaviorofthefeedbackamplifier,
regulator, therebyprovidingan appropriatesupply voltage
compensation is different from traditional current mode
controllers. Normally only C
at the V pin for the LTC4278. This supply voltage is
CC
is required. R
can
typically in the range 7V and is used during start-up. After
converter startup, the third transformer winding becomes
energizedandisdesignedtogenerateahighervoltagethan
the preregulator. The higher voltage of the third winding
turns off QPR and provides an efficient method to power
the LTC4278.
VCMP
VCMP
be used to add a zero, but the phase margin improvement
traditionallyofferedbythisextraresistorisusuallyalready
accomplishedbythenonzerosecondarycircuitimpedance.
C
can be used to add an additional high frequency
VCMP2
pole and is usually sized at 0.1 times C
.
VCMP
Design of the V power circuitry involves selecting ap-
CC
V
CMP
17
propriate voltage ranges for both the preregulator and
the third transformer winding. The preregulator voltage
is set as low as possible while ensuring it’s worst-case
minimum voltage is high enough to drive the switching
FETs gates during the startup period. The third winding
output voltage is selected to ensure that it’s worst-case
minimumvoltageexceedsthepreregulatorvoltageinorder
C
R
VCMP
VCMP2
C
VCMP
4278 F15
Figure 15. VCMP Compensation Network
4278fc
32
LTC4278
APPLICATIONS INFORMATION
In further contrast to traditional current mode switch-
In normal use, the peak switch current increases while
FB is below the internal reference. This continues until
ers, V
pin ripple is generally not an issue with the
CMP
LTC4269-1. The dynamic nature of the clamped feedback
amplifier forms an effective track/hold type response,
V
reaches its 2.56V clamp. At clamp, the primary-side
CMP
MOSFET will turn off at the rated 100mV V
repeats on the next cycle.
level. This
SENSE
whereby the V
voltage changes during the flyback
CMP
pulse, but is then held during the subsequent switch-on
portion of the next cycle. This action naturally holds the
It is possible for the peak primary switch currents as
referred across R to exceed the max 100mV rating
SENSE
V
voltage stable during the current comparator sense
CMP
because of the minimum switch on time blanking. If the
action (current mode switching).
voltage on V exceeds 205mV after the minimum
SENSE
Application Note 19 provides a method for empirically
tweaking frequency compensation. Basically, it involves
introducing a load current step and monitoring the
response.
turn-on time, the SFST capacitor is discharged, causing
the discharge of the V capacitor. This then reduces
CMP
the peak current on the next cycle and will reduce overall
stress in the primary switch.
Slope Compensation
Short-Circuit Conditions
The LTC4278 incorporates current slope compensation.
Slope compensation is required to ensure current loop
stabilitywhentheDCisgreaterthan50%.Insomeswitching
regulators,slopecompensationreducesthemaximumpeak
current at higher duty cycles. The LTC4278 eliminates this
problembyhavingcircuitrythatcompensatesfortheslope
compensation so that maximum current sense voltage is
constant across all duty cycles.
Loss of current limit is possible under certain conditions
such as an output short-circuit. If the duty cycle exhibited
by the minimum on-time is greater than the ratio of
secondary winding voltage (referred-to-primary) divided
by input voltage, then peak current is not controlled at
the nominal value. It ratchets up cycle-by-cycle to some
higher level. Expressed mathematically, the requirement
to maintain short-circuit control is:
Minimum Load Considerations
I
• R
+ R
SEC DS(ON)
(
)
SC
DC
= t
• f
<
MIN
ON(MIN) OSC
At light loads, the LTC4278 derived regulator goes into
forced continuous conduction mode. The primary-side
switch always turns on for a short time as set by the
V •N
IN
SP
where:
t
is the primary-side switch minimum on-time
ON(MIN)
t
resistor. If this produces more power than the
ON(MIN)
I
SC
is the short-circuit output current
load requires, power will flow back into the primary dur-
ing the off period when the synchronization switch is on.
This does not produce any inherently adverse problems,
although light load efficiency is reduced.
N
SP
is the secondary-to-primary turns ratio (N /N
(other variables as previously defined)
)
SEC PRI
Trouble is typically encountered only in applications with
a relatively high product of input voltage times secondary
to primary turns ratio and/or a relatively long minimum
switchontime.Additionally,severalrealworldeffectssuch
astransformerleakageinductance,ACwindinglossesand
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate. Prudent
Maximum Load Considerations
The current mode control uses the V
node voltage and
CMP
amplified sense resistor voltage as inputs to the current
comparator.Whentheamplifiedsensevoltageexceedsthe
V
CMP
node voltage, the primary-side switch is turned off.
4278fc
33
LTC4278
APPLICATIONS INFORMATION
design evaluates the switcher for short-circuit protection
and adds any additional circuitry to prevent destruction.
whereX ispeak-to-peakcurrentratioasdefinedearlier.
MIN
For each secondary-side power MOSFET, the peak cur-
rent is:
Output Voltage Error Sources
IOUT
1−DCMAX
XMIN
2
The LTC4278’s feedback sensing introduces additional
minor sources of errors. The following is a summary list:
IPK(SEC)
=
• 1+
• Theinternalbandgapvoltagereferencesetsthereference
voltage for the feedback amplifier. The specifications
detail its variation.
Select a primary-side power MOSFET with a BVDSS
greater than:
VOUT(MAX)
• The external feedback resistive divider ratio directly
affects regulated voltage. Use 1% components.
• Leakage inductance on the transformer secondary
reduces the effective secondary-to-feedback winding
turns ratio (NS/NF) from its ideal value. This increases
the output voltage target by a similar percentage. Since
secondary leakage inductance is constant from part to
part (within a tolerance) adjust the feedback resistor
ratio to compensate.
LLKG
CP
BVDSS ≥ IPK
+ V
+
IN(MAX)
NSP
where NSP reflects the turns ratio of that secondary-to
primary winding. LLKG is the primary-side leakage induc-
tanceandCPistheprimary-sidecapacitance(mostlyfrom
the drain capacitance (COSS) of the primary-side power
MOSFET). A clamp may be added to reduce the leakage
inductance as discussed.
• The transformer secondary current flows through the
impedances of the winding resistance, synchronous
Foreachsecondary-sidepowerMOSFET,theBV should
DSS
be greater than:
MOSFET R
and output capacitor ESR. The DC
DS(ON)
equivalent current for these errors is higher than the
load current because conduction occurs only during
the converter’s off-time. So, divide the load current by
(1 – DC).
BV
≥ V
+ V
• N
DSS
OUT
IN(MAX) SP
Choose the primary-side MOSFET R
gatedrivevoltage(7.5V).Thesecondary-sideMOSFETgate
drive voltage depends on the gate drive method.
at the nominal
DS(ON)
Iftheoutputloadcurrentisrelativelyconstant,thefeedback
resistive divider is used to compensate for these losses.
Otherwise, use the LTC4278 load compensation circuitry
(see Load Compensation). If multiple output windings are
used, theflybackwindingwillhaveasignalthatrepresents
an amalgamation of all these windings impedances. Take
carethatyouexamineworst-caseloadingconditionswhen
tweaking the voltages.
Primary-side power MOSFET RMS current is given by:
P
IN
IRMS(PRI)
=
V
DCMAX
IN(MIN)
For each secondary-side power MOSFET RMS current is
given by:
IOUT
Power MOSFET Selection
IRMS(SEC)
=
1–DCMAX
ThepowerMOSFETsareselectedprimarilyonthecriteriaof
on-resistanceR
,inputcapacitance,drain-to-source
DSS
DS(ON)
Calculate MOSFET power dissipation next. Because the
primary-side power MOSFET operates at high V , a
transitionpowerlosstermisincludedforaccuracy.C
breakdown voltage (BV ), maximum gate voltage (V )
GS
DS
and maximum drain current (ID
).
(MAX)
MILLER
is the most critical parameter in determining the transition
loss, but is not directly specified on the data sheets.
For the primary-side power MOSFET, the peak current is:
P
XMIN
2
IN
IPK(PRI)
=
• 1+
VIN(MIN) •DCMAX
4278fc
34
LTC4278
APPLICATIONS INFORMATION
C
is calculated from the gate charge curve included
The secondary-side power MOSFETs typically operate
MILLER
at substantially lower V , so you can neglect transition
losses. The dissipation is calculated using:
on most MOSFET data sheets (Figure 16).
DS
2
P
= I
• R (1 + d)
DS(ON)
MILLER EFFECT
DIS(SEC)
RMS(SEC)
V
GS
With power dissipation known, the MOSFETs’ junction
temperatures are obtained from the equation:
a
b
4278 F16
Q
Q
B
A
GATE CHARGE (Q )
G
T = T + P • θ
JA
J
A
DIS
Figure 16. Gate Charge Curve
whereT istheambienttemperatureandθ istheMOSFET
A
JA
junction to ambient thermal resistance.
The flat portion of the curve is the result of the Miller (gate
to-drain)capacitanceasthedrainvoltagedrops.TheMiller
capacitance is computed as:
Once you have T iterate your calculations recomputing
J
d and power dissipations until convergence.
QB –QA
Gate Drive Node Consideration
CMILLER
=
VDS
The PG and SG gate drivers are strong drives to minimize
gate drive rise and fall times. This improves efficiency,
but the high frequency components of these signals can
cause problems. Keep the traces short and wide to reduce
parasitic inductance.
The curve is done for a given V . The Miller capacitance
DS
for different V voltages are estimated by multiplying the
DS
MILLER
computed C
by the ratio of the application V to
DS
the curve specified V .
DS
The parasitic inductance creates an LC tank with the
MOSFET gate capacitance. In less than ideal layouts, a
series resistance of 5Ω or more may help to dampen the
ringing at the expense of slightly slower rise and fall times
and poorer efficiency.
WithC
determined,calculatetheprimary-sidepower
MILLER
MOSFET power dissipation:
PD(PRI) =IRMS(PRI)2 •RDS(ON) 1+ δ +
(
)
P
CMILLER
V
•
IN(MAX) •RDR
DCMIN
•
• fOSC
IN(MAX)
The LTC4278 gate drives will clamp the max gate voltage
to roughly 7.5V, so you can safely use MOSFETs with
VGATE(MAX) – VTH
maximum V of 10V and larger.
GS
where:
R
V
is the gate driver resistance (≈10Ω)
is the MOSFET gate threshold voltage
is the operating frequency
DR
Synchronous Gate Drive
There are several different ways to drive the synchronous
gateMOSFET.Fullconverterisolationrequiresthesynchro-
nousgatedrivetobeisolated.Thisisusuallyaccomplished
by way of a pulse transformer. Usually the pulse driver is
used to drive a buffer on the secondary, as shown in the
application on the front page of this data sheet.
TH
f
OSC
V
= 7.5V for this part
GATE(MAX)
(1 + d) is generally given for a MOSFET in the form of a
normalizedR vstemperaturecurve.Ifyoudon’thave
DS(ON)
a curve, use d = 0.005/°C • ΔT for low voltage MOSFETs.
However,otherschemesarepossible.Therearegatedrivers
andsecondary-sidesynchronouscontrollersavailablethat
provide the buffer function as well as additional features.
4278fc
35
LTC4278
APPLICATIONS INFORMATION
Capacitor Selection
I
PRI
PRIMARY
CURRENT
In a flyback converter, the input and output current flows
in pulses, placing severe demands on the input and output
filter capacitors. The input and output filter capacitors are
selected based on RMS current ratings and ripple voltage.
I
PRI
N
SECONDARY
CURRENT
Select an input capacitor with a ripple current rating
greater than:
RINGING
DUE TO ESL
∆V
COUT
P
1–DCMAX
DCMAX
OUTPUT VOLTAGE
RIPPLE WAVEFORM
IN
IRMS(PRI)
=
∆V
ESR
V
4278 F17
IN(MIN)
Figure 17. Typical Flyback Converter Waveforms
Continuing the example:
29.5W 1– 49.4%
ripple, divided equally between the ESR step and the
charging/discharging ΔV. This percentage ripple changes,
dependingontherequirementsoftheapplication. Youcan
modify the following equations.
IRMS(PRI)
=
= 0.728A
41V
49.4%
Keep input capacitor series resistance (ESR) and
inductance (ESL) small, as they affect electromagnetic
interferencesuppression.Insomeinstances,highESRcan
alsoproducestabilityproblemsbecauseflybackconverters
exhibit a negative input resistance characteristic. Refer to
Application Note 19 for more information.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor is determined by:
VOUT • 1–DC
(
)
MAX
ESRCOUT ≤1%•
IOUT
The output capacitor is sized to handle the ripple current
andtoensureacceptableoutputvoltageripple. Theoutput
capacitor should have an RMS current rating greater than:
The other 1% is due to the bulk C component, so use:
IOUT
1%• VOUT • fOSC
COUT
≥
DCMAX
1–DCMAX
IRMS(SEC) = IOUT
In many applications, the output capacitor is created from
multiple capacitors to achieve desired voltage ripple,
reliability and cost goals. For example, a low ESR ceramic
capacitor can minimize the ESR step, while an electrolytic
capacitor satisfies the required bulk C.
Continuing the example:
49.4%
1– 49.4%
IRMS(SEC) = 5.3A
= 5.24A
Continuing our example, the output capacitor needs:
This is calculated for each output in a multiple winding
application.
5V • 1– 49.4%
(
)
= 4mΩ
ESRCOUT ≤1%•
5.3A
1%•5•200kHz
ESRandESLalongwithbulkcapacitancedirectlyaffectthe
output voltage ripple. The waveforms for a typical flyback
converter are illustrated in Figure 17.
5.3A
= 600µF
COUT
≥
The maximum acceptable ripple voltage (expressed as a
percentage of the output voltage) is used to establish a
starting point for the capacitor values. For the purpose of
simplicity, we will choose 2% for the maximum output
These electrical characteristics require paralleling several
low ESR capacitors possibly of mixed type.
4278fc
36
LTC4278
APPLICATIONS INFORMATION
One way to reduce cost and improve output ripple is to use
a simple LC filter. Figure 18 shows an example of the filter.
unidirectional58Vtransientvoltagesuppressorbeinstalled
betweenthediodebridgeandtheLTC4278(D3inFigure2).
L1, 0.1µH
ISOLATION
V
OUT
C
FROM
SECONDARY
WINDING
+
+
C1
47µF
×3
C
The802.3standardrequiresEthernetportstobeelectrically
isolatedfromallotherconductorsthatareuseraccessible.
This includes the metal chassis, other connectors and
any auxiliary power connection. For PDs, there are two
common methods to meet the isolation requirement. If
there will be any user accessible connection to the PD,
then an isolated DC/DC converter is necessary to meet
the isolation requirements. If user connections can be
avoided, then it is possible to meet the safety requirement
by completely enclosing the PD in an insulated housing.
In all PD applications, there should be no user accessible
electrical connections to the LTC4278 or support circuitry
other than the RJ-45 port.
OUT
OUT2
R
LOAD
470µF
1µF
4278 F18
Figure 18.
The design of the filter is beyond the scope of this data
sheet. However, as a starting point, use these general
guidelines. Start with a C
solution. Make C1 1/4 of C
pole independent of C . C1 may be best implemented
1/4 the size of the nonfilter
to make the second filter
OUT
OUT
OUT
with multiple ceramic capacitors. Make L1 smaller than
the output inductance of the transformer. In general, a
0.1µH filter inductor is sufficient. Add a small ceramic
capacitor (C
) for high frequency noise on V . For
OUT2
OUT
those interested in more details refer to “Second-Stage
LC Filter Design,” Ridley, Switching Power Magazine, July
2000 p8-10.
LAYOUT CONSIDERATIONS FOR THE LTC4278
The LTC4278’s PD front end is relatively immune to layout
problems. Excessive parasitic capacitance on the R
CLASS
Circuit simulation is a way to optimize output capacitance
and filters, just make sure to include the component
parasitic. LTC SwitcherCAD® is a terrific free circuit
simulation tool that is available at www.linear.com. Final
optimization of output ripple must be done on a dedicated
PC board. Parasitic inductance due to poor layout can
significantly impact ripple. Refer to the PC Board Layout
section for more details.
pin should be avoided. Include a PCB heat sink to which
the exposed pad on the bottom of the package can be
soldered. This heat sink should be electrically connected
to GND. For optimum thermal performance, make the
heat sink as large as possible. Voltages in a PD can be as
large as 57V for PoE applications, so high voltage layout
techniques should be employed. The SHDN pin should
be separated from other high voltage pins, like V
,
PORTP
V
, to avoid the possibility of leakage currents shutting
NEG
ELECTRO STATIC DISCHARGE AND SURGE
PROTECTION
down the LTC4278. If not used, tie SHDN to V
. The
of the
PORTN
load capacitor connected between V
and V
PORTP
NEG
LTC4278 can store significant energy when fully charged.
The design of a PD must ensure that this energy is not
inadvertently dissipated in the LTC4278. The polarity-
protection diodes prevent an accidental short on the cable
The LTC4278 is specified to operate with an absolute
maximum voltage of –100V and is designed to tolerate
brief overvoltage events. However, the pins that interface
to the outside world (primarily V
and V
) can
PORTN
PORTP
from causing damage. However if, V
is shorted
PORTN
routinely see peak voltages in excess of 10kV. To protect
the LTC4278, it is highly recommended that the SMAJ58A
to V
inside the PD while capacitor C1 is charged,
PORTP
4278fc
37
LTC4278
APPLICATIONS INFORMATION
current will flow through the parasitic body diode of the
internal MOSFET and may cause permanent damage to
the LTC4278.
Check that the maximum BV
ratings of the MOSFETs
DSS
are not exceeded due to inductive ringing. This is done by
viewingtheMOSFETnodevoltageswithanoscilloscope.If
it is breaking down, either choose a higher voltage device,
add a snubber or specify an avalanche-rated MOSFET.
In order to minimize switching noise and improve output
loadregulation,connecttheGNDpinoftheLTC4278directly
to the ground terminal of the V decoupling capacitor,
Placethesmall-signalcomponentsawayfromhighfrequency
switching nodes. This allows the use of a pseudo-Kelvin
connection for the signal ground, where high di/dt gate
drivercurrentsflowoutoftheICgroundpininonedirection
(to the bottom plate of the V decoupling capacitor) and
small-signal currents flow in the other direction.
CC
the bottom terminal of the current sense resistor and the
groundterminaloftheinputcapacitor,usingagroundplane
with multiple vias. Place the V capacitor immediately
CC
adjacent to the V and GND pins on the IC package. This
CC
CC
capacitor carries high di/dt MOSFET gate drive currents.
Use a low ESR ceramic capacitor.
Keep the trace from the feedback divider tap to the FB pin
short to preclude inadvertent pick-up.
TakecareinPCBlayouttokeepthetracesthatconducthigh
switching currents short, wide and with minimal overall
loop area. These are typically the traces associated with
the switches. This reduces the parasitic inductance and
alsominimizesmagneticfieldradiation. Figure19outlines
the critical paths.
Forapplicationswithmultipleswitchingpowerconverters
connected to the same input supply, make sure that the
input filter capacitor for the LTC4278 is not shared with
other converters. AC input current from another converter
could cause substantial input voltage ripple which could
interfere with the LTC4278 operation. A few inches of PC
Keep electric field radiation low by minimizing the length
andareaoftraces(keepstraycapacitanceslow). Thedrain
of the primary-side MOSFET is the worst offender in this
category. Always use a ground plane under the switcher
circuitry to prevent coupling between PCB planes.
trace or wire (L @ 100nH) between the C of the LTC4278
IN
and the actual source V , is sufficient to prevent current
IN
sharing problems.
T1
V
CC
V
IN
•
•
C
VCC
GATE
TURN-ON
V
•
CC
+
PG
C
MP
VIN
OUT
GATE
TURN-OFF
+
R
SENSE
+
C
OUT
GATE
C
R
Q4
Q3
V
TURN-ON
CC
T2
V
MS
CC
•
•
SG
GATE
TURN-OFF
4278 F19
Figure 19. Layout Critical High Current Paths
4278fc
38
LTC4278
TYPICAL APPLICATION
4278fc
39
LTC4278
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DKD Package
32-Lead Plastic DFN (7mm × 4mm)
(Reference LTC DWG # 05-08-1734 Rev A)
0.70 0.05
4.50 0.05
6.43 0.05
2.65 0.05
3.10 0.05
PACKAGE
OUTLINE
0.20 0.05
0.40 BSC
6.00 REF
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
7.00 0.10
17
32
R = 0.05
TYP
0.40 0.10
6.43 0.10
2.65 0.10
4.00 0.10
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
16
1
0.20 0.05
0.40 BSC
6.00 REF
BOTTOM VIEW—EXPOSED PAD
0.75 0.05
(DKD32) QFN 0707 REV A
0.200 REF
NOTE:
0.00 – 0.05
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4278fc
40
LTC4278
REVISION HISTORY (Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
3/12
Added B1100 to schematic
1, 19
2
Revised Max Junction Temperature
Added Typical Application
39
1
C
4/12
Updated component values on Typical Application
Updated Maximum Junction Temperature to 125°C
Updated Typical Application
2
39
4278fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
41
LTC4278
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT®1952
Single Switch Synchronous Forward Counter
Current Mode Flyback DC/DC Controller in ThinSOTTM
Synchronous Controller, Programmable Volt-Sec Clamp, Low Start Current
LTC3803-3
300kHz Constant-Frequency, Adjustable Slope Compensation, Optimized
for High Input Voltage Applications
LTC3805
LTC3825
Adjustable Frequency Current Mode Flyback Controller Slope Comp, Overcurrent Protect, Internal/External Clock
Isolated No-Opto Synchronous Flyback Controller with Adjustable Switching Frequency, Programmable Undervoltage Lockout,
Wide Input Supply Range
Accurate Regulation without Trim, Synchronous for High Efficiency
LTC4257-1
LTC4258
IEEE 802.3af PD Interface Controller
100V 400mA Internal Switch, Programmable Classification, Dual
Current Limit
Quad IEEE 802.3af Power over Ethernet Controller
Quad IEEE 802.3af Power over Ethernet Controller
Single IEEE 802.3af Power over Ethernet Controller
High Power Single PSE Controller
DC Disconnect Only, IEEE-Compliant PD Detection and Classification,
2
Autonomous Operation or I C Control
LTC4259A-1
LTC4263
AC or DC Disconnect, IEEE-Compliant PD Detection and Classification,
Autonomous Operation
AC or DC Disconnect, IEEE-Compliant PD Detection and Classification,
2
Autonomous Operation or I C Control
LTC4263-1
LTC4264
Internal Switch, Autonomous Operation, 30W
High Power PD Interface Controller with 750mA
Current Limit
750mA Internal Switch, Programmable Classification Current to 75mA,
Precision Dual Current Limit with Disable.
LTC4265
LTC4266
IEEE 802.3at High Power PD Interface Controller with
2-Event Classification
2-Event Classification Recognition, 100mA Inrush Current, Single-Class
Programming Resistor, Full Compliance to 802.3at
IEEE 802.3at Quad PSE Controller
Supports IEEE 802.3at Type 1 and Type 2 PDs, 0.34Ω Channel Resistance,
Advanced Power Management, High Reliability 4-Point PD Detection,
Legacy Capacitance Detect
LTC4267-1
LTC4267-3
LTC4269-1
LTC4269-2
IEEE 802.3af PD Interface with an Integrated
Switching Regulator
100V 400mA Internal Switch, Programmable Classification, 200kHz
Constant-Frequency PWM, Optimized for IEEE-Compliant PD System
IEEE 802.3af PD Interface with an Integrated
Switching Regulator
100V 400mA Internal Switch, Programmable Classification, 300kHz
Constant-Frequency PWM, Optimized for IEEE-Compliant PD System
IEEE 802.3af/IEEE 802.3at PD with Synchronous
No-Opto Flyback Controller
2-Event Classification Recognition, 92% Power Supply Efficiency, Flexible
Aux Support, Superior EMI
IEEE 802.3af/IEEE 802.3at PD with Synchronous
Forward Controller
2-Event Classification Recognition, 94% Power Supply Efficiency, Flexible
Aux Support, Superior EMI
4278fc
LT 0412 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
42
l
l
LINEAR TECHNOLOGY CORPORATION 2009
(408)432-1900 FAX: (408) 434-0507 www.linear.com
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