LTC4279IS#PBF_技术文档

LTC4279

+

Single Port PoE/PoE /

++

LTPoE PSE Controller

FEATURES

DESCRIPTION

The LTC^®4279 is an autonomous single port power sourc-

ing equipment (PSE) controller designed for use in IEEE

n

Compliant with IEEE 802.3at Type 1 and 2

Supports LTPoE ^®Up to 90W

++

n

++

Supports Dual-Signature PDs

802.3at Type 1, Type 2 and LTPoE compliant Power

Fully Autonomous Operation without Microcontroller

Very Low Power Dissipation

over Ethernet (PoE) systems. The LTC4279 provides fully

++

autonomousIEEE802.3andLTPoE compliantoperation

– 0.1Ω Sense Resistance

without a microcontroller. The LTC4279 simplifies PSE

implementation, requiringonlyasinglesupplyandasmall

number of passive support components.

– Low R

External MOSFET

DS(ON)

n

Very High Reliability 4-Point PD Detection

– 2-Point Forced Voltage and Forced Current

Robust Short-Circuit Protection

The LTC4279 delivers lowest-in-industry heat dissipation

n

by utilizing a low-R

external MOSFET and a 0.1Ω

DS(ON)

Cable Surge Protected 80ꢀ OUT Pin

Classiﬁcation Dependent I

Thresholds

sense resistor, eliminating the need for expensive heat

sinks and increasing efficiency.

and I Current

CUT

LIM

n

PDdiscoveryusesaproprietarydual-mode4-pointdetec-

tion mechanism ensuring excellent immunity from false

PD detection. Midspan PSEs are supported with physical

layer classification and a 2.5 second backoff timer.

Supports 2-Pair and 4-Pair Output Power

UltraPWR Mode Supports Custom PDs Up to 123W

Pin-Selectable Detection Backoff Timer for Midspans

Pin Programmable Legacy PD Detection

Pin Programmable Maximum Power Mode

Status LED Pin

LegacyandcustomPDsaresupportedwithpin-selectable

LEGACY and UltraPWR modes. LEGACY mode detects

and powers pre-IEEE specification PDs. UltraPWR mode

aggressively turns on and powers custom PDs requiring

high inrush and/or operational currents.

Available in 20-Pin QFN and 16-Pin SO Packages

APPLICATIONS

++

L, LT, LTC, LTM, Linear Technology, the Linear logo and LTPoE are registered trademarks of

Analog Devices, Inc. All other trademarks are the property of their respective owners.

n

PoE PSE Endpoints (Switch/Router)

n

PoE Midspan Power Injectors

n

Power Forwarders

n

Femto Cells

n

Security Systems

TYPICAL APPLICATION

MAXIMUM PD INPUT POWER

Type 1 (13W)

R

( 1ꢀ)

PM

+

2.37k

0.22µF

100V

X7R

PORT

S1B

10Ω

BULK

AGND

Type 2 (25.5W)

++

LTPoE 38.7W

++

LTPoE 52.7W

++

LTPoE 70W

3.32k

4.64k

5.90k

7.87k

10.0k

13.0k

–

TVS

LED

RESET

OUT

LTC4279

R

GATE

PWRMODE

1µF

100V

X7R

SENSE

MID

LEGACY

DUALPD

C

BULK

0.1Ω

++

LTPoE 90W

R

PM

VSSK

V

SMAJ58A

EE

UltraPWR – (Up to 123W*)

4279 TA01

V

EE

*Depending on ꢀ

PSE

4279fa

1

For more information www.linear.com/LTC4279

LTC4279

ABSOLUTE MAXIMUM RATINGS ^{(Notes 1 and 4)}

Supply ꢀoltages

SENSE........................................ ꢀ – 20ꢀ to ꢀ + 80ꢀ

EE

AGND – ꢀ ........................................... –0.3ꢀ to 80ꢀ

Operating Ambient Temperature Range

EE

ꢀSSK ................................... ꢀ – 0.3ꢀ to ꢀ + 0.3ꢀ

LTC4279I .............................................–40°C to 85°C

Junction Temperature (Note 2) ............................ 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)...................300°C

EE

LEGACY, MID, DUALPD, LED,

RESET, GATE, PWRMODE......... ꢀ – 0.3ꢀ to ꢀ + 80ꢀ

EE

OUT............................................ ꢀ – 80ꢀ to ꢀ + 80ꢀ

EE

PIN CONFIGURATION

TOP VIEW

20 19 18 17

MID

DNC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

RESET

DNC

1

2

3

4

5

6

16 DUALPD

15 LEGACY

14 DNC

DNC

DUALPD

LEGACY

PWRMODE

DNC

21

VSSK

SENSE

GATE

OUT

V

EE

V

EE

13 PWRMODE

12 DNC

VSSK

SENSE

11 DNC

V

EE

7

8

9 10

AGND

LED

S PACKAGE

16-LEAD PLASTIC SO

= 125°C, θ = 80°C/W, θ = 30°C/W

JA JC

UFD PACKAGE

20-LEAD (4mm × 5mm) PLASTIC QFN

= 125°C, θ = 43°C/W, θ = 3.4°C/W

T

JMAX

T

JMAX

JA

JC

EXPOSED PAD (PIN 21) IS ꢀ

EE

http://www.linear.com/product/LTC4279#orderinfo

ORDER INFORMATION

LEAD FREE FINISH

LTC4279IUFD#PBF

LTC4279IS#PBF

TAPE AND REEL

PART MARKING

4279

PACKAGE DESCRIPTION

20-Lead (4mm × 5mm) Plastic QFN

16-Lead Plastic SO

TEMPERATURE RANGE

LTC4279IUFD#TRPBF

LTC4279IS#TRPBF

–40°C to 85°C

LTC4279S

Consult LTC Marketing for parts specified with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

4279fa

2

For more information www.linear.com/LTC4279

LTC4279

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Notes 3 and 4)

SYMBOL PARAMETER CONDITIONS

AGND – ꢀ

MIN

TYP

MAX UNITS

ꢀ

Main PoE Supply ꢀoltage

EE

l

For IEEE Type 1 Compliant Output

45

51

57

ꢀ

++

For IEEE Type 2, DUALPD, LTPoE 38.7W and

++

LTPoE 52.7W Compliant Output

++

l

For LTPoE 70W and LTPoE 90W Compliant

54.75

57

ꢀ

Output

For UltraPWR Output

l

51

20

65

30

ꢀ

Undervoltage Lockout

AGND – ꢀ

25

UꢀLO_ꢀEE

EE

I

ꢀ

Supply Current

AGND – ꢀ = 55ꢀ

–1.7

mA

kΩ

EE

UꢀLO_ꢀEE

l

R

Supply Resistance

ꢀ

EE

< ꢀ

12

EE

Detection

l

Detection Current – Forced Current

Detection ꢀoltage – Forced ꢀoltage

First Point, AGND – ꢀ

Second Point, AGND – ꢀ

= 10ꢀ

220

143

240

160

260

180

µA

OUT

= 3.5ꢀ

OUT

AGND – ꢀ , 5µA ≤ I

≤ 500µA

OUT

l

First Point

Second Point

7

3

8

4

9

5

ꢀ

l

Detection Current Compliance

Detection ꢀoltage Compliance

Detection ꢀoltage Slew Rate

Min. ꢀalid Signature Resistance

Max. ꢀalid Signature Resistance

AGND – ꢀ

= 0ꢀ

0.8

0.9

12

mA

ꢀ

OUT

ꢀ

AGND – ꢀ , Open Port

10.4

OC

OUT

AGND – ꢀ , C

= 0.15µF (Note 6)

0.01

18.5

32

ꢀ/µs

kΩ

OUT PORT

15.5

27.5

17

29.7

Classification

l

ꢀ

Classification ꢀoltage

AGND – ꢀ , 0mꢀ ≤ ꢀ ≤ 8.8mꢀ

SENSE

16

8.8

7.5

8.8

20.5

10

ꢀ

mꢀ

ꢀ

CLASS

OUT

Classification Current Compliance

Mark State ꢀoltage

SENSE – ꢀSSK, ꢀ

= AGND

9.4

OUT

ꢀ

MARK

AGND – ꢀ , 0.1mꢀ ≤ ꢀ

≤ 0.5mꢀ

SENSE

10

OUT

Mark State Current Compliance

Classification Threshold ꢀoltage

SENSE – ꢀSSK, ꢀ

= AGND

10

mꢀ

OUT

SENSE – ꢀSSK

Class 0 to 1

Class 1 to 2

Class 2 to 3

Class 3 to 4

l

0.5

1.3

2.1

3.1

4.5

0.65

1.45

2.3

3.3

4.8

0.8

1.6

2.5

3.5

5.1

mꢀ

Class 4 to Overcurrent

Gate Driver

l

GATE Pin Pull-Down Current

Port Off, ꢀ

= ꢀ + 5ꢀ

0.4

0.08

mA

GATE

EE

= ꢀ + 1ꢀ

0.12

30

EE

GATE Pin Fast Pull-Down Current

GATE Pin On ꢀoltage

ꢀ

GATE

ꢀ

GATE

= ꢀ + 5ꢀ

mA

ꢀ

EE

l

– ꢀ , I

= 1µA

8

14

EE GATE

Output Voltage Sense

Power Good Threshold ꢀoltage

OUT Pin Pull-Up Resistance to AGND

l

ꢀ

– ꢀ

2

2.4

2.8

ꢀ

OUT

EE

0ꢀ ≤ (AGND – ꢀ ) ≤ 5ꢀ

300

500

700

kΩ

OUT

4279fa

3

For more information www.linear.com/LTC4279

LTC4279

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Notes 3 and 4)

SYMBOL PARAMETER

Current Sense

CONDITIONS

MIN

TYP

MAX UNITS

ꢀ

CUT

Overcurrent Sense

SENSE – ꢀSSK

Class 0, Class 3

Class 1

l

35.6

10.0

19.6

60.8

89.0

130

37.5

11.2

20.8

63.6

91.9

135

39.6

12.0

22.0

67.2

95.0

140

mꢀ

Class 2

Class 4

++

LTPoE 38.7W

++

LTPoE 52.7W, Dual-Signature PD

++

LTPoE 70W

160

225

165

232

170

240

++

LTPoE 90W

ꢀ

LIM

Active Current Limit

SENSE – ꢀSSK, ꢀ ≤ OUT ≤ ꢀ + 10ꢀ

EE EE

l

Class 0 to 3

Class 4

40.8

81.6

120

140

180

240

280

42.5

85.0

127

148

191

255

295

44.2

88.4

135

160

200

270

310

mꢀ

++

LTPoE 38.7W

++

LTPoE 52.7W, Dual-Signature PD

++

LTPoE 70W

++

LTPoE 90W

UltraPWR

Inrush Active Current Limit

SENSE – ꢀSSK, ꢀ ≤ OUT ≤ AGND – 29ꢀ,

Class 0 to 4, LTPoE

Dual-Signature PD

UltraPWR

EE

++

l

40.8

81.6

140

42.5

85.0

148

44.2

88.4

160

mꢀ

l

ꢀ

DC Disconnect Sense ꢀoltage

Short-Circuit Sense

SENSE – ꢀSSK (Note 10)

0.5

30

0.75

60

1

mꢀ

MIN

SENSE – ꢀSSK – ꢀ

90

SC

LIM

Digital Interface

Digital Input Low ꢀoltage

Digital Input High ꢀoltage

Internal Pull-Down to ꢀ

l

MID, LEGACY, DUALPD, RESET (Note 9)

MID, LEGACY, DUALPD

RESET

0.8

ꢀ

2.1

10

–10

3.6

µA

ꢀ

EE

ROC

Internal Pull-Up to ꢀ

ꢀ

ROC

Input Open Circuit ꢀoltage

RESET (Note 9)

LED Pin

l

Output Low

ꢀ

LED

– ꢀ , I

= 1mA

0.4

ꢀ

EE LED

LED Pin Current Limit

10

mA

PSE Timing Characteristics

l

t

Detection Time

Beginning to End of Detection (Note 6)

380

12

410

15

440

18

ms

DET

Class Event Duration, Single Class Event

Class Event Duration

(Note 6)

CLE1

CLE

9.6

12

14.4

0.1

10.8

24

Class Event Turn-On Duration

Mark Event Duration

C

PORT

= 0.6µF (Note 6)

CLEON

ME

(Note 6, Note 8)

6.8

16

8.6

20

Last Mark Event Duration

Power-On Delay

MEL

PON

From End of ꢀalid Detect to Application of

Power to Port (Note 6)

82

l

Turn-On Rise Time

Turn-On Ramp Rate

(AGND – ꢀ ): 10% to 90% of (AGND – ꢀ ),

15

24

µs

OUT

EE

C

PORT

= 0.15µF (Note 6)

C

PORT

= 0.15µF (Note 6)

10

ꢀ/µs

4279fa

4

For more information www.linear.com/LTC4279

LTC4279

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Notes 3 and 4)

SYMBOL PARAMETER CONDITIONS

= 0.15µF (Note 6)

MIN

TYP

MAX UNITS

l

t

Turn-On Class Transition

Fault Delay

C

PORT

0.1

ms

s

TOCL

ED

From I

or I Fault to Next Detect (Note 6)

1

1.3

3

CUT

LIM

LEGACY Mode Detection Backoff

Midspan Mode Detection Backoff

LEGACY Enabled, R

= 150Ω (Note 6)

2.7

2.3

3.3

2.7

s

PORT

LEGACY Disabled, MID Enabled, R

15.5kΩ (Note 6)

=

2.5

s

PORT

l

Power Removal Detection Delay

From Power Removal after t to Next Detect

(Note 6)

1

1.3

59

2.5

66

s

ms

DIS

t

Maximum Current Limit Duration During Port

Start-Up

(Note 6)

52

START

Maximum Overcurrent Duration after Port

Start-Up

(Note 6)

CUT

l

Maximum Overcurrent Duty Cycle

5.8

10

6.3

12

6.7

14

%

++

t

Maximum Current Limit Duration after Port

Start-Up

LTPoE PD, Dual-Signature PD or UltraPWR

ms

LIM

Mode Enabled (Note 6)

l

(Legacy or IEEE PD) and UltraPWR Mode

Disabled (Note 6)

52

59

66

3.6

380

ms

t

Maintain Power Signature (MPS) Pulse Width

Sensitivity

Current Pulse Width to Reset Disconnect Timer

(Notes 6 and 7)

1.6

MPS

l

Maintain Power Signature (MPS) Dropout Time (Notes 5 and 6)

320

4.5

350

ms

µs

DIS

Minimum Pulse Width for RESET

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 5: t is the same as t

Note 6: Guaranteed by design, not subject to test.

Note 7: The IEEE 802.3at specification allows a PD to present its

Maintain Power Signature (MPS) on an intermittent basis without being

defined by IEEE 802.3.

DIS

MPDO

Note 2: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 140°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 3: All currents into device pins are positive; all currents out of device

pins are negative.

Note 4: The LTC4279 operates with a negative supply voltage (with

respect to AGND). To avoid confusion, voltages in this data sheet are

referred to in terms of absolute magnitude.

disconnected. In order to stay powered, the PD must present the MPS for

within any t time window.

t

MPS

MPDO

Note 8: Load characteristics of the LTC4279 during Mark:

7ꢀ < (AGND – ꢀ ) < 10ꢀ or I < 50µA.

OUT

Note 9: The LTC4279 Digital Interface operates with respect to ꢀ . All

EE

logic levels are measured with respect to ꢀ

.

EE

Note 10: See Main PoE Power Supply section for DC disconnect related

power supply requirements.

4279fa

5

For more information www.linear.com/LTC4279

LTC4279

TYPICAL PERFORMANCE CHARACTERISTICS

++

Type 1 Power On Sequence

Type 2 Power On Sequence

LTPoE Power-On Sequence

FORCED VOLTAGE DETECTION

++

LTPoE

CLASSIFICATION

TYPE 2

CLASSIFICATION

TYPE 1

CLASSIFICATION

FORCED CURRENT

DETECTION

FORCED CURRENT

DETECTION

FORCED CURRENT

DETECTION

AGND – OUT

10V/DIV

V

= –55V

V

= –55V

V

= –55V

EE

++

CLASS 3 PD

CLASS 4 PD

LTPoE

70W PD

V

EE

POWER ON

100ms/DIV

POWER ON

100ms/DIV

POWER ON

100ms/DIV

4279 G01

4279 G02

4279 G03

UltraPWR, DUALPD, 802.3

Current Limits

++

LTPoE Current Limits

3.0

2.5

2.0

1.5

1.0

0.5

0

300

250

200

150

100

50

3.0

2.5

2.0

1.5

1.0

0.5

0

300

250

200

150

100

50

ULTRAPWR

90.0W

70.0W

52.7W

38.7W

DUALPD

CLASS 4

CLASS 0 TO 3

0

11

22

33

44

55

0

11

22

V

OUT

33

– V (V)

44

55

V

OUT

– V (V)

EE

4279 G04

4279 G05

MOSFET Gate Drive with Fast

Pull-Down

Inrush Current Limits

Classification Current Compliance

0

–4

–8

3.0

2.5

2.0

1.5

1.0

0.5

0

300

250

200

150

100

50

10Ω

FAULT

APPLIED

FAULT

REMOVED

ULTRAPWR

DUALPD

PORT

CURRENT

++

802.3/LTPoE

10A/DIV

CURRENT

LIMIT

GATE

VOLTAGE

10V/DIV

FAST

PULL-

DOWN

PORT

VOLTAGE

20V/DIV

–12

–16

–20

4279 G08

50µs/DIV

0

2

4

6

8

10

0

11

22

33

44

55

V

(mV)

V

OUT

– V (V)

EE

SENSE

4279 G07

4279 G06

4279fa

6

For more information www.linear.com/LTC4279

LTC4279

TYPICAL PERFORMANCE CHARACTERISTICS

V_EESupply Current vs Voltage

LED Current vs Voltage

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

20

16

12

8

85°C

25°C

–40°C

4

OUTPUT LOW

OUT = V

EE

0

10

20

30

40

(V)

50

60

70

0.1

1

10

80

V

(V)

EE

LED

4279 G09

4279 G10

DUALPD, MID and LEGACY

Current vs Voltage

RESET Current vs Voltage

2

0

16

14

12

10

8

–2

–4

–6

–8

6

–10

–12

–14

4

2

0

0.1

1

10

80

0.1

1

10

80

V

(V)

V

(V)

RESET

4279 G11

4279 G13

TEST TIMING DIAGRAMS

t

CLASSIFICATION

FORCED-

VOLTAGE

DET

FORCED-CURRENT

0V

V

PORT

V

OC

15.5V

20.5V

V

CLASS

t

CLE1

PD

CONNECTED

t

PON

V

EE

4279 F01

Figure 1. Detect, Single Event Class and Turn-On Timing

4279fa

7

For more information www.linear.com/LTC4279

LTC4279

TEST TIMING DIAGRAMS

t

CLASSIFICATION

DET

FORCED-

VOLTAGE

FORCED-CURRENT

0V

t

ME

V

PORT

t

MEL

V

OC

V

MARK

15.5V

20.5V

V

CLASS

t

CLE

t

CLE

PD

CONNECTED

t

CLEON

t

PON

V

EE

4279 F02

Figure 2. Detect, Two Event Class and Turn-On Timing

t

CLASSIFICATION

DET

FORCED-

VOLTAGE

FORCED-CURRENT

0V

t

ME

t

ME

V

PORT

t

MEL

V

OC

V

MARK

15.5V

20.5V

V

CLASS

t

CLE

t

CLE

PD

CONNECTED

t

CLEON

t

PON

V

EE

4279 F03

Figure 3. Detect, Three Event Class and Turn-On Timing

V

LIM

V

CUT

V

SENSE

V

MIN

V

TO V

EE

SENSE

TO V

EE

0V

t

, t

START CUT

LED

t

DIS

MPS

4279 F05

4279 F04

Figure 4. Current Limit Timing

Figure 5. DC Disconnect Timing

4279fa

8

For more information www.linear.com/LTC4279

LTC4279

PIN FUNCTIONS

RESET: Reset Input, Active Low. When logic low, the

LTC4279 is held inactive with the port off. When logic

high, the LTC4279 begins normal operation. RESET can

be connected to an external capacitor or RC network to

provide a power turn-on delay. Internal filtering of the

RESET pin prevents glitches less than 4.5μs wide from

LED: Port Powered LED. This pin is an open drain output

that pulls down to V when the port is powered. See the

EE

LED Drive section for details on this circuit.

AGND: Analog Ground. AGND pin should be connected

to the return for the V supply through a 10Ω resistor.

EE

V : Supply Input. Connect to a negative voltage of be-

resetting the LTC4279. Internally pulled up to V . See

ConfigurationPinProtectionsectionforproperconnection.

EE

ROC

tween –45V and –57V for Type 1 PSEs, –51V to –57V for

++

Type 2 PSEs and LTPoE 38.7W/52.7W PSEs, –54.75V

MID: Midspan Mode Input. When logic high, midspan

mode is enabled and the LTC4279 acts as a midspan

device. When logic low, midspan mode is disabled and

the LTC4279 acts as an endpoint device. Internally pulled

++

to –57V for LTPoE 70W/90W PSEs or –51V to –65V for

UltraPWR PSEs, relative to AGND.

VSSK: Kelvin Sense to V . Connect to sense resistor

EE

common node. Do not connect directly to V plane. See

down to V . See Configuration Pin Protection section for

EE

Kelvin Sense section for proper connection.

proper connection.

SENSE:CurrentSenseInput.SENSEmonitorstheexternal

LEGACY: LEGACY Mode Input. When logic high, LEGACY

modeisenabled.WithLEGACYmodeenabled,validdetec-

tion results include R too Low, Detect Good, R too

MOSFETcurrentviaa0.1ΩsenseresistorbetweenSENSE

and V . Whenever the voltage across the sense resistor

EE

SIG

exceeds the overcurrent detection threshold V , the

High, and C too High as defined in Table 2; all Class 0,

CUT

PD

current limit fault timer counts up. If the voltage across

1, 2 and 3 PDs presenting a valid detection signature are

the sense resistor reaches the current limit threshold

allocated13Wtoensurepre-802.3afPDsreceivesufficient

V

, the GATE pin voltage is lowered to maintain con-

++

power; IEEE PoE PDs and LTPoE PDs are detected and

LIM

stant current in the external MOSFET. See Applications

Information for further details. See Kelvin Sense section

for proper connection.

classified as normal. When logic low, LEGACY mode is

disabled. With LEGACY mode disabled only Detect Good

is considered a valid detection result. Warning: LEGACY

modeis,bydefinition,notIEEEcompliant.Internallypulled

GATE: Gate Drive. GATE should be connected to the gate

down to V . See Configuration Pin Protection section for

EE

of the external MOSFET through the R

resistor. When

GATE

proper connection.

the MOSFET is turned on, the gate voltage is driven to 12V

(typ) above V . During a current limit condition, the volt-

DUALPD:Dual-SignaturePDModeInput.Whenlogichigh,

DUALPD mode is enabled and the LTC4279 detects, clas-

sifiesandpowersdual-signaturePDs.Validdual-signature

PDsarepresentwhentwoType2PDsignaturesaredetected

andclassifiedinparallel. PWRMODEmustbesetto52.7W

or greater. When logic low, dual-signature PD support is

EE

age at GATE will be reduced to maintain constant current

through the external MOSFET. If the fault timer expires,

GATE is pulled down, turning the MOSFET off.

OUT:OutputVoltageMonitor.OUTshouldbeconnectedto

the output port. A current limit foldback circuit limits the

power dissipation in the external MOSFET by reducing the

current limit threshold when the drain-to-source voltage

exceeds 10V. A 500k resistor is connected internally from

OUT to AGND when the port is idle.

disabled. Internally pulled down to V . See Configuration

EE

Pin Protection section for proper connection.

PWRMODE: Maximum Power Mode. A single resistor

from the PWRMODE pin to V sets the LTC4279 maxi-

EE

mum deliverable power. See Applications Information for

the resistor value to desired maximum power mappings.

The resistor tolerance must be 1% or better. The PWR-

MODE pin can be set to 13W (Type 1), 25.5W (Type 2),

DNC: Do Not Connect. All pins identified with DNC must

be left unconnected.

++

LTPoE 38.7W,52.7W,70W,90WorUltraPWRmaximum

power levels.

4279fa

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For more information www.linear.com/LTC4279

LTC4279

APPLICATIONS INFORMATION

OVERVIEW

and increasing need for more than 25.5W of delivered

power.TheLTC4279respondstothismarketbyallowinga

reliable means of providing up to 90W of delivered power

PoweroverEthernet,orPoE,isastandardprotocolforsend-

ing DC power over copper Ethernet data wiring. The IEEE

group that administers the 802.3 Ethernet data standards

added PoE powering capability in 2003. This original PoE

spec, known as 802.3af, allowed for 48V DC power at up

to 13W. This initial specification was widely popular, but

13W was not adequate for some requirements. In 2009,

the IEEE released a new standard, known as 802.3at or

PoE+, increasing the voltage and current requirements to

provide 25.5W of power.

++

to an LTPoE PD. The LTPoE specification provides

reliable detection and classification extensions to the

existing IEEE PoE protocols that are backward compat-

ible and interoperable with existing Type 1 and Type 2

++

PDs. Unlike other proprietary PoE solutions, Linear’s

++

LTPoE provides mutual identification between the PSE

++

and PD. This ensures the LTPoE PD knows it may use

the requested power at start-up because it has detected

++

an LTPoE PSE.

The IEEE standard also defines PoE terminology. A device

that provides power to the network is known as a PSE, or

powersourcingequipment,whileadevicethatdrawspower

from the network is known as a PD, or powered device.

PSEs come in two types: Endpoints (typically network

switches or routers), which provide data and power; and

Midspans, which provide power but pass through data.

MidspansaretypicallyusedtoaddPoEcapabilitytoexisting

non-PoE networks. PDs are typically IP phones, wireless

access points, security cameras, and similar devices.

Dual-Signature PD Systems

There exist proprietary solutions in which the data and

spare pairs present two separate and individually valid PD

signatures. Such systems provide roughly 51W at the PD

interface. Each PD power channel, viewed in isolation, is

fully compatible with IEEE 802.3at.

One example of a dual-signature PD system is shown in

Figure 7. As shown, the PSE controller simultaneously de-

tects and classifies both PDs. Once successfully identified,

the lumped PDchannelis providedtwicetheClass4Current

Inrush, twice the Class 4 Current Cutoff, twice the Class 4

CurrentLimit,andnormalClass4DCDisconnectallocations.

++

LTPoE Evolution

Even during the process of creating the IEEE PoE+ 25.5W

specification it became clear that there was a significant

CAT 5

20Ω MAX

ROUNDTRIP

0.05µF MAX

PSE

PD

RJ45

4

RJ45

4

5

GND

SPARE PAIR

1

AGND

Tx

Rx

2

3

2

3

DATA PAIR

PSE

0.1µF

Rx

Tx

V

EE

GATE

GND

DC/DC

6

PWRGD

+

CONVERTER

PD

CONTROLLER

–54V –54V

–54V

V

OUT

7

8

7

–

IN

OUT

8

SPARE PAIR

4279 F06

Figure 6. Power over Ethernet System Diagram

4279fa

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For more information www.linear.com/LTC4279

LTC4279

APPLICATIONS INFORMATION

PSE

PD

GND

RJ45

1

AGND

2

3

2

3

+

OUT

GND

PWRGD

DC/DC

CONVERTER

V

PD

–

CONTROLLER

PSE

CONTROLLER

6

–V

OUT

IN

4

V

EE

GATE

OUT

5

7

5

7

–54V

+

OUT

GND

PWRGD

PD

DC/DC

CONVERTER

V

–

CONTROLLER

8

–V –V

IN

OUT

4279 F07

Figure 7. Dual-Signature PD Power over Ethernet System Diagram

LTC4279 Single Port PSE

sified and powered on by the LTC4279. Current inrush,

cutoff, and limit are doubled to support dual-signature

PD topologies.

The LTC4279 is a fourth-generation single port PSE

controller. Virtually all necessary circuitry is included to

implementanIEEE802.3atcompliantPSEdesign,requiring

only an external power MOSFET and sense resistor; these

minimizepowerlosscomparedtoalternativedesignswith

an on-board MOSFET and sense resistor.

++

When in LTPoE or Type 2 mode, the LTC4279 is a fully

IEEE-compliantType2PSEsupportingautonomousdetec-

tion, classificationandpoweringofType1andType2PDs.

When in Type 1 mode, the LTC4279 is a fully autonomous

802.3af Type 1 PSE solution. Two-event classification is

prohibited and Class 4 PDs are automatically treated as

Class 0 PDs.

TheLTC4279supportssevenPDpowerlevels.Themodeis

setbythePWRMODEresistor,assampledduringresetexit.

++

When in LTPoE mode, the LTC4279 extends PoE power

++ ++

deliverycapabilitiestooneoffourLTPoE levels.LTPoE

is a Linear Technology proprietary specification allowing

UltraPWR mode enables the PSE to power all PDs pre-

senting a valid detection and classification signature with

enhancedinrushandoperationalcurrentlimits,regardless

of classification result. This mode aggressively powers

nonstandard PDs.

++

for the delivery of up to 90W to LTPoE compliant PDs.

++

The LTPoE architecture extends the 802.3at physical

power negotiation to include 38.7W, 52.7W, 70W and

90W power levels.

PoE BASICS

When DUALPD is enabled, the LTC4279 supports dual-

signature PD topologies. Dual-signature PDs are defined

as two PDs whose signature appears at the PD Power

Interface (PI) as the parallel combination of two Type 2

PDs.Dual-signaturePDsareautonomouslydetected,clas-

Common Ethernet data connections consist of two or four

twisted pairs of copper wire (commonly known as CAT-5

cable), transformer-coupled at each end to avoid ground

4279fa

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For more information www.linear.com/LTC4279

LTC4279

APPLICATIONS INFORMATION

loops. PoE systems take advantage of this coupling ar-

rangement by applying voltage between the center-taps

of the data transformers to transmit power from the PSE

to the PD without affecting data transmission. Figure 6

shows a high-level PoE system schematic.

Table 1 shows the PWRMODE encodings. The PWRMODE

pin is configured by connecting R between the PWR-

PM

MODEpinandV .ThePWRMODEeffectonPSEbehavioris

EE

describedintheClassificationandPowerControlsections.

Table 1. PWRMODE Encodings

To avoid damaging legacy data equipment that does not

expect to see DC voltage, the PoE specification defines

a protocol that determines when the PSE may apply and

remove power. Valid PDs are required to have a specific

25k common mode resistance at their input. When such a

PDisconnectedtothecable,thePSEdetectsthissignature

resistance and turns on the power. When the PD is later

disconnected, the PSE senses the open circuit and turns

power off. The PSE also turns off power in the event of a

current fault or short-circuit.

PWRMODE

R

( 1ꢀ%

PM

Type 1 (13W)

Type 2 (25.5W)

++

LTPoE 38.7W

++

LTPoE 52.7W

++

LTPoE 70W

2.37k

3.32k

4.64k

5.90k

7.87k

10.0k

13.0k

++

LTPoE 90W

UltraPWR

The LEGACY pin determines whether pre-IEEE standard

legacy PDs are powered.

When a PD is detected, the PSE looks for a classification

signature that tells the PSE the maximum power the PD

will draw. The PSE can use this information to reject a

PD that will draw more power than the PSE has available.

The MID pin determines whether midspan detection tim-

ing is enabled. The MID pin should be logic high if the

standalone application is a midspan.

OPERATING MODES

DETECTION

The LTC4279 is a fully autonomous PSE controller and

provides a complete PSE solution for detection, classifi-

cation and powering of PDs in an IEEE 802.3 or LTPoE

compliant system.

Detection Overview

++

Toavoiddamagingnetworkdevicesthatwerenotdesigned

to tolerate DC voltage, a PSE must determine whether the

connected device is a valid PD before applying power. The

IEEE specification requires that a valid PD have a common

mode resistance of 25k 5% at any port voltage below

10V. The PSE must accept resistances that fall between

19k and 26.5k, and it must reject resistances above 33k

or below 15k (shaded regions in Figure 8). The PSE may

choose to accept or reject resistances in the undefined

areasbetweenthemust-acceptandmust-rejectranges. In

particular,thePSEmustrejectstandardcomputernetwork

ports, many of which have 150Ω common mode termina-

tion resistors that will be damaged if power is applied to

them (the black region at the left of Figure 8).

The LTC4279 will power all valid PDs with I

and I

LIM

CUT

values based on the PWRMODE pin and the PD classifica-

tion result.

The LTC4279 will remove power automatically if the port

generates a current cutoff or limit fault. The LTC4279

senses removal of a PD and turns off power when the

PD is disconnected. Internal control circuits comply with

IEEE timing and electrical parameters.

Power-On Reset and the Configuration Pins

The initial LTC4279 configuration depends on the state

of the MID, LEGACY, DUALPD and PWRMODE pins dur-

ing reset exit. Reset occurs at power-up or whenever the

RESETpinispulledlow.Changinganyoftheconfiguration

pins after power-up will not change the behavior of the

LTC4279 until a subsequent reset occurs.

Table 2 shows the possible detection results. If a Detect

Good result is acquired the LTC4279 will proceed to clas-

sification.

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For more information www.linear.com/LTC4279

LTC4279

APPLICATIONS INFORMATION

RESISTANCE 0Ω

10k

20k

30k

sufficient power. When LEGACY is disabled, only PDs

presenting Detect Good (including compliant IEEE PoE

150Ω (NIC)

23.75k

26.25k

26.5k

PD

++

and LTPoE PDs) will be considered valid.

PSE

15k 19k

33k

4279 F08

Detection of Dual-Signature PDs

Figure 8. IEEE 802.3at Signature Resistance Ranges

Table 2. Detection Status

ProprietaryPDsthatemployadual-signaturePDtopology

are detected in parallel. Such PDs will present a parallel

resistance of one half of the Detect Good resistance. This

MEASURED PD SIGNATURE

(TYPICAL%

DETECTION RESULT

parallel detection resistance is located in the R too Low

SIG

Incomplete or Not Yet Tested

<2.4k

Detect Status Unknown

Short-Circuit

range as shown in Table 2. When DUALPD is enabled,

dual-signature PDs (R too Low detection results) will

SIG

Capacitance > 2.7µF

C

too High

too Low

PD

proceed to classification regardless of the LEGACY mode.

2.4k < R < 17k

R

SIG

PD

17k < R < 29k

Detect Good

R too High

SIG

PD

CLASSIFICATION

>29k

>50k

Open Circuit

802.3af Classification

Voltage > 10V

Port Voltage Outside Detect Range

A PD must present a classification signature to the PSE to

indicate the maximum power it will draw while operating.

The IEEE specification defines this signature as a constant

current draw when the PSE port voltage is in the V

CLASS

275

165

range (between 15.5V and 20.5V), with the current level

indicating one of 5 possible PD classes. Figure 10 shows

a typical PD load line, starting with the slope of the 25k

signature resistor below 10V, then transitioning to the

classification signature current (in this case, Class 3) in

FIRST

DETECTION

POINT

25kΩ SLOPE

SECOND

DETECTION

POINT

VALID PD

the V

range. Table 3 shows the possible classifica-

CLASS

tion values.

0V-2V

OFFSET

VOLTAGE

When LEGACY is enabled all Class 0, 1, 2 and 3 PDs are

allocated 13W to ensure legacy PDs receive sufficient

power.LegacyPDsmayhaveanIEEE-likedetectionsigna-

ture and do not support physical classification. Therefore,

allocating 13W to all Type 1 and legacy PDs ensures full

legacy PD support.

4279 F09

Figure 9. PD Detection

Detection of Legacy PDs

Proprietary PDs that predate the original IEEE 802.3af

standard are commonly referred to today as legacy PDs.

One type of legacy PD uses a large common mode capaci-

tance (>10μF) as the detection signature. Note that PDs in

this range of capacitance are defined as invalid, so a PSE

that detects legacy PDs is technically noncompliant with

the IEEE specification. The LTC4279 can be configured to

detect this type of legacy PD when LEGACY is enabled.

When LEGACY is enabled, valid detection results include

Table 3. 802.3af and 802.3at Classification Values

(LEGACY = Disabled%

CLASS

Class 0

Class 1

Class 2

Class 3

Class 4

PWRMODE = TYPE 1

PWRMODE = TYPE 2

No Class Signature Present; Treat Like Class 3

3W

7W

13W

C

too High, R too low, Detect Good, and R too

13W (Demote to Class 0)

25.5W (Type 2)

PD

SIG SIG

High. PDs presenting Class 0, 1, 2 or 3 are assigned Class

0 power allocation to ensure pre-802.3af PDs receive

4279fa

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For more information www.linear.com/LTC4279

LTC4279

APPLICATIONS INFORMATION

ThePSEwillclassifythePDimmediatelyafterasuccessful

detection cycle. The PSE measures the PD classification

signaturebyapplying18Vfor12ms(bothvaluestypical)to

the port via the OUT pin and measuring the resulting cur-

rent.Ifavalidclassificationresultisobtained,theLTC4279

A Type 2 PD that is requesting more than 13W will indi-

cate Class 4 during normal 802.3af classification. If the

LTC4279 sees Class 4, it forces the port to a specified

lowervoltage(calledthemarkvoltage,typically9V),pauses

briefly, and then re-runs classification to verify the Class

4 reading (Figure 2). The second cycle informs the PD

that it is connected to a Type 2 PSE capable of supplying

Type 2 power levels.

will use the result to set the I

and I thresholds.

CUT

LIM

The LTC4279 supports 802.3af 1-event classification

regardless of the PWRMODE setting. A Class 0 to 3 result

during the first classification event will result in the PD

receiving the appropriate amount of power as shown in

Table 3.

Note that the LTC4279 only runs the second classification

cycle when it detects a Class 4 device; if the first cycle

returns Class 0 to 3, the port determines it is connected

to a Type 1 PD and does not run the second classifica-

tion cycle.

When a Class 4 result is obtained the LTC4279 response

dependsonPWRMODE,asshowninTable3.IfPWRMODE

is set to Type 1 then the PD will be powered on after re-

ceiving only a single class event and will be allocated only

13W. If PWRMODE is set to Type 2 or higher, additional

class events will be issued as described in the following

sections.

Invalid Type 2 Class Combinations

The 802.3at specification defines a Type 2 PD class

signature as two consecutive Class 4 results; a Class 4

followed by a Class 0 to 3 is not a valid signature. If the

PD presents an invalid Type 2 signature (Class 4 followed

by Class 0 to 3), the LTC4279 will not provide power and

will restart the detection process.

100

90

Dual-Signature PD Classification

80

Dual-signature PDs are supported by performing a paral-

lel classification. When a dual-signature PD is present,

each PD will draw a nominal classification current of up

to 40mA, for a total possible of 80mA. A dual-signature

OVER

70

60

50

40

30

20

10

0

CURRENT

PSE LOAD LINE

48mA

PD is validated when the LTC4279 observes both an R

SIG

too Low detection result and a multiple-event overcurrent

classification result.

CLASS 4

CLASS 3

33mA

23mA

++

Extended Power LTPoE Classification

CLASS 2

TYPICAL

CLASS 3

PD LOAD

LINE

The 802.3at 2-event physical classification method is

14.5mA

6.5mA

CLASS 1

CLASS 0

++

extended using LTPoE 3-event classification signaling

methods (Figure 3).

0

5

10

15

20

25

++

LTPoE 3-eventclassificationandpowerlevelsareenabled

VOLTAGE (V

)

CLASS

4279 F10

by setting PWRMODE to 38.7W or higher.

Figure 10. PD Classification

++

The higher levels of LTPoE delivery impose additional

++

layout and component selection constraints. LTPoE

802.3at 2-Event Classification

PDs requesting more than the available power limits are

TheLTC4279supports802.3at2-eventphysicalclassifica-

tion when PWRMODE is set to Type 2 or higher.

not powered. For example, if PWRMODE is set to 70W

++

and an LTPoE 90W PD is detected and classified, the

PD will not be powered.

4279fa

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For more information www.linear.com/LTC4279

LTC4279

APPLICATIONS INFORMATION

Power Allocation

UltraPWR MODE

LTC4279allocatespowerbasedonthePWRMODEsetting

as described in Table 1. The PWRMODE informs the PSE

howmuchpowerisavailable. BasedonthePDclassresult

the PD is allocated power if sufficient power is available

as shown in Figure 11. In some situations the PD will be

A PSE in UltraPWR mode issues up to three class events

andpowersallvalidPDswithmaximumdeliverablepower,

as determined by V . Figure 12 shows PSE source

PSE

power (at the PSE RJ45 jack) and PD delivered power (at

the PD RJ45 jack) vs V . The gray shaded area above

PSE

++

denied power in accordance with the LTPoE protocol.

60V shows voltages exceeding SELV maximum; systems

exceeding SELV maximum voltage may incur additional

regulatory hurdles.

DEVICE

STANDARD

TYPE TYPE 1 TYPE 2 38.7W 52.7W 70W

TYPE 1 13W 13W 13W 13W 13W

PSE PWRMODE SETTING

++

802.3at

LTPoE

90W

POWER CONTROL

13W

802.3at

The primary function of the LTC4279 is to control the

delivery of power to the PSE port. It does this by control-

ling the gate drive voltage of an external power MOSFET

while monitoring the current via an external sense resis-

tor and the output voltage at the OUT pin. This circuitry

TYPE 2 13W 25.5W 25.5W 25.5W 25.5W 25.5W

38.7W 13W 25.5W 38.7W 38.7W 38.7W 38.7W

PD

52.7W 13W 25.5W

–

52.7W 52.7W 52.7W

++

LTPoE

70W

90W

13W 25.5W

–

70W

–

70W

90W

serves to couple the raw V input supply to the port in

EE

a controlled manner that satisfies the PD’s power needs

Figure 11. PSE PWRMODE vs PD Class Power Allocation

while minimizing both power dissipation in the MOSFET

++

For example, an LTPoE 70W PSE will refuse power to

and disturbances on the V backplane.

EE

++

an LTPoE 90W PD, but will power IEEE 802.3at PDs

++

and LTPoE PDs requesting 70W and under with their

Inrush Control

full power allocation. In comparison, an IEEE Type 2 PSE

Once the decision has been made to turn on a port, the

LTC4279 ramps up the GATE pin of the external MOSFET in

acontrolledmanner.Undernormalpower-upcircumstances,

the MOSFET gate voltage will rise until the port current

reaches the inrush current limit level, at which point the

will issue full power allocation to Type 1 and Type 2 PDs;

++

all LTPoE PDs will be powered with a demoted alloca-

tion of 25.5W. An IEEE Type 1 PSE will issue full power

++

allocation to IEEE Type 1 PDs; all Type 2 and LTPoE

PDs will be powered with a demoted allocation of 13W.

GATE pin will be servoed to maintain the specified I

INRUSH

) runs.

current. During this inrush period, a timer (t

ABOVE SELV

START

180

When output charging is complete, the port current will fall

and the GATE pin will be allowed to continue rising to fully

enhance the MOSFET and minimize its on-resistance. The

160

140

120

100

80

finalV isnominally12V.Ifthet

timerexpiresandthe

GS

START

PD is over the current limit level, the port will be turned off.

Per the IEEE specification, the LTC4279 will normally set

60

the inrush current limit (I ) to 425mA during inrush at

LIM

40

port turn-on, and then switch to the classified I setting

PSE SOURCE POWER

LIM

PD DELIVERED POWER AT 50m

PD DELIVERED POWER AT 100m

20

0

once inrush has completed.

52

54

56

58

60

62

64

66

When DUALPD is enabled and a dual-signature PD is

successfully detected and classified, the inrush current

will be doubled. This allows dual-signature PDs to be

powered up in parallel.

V

PSE

(V)

4279 F12

Figure 12. UltraPWR Power vs V_PSE

4279fa

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For more information www.linear.com/LTC4279

LTC4279

APPLICATIONS INFORMATION

When UltraPWR mode is enabled and a legacy, dual-

The I

current limiting circuit is always enabled and

LIM

++

signature, LTPoE or IEEE PD is detected and classified,

actively limits port current. I

is set to a lower value

CUT

I

will be set to 1.5A to provide more substantial inrush

than I to allow the port to tolerate minor faults without

current limiting.

LIM

current for custom PDs.

A second timer, t , is enabled when a PD is allocated

LIM

Current Cutoff and Limit

more than 25.5W to provide more aggressive MOSFET

The LTC4279 automatically maintains two current thresh-

protection and turn off a port before MOSFET damage

olds (I

CUT

and I ), each with a corresponding timer

can occur. The t

timer starts when the I

threshold

CUT

LIM

(t

and t ). The I

and I

thresholds depend on

is exceeded. When the t timer reaches 12ms (typical)

LIM

CUT

LIM

several factors: the PD Class, the UltraPWR mode, and

the DUALPD and LEGACY pin states.

the port is turned off.

t

is not enabled when a PD is allocated 25.5W or less.

LIM

Table4showstheI andI valuesthatwillbeautomati-

Instead,t behaviorsaretrackedbythet timer,which

CUT

LIM

CUT

events.

cally set depending on LEGACY pin, the UltraPWR state

counts up during both I and I

LIM

CUT

and the negotiated PD class. When UltraPWR is enabled,

I

is disabled and I

is 2950mA (typical) regardless

I

Foldback

CUT

LIM

of classification result.

The LTC4279 features a two-stage foldback circuit that

reduces the port current if the port voltage falls below the

normal operating voltage. This helps keep MOSFET power

dissipation at safe levels.

Table 4. Typical I_CUTand I_LIMValues

CLASS

ULTRAPWR

Disabled

LEGACY

Disabled

Enabled

I

LIM

CUT

Class 1

112mA

206mA

375mA

638mA

425mA

850mA

Class 2

The LTC4279 will support current levels well beyond the

maximum values in the 802.3at specification. High power

PSEimplementationsrequirealargerexternalMOSFETand

possibly additional heat sinking. Due to the high inrush

current extra care is required during MOSFET selection.

See the External Component Selection – External MOSFET

section for more information.

Class 3, 0

Class 0, 1, 2, 3

Class 4

Don't Care

++

LTPoE 38.7W

919mA 1275mA

Dual-Signature PD/

Don't Care 1350mA 1488mA

++

LTPoE 52.7W

++

LTPoE 70W

Disabled

Enabled

Don't Care 1650mA 1913mA

Don't Care 2325mA 2550mA

Don't Care Disabled 2950mA

++

LTPoE 90W

MOSFET Fault Detection

All Classes

The LTC4279 is designed to tolerate significant levels of

abuse, but in extreme cases it is possible for the external

MOSFETtobedamaged.AfailedMOSFETmayshortsource

to drain, which will make the port appear to be on when

it should be off; this condition may also cause the sense

resistor to fuse open, turning off the port but causing the

LTC4279 SENSE pin to rise to an abnormally high volt-

age. A failed MOSFET may also short from gate to drain,

causing the LTC4279 GATE pin to rise to an abnormally

high voltage. The LTC4279 OUT, SENSE and GATE pins

are designed to tolerate up to 80V faults without damage.

Per the IEEE specification, the LTC4279 will allow the port

current to exceed I for a limited period of time before

CUT

removing power from the port, whereas it will actively

control the MOSFET gate drive to keep the port current

below I . The port does not take any action to limit the

LIM

currentwhenonlytheI thresholdisexceeded,butdoes

CUT

start the t

timer. If the current drops below the I

CUT

timer

current threshold before its timer expires, the t

CUT

counts back down, but at 1/16 the rate that it counts up. If

thet timerreaches60ms(typical)theportisturnedoff.

CUT

Thisallowsthecurrentlimitcircuitrytotolerateintermittent

overload signals with duty cycles below about 6%; longer

duty cycle overloads will turn the port off.

If the LTC4279 sees any of these conditions for more than

180μs, it resets the entire chip.

4279fa

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For more information www.linear.com/LTC4279

LTC4279

APPLICATIONS INFORMATION

Disconnect

External MOSFET

The LTC4279 monitors the powered port to ensure the

PD continues to draw the minimum specified current. A

disconnecttimercountsupwheneverportcurrentisbelow

7.5mA(typ),indicatingthatthePDhasbeendisconnected.

CarefulselectionofthepowerMOSFETiscriticaltosystem

reliability. LTC recommends the NXP PSMN075-100MSE

for proven reliability in Type 1 and Type 2 PSE applica-

tions. LTC recommends the NXP PSMN040-100MSE for

++

If the t timer expires, the port will be turned off. If the

dual-signature PD and LTPoE PSE applications. SOA

DIS

current returns before the t timer runs out, the timer

curves are not a reliable specification for MOSFET selec-

DIS

resets. As long as the PD exceeds the minimum current

tion. Contact LTC Applications before using a MOSFET

level for t

more often than t , it will remain powered.

otherthanoneoftheserecommendedparts.R

(Figure

MPS

DIS

GATE

13) is an essential part of the current limit control loop.

The R value may depend upon MOSFET selection. An

additional RC network across the MOSFET drain and gate

is required for the UltraPWR MOSFET. See the UltraPWR

Endpoint PSE application circuit for details.

GATE

EXTERNAL COMPONENT SELECTION

Main PoE Power Supply and Bypassing

The LTC4279 requires one supply voltage to operate at

V . V requires a negative voltage relative to AGND

EE

Sense Resistor

within the range specified in the Electrical Characteristics

for each PSE Type.

TheLTC4279isdesignedtousea0.1Ωcurrentsenseresis-

tor to reduce power dissipation. In order to meet the I

CUT

V

is the main isolated PoE supply that provides power

EE

and I

accuracy required by the IEEE specification, the

LIM

to the PD. Because it supplies a relatively large amount

of power and is subject to significant current transients,

it requires more design care than a simple logic supply.

senseresistorshouldhave 1%toleranceorbetter, andno

morethan 200ppm/ꢀCtemperaturecoefficient.Thesense

resistor must be sized according to power dissipation. See

the Layout Guidelines section for proper Kelvin sensing.

For minimum IR loss and best system efficiency, set V

EE

near maximum amplitude (57V, or 65V for UltraPWR),

leaving enough margin to account for transient over- or

undershoot, temperature drift, and the line regulation

specifications of the particular power supply used.

Port Output Capacitor

The port requires a 0.22μF capacitor across the LTC4279

OUTpinandAGNDpintokeeptheLTC4279stablewhilein

currentlimitduringstartuporoverload. Commonceramic

capacitors often have significant voltage coefficients; this

means the capacitance is reduced as the applied volt-

age increases. To minimize this problem, X7R ceramic

capacitors rated for at least 100V are recommended and

must be located close to the OUT pin and AGND pin (see

Layout Guidelines).

Bypass capacitance between AGND and V is very impor-

EE

tant for reliable operation. If a short-circuit occurs at the

port output, it can take as long as 1μs for the LTC4279 to

begin regulating the current. During this time the current

is limited only by the small impedances in the circuit. A

high current spike typically occurs, causing a voltage

transient on the V supply and possibly causing the

EE

LTC4279 to reset due to a UVLO fault. A 1μF, 100V X7R

capacitor placed near the AGND and V pins along with

EE

Surge Protection

an electrolytic bulk capacitor of at least 47µF across the

mainsupplyisrecommendedtominimizespuriousresets.

Ethernet ports can be subject to significant cable surge

events.TokeepPoEvoltagesbelowasafelevelandprotect

the application against damage, protection components

(Figure13)arerequiredatthemainsupply,attheLTC4279

supply pins and at the output port.

To ensure compliance with DC disconnect, V supply

ripple and noise must be less than 100mV at frequen-

cies above 150kHz. Note that supply ripple and noise is

also limited by the IEEE 802.3at standard.

EE

P-P

Bulk transient voltage suppression (TVS

) and bulk

BULK

For UltraPWR applications only, limit dV/dt on the V

supply to less than 10V/ms when the supply is starting up.

EE

capacitance (C

) are required across the main PoE

BULK

4279fa

17

For more information www.linear.com/LTC4279

LTC4279

APPLICATIONS INFORMATION

R10

10Ω

0805

C4

C

BULK

D1

SMAJ58A

1µF

100V

X7R

R

PU

C6

V

EE

0.22µF

100V

X7R

100Ω

AGND

RESET

MID

RESET

MID

TVS

BULK

U1

LTC4279

DUALPD

LEGACY

DUALPD

LEGACY

V

VSSK SENSE GATE OUT

EE

+

R

GATE

D3

OUT TO

S1B PORT

R

S1

–

V

EE

4279 F13

Q1

Figure 13. LTC4279 Surge Protection

supply and should be sized to accommodate system level

surge requirements.

ance when the port is off. Pull the LED up to a supply with a

currentlimitingresistor.Selecttheresistorvaluetoprovide

enough LED current for adequate LED brightness and limit

thecurrenttobelowtheLTC4279LEDpincurrentlimitover

the full supply range. The resistor must also have a power

rating capable of the maximum supply voltage minus the

LED drop and LED current. If the main PoE power supply

is driving the LED, the pull-up resistor must connect to

the LTC4279 AGND pin side of the surge protection 10Ω

resistor. Refer to the Typical Application figure.

The LTC4279 (U1) requires a 10Ω, 0805 resistor (R10) in

seriesfromsupplyAGNDtotheLTC4279AGNDpin.Across

the LTC4279 AGND pin and V pin are an SMAJ58A, 58V

EE

TVS (D1) and a 1µF, 100V bypass capacitor (C4). These

components must be placed close to the LTC4279 pins.

Finally, the port requires an S1B clamp diode (D3) from

OUT to supply AGND. The diode protects the port from

harmful surges that could cause OUT to go above AGND.

This diode must have low impedance paths to the port.

LAYOUT GUIDELINES

See Layout Guidelines for additional information on parts

placement.

Strict adherence to parts placement and board layout is

critical for optimal current reading accuracy, IEEE compli-

ance,systemrobustnessandthermaldissipation.Referto

the DC2541 demo board as a layout reference. Figure 14

is a cutout portion of the DC2541 that displays the focus

topics in this section. The components are referenced in

Figure 13.

Configuration Pin Protection

The logic input pins (RESET, MID, LEGACY and DUALPD)

may be hard tied to the AGND pin or to V . Alternatively,

EE

if a pull-up resistor (R ) is implemented from a logic

PU

input pin to the LTC4279 supply, connect the resistor to

the protected side of the 10Ω resistor at the AGND pin. For

logic input pins configured off board through a connector,

add a 100Ω resistor in series with the respective pin for

protection during high voltage transients.

Kelvin Sense

Proper connection of the port current Kelvin sense lines is

importantforcurrentthresholdaccuracyandIEEEcompli-

ance. Refer to Figure 14 for an example layout of these

Kelvin sense lines. The LTC4279 VSSK pin connects to a

LED Drive

Kelvin sense trace to the sense resistor (V side) pad and

EE

ConnectanLEDtotheLTC4279LEDpinforaportonstatus

indicator. The LED pin open drain pull-down output pulls

isnotconnecteddirectlytoV copperareas.Similarly,the

EE

LTC4279 SENSE pin connects to a Kelvin sense trace that

downtoV whentheportispoweredonandishighimped-

leads to the sense resistor (SENSE side) pad and is not

EE

4279fa

18

For more information www.linear.com/LTC4279

LTC4279

APPLICATIONS INFORMATION

heat out away from the components. This is particularly

important around the power MOSFET (Q1) during current

limit conditions.

connected in the power path between the sense resistor

and the MOSFET. Figure 14 shows the two Kelvin traces

from the LTC42479 (U1) to the sense resistor (R ). The

S1

LTC4249 V pins and the sense resistor V pad connect

EE

to the V copper areas.

EE

R10

C6

Parts Placement

Q1

The placement of key components around the LTC4279 is

essentialforapplicationaccuracy,stabilityandrobustness.

Figure14showstheportOUTcapacitor(C6)andLTC4279

surge protection components located near the LTC4279.

C4

D1

U1

Thermal Considerations

RS1

The power paths from the main power supply to the port

output will have high currents pass through at peak port

power. Use wide traces and copper areas, along multiple

vias to keep the power path resistance low. Use copper

areas around power path components to help spread

4279 F14

Figure 14. Example LTC4279 Layout

TYPICAL APPLICATIONS

IEEE 802.3at, Type 1 or Type 2, Endpoint PSE

T1

SML-012P8T

GREEN

10Ω

0805

+

TR0

•

C

75Ω

12k

1/2W

BULK

TVS

BULK

T0C

–

TR0

+

DATA AND

1µF

100V

X7R

TR1

V

EE

•

75Ω

POWER OUT

SMAJ58A

T1C

1

–

TR1

DATA

TO

2

3

4

5

6

7

8

V

EE

100Ω

+

PHY

TR2

AGND

•

RESET

MID

RJ45

75Ω

T2C

–

TR2

DUALPD

LEGACY

LTC4279

LED

0.22µF

100V

X7R

+

TR3

•

PWRMODE

75Ω

T3C

V

VSSK SENSE GATE OUT

EE

–

TR3

200Ω

R

PM

0.01µF

200V

×4

S1B

0.1Ω

V

EE

PSMN075-100MSE

1000pF

2kV

MAXIMUM PD INPUT POWER

TYPE 1 (13W)

R

V

RANGE

T1

4279 TA02

PM

EE

2.37k

–45V to –57V

749023015

749022017

TYPE 2 (25.5W)

3.32k

–51V to –57V

4279fa

19

For more information www.linear.com/LTC4279

LTC4279

TYPICAL APPLICATIONS

IEEE 802.3at, Type 1 or Type 2, Midspan PSE

10Ω

0805

1µF

100V

X7R

SMAJ58A

12k

1/2W

V

EE

100Ω

AGND

RESET

MID

SML-012P8T

GREEN

TVS

BULK

S1B

LED

DUALPD

LTC4279

0.22µF

100V

X7R

C

BULK

LEGACY

PWRMODE

V

EE

VSSK SENSE GATE OUT

200Ω

0.1Ω

R

PM

V

EE

PSMN075-100MSE

ETH1-230L

•

DATA AND

POWER OUT

DATA IN

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

RJ45

4279 TA03

75Ω

0.01µF

200V

0.01µF

200V

1000pF

2kV

1000pF

2kV

MAXIMUM PD INPUT POWER

TYPE 1 (13W)

R

V

RANGE

PM

EE

2.37k

–45V to –57V

TYPE 2 (25.5W)

3.32k

–51V to –57V

4279fa

20

For more information www.linear.com/LTC4279

LTC4279

TYPICAL APPLICATIONS

++

LTPoE or Dual-Signature PD, Midspan or Endpoint, 4-Pair PSE Options

10Ω

0805

1µF

100V

X7R

SMAJ58A

12k

1/2W

C

BULK

V

EE

100Ω

AGND

RESET

MID

RESET

MID

SML-012P8T

TVS

BULK

GREEN

S1B

LED

DUALPD

LTC4279

0.22µF

100V

X7R

LEGACY

PWRMODE

V

EE

VSSK SENSE GATE OUT

200Ω

R

0.1Ω

SENSE

R

PM

V

EE

PSMN040-100MSE

WURTH 749022016

COILCRAFT ETH1-460L

+

TR0

•

75Ω

0.01µF, 200V

T0C

–

TR0

+

DATA AND

POWER OUT

TR1

•

75Ω

T1C

1

–

TR1

2

3

4

5

6

7

8

DATA

SOURCE

+

TR2

•

RJ45

T2C

–

TR2

+

TR3

•

T3C

–

TR3

1000pF

2kV

4279 TA04

MAXIMUM PD INPUT POWER

++

V

RANGE

R

DUALPD PIN

R

SENSE

POWER RATING

1/4W

EE

PM

LTPoE 38.7W

–51V to –57V

4.64k

5.90k

7.87k

10.0k

LOW

HIGH

LOW

++

LTPoE 52.7W

1/2W

DUALPD (52.7W)

–51V to –57V

1/2W

++

LTPoE 70W

–54.75V to –57V

1/2W

++

LTPoE 90W

1W

DEVICE TYPE

ENDPOINT SWITCH

DATA SOURCE

MID PIN

LOW

PHY

MIDSPAN POWER INJECTOR

DATA IN RJ45

HIGH

4279fa

21

For more information www.linear.com/LTC4279

LTC4279

TYPICAL APPLICATIONS

UltraPWR Endpoint PSE

10Ω

0805

1µF

SMAJ70A

100V

12k

1/2W

X7R

C

BULK

V

EE

SML-012P8T

GREEN

100Ω

AGND

RESET

MID

LED

S1B

DUALPD

LEGACY

PWRMODE

LTC4279

0.22µF

100V

X7R

TVS

BULK

V

VSSK SENSE GATE

OUT

EE

R

GATE

200Ω

C

GD

47nF

100V

13.0k

R

GD

0.1Ω

2W

400Ω

V

EE

–51V to –65V

PSMN4R8-100BSE

7490220123

TR0+

T0C

75Ω

0.01µF, 200V

TR0–

POWER

and

DATA OUT

TR1+

T1C

75Ω

0.01µF, 200V

1

2

3

4

5

6

7

8

TR1–

DATA

TO

PHY

TR2+

T2C

RJ45

0.01µF, 200V

TR2–

TR3+

T3C

0.01µF, 200V

TR3–

1000pF

2kV

4279 TA05

4279fa

22

For more information www.linear.com/LTC4279

LTC4279

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC4279#packaging for the most recent package drawings.

S Package

16-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610 Rev G)

.386 – .394

(9.804 – 10.008)

.045 .005

NOTE 3

.050 BSC

16

N

15

14

13

12

11

10

9

N

1

.245

MIN

.160 .005

.150 – .157

(3.810 – 3.988)

NOTE 3

.228 – .244

(5.791 – 6.197)

2

3

N/2

8

.030 .005

TYP

RECOMMENDED SOLDER PAD LAYOUT

2

3

5

6

7

1

4

.010 – .020

(0.254 – 0.508)

× 45°

.053 – .069

(1.346 – 1.752)

.004 – .010

(0.101 – 0.254)

.008 – .010

(0.203 – 0.254)

0° – 8° TYP

.050

(1.270)

BSC

.014 – .019

(0.355 – 0.483)

TYP

.016 – .050

(0.406 – 1.270)

S16 REV G 0212

NOTE:

1. DIMENSIONS IN

INCHES

(MILLIMETERS)

2. DRAWING NOT TO SCALE

3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE

4279fa

23

For more information www.linear.com/LTC4279

LTC4279

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC4279#packaging for the most recent package drawings.

UFD Package

20-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1711 Rev B)

0.70 0.05

2.65 0.05

3.65 0.05

4.50 0.05

3.ꢀ0 0.05

ꢀ.50 REF

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

2.50 REF

4.ꢀ0 0.05

5.50 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN ꢀ NOTCH

R = 0.20 OR

C = 0.35

0.75 0.05

ꢀ.50 REF

ꢀ9

4.00 0.ꢀ0

(2 SIDES)

R = 0.05 TYP

20

0.40 0.ꢀ0

PIN ꢀ

TOP MARK

(NOTE 6)

ꢀ

2

5.00 0.ꢀ0

(2 SIDES)

2.50 REF

3.65 0.ꢀ0

2.65 0.ꢀ0

(UFD20) QFN 0506 REV B

0.25 0.05

0.50 BSC

0.200 REF

R = 0.ꢀꢀ5

TYP

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

4279fa

24

For more information www.linear.com/LTC4279

LTC4279

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

08/17 Changed minimum/maximum limits for t

Corrected transformer P/Ns.

, t

and t

.

ME

4

CLE1 CLE

21, 22

4279fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

25

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC4279

LTC4279

TYPICAL APPLICATION

IEEE 802.3at, Type 2, Endpoint PSE

749022017

SML-012P8T

GREEN

10Ω

0805

+

TR0

•

C

75Ω

12k

1/2W

BULK

TVS

BULK

T0C

•

–

TR0

+

TR1

•

DATA AND

1µF

100V

X7R

V

EE

•

75Ω

POWER OUT

SMAJ58A

T1C

•

1

–

TR1

DATA

TO

2

3

4

5

6

7

8

V

EE

100Ω

+

PHY

TR2

AGND

•

RESET

MID

RJ45

75Ω

T2C

–

TR2

DUALPD

LEGACY

LTC4279

LED

+

0.22µF

100V

X7R

TR3

PWRMODE

•

75Ω

T3C

V

VSSK SENSE GATE OUT

EE

–

TR3

200Ω

0.01µF

200V

×4

3.32k

V

EE

S1B

0.1Ω

–51V

to

1000pF

2kV

PSMN075-100MSE

–57V

4279 TA06

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LT4321

PoE Ideal Diode Bridge Controller

Replaces 8 Diodes with 8 N-Channel MOSFETs, Reduces Heat, Maximizes

Efficiency

LTC4257-1

LTC4263

LTC4265

IEEE 802.3af PD Interface Controller

Single IEEE 802.3af PSE Controller

IEEE 802.3at PD Interface Controller

100V, 400mA Internal Switch, Dual Current Limit, Programmable Class

Internal FET Switch

100V, 1A Internal Switch, 2-Event Classification Recognition

++

LTC4266/

LTC4266A/LTC4266C

Quad IEEE 802.3at/LTPoE /af PoE PSE Controller With Programmable CUT/LIM, PD Classification, and Port Current and Voltage

++

Monitoring. LTPoE Provides up to 90W

LTC4267-3

IEEE 802.3af PD Interface with Integrated

Switching Regulator

100V, 400mA Internal Switch, Programmable Class, 300kHz Constant

Frequency PWM

LTC4269-1

IEEE 802.3at PD Interface with Integrated

Switching Regulator

2-Event Classification, Programmable Classification, Synchronous No-Opto

Flyback Controller, 50kHz to 250kHz, Aux Support

LTC4269-2

IEEE 802.3at PD Interface with Integrated

Switching Regulator

2-Event Classification, Programmable Classification, Synchronous Forward

Controller, 100kHz to 500kHz, Aux Support

++

12-port PoE/PoE+/LTPoE PSE Controller

++

LTC4270/LTC4271

Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE PDs

++

LTC4274/LTC4274A/ Single IEEE 802.3at/LTPoE /af PoE PSE

With Programmable CUT/LIM, PD Classification, and Port Current and Voltage

Monitoring. LTPoE Provides up to 90W

++

LTC4274C

Controller

++

LT4275

PoE/PoE+/LTPoE PD Interface Controller

100V, External Low R MOSFET, and 1/2/3-Event Classification

DS(ON)

++

Recognition, Aux Support, LTPoE Provides up to 90W

++

LT4276A/LT4276B/

LT4276C

LTPoE /PoE+/PoE PD Interface Controller with

100V, External Low R MOSFET, Forward or Flyback Topology, Aux

DS(ON)

++

Support, LTPoE Provides up to 90W

Forward/Flyback Controller

++

LTC4290/LTC4271

LT4295

8-port PoE/PoE+/LTPoE PSE Controller

Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE PDs

IEEE 802.3bt PD with Forward/Flyback Switching

Regulator Controller

External Switch, IEEE 802.3bt Support, Configurable Class, Forward or

No-Opto Flyback Operation, Frequency, PG/SG Delays, Soft-Start, and Aux

Support as Low as 9V, Including Housekeeping Buck, Slope Compensation

4279fa

LT 0817 REV A • PRINTED IN USA

www.linear.com/LTC4279

26

 LINEAR TECHNOLOGY CORPORATION 2017

For more information www.linear.com/LTC4279


型号：	LTC4279IS#PBF
厂家：	Linear
描述：	LTC4279 - Single Port PoE/PoE+/ LTPoE++ PSE Controller; Package: SO; Pins: 16; Temperature Range: -40°C to 85°C
文件：	总26页 (文件大小：1136K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC4279IS#PBF [Linear]

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