LTC4280CUFD-TRPBF_技术文档

LTC4280

Hot Swap Controller with

2

I C Compatible Monitoring

FEATURES

DESCRIPTION

The LTC^®4280 Hot Swap™ controller allows a board to be

safely inserted and removed from a live backplane. Using

anexternalN-channelpasstransistor,boardsupplyvoltage

and inrush current are ramped up at an adjustable rate.

n

Allows Safe Insertion into Live Backplane

n

8-Bit ADC Monitors Current and Voltage

2

n

I C/SMBus Interface

n

Wide Operating Voltage Range: 2.9V to 15V

2

n

Adjustable Overcurrent Filter Time

An I C interface and onboard ADC allow for monitoring

n

High Side Drive for External N-Channel MOSFET

of load current, voltage and fault status.

n

No External Gate Capacitor Required

The device features adjustable analog foldback current

limit and a FILTER pin which conﬁgures the time spent in

overcurrent before declaring a fault. An I C interface may

conﬁgure the part to latch off or automatically restart after

the LTC4280 detects a current limit fault.

n

Input Overvoltage/Undervoltage Protection

n

Optional Latchoff or Auto-Retry After Faults

2

n

Alerts Host After Faults

Inrush Current Limit with Foldback

n

Available in 24-Pin 4mm × 5mm QFN Package

The controller has additional features to interrupt the host

when a fault has occurred, notify when output power is

good, detect insertion of a load card, and power-up either

APPLICATIONS

2

n

automatically upon insertion or wait for an I C command

Live Board Insertion

n

to turn on.

Electronic Circuit Breakers

Computers, Servers

n

Platform Management

L, LT, LTC, LTM, Linear Technology, the Linear logo and Hot Swap are registered trademarks of

Linear Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION

12V Application with 5A Circuit Breaker

Start-Up Waveform

0.005Ω

FDC653N

V

OUT

12V

V

+

DD

10V/DIV

C

L

34.8k

1.18k

30.1k

0.1μF

10Ω

CONTACT

BOUNCE

3.57k

INRUSH

CURRENT

2.5A/DIV

P6KE16A

3.4k

+

SENSE

–

UV

OV

SDAO

SDAI

SCL

V

SENSE GATE SOURCE

FB

DD

V

OUT

INTV

EN

ADIN

GPIO

CC

24k

10V/DIV

SDA

SCL

ALERT

LTC4280

V

GPIO

(POWERGOOD)

10V/DIV

ALERT

INTV

CC

INTV

CC

ON TIMER FILTER

GND

4280 TA02

C

L

= 12000μF

50ms/DIV

47nF

0.1μF

GND

4280 TA01

BACKPLANE PLUG-IN

CARD

4280f

1

LTC4280

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Notes 1, 2)

TOP VIEW

Supply Voltage (V ) .................................–0.3V to 24V

DD

Supply Voltage (INTV )...........................–0.3V to 6.5V

CC

24 23 22 21 20

Input Voltages

UV

OV

1

2

3

4

5

6

7

19

18

FB

GATE-SOURCE (Note 3)...........................–0.3V to 5V

GPIO

+

–

SENSE , SENSE ................ V – 0.3V to V + 0.3V

FILTER

GND

ON

17 INTV

CC

DD

25

16

15

14

13

TIMER

SOURCE....................................................–5V to 24V

EN, FB, ON, OV, UV ................................–0.3V to 12V

ADR0, ADR1, ADR2, TIMER,

ADIN

ADR2

ADR1

EN

SDAO

8

9

10 11 12

ADIN, FILTER .........................–0.3V to INTV + 0.3V

CC

ALERT SCL, SDA, SDAI, SDAO.............–0.3V to 6.5V

UFD PACKAGE

24-LEAD (4mm s 5mm) PLASTIC QFN

Output Voltages

GATE, GPIO............................................–0.3V to 24V

Operating Temperature Range

T

= 125°C, θ = 34°C/W

JA

JMAX

EXPOSED PAD (PIN 25) NOT GUARANTEED LOW IMPEDANCE TO GND,

ELECTRICAL CONNECTION OPTIONAL

LTC4280C ................................................ 0°C to 70°C

LTC4280I..............................................–40°C to 85°C

Storage Temperature Range

SSOP .................................................–65°C to 150°C

QFN....................................................–65°C to 125°C

Lead Temperature (Soldering, 10 sec)

SSOP ................................................................ 300°C

ORDER INFORMATION

LEAD FREE FINISH

LTC4280CUFD#PBF

LTC4280IUFD#PBF

LEAD BASED FINISH

LTC4280CUFD

TAPE AND REEL

PART MARKING*

4280

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC4280CUFD#TRPBF

LTC4280IUFD#TRPBF

TAPE AND REEL

0°C to 70°C

24-Lead (4mm × 5mm) Plastic QFN

PACKAGE DESCRIPTION

4280

–40°C to 85°C

TEMPERATURE RANGE

0°C to 70°C

PART MARKING*

4280

LTC4280CUFD#TR

LTC4280IUFD#TR

24-Lead (4mm × 5mm) Plastic QFN

LTC4280IUFD

4280

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

4280f

2

LTC4280

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_DD= 12V unless otherwise noted.

SYMBOL

Supplies

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Input Supply Range

2.9

15

16.5

5

V

DD

Input Supply Overvoltage Threshold

Input Supply Current

15.6

3

OV(VDD)

I

mA

V

DD

V

Input Supply Undervoltage Lockout

Input Supply Undervoltage Lockout Hysteresis

Internal Regulator Voltage

V

Rising

≥ 3.3V

2.75

75

2.84

100

3.1

2.64

55

2.89

125

3.4

2.79

75

DD(UVL)

DD

mV

V

DD(HYST)

INTV

2.9

2.55

20

CC

DD

INTV Undervoltage Lockout

INTV Rising

V

CC(UVL)

CC(HYST)

CC

INTV Undervoltage Lockout Hysteresis

mV

CC

Current Limit and Circuit Breaker

l

Circuit Breaker Threshold (V – V

)

22.5

25

27.5

mV

Δ

V

DD

SENSE

SENSE(TH)

SENSE

l

Current Limit Voltage (V – V

)

V

= 1.3V

= 0V

22.5

7

26

10

29.5

13.5

mV

Δ

DD

SENSE

FB

l

I

V = 12V

SENSE

10

20

35

μA

SENSE +/– Input Current

SENSE(IN)

Gate Drive

l

External N-Channel Gate Drive (V

(Note 3)

– V

)

V

= 2.9V to 15V

DD

4.7

5.9

6.5

V

ΔV

GATE

SOURCE

GATE

l

I

External N-Channel Gate Pull-Up Current

Gate On, V

Gate Off, V

= 0V

–15

0.8

–20

1

–30

1.6

μA

mA

GATE(UP)

GATE

External N-Channel Gate Pulldown Current

= 15V

GATE(DN)SLOW

GATE(DN)FAST

GATE

Pulldown Current From GATE to SOURCE

During OC/UVLO

V

DD

– SENSE = 100mV, V = 4V

300

450

700

GS

l

t

(V – SENSE) High to GATE Low

V

– SENSE = 100mV, C = 10nF

0.5

4.3

1

μs

V

PHL(SENSE)

DD

GS

V

Gate-Source Voltage for Power Bad Fault

= 2.9V – 15V

3.8

4.7

GS(POWERBAD)

SOURCE

Comparator Inputs

l

V

ON Pin Threshold Voltage

ON Pin Hysteresis

V

Rising

1.210

60

1.235

128

0

1.26

180

±1

V

mV

μA

V

ON(TH)

ON

Δ

V

ON(HYST)

I

ON Pin Input Current

V

= 1.2V

ON(IN)

ON

V

EN Input Threshold

= Rising

1.215

50

1.235

128

0

1.255

200

±1

EN(TH)

EN

EN Hysteresis

mV

μA

V

Δ

V

EN(HYST)

I

EN

EN Pin Input Current

EN = 3.5V

V

OV Pin Threshold Voltage

OV Pin Hysteresis

V

OV

Rising

1.215

10

1.235

30

1.255

40

OV(TH)

mV

μA

V

Δ

V

OV(HYST)

I

OV Pin Input Current

V

= 1.8V

Rising

0

±1

OV(IN)

OV

V

UV Pin Threshold Voltage

UV Pin Hysteresis

1.215

60

1.235

80

1.255

100

±1

UV(TH)

UV

mV

μA

V

Δ

V

UV(HYST)

I

UV Pin Input Current

V

= 1.8V

Falling

0

UV(IN)

UV

V

UV Pin Reset Threshold Voltage

UV Pin Reset Threshold Hysteresis

Foldback Pin Power Good Threshold

FB Pin Power Good Hysteresis

Foldback Pin Input Current

GPIO Pin Input Threshold

0.33

60

0.4

125

1.235

8

0.47

210

1.255

15

UV(RTH)

UV

mV

V

Δ

V

UV(RHYST)

V

FB

FB Rising

1.215

3

mV

μA

Δ

V

FB(HYST)

I

FB

FB = 1.8V

0

±1

V

GPIO

Rising

0.8

1

1.2

V

GPIO(TH)

4280f

3

LTC4280

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_DD= 12V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Other Pin Functions

l

V

I

GPIO Pin Output Low Voltage

GPIO Pin Input Leakage Current

SOURCE Pin Input Current

I

= 5mA

= 15V

0.25

0

0.5

±1

120

5

V

μA

μs

GPIO(OL)

GPIO

V

GPIO(OH)

SOURCE

P(GATE)

GPIO

I

t

SOURCE = 15V

40

80

3

Input (ON, OV, UV, EN) to GATE Off

Propagation Delay

l

t

Turn-On Delay

ON

1

100

5

2

150

75

μs

ms

s

D(GATE)

UV, OV, EN

50

2.5

Overcurrent Auto-Retry

l

V

Timer Low Threshold

0.17

1.2

–80

1.4

40

0.2

1.235

–100

2

0.23

1.26

–120

2.6

V

TIMERL(TH)

V

Timer High Threshold

TIMERH(TH)

I

TIMER Pin Pull-Up Current

TIMER Pin Pulldown Current for OC Auto-Retry

TIMER Current Up/Down Ratio

FILTER High Threshold

μA

TIMER(UP)

TIMER(DOWN)

TIMER(UP/DOWN)

50

60

V

1.2

–7.5

1

1.235

–10

2

1.27

–12.5

3.5

V

μA

FILTER(TH)

FILTER

I

FILTER Timer Current

During OC FILTER = 0.5V

After OC FILTER = 0.5V

μA

During Startup FILTER = 0.5V

.03

0.6

1.2

mA

ADC

RES

INL

l

Resolution (No Missing Codes)

Integral Nonlinearity

8

Bits

l

V

– SENSE (Note 5)

–2

–1.25

0.5

0.2

2

1.25

LSB

DD

SOURCE

ADIN

l

V

Offset Error (Note 4)

Total Unadjusted Error

Full-Scale Error

V

– SENSE

LSB

±2.0

±1.0

OS

DD

SOURCE

ADIN

l

TUE

FSE

V

– SENSE

LSB

±5.5

±5.0

DD

SOURCE

ADIN

l

V

– SENSE

LSB

±5.5

±5.0

DD

SOURCE

ADIN

l

V

FS

Full-Scale Voltage (255 • V

)

LSB

V – SENSE

DD

SOURCE

ADIN

37.625

15.14

1.205

38.45

15.44

1.23

39.275

15.74

1.255

mV

V

l

R

I

ADIN Pin Sampling Resistance

ADIN Pin Input Current

Conversion Rate

V

= 1.28V

1

2

0

MΩ

μA

ADIN

V

ADIN

= 1.28V

±0.1

ADIN

10

Hz

4280f

4

LTC4280

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_DD= 12V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

2

I C Interface

l

V

ADR0, ADR1, ADR2 Input High Voltage

ADR0, ADR1, ADR2 Hi-Z Input Current

INTV

CC

V

ADR(H)

CC

–0.8

–0.4

–0.2

l

I

ADR0, ADR1, ADR2 = 0.8V

–3

μA

ADR(IN,Z)

ADR0, ADR1, ADR2 = INTV – 0.8V

3

CC

l

V

ADR0, ADR1, ADR2 Input Low Voltage

ADR0, ADR1, ADR2 Input Current

ALERT Input Current

0.2

–80

0.4

0.8

80

1

V

μA

V

ADR(L)

I

ADR0, ADR1, ADR2 = 0V, INTV

ADR(IN)

CC

ALERT = 6.5V

ALERT

V

ALERT Output Low Voltage

SDA, SCL Input Threshold

SDA, SCL Input Current

I

= 3mA

0.2

1.7

0.4

1.9

1

ALERT(OL)

SDA,SCL(TH)

SDA,SCL(OH)

ALERT

1.3

V

I

SCL, SDA = 6.5V

= 3mA

μA

V

SDA Output Low Voltage

I

0.2

0.4

SDA(OL)

SDA

2

I C Interface Timing

l

f

t

SCL Clock Frequency

Operates with f

≤ f

SCL(MAX)

400

1000

0.12

30

kHz

μs

ns

pF

SCL(MAX)

BUF(MIN)

SCL

Bus Free Time Between Stop/Start Condition

Hold Time After (Repeated) Start Condition

Repeated Start Condition Set-Up Time

Stop Condition Set-Up Time

Data Hold Time (Input)

1.3

600

100

900

600

250

10

HD,STA(MIN)

SU,STA(MIN)

SU,STO(MIN)

HD,DAT(MIN)

HD,DATO

30

140

30

Data Hold Time (Output)

300

50

500

30

Data Set-Up Time

SU,DAT(MIN)

SP

Suppressed Spike Pulse Width

SCL, SDA Input Capacitance

110

C

SDAI Tied to SDAO (Note 6)

X

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive; all voltages are referenced to

GND unless otherwise speciﬁed.

Note 4: Offset error is the offset voltage measured from 1LSB when the

output code ﬂickers between 0000 0000 and 0000 0001.

Note 5: Integral nonlinearity is deﬁned as the deviation of a code from a

precise analog input voltage. Maximum speciﬁcations are limited by the

LSB step size and the single shot measurement. Typical speciﬁcations are

measured from the 1/4, 1/2 and 3/4 areas of the quantization band.

Note 3: An internal clamp limits the GATE pin to a minimum of 5V above

Note 6: Guaranteed by design and not subject to test.

SOURCE. Driving this pin to voltages beyond the clamp may damage the device.

4280f

5

LTC4280

T_A= 25°C, V_DD= 12V unless otherwise noted

TYPICAL PERFORMANCE CHARACTERISTICS

I_DDvs V_DD

INTV_CCvs V_DD

INTV_CCvs I_LOAD

4.0

3.5

3.0

2.5

4

3

2

1

0

4

V

= 12V, 5V

DD

3

2

1

0

V

= 3.3V

DD

0

6

(mA)

8

10

0

5

10

V

15

(V)

20

25

2.5

3.0

3.5

4.0

2

4

I

INTV (V)

DD

LOAD

CC

4280 G01

4280 G03

4280 G02

V_TH(UV)vs Temperature

V_HYST(UV)vs Temperature

I_TIMERvs Temperature

1.240

1.238

1.236

1.234

1.232

1.230

90

85

80

75

70

110

105

100

95

90

–50

–25

0

25

50

75

100

–50 –25

0

25

50

100

–50

–25

0

25

50

75

100

75

TEMPERATURE (°C)

4280 G04

4280 G05

4280 G06

T_PHL(GATE)vs Sense Voltage

Current Limit vs V_FB

V_THCircuit Breaker vs Temperature

27

26

25

24

23

22

100

10

1

30

25

V

= 5V, 12V

DD

20

15

10

5

V

= 3.3V

DD

0

0.1

0.6 0.8 1.0

(V)

0

0.2 0.4

1.2 1.4

–50

–25

0

25

50

75

100

0

25

50

75

– V

100

125

150

V

TEMPERATURE (°C)

V

(SENSE+)

(mV)

FB

(SENSE–)

4280 G09

4280 G07

4280 G08

4280f

6

LTC4280

T_A= 25°C, V_DD= 12V unless otherwise noted

TYPICAL PERFORMANCE CHARACTERISTICS

ΔV_GATEvs Temperature

ΔV_GATEvs I_GATE

I_GATEPull-Up vs Temperature

6.1

6.0

–30

–25

–20

–15

–10

7

6

V

= 5V

DD

V

= 5V

DD

V

= 12V

DD

5

4

3

2

1

0

5.9

V

= 12V

DD

5.8

5.7

5.6

5.5

V

= 3.3V

DD

V

= 3.3V

DD

5.4

–25

0

25

50

100

5

10

15

(μA)

25

–50

75

0

20

–50

0

25

50

75

100

–25

TEMPERATURE (°C)

I

GATE

4280 G10

4280 G11

4280 G12

Total Unadjusted Error

vs Code (ADIN)

V_OL(GPIO)vs I_GPIO

ADC INL vs Code (ADIN)

0.006

0.005

0.004

0.003

0.002

0.001

0

0.5

0.4

0.6

0.5

0.3

0.2

0.4

0.3

0.1

V

= 3.3V, 5V, 12V

DD

0

–0.1

–0.2

–0.3

–0.4

–0.5

0.2

0.1

0

64

128

192

256

0

64

256

0

2

4

6

8

10

128

192

CODE

I

(mA)

4280 G14

4280 G15

GPIO1

4280 G13

ADC Full-Scale Error

vs Temperature

ADC DNL vs Code (ADIN)

1.0

0.8

0.5

0.4

0.3

0.2

0.1

0

0.6

0.4

0.2

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.2

–0.4

–0.6

–0.8

–1.0

0

64

256

50

100

128

192

–50

–25

0

25

75

CODE

TEMPERATURE (°C)

4280 G16

4280 G17

4280f

7

LTC4280

PIN FUNCTIONS

ADIN: ADC Input. A voltage between 0V and 1.235V

applied to this pin is measured by the onboard ADC. Tie

to ground if unused.

GATE: Gate Drive for External N-Channel MOSFET. An

internal 20μA current source charges the gate of the

MOSFET. Often no compensation capacitor is required

on the GATE pin, but a resistor and capacitor network

from this pin to ground may be used to set the turn-on

output voltage slew rate. See Applications Information.

During turn-off there is a 1mA pulldown current. During

ADR0, ADR1, ADR2: Serial Bus Address Inputs. Tying

these pins to ground, to the INTV pin or open conﬁgures

CC

one of 27 possible addresses. See Table 1 in Applications

Information.

a short-circuit or undervoltage lockout (V or INTV ),

DD

CC

ALERT: Fault Alert Output. Open-drain logic output that

is pulled to ground when a fault occurs to alert the host

controller. A fault alert is enabled by the ALERT register.

See Applications Information. Tie to ground if unused.

a 450mA pulldown current source between GATE and

SOURCE is activated.

GND: Device Ground.

GPIO: General Purpose Input/Output. Open-drain logic

output or logic input. Defaults to an output set to pull

low to indicate power is not good. Conﬁgure according

to Table 2 and 3.

EN: Enable Input. Ground this pin to indicate a board is

presentandenabletheN-channelMOSFETtoturnon.When

this pin is high, the MOSFET is not allowed to turn on. An

internal 10μA current source pulls up this pin. Transitions

on this pin are recorded in the Fault register. A high-to-low

transition activates the logic to read the state of the ON pin

and clear Faults. See Applications Information.

INTV : Low Voltage Supply Decoupling Output. Connect

CC

a 0.1μF capacitor from this pin to ground.

ON: On Control Input. A rising edge turns on the external

N-channel MOSFET and a falling edge turns it off. This pin

also conﬁgures the state of the FET On bit in the control

register (and hence the external MOSFET) at power up.

For example, if the ON pin is tied high, then the FET On bit

(A3 in Table 2) goes high 100ms after power-up. Likewise

if the ON pin is tied low then the part remains off after

EXPOSED PAD (Pin 25): Exposed pad may be left open

or connected to device ground.

FB: Foldback Current Limit and Power Good Input. A

resistive divider from the output is tied to this pin. When

the voltage at this pin drops below 1.235V, power is not

consideredgood.Thepowerbadconditionmayresultinthe

GPIO pin pulling low or going high impedance depending

on the conﬁguration of control register bits A6 and A7.

Also a power bad fault is logged in this condition if the

LTC4280 has ﬁnished the start-up cycle and the GATE pin

is high. See Applications Information. The current limit

folds back from a 26mV sense voltage to 10mV as the

FB pin voltage falls from 0.6V to 0V.

2

power-up until the FET On bit is set high using the I C

bus. A high-to-low transition on this pin clears the fault

register.

OV: Overvoltage Comparator Input. Connect this pin to an

external resistive divider from V . If the voltage at this

DD

pin rises above 1.235V, an overvoltage fault is detected

and the GATE turns off. Tie to GND if unused.

FILTER:FaultFilterInput.Connectacapacitorbetweenthis

pin and ground to set a 123ms/μF delay for overcurrent

fault ﬁltering after startup.

4280f

8

LTC4280

PIN FUNCTIONS

SCL: Serial Bus Clock Input. Data at the SDA pin is shifted

in or out on rising edges of SCL. This is a high impedance

pin that is generally driven by an open-collector output

from a master controller. An external pull-up resistor or

current source is required.

SOURCE: N-Channel MOSFET Source and ADC Input.

Connect this pin to the source of the external N-channel

MOSFETswitchforgatedrivereturn.Thispinalsoservesas

the ADC input to monitor output voltage. The pin provides

a return for the gate pulldown circuit.

SDAO: Serial Bus Data Output. Open-drain output for

sendingdatabacktothemastercontrolleroracknowledging

a write operation. Normally tied to SDAI to form the SDA

line. An external pull-up resistor or current source is

required.

TIMER: Start-Up Timer Input. Connect a capacitor

between this pin and ground to set a 12.3ms/μF duration

for start-up, after which an overcurrent fault is logged if

the inrush is still current limited. The duration of the off

time is 600ms/μF when overcurrent auto-retry is enabled,

resulting in a 1:50 duty cycle. An internal timer provides

a 100ms start-up time and 5 seconds auto-retry time if

SDAI: Serial Bus Data Input. A high impedance input for

shifting in address, command or data bits. Normally tied

to SDAO to form the SDA line.

this pin is tied to INTV .

CC

UV: Undervoltage Comparator Input. Connect this pin

+

SENSE : Positive Current Sense Input. Connect this pin to

to an external resistive divider from V . If the voltage

DD

the input of the current sense resistor. Must be connected

to the same trace as V .

at this pin falls below 1.155V, an undervoltage fault is

detected and the GATE turns off. Pulling this pin below

0.4V resets all faults and allows the GATE to turn back on.

DD

–

SENSE :NegativeCurrentSenseInput.Connectthispinto

the output of the current sense resistor. This pin provides

sense voltage feedback and monitoring for the current

limit, circuit breaker and ADC.

Tie to INTV if unused.

CC

V : Supply Voltage Input. This pin has an undervoltage

DD

lockout threshold of 2.84V and overvoltage lockout

threshold of 15.6V.

4280f

9

LTC4280

FUNCTIONAL DIAGRAM

–

+

SENSE

GATE

–

+

CB

CS

CHARGE

PUMP AND

GATE DRIVER

+

– –

FOLDBACK

SOURCE

1.235V

0.6V

+

–

FB

26mV

FAULT

25mV

FET ON

UV

RST

OV1

EN

+

–

1.235V

0.4V

UV

PG

UV

+

–

10μA

PWRGD

FILTER

1.235V

+

–

RESET

OV

1.235V

2μA

FAULT

OV

GP

+

–

GPI0

+

–

INTV

CC

LOGIC

1.235V

10μA

1.235V

1V

+

–

EN

TM1

TM2

ON

0.2V

+

–

ON

+

–

ON

100μA

2μA

1.235V

2.84V

TIMER

UVLO1

V

+

–

+

–

DD(UVLO)

OV2

3.1V

GEN

V

DD

1.235V

INTV

UVLO2

CC

+

–

OV2

+

–

2.64V

A/D

15.6V

CONVERTER

ADIN

8

SOURCE

–

SDAI

SDAO

SCL

+

SENSE - SENSE

2

I C

I C ADDR

5

ADRO

ADR1

ADR2

1 OF 27

ALERT

4280 BD

4280f

10

LTC4280

TIMING DIAGRAM

SDAI/SDAO

t

SP

t

SU,STA

t

SU, DAT

t

BUF

HD, DATO,

HD, DATI

t

HD, STA

t

SU, STO

t

SP

4280 TD01

SCL

t

HD, STA

START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

START

CONDITION

4280f

11

LTC4280

OPERATION

The LTC4280 is designed to turn a board’s supply voltage

on and off in a controlled manner, allowing the board to be

safely inserted or removed from a live backplane. During

normal operation, the charge pump and gate driver turn

on an external N-channel MOSFET’s gate to pass power to

the load. The gate driver uses a charge pump that derives

The output voltage is monitored using the FB pin and the

Power Good (PG) comparator to determine if the power

is available for the load. The power good condition can be

signaled by the GPIO pin using an open-drain pulldown

transistor. The GPIO pin may also be conﬁgured to signal

powerbad,orasageneralpurposeinput(GPcomparator),

or a general purpose open drain output.

its power from the V pin. Also included in the gate driver

DD

is an internal 6.5V gate-to-source clamp. During start-up

the inrush current is tightly controlled by using current

limit foldback and output dV/dt limiting.

The Functional Diagram shows the monitoring blocks of

the LTC4280. The group of comparators on the left side

includes the undervoltage (UV), overvoltage (OV), reset

(RST),enable(EN)andsignalon(ON)comparators.These

comparators determine if the external conditions are valid

priortoturningontheGATE.Butﬁrstthetwoundervoltage

lockout circuits, UVLO1 and UVLO2, validate the input

The current sense (CS) ampliﬁer monitors the load

+

current using the difference between the SENSE and

–

SENSE pin voltages. The CS ampliﬁer limits the current

in the load by pulling back on the gate-to-source voltage

in an active control loop when the sense voltage exceeds

the commanded value. The CS ampliﬁer requires 20μA

supply and the internally generated 3.1V supply, INTV .

CC

UVLO2 also generates the power-up initialization to the

+

input bias current from both the SENSE and the

logiccircuitsasINTV crossesthisrisingthreshold.Ifthe

CC

–

SENSE pins.

ﬁxed internal overvoltage comparator, OV2, detects that

V

is greater than 15.6V, the part immediately generates

DD

A short-circuit on the output to ground results in exces-

sive power dissipation during active current limiting. To

limit this power, the CS ampliﬁer regulates the voltage

an overvoltage fault and turns the GATE off.

Included in the LTC4280 is an 8-bit A/D converter. The

converter has a 3-input multiplexer to select between the

+

–

between the SENSE and SENSE pins at 26mV with

foldback to 10mV.

+

–

ADIN pin, the SOURCE pin and the SENSE – SENSE

voltage.

If an overcurrent condition persists, the internal circuit

breaker (CB) registers a fault when either the sense

voltage exceeds 25mV or the current sense ampliﬁer

is in regulation for more than the time limit set by the

capacitor on the FILTER pin. This indicates to the logic

that it is time to turn off the GATE to prevent overheating.

At this point the start-up TIMER pin voltage ramps down

usingthe2μAcurrentsourceuntilthevoltagedropsbelow

0.2V (comparator TM1) which tells the logic that the pass

transistor has cooled and it is safe to turn it on again if

overcurrent auto-retry is enabled. If the TIMER pin is tied

2

An I C interface is provided to read the A/D registers. It

also allows the host to poll the device and determine if

faults have occurred. If the ALERT line is conﬁgured as an

interrupt, the host is enabled to respond to faults in real

time. The typical SDA line is divided into an SDAI (input)

and SDAO (output). This simpliﬁes applications using an

optoisolator driven directly from the SDAO output. An

application which uses optoisolation is shown on the back

2

cover. The I C device address is decoded using the ADR0,

ADR1 and ADR2 pins. These inputs have three states each

that decode into a total of 27 device addresses.

to INTV , the cool-down time defaults to 5 seconds on

CC

an internal system timer in the logic.

4280f

12

LTC4280

APPLICATIONS INFORMATION

AtypicalLTC4280applicationisinahighavailabilitysystem

in which a positive voltage supply is distributed to power

individual cards. The device measures card voltages and

currents and records past and present fault conditions.

internally generated supply, INTV , must cross its 2.64V

CC

undervoltage threshold. This generates a 60μs to 120μs

power-on-reset pulse. During reset the fault registers are

cleared and the control registers are set or cleared as

described in the register section.

2

ThesystemquerieseachLTC4280overtheI Cperiodically

and reads status and measurement information.

After a power-on-reset pulse, the LTC4280 goes through

the following turn-on sequence. First the UV and OV pins

indicate that input power is within the acceptable range,

which is indicated by bits C0-C1 in Table 4. Second, the EN

pin is externally pulled low. Finally, all of these conditions

must be satisﬁed for the duration of 100ms to ensure that

any contact bounce during insertion has ended.

A basic LTC4280 application circuit is shown in Figure 1.

The following sections cover turn-on, turn-off and various

faults that the LTC4280 detects and acts upon. External

component selection is discussed in detail in the Design

Example section.

Turn-On Sequence

When these initial conditions are satisﬁed, the ON pin is

checked and it’s state written to bit A3 in Table 2. If it is

high, the external MOSFET is turned on. If the ON pin is

low, the external MOSFET is turned on when the ON pin is

brought high or if a serial bus turn-on command is sent

by setting bit A3.

The power supply on a board is controlled by using

an external N-channel pass transistor (Q1) placed in

the power path. Note that resistor R provides current

S

detection.ResistorsR1,R2andR3deﬁneundervoltageand

overvoltagelevels.R5preventshighfrequencyoscillations

in Q1 and R6 and C1 form an optional network that may

be used to provide an output dV/dt limited start-up.

The MOSFET is turned on by charging up the GATE with

a 20μA current source. When the GATE voltage reaches

the MOSFET threshold voltage, the MOSFET begins to

turn on and the SOURCE voltage then follows the GATE

voltage as it increases.

Several conditions must be present before the external

MOSFET turns on. First the external supply, V , must

DD

exceed its 2.84V undervoltage lockout level. Next the

RS

0.005ꢀ

Q1

FDC653N

V

OUT

12V

R7

30.1k

1%

R8

3.57k

1%

+

R1

Z1

C

L

34.8k

P6KE16A

1%

R5

R6

330μF

10ꢀ

15k

C

F

R2

1.18k

1%

C1

6.8nF

0.1μF

R4

100k

+

–

UV V SENSE

OV

ON

SDAI

SDA0

SCL

SENSE GATE

SOURCE

FB

R3

3.4K

1%

DD

ADIN

GPIO

EN

LTC4280

SDA

SCL

ALERT

FILTER

ALERT

C

F

TIMER INTV

ADR0 ADR1 ADR2 GND

CC

47nF

C

C3

0.1μF

TIMER

4280 F01

0.68μF

GND

BACKPLANE PLUG-IN

CARD

Figure 1. Typical Application

4280f

13

LTC4280

APPLICATIONS INFORMATION

WhentheMOSFETisturningon,theinrushcurrentfollows

the foldback proﬁle as shown in Figure 2. Meanwhile the

FILTER pin is held low with 0.6mA to prevent the FILTER

pin from generating an overcurrent fault during start-up.

The TIMER pin integrates at 100μA during start-up and

once it reaches its threshold of 1.235V, the part checks

to see if it is in current limit, which indicates that it has

started up into a short-circuit condition. If this is the case,

the overcurrent fault bit, D2 in Table 5, is set and the part

turns off. If the part is not in current limit, the FILTER pin

isreleasedtoenablecircuitbreakerandcurrentlimitbased

overcurrent faults. Alternately an internal 100ms start-up

a 20μA pull-up current from the gate pin slews the gate

upwards and the part is not in current limit. The start-up

TIMER may expire in this condition and an OC fault is not

generated even though start-up has not completed. Either

the sense voltage increases to the 25mV CB threshold or

the current limit as set by the FB pin which generates an

OCfaultwhentheFILTERpinreachesits1.235Vthreshold,

or the FB pin voltage crosses its 1.235V power good

threshold and the GPIO pin signals power good.

GATE Pin Voltage

A curve of gate-to-source drive vs V is shown in the

DD

timer may be selected by tying the TIMER pin to INTV .

CC

Typical Performance Characteristics. At minimum input

supply voltage of 2.9V, the minimum gate-to-source drive

voltage is 4.7V. The gate-to-source voltage is clamped

below 6.5V to protect the gates of logic level N-channel

MOSFETs.

V

+ 6V

V

DD

GATE

V

DD

OUT

Turn-Off Sequence

GPIO1

(POWER GOOD)

The GATE is turned off by a variety of conditions. A normal

turn-off is initiated by the ON pin going low or a serial bus

turn-off command. Additionally, several fault conditions

turn off the GATE. These include an input overvoltage

(OV pin), input undervoltage (UV pin), overcurrent circuit

t

V

STARTUP

SENSE

25mV

–

breaker (SENSE pin), or EN transitioning high. Writing

10mV

a logic one into the UV, OV or OC fault bits (D0-D2 in

Table 5) also latches off the GATE if their auto-retry bits

are set to false.

I

• R

SENSE

LOAD

4280 F02

FB

LIMITED

TIMER

EXPIRES

Normally the MOSFET is turned off with a 1mA current

pulling down the GATE pin to ground. With the MOSFET

Figure 2. Power-Up Waveforms

turned off, the SOURCE and FB voltages drop as C

L

As the SOURCE voltage rises, the FB pin follows as set

by R7 and R8. Once FB crosses its 1.235V threshold, and

the start-up timer has expired, the GPIO pin, in its default

conﬁguration, ceases to pull low and indicates that power

is now good.

discharges. When the FB voltage crosses below its

threshold, GPIOpullslowtoindicatethattheoutputpower

is no longer good.

If the V pin falls below 2.74V for greater than 2μs or

DD

INTV drops below 2.60V for greater than 1μs, a fast shut

CC

If R6 and C1 are employed for a constant current during

start-up, which produces a constant dV/dt at the output,

down of the MOSFET is initiated. The GATE pin is pulled

down with a 450mA current to the SOURCE pin.

4280f

14

LTC4280

APPLICATIONS INFORMATION

Overcurrent Fault

it to INTV , the part is allowed to turn on again after an

CC

internal 5 second timer has expired, in the same manner

The LTC4280 features an adjustable current limit that

protects against short-circuits or excessive load current

until an overcurrent fault is generated. An overcurrent

faultcanoccurintwodifferentmanners.First,attheendof

start-up when the TIMER pin reaches its 1.235V threshold

or the internal 100ms start-up timer expires, if the part is

in current limit an overcurrent fault is generated. Second,

afterstart-uptheFILTERpinrampsupwith10μAifthesense

voltage exceeds the 25mV circuit breaker threshold or the

current limit circuit regulates the sense voltage. When the

FILTER pin passes its 1.235V threshold the overcurrent

present bit C2 is set and an overcurrent fault is generated.

In both cases the external MOSFET is turned off and the

overcurrent fault bit is set.

as the TIMER pin passing its 0.2V threshold.

Overvoltage Fault

An overvoltage fault occurs when either the OV pin rises

above its 1.235V threshold, or the V pin rises above its

DD

15.6Vthreshold,formorethan2μs.ThisshutsofftheGATE

with a 1mA current to ground and sets the overvoltage

present bit C0 and the overvoltage fault bit D0. If the pin

subsequently falls back below the threshold for 100ms,

the GATE is allowed to turn on again unless overvoltage

auto-retry has been disabled by clearing bit A0.

Undervoltage Fault

An undervoltage fault occurs when the UV pin falls below

its 1.235V threshold for more than 2μs. This turns off the

GATE with a 1mA current to ground and sets undervoltage

present bit C1 and undervoltage fault bit D1. If the UV pin

subsequently rises above the threshold for 100ms, the

GATEisturnedonagainunlessundervoltageauto-retryhas

been disabled by clearing bit A1. When power is applied

to the device, if UV is below its 1.235V threshold after

V

GATE

10V/DIV

V

SOURCE

10V/DIV

V

DD

10V/DIV

I

LOAD

10A/DIV

INTV crosses its 2.64V undervoltage lockout threshold,

CC

an undervoltage fault is logged in the fault register.

4280 F03

R

= 5mꢀ

= 0

SHORT

5μs/DIV

S

L

C

R

= 1ꢀ

Board Present Change of State

R6 = 30k

C1 = 0.1μF

Whenever the EN pin toggles, bit D4 is set to indicate a

change of state. When the EN pin goes high, indicating

boardremoval,theGATEturnsoffimmediately(witha1mA

current to ground) and clears the board present bit, C4. If

the EN pin is pulled low, indicating a board insertion, all

fault bits except D4 are cleared and enable bit, C4, is set.

If the EN pin remains low for 100ms the state of the ON

pin is captured in ‘FET On’ control bit A3. This turns the

switch on if the ON pin is tied high. There is an internal

10μA pull-up current source on the EN pin.

Figure 3. Short-Circuit Waveforms

After the MOSFET is turned off, the TIMER and FILTER

capacitorsbeginsdischargingwith2μApulldowncurrents.

WhentheTIMERpinreachesits0.2VthresholdtheMOSFET

is allowed to turn on again if the overcurrent fault has been

cleared. However, if the overcurrent auto-retry bit, A2 has

been set then the MOSFET turns on again automatically

without resetting the overcurrent fault. Use a minimum

value of 10nF for C . If the TIMER pin is bypassed by tying

T

4280f

15

LTC4280

APPLICATIONS INFORMATION

If the system shuts down due to a fault, it may be desirable

to restart the system simply by removing and reinserting

a load card. In cases where the LTC4280 and the switch

reside on a backplane or midplane and the load resides on

a plug-in card, the EN pin detects when the plug-in card is

removed. Figure 4 shows an example where the EN pin is

usedtodetectinsertion.Oncetheplug-incardisreinserted

the fault register is cleared (except for D4). After 100ms

the state of the ON pin is latched into bit A3 of the control

register. At this point the system starts up again.

Power Bad Fault

A power bad fault is reported if the FB pin voltage drops

below its 1.235V threshold for more than 2μs when the

GATE is high. This pulls the GPIO pin low immediately

when conﬁgured as power-good, and sets power-bad

present bit, C3, and power bad fault bit D3. A circuit

prevents power-bad faults if the gate-to-source voltage is

low, eliminating false power-bad faults during power-up

or power-down. If the FB pin voltage subsequently rises

back above the threshold, the GPIO pin returns to a high

impedance state and bit C3 is reset.

If a connection sense on the plug-in card is driving the EN

pin, insertion or removal of the card may cause the pin

voltagetobounce. Thisresultsinclearingthefaultregister

when the card is removed. The pin may be debounced

Fault Alerts

When any of the fault bits in FAULT register D are set, an

optional bus alert is generated if the appropriate bit in the

ALERT register B has been set. This allows only selected

faults to generate alerts. At power-up the default state is to

not alert on faults. If an alert is enabled, the corresponding

faultcausestheALERTpintopulllow. Afterthebusmaster

controller broadcasts the Alert Response Address, the

LTC4280 responds with its address on the SDA line and

releases ALERT as shown in Table 6. If there is a collision

between two LTC4215s responding with their addresses

simultaneously, then the device with the lower address

wins arbitration and responds ﬁrst. The ALERT line is also

released if the device is addressed by the bus master.

using a ﬁlter capacitor, C , on the ENpin as shown in

EN

Figure 4. The ﬁlter time is given by:

t

= C • 123 [ms/μF]

FILTER

EN

OUT

LTC4280

SOURCE

10μA

EN

+

LOAD

C

EN

1.235V

–

GND

Once the ALERT signal has been released for one fault, it

is not pulled low again until the FAULT register indicates a

different fault has occurred or the original fault is cleared

and it occurs again. Note that this means repeated or

continuingfaultsdonotgeneratealertsuntiltheassociated

FAULT register bit has been cleared.

4280 F04

CONNECTOR

PLUG-IN

CARD

MOTHERBOARD

Figure 4. Plug-In Card Insertion/Removal

FET Short Fault

Resetting Faults

AFETshortfaultisreportedifthedataconvertermeasures

a current sense voltage greater than or equal to 1.6mV

while the GATE is turned off. This condition sets FET short

present bit, C5, and FET short fault bit D5.

Faults are reset with any of the following conditions. First,

a serial bus command writing zeros to the FAULT register

D clears the associated faults. Second, the entire FAULT

register is cleared when the switch is turned off by the ON

4280f

16

LTC4280

APPLICATIONS INFORMATION

pinorbitA3goingfromhightolow, iftheUVpinisbrought

Conﬁguring the GPIO Pin

below its 0.4V reset threshold for 2μs, or if INTV falls

CC

Table 2 describes the possible states of the GPIO pin using

thecontrolregisterbitsA6andA7.Atpower-up,thedefault

stateisfortheGPIOpintogohighimpedancewhenpower

is good (FB pin greater than 1.235V). Other applications

for the GPIO pin are to pull down when power is good, a

general purpose output and a general purpose input.

below its 2.64V undervoltage lockout threshold. Finally,

when EN is brought from high to low, only FAULT bits

D0-D3 are cleared, and bit D4, that indicates a EN change

of state, is set. Note that faults that are still present, as

indicated in STATUS Register C, cannot be cleared.

The FAULT register is not cleared when auto-retrying.

When auto-retry is disabled the existence of a D0, D1

or D2 fault keeps the switch off. As soon as the fault is

cleared, the switch turns on. If auto-retry is enabled, then

a high value in C0, C1 or C2 holds the switch off and the

fault register is ignored. Subsequently, when bits C0, C1

and C2 are cleared by removal of the fault condition, the

switch is allowed to turn on again.

Current Limit Stability

For many applications the LTC4280 current limit will be

stable without additional components. However there

are certain conditions where additional components

may be needed to improve stability. The dominant pole

of the current limit circuit is set by the capacitance and

resistance at the gate of the external MOSFET, and larger

gatecapacitancemakesthecurrentlimitloopmorestable.

Usuallyatotalof8nFgatetosourcecapacitanceissufﬁcient

for stability and is typically provided by inherent MOSFET

The LTC4280 will set bit D2 and turn off in the event of

an overcurrent fault, preventing it from remaining in an

overcurrent condition. If conﬁgured to auto-retry, the

LTC4280willcontinuallyattempttorestartaftercool-down

cycles until it succeeds in starting up without generating

an overcurrent fault.

C , however the stability of the loop is degraded by

GS

increasing R

or by reducing the size of the resistor

SENSE

on a gate RC network if one is used, which may require

additional gate to source capacitance. Board level short-

circuit testing in highly recommended as board layout can

also affect transient performance, for stability testing the

worstcaseconditionforcurrentlimitstabilityoccurswhen

the output is shorted to ground after a normal startup.

Data Converter

The LTC4280 incorporates an 8-bit Δ∑ A/D converter

that continuously monitors three different voltages. The

Δ∑ architecture inherently averages signal noise during

the measurement period. The SOURCE pin has a 1/12.5

resistive divider to monitor a full-scale voltage of 15.4V

with 60mV resolution. The ADIN pin is monitored with a

1.235V full-scale and 4.82mV resolution, and the voltage

There are two possible parasitic oscillations when the

MOSFET operates as a source follower when ramping

at power-up or during current limiting. The ﬁrst type of

oscillation occurs at high frequencies, typically above

1MHz. This high frequency oscillation is easily damped

with R5 as shown in Figure 1. In some applications, one

may ﬁnd that R5 helps in short-circuit transient recovery

as well. However, too large of an R5 value will slow down

the turn-off time. The recommended R5 range is between

5Ω and 500Ω.

between the V and SENSE pins is monitored with a

DD

38.6mV full-scale and 151μV resolution.

Results from each conversion are stored in registers E

(Sense), F (Source) and G (ADIN), as seen in Tables 6-8,

and are updated 10 times per second. Setting CONTROL

register bit A5 invokes a test mode that halts the data

converter so that registers E, F, and G may be written to

and read from for software testing.

The second type of source follower oscillation occurs at

frequencies between 200kHz and 800kHz due to the load

capacitance being between 0.2μF and 9μF, the presence

4280f

17

LTC4280

APPLICATIONS INFORMATION

of R5 resistance, the absence of a drain bypass capacitor,

a combination of bus wiring inductance and bus supply

outputimpedance.Topreventthissecondtypeofoscillation

avoid load capacitance below 10μF, alternately connect an

external capacitor from the MOSFET gate to ground with

a value greater than 1.5μF.

Selectionofthesenseresistor,R ,issetbytheovercurrent

S

threshold of 25mV:

25mV

I_MAX

R_S=

= 0.005Ω

TheMOSFETissizedtohandlethepowerdissipationduring

inrush when output capacitor C is being charged. A

OUT

Supply Transients

method to determine power dissipation during inrush is

based on the principle that:

TheLTC4280isdesignedtoridethroughsupplytransients

caused by load steps. If there is a shorted load and the

parasitic inductance back to the supply is greater than

0.5μH, there is a chance that the supply collapses before

the active current limit circuit brings down the GATE pin.

If this occurs, the undervoltage monitors pull the GATE

pin low. The undervoltage lockout circuit has a 2μs ﬁlter

Energy in CL = Energy in Q1

This uses:

1

2

1

2

Energy in C_L= CV²= 0.33mF 12

(

)( )

or 0.024 joules. Calculate the time it takes to charge up

time after V drops below 2.74V. The UV pin reacts in

DD

C

:

OUT

2μs to shut the GATE off, but it is recommended to add a

ﬁlter capacitor C to prevent unwanted shutdown caused

V_DD

I_INRUSH

12V

1A

F

t

_STARTUP=C_L•

= 0.33mF •

= 4ms

byatransient.EventuallyeithertheUVpinorundervoltage

lockoutrespondstobringthecurrentundercontrolbefore

the supply completely collapses.

The power dissipated in the MOSFET:

Energyin C_L

t_STARTUP

Supply Transient Protection

P_DISS

=

= 6W

The LTC4280 is safe from damage with supply voltages up

to 24V. However, spikes above 24V may damage the part.

During a short-circuit condition, large changes in current

ﬂowing through power supply traces may cause inductive

voltagespikeswhichexceed24V.Tominimizesuchspikes,

the power trace inductance should be minimized by using

widertracesorheaviertraceplating.Also,asnubbercircuit

dampensinductivevoltagespikes.Buildasnubberbyusing

a 100Ω resistor in series with a 0.1μF capacitor between

TheSOA(safeoperatingarea)curvesofcandidateMOSFETs

must be evaluated to ensure that the heat capacity of the

package tolerates 6W for 4ms. The SOA curves of the

Fairchild FDC653N provide for 2A at 12V (24W) for 10ms,

satisfying this requirement. Since the FDC653N has less

than 8μF of gate capacitance and we are using a GATE

RC network, the short-circuit stability of the current limit

should be checked and improved by adding a capacitor

from GATE to SOURCE if needed.

V

and GND. A surge suppressor, Z1 in Figure 1, at the

DD

input can also prevent damage from voltage surges.

The inrush current is set to 1A using C1:

Design Example

I_GATE

C1= C_L•

I_INRUSH

As a design example, take the following speciﬁcations:

V

L

= 12V, I

= 5A, I

= 1A, 5ms FILTER time,

OV(OFF) PWRGD(UP)

IN

MAX

INRUSH

=10.75V,V

20μA

C =330μF,V

=14.0V,V

UV(ON)

C1= 0.33mF •

or C1= 6.8nF

2

1A

= 11.6V, and I C ADDRESS = 1010011. This completed

design is shown in Figure 1.

4280f

18

LTC4280

APPLICATIONS INFORMATION

For a start-up time of 4ms with a 2x safety margin we

choose:

In addition a 0.1μF ceramic bypass capacitor is placed on

the INTV pin.

CC

t_STARTUP

Layout Considerations

C

_TIMER= 2•

12.3ms/μF

8ms

To achieve accurate current sensing, a Kelvin connection

is required. The minimum trace width for 1oz copper

foil is 0.02" per amp to make sure the trace stays at a

reasonable temperature. Using 0.03" per amp or wider

is recommended. Note that 1oz copper exhibits a sheet

C_TIMER

=

≅ 0.68μF

12.3ms/μF

For an overcurrent fault ﬁlter time of 5ms we choose:

C = t /123ms/μF ≅ 47nF

F

FILTER

resistance of about 530μΩ/ . Small resistances add up

®

quickly in high current applications. To improve noise

immunity, put the resistive dividers to the UV, OV and FB

The UV and OV resistor string values can be solved in the

following method. First pick R3 based on I being

STRING

pins close to the device and keep traces to V and GND

DD

1.235V/R3 at the edge of the OV rising threshold, where

short. It is also important to put the bypass capacitor for

I

> 40μA. Then solve the following equations:

STRING

the INTV pin, C3, as close as possible between INTV

CC

V_OV(OFF)

UV_TH(RISING)

and GND. A 0.1μF capacitor from the UV pin (and OV pin

throughresistorR2)toGNDalsohelpsrejectsupplynoise.

Figure 4 shows a layout that addresses these issues. Note

that a surge suppressor, Z1, is placed between supply and

ground using wide traces.

R2 =

• R3 •

– R3

V_UV(ON)

OV_TH(FALLING)

V_UV(ON)•(R3+R2)

R1 =

– R3 – R2

UV_TH(RISING)

I

LOAD

SENSE RESISTOR R

S

In our case we choose R3 to be 3.4kΩ to give a resistor

string current below 100μA. Then solving the equations

results in R2 = 1.16kΩ and R1 = 34.6kΩ.

The FB divider is solved by picking R8 and solving for R7,

choosing 3.57kΩ for R8 we get:

R1

UV

OV

FB

Z1

C

R2

R3

F

V_PWRGD(UP)•R8

GPIO

R7 =

– R8

R8

FILTER

GND

ON

INTV

FB_TH(RISING)

CC

C3

TIMER

LTC4280UFD

resulting in R7 = 30kΩ.

ADIN

ADR2

ADR1

EN

A 0.1μF capacitor, C , is placed on the UV pin to prevent

F

SDAO

supply glitches from turning off the GATE via UV or OV.

The address is set with the help of Table 1, which indicates

binary address 1010011 corresponds to address 19.

Address 19 is set by setting ADR2 high, ADR1 open and

ADR0 high.

I

LOAD

4280 F05

Next the value of R5 and R6 are chosen to be the default

values 10Ω and 15k as discussed previously.

Figure 5. Recommended Layout

4280f

19

LTC4280

APPLICATIONS INFORMATION

SDA

a6 - a0

b7 - b0

SCL

1 - 7

8

9

1 - 7

8

9

1 - 7

8

9

S

P

START

CONDITION

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

STOP

CONDITION

4280 F06

Figure 6. Data Transfer Over I²C or SMBus

2

Digital Interface

I C Device Addressing

The LTC4280 communicates with a bus master using a

Twenty-seven distinct bus addresses are available using

three 3-state address pins, ADR0-ADR2. Table 1 shows

the correspondence between pin states and addresses.

Note that address bits B7 and B6 are internally conﬁgured

to 10. In addition, the LTC4280 responds to two special

addresses. Address (1011 111) is a mass write address

that writes to all LTC4280s, regardless of their individual

address settings. Mass write can be disabled by setting

registerA4tozero. Address(0001100)istheSMBusAlert

Response Address. If the LTC4280 is pulling low on the

ALERT pin, it acknowledges this address by broadcasting

its address and releasing the ALERT pin.

2

2-wire interface compatible with I C Bus and SMBus, an

2

I C extension for low power devices.

The LTC4280 is a read-write slave device and supports

SMBus bus Read Byte, Write Byte, Read Word and Write

Word commands. The second word in a Read Word

command is identical to the ﬁrst word. The second word

in a Write Word command is ignored. Data formats for

these commands are shown in Figures 6 to 11.

START and STOP Conditions

When the bus is idle, both SCL and SDA are high. A bus

mastersignalsthebeginningofatransmissionwithastart

condition by transitioning SDA from high to low while SCL

ishigh,asshowninFigure6.Whenthemasterhasﬁnished

communicating with the slave, it issues a STOP condition

by transitioning SDA from low to high while SCL is high.

The bus is then free for another transmission.

Acknowledge

The acknowledge signal is used in handshaking between

transmitter and receiver to indicate that the last byte of

data was received. The transmitter always releases the

SDA line during the acknowledge clock pulse. When the

slave is the receiver, it pulls down the SDA line so that it

4280f

20

LTC4280

APPLICATIONS INFORMATION

remains LOW during this pulse to acknowledge receipt

of the data. If the slave fails to acknowledge by leaving

SDA high, then the master may abort the transmission by

generatingaSTOPcondition.Whenthemasterisreceiving

data from the slave, the master pulls down the SDA line

during the clock pulse to indicate receipt of the data. After

the last byte has been received the master leaves the SDA

line HIGH (not acknowledge) and issues a stop condition

to terminate the transmission.

set to zero, as shown in Figure 9. The addressed LTC4280

acknowledges this and then the master sends a command

byte which indicates which internal register the master

wishes to read. The LTC4280 acknowledges this and then

latches the lower three bits of the command byte into its

internal Register Address pointer. The master then sends

a repeated START condition followed by the same seven

bit address with the R/W bit now set to one. The LTC4280

acknowledges and send the contents of the requested

register. The transmission is ended when the master

sends a STOP condition. If the master acknowledges

the transmitted data byte, as in a Read Word command,

Figure 10, the LTC4280 repeats the requested register as

the second data byte.

Write Protocol

ThemasterbeginscommunicationwithaSTARTcondition

followed by the seven bit slave address and the R/W bit

set to zero, as shown in Figure 7. The addressed LTC4280

acknowledges this and then the master sends a command

byte which indicates which internal register the master

wishes to write. The LTC4280 acknowledges this and

then latches the lower three bits of the command byte

into its internal Register Address pointer. The master then

delivers the data byte and the LTC4280 acknowledges

once more and latches the data into its control register.

The transmission is ended when the master sends a STOP

condition. If the master continues sending a second data

byte, as in a Write Word command, the second data byte

is acknowledged by the LTC4280 but ignored, as shown

in Figure 8.

Alert Response Protocol

When any of the fault bits in FAULT register D are set, an

optional bus alert is generated if the appropriate bit in

the ALERT register B is also set. If an alert is enabled, the

correspondingfaultcausestheALERTpintopulllow.After

the bus master controller broadcasts the Alert Response

Address, the LTC4280 responds with its address on the

SDA line and then release ALERT as shown in Figure 11.

The ALERT line is also released if the device is addressed

by the bus master. The ALERT signal is not pulled low

again until the FAULT register indicates a different fault

has occurred or the original fault is cleared and it occurs

again. Note that this means repeated or continuing faults

do not generate alerts until the associated FAULT register

bit has been cleared.

Read Protocol

ThemasterbeginsareadoperationwithaSTARTcondition

followed by the seven bit slave address and the R/W bit

4280f

21

LTC4280

APPLICATIONS INFORMATION

S

ADDRESS W A

1 0 a4:a0

COMMAND

A

DATA

A

P

0

X X X X X b2:b0

0

b7:b0

0

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

A: ACKNOWLEDGE (LOW)

A: NOT ACKNOWLEDGE (HIGH)

R: READ BIT (HIGH)

W: WRITE BIT (LOW)

S: START CONDITION

P: STOP CONDITION

4280 F07

Figure 7. LTC4280 Serial Bus SDA Write Byte Protocol

S

ADDRESS W A

1 0 a4:a0

COMMAND

A

DATA

A

DATA

A

P

0

X X X X X b2:b0

0

b7:b0

0

X X X X X X X X

0

4280 F08

Figure 8. LTC4280 Serial Bus SDA Write Word Protocol

ADDRESS W A

1 0 a4:a0

COMMAND

A

S

ADDRESS

R

A

DATA

A

P

0

X X X X X b2:b0

0

1 0 a4:a0

1

0

b7:b0

1

4280 F09

Figure 9. LTC4280 Serial Bus SDA Read Byte Protocol

S

ADDRESS W A

1 0 a4:a0

COMMAND

A

S

ADDRESS

R

A

DATA

A

DATA

A

P

0

X X X X X b2:b0

0

1 0 a4:a0

1

0

b7:b0

0

b7:b0

1

4280 F10

Figure 10. LTC4280 Serial Bus SDA Read Word Protocol

ALERT

RESPONSE

ADDRESS

DEVICE

ADDRESS

S

R

P

A

0 0 0 1 1 0 0

1

0

1 0 a4:a0 0

1

4280 F11

Figure 11. LTC4280 Serial Bus SDA Alert Response Protocol

4280f

22

LTC4280

APPLICATIONS INFORMATION

Table 1. LTC4280 Device Addressing (UH24 Package)

DEVICE

ADDRESS

h

LTC4280UH

ADDRESS PINS

DESCRIPTION

DEVICE ADDRESS

7

1

0

1

6

0

5

1

0

1

4

1

0

1

0

1

3

1

0

1

0

1

0

1

0

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

ADR2

X

ADR1

X

ADR0

X

Mass Write

BE

19

Alert Response

1

X

0

1

80

X

L

NC

H

L

82

L

NC

H

2

84

L

NC

L

3

86

L

4

88

L

5

8A

8C

8E

L

H

6

L

NC

H

7

L

8

90

NC

H

NC

H

L

9

92

NC

H

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

94

NC

L

96

98

L

9A

9C

9E

H

L

NC

H

L

A0

A2

A4

A6

A8

AA

AC

AE

B0

NC

H

L

H

NC

H

NC

L

H

L

H

L

NC

H

L

H

L

25

26

B2

B4

1

0

1

0

1

0

X

NC

H

L

4280f

23

LTC4280

APPLICATIONS INFORMATION

Table 2. CONTROL Register A (00h)—Read/Write

BIT

NAME

OPERATION

A7:6 GPIO Conﬁgure

FUNCTION

A6

A7

GPIO PIN

GPIO = C3

Power Good (Default)

Power Good

0

1

0

1

0

1

GPIO = C3

GPIO = B6

C6 = GPIO

General Purpose Output

General Purpose Input

A5

A4

A3

A2

Test Mode Enable Enables Test Mode to Disable the ADC; 1 = ADC Disable, 0 = ADC Enable (Default)

Mass Write Enable Allows Mass Write Addressing; 1 = Mass Write Enabled (Default), 0 = Mass Write Disabled

FET On Control

On Control Bit Latches the State of the ON Pin at the End of the Debounce Delay; 1 = FET On, 0 = FET Off

Overcurrent Auto-Retry Bit; 1 = Auto-Retry After Overcurrent, 0 = Latch Off After Overcurrent

Overcurrent

Auto-Retry

A1

A0

Undervoltage

Auto-Retry

Undervoltage Auto-Retry; 1 = Auto-Retry After Undervoltage (Default), 0 = Latch Off After Undervoltage

Overvoltage Auto-Retry; 1 = Auto-Retry After Overvoltage (Default), 0 = Latch Off After Overvoltage

Overvoltage

Auto-Retry

Table 3. ALERT Register B (01h)—Read/Write

BIT

B7

B6

B5

B4

NAME

OPERATION

Reserved

GPIO Output

Not Used

Output Data Bit to GPIO Pin when Conﬁgured as Output. Defaults to 0

FET Short Alert Enables Alert for FET Short Condition; 1 = Enable Alert, 0 = Disable Alert (Default)

EN State

Change Alert

Enables Alert when EN Changes State; 1 = Enable Alert, 0 Disable Alert (Default)

Enables Alert when Output Power is Bad; 1 = Enable Alert, 0 Disable Alert (Default)

Enables Alert for Overcurrent Condition; 1 = Enable Alert, 0 Disable Alert (Default)

Enables Alert for Undervoltage Condition; 1 = Enable Alert, 0 Disable Alert (Default)

Enables Alert for Overvoltage Condition; 1 = Enable Alert, 0 Disable Alert (Default)

B3

B2

B1

B0

Power Bad

Alert

Overcurrent

Alert

Undervoltage

Alert

Overvoltage

Alert

4280f

24

LTC4280

APPLICATIONS INFORMATION

Table 4. STATUS Register C (02h)—Read

BIT

C7

C6

C5

NAME

OPERATION

FET On

1 = FET On, 0 = FET Off

GPIO Input

State of the GPIO Pin; 1 = GPIO High, 0 = GPIO Low

FET Short

Present

Indicates Potential FET Short if Current Sense Voltage Exceeds 1mV While FET is Off; 1 = FET is Shorted, 0 = FET is Not

Shorted

C4

C3

C2

C1

C0

EN

Indicates if the LTC4280 is enabled when EN is low; 1 = EN Pin Low, 0 = EN Pin High

Indicates Power is Bad when FB is low; 1 = FB Low, 0 = FB High

Power Bad

Overcurrent

Undervoltage

Overvoltage

Indicates Overcurrent Condition During Cool Down Cycle; 1 = Overcurrent, 0 = Not Overcurrent

Indicates Input Undervoltage when UV is Low; 1 = UV Low, 0 = UV High

Indicates V or OV Input Overvoltage when OV is High; 1 = OV High, 0 = OV Low

DD

Table 5. FAULT Register D (03h)—Read/Write

BIT NAME OPERATION

D7:6 Reserved

D5

D4

D3

D2

D1

D0

FET Short Fault Indicates Potential FET Short was Detected when Measured Current Sense Voltage Exceeded 1mV while FET was Off;

Occurred

1 = FET is Shorted, 0 = FET is Good

EN Changed

State

Indicates That the LTC4280 was Enabled or Disabled when EN Changed State; 1 = EN Changed State, 0 = EN Unchanged

Power Bad

Fault Occurred

Indicates Power was Bad when FB when Low; 1 = FB was Low, 0 = FB was High

Overcurrent

Indicates Overcurrent Fault Occurred; 1 = Overcurrent Fault Occurred, 0 = Not Overcurrent Faults

Indicates Input Undervoltage Fault Occurred when UV went Low; 1 = UV was Low, 0 = UV was High

Indicates Input Overvoltage Fault Occurred when OV went High; 1 = OV was High, 0 = OV was Low

Fault Occurred

Undervoltage

Fault Occurred

Overvoltage

Fault Occurred

Table 6. SENSE Register E (04h)—Read/Write

BIT

NAME

OPERATION

E7:0

SENSE Voltage Measurement Sense Voltage Data. 8-Bit Data with 151μV LSB and 38.45mV Full Scale.

Table 7. SOURCE Register F (05h)—Read/Write

BIT

NAME

OPERATION

F7:0

SOURCE Voltage Measurement Source Voltage Data. 8-Bit Data with 60.5mV LSB and 15.44V Full Scale.

Table 8. ADIN Register G (06h)—Read/Write

BIT

NAME

OPERATION

G7:0

ADIN Voltage Measurement

ADIN Voltage Data. 8-Bit Data with 4.82mV LSB and 1.23V Full Scale.

4280f

25

LTC4280

TYPICAL APPLICATIONS

5V Backplane Resident Application with Insertion Activated Turn-On and a 5A Circuit Breaker

R

Q1

FDD3706

S

0.005Ω

V

IN

OUT

5V

R1

11.5k

1%

R7

6.98k

1%

R5

R4

10Ω

100k

R2

1.74k

1%

C

F

R8

2.67k

1%

0.1μF

+

–

UV V

SENSE SENSE GATE SOURCE

DD

R3

2.67k

1%

OV

ON

FB

LOAD

GPIO

EN

SDAI

SDAO

SCL

LTC4280UFD

C

1μF

EN

ADIN

FILTER

ALERT

C

F

47nF

INTV

TIMER ADR0 ADR1 ADR2 GND

CC

C3

0.1μF

4280 F13

BACKPLANE PLUG-IN

CARD

4280f

26

LTC4280

PACKAGE DESCRIPTION

UFD Package

24-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1696 Rev A)

0.70 p 0.05

4.50 p 0.05

3.10 p 0.05

2.65 p 0.05

2.00 REF

3.65 p 0.05

PACKAGE OUTLINE

0.25 p 0.05

0.50 BSC

3.00 REF

4.10 p 0.05

5.50 p 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

R = 0.05 TYP

PIN 1 NOTCH

2.00 REF

R = 0.20 OR C = 0.35

R = 0.115

TYP

0.75 p 0.05

4.00 p 0.10

(2 SIDES)

23

24

0.40 p 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

5.00 p 0.10

(2 SIDES)

3.00 REF

3.65 p 0.10

2.65 p 0.10

(UFD24) QFN 0506 REV A

0.25 p 0.05

0.200 REF

0.50 BSC

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

4280f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LTC4280

TYPICAL APPLICATION

–12V Card Resident Application with Optically Isolated I²C and a 16.6A Circuit Breaker

R

Q1

Si7880DP

S

0.0015Ω

OUTPUT

GND

5V

R1

34.8k

1%

–7V

R9

10k

R5

10Ω

R10

3.3k

–7V

8

R2

1.18k

1%

C1

R6

15k

22nF

2

3

6

R7

30.1k

1%

C

F

–12V

0.1μF

R3

3.4k

1%

+

–

UV V

SENSE SENSE GATE

SOURCE

FB

DD

HCPL-0300

5

OV

R8

3.57k

1%

ADIN

GPIO

EN

–12V

–7V

SDAI

SDAO

SCL

SDA

LTC4280UFD

R4

3.3k

C

L

D2

P6KE16A

ON

FILTER

1000μF

INTV

CC

ADR0 ADR1 ADR2 GND TIMER

6

5

8

2

–7V

R12

HCPL-0300

3

C3

0.1μF

C

F

TIMER

1μF

R13

3.3k

47nF

10k

–7V

8

SCL

2

3

6

5

R14

100k

HCPL-0300

Q2

D1

5.6V

–7V

V

IN

–12V

4280 F14

BACKPLANE PLUG-IN

CARD

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

7V to 80V Single Voltage/Current Monitor with 12-Bit ADC

LTC4151

High Voltage Current and Voltage Monitor

with ADC and I C

2

LTC4210

LTC4211

LTC4212

LTC4215

Single Channel, Hot Swap Controller

Single Channel, Hot Swap Controller with

Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6

Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10

Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10

Operates from 2.9V to 15V, 8-Bit ADC Monitors Current and Voltage

2

I C Monitoring

LTC4216

LTC4222

LTC4245

Single Channel, Hot Swap Controller

Operates from 0V to 6V, MSOP-10 or 12-Lead (4mm × 3mm) DFN

2

Dual Hot Swap Controller with ADC and I C 2.9V to 29V Dual Controller with 10-Bit ADC, dl/dt Controlled Soft-Start

Multiple Supply CompactPCI or PCI Express Internal 8-Bit ADC, dl/dt Controlled Soft-Start

2

Hot Swap Controller with I C

LTC4260

LTC4261

Positive High Voltage Hot Swap Controller

8-Bit ADC Monitoring Current and Voltages, Supplies from 8.5V to 80V

2

with ADC and I C

Negative High Voltage Hot Swap Controller 10-Bit ADC Monitoring Current and Voltages, Supplies from –12V to –100V

2

with ADC and I C

4280f

LT 0510 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC4280CUFD-TRPBF
厂家：	Linear
描述：	Hot Swap Controller with I2C Compatible Monitoring 热插拔控制器与I2C兼容的监控监控控制器
文件：	总28页 (文件大小：286K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC4280CUFD-TRPBF [Linear]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E