LTC4303CMS8#PBF [Linear]
LTC4303 - Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C;
| 型号： | LTC4303CMS8#PBF |
| 厂家： | 
Linear |
| 描述： | LTC4303 - Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C 驱动程序和接口 接口集成电路 光电二极管 |
| 文件： | 总12页 (文件大小：541K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4303
Hot Swappable 2-Wire
Bus Buffer with Stuck
Bus Recovery
U
FEATURES
DESCRIPTIO
The LTC®4303 hot swappable 2-wire Bus Buffer allows I/O
card insertion into a live backplane without corruption of
the data and clock busses. When a connection is made,
the LTC4303 provides bidirectional buffering, keeping the
backplane and card capacitances isolated. If SDAOUT or
SCLOUTislowfor≥30ms(typ),theLTC4303automatically
breaks the data and clock bus connection. At this time the
LTC4303automaticallygeneratesupto16clockpulseson
SCLOUT in an attempt to free the bus. A connection will
be enabled automatically when the bus becomes free.
■
Automatic Disconnect of SDA/SCL Lines when Bus
is Stuck Low for ≥ 30ms
■
Recovers Stuck Busses with Automatic Clocking*
■
Bidirectional Buffer* for SDA and SCL Lines
Increases Fanout
■
Prevents SDA and SCL Corruption During Live
Board Insertion and Removal from Backplane
■
Pin Compatible with LTC4300A-1
■
1ꢀkꢁ ꢂuman Bodꢃ ꢄodel ꢅSD Protection
■
Isolates Input SDA and SCL Lines from Output
2
2
Compatible with I CTM, I C Fast-Mode and SMBus
Standards (Up to 400kHz Operation)
READY Open Drain Output
■
Rise-timeacceleratorcircuitryallowstheuseoflargerpull-
up resistance while still meeting rise-time requirements.
During insertion, the SDA and SCL lines are precharged
to 1V to minimize bus disturbances. When driven high,
ENABLE allows the LTC4303 to connect after a stop bit or
busidleoccurs.DrivingENABLElowbreakstheconnection
betweenSDAINandSDAOUT,SCLINandSCLOUT.READY
is an open drain output that indicates when the backplane
and card sides are connected together.
■
■
■
■
■
1V Precharge on All SDA and SCL Lines
High Impedance SDA, SCL Pins for V = 0V
CC
ENABLE Gates Connection from Input to Output
MSOP 8-Pin andUDFN (3mm × 3mm) Packages
APPLICATIO S
■
Hot Board Insertion
■
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6356140, 6650174, 7032051.
Servers
■
Capacitance Buffer/Bus Extender
■
RAID Systems
U
TYPICAL APPLICATIO
Stuck Bus Resolved
with Automatic Clocking
5V 3.3V
0.01
F
10k 10k
V
CC
10k 10k
LTC4303
SDAOUT
5V/DIV
SCLIN
SCLOUT
BACK_SCL
CARD_SCL
CARD_SDA
SDAIN
5V/DIV
SDAIN
SDAOUT
READY
BACK_SDA
3.3V
SCLOUT
5V/DIV
ENABLE
GND
100k
4303 TA01
4303 TA01b
200 s/DIV
BACKPLANE
CONNECTOR CONNECTOR
CARD
STAGGERED
4303fb
1
LTC4303
W W U W
(Notes 1, 2)
ABSOLUTE AXI U RATI GS
SDAIN, SCLIN, SDAOUT, SCLOUT, READY
(Note 3)..................................................................30mA
Storage Temperature Range
V
to GND ..................................................–0.3V to 7V
CC
SDAIN, SCLIN, SDAOUT, SCLOUT,
READY, ENABLE...........................................–0.3V to 7V
Operating Temperature
MSOP ................................................–65°C to 150°C
DFN....................................................–65°C to 125°C
Lead Temperature (Soldering, 10sec)
LTC4303C ................................................ 0°C to 70°C
LTC4303I .............................................–40°C to 85°C
MSOP ............................................................... 300°C
U
W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ENABLE
SCLOUT
SCLIN
GND
1
2
3
4
8
7
6
5
V
CC
TOP VIEW
SDAOUT
SDAIN
9
ENABLE
SCLOUT
SCLIN
GND
1
2
3
4
8 V
CC
7 SDAOUT
6 SDAIN
5 READY
READY
MS8 PACKAGE
8-LEAD PLASTIC MSOP
= 125°C, θ = 200°C/W
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
T
JMAX
JA
T
JMAX
= 125°C, θ = 43°C/W
JA
EXPOSED PAD (PIN 9)
PCB CONNECTION OPTIONAL
ORDER PART NUMBER
DD PART MARKING*
LBPZ
ORDER PART NUMBER
MS8 PART MARKING*
LTBPY
LTC4303CDD
LTC4303IDD
LTC4303CMS8
LTC4303IMS8
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which applꢃ over the full operating
temperature range, otherwise specifications are at T = 2ꢀ°C. ꢁ = 2.7ꢁ to ꢀ.ꢀꢁ, unless otherwise noted.
A
CC
SYꢄBOL
PARAꢄꢅTꢅR
CONDITIONS
ꢄIN
TYP
ꢄAX
UNITS
Power Supplꢃ
V
Positive Supply Voltage
●
●
2.7
5.5
8
V
CC
I
CC
Supply Current
Supply Current, ENABLE = GND
V
V
= 5.5V, V
= 5.5V
= V = 0V (Note 7)
SDAOUT
6
1.5
mA
mA
CC
CC
SDAIN
Startup Circuitrꢃ
V
Precharge Voltage
Bus Idle Time
SDA, SCL Floating, V = 5.5V
●
●
0.8
60
1
1.2
V
PRE
CC
T
IDLE
95
175
µs
V
READY Output Low Voltage
I
I
= 3mA
= 6mA, V = 4.7V
●
●
0.4
0.4
V
V
OL_READY
PULLUP
PULLUP
CC
V
ENABLE Threshold
●
●
●
0.8
1.6
1.4
0.1
1.8
2
V
µA
V
THR_ENABLE
ENABLE
I
ENABLE Input Current
ENABLE from 0 to V
1.5
2
CC
V
THR
SDA, SCL Logic Input Threshold Voltage Rising Edge
4303fb
2
LTC4303
The
●
denotes the specifications which applꢃ over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T = 2ꢀ°C. ꢁ = 2.7ꢁ to ꢀ.ꢀꢁ, unless otherwise noted.
A
CC
SYꢄBOL
PARAꢄꢅTꢅR
CONDITIONS
ꢄIN
TYP
ꢄAX
UNITS
V
SDA, SCL, Logic Input Threshold Voltage (Note 6)
Hysteresis
50
mV
HYS
t
t
t
t
I
Delay ENABLE High-Low to Disconnect
Delay READY High-Low after Disconnect
Delay ENABLE Low-High to Connect
Delay READY Low-High after Connect
Ready Off Leakage Current
V
= 3.3V
300
10
ns
ns
µs
ns
µA
PHL_ENABLE
PHL_READY
PLH_ENABLE
PLH_READY
OFF_READY
CC
V
CC
= 3.3V
●
●
60
95
175
10
10
Rise-Time Accelerators
Transient Boosted Pull-Up Current
I
Positive Transition on SDA, SCL, V = 2.7V,
Slew Rate = 0.8V/µs (Note 5)
2
3.5
30
5.5
mA
ms
PULLUPAC
CC
Bus Stuck Low Timeout
Bus Stuck Low Timer
Input-Output Connection
t
SDAOUT, SCLOUT = 0V
●
25
35
TIMEOUT
V
Input-Output Offset Voltage
10k to V on SDA, SCL,
●
●
40
50
80
100
120
150
mV
mV
OS
CC
2.7k to V on SDA, SCL
CC
V
CC
= 3.3V, V
= 0.2V (Note 4)
SDA/SCL
C
V
Digital Input Capacitance
SDAIN, SDAOUT, SCLIN, SCLOUT
(Note 6)
10
pF
IN
Input Logic Low Voltage
Input Leakage Current
●
●
●
0.4
5
V
µA
V
IL, MAX
LEAK
I
SDA, SCL, V = 5.5V
CC
V
Output Low Voltage, Input = 0
SDA, SCL Pins, I
= 4mA, V = 2.7V
0
0.19
600
0.3
OL
SINK
CC
Timing Characteristics
2
f
t
I C Maximum Operating Frequency
(Note 6)
(Note 6)
400
kHz
µs
I2C, MAX
BUF
Bus Free Time Between Stop and Start
Condition
1.3
t
Hold Time After (Repeated)
Start Condition
(Note 6)
100
ns
HD, STA
t
t
t
t
Repeated Start Condition Set-Up Time
Stop Condition Set-Up Time
Data Hold Time Input
(Note 6)
(Note 6)
(Note 6)
(Note 6)
0
0
ns
ns
ns
ns
SU, STA
SU, STO
HD, DATI
SU, DAT
0
Data Set-Up Time
100
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The connection circuitry always regulates the output to a higher
voltage than its input. The magnitude of this offset voltage as a function of
the pull-up resistor and V voltage is shown in the Typical Performance
CC
Characteristics section.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specified.
Note ꢀ: I
varies with temperature and V voltage, as shown in
PULLUPAC
CC
the Typical Performance Characteristics section.
Note 3: Pulsed less than 5µs.
Note 6: Guaranteed by design, not tested in production.
Note 7: I test performed with connection circuitry active.
CC
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3
LTC4303
U W
T = 2ꢀ°C unless otherwise indicated.
A
TYPICAL PERFOR A CE CHARACTERISTICS
I
vs Temperature
Input-Output t
vs Temperature
I
vs Temperature
CC
PꢂL
PULLUPAC
140
120
100
80
14
12
10
8
6.2
6.0
C
= C
OUT
PULLUPIN
= 100pF
IN
V
= 5.5V
R
= R
= 10k
PULLUPOUT
CC
V
= 5.5V
= 3.3V
CC
5.8
5.6
V
CC
60
6
5.4
5.2
40
4
V
= 2.7V
25
V
= 2.7V
CC
CC
0
20
2
0
–50
0
–50
5.0
–50
0
50
75
100
0
25
50
75
100
25
50
75
100
–25
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4303 G02
4303 G03
4303 G01
Connection Circuitrꢃ ꢁ
- ꢁ
Input-Output t vs C
PꢂL OUT
OUT
IN
180
250
200
C
= 50pF
PULLUPIN
IN
R
= R
= 10k
PULLUPOUT
160
140
120
100
80
V
= 5.5V
= 2.7V
CC
150
100
50
0
V
CC
60
40
20
1000
3000
5000
7000
(Ω)
9000
0
500
1000
1500
2000
R
C
(pF)
PULLUP
OUT
4303 G05
4303 G04
4303fb
4
LTC4303
U
U
U
PI FU CTIO S
ꢅNABLꢅ (Pin 1): Connection Enable. This is a digital
threshold input pin. For normal operation ENABLE is high.
DrivingENABLEbelow0.8VisolatesSDAINfromSDAOUT,
SCLIN from SCLOUT, asserts READY low and disables
automatic clocking. A rising edge on ENABLE after a fault
hasoccurredunconditionallyforcesaconnectionbetween
SDAIN, SDAOUT and SCLIN, SCLOUT.
RꢅADY (Pin ꢀ): Connection Status Flag. READY provides
a digital flag which indicates the status of the connection
circuitry described in the “Connection Circuitry” section.
Connect a resistor of 10k to V to provide the pull-up.
CC
SDAIN (Pin 6): Serial Data Input. Connect this pin to the
SDA bus on the backplane.
SDAOUT (Pin 7): Serial Data Output. Connect this pin to
the SDA bus on the card.
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
the SCL bus on the card.
ꢁ
(Pin8):SupplyVoltageInput.Placeabypasscapacitor
CC
SCLIN (Pin 3): Serial Clock Input. Connect this pin to SCL
on the bus backplane.
of at least 0.01µF close to V for best results.
CC
ꢅxposed Pad (Pin 9, DFN Onlꢃ): Exposed pad may be left
open or connected to the ground plane.
GND (Pin 4): Device Ground. Connect this pin to a ground
plane for best results.
W
BLOCK DIAGRA
LTC4303 2-Wire Bus Buffer with Stuck Bus Protection
3.5mA
3.5mA
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
CONNECT
V
8
6
CC
SDAIN
SDAOUT
200k
7
2
5
200k
PC_CONNECT
PC_CONNECT
PRECHARGE
3.5mA
3.5mA
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
200k
200k
CONNECT
SCLIN
SCLOUT
3
+
–
+
–
AUTOMATIC
CLOCKING
30ms
TIMER
UVLO
+
–
1.8V
–
+
LOGIC
PC_CONNECT
1.8V
READY
GND
CONNECT
ENABLE
+
–
1
95 s
DELAY
CONNECT
UVLO
1.4V
4
4301 BD
4303fb
5
LTC4303
U
OPERATIO
Start-Up
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms, as
described here.
When the LTC4303 first receives power on its V pin,
CC
eitherduringpoweruporliveinsertion,itstartsinanunder
voltage lockout (UVLO) state, ignoring any activity on the
Input to Output Offset ꢁoltage
SDA or SCL pins until V rises above 2.5V (typical).
CC
When a logic low voltage, V
, is driven on any of the
LOW1
During this time, the precharge circuitry is active and
forces 1V through 200k nominal resistors to the SDA
and SCL pins. Because the I/O card is being plugged
into a live backplane, the voltage on the backplane SDA
LTC4303’s data or clock pins, the LTC4303 regulates the
voltage on the opposite side of the part (call it V
)
LOW2
to a slightly higher voltage, as directed by the following
equation:
and SCL busses may be anywhere between 0V and V .
CC
V
LOW2
= V + 75mV + (V /R) • 20Ω (typical)
LOW1 CC
Precharging the SCL and SDA pins to 1V minimizes the
worst-case voltage differential these pins will see at the
moment of connection, therefore minimizing the amount
of disturbance caused by the I/O card.
where R is the bus pull-up resistance in ohms. For ex-
ample, if a device is forcing SDAOUT to 10mV where
V
CC
= 3.3V and the pull-up resistor R on SDAIN is 10k,
then the voltage on SDAIN = 10mV + 75mV + (3.3/10000)
• 20 = 91.6mV (typical). See the Typical Performance
Characteristics section for curves showing the offset
Once the LTC4303 comes out of UVLO, it assumes that
SDAIN and SCLIN have been inserted into a live system
and that SDAOUT and SCLOUT are being powered up at
the same time as itself. Therefore, it looks for either a stop
bit or bus idle condition on the input side to indicate the
completion of a data transaction. When either one occurs,
the part also verifies that both the SDAOUT and SCLOUT
voltages are high. When all of these conditions are met,
the input-to-output connection circuitry is activated, join-
ing the SDA and SCL busses on the I/O card with those
on the backplane and READY goes high.
voltage as a function of V and R.
CC
Bus Stuck Low Time-Out
When SDAOUT or SCLOUT is low, an internal timer starts.
The timer is only reset when SDAOUT and SCLOUT are
both high. If they do not go high within 30ms (typical),
the connection between SDAIN and SDAOUT, and SCLIN
and SCLOUT is broken. After a delay of at least 40µs the
LTC4303 automatically generates up to 16 clock pulses at
8.5kHz (typical) on SCLOUT in an attempt to unstick the
bus. When SDAOUT and SCLOUT go high, reconnection
occurs when the conditions described in the “Start-Up”
section above are satisfied.
Connection Circuitrꢃ
Oncetheconnectioncircuitryisactivated,thefunctionality
of the SDAIN and SDAOUT pins is identical. A low forced
on either pin at any time results in both pin voltages be-
ing low. For proper operation, logic low input voltages
shouldbenohigherthan0.4ꢁwithrespecttotheground
pin voltage of the LTC4303. SDAIN and SDAOUT enter
a logic high state only when all devices on both SDAIN
and SDAOUT release high. The same is true for SCLIN
and SCLOUT. This important feature ensures that clock
stretching, clock synchronization, arbitration and the ac-
knowledge protocol always work, regardless of how the
devices in the system are tied to the LTC4303.
When powering up into a bus stuck low condition, the
connection circuitry joining the SDA and SCL busses on
the I/O card with those on the backplane is not activated.
30ms after UVLO, automatic clocking takes place as
described above.
Propagation Delaꢃs
During a rising edge, the rise-time on each side is de-
termined by the bus pull-up resistor and the equivalent
capacitance on the line. If the pull-up resistors are the
same, a difference in rise-time occurs which is directly
proportional to the difference in capacitance between
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation,
4303fb
6
LTC4303
U
OPERATIO
OUTPUT SIDE
50pF
INPUT SIDE
150pF
0.5V/DIV
INPUT SIDE
50pF
0.5V/DIV
OUTPUT SIDE
150pF
0.5V/DIV
0.5V/DIV
4303 F01
4303 F02
200ns/DIV
20ns/DIV
Figure 1. Input-Output Connection t
Figure 2. Input-Output Connection t
PLꢂ
PꢂL
ꢅNABLꢅ
the two sides. This effect is displayed in Figure 1 for a
= 3.3V and a 10k pull-up resistor on each side (50pF
V
CC
When the ENABLE pin is driven below 0.8V with respect
to the LTC4303’s ground, the backplane side is discon-
nected from the card side, and the READY pin is internally
pulled low. When the pin is driven above 2V, the part waits
for data transactions on the IN side to be complete and
for the OUT side to be high (as described in the Start-Up
section) before connecting the two sides. At this time the
internal pull-down on READY releases. When ENABLE is
low, automatic clocking is disabled.
on one side and 150pF on the other). Since the output side
has less capacitance than the input, it rises faster and the
effective t
is negative.
PLH
There is a propagation delay, t , through the connec-
PHL
tion circuitry for falling waveforms. Figure 2 shows the
falling edge waveforms. An external driver pulls down
the voltage on the side with 50pF capacitance; LTC4303
pulls down the voltage on the opposite side with a delay
of 80ns. This delay is always positive and is a function of
supply voltage, temperature and the pull-up resistors and
equivalent bus capacitances on both sides of the bus. The
A rising edge on ENABLE after a stuck bus condition has
occurred forces a connection between SDAIN, SDAOUT
and SCLIN, SCLOUT even if bus idle conditions are not
met. At this time the internal 30ms timer is reset but not
disabled.
Typical Performance Characteristics section shows t
PHL
as a function of temperature and voltage for 10k pull-up
resistors and 100pF equivalent capacitance on both sides
of the part. Larger output capacitances translate to longer
delays. Users must quantify the difference in propagation
timesforarisingedgeversusafallingedgeintheirsystems
and adjust setup and hold times accordingly.
Rise Time Accelerators
Onceconnectionhasbeenestablished,risetimeaccelerator
circuits on all four SDA and SCL pins are activated. These
allow the use of larger pull-up resistors, reducing power
consumption, or bus capacitance beyond that specified
RꢅADY Digital Output
2
in I C, while still meeting system rise time requirements.
The READY pin provides a digital flag which indicates the
status of the connection circuitry described previously in
the “Connection Circuitry” section. READY is high when
the connection circuitry is active, and pulls low when
there is not a valid connection. The pin is driven by an
open drain pull-down capable of sinking 3mA while hold-
During positive bus transitions, the LTC4303 switches in
3.5mA (typical) of current to quickly slew the SDA and
SCL lines once their DC voltages exceed 0.8V. Choose a
pull-up resistor so that the bus will rise on its own at a
rate of at least 0.8V/µs to guarantee activation of the ac-
celerators. Rise time accelerators turn off when SDA and
ing 0.4V on the pin. Connect a resistor of 10k to V to
CC
SCL lines are approximately 1V below V .The rise time
CC
provide the pull-up.
accelerators are automatically disabled during automatic
clocking.
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7
LTC4303
U
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APPLICATIO S I FOR ATIO
Resistor Pull-Up Selection
In most applications the LTC4303 will be used with a
staggered connector where V and GND will be long
CC
The system pull-up resistors must be strong enough
to provide a positive slew rate of 0.8V/µs on the SDA
and SCL pins, in order to activate the rise time accelera-
tors during rising edges. Choose maximum resistor value
pins. SDA and SCL are medium length pins to ensure that
the V and GND pins make contact first. This will allow
CC
the precharge circuitry to be activated on SDA and SCL
before they make contact. ENABLE is a short pin that is
pulled down when not connected. This is to ensure that
the connection between the backplane and the cards data
and clock busses is not enabled until the transients as-
sociated with live insertion have settled.
R
using the formula:
PULL-UP(MAX)
where V
ply voltage, and C
tive bus line.
is the minimum operating pull-up sup-
BUS
BUSMIN
the total capacitance on respec-
V
– 0.8V •1250[ns/V]
(
)
Figure 3 shows the LTC4303 in a CompactPCITM configu-
BUS(MIN)
R
PULLUP(MAX)[kΩ] =
CBUS[pF]
ration. Connect V and ENABLE to the output of one of
CC
the CompactPCI power supply Hot Swap circuits. Use a
pull-up resistor to ENABLE for a card side enable/disable.
For example, assume V
= V = 3.3V, and assuming
CC
BUS
10ꢀ supply tolerance, V
= 2.97V. With C
=
BUSMIN
BUS
V
is monitored by a filtered UVLO circuit. With the V
CC
CC
100pF, R
= 27.1k. Therefore a smaller pull-up
PULL-UP, MAX
voltagepoweringupafteralltheotherpinshaveestablished
connection, the UVLO circuit ensures that the backplane
andthecarddataandclockbussesarenotconnecteduntil
the transients associated with live insertion have settled.
Owing to their small capacitance, the SDAIN and SCLIN
pins cause minimal disturbance on the backplane busses
when they make contact with the connector.
resistor than 27.1k must be used, so 10k works fine.
Live Insertion and Capacitance Buffering Application
Figures 3 through 6 illustrate applications of the LTC4303
TM
thattakeadvantageofbothitsHotSwap controllingand
capacitancebufferingfeatures. Inalloftheseapplications,
note that if the I/O cards were plugged directly into the
backplanewithouttheLTC4303buffer, allofthebackplane
andcardcapacitanceswouldadddirectlytogether,making
rise-andfall-timerequirementsdifficulttomeet. Placinga
LTC4303 on the edge of each card, however, isolates the
card capacitance from the backplane. For a given I/O card,
the LTC4303 drives the capacitance on the card side and
thebackplanemustdriveonlythedigitalinputcapacitance
of the LTC4303, which is less than 10pF.
Figure 4 shows the LTC4303 in a PCI application where all
of the pins have the same length. In this case, a RC filter
circuit on the I/O card with a product of 10ms provides
a filter to prevent the LTC4303 from becoming activated
until the transients associated with live insertion have
settled. Connect the capacitor between ENABLE and GND,
and the resistor from V to ENABLE.
CC
Hot Swap is a trademark of Linear Technology Corporation.
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LTC4303
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APPLICATIO S I FOR ATIO
BACKPLANE
CONNECTOR
STAGGERED
CONNECTOR
BACKPLANE
I/O PERIPHERAL CARD 1
C1
POWER SUPPLY
HOT SWAP
V
CC
R3
10k
R4
10k
R5
R6
10k
0.01µF
R1
10k
R2
10k
10k
CARD
ENABLE/DISABLE
V
CARD1_SDA
CARD1_SCL
BD_SEL
SDA
ENABLE
SDAIN
SCLIN
SDAOUT
CC
SCLOUT
READY
LTC4303
SCL
GND
I/O PERIPHERAL CARD 2
C3
POWER SUPPLY
HOT SWAP
R7
10k
R8
10k
R9
10k
R10
10k
0.01µF
CARD
ENABLE/DISABLE
CARD2_SDA
CARD2_SCL
V
ENABLE
SDAIN
SCLIN
SDAOUT
CC
SCLOUT
READY
LTC4303
GND
I/O PERIPHERAL CARD N
C5
POWER SUPPLY
HOT SWAP
R11
10k
R12
10k
R13
10k
R14
10k
0.01µF
CARD
ENABLE/DISABLE
CARDN_SDA
CARDN_SCL
V
ENABLE
SDAIN
SCLIN
SDAOUT
CC
SCLOUT
READY
LTC4303
GND
4303 F03
Figure 3. Inserting ꢄultiple I/O Cards into a Live Backplane Using the LTC4303 in a CompactPCI Sꢃstem
4303fb
9
LTC4303
U
W U U
APPLICATIO S I FOR ATIO
BACKPLANE
CONNECTOR
BACKPLANE
I/O PERIPHERAL CARD 1
C1
V
CC
R3
100k
R4
10k
R5
10k
R6
10k
R1
10k
R2
10k
0.01 F
V
CC
SDAOUT
SCLOUT
READY
CARD1_SDA
CARD1_SCL
ENABLE
SDAIN
SCLIN
SDA
SCL
LTC4303
GND
C2
0.1 F
I/O PERIPHERAL CARD 2
C3
R8
10k
R9
10k
R10
10k
R7
100k
0.01 F
V
CC
SDAOUT
SCLOUT
READY
CARD2_SDA
CARD2_SCL
ENABLE
SDAIN
SCLIN
LTC4303
GND
C4
0.1 F
4303 F04
•
•
•
Figure 4. Inserting ꢄultiple I/O Cards into a Live Backplane Using the LTC4303 in a PCI Sꢃstem
V
CC
ATCA BOARD
SHELF MANAGER
0.01µF
0.01µF
R5
10k
R6
10k
R1
10k
R2
10k
R3
R4
2.7k 2.7k
V
V
V
V
CC
CC
CC
CC
ENABLE
SDAOUT
SCLOUT
ENABLE
SDAOUT
SDAIN
SDAIN
SCLIN
ShMC
IPMC
LTC4303
LTC4303
SCLIN
SCLOUT
IPM
BUS
(1 OF 2)
4303 F05
Figure ꢀ. Simplified ATCA IPꢄB Application
4303fb
10
LTC4303
U
PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 0ꢀ-08-1698)
R = 0.115
0.38 0.10
8
TYP
5
0.675 0.05
3.5 0.05
2.15 0.05 (2 SIDES)
1.65 0.05
3.00 0.10
(4 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
(DD8) DFN 1203
4
1
0.25 0.05
0.75 0.05
0.200 REF
0.25 0.05
0.50 BSC
0.50
BSC
2.38 0.05
(2 SIDES)
2.38 0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
ꢄS8 Package
8-Lead Plastic ꢄSOP
(Reference LTC DWG # 0ꢀ-08-1660)
3.00 0.102
(.118 .004)
(NOTE 3)
0.889 0.127
(.035 .005)
0.52
(.0205)
REF
8
7 6
5
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .006)
DETAIL “A”
0° – 6° TYP
0.254
(.010)
GAUGE PLANE
0.65
(.0256)
BSC
0.42 0.038
(.0165 .0015)
TYP
1
2
3
4
0.53 0.152
(.021 .006)
1.10
(.043)
MAX
0.86
(.034)
REF
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.18
(.007)
SEATING
PLANE
NOTE:
0.22 – 0.38
0.127 0.076
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
(.009 – .015)
(.005 .003)
0.65
(.0256)
BSC
TYP
MSOP (MS8) 0204
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
4303fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC4303
U
TYPICAL APPLICATIO
3.3V
C1
5V
0.01 F
R3
10k 10k
R4
V
CC
R1
R2
LTC4303
10k 10k
SCLIN
SCLOUT
SDAOUT
BACK_SCL
BACK_SDA
CARD_SCL
SDAIN
CARD_SDA
FROM
MICROPROCESSOR
ENABLE
READY
GND
R5
100k
4303 F06
BACKPLANE
CONNECTOR CONNECTOR
CARD
STAGGERED
Figure 6. Sꢃstem with Active Connection Control
RELATED PARTS
PART NUꢄBꢅR
DꢅSCRIPTION
COꢄꢄꢅNTS
LTC1380/LTC1393
Single-Ended 8-Channel/Differential 4-Channel Analog
Mux with SMBus Interface
Low RON: 35Ω Single-Ended/70Ω Differential,
Expandable to 32 Single or 16 Differential Channels
LTC1427-50
Micropower, 10-Bit Current Output DAC
with SMBus Interface
Precision 50µA 2.5ꢀ Tolerance Over Temperature,
4 Selectable SMBus Addresses, DAC Powers up at Zero or Midscale
LTC1623
Dual High Side Switch Controller with SMBus Interface 8 Selectable Addresses/16-Channel Capability
LTC1663
SMBus Interface 10-Bit Rail-to-Rail Micropower DAC
SMBus Accelerator
DNL < 0.75LSB Max, 5-Lead SOT-23 Package
LTC1694/LTC1694-1
Improved SMBus/I2C Rise-Time,
Ensures Data Integrity with Multiple SMBus/I2C Devices
LT1786F
LTC1695
LTC1840
SMBus Controlled CCFL Switching Regulator
SMBus/I2C Fan Speed Controller in ThinSOTTM
Dual I2C Fan Speed Controller
1.25A, 200kHz, Floating or Grounded Lamp Configurations
0.75Ω PMOS 180mA Regulator, 6-Bit DAC
Two 100µA 8-Bit DACs, Two Tach Inputs, Four GPI0
Isolates Backplane and Card Capacitances
LTC4300A-1/LTC4300A-2 Hot Swappable 2-Wire Bus Buffer
LTC4300A-3
LTC4301
Hot Swappable 2-Wire Bus Buffer
Provides Level Shifting and Enable Functions
Supply Independent
Supply Independent Hot Swappable 2-Wire Bus Buffer
LTC4301L
Hot Swappable 2-Wire Bus Buffer
with Low Voltage Level Translation
Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN
LTC4302-1/LTC4302-2
LTC4304
Addressable 2-Wire Bus Buffer
Address Expansion, GPIO, Software Controlled
2
Hot Swappable 2-Wire Bus Buffer with
Stuck Bus Recovery
Provides Automatic Clocking to Free Stuck I C Busses; Fault Flag
for Stuck Bus, Level Shifting Functions
ThinSOT is a trademark of Linear Technology Corporation.
4303fb
LT/LWI 0806 REV B • PRINTED IN USA
12 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
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