LTC4305IDHD_技术文档

LTC4305

2-Channel,

2-Wire Bus Multiplexer with

Capacitance Buffering

U

FEATURES

DESCRIPTIO

The LTC^®4305 is a 2-channel, 2-wire bus multiplexer with

bus buffers to provide capacitive isolation between the

upstream bus and downstream buses. Through software

control, the LTC4305 connects the upstream 2-wire bus

to any desired combination of downstream channels.

Each channel can be pulled up to a supply voltage ranging

from 2.2V to 5.5V, independent of the LTC4305 supply

voltage. The downstream channels are also provided with

an ALERT1–ALERT2 inputs for fault reporting.

■

1:2 2-Wire Multiplexer/Switch

■

Connect SDA and SCL Lines with 2-Wire Bus

Commands

■

Supply Independent Bidirectional Buffer for SDA

and SCL Lines Increases Fan-Out

■

Programmable Disconnect from Stuck Bus

Compatible with I²C and SMBus Standards

■

Rise Time Accelerator Circuitry

■

SMBus Compatible ALERT Response Protocol

■

Prevents SDA and SCL Corruption During Live Board

Programmable timeout circuitry disconnects the down-

stream buses if the bus is stuck low. When activated, rise

time accelerators source currents into the 2-wire bus pins

to reduce rise time. Driving the ENABLE pin low restores

all features to their default states. Three address pins

provide 27 distinct addresses.

Insertion and Removal from Backplane

■

±10kV Human Body Model ESD Ruggedness

■

16-Lead (4mm × 5mm) DFN and SSOP Packages

U

APPLICATIO S

The LTC4305 is available in 16-lead (4mm × 5mm) DFN

■

Nested Addressing

and SSOP packages.

■

5V/3.3V Level Translator

, LTC and LT are registered trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners. Patent Pending.

■

Capacitance Buffer/Bus Extender

U

TYPICAL APPLICATIO

A Level-Shifting and Nested Addressing Application

2

I C Bus Waveforms

2.5V

3.3V

V

= 3.3V

CC

0.01µF

VBACK = 2.5V

10k 10k 10k

10k

SCLIN

2V/DIV

V

CC

SCL1

SDA1

SCLIN

MICRO-

CONTROLLER

SFP

MODULE #1

VCARD1 = 3.3V

SDAIN

ALERT

SCL1

2V/DIV

ALERT1

ADDRESS = 1111 000

5V

LTC4305

ADR2

VCARD2 = 5V

SCL2

2V/DIV

10k

ADR1

ADR0

GND

SCL2

SDA2

SFP

MODULE #2

4305 TA01b

500ns/DIV

ALERT2

4305 TA01

ADDRESS = 1111 000

ADDRESS = 1000 100

4305f

1

LTC4305

W W

U W

ABSOLUTE AXI U RATI GS ^{(Note 1)}

Supply Voltage (V_CC) ................................... –0.3V to 7V

Input Voltages (ADR0, ADR1, ADR2,

Operating Temperature Range

LTC4305C ............................................... 0°C to 70°C

LTC4305I............................................. –40°C to 85°C

Storage Temperature Range

ENABLE, ALERT1, ALERT2) .................... –0.3V to 7V

Output Voltages (ALERT, READY) ............... –0.3V to 7V

Input/Output Voltages (SDAIN, SCLIN,

DHD Package .................................... –65°C to 125°C

GN Package ....................................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

SCL1, SDA1, SCL2, SDA2) ...................... –0.3V to 7V

Output Sink Current (SDAIN, SCLIN, SCL1,

SDA1, SCL2, SDA2, ALERT, READY) ............... 10mA

GN Package ...................................................... 300°C

U W

U

PACKAGE/ORDER I FOR ATIO

TOP VIEW

ALERT2

ALERT

SDAIN

GND

1

2

3

4

5

6

7

8

16 SCL2

15 SDA2

14 ALERT1

13 SDA1

12 SCL1

11 READY

10 ADR2

1

2

3

4

5

6

7

8

SCL2

16

15

14

13

12

11

10

9

ALERT2

ALERT

SDAIN

GND

SDA2

ALERT1

SDA1

SCL1

17

SCLIN

ENABLE

SCLIN

ENABLE

READY

ADR2

ADR1

V

CC

V

CC

ADRO

9

ADR1

ADR0

DHD PACKAGE

GN PACKAGE

16-LEAD NARROW PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 135°C/W

16-LEAD (4mm × 5mm) PLASTIC DFN

EXPOSED PAD (PIN 17) PCB CONNECTION OPTIONAL

MUST BE CONNECTED TO PCB TO OBTAIN

_JA= 43°C/W OTHERWISE θ_JA= 140°C/W. T_JMAX= 125°C

θ

ORDER PART NUMBER

DHD PART MARKING

ORDER PART NUMBER

GN PART MARKING

LTC4305CDHD

LTC4305IDHD

4305

LTC4305CGN

LTC4305IGN

4305

4305I

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marketing: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The

●

denotes specifications which apply over the full specified temperature

range, otherwise specifications are at T = 25°C. V = 3.3V unless otherwise noted.

A

CC

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Power Supply/Start-Up

V

Input Supply Range

Input Supply Current

●

2.7

5.5

8

V

CC

I

Downstream Connected, V = 5.5V

5.2

mA

CC

SCL Bus Low, SDA Bus High

I

= 0V

Input Supply Current

V

= 0V, V = 5.5V

●

1.25

2.5

2.7

mA

V

CC ENABLE

ENABLE

CC

V

UVLO Upper Threshold Voltage

2.3

UVLOU

UVLO Threshold Hysteresis Voltage

100

175

250

mV

4305f

UVLOHYST

2

LTC4305

ELECTRICAL CHARACTERISTICS

The

●

denotes specifications which apply over the full specified temperature

range, otherwise specifications are at T = 25°C. V = 3.3V unless otherwise noted.

A

CC

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Power Supply/Start-Up

V

ENABLE Falling Threshold Voltage

●

0.8

1.0

60

1.2

V

mV

ns

µA

V

TH EN

EN HYST

PHL EN

PLH EN

IN EN

ENABLE Threshold Hysteresis Voltage

ENABLE Delay, On-Off

t

I

60

ENABLE Delay, Off-On

20

ENABLE Input Leakage Current

READY Pin Logic Low Output Voltage

READY Off State Input Leakage Current

V

= 0V, 5.5V, V = 5.5V

●

0.1

0.18

0

±1

0.4

±1

ENABLE

CC

V

I

= 3mA, V = 2.7V

PULL-UP CC

LOW READY

I

V

= 0V, 5.5V, V = 5.5V

µA

OFF READY

READY

CC

ALERT

V

ALERT Output Low Voltage

I

= 3mA, V = 2.7V

●

0.2

0

0.4

±1

1.2

V

µA

V

ALERT(OL)

OFF, ALERT

IN, ALERT1–2

ALERT

CC

I

ALERT Off State Input Leakage Current

ALERT1–ALERT2 Input Current

V

= 0V, 5.5V

ALERT

= 0V, 5.5V

0

ALERT1–2

V

ALERT1–ALERT2 Pin Input Falling

Threshold Voltages

0.8

1.0

ALERT1–2(IN)

●

V

ALERT1–ALERT2 Pin Input Threshold

Hysteresis Voltages

80

mV

ALERT1–2(HY)

Rise Time Accelerators

V

Initial Slew Requirement to Activate

Rise Time Accelerator Currents

SDAIN, SCLIN, SDA1–2,

SCL1–2 Pins

0.4

0.8

5.5

0.8

1

V/µs

V

SDA,SCL slew

●

V

Rise Time Accelerator DC Threshold Voltage

SDAIN, SCLIN, SDA1–2,

SCL1–2 Pins

0.7

4

RISE,DC

I

Rise Time Accelerator Pull-Up Current

SDAIN, SCLIN, SDA1–2,

SCL1–2 Pins (Note 3)

mA

BOOST

Stuck Low Timeout Circuitry

V

Stuck Low Falling Threshold Voltage

Stuck Low Threshold Hysteresis Voltage

Timeout Time #1

V

= 2.7V, 5.5V

CC

●

0.4

0.52

80

0.64

V

mV

ms

TIMER(L)

TIMER(HYST)

TIMER1

T

TIMSET1,0 = 01

TIMSET1,0 = 10

TIMSET1,0 = 11

●

25

30

35

Timeout Time #2

12.5

6.25

15

17.5

8.75

TIMER2

Timeout Time #3

7.5

TIMER3

Upstream-Downstream Buffers

V

Buffer Offset Voltage

R

= 10k, V = 2.7V, 5.5V (Note 4)

●

25

60

100

mV

OS,BUF

BUS

CC

Upstream Buffer Offset Voltage

V

= 2.7V, R

= 2.7k (Note 4)

●

40

70

80

110

120

150

mV

OS,UP-BUF

CC

BUS

V

= 0V

= 5.5V, R

IN,BUFFER

V

Downstream Buffer Offset Voltage

= 0V

V

= 2.7V, R

= 5.5V, R

= 2.7k (Note 4)

●

60

80

110

140

160

200

mV

OS,DOWN-BUF

CC

BUS

V

IN,BUFFER

Output Low Voltage, V

= 0V

SDA, SCL Pins; I

V

= 4mA,

●

400

mV

OL

IN,BUFFER

SINK

= 3V, 5.5V

CC

Output Low Voltage, V

= 0.2V

SDA, SCL Pins; I

V

= 500µA,

●

320

mV

IN,BUFFER

SINK

= 2.7V, 5.5V

CC

V

Buffer Input Logic Low Voltage

V

= 2.7V, 5.5V

●

0.4

0.8

0.52

1.0

0.64

1.2

±5

V

IL,MAX

THSDA,SCL

LEAK

CC

Downstream SDA, SCL Logic Threshold Voltage

Input Leakage Current

I

SDA, SCL Pins;

= 0 to 5.5V;

µA

V

CC

Buffers Inactive

4305f

3

LTC4305

ELECTRICAL CHARACTERISTICS

The

●

denotes specifications which apply over the full specified temperature

range, otherwise specifications are at T = 25°C. V = 3.3V unless otherwise noted.

A

CC

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

2

I C Interface

V

ADR0–2 Input High Voltage

●

0.75 • V 0.9 • V

CC

V

ADR(H)

CC

ADR0–2 Input Low Voltage

0.1 • V 0.25 • V

CC CC

ADR(L)

I

ADR0–2 Logic Low Input Current

ADR0–2 Logic High Input Current

ADR0–2 Allowed Input Current

ADR0–2 = 0V, V = 5.5V

–30

30

–60

60

–80

80

µA

V

ADR(IN, L)

ADR(IN, H)

ADR,FLOAT

CC

ADR0–2 = V = 5.5V

CC

V

CC

V

CC

= 2.7V, 5.5V (Note 5)

= 5.5V

±5

±13

1.6

30

V

SDAIN, SCLIN Input Falling Threshold Voltages

SDAIN, SCLIN Hysteresis

1.4

1.8

SDAIN,SCLIN(TH)

SDAIN,SCLIN(HY)

SDAIN,SCLIN(OH)

mV

µA

pF

V

I

SDAIN, SCLIN Input Current

SCL, SDA = V

(Note 2)

●

±5

10

CC

C

V

SDA, SCL Input Capacitance

6

IN

SDAIN Output Low Voltage

I

= 4mA, V = 2.7V

0.2

0.4

SDAIN(OL)

SDA

CC

2

I C Interface Timing

f

t

Maximum SCL Clock Frequency

Bus Free Time Between Stop/Start Condition

Hold Time After (Repeated) Start Condition

Repeated Start Condition Set-Up Time

Stop Condition Set-Up Time

Data Hold Time Input

(Note 2)

400

kHz

µs

ns

SCL

0.75

45

1.3

100

0

BUF

HD, STA

SU, STA

SU, STO

HD, DATI

HD, DATO

SU, DAT

f

–30

–25

600

50

0

Data Hold Time Output

300

900

100

300

Data Set-Up Time

SCL, SDA Fall Times

20 + 0.1 •

C

BUS

t

Pulse Width of Spikes Suppressed by the

Input Filter

(Note 2)

50

150

250

ns

SP

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: Guaranteed by design and not subject to test, unless stated

otherwise in the Conditions.

Note 3: The boosted pull-up currents are regulated to prevent excessively

fast edges for light loads. See the Typical Performance Characteristics for

Note 4: When a logic low voltage V

is forced on one side of the

LOW

upstream-downstream buffers, the voltage on the other side is regulated

to a voltage V = V + V is a positive offset voltage. V

OS,DOWN-BUF

LOW2

LOW

OS

is the offset voltage when the LTC4305 is driving the upstream pin (e.g.,

SDAIN) and V is the offset voltage when the LTC4305 is

OS,DOWN-BUF

driving the downstream pin (e.g., SDA1). See the Typical Performance

Characteristics for V_OS,UP-BUFand V_OS,DOWN-BUFas a function of V and

bus pull-up current.

Note 5: When floating, the ADR0–ADR2 pins can tolerate pin leakage

CC

rise time as a function of V and parasitic bus capacitance C

and for

CC

BUS

I

as a function of V and temperature.

BOOST

CC

currents up to I

and still convert the address correctly.

ADR,FLOAT

4305f

4

LTC4305

U W

TYPICAL PERFOR A CE CHARACTERISTICS

(T = 25°C unless otherwise specified.)

A

Buffer Circuitry t

vs Temperature

PHL

Rise Time vs C

vs V

I

CC

vs Temperature

BUS

CC

120

100

80

6

5

4

3

250

200

150

100

50

dV = 0.3V • V TO 0.7V • V

BUS

CC

V

= 5V

CC

R

= 10k

V

= 3.3V

CC

V

CC

= 3.3V

V

= 3.3V

CC

V

= 5V

CC

V

= 5V

CC

60

40

20

0

2

1

0

UPSTREAM CONNECTED TO CHANNEL 1,

SCL BUS LOW, SDA BUS HIGH

0

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

50

100 125

–50 –25

0

25

75

0

200

400

600

800

(pF)

1000

TEMPERATURE (°C)

CAPACITANCE, C

BUS

4305 G01

4305 G03

4305 G02

V

OS,DOWN-BUF

V

vs Bus Pull-Up Current

OS,UP-BUF

180

160

140

120

100

80

300

250

200

150

V

= 3.3V

CC

V

= 3.3V

CC

V

= 5V

CC

V

= 5V

CC

60

100

50

0

40

20

0

3

0

1

2

4

0

1

2

3

4

BUS PULL-UP CURRENT (mA)

4305 G04

4305 G05

Downstream R on Resistance

FET

vs V and Temperature

I

vs Temperature

CC

BOOST

45

40

35

30

25

20

15

10

5

14

12

10

8

V

= 5V

CC

V

= 3.3V

CC

V

= 5V

CC

6

V

= 3.3V

CC

4

2

0

–50 –25

0

25

50

75

100 125

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

4305 G07

4305 G06

4305f

5

LTC4305

U

PI FU CTIO S

ALERT1–ALERT2 (Pins 14, 1): Fault Alert Inputs,

Channels1–2. Devicesoneachofthetwooutputchannels

can pull their respective pin low to indicate that a fault has

occurred. The LTC4305 then pulls the ALERT low to pass

the fault indication on to the host. See the “Operation”

section below for the details of how ALERT is set and

cleared. Connect unused fault alert inputs to V_CC.

V_CC(Pin 7): Power Supply Voltage. Connect a bypass

capacitor of at least 0.01µF directly between V_CCand GND

for best results.

ADR0–ADR2 (Pins 8–10): Three-State Serial Bus

Address Inputs. Each pin may be floated, tied to ground,

or tied to V_CC. There are therefore 27 possible addresses.

See Table 1 in Applications Information section. When the

pins are floated, they can tolerate ±5µA of leakage current

and still convert the address correctly.

ALERT (Pin 2): Fault Alert Output. An open-drain output

that is pulled low when a fault occurs to alert the host

controller. The LTC4305 pulls ALERT low when any of the

ALERT1–ALERT2 pins is low; when the two-wire bus is

stuck low; or when the Connection Requirement bit of

register 2 is low and a master tries to connect to a

downstream channel that is low. See the “Operation”

section below for the details of how ALERT is set and

cleared. The LTC4305 is compatible with the SMBus Alert

Response Address protocol. Connect a 10k resistor to a

power supply voltage to provide the pull-up. Tie to ground

if unused.

READY (Pin 11): Connection Ready Digital Output. An

N-channelMOSFETopen-drainoutputtransistorthatpulls

down when none of the downstream channels is con-

nected to the upstream bus and turns off when one or

more downstream channels is connected to the upstream

bus. Connect a 10k resistor to a power supply voltage to

provide the pull-up. Tie to ground if unused.

SCL1–SCL2 (Pins 12, 16): Serial Bus Clock Outputs

Channels 1–2. Connect pins SCL1–SCL2 to the SCL lines

on the downstream channels 1–2, respectively. It is ac-

ceptable to float any pin that will never be connected to the

upstream bus. Otherwise, an external pull-up resistor or

current source is required on each pin.

SDAIN (Pin 3): Serial Bus Data Input and Output. Connect

this pin to the SDA line on the master side. An external

pull-up resistor or current source is required.

GND (Pin 4): Device Ground.

SDA1–SDA2 (Pins 13, 15): Serial Bus Data Output

Channels1–2. ConnectpinsSDA1–SDA2totheSDAlineson

downstream channels 1–2, respectively. It is acceptable

to float any pin that will never be connected to the

upstream bus. Otherwise, an external pull-up resistor or

current source is required on each pin.

SCLIN (Pin 5): Serial Bus Clock Input. Connect this pin to

the SCL line on the master side. An external pull-up

resistor or current source is required.

ENABLE (Pin 6): Digital Interface Enable and Register

Reset. Driving ENABLE high enables I²C communication

to the LTC4305. Driving ENABLE low disables I²C com-

munication to the LTC4305 and resets the registers to

their default state as shown in the Operations section.

When ENABLE returns high, masters can read and write

the LTC4305 again. If unused, tie ENABLE to V_CC.

Exposed Pad (Pin 17, DHD Package Only): Exposed pad

may be left open or connected to device ground.

4305f

6

LTC4305

W

BLOCK DIAGRA

INACC

OUTACC

UPSTREAM

DOWNSTREAM

BUFFERS

SLEW RATE

DETECTOR

SLEW RATE

DETECTOR

SDA1

SDA2

SDAIN

3

13

15

DOWNSTREAM

1V THRESHOLD

COMPARATORS

INACC

OUT ACC

UPSTREAM

DOWNSTREAM

BUFFERS

2

SLEW RATE

DETECTOR

SLEW RATE

DETECTOR

SCL1

SCL2

SCLIN

5

12

16

STUCK LOW 0.52V

COMPARATORS

READY 11

FET1

FET2

ALERT1

ALERT2

14

1

CONN

FET1

FET2

ALERT

1V THRESHOLD

COMPARATORS

2

+

–

SCLIN

100ns

GLITCH FILTER

1.6V/1.52V

AL1-AL2

STUCK LOW

TIMEOUT

TIMSET1

TIMSET0

SDAIN

+

–

ALERT

2

4

100ns

GLITCH FILTER

CIRCUITRY

FET1

FET2

TIMEOUT_REAL

TIMEOUT_LATCH

ALERT LOGIC

V

CC

CH1CONN-CH2CONN

2

R

CONNECTION

CIRCUITRY

LIM

UVLO

50k

CONN_REQ

C1

2pF

2-WIRE

DIGITAL

INTERFACE

AND

GND

FAILCONN_ATTEMPT

REGISTERS

BUS1_LOG-BUS2_LOG

2

AL1-AL2

+

–

V

7

UVLO

CC

1µs

FILTER

PORB

ADDRESS

FIXED BITS

“10”

2.5V/2.35V

ADR2

ADR1

ADR0

4305 BD

10

9

2

I C ADDR

5

+

–

ENABLE

6

1 OF 27

1.1V/1V

INACC

8

OUTACC

4305f

7

LTC4305

U

OPERATIO

Control Register Bit Definitions

Register 1 (01h)

BIT NAME

Register 0 (00h)

BIT NAME

TYPE* DESCRIPTION

d7 Upstream

Accelerators

Enable

R/W Activates upstream rise time

accelerator currents

d7 Downstream

Connected

R

Indicates if upstream bus is connected

to any downstream buses

0 = upstream bus disconnected from

all downstream buses

1 = upstream bus connected to one or

more downstream buses

0 = upstream rise time accelerator

currents inactive (default)

1 = upstream rise time accelerator

currents active

d6 Downstream

Accelerators

Enable

R/W Activates downstream rise time

accelerator currents

d6 ALERT1 Logic State

d5 ALERT2 Logic State

d4 Reserved

R

Logic state of ALERT1 pin, noninverting

Logic state of ALERT2 pin, noninverting

Not Used

0 = downstream rise time accelerator

currents inactive (default)

1 = downstream rise time accelerator

currents active

d3 Reserved

Not Used

d2 Failed Connection

Attempt

Indicates if an attempt to connect to a

downstream bus failed because the

“Connection Requirement” bit in

Register 2 was low and the

d5-d0 Reserved

R

Not Used

* For Type, “R/W” = Read Write, “R” = Read Only

downstream bus was low

0 = Failed connection attempt occurred

1 = No failed attempts at connection

occurred

d1 Latched Timeout

d0 Timeout Real Time

R

Latched bit indicating if a timeout has

occurred and has not yet been cleared.

0 = no latched timeout

1 = latched timeout

Indicates real-time status of Stuck Low

Timeout Circuitry

0 = no timeout is occurring

1 = timeout is occurring

Note: Masters write to Register 0 to reset the fault circuitry after a fault

has occurred and been resolved. Because Register 0 is Read-Only, no

other functionality is affected.

* For Type, “R/W” = Read Write, “R” = Read Only

4305f

8

LTC4305

U

OPERATIO

Register 2 (02h)

Register 3 (03h)

BIT NAME

TYPE* DESCRIPTION

d7 Reserved

d6 Reserved

R

Not Used

d7 Bus 1 FET State

R/W Sets and indicates state of FET

switches connected to downstream

bus 1

d5 Connection

Requirement

R/W Sets logic requirements for

downstream buses to be connected

to upstream bus

0 = switch open (default)

1 = switch closed

d6 Bus 2 FET State

R/W Sets and indicates state of FET

switches connected to downstream

bus 2

0 = Bus Logic State bits (see register

3) of buses to be connected must be

high for connection to occur (default)

1 = Connect regardless of

0 = switch open (default)

1 = switch closed

downstream logic state

d5 Reserved

R

Not Used

d4 Reserved

R

Not Used

d4 Reserved

d3 Reserved

d3 Bus 1 Logic State

Indicates logic state of downstream

bus 1; only valid when disconnected

from upstream bus

0 = SDA1, SCL1 or both are below 1V

1 = SDA1 and SCL1 are both above

1V

d2 Mass Write Enable

R/W Enable Mass Write Address using

address (1011 110)b

†

0 = Disable Mass Write

1 = Enable Mass Write (default)

d1 Timeout Mode Bit 1 R/W Stuck Low Timeout Set Bit 1**

d0 Timeout Mode Bit 0 R/W Stuck Low Timeout Set Bit 0**

d2 Bus 2 Logic State

R

Indicates logic state of downstream

bus 2; only valid when disconnected

from upstream bus

* For Type, “R/W” = Read Write, “R” = Read Only

**

†

0 = SDA2, SCL2 or both are below 1V

1 = SDA2 and SCL2 are both above

1V

TIMSET1

TIMSET0

TIMEOUT MODE

Timeout Disabled (Default)

Timeout After 30ms

Timeout After 15ms

Timeout After 7.5ms

0

1

0

1

0

1

d1 Reserved

d0 Reserved

R

Not Used

* For Type, “R/W” = Read Write, “R” = Read Only

These bits are meant to give the logic state of disconnected downstream

†

buses to the master, so that the master can choose not to connect to a low

downstream bus. A given bit is a “don’t care” if its associated downstream

bus is already connected to the upstream bus.

4305f

9

LTC4305

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OPERATIO

The LTC4305 is a 2-channel 2-wire bus multiplexer/

switch with bus buffers to provide capacitive isolation

between the upstream bus and downstream buses. Mas-

ters on the upstream 2-wire bus (SDAIN and SCLIN) can

command the LTC4305 to neither, either or both of the 2

downstreambuses.MasterscanalsoprogramtheLTC4305

to disconnect the upstream bus from the downstream

buses if the bus is stuck low.

stuck low. Masters can override this feature by setting the

Connection Requirement Bit of register 2 high. With this

bit high, the LTC4305 executes connection commands

without regard to the logic states of the downstream

channels.

Upon receiving the connection command, the Connection

Circuitry shown in the block diagram will activate the

Upstream-Downstream Buffers under two conditions:

first, the master must be commanding connection to one

ormoredownstreamchannels, andsecond, theremustbe

no stuck low condition (see “Stuck Low Timeout Fault”

discussion that follows). If the connection command is

successful, the Upstream-Downstream Buffer circuitry

passes signals between the upstream bus and the con-

nected downstream buses. The LTC4305 also turns off its

N-channel MOSFET open-drain pull-down on the READY

pin, so that READY can be pulled high by its external pull-

up resistor.

Undervoltage Lockout (UVLO) and ENABLE

Functionality

The LTC4305 contains undervoltage lockout circuitry that

maintains all of its SDA, SCL and ALERT pins in high

impedance states until the device has sufficient V_CCsup-

ply voltage to function properly. It also ignores any

attempts to communicate with it via the 2-wire buses in

thiscondition. WhentheENABLEpinvoltageislow(below

0.8V), all control bits are reset to their default high

impedance states, and the LTC4305 ignores 2-wire bus

commands. However, with ENABLE low, the LTC4305 still

monitors the ALERT1–ALERT2 pin voltages and pulls the

ALERT pin low if any of ALERT1–ALERT2 is low. When

ENABLE is high, devices can read from and write to the

LTC4305.

Upstream-Downstream Buffers

Once the Upstream-Downstream Buffers are activated,

the functionality of the SDAIN and any connected down-

stream SDA pins is identical. A low forced on any con-

nected SDA pin at any time results in all pins being low.

External devices must pull the pin voltages below 0.4V

worst-case with respect to the LTC4305’s ground pin to

ensure proper operation. The SDA pins enter a logic high

state only when all devices on all connected SDA pins

forceahigh. ThesameistrueforSCLINandtheconnected

downstream SCL pins. This important feature ensures

that clock stretching, clock arbitration and the acknowl-

edge protocol always work, regardless of the how the

devices in the system are connected to the LTC4305.

Connection Circuitry

Masters on the upstream SDAIN/SCLIN bus can write to

the Bus 1 FET State and Bus 2 FET State bits of register 3

to connect to any combination of downstream channels.

By default, the Connection Circuitry shown in the block

diagram will only connect to downstream channels whose

corresponding Bus Logic State bits in register 3 are high

at the moment that it receives the connection command.

If the LTC4305 is commanded to connect to multiple

channels at once, it will only connect to the channels that

are high. This prevents the master on the upstream bus

from connnecting to a downstream channel that may be

The Upstream-Downstream Buffers provide capacitive

isolation between SDAIN/SCLIN and the downstream

connected buses. Note that there is no capacitive isolation

between connected downstream buses; they are only

4305f

10

LTC4305

U

OPERATIO

separated by the series combination of their switches’ on

resistances. While neither, either or both downstream

buses may be connected at the same time, logic high

levels are corrupted if both downstream buses are active

and both the V_CCvoltage and one downstream bus pull-up

voltage are larger than the pull-up supply voltage of the

other downstream bus. An example of this issue is shown

in Figure 1. During logic highs, DC current flows from

first, the pin’s voltage is rising at a minimum slew rate of

0.8V/µs; second, the voltages on both the upstream bus

and the connected downstream buses exceed 0.8V.

Note that a downstream bus must be connected to the

upstream bus in order for its rise time accelerator current

to be active. See the Applications Section for choosing a

bus pull-up resistor value to ensure that the rise time

accelerator switches turn on. Do not activate boost cur-

rents on a bus whose pull-up supply voltage V_BUS< V_CC.

Doing so would cause the boost currents to source

current from V_CCinto the V_BUSsupply during rising

edges.

V

_BUS1through the series combination of R1, N1, N2 and

R2 and into V_BUS2, causing the SDA1 voltage to drop and

current to be sourced into V_BUS2. To avoid this problem,

do not activate bus 1 when bus 2 is active.

V

= V

= 5V

BUS1

CC

Downstream Bus Connection Fault

R1

10k

By default, the LTC4305 will only connect to downstream

buses whose SDA and SCL pins are both high (above 1V)

at the moment that it receives the connection command.

In this case, the LTC4305 sets the Failed Connection

Attemptbitofregister0lowandpullstheALERTlowwhen

the master tries to connect to a low downstream bus. Note

that users can write a high to the Connection Requirement

bit of register 2 to program the LTC4305 to connect to

downstream buses regardless of their logic state at the

moment of connection. In this case, the Downstream

Channel Connection Fault never occurs.

SDA1

N1

N2

V

= 2.5V

BUS2

R2

10k

SDA2

4305 F01

Figure 1. Example of Unacceptable Level Shifting

Rise Time Accelerators

The Upstream Accelerators Enable and Downstream Ac-

celerators Enable bits of register 1 activate the upstream

anddownstreamrisetimeaccelerators,respectively.When

activated, the accelerators turn on in a controlled manner

and source current into the pins during positive bus

transitions.

Stuck Low Timeout Fault

The Stuck Low Timeout Circuitry monitors the two com-

mon internal nodes of the downstream SDA and SCL

switches and runs a timer whenever either of the internal

node voltages is below 0.52V. The timer is reset whenever

both internal node voltages are above 0.6V. If the timer

ever reaches the time programmed by Timeout Mode Bits

1 and 0 of register 2, the LTC4305 pulls ALERT low and

When no downstream buses are connected, an upstream

accelerator turns on when its pin voltage exceeds 0.8V

and is rising at a minimum slew rate of 0.8V/µs. When one

or more downstream buses are connected, the accelera-

tor on a given pin turns on when these conditions are met:

4305f

11

LTC4305

U

OPERATIO

ALERT

FAULT ON DISCONNECTED

DOWNSTREAM BUS

disconnects the downstream buses from the upstream

bus by de-biasing the Upstream-Downstream Buffers.

Note that the downstream switches remain in their exist-

ing state. The Timeout Real Time bit of register 0 indicates

thereal-timestatusofthestucklowsituation. TheLatched

Timeout Bit of register 0 is a latched bit that is set high

when a timeout occurs.

DOWNSTREAM BUS

CONNECTION FAULT

V

CC

D

Q

WRITE

REGISTER 0

R

D

FAULT ON CONNECTED

DOWNSTREAM BUS

ADDRESS LTC4305

LTC4305 RESPONDS

TO ARA

STUCK BUS

V

CC

D

Q

WRITE

REGISTER 0

R

D

External Faults on the Downstream Channels

4305 F02

When a slave on downstream channel 1 pulls the ALERT1

pin below 1V, the LTC4305 passes this information to

master on the upstream bus by pulling the ALERT pin low.

The functionality is the same for the slaves on down-

stream channel 2 and the ALERT2 pin. Each channel has

its own dedicated fault bit in Register 0, so that masters

can read Register 0 to determine which channels have

faults.

Figure 2. Setting and Resetting the ALERT Pin

occur on unconnected downstream buses are grouped

together and generate a single signal to drive ALERT. The

StuckLowTimeoutFaulthasitsowndedicatedpathwayto

ALERT; however, once a stuck low occurs, another one

will not occur until the first one is cleared. For these

reasons, once the master has established the LTC4305 as

the source of the fault, it should read register 0 to deter-

mine the specific problem, take action to solve the prob-

lem, and clear the fault promptly. All faults are cleared by

writing a dummy databyte to register 0, which is a read-

only register.

ALERT Functionality and Fault Resolution

Whenafaultoccurs,theLTC4305pullstheALERTpinlow,

as described previously. The procedure for resolving

faults depends on the type of fault. If a master on the

upstream bus is communicating with devices on a down-

streambusviatheupstream-downstreambuffercircuitry—

channel 1, for example—and a device on this bus pulls the

ALERT1 pin low, the LTC4305 acts transparently, and the

master communicates directly with the device that caused

the fault via the Upstream-Downstream Buffer circuitry to

resolve the fault.

For example, assume that a fault occurs, the master sends

out the ARA, and the LTC4305 successfully writes

its address onto SDAIN and releases its ALERT pin. The

master reads register 0 and learns that the ALERT2 logic

state bit is low. The master now knows that a device on

downstream bus 2 has a fault and writes to register 3 to

connect to bus 2, so that it can communicate with the

source of the fault. At this point, the master writes to

register 0 to clear the fault.

In all other cases, the LTC4305 communicates with the

mastertoresolvethefault.Afterthemasterbroadcaststhe

Alert Response Address (ARA), the LTC4305 will respond

with its address on the SDAIN line and release the ALERT

pin. The ALERT line will also be released if the LTC4305 is

addressed by the master.

I²C Device Addressing

Twenty-seven distinct bus addresses are configurable

using the three state ADR0, ADR1 and ADR2 pins. Table

1 shows the correspondence between pin states and

addresses. Note that address bits a6 and a5 are internally

configured to 1 and 0, respectively. In addition, the

LTC4305 responds to two special addresses. Address

(1011 110) is a mass write used to write all LTC4305’s,

The ALERT signal will not be pulled low again until a

different type of fault has occurred or the original fault is

clearedandhasoccurredagain. Figure2showsthedetails

of how the fault latches and ALERT pin are set and reset.

The Downstream Bus Connection Fault and faults that

4305f

12

LTC4305

U

OPERATIO

regardless of their individual address settings. The mass

write can be masked by setting the mass write enable bit

of register 2 to zero. Address (0001 100) is the SMBus

Alert Response Address. Figure 3 shows data transfer

over a 2-wire bus.

Glitch Filters

The LTC4305 provides glitch filters on the SDAIN and

SCLIN pins as required by the I²C Fast Mode (400kHz)

Specification. The filters prevent signals of up to 50ns

(minimum) time duration and rail-to-rail voltage magni-

tude from passing into the two-wire bus digital interface

circuitry.

Supported Commands

Users must write to the LTC4305 using the SMBus Write

Byte protocol and read from it using the Read Byte

protocol. During fault resolution, the LTC4305 also

supports the Alert Response Address protocol. The

formats for these protocols are shown in Figure 4. Users

must follow the Write Byte protocol exactly to write to the

LTC4305; if a Repeated Start Bit is issued before a Stop

Bit, the LTC4305 ignores the attempted write, and its

control bits remain in their preexisting state. When users

follow the WriteByte protocol exactly, the new data con-

tained in the Data Byte is written into the register selected

by r1 and r0 on the Stop Bit.

Fall Time Control

Per the I²C Fast Mode (400kHz) Specification, the

two-wire bus digital interface circuitry provides fall time

control when forcing logic lows onto the SDAIN bus. The

fall time always meets the limits:

(20 + 0.1 • C_B) < t_f< 300ns

where t_fis the fall time in ns and C_Bis the equivalent bus

capacitance in pF. Whenever the upstream-downstream

buffer circuitry is active, its output signal will meet the fall

timerequirements,providedthatitsinputsignalmeetsthe

fall time requirements.

SDA

SCL

a6 - a0

1 - 7

d7 - d0

8

9

1 - 7

8

9

1 - 7

8

9

S

P

START

CONDITION

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

STOP

CONDITION

4305 F03

2

Figure 3. Data Transfer Over I C/SMBus

7

1

8

1

8

1

START

10 a4 - a0

WR

ACK

XXXXXX r1 r0

REGISTER

ACK

d7 - d0

ACK

STOP

SLAVE

ADDRESS

S

0

S

0

DATA

BYTE

S

0

WRITE BYTE PROTOCOL

7

1

8

1

7

1

8

1

10 a4 - a0

WR

ACK

XXXXXX r1 r0

REGISTER

ACK

10 a4 - a0

RD

ACK

d7 - d0

ACK

STOP

START

SLAVE

ADDRESS

S

0

S

0

SLAVE

ADDRESS

S

0

DATA

BYTE

M

1

0

1

READ BYTE PROTOCOL

7

1

8

1

0001 100

Rd

ACK DEVICE ADDRESS ACK

P

S

0

M

1

ALERT RESPONSE ADDRESS PROTOCOL

4305 F04

Figure 4. Protocols Accepted by LTC4305

4305f

13

LTC4305

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OPERATIO

2

Table 1. LTC4305 I C Device Addressing

HEX DEVICE

ADDRESS

LTC4305

ADDRESS PINS

DESCRIPTION

BINARY DEVICE ADDRESS

h

a6

1

0

1

a5

0

a4

1

0

1

a3

1

0

1

0

1

a2

1

0

1

0

1

0

1

0

a1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

a0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

R/W

0

ADR2

X

ADR1

X

ADR0

X

Mass Write

BC

19

Alert Response

1

X

0

1

80

X

L

NC

H

L

82

L

NC

H

2

84

L

NC

L

3

86

L

4

88

L

5

8A

8C

8E

L

H

6

L

NC

H

7

L

8

90

NC

H

NC

H

L

9

92

NC

H

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

94

NC

L

96

98

L

9A

9C

9E

H

L

NC

H

L

A0

A2

A4

A6

A8

AA

AC

AE

B0

B2

B4

NC

H

L

H

NC

H

NC

L

H

L

H

L

NC

H

L

H

L

H

L

NC

H

L

4305f

14

LTC4305

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APPLICATIO S I FOR ATIO

For larger bus capacitances, refer to equation (1) below.

The LTC4305 works with capacitive loads up to 2nF.

Design Example

A typical LTC4305 application circuit is shown in Figure 5.

Thecircuitillustratesthelevel-shifting,multiplexer/switch

and capacitance buffering features of the LTC4305. In this

application, the LTC4305 V_CCvoltage and downstream

bus 1 are powered from 3.3V, downstream bus 2 is

powered from 5V, and the upstream bus is powered from

2.5V. The following sections describe a methodology for

choosing the external components in Figure 5.

Assume in Figure 5 that the total parasitic bus capacitance

on SDA1 due to trace and device capacitance is 100pF. To

ensure that the boost currents are active during rising

edges, the pull-up resistor must be strong enough to

cause the SDA1 pin voltage to rise at a rate of 0.8V/µs as

the pin voltage is rising above 0.8V. The equation is:

⎧

⎫

⎬

⎭

ns

V

⎡

⎤

(V_BUSMIN– 0.8V) • 1250

⎨

⎢

⎣

⎥

⎦

SDA, SCL Pull-Up Resistor Selection

⎩

(1)

R_{PULL−UP,MAX}kΩ =

[

]

C_BUSpF

[

]

The pull-up resistors on the SDA and SCL pins must be

strong enough to provide a minimum of 100µA pull-up

current, per the SMBus Specification. In most systems,

the required minimum strength of the pull-up resistors is

determined by the minimum slew requirement to guaran-

tee that the LTC4305’s rise time accelerators are activated

during rising edges. At the same time, the pull-up value

should be kept low to maximize the logic low noise margin

and minimize the offset voltage of the Upstream-Down-

stream Buffer circuitry. The LTC4305 is designed to

function for a maximum DC pull-up current of 4mA. If

multipledownstreamchannelsareactiveatthesametime,

this means that the sum total of the pull-up currents from

these channels must be less than 4mA. At supply voltages

of 2.7V and 5.5V, pull-up resistor values of 10k work well

for capacitive loads up to 215pF and 420pF, respectively.

where V_BUSMINis the minimum operating pull-up supply

voltage, and C_BUSis the bus parasitic capacitance. In our

example, V_BUS1= V_CC= 3.3V, and assuming ±10% supply

tolerance, V_BUS1MIN= 2.97V. With C_BUS= 100pF,

R_PULL-UP,MAX= 27.1kΩ. Therefore, we must choose a

pull-up resistor smaller (i.e., stronger pull-up) than 27.1k,

so a 10k resistor works fine.

ALERT and READY Component Selection

The pull-up resistors on the ALERT and READY pins must

provide a maximum pull-up current of 3mA, so that the

LTC4305 is capable of holding the pins at logic low

voltages below 0.4V.

V

BACK

= 2.5V

V

CC

= V

BUS1

= 3.3V

C1

0.01µF

R1

10k

R2

10k

R3

10k

R4

10k

R5

10k

R6

10k

7

5

3

2

V

CC

SCLIN

SDAIN

ALERT

12

MICRO-

SCL1

SDA1

CONTROLLER

13

14

SFP

MODULE #1

ALERT1

ADDRESS = 1111 000

= 5V

V

BUS2

LTC4305

R7

10k

R8

10k

R9

10k

10

9

ADR2

ADR1

ADR0

GND

16

15

1

SCL2

SDA2

8

SFP

MODULE #2

4

ALERT2

ADDRESS = 1111 001

ADDRESS = 1000 100

4305 F05

Figure 5. A Level Shifting Circuit

4305f

15

LTC4305

U

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APPLICATIO S I FOR ATIO

Level Shifting Considerations

from the ENABLE pin and make the ENABLE pin the

shortestpinonthecardconnector, sothattheENABLEpin

remains at a constant logic low while all other pins are

connecting. This ensures that the LTC4305 remains in its

default high impedance state and ignores connection

transients on its SDAIN and SCLIN pins until they have

established solid contact with the backplane 2-wire bus.

In addition, make sure that the ALERT card connector pin

is shorter than the V_CCpin, so that V_CCestablishes solid

contact with the I/O card pull-up supply pin and powers

the pull-up resistors on ALERT1–ALERT2 before ALERT

makes contact.

In Figure 5, the LTC4305 V_CCvoltage is less than or equal

to both of the downstream bus pull-up voltages, so both

downstream buses can be active at the same time. Like-

wise, the rise time accelerators can be turned on for the

downstream buses, but must never be activated on SCLIN

and SDAIN, because doing so would result in significant

current flow from V_CCto V_BACKduring rising edges.

Other Application Circuits

Figure 6 illustrates how the LTC4305 can be used to

expand the number of devices in a system by using nested

addressing. Each I/O card contains a temperature sensor

having device address 1001 000. If both I/O cards were

plugged directly into the backplane, the two sensors

would require two unique addresses. However, if masters

use the LTC4305 in multiplexer mode, where only one

downstream channel is connected at a time, then each

I/O card can have a device with address 1001 000 and no

problems will occur.

Figure 8 illustrates an alternate SDA and SCL hot-

swapping technique, where the LTC4305 is located on the

backplane and an I/O card plugs into downstream channel

2. BeforepluggingandunpluggingtheI/Ocard, makesure

thatchannel2’sdownstreamswitchisopen,sothatitdoes

not disturb any 2-wire transaction that may be occurring

at the moment of connection/disconnection. Note that

pull-up resistor R10 on ALERT2 should be located on the

backplane and not the I/O card to ensure proper operation

of the LTC4305 when the I/O card is not present. The pull-

up resistors on SCL2 and SDA2—R8 and R9, respec-

tively—may be located on the I/O card, provided that

downstream bus 2 is never activated when the I/O card is

notpresent.Otherwise,locateR8andR9onthebackplane.

Figures 7 and 8 show two different methods for hot-

swapping I/O cards onto a live two-wire bus using the

LTC4305. The circuitry of Figure 7 consists of an LTC4305

residing on the edge of an I/O card having two separate

downstream buses. Connect a 200k resistor to ground

V

CC

C1

0.01µF

R1

10k

R2

10k

R3

10k

R4

10k

R5

10k

R6

10k

R7

10k

7

V

5

CC

SCLIN

MICRO-

CONTROLLER

3

6

12

13

14

SDAIN

SCL1

SDA1

TEMPERATURE

SENSOR

ENABLE

2

ALERT1

ALERT

READY

ADR2

ADDRESS = 1001 000

I/O CARD #1

LTC4305

11

10

V

CC

R8

10k

R9

10k

R10

10k

16

15

1

9

SCL2

SDA2

OPEN

ADR1

TEMPERATURE

SENSOR

8

4

ALERT2

ADR0

GND

ADDRESS = 1001 000

I/O CARD #2

4305 F06

ADDRESS = 1010 000

Figure 6. Nested Addressing Application

4305f

16

LTC4305

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W U U

APPLICATIO S I FOR ATIO

V

CC

C1

0.01µF

R1

10k

R2

10k

R5

R6

R7

7

10k

12

V

CC

CARD_SCL1

SCL1

SDA1

13

14

5

3

6

CARD_SDA1

CARD_ALERT1#

SCLIN

MICRO-

CONTROLLER

ALERT1

SDAIN

ENABLE

V

CC

V

BUS2

R8

10k

R9

10k

R10

10k

R4

200k

CC

16

15

1

CARD_SCL2

SCL2

SDA2

R3

10k

CARD_SDA2

CARD_ALERT2#

2

ALERT

ALERT2

LTC4305

V

CC

R11

10k

10

9

11

READY

ADR2

ADR1

ADR0

GND

OPEN

8

4

4305 F07

BACKPLANE

CONNECTOR

CARD

CONNECTOR

ADDRESS = 1010 000

Figure 7. Hot-Swapping Application

4305f

17

LTC4305

U

PACKAGE DESCRIPTIO

DHD Package

16-Lead Plastic DFN (4mm x 5mm)

(Reference LTC DWG # 05-08-1707)

0.70 ±0.05

4.50 ±0.05

3.10 ±0.05

2.44 ±0.05

(2 SIDES)

PACKAGE

OUTLINE

0.25 ± 0.05

0.50 BSC

4.34 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

R = 0.115

TYP

0.40 ± 0.10

5.00 ±0.10

(2 SIDES)

9

16

R = 0.20

TYP

4.00 ±0.10 2.44 ± 0.10

(2 SIDES)

PIN 1

TOP MARK

(SEE NOTE 6)

PIN 1

NOTCH

(DHD16) DFN 0504

8

1

0.25 ± 0.05

0.75 ±0.05

0.200 REF

0.50 BSC

4.34 ±0.10

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJGD-2) IN JEDEC

PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

4305f

18

LTC4305

U

PACKAGE DESCRIPTIO

GN Package

16-Lead Narrow Plastic SSOP

(Reference LTC DWG # 05-08-1641)

.189 – .196*

(4.801 – 4.978)

.045 ±.005

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 ± .0015

.0250 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 ± .004

(0.38 ± 0.10)

× 45°

.0532 – .0688

(1.35 – 1.75)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

GN16 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

4305f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

19

LTC4305

U

TYPICAL APPLICATIO

V

CC

C1

0.01µF

R1

10k

R2

10k

R3

10k

R4

10k

R5

10k

R6

10k

R7

10k

V

CC

SCLIN

SDAIN

ENABLE

ALERT

READY

SCL1

MICRO-

CONTROLLER

TEMPERATURE

SENSOR

SDA1

ALERT1

LTC4305

V

CC2

V

CC

R8

10k

R9

10k

R10

10k

ADR2

ADR1

ADR0

GND

SCL2

SDA2

OPEN

VOLTAGE

MONITOR

ALERT2

I/O CARD

4305 F08

ADDRESS = 1010 000

Figure 8. Alternate Hot-Swapping Application

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1380/LTC1393

Single-Ended 8-Channel/Differential 4-Channel Analog

Mux with SMBus Interface

Low R : 35Ω Single-Ended/70Ω Differential,

ON

Expandable to 32 Single or 16 Differential Channels

LTC1427-50

Micropower, 10-Bit Current Output DAC

with SMBus Interface

Precision 50µA ± 2.5% Tolerance Over Temperature,

4 Selectable SMBus Addresses, DAC Powers up at Zero or Midscale

LTC1623

Dual High Side Switch Controller with SMBus Interface 8 Selectable Addresses/16-Channel Capability

LTC1663

SMBus Interface 10-Bit Rail-to-Rail Micropower DAC

SMBus Accelerator

DNL < 0.75LSB Max, 5-Lead SOT-23 Package

2

LTC1694/LTC1694-1

Improved SMBus/I C Rise-Time,

Ensures Data Integrity with Multiple SMBus/I C Devices

2

LT1786F

LTC1695

LTC1840

SMBus Controlled CCFL Switching Regulator

1.25A, 200kHz, Floating or Grounded Lamp Configurations

0.75Ω PMOS 180mA Regulator, 6-Bit DAC

2

SMBus/I C Fan Speed Controller in ThinSOT™

2

Dual I C Fan Speed Controller

Two 100µA 8-Bit DACs, Two Tach Inputs, Four GPI0

Isolates Backplane and Card Capacitances

LTC4300A-1/LTC4300A-2 Hot Swappable 2-Wire Bus Buffer

LTC4300A-3

LTC4301

Hot Swappable 2-Wire Bus Buffer

Provides Level Shifting and Enable Functions

Supply Independent Hot Swappable 2-Wire Bus Buffer Supply Independent

LTC4301L

Hot Swappable 2-Wire Bus Buffer

with Low Voltage Level Translation

Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN

LTC4302-1/LTC4302-2

LTC4303/LTC4304

Addressable 2-Wire Bus Buffer

Address Expansion, GPIO, Software Controlled

2

Hot Swappable 2-Wire Bus Buffer with Stuck

Bus Recovery

Provides Automatic Clocking to Free Stuck I C Busses

LTC4306

4-Channel 2-Wire Multiplexer with Capacitance

Buffering

4 Selectable Downstream Buses, Stuck Bus Disconnect, Rise Time

Accelerators, Fault Reporting, ±10kV HBM ESD Tolerance

ThinSOT is a trademark of Linear Technology Corporation.

4305f

LT/LWI/TP 0805 500 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC4305IDHD
厂家：	Linear
描述：	2-Channel, 2-Wire Bus Multiplexer with 双通道， 2线总线多路复用器与复用器开关复用器或开关信号电路光电二极管
文件：	总20页 (文件大小：213K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC4305IDHD [Linear]

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