LTC4306IUFD#TRPBF [Linear]
LTC4306 - 4-Channel, 2-Wire Bus Multiplexer with Capacitance Buffering; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C;型号: | LTC4306IUFD#TRPBF |
厂家: | Linear |
描述: | LTC4306 - 4-Channel, 2-Wire Bus Multiplexer with Capacitance Buffering; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C 复用器 |
文件: | 总20页 (文件大小:256K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC4306
4-Channel,
2-Wire Bus Multiplexer with
Capacitance Buffering
U
FEATURES
DESCRIPTIO
The LTC®4306 is a 4-channel, 2-wire bus multiplexer with
bus buffers to provide capacitive isolation between the
upstream bus and downstream buses. Through software
control,theLTC4306connectstheupstream2-wirebusto
any desired combination of downstream buses. Each
channel can be pulled up to a supply voltage ranging from
2.2V to 5.5V, independent of the LTC4306 supply voltage.
The downstream channels are also provided with
ALERT1-ALERT4 inputs for fault reporting.
■
1:4 2-Wire Multiplexer/Switch
■
Connect SDA and SCL Lines with 2-Wire Bus
Commands
■
Supply Independent Bidirectional Buffer for SDA
and SCL Lines Increases Fan-Out
■
Programmable Disconnect from Stuck Bus
Compatible with I2C and SMBus Standards
■
■
Rise Time Accelerator Circuitry
■
SMBus Compatible ALERT Response Protocol
■
Two General Purpose Inputs-Outputs
Programmable timeout circuitry disconnects the down-
stream buses if the bus is stuck low. When activated, rise
time accelerators source currents into the 2-wire bus pins
to reduce rise time. Driving the ENABLE pin low restores
all features to their default states. Three address pins
provide 27 distinct addresses.
■
Prevents SDA and SCL Corruption During Live Board
Insertion and Removal from Backplane
■
±10kV Human Body Model ESD Ruggedness
■
24-Lead QFN (4mm × 5mm) and SSOP Packages
U
APPLICATIO S
The LTC4306 is available in 24-lead QFN (4mm × 5mm)
■
Nested Addressing
and SSOP packages.
■
5V/3.3V Level Translator
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Patent pending.
■
Capacitance Buffer/Bus Extender
U
TYPICAL APPLICATIO
A Level Shifting and Nested Addressing Application
3.3V
2.5V
2
I C Bus Waveforms
0.01µF
V
= 3.3V
CC
10k
10k 10k 10k
10k 10k
VBACK = 2.5V
V
CC
SCLIN
2V/DIV
SCLIN
SDAIN
ALERT ALERT1
SCL1
SDA1
MICRO-
CONTROLLER
SFP
MODULE 1
VCARD1 = 3.3V
SCL1
2V/DIV
ADDRESS = 1111 000
5V
•
•
•
LTC4306
10k 10k 10k
VCARD4 = 5V
ADR2
ADR1
ADR0 ALERT4
GND
SCL4
SDA4
SCL4
2V/DIV
SFP
MODULE 4
4306 TA01b
ADDRESS = 1111 000
4306 TA01a
500ns/DIV
ADDRESS = 1000 100
4306f
1
LTC4306
W W U W
(Note 1)
ABSOLUTE AXI U RATI GS
Supply Voltage (VCC) ................................... –0.3V to 7V
Input Voltages (ADR0, ADR1, ADR2,
Operating Temperature Range
LTC4306C ............................................... 0°C to 70°C
LTC4306I............................................. –40°C to 85°C
Storage Temperature Range
ENABLE, ALERT1, ALERT2, ALERT3,
ALERT4) .................................................. –0.3V to 7V
Output Voltages (ALERT, READY) ............... –0.3V to 7V
Input/Output Voltages (SDAIN, SCLIN,
SSOP ................................................. –65°C to 150°C
QFN ................................................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
SCL1, SDA1, SCL2, SDA2, SCL3,
SDA3, SCL4, SDA4, GPIO1, GPIO2) ........ –0.3V to 7V
Output Sink Currents (SDAIN, SCLIN, SCL1-4, SDA1-4,
GPI01-2, ALERT, READY)..................................... 10mA
SSOP ................................................................ 300°C
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
ORDER PART
NUMBER
ORDER PART
1
2
ALERT2
SCL2
24
23
22
21
20
19
18
17
16
15
14
13
SCL3
SDA3
NUMBER
24 23 22 21 20
LTC4306CUFD
LTC4306IUFD
LTC4306CGN
LTC4306IGN
3
SDA2
ALERT
SDAIN
GND
ALERT
SDAIN
GND
1
2
3
4
5
6
7
19
18
17
16
15
14
13
ALERT3
ALERT1
SDA1
4
ALERT3
ALERT1
SDA1
5
25
6
SCLIN
ENABLE
SCL1
SCLIN
ENABLE
SCL4
7
SCL1
V
CC
SDA4
8
SCL4
V
CC
ALERT4
READY
UF PART MARKING*
4306
9
SDA4
ALERT4
GPI01
GPI02
ADR0
8
9 10 11 12
10
11
12
READY
ADR2
ADR1
UFD PACKAGE
24-LEAD (4mm × 5mm) PLASTIC QFN
GN PACKAGE
EXPOSED PAD (PIN 25), PCB CONNECTION OPTIONAL
MUST BE CONNECTED TO THE PCB TO OBTAIN
JA = 43°C/W OTHERWISE θJA = 140°C/W. TJMAX = 125°C
24-LEAD PLASTIC SSOP
θ
TJMAX = 125°C, θJA = 85°C/W
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications which apply over the full specified temperature
range, otherwise specifications are at T = 25°C. V = 3.3V unless otherwise noted.
A
CC
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply/Start-Up
V
Input Supply Range
Input Supply Current
●
●
2.7
5.5
8
V
CC
I
Downstream Connected, SCL Bus Low,
5.2
mA
CC
SDA Bus High, V = 5.5V
CC
I
= 0V Input Supply Current
V
= 0V, V = 5.5V
●
●
1.25
2.5
2.5
2.7
mA
V
CC ENABLE
ENABLE
CC
V
UVLO Upper Threshold Voltage
2.3
UVLOU
4306f
2
LTC4306
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications which apply over the full specified temperature
range, otherwise specifications are at T = 25°C. V = 3.3V unless otherwise noted.
A
CC
SYMBOL
PARAMETER
CONDITIONS
MIN
100
0.8
TYP
175
1.0
60
MAX
250
1.2
UNITS
mV
V
V
V
V
UVLO Threshold Hysteresis Voltage
ENABLE Falling Threshold Voltage
ENABLE Threshold Hysteresis Voltage
ENABLE Delay, On-Off
●
●
UVLOHYST
TH EN
mV
ns
ENHYST
PHLEN
PLHEN
INEN
t
t
I
60
ENABLE Delay, Off-On
20
ns
ENABLE Input Leakage Current
READY Pin Logic Low Output Voltage
READY Off State Input Leakage Current
V
= 0V, 5.5V, V = 5.5V
●
●
●
0
±1
0.4
±1
µA
V
ENABLE
CC
V
I
= 3mA, V = 2.7V
0.18
0
LOWREADY
OFFREADY
PULL-UP
CC
I
V
= 0V, 5.5V, V = 5.5V
µA
READY
CC
Upstream-Downstream Buffers
V
V
Buffer Offset Voltage
R
= 10k, V = 2.7V, 5.5V (Note 4)
●
25
60
100
mV
OS,BUF
BUS
CC
Upstream Buffer Offset Voltage
V
CC
V
CC
= 2.7V, R
= 2.7k (Note 4)
= 2.7k (Note 4)
●
●
40
70
80
110
120
150
mV
mV
OS,UP-BUF
BUS
BUS
V
= 0V
= 5.5V, R
IN, BUFFER
V
V
Downstream Buffer Offset Voltage
= 0V
V
V
= 2.7V, R
= 5.5V, R
= 2.7k (Note 4)
= 2.7k (Note 4)
●
●
60
80
110
140
160
200
mV
mV
OS,DOWN-BUF
OL
CC
CC
BUS
BUS
V
IN, BUFFER
Output Low Voltage, V
= 0V
SDA, SCL Pins; I
= 4mA,
●
400
mV
IN,BUFFER
SINK
V
CC
= 3V, 5.5V
Output Low Voltage, V
= 0.2V
SDA, SCL Pins; I
= 500µA,
●
320
mV
IN,BUFFER
SINK
V
CC
= 2.7V, 5.5V
V
V
Buffer Input Logic Low Voltage
V
= 2.7V, 5.5V
●
●
●
0.4
0.8
0.52
1.0
0
0.64
1.2
±5
V
V
IL,MAX
THSDA,SCL
LEAK
CC
Downstream SDA, SCL Logic Threshold Voltage
Input Leakage Current
I
SDA, SCL Pins; V = 0V to 5.5V;
Buffers Inactive
µA
CC
Rise Time Accelerators
V
Minimum Slew Requirement to Activate
Rise Time Accelerator Currents
SDAIN, SCLIN, SDA1-4, SCL1-4 Pins
SDAIN, SCLIN, SDA1-4, SCL1-4 Pins
●
●
0.4
0.8
1
V/µs
SDA,SCL slew
V
Rise Time Accelerator DC Threshold Voltage
Rise Time Accelerator Pull-Up Current
0.7
4
0.8
5.5
V
RISE,DC
BOOST
I
SDAIN, SCLIN, SDA1-4, SCL1-4 Pins
(Note 3)
mA
GPIOs
V
V
V
GPIO Pin Input Threshold
●
●
●
●
0.8
1
1.2
0.4
V
V
GPIO(TH)
GPIO(OL)
GPIO(OH)
GPIO(IN)
GPIO Pin Output Low Voltage
GPIO Pin Output High Voltage
GPIO Pin Input Leakage Current
I
I
= 5mA, V = 2.7V
0.2
GPIO
GPIO
CC
= –200µA, V = 2.7V
V
– 0.3
V
CC
CC
I
V
= 0V, 5.5V, V = 5.5V
0
±1
µA
GPIO
CC
Stuck Low Timeout Circuitry
V
V
Stuck Low Falling Threshold Voltage
Stuck Low Threshold Hysteresis Voltage
Timeout Time #1
V
= 2.7V, 5.5V
CC
●
0.4
0.52
80
0.64
V
mV
ms
ms
ms
TIMER(L)
TIMER(HYST)
TIMER1
T
T
T
TIMSET1,0 = 01
TIMSET1,0 = 10
TIMSET1,0 = 11
●
●
●
25
30
35
Timeout Time #2
12.5
6.25
15
17.5
8.75
TIMER2
Timeout Time #3
7.5
TIMER3
ALERT
V
ALERT Output Low Voltage
I
= 3mA, V = 2.7V
●
●
●
0.2
0
0.4
±1
±1
V
ALERT(OL)
OFF,ALERT
IN,ALERT1-4
ALERT
CC
I
I
ALERT Off State Input Leakage Current
ALERT1-ALERT4 Input Current
V
V
= 0V, 5.5V
µA
ALERT
= 0V, 5.5V
0
µA
4306f
ALERT1-4
3
LTC4306
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications which apply over the full specified temperature
range, otherwise specifications are at T = 25°C. V = 3.3V unless otherwise noted.
A
CC
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
ALERT1-ALERT4 Pin Input Falling
Threshold Voltages
●
0.8
1.0
1.2
V
ALERT1-4(IN)
ALERT1-4(HY)
V
ALERT1-ALERT4 Pin Input Threshold
Hysteresis Voltages
80
mV
2
I C Interface
V
V
ADR0-2 Input High Voltage
ADR0-2 Input Low Voltage
ADR0-2 Logic Low Input Current
●
●
●
0.75 • V 0.9 • V
CC
V
V
ADR(H)
ADR(L)
CC
0.1 • V 0.25 • V
CC
CC
I
ADR0-2 = 0V, V = 5.5V
–30
–60
–80
µA
ADR(IN, L)
CC
I
I
ADRO-2 Allowed Input Current
ADR0-2 Logic High Input Current
V
= 2.7V, 5.5V (Note 5)
CC
●
●
●
±5
30
±13
60
µA
µA
V
ADR(FLOAT)
ADR(IN, H)
ADR0-2 = V = 5.5V
80
CC
V
SDAIN, SCLIN Input Falling Threshold
Voltages
V
= 5.5V
CC
1.4
1.6
1.8
SDAIN,SCLIN(TH)
V
SDAIN, SCLIN Hysteresis
SDAIN, SCLIN Input Current
SDA, SCL Input Capacitance
SDAIN Output Low Voltage
30
0
mV
µA
pF
V
SDAIN,SCLIN(HY)
SDAIN,SCLIN(OH)
I
SCL, SDA = V
(Note 2)
●
●
±5
CC
C
V
6
IN
I
= 4mA, V = 2.7V
0.2
0.4
SDAIN(OL)
SDA
CC
2
I C Interface Timing
f
t
t
t
t
t
t
t
t
Maximum SCL Clock Frequency
(Note 2)
400
kHz
µs
ns
ns
ns
ns
ns
ns
ns
SCL
Bus Free Time Between Stop/Start Condition (Note 2)
0.75
45
1.3
100
0
BUF
Hold Time After (Repeated) Start Condition
Repeated Start Condition Set-up Time
Stop Condition Set-up Time
Data Hold Time Input
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
HD,STA
SU,STA
SU,STO
HD,DATI
HD,DATO
SU,DAT
f
–30
–30
–25
600
50
0
0
Data Hold Time Output
300
900
100
300
Data Set-up Time
SCL, SDA Fall Times
20 + 0.1 •
C
BUS
t
Pulse Width of Spikes Suppressed by the
Input Filter
(Note 2)
50
150
250
ns
SP
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
to a voltage V
= V
+ V , where V is a positive offset voltage.
LOW OS OS
LOW2
V
is the offset voltage when the LTC4306 is driving the upstream
OS,UP-BUF
pin (e.g., SDAIN) and V
LTC4306 is driving the downstream pin (e.g., SDA1). See the Typical
Performance Characteristics for V and V as a
is the offset voltage when the
Note 2: Guaranteed by design and not subject to test.
Note 3: The boosted pull-up currents are regulated to prevent excessively
fast edges for light loads. See the Typical Performance Characteristics for
OS,DOWN-BUF
OS,UP-BUF
OS,DOWN-BUF
function of V and bus pull-up current.
CC
rise time as a function of V and parasitic bus capacitance C
and for
CC
BUS
Note 5: When floating, the ADR0-ADR2 pins can tolerate pin leakage
currents up to I and still convert the address correctly.
I
as a function of V and temperature.
BOOST
CC
ADR(FLOAT)
Note 4: When a logic low voltage, V
, is forced on one side of the
LOW
Upstream-Downstream Buffers, the voltage on the other side is regulated
4306f
4
LTC4306
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(T = 25°C, unless otherwise indicated)
A
Buffer Circuitry t
vs Temperature
PHL
Rise Time vs C
vs V
CC
I
vs Temperature
BUS
CC
6
5
4
3
120
100
80
250
200
150
100
50
dV = 0.3V • V TO 0.7V • V
CC
CC
V
= 5V
CC
R
= 10k
BUS
V
CC
= 3.3V
V
= 3.3V
CC
V
= 3.3V
CC
V
= 5V
CC
V
CC
= 5V
60
2
1
0
40
20
0
UPSTREAM CONNECTED TO CHANNEL 1,
SCL BUS LOW, SDA BUS HIGH
0
50
100 125
50
100 125
–50 –25
0
25
75
–50 –25
0
25
75
0
200
400
600
800
(pF)
1000
TEMPERATURE (°C)
TEMPERATURE (°C)
CAPACITANCE, C
BUS
4306 G03
4306 G01
4306 G02
V
OS,DOWN-BUF
V
vs Bus Pull-Up Current
vs Bus Pull-Up Current
OS,UP-BUF
300
180
160
140
120
250
200
150
V
= 3.3V
CC
V
= 3.3V
CC
100
80
60
40
20
0
V
CC
= 5V
V
= 5V
CC
100
50
0
3
0
1
2
4
0
1
2
3
4
BUS PULL-UP CURRENT (mA)
BUS PULL-UP CURRENT (mA)
4306 G04
4306 G05
Downstream R On Resistance
FET
I
vs Temperature
vs V and Temperature
BOOST
CC
45
40
35
30
25
20
15
10
5
14
12
10
8
V
= 5V
CC
V
= 3.3V
CC
V
= 5V
CC
6
V
= 3.3V
CC
4
2
0
0
–50 –25
0
25
125
50
TEMPERATURE (°C)
100 125
50
75 100
–50 –25
0
25
75
TEMPERATURE (°C)
4306 G06
4306 G07
4306f
5
LTC4306
U
U
U
PI FU CTIO S (GN24 Package/UFD24 Package)
ALERT (Pin 3/Pin 1): Fault Alert Output. An open-drain
output that is pulled low when a fault occurs to alert the
host controller. The LTC4306 pulls ALERT low when any
of the ALERT1-ALERT4 pins is low, when the 2-wire bus
is stuck low, or when the Connection Requirement bit of
Register 2 is low and a master tries to connect to a
downstreamchannelthatislow.SeeOperationsectionfor
the details of how ALERT is set and cleared. The LTC4306
is compatible with the SMBus Alert Response Address
protocol. Connecta10kresistortoapowersupplyvoltage
to provide the pull-up. Tie to ground if unused.
ADR0-ADR2 (Pins 12, 13, 14/Pins 10, 11, 12): Three-
State Serial Bus Address Inputs. Each pin may be floated,
tied to ground or tied to VCC. There are therefore 27
possible addresses. See Table 1 in applications informa-
tion. When the pins are floated, they can tolerate ±5µA of
leakage current and still convert the address correctly.
READY (Pin 15/Pin 13):Connection Ready Digital Output.
An N-channel MOSFET open-drain output transistor that
pulls down when none of the downstream channels is
connected to the upstream bus and turns off when one or
more downstream channels is connected to the upstream
bus. Connect a 10k resistor to a power supply voltage to
provide the pull-up. Tie to ground if unused.
SDAIN (Pin 4/Pin 2): Serial Bus Data Input and Output.
Connect this pin to the SDA line on the master side. An
external pull-up resistor or current source is required.
SCL1-SCL4 (Pins 18, 23, 1, 17/Pins 16, 21, 23, 15):
Serial Bus Clock Outputs Channels 1-4. Connect pins
SCL1-SCL4 to the SCL lines on the downstream
channels 1-4, respectively. It is acceptable to float any pin
that will never be connected to the upstream bus. Other-
wise, an external pull-up resistor or current source is
required on each pin.
GND (Pin 5/Pin 3): Device Ground.
SCLIN (Pin 6/Pin 4): Serial Bus Clock Input. Connect this
pin to the SCL line on the master side. An external pull-up
resistor or current source is required.
ENABLE (Pin 7/Pin 5): Digital Interface Enable and Regis-
ter Reset. Driving ENABLE high enables I2C communica-
tion to the LTC4306. Driving this pin low disables I2C
communicationtotheLTC4306andresetstheregistersto
their default state as shown in the Operation section.
When ENABLE returns high, masters can read and write
the LTC4306 again. If unused, tie ENABLE to VCC.
SDA1-SDA4 (Pins 19, 22, 2, 16/Pins 17, 20, 24, 14):
Serial Bus Data Output Channels 1-4. Connect pins
SDA1-SDA4 to the SDA lines on downstream channels
1-4, respectively. It is acceptable to float any pin that will
never be connected to the upstream bus. Otherwise, an
external pull-up resistor or current source is required on
each pin.
VCC (Pin 8/Pin 6): Power Supply Voltage. Connect a
bypass capacitor of at least 0.01µF directly between VCC
and GND for best results.
ALERT1-ALERT4 (Pins 20, 24, 21, 9/Pins 18, 22,
19, 7): Fault Alert Inputs, Channels 1-4. Devices on each
of the four output channels can pull their respective pin
lowtoindicatethatafaulthasoccurred.TheLTC4306then
pulls the ALERT low to pass the fault indication on to the
host. See Operation section below for the details of how
ALERT is set and cleared. Connect unused fault alert
inputs to VCC.
GPIO1-GPIO2 (Pins 10, 11/Pins 8, 9): General Purpose
Input/Output. These two pins can be used as logic inputs,
open-drain outputs or push-pull outputs. The N-channel
MOSFET pull-down devices are capable of driving LEDs.
Whenusedininputoropen-drainoutputmode, theGPIOs
can be pulled up to a supply voltage ranging from 1.5V to
5.5V independent of the VCC voltage. GPIOs default to a
high impedance open-drain output mode. There are GPIO
configuration and status bits in Register 1 and Register 2.
Float if unused.
ExposedPad(Pin25,UFDPackageOnly):PowerGround.
Exposed Pad may be left open or connected to device
ground.
4306f
6
LTC4306
W
BLOCK DIAGRA
4306f
7
LTC4306
U
OPERATIO
Control Register Bit Definitions
Register 1 (01h)
BIT NAME
Register 0 (00h)
BIT NAME
TYPE* DESCRIPTION
TYPE* DESCRIPTION
d7 Upstream
Accelerators
Enable
R/W Activates upstream rise time
accelerator currents
d7 Downstream
Connected
R
Indicates if upstream bus is connected
to any downstream buses
0 = upstream bus disconnected from
all downstream buses
1 = upstream bus connected to one or
more downstream buses
0 = upstream rise time accelerator
currents inactive (default)
1 = upstream rise time accelerator
currents active
d6 Downstream
Accelerators
Enable
R/W Activates downstream rise time
accelerator currents
d6 ALERT1 Logic State
d5 ALERT2 Logic State
d4 ALERT3 Logic State
d3 ALERT4 Logic State
R
R
R
R
R
Logic state of ALERT1 pin, noninverting
Logic state of ALERT2 pin, noninverting
Logic state of ALERT3 pin, noninverting
Logic state of ALERT4 pin, noninverting
0 = downstream rise time accelerator
currents inactive (default)
1 = downstream rise time accelerator
currents active
d2 Failed Connection
Attempt
Indicates if an attempt to connect to a
downstream bus failed because the
“Connection Requirement” bit in
Register 2 was low and the
d5 GPIO1 Output R/W GPIO1 output driver state,
Driver State noninverting, default = 1
d4 GPIO2 Output R/W GPIO2 output driver state,
downstream bus was low
Driver State
noninverting, default = 1
0 = Failed connection attempt occurred
1 = No failed attempts at connection
occurred
d3-d2 Reserved
R
R
Not Used
d1 GPIO1 Logic
State
Logic state of GPIO1 pin,
noninverting
d1 Latched Timeout
d0 Timeout Real Time
R
R
Latched bit indicating if a timeout has
occurred and has not yet been cleared.
0 = no latched timeout
d0 GPIO2 Logic
State
R
Logic state of GPIO2 pin,
noninverting
1 = latched timeout
* For Type, “R/W” = Read Write, “R” = Read Only
Indicates real-time status of Stuck Low
Timeout Circuitry
0 = no timeout is occurring
1 = timeout is occurring
Note: Masters write to Register 0 to reset the fault circuitry after a fault
has occurred and been resolved. Because Register 0 is Read-Only, no
other functionality is affected.
* For Type, “R/W” = Read Write, “R” = Read Only
4306f
8
LTC4306
U
OPERATIO
Register 2 (02h)
Register 3 (03h)
BIT NAME
BIT NAME
TYPE* DESCRIPTION
TYPE* DESCRIPTION
d7 GPIO1 Mode
Configure
R/W Configures Input/Output mode of
GPIO1
d7 Bus 1 FET State
R/W Sets and indicates state of FET
switches connected to downstream
bus 1
0 = output mode (default)
1 = input mode
0 = switch open (default)
1 = switch closed
d6 GPIO2 Mode
Configure
R/W Configures Input/Output Mode of
GPIO2
d6 Bus 2 FET State
d5 Bus 3 FET State
d4 Bus 4 FET State
d3 Bus 1 Logic State
R/W Sets and indicates state of FET
switches connected to downstream
bus 2
0 = output mode (default)
1 = input mode
0 = switch open (default)
1 = switch closed
d5 Connection
Requirement
R/W Sets logic requirements for
downstream buses to be connected
to upstream bus
R/W Sets and indicates state of FET
switches connected to downstream
bus 3
0 = Bus Logic State bits (see register
3) of buses to be connected must be
high for connection to occur (default)
1 = Connect regardless of
0 = switch open (default)
1 = switch closed
downstream logic state
R/W Sets and indicates state of FET
switches connected to downstream
bus 4
d4 GPIO1 Output
Mode Configure
R/W Configures GPIO1 Output Mode
0 = open-drain pull-down (default)
1 = push-pull
0 = switch open (default)
1 = switch closed
d3 GPIO2 Output
Mode Configure
R/W Configures GPIO2 Output Mode
0 = open-drain pull-down (default)
1 = push-pull
R
R
R
R
Indicates logic state of downstream
bus 1; only valid when disconnected
from upstream bus†
0 = SDA1, SCL1 or both are below 1V
1 = SDA1 and SCL1 are both above
1V
d2 Mass Write Enable R/W Enable Mass Write Address using
address (1011 101)b
0 = Disable Mass Write
1 = Enable Mass Write (default)
d2 Bus 2 Logic State
d1 Bus 3 Logic State
d0 Bus 4 Logic State
Indicates logic state of downstream
bus 2; only valid when disconnected
from upstream bus†
0 = SDA2, SCL2 or both are below 1V
1 = SDA2 and SCL2 are both above
1V
d1 Timeout Mode Bit 1 R/W Stuck Low Timeout Set Bit 1**
d0 Timeout Mode Bit 0 R/W Stuck Low Timeout Set Bit 0**
* For Type, “R/W” = Read Write, “R” = Read Only
**Stuck bus program table
TIMSET1
TIMSET0
TIMEOUT MODE
Timeout Disabled (Default)
Timeout After 30ms
Timeout After 15ms
Timeout After 7.5ms
Indicates logic state of downstream
bus 3; only valid when disconnected
from upstream bus†
0 = SDA3, SCL3 or both are below 1V
1 = SDA3 and SCL3 are both above
1V
0
0
1
1
0
1
0
1
Indicates logic state of downstream
bus 4; only valid when disconnected
from upstream bus†
0 = SDA4, SCL4 or both are below 1V
1 = SDA4 and SCL4 are both above
1V
* For Type, “R/W” = Read Write, “R” = Read Only
† These bits give the logic state of disconnected downstream buses to
the master, so that the master can choose not to connect to a low
downstream bus. A given bit is a “don’t care” if its associated
downstream bus is already connected to the upstream bus.
4306f
9
LTC4306
U
OPERATIO
The LTC4306 is a 4-channel, 2-wire bus multiplexer/
switch with bus buffers to provide capacitive isolation
between the upstream bus and downstream buses. Mas-
ters on the upstream 2-wire bus (SDAIN and SCLIN) can
command the LTC4306 to any combination of the 4
downstreambuses.MasterscanalsoprogramtheLTC4306
to disconnect the upstream bus from the downstream
buses if the bus is stuck low.
commanding connection to one or more downstream
channels, and second, there must be no stuck low
condition (see Stuck Low Timeout Fault discussion). If
the connection command is successful, the Upstream-
Downstream Buffers pass signals between the upstream
busandtheconnecteddownstreambuses. TheLTC4306
also turns off its N-channel MOSFET open-drain pull-
down on the READY pin, so that READY can be pulled
high by its external pull-up resistor.
Undervoltage Lockout (UVLO) and ENABLE
Functionality
Upstream-Downstream Buffers
Once the Upstream-Downstream Buffers are activated,
the functionality of the SDAIN and any connected down-
stream SDA pins is identical. A low forced on any con-
nected SDA pin at any time results in all pins being low.
External devices must pull the pin voltages below 0.4V
worst-case with respect to the LTC4306’s ground pin to
ensure proper operation. The SDA pins enter a logic high
stateonlywhenalldevicesonallconnectedSDApinsforce
a high. The same is true for SCLIN and the connected
downstream SCL pins. This important feature ensures
that clock stretching, clock arbitration and the acknowl-
edge protocol always work, regardless of how the devices
in the system are connected to the LTC4306.
The LTC4306 contains undervoltage lockout circuitry that
maintainsallofitsSDA, SCL, GPIOandALERTpinsinhigh
impedancestatesuntilthedevicehassufficientVCC supply
voltage to function properly. It also ignores any attempts
to communicate with it via the 2-wire buses in this condi-
tion. When the ENABLE pin voltage is low (below 0.8V), all
control bits are reset to their default high impedance
states, and the LTC4306 ignores 2-wire bus commands.
However, with ENABLE low, the LTC4306 still monitors
the ALERT1-ALERT4 pin voltages and pulls the ALERT pin
low if any of ALERT1-ALERT4 is low. When ENABLE is
high, devices can read from and write to the LTC4306.
Connection Circuitry
The Upstream-Downstream Buffers provide capacitive
isolationbetweenSDAIN/SCLINandthedownstreamcon-
nected buses. Note that there is no capacitive isolation
between connected downstream buses; they are only
separated by the series combination of their switches’ on
resistances.
Masters on the upstream SDAIN/SCLIN bus can write to
theBus1FETStatethroughBus4FETStatebitsofregister
3 to connect to any combination of downstream channels
1 to 4. By default, the Connection Circuitry shown in the
Block Diagram will only connect to downstream channels
whosecorrespondingBusLogicStatebitsinregister 3are
high at the moment that it receives the connection com-
mand. If the LTC4306 is commanded to connect to mul-
tiple channels at once, it will only connect to the channels
that are high. Masters can override this feature by setting
the Connection Requirement bit of register 2 high. With
this bit high, the LTC4306 executes connection com-
mands without regard to the logic states of the down-
stream channels.
While any combination of downstream buses may be
connectedatthesametime,logichighlevelsarecorrupted
if multiple downstream buses are active and both the VCC
voltageandoneormoredownstreambuspull-upvoltages
are larger than the pull-up supply voltage for another
downsteam bus. An example of this issue is shown in
Figure 1. During logic highs, DC current flows from VBUS1
through the series combination of R1, N1, N2 and R2 and
into VBUS2, causing the SDA1 voltage to drop and current
to be sourced into VBUS2. To avoid this problem, do not
activate bus 1 or any other downstream bus whose pull-
up voltage is above 2.5V when bus 2 is active.
Upon receiving the connection command, the Connec-
tion Circuitry will activate the Upstream-Downstream
Buffers under two conditions: first, the master must be
4306f
10
LTC4306
U
OPERATIO
V
CC
= V
= 5V
BUS1
channel.NotethatuserscanwriteahightotheConnection
Requirementbitofregister2hightoprogramtheLTC4306
to connect to downstream channels regardless of their
logic state at the moment of connection. In this case, the
downstream channel connection fault never occurs.
R1
SDA1
SDA2
10k
N1
N2
V
= 2.5V
BUS2
R2
10k
Stuck Low Timeout Fault
4306 F01
The stuck low timeout circuitry monitors the two common
internal nodes of the downstream SDA and SCL switches
and runs a timer whenever either of the internal node
voltages is below 0.52V. The timer is reset whenever both
internal node voltages are above 0.6V. If the timer ever
reachesthetimeprogrammedbyTimeoutModeBits1and
0 of register 2, the LTC4306 pulls ALERT low and discon-
nects the downstream bus(es) from the upstream bus by
de-biasing the Upstream-Downstream Buffers. Note that
the downstream switches remain in their existing state.
The Timeout Real-Time bit of register 0 indicates the real-
timestatusofthestucklowsituation.TheLatchedTimeout
Bit of register 0 is a latched bit that is set high when a
timeout occurs.
Figure 1. Example of Unacceptable Level Shifting
Rise Time Accelerators
The Upstream Accelerators Enable and Downstream Ac-
celerators Enable bits of register 1 activate the upstream
and downstream rise time accelerators, respectively.
When activated, the accelerators turn on in a controlled
manner and source current into the pins during positive
bus transitions.
When no downstream buses are connected, an upstream
accelerator turns on when its pin voltage exceeds 0.8V
andisrisingataminimumslewrateof0.8V/µs. Whenone
or more downstream buses are connected, the accelera-
tor on a given pin turns on when these conditions are met:
first, the pin’s voltage is rising at a minimum slew rate of
0.8V/µs; second, the voltages on both the upstream bus
and the connected downstream buses exceed 0.8V.
External Faults on the Downstream Channels
When a slave on downstream bus 1 pulls the ALERT1 pin
below 1V, the LTC4306 passes this information to the
master on the upstream bus by pulling the ALERT pin low.
The same is true for the other three downstream buses.
Each bus has its own dedicated fault bit in Register 0, so
thatmasterscanreadRegister0todeterminewhichbuses
have faults.
Note that a downstream bus’s switch must be closed in
order for its rise time accelerator current to be active. See
the Applications Section for choosing a bus pull-up resis-
tor value to ensure that the rise time accelerator switches
turn on. Do not activate boost currents on a bus whose
pull-up supply voltage VBUS is less than VCC. Doing so
would cause the boost currents to source current from
VCC into the VBUS supply during rising edges.
ALERT Functionality and Fault Resolution
Whenafaultoccurs,theLTC4306pullstheALERTpinlow,
as described previously. The procedure for resolving
faults depends on the type of fault. If a master on the
upstream bus is communicating with devices on a down-
stream bus via the Upstream-Downstream Buffer cir-
cuitry—channel 1, for example—and a device on this bus
pullstheALERT1pinlow, theLTC4306actstransparently,
andthemastercommunicatesdirectlywiththedevicethat
caused the fault via the upstream-downstream buffer
circuitry to resolve the fault.
Downstream Bus Connection Fault
By default, the LTC4306 will only connect to downstream
channels whose SDA and SCL pins are both high (above
1V) at the moment that it receives the connection com-
mand. In this case, the LTC4306 sets the Failed Connec-
tion Attempt bit of register 0 low and pulls the ALERT pin
lowwhenthemastertriestoconnecttoalowdownstream
4306f
11
LTC4306
U
OPERATIO
In all other cases, the LTC4306 communicates with the
mastertoresolvethefault.Afterthemasterbroadcaststhe
Alert Response Address (ARA), the LTC4306 will respond
with its address on the SDAIN line and release the ALERT
pin. The ALERT line will also be released if the LTC4306 is
addressed by the master.
connect to bus 2, so that it can communicate with the
source of the fault. At this point, the master writes to
register 0 to clear the LTC4306 fault register.
I2C Device Addressing
Twenty-seven distinct bus addresses are configurable
using the three state ADR0, ADR1 and ADR2 pins. Table 1
shows the correspondence between pin states and ad-
dresses. Note that address bits a6 and a5 are internally
configuredto1and0respectively.Inaddition,theLTC4306
responds to two special addresses. Address (1011 101) is
a mass write used to write all LTC4306’s, regardless of
their individual address settings. The mass write can be
masked by setting the Mass Write Enable bit of register 2
to zero. Address (0001 100) is the SMBus Alert Response
Address. Figure 3 shows data transfer over a 2-wire bus.
The ALERT signal will not be pulled low again until a
different type of fault has occurred or the original fault is
cleared and it occurs again. Figure 2 shows the details of
how the ALERT pin is set and reset. The downstream bus
connection fault and faults that occur on unconnected
downstream buses are grouped together and generate a
single signal to drive ALERT. The stuck low timeout fault
has its own dedicated pathway to ALERT; however, once
astucklowoccurs,anotheronewillnotoccuruntilthefirst
one is cleared. For these reasons, once the master has
established the LTC4306 as the source of the fault, it
should read register 0 to determine the specific problem,
take action to solve the problem, and clear the fault
promptly. All faults are cleared by writing a dummy data
byte to register 0, which is a read-only register.
Supported Commands
Users must write to the LTC4306 using the SMBus Write
Byte protocol and read from it using the Read Byte
protocol. During fault resolution, the LTC4306 also
supports the Alert Response Address protocol. The
formats for these protocols are shown in Figure 4. Users
must follow the Write Byte protocol exactly to write to the
LTC4306; if a Repeated Start Condition is issued before a
Stop Condition, the LTC4306 ignores the attempted write,
and its control bits remain in their preexisting state. When
For example, assume that a fault occurs, the master sends
out the ARA, and the LTC4306 successfully writes
its address onto SDAIN and releases its ALERT pin. The
master reads register 0 and learns that the ALERT2 logic
state bit is low. The master now knows that a device on
downstream bus 2 has a fault and writes to register 3 to
ALERT
FAULT ON DISCONNECTED
DOWNSTREAM BUS
DOWNSTREAM BUS
CONNECTION FAULT
V
CC
D
Q
FAULT ON CONNECTED
DOWNSTREAM BUS
WRITE
REGISTER 0
R
D
ADDRESS LTC4306
LTC4306 RESPONDS
TO ARA
STUCK BUS
V
CC
D
Q
WRITE
REGISTER 0
R
D
4306 F02
Figure 2. Setting and Resetting the ALERT Pin
4306f
12
LTC4306
U
OPERATIO
2
Table 1. LTC4306 I C Device Addressing
HEX DEVICE
ADDRESS
LTC4306
ADDRESS PINS
DESCRIPTION
BINARY DEVICE ADDRESS
h
a6
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
a5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
a4
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
a3
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
a2
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
a1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
a0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
R/W
0
ADR2
X
ADR1
X
ADR0
X
Mass Write
BA
19
Alert Response
1
X
X
X
0
1
80
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
NC
H
L
82
L
NC
NC
H
2
84
L
NC
NC
L
3
86
L
4
88
L
L
5
8A
8C
8E
L
H
H
6
L
L
NC
H
7
L
L
8
90
NC
NC
NC
NC
NC
NC
NC
NC
H
NC
H
L
9
92
NC
NC
H
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
94
NC
NC
L
96
98
L
9A
9C
9E
H
H
L
NC
H
L
A0
A2
A4
A6
A8
AA
AC
AE
B0
B2
B4
NC
H
L
H
NC
NC
H
H
NC
NC
L
H
H
L
H
H
H
H
L
NC
H
H
L
H
H
L
L
H
L
NC
H
L
users follow the Write Byte protocol exactly, the new data Mode Configure bits in register 2 determine whether the
contained in the Data Byte is written into the register GPIOs are used as inputs or outputs. When the GPIOs are
selected by bits r1 and r0 on the Stop Bit.
used as outputs, the GPIO1 and GPIO2 Output Mode
Configure bits of register 2 configure the GPIO outputs
either as open-drain N-channel MOSFET pull-downs or
push-pull stages.
General Purpose Input/Outputs (GPIOs)
The LTC4306 provides two general purpose input/output
pins (GPIOs) that can be configured as logic inputs, open-
drain outputs or push-pull outputs. The GPIO1 and GPIO2
In push-pull mode, at VCC = 3.3V, the typical pull-up
impedance is 670Ω and the typical pull-down impedance
4306f
13
LTC4306
U
OPERATIO
SDA
SCL
a6-a0
1-7
d7-d0
d7-d0
8
9
1-7
8
9
1-7
8
9
S
P
START
CONDITION
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
STOP
CONDITION
4306 F03
2
Figure 3. Data Transfer Over I C or SMBus
7
1
1
8
1
8
1
1
1
START
10 a4-a0
WR
ACK
XXXXXX r1r0
REGISTER
ACK
d7-d0
ACK
STOP
SLAVE
ADDRESS
S
0
S
0
DATA
BYTE
S
0
0
WRITE BYTE PROTOCOL
7
1
1
8
1
7
1
1
8
1
1
1
1
10 a4-a0
WR
ACK
XXXXXX r1r0
REGISTER
ACK
10 a4-a0
RD
ACK
d7-d0
ACK
STOP
START
START
SLAVE
ADDRESS
S
0
S
0
SLAVE
ADDRESS
S
0
DATA
BYTE
M
1
0
1
READ BYTE PROTOCOL
7
1
1
8
1
1
1
0001 100
RD
ACK DEVICE ADDRESS ACK
P
S
4306 F04
S
0
M
1
1
ALERT RESPONSE ADDRESS PROTOCOL
Figure 4. Protocols Accepted by LTC4306
is 35Ω, making the GPIO pull-downs capable of driving
LEDs. At VCC = 5V, the typical pull-up impedance is 320Ω
and the typical pull-down impedance is 20Ω. In open-
drain output mode, the user provides the logic high by
connecting a pull-up resistor between the GPIO pin and an
external supply voltage. The external supply voltage can
range from 1.5V to 5.5V independent of the VCC voltage.
In input mode, the GPIO input threshold voltage is 1V.
in open-drain output mode and one or more external
devices are connected to the GPIOs. If the LTC4306 is
trying to write a high to a GPIO pin, but the pin’s actual
logic state is low, then the LTC4306 knows that the low is
being forced by an external device.
Glitch Filters
The LTC4306 provides glitch filters on the SDAIN and
SCLIN pins as required by the I2C Fast Mode (400kHz)
Specification. The filters prevent signals of up to 50ns
(minimum) time duration and rail-to-rail voltage
magnitude from passing into the two-wire bus digital
interface circuitry.
The GPIO1 and GPIO2 Logic State bits in register 1
indicate the logic state of the two GPIO pins. The logic-
level threshold voltage for each pin is 1V. The GPIO1 and
GPIO2 Output Driver State bits in register 1 indicate the
logic state that the LTC4306 is attempting to write to the
GPIO pins. This is useful when the GPIOs are being used
4306f
14
LTC4306
U
OPERATIO
Fall Time Control
where tf is the fall time in ns and CB is the equivalent bus
capacitance in pF. Whenever the Upstream-Downstream
Buffer Circuitry is active, its output signal will meet the fall
time requirements, provided that its input signal meets the
fall time requirements.
Per the I2C Fast Mode (400kHz) Specification, the two-
wire bus digital interface circuitry provides fall time con-
trol when forcing logic lows onto the SDAIN bus. The fall
time always meets the limits:
(20 + 0.1 • CB) < tf < 300ns
W U U
U
APPLICATIO S I FOR ATIO
Design Example
the required minimum strength of the pull-up resistors is
determined by the minimum slew requirement to guaran-
tee that the LTC4306’s rise time accelerators are activated
during rising edges. At the same time, the pull-up value
should be kept low to maximize the logic low noise margin
and minimize the offset voltage of the Upstream-Down-
stream Buffer circuitry. The LTC4306 is designed to func-
tion for a maximum DC pull-up current of 4mA. If multiple
downstream channels are active at the same time, this
meansthatthesumtotalofthepull-upcurrentsfromthese
channels must be less than 4mA. At supply voltages of
2.7V and 5.5V, pull-up resistor values of 10k work well for
capacitive loads up to 215pF and 420pF, respectively. For
larger bus capacitances, refer to equation (1) below. The
LTC4306 works with capacitive loads up to 2nF.
A typical LTC4306 application circuit is shown in Figure 5.
Thecircuitillustratesthelevel-shifting,multiplexer/switch
and capacitance buffering features of the LTC4306. In this
application, the LTC4306 VCC voltage and downstream
bus 1 are powered from a 3.3V supply voltage; down-
stream bus 4 is powered from 5V, and the upstream bus
is powered from 2.5V. Channels 2 and 3 are omitted for
simplicity.Thefollowingsectionsdescribeamethodology
for choosing the external components in Figure 5.
SDA, SCL Pull-Up Resistor Selection
The pull-up resistors on the SDA and SCL pins must be
strong enough to provide a minimum of 100µA pull-up
current, per the SMBus Specification. In most systems,
V
= V
= 3.3V
C1
CC
BUS1
V
= 2.5V
BACK
0.01µF
R1
10k
R4
10k
R5
R6
R2
R3
6
10k 10k
10k 10k
V
CC
4
2
1
16
17
18
SCLIN
SDA1N
ALERT ALERT1
SCL1
SDA1
SFP
MODULE 1
MICROCONTROLLER
ADDRESS = 1111 000
= 5V
V
BUS4
LTC4306UFD
GPIO1
R10
1k
D1
8
V
CC
R7
R8
R9
10k
10k 10k
12
11
10
3
15
14
7
ADR2
ADR1
SCL4
SDA4
SFP
MODULE 4
ADR0 ALERT4
GND
ADDRESS = 1111 001
4306 F05
ADDRESS = 1000 100
Figure 5. A Level Shifting Circuit
4306f
15
LTC4306
W U U
U
APPLICATIO S I FOR ATIO
Assume in Figure 5 that the total parasitic bus capacitance
on SDA1 due to trace and device capacitance is 100pF. To
ensure that the boost currents are active during rising
edges, the pull-up resistor must be strong enough to
cause the SDA1 pin voltage to rise at a rate of 0.8V/µs as
the pin voltage is rising above 0.8V. The equation is:
having device address 1001 000. If the four I/O cards were
plugged directly into the backplane, the four sensors
would require four unique addresses. However, if masters
use the LTC4306 in multiplexer mode, where only one
downstream channel is connected at a time, then each
I/O card can have a device with address 1001 000 and no
problems will occur.
⎧
⎫
⎬
⎭
ns
V
⎡
⎤
Figures 7 and 8 show two different methods for hot-
swapping I/O cards onto a live two-wire bus using the
LTC4306. The circuitry of Figure 7 consists of an LTC4306
residing on the edge of an I/O card having four separate
downstream buses. Connect a 200k resistor to ground
from the ENABLE pin and make the ENABLE pin the
shortest pin on the connector, so that the ENABLE pin
remains at a constant logic low while all other pins are
connecting. This ensures that the LTC4306 remains in its
default high impedance state and ignores connection
transients on its SDAIN and SCLIN pins until they have
establishedsolidcontactwiththebackplane2-wirebus.In
addition, make sure that the ALERT connector pin is
shorter than the VCC pin, so that VCC establishes solid
contact with the I/O card pull-up supply pin and powers
the pull-up resistors on ALERT1–ALERT4 before ALERT
makes contact.
(VBUSMIN – 0.8V) • 1250
⎨
⎢
⎣
⎥
⎦
⎩
(1)
RPULL−UP,MAX kΩ =
[
]
CBUS pF
[
]
where VBUSMIN is the minimum operating pull-up supply
voltage, and CBUS is the bus parasitic capacitance. In our
example, VBUS1 = VCC = 3.3V, and assuming ±10% supply
tolerance, VBUS1MIN = 2.97V. With CBUS = 100pF,
RPULL-UP,MAX = 27.1k. Therefore, we must choose a pull-
up resistor smaller (i.e., stronger pull-up) than 27.1k, so
a 10k resistor works fine.
ALERT, READY and GPIO Component Selection
The pull-up resistors on the ALERT and READY pins must
provide a maximum pull-up current of 3mA, so that the
LTC4306iscapableofholdingthepinatlogiclowvoltages
below 0.4V. When choosing LEDs to be driven by the
LTC4306’s GPIO pins, make sure that the required LED
sinking current is less than 5mA, and add a current-
limiting resistor in series with the LED.
Figure 8 illustrates an alternate SDA and SCL hot-swap-
ping technique, where the LTC4306 is located on the
backplane and an I/O card plugs into downstream channel
4. BeforepluggingandunpluggingtheI/Ocard, makesure
thatchannel4’sdownstreamswitchisopen,sothatitdoes
not disturb any 2-wire transaction that may be occurring
at the moment of connection/disconnection. Note that
pull-up resistor, R17, on ALERT4 should be located on the
backplane and not the I/O card to ensure proper operation
of the LTC4306 when the I/O card is not present. The pull-
up resistors on SCL4 and SDA4, R15 and R16 respec-
tively, may be located on the I/O card, provided that
downstream bus 4 is never activated when the I/O card is
not present. Otherwise, locate R15 and R16 on the
backplane.
Level Shifting Considerations
In the design example of Figure 5, the LTC4306 VCC
voltageislessthanorequaltobothofthedownstreambus
pull-up voltages, so buses 1 and 4 can be active at the
same time. Likewise, the rise time accelerators can be
turned on for the downstream buses, but must never be
activated on SCLIN and SDAIN, because doing so would
result in significant current flow from VCC to VBACK during
rising edges.
Other Application Circuits
Figure 6 illustrates how the LTC4306 can be used to
expand the number of devices in a system by using nested
addressing. Each I/O card contains a temperature sensor
4306f
16
LTC4306
W U U
APPLICATIO S I FOR ATIO
U
V
CC
C1
0.01µF
R6
10k
R7
10k
R8
10k
R2
10k
R3
10k
R4
10k
R5
10k
6
16
V
CC
SCL1
SDA1
4
2
5
1
17
18
TEMPERATURE
SENSOR
SCLIN
ALERT1
µP
ADDRESS = 1001 000
SDAIN
ENABLE
ALERT
READY
R9
10k
R10
10k
R11
10k
21
20
22
SCL2
SDA2
TEMPERATURE
SENSOR
13
8
ALERT2
R1
1k
ADDRESS = 1001 000
L
TC4306UFD
LED
GPI01
R12
10k
R13
10k
R14
10k
9
GPI02
23
SCL3
24
19
TEMPERATURE
SENSOR
SDA3
ALERT3
12
11
10
3
ADDRESS = 1001 000
V
ADR2
ADR1
ADR0
GND
CC
OPEN
R15
10k
R16
10k
R17
10k
15
14
7
SCL4
SDA4
TEMPERATURE
SENSOR
ALERT4
ADDRESS = 1001 000
4306 F06
ADDRESS = 1010 000
Figure 6. Nested Addressing Application
4306f
17
LTC4306
W U U
U
APPLICATIO S I FOR ATIO
V
CC
C1
0.01µF
R4
10k
R5
R6
R7
R8
6
10k
10k
10k
10k
16
17
18
V
CC
SCL1
SDA1
CARD_SCL1
CARD_SDA1
CARD_ALERT1
4
2
5
SCLIN
ALERT1
µP
SDAIN
ENABLE
V
BUS2
V
CC
R9
10k
R10
10k
R11
10k
R18
200k
V
21
20
22
CC
SCL2
SDA2
CARD_SCL2
CARD_SDA2
CARD_ALERT2
R3
10k
1
ALERT2
ALERT
LTC4306UFD
R12
10k
R13
10k
R14
10k
23
24
19
SCL3
CARD_SCL3
CARD_SDA3
CARD_ALERT3
SDA3
ALERT3
12
11
10
V
ADR2
ADR1
ADR0
GND
CC
OPEN
R15
10k
R16
10k
R17
10k
15
14
7
SCL4
SDA4
CARD_SCL4
CARD_SDA4
CARD_ALERT4
3
ALERT4
R2
10k
LED
13
8
R1
1k
READY
GPI01
GPI02
9
4306 F07
BACKPLANE
CONNECTOR
CARD
CONNECTOR
ADDRESS = 1010 000
Figure 7. Hot-Swapping Application
4306f
18
LTC4306
U
PACKAGE DESCRIPTIO
UFD Package
24-Lead Plastic QFN (4mm x 5mm)
(Reference LTC DWG # 05-08-1696)
2.65 ± 0.10
PIN 1 NOTCH
R = 0.30 TYP
(2 SIDES)
R = 0.115
TYP
0.75 ± 0.05
4.00 ± 0.10
(2 SIDES)
23 24
0.40 ± 0.05
PIN 1
TOP MARK
(NOTE 6)
0.70 ±0.05
1
2
4.50 ± 0.05
3.10 ± 0.05
2.65 ± 0.05
(2 SIDES)
5.00 ± 0.10
(2 SIDES)
3.65 ± 0.10
(2 SIDES)
PACKAGE
OUTLINE
0.25 ±0.05
(UFD24) QFN 0505
0.25 ± 0.05
0.50 BSC
0.50 BSC
0.200 REF
3.65 ± 0.05
(2 SIDES)
0.00 – 0.05
4.10 ± 0.05
5.50 ± 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
GN Package
24-Lead Plastic SSOP
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
.033
(0.838)
REF
.045 ±.005
24 23 22 21 20 19 18 17 16 15 14 13
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
.254 MIN
.150 – .165
1
2
3
4
5
6
7
8
9 10 11 12
.0165 ± .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
(0.38 ± 0.10)
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
× 45°
.0075 – .0098
(0.19 – 0.25)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
.0250
(0.635)
BSC
GN24 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
4306f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC4306
W U U
U
APPLICATIO S I FOR ATIO
V
= 3.3V
CC
C1
0.01µF
R2
10k
R3
10k
R4
10k
R5
10k
R6
10k
R7
10k
R8
10k
V
CC
SCL1
TEMPERATURE
SENSOR
SCLIN
SDA1
MICRO-
CONTROLLER
ALERT1
SDAIN
ENABLE
ALERT
READY
V
= 5V
CC2
R9
10k
R10
10k
R11
10k
SCL2
SDA2
VOLTAGE
MONITOR
ALERT2
V
CC
LTC4306UFD
GPI01
V
= 2.5V
CC3
R1
1k
LED
R12
10k
R13
10k
R14
10k
GPI02
SCL3
SDA3
TEMPERATURE
SENSOR
ALERT3
ADR2
ADR1
ADR0
GND
V
= 3.3V
CC4
OPEN
R15
10k
R16
10k
R17
10k
SCL4
SDA4
VOLTAGE
MONITOR
ALERT4
4306 F08
I/O CARD
ADDRESS = 1010 000
Figure 8. Downstream Side Hot-Swapping Application
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1380/LTC1393
Single-Ended 8-Channel/Diffierential 4-Channel Analog Low R : 35Ω Single-Ended/70Ω Differential, Expandable to
ON
Mux with SMBus Interface
32 Single or 16 Differential Channels
LTC1427-50
Micropower, 10-Bit Current Output DAC with SMBus
Interface
Precision 50µA ±2.5% Tolerance Over Temperature, 4 Selectable
SMBus Addresses, DAC Powers Up at Zero or Midscale
2
LTC1694/LTC1694-1
SMBus Accelerator
Improved SMBus/I C Rise Time, Ensures Data Integrity with Multiple
2
SMBus/I C Devices
LT®1786F
LTC1695
LTC1840
SMBus Controlled CCFL Switching Regulator
1.25A, 200kHz, Floating or Grounded Lamp Configurations
0.75Ω PMOS 180mA Regulator, 6-Bit DAC
Two 100µA 8-Bit DACs, Two Tach Inputs, Four GPIO
Isolates Backplane and Card Capacitances
TM
2
SMBus/I C Fan Speed Controller in ThinSOT
2
Dual I C Fan Speed Controller
LTC4300A-1/LTC4300A-2 Hot Swappable 2-Wire Bus Buffer
LTC4300A-3
LTC4301
Hot Swappable 2-Wire Bus Buffer
Provides Level Shifting and Enable Functions
Supply Independent Hot Swappable 2-Wire Bus Buffer Supply Independent
LTC4301L
Hot Swappable 2-Wire Bus Buffer with Low Voltage
Level Translation
Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN
LTC4303/LTC4304
LTC4305
How Swappable Bus Buffers with Stuck Bus Recovery
Recover Stuck Buses with Automatic Clocking
2-Channel 2-Wire Multiplexer with Capacitance
Buffering
2 Selectable Downstream Buses, Stuck Bus Disconnect, Rise Time
Accelerators, Fault Reporting, ±10kV HBM ESD Tolerance
ThinSOT is a trademark of Linear Technology Corporation.
4306f
LT/LWI/TP 0805 500 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
相关型号:
LTC4307CDD#PBF
LTC4307 - Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C
Linear
LTC4307CDD-1#PBF
LTC4307-1 - High Definition Multimedia Interface (HDMI) Level-Shifting 2-Wire Bus Buffer; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C
Linear
LTC4307CDD-1#TRPBF
LTC4307-1 - High Definition Multimedia Interface (HDMI) Level-Shifting 2-Wire Bus Buffer; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C
Linear
LTC4307CDD-1-PBF
High Defi nition Multimedia Interface (HDMI) Level- Shifting 2-Wire Bus Buffer
Linear
LTC4307CDD-1-TRPBF
High Defi nition Multimedia Interface (HDMI) Level- Shifting 2-Wire Bus Buffer
Linear
©2020 ICPDF网 联系我们和版权申明