LTC4307CMS8 [Linear]
Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery; 低偏移可热插拔二线式总线缓冲器具有阻塞总线恢复
| 型号： | LTC4307CMS8 |
| 厂家： | 
Linear |
| 描述： | Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery |
| 文件： | 总16页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4307
Low Offset Hot Swappable
2-Wire Bus Buffer with Stuck
Bus Recovery
U
DESCRIPTIO
FEATURES
The LTC®4307 hot swappable, 2-wire bus buffer allows
I/O card insertion into a live backplane without corrup-
tion of the data and clock busses. The LTC4307 provides
bidirectional buffering, keeping the backplane and card
■
Bidirectional Buffer with Stuck Bus Recovery
■
60mV Buffer Offset Independent of Load
■
30ms Stuck Bus Timeout
Compatible with Non-Compliant V I C Devices
2
■
OL
■
Prevents SDA and SCL Corruption During Live
Board Insertion and Removal from Backplane
±±kV ꢀuman Body ꢁodel ꢂSD Protection
Isolates Input SDA and SCL Line from Output
capacitances isolated. Low offset and high V tolerance
OL
allows multiple devices to be cascaded on the clock and
data busses. If SDAOUT or SCLOUT are low for 30ms, the
LTC4307 will automatically break the bus connection. At
this time the LTC4307 automatically generates up to 16
clock pulses on SCLOUT in an attempt to free the bus. A
connection will resume if the stuck bus is cleared.
■
■
■
■
■
■
■
2
2
Compatible with I CTM, I C Fast Mode and SMBus
READY Open-Drain Output
1V Precharge on All SDA and SCL Lines
High Impedance SDA, SCL Pins for V = 0V
CC
During insertion, the SDA and SCL lines are pre-charged
to 1V to minimize bus disturbances. When driven high,
the ENABLE input allows the LTC4307 to connect after a
stop bit or bus idle. Driving ENABLE low breaks the con-
nectionbetweenSDAINandSDAOUT,SCLINandSCLOUT.
READY is an open-drain output which indicates that the
backplane and card sides are connected.
Small 8-Lead (3mm × 3mm) DFN and 8-Lead MSOP
Packages
U
APPLICATIO S
■
Live Board Insertion
■
Servers
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
■
Capacitance Buffer/Bus Extender
RAID Systems
ATCA
All other trademarks are the property of their respective owners.
■
Protected by U.S. Patents, including 7032051, 6356140, 6650174
■
U
TYPICAL APPLICATIO
3.3V
Rising ꢂdge from Asserted Low
1000
0.01μF
10k 10k
2.7k 2.7k
10k 10k
0.01μF
V
CC
V
CC
ENABLE
LTC4307
SCLIN SCLOUT
ENABLE
LTC4307
SCLIN SCLOUT
800
600
400
100k
MICRO-
CONTROLLER
CARD_SCL
CARD_SDA
LOW
OFFSET
SDAOUT
SDAIN
SDAIN SDAOUT
SDAIN SDAOUT
3.3V
10k
3.3V
10k
200
0
READY
GND
READY
GND
4307 TA01a
0
100
200
300
100ns/DIV
400
500
4307 TA01b
600
BACKPLANE
CARD
CARD
CONNECTOR CONNECTOR
4307f
1
LTC4307
W W U W
ABSOLUTE AXI U RATI GS
(Notes 1, 7)
V
to GND ................................................. –0.3V to 6V
Storage Temperature Range
CC
SDAIN, SCLIN, SDAOUT, SCLOUT,
DFN....................................................–65°C to 125°C
MSOP ................................................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
READY, ENABLE.......................................... –0.3V to 6V
Maximum Sink Current (SDAIN, SCLIN, SDAOUT,
SCLOUT, READY).............................................. 50mA
Operating Temperature Range
MSOP ............................................................... 300°C
LTC4307C ................................................ 0°C to 70°C
LTC4307I .............................................–40°C to 85°C
U
W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
ENABLE
SCLOUT
SCLIN
GND
1
2
3
4
8
7
6
5
V
CC
TOP VIEW
LTC4307CDD
LTC4307IDD
LTC4307CMS8
LTC4307IMS8
SDAOUT
SDAIN
ENABLE
SCLOUT
SCLIN
GND
1
2
3
4
8 V
CC
9
7 SDAOUT
6 SDAIN
5 READY
READY
DD PART*
MARKING
MS8 PART*
MARKING
MS8 PACKAGE
8-LEAD PLASTIC MSOP
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
T
= 125°C, θ = 200°C/W
JA
JMAX
T
= 125°C, θ = 43°C/W
JA
EXPOSED PAD (PIN 9) CONNECTION TO GND IS OPTIONAL
JMAX
LBTW
LBTW
LTBTV
LTBTV
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 2±°C. VCC = 3.3V, unless otherwise noted.
SYꢁBOL
PARAꢁꢂTꢂR
CONDITIONS
ꢁIN
TYP
ꢁAX
UNITS
Power Supply
●
●
●
●
●
V
Positive Supply Voltage
Supply Current
2.3
5.5
11
V
mA
μA
V
CC
I
CC
I
SD
V
V
= 5.5V, V
= V = 0V (Note 6)
SDAOUT
8
900
1
CC
SCLOUT
Shutdown Supply Current
Precharge Voltage
= 5.5V, ENABLE = GND, SDA, SCL = 5.5V
1200
1.2
175
2
CC
V
PRE
SDA, SCL Floating
0.8
55
t
Bus Idle Time
95
1.4
0.1
95
10
10
10
μs
V
IDLE
V
ENABLE Threshold
0.8
THR_ENABLE
ENABLE
●
I
t
t
t
t
ENABLE Input Current
ENABLE Delay Off-On
ENABLE Delay On-Off
READY Delay Off-On
READY Delay On-Off
READY Output Low Voltage
READY Off Leakage Current
ENABLE from 0V to V
5
μA
μs
ns
ns
ns
V
CC
V
V
V
V
= 3.3V (Figure 1)
PLH_EN
CC
= 3.3V (Note 3) (Figure 1)
= 3.3V (Note 3) (Figure 1)
= 3.3V (Note 3) (Figure 1)
PHL_EN
CC
PLH_READY
PHL_READY
CC
CC
●
●
V
I
= 3mA, V = 2.3V
0.4
5
OL_READY
OFF_READY
PULLUP
CC
I
V
CC
= READY = 5.5V
0.1
μA
4307f
2
LTC4307
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 2±°C. VCC = 3.3V, unless otherwise noted.
SYꢁBOL PARAꢁꢂTꢂR CONDITIONS
Propagation Delay and Rise-Time Accelerators
ꢁIN
TYP
ꢁAX
UNITS
t
t
t
t
I
SDA/SCL Propagation Delay High to Low
SDA/SCL Propagation Delay Low to High
SDA/SCL Transition Time Low to High
SDA/SCL Transition Time High to Low
Transient Boosted Pull-Up Current
C
V
= 50pF, 2.7k to V on SDA, SCL,
70
10
30
30
8
ns
ns
PHL
LOAD
CC
CC
= 3.3V (Notes 2, 3) (Figure 1)
C
V
= 50pF, 2.7k to V on SDA, SCL,
CC
= 3.3V (Notes 2, 3) (Figure 1)
PLH
LOAD
CC
C
LOAD
= 100pF, 10k to V on SDA, SCL, V
300
300
ns
RISE
CC
CC
= 3.3V (See Notes 3, 4) (Figure 1)
C
LOAD
= 100pF, 10k to V on SDA, SCL, V
ns
FALL
CC
CC
= 3.3V (See Notes 3, 4) (Figure 1)
Positive Transition on SDA, SCL, V = 3.3V
(Note 5)
5
mA
PULLUPAC
CC
Input-Output Connection
●
V
Input-Output Offset Voltage
2.7k to V on SDA, SCL, V = 3.3V,
20
60
100
mV
OS
CC
CC
Driven SDA/SCL = 0.2V
V
V
SDA, SCL Logic Input Threshold Voltage
Rising Edge
(Note 3)
0.45V
0.55V
50
0.65V
V
THR
CC
CC
CC
SDA, SCL Logic Input Threshold Voltage
Hysteresis
mV
HYS
C
IN
Digital Input Capacitance SDAIN, SDAOUT, (Note 3)
SCLIN, SCLOUT
10
pF
●
●
I
Input Leakage Current
Output Low Voltage
SDA, SCL, Pins
5
μA
V
LEAK
V
SDA, SCL Pins, I
Driven SDA/SCL = 0.2V, V = 2.7V
= 4mA,
SINK
0
0.4
OL
CC
●
●
2.7k to V on SDA, SCL, V = 3.3V,
120
160
205
1.2
mV
V
CC
CC
Driven SDA/SCL = 0.1V
V
Buffer Input Logic Low Voltage
V
CC
= 3.3V
ILMAX
Bus Stuck Low Timeout
Bus Stuck Low Timer
●
t
V
CC
= 3.3V, SDAOUT, SCLOUT = 0V
25
30
35
ms
TIMEOUT
Timing Characteristics
2
f
I C Maximum Operating Frequency
(Note 3)
(Note 3)
400
600
kHz
μs
I2C,MAX
BUF
t
Bus Free Time Between Stop and Start
Condition
1.3
t
t
t
t
t
Hold Time After (Repeated) Start Condition (Note 3)
100
0
ns
ns
ns
ns
ns
HD,STA
SU,STA
SU,STO
HD,DATI
SU,DAT
Repeated Start Condition Set-Up Time
Stop Condition Set-Up Time
Data Hold Time Input
(Note 3)
(Note 3)
(Note 3)
(Note 3)
0
0
Data Set-Up Time
100
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: Measure points are 0.3 • V and 0.7 • V .
CC CC
Note ±: I
varies with temperature and V voltage as shown in the
CC
PULLUP
Typical Performance Characteristics section.
Note 6: I test performed with connection circuitry active.
CC
Note 2: See “Propagation Delays” in the Operations section for a
Note 7: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specified.
discussion of t
capacitance.
and t
as a function of pull-up resistance and bus
PHL
PLH
Note 3: Determined by design, not tested in production.
4307f
3
LTC4307
TIMING DIAGRAMS
ꢂNABLꢂ, CONNꢂCT, RꢂADY Timing
t
t
PLH_READY
PHL_READY
t
PHL_EN
t
PLH_EN
ENABLE
CONNECT
READY
4307 TD01
Rising and Falling Propagation Delay and Rise and Fall Times for SDAIN, SDAOUT and SCLIN, SCLOUT
t
t
FALL
RISE
t
t
t
t
FALL
PLH
PHL
RISE
SDAIN/SCLIN
SDAOUT/SCLOUT
4307 TD02
Figure 1. Timing Diagrams
4307f
4
LTC4307
U W
TYPICAL PERFOR A CE CHARACTERISTICS TA = 2±°C, VCC = 3.3V, unless otherwise indicated.
ISD vs Temperature
ICC vs Temperature
IPULLUPAC vs Temperature
20
16
12
8
950
900
850
800
750
700
8.3
8.0
7.7
7.4
V
= 5.5V
CC
V
= 5.5V
CC
V
V
= 5.5V
= 3.3V
CC
CC
V
= 3.3V
= 2.3V
CC
7.1
6.8
V
= 3.3V
CC
CC
V
CC
6.5
6.2
5.9
4
V
= 2.3V
0
0
–50 –25
25
50
75
100
–50 –25
25
50
75
100
–25
0
50
0
–50
75
100
25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4307 G02
4307 G02
4307 G01
Input-Output ꢀigh to Low
Propagation Delay vs COUT
Input-Output ꢀigh to Low
Propagation Delay vs Temperature
130
120
110
100
90
100
80
C
= 50pF
PULLUPIN
IN
R
= R
= 10k
PULLUPOUT
V
= 5.5V
CC
V
= 2.3V
CC
V
= 5.5V
CC
V
= 3.3V
CC
60
40
V
CC
= 3.3V
80
20
0
70
C
= C
PULLUPIN
= 50pF
OUT
IN
R
= R
= 10k
50
PULLUPOUT
60
–50
0
25
75
100
0
200
400
600
(pF)
800
1000
–25
TEMPERATURE (°C)
C
OUT
4307 G04
4307 G07
Connection Circuitry VOUT – VIN
(VOS
Bus Stuck Low Timeout vs VCC
)
34
32
30
28
26
85
75
65
55
45
1
2
3
4
5
6
7
8
9
10
2
3
3.5
V
4
4.5
5
5.5
2.5
R
(kΩ)
(V)
PULLUP
CC
4307 G05
4307 G06
4307f
5
LTC4307
U
U
U
PI FU CTIO S
ꢂNABLꢂ (Pin 1): Connection Enable Input. This is a 1.4V
digital threshold input pin. For normal operation pull or tie
ENABLE high. Driving ENABLE below 0.8V isolates SDAIN
from SDAOUT, SCLIN from SCLOUT and asserts READY
low. A rising edge on ENABLE after a fault has occurred
forces a connection between SDAIN, SDAOUT and SCLIN,
connection sequence described in the Operation section
has not been completed. READY also goes low when the
LTC4307 disconnects the inputs from the outputs due to
thebusbeingstucklowforatleast30ms.READYgoeshigh
when ENABLE is high and a connection is made. Connect
a pull-up resistor, typically 10k, from this pin to V to
CC
SCLOUT. Connect to V if unused.
provide the pull-up. This pin can be floated if unused.
CC
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
an SCL bus segment where stuck bus recovery is needed.
A pull-up resistor should be connected between this pin
SDAIN (Pin 6): Serial Data Input. Connect this pin to an
SDA bus segment that needs to be isolated from stuck
bus problems. A pull-up resistor should be connected
and V .
between this pin and V .
CC
CC
SCLIN (Pin 3): Serial Clock Input. Connect this pin to an
SCL bus segment that needs to be isolated from stuck
bus problems. A pull-up resistor should be connected
SDAOUT (Pin 7): Serial Data Output. Connect this pin
to the SDA bus segment where stuck bus recovery is
needed. A pull-up resistor should be connected between
between this pin and V .
this pin and V .
CC
CC
GND (Pin 4): Device Ground. Connect this pin to a ground
plane for best results.
V
(Pin8):SupplyVoltageInput.Placeabypasscapacitor
CC
of at least 0.01μF close to V for best results.
CC
RꢂADY (Pin ±): Connection READY Status Output. The
READYpinisanopen-drainN-channelMOSFEToutputthat
pulls low when ENABLE is low, or when the start-up and
ꢂxposed Pad (Pin 9, DFN Package Only): Exposed Pad
may be left open or connected to device ground.
4307f
6
LTC4307
W
BLOCK DIAGRA
Low Offset 2-Wire Bus Buffer with Stuck Low Timeout
8mA
8mA
V
8
7
CC
CONNECT
I
I
BOOSTSDA
BOOSTSDA
SDAIN
SDAOUT
100k
6
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
100k
100k
CONNECT
PRECHARGE
PC_CONNECT
PC_CONNECT
CONNECT
8mA
8mA
100k
I
I
BOOSTSCL
BOOSTSCL
SCLIN
SCLOUT
3
2
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
+
CONNECT
0.55V
0.55V
–
CC
30ms
TIMER
+
–
+
–
0.55V
CC
CC
I
I
BOOSTSCL
BOOSTSDA
+
–
LOGIC
0.55V
CC
READY
5
CONNECT
PC_CONNECT
ENABLE
+
–
1
1.4V
GND
95μs
DELAY
CONNECT
4
UVLO
4307 BD
OPERATION
Start-Up
During this time, the 1V precharge circuitry is active and
forces 1V through 100k nominal resistors to the SDA
and SCL pins. Because the I/O card is being plugged
into a live backplane, the voltage on the backplane SDA
When the LTC4307 first receives power on its V pin,
CC
either during power-up or live insertion, it starts in an
undervoltage lockout (UVLO) state, ignoring any activity
and SCL busses may be anywhere between 0V and V .
CC
on the SDA or SCL pins until V rises above 2V (typ).
CC
Precharging the SCL and SDA pins to 1V minimizes the
worst-case voltage differential these pins will see at the
4307f
This is to ensure that the LTC4307 does not try to function
until it has enough voltage to do so.
7
LTC4307
OPERATION
moment of connection, therefore minimizing the amount
of disturbance caused by the I/O card.
Input to Output Offset Voltage
When a logic low voltage, V
, is driven on any of the
LOW1
LTC4307’s data or clock pins, the LTC4307 regulates the
voltage on the opposite data or clock pins to a slightly
Once the LTC4307 comes out of UVLO, it monitors both
thebackplaneandcardsidesforeitherastopbitorbusidle
condition to indicate the completion of data transactions.
When both sides are idle or one side has a stop bit condi-
tion while the other is idle, the input-to-output connection
circuitry is activated, joining the SDA and SCL busses on
the I/O card with those on the backplane. In addition, the
prechargecircuitryisdeactivatedandwillnotbereactivated
higher voltage, typically 60mV above V
. This offset is
LOW1
practically independent of pull-up current (see the Typical
Performance curves).
Propagation Delays
During a rising edge, the rise time on each side is de-
termined by the bus pull-up resistor and the equivalent
capacitance on the line. If the pull-up resistors are the
same, a difference in rise time occurs which is directly
proportional to the difference in capacitance between
the two sides. This effect is displayed in Figure 2 for
unless the V voltage falls below the UVLO threshold.
CC
Connection Circuitry
Oncetheconnectioncircuitryisactivated,thefunctionality
of the SDAIN and SDAOUT pins is identical. A low forced
on either pin at any time results in both pin voltages be-
V = 5.5V and a 10k pull-up resistor on each side (50pF
CC
2
ing low. The LTC4307 is tolerant of I C bus DC logic low
on one side and 150pF on the other). Since the output
side has less capacitance than the input, it rises faster
and the effective propagation delay is negative.
2
voltages up to the 0.3V V I C specification.
CC IL
When the LTC4307 senses a rising edge on the bus, it
deactivates its pull-down devices for bus voltages as low
as 0.48V and activates its accelerators. This methodology
maximizes the effectiveness of the rise time accelerator
circuitryandmaintainscompatibilitywiththeotherdevices
in the LTC4300 bus buffer family. Care must be taken to
ensure that devices participating in clock stretching or
arbitration force logic low voltages below 0.48V at the
LTC4307 inputs.
There is a finite propagation delay through the connec-
tion circuitry for falling waveforms. Figure 3 shows the
falling edge waveforms for the same pull-up resistors and
equivalent capacitance conditions as used in Figure 2.
An external N-channel MOSFET device pulls down the
voltage on the side with 150pF capacitance; the LTC4307
pulls down the voltage on the opposite side with a delay
of 80ns. This delay is always positive and is a function
of supply voltage, temperature and the pull-up resistors
and equivalent bus capacitances on both sides of the bus.
The Typical Performance Characteristics section shows
propagationdelayasafunctionoftemperatureandvoltage
for 10k pull-up resistors and 50pF equivalent capacitance
SDAIN and SDAOUT enter a logic high state only when
all devices on both SDAIN and SDAOUT release high.
The same is true for SCLIN and SCLOUT. This important
feature ensures that clock stretching, clock synchroniza-
tion, arbitration and the acknowledge protocol always
work, regardless of how the devices in the system are
tied to the LTC4307.
on both sides of the part. Also, the t
CC
vs C
curve for
PHL
OUT
V
= 5.5V shows that increasing the capacitance from
50pFto150pFresultsinat increasefrom81nsto91ns.
PHL
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation,
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms as
described here.
Larger output capacitances translate to longer delays (up
to 125ns). Users must quantify the difference in propaga-
tion times for a rising edge versus a falling edge in their
systems and adjust setup and hold times accordingly.
4307f
8
LTC4307
OPERATION
INPUT SIDE
150pF
OUTPUT SIDE
50pF
1V/DIV
OUTPUT SIDE
50pF
INPUT SIDE
150pF
1V/DIV
1V/DIV
1V/DIV
4307 F03
4307 F02
200ns/DIV
200ns/DIV
Figure 2. Input-Output Rising ꢂdge Waveforms
Figure 3. Input-Output Falling ꢂdge Waveforms
Bus Stuck Low Timeout
low. When the pin is driven above 2V, the part waits for
data transactions on both the backplane and card sides to
be complete (as described in the Start-Up section) before
connecting the two sides. At this time the internal pull-
downonREADYreleases.WhenENABLEislow,automatic
clocking is disabled.
When SDAOUT or SCLOUT is low, an internal timer is
started. The timer is only reset by that respective input
going high. If it does not go high within 30ms (typical)
theconnectionbetweenSDAINandSDAOUT,andbetween
SCLIN and SCLOUT is broken. After at least 40μs, the
LTC4307 automatically generates up to 16 clock pulses
at 8.5kHz (typical) on SCLOUT in an attempt to unstick
the bus. When the clock pulses are completed, a stop bit
will be generated on SCLOUT and SDAOUT to reset any
circuity on that bus. When the low SDAOUT or SCLOUT
pin goes high, a connection is enabled waiting for a stop
bit or a bus idle to make a connection.
A rising edge on ENABLE after a bus stuck low condition
hasoccurredforcesaconnectionbetweenSDAIN,SDAOUT,
and SCLIN, SCLOUT even if the bus stuck low condition
has not been cleared. At this time the 30ms timer is reset
but not disabled.
Rise Time Accelerators
Onceconnectionhasbeenestablished,risetimeaccelerator
circuits on all four SDA and SCL pins are enabled. During
positive bus transitions, the rise time accelerators provide
strong, slew-limited pull-up currents that make the bus
voltageriseatarateof100V/μs. Therisetimeaccelerators
significantly improve system reliability in two ways. First,
they provide smooth, controlled transitions during rising
edges for both small and large systems. Because the ac-
celerator pull-up impedance is significantly lower than the
buspull-upresistance,thesystemismuchlesssusceptible
to noise on rising edges. Second, the accelerators allow
userstochooselargebuspull-upresistors,reducingpower
consumption and improving logic low noise margin.
When powering up into a bus stuck low condition, the
connection circuitry joining the SDA and SCL busses on
the I/O card with those on the backplane is not activated
and is only reset when SDAOUT and SCLOUT are high.
30ms after UVLO, automatic clocking takes place as
described above.
RꢂADY Digital Output
This pin provides a digital flag which is low when either
ENABLE is low, the start-up sequence described earlier in
this section has not been completed, or the LTC4307 has
disconnected due to a stuck bus condition. READY goes
high when ENABLE is high and the backplane and card
sides are connected. The pin is driven by an open-drain
pull-down capable of sinking 3mA while holding 0.4V on
For these reasons, it is strongly recommended that users
choose bus pull-up resistors so that the bus will rise on its
own at a rate of at least 0.8V/μs to guarantee activation of
the accelerators. The rise time accelerators are disabled
until the sequence of events described in the start-up sec-
tion has been completed. They are also disabled during
automatic clocking.
the pin. Connect a resistor to V to provide the pull-up.
CC
ꢂNABLꢂ
When the ENABLE pin is driven below 0.8V with respect to
theLTC4307’sground, thebackplanesideisdisconnected
from the card side and the READY pin is internally pulled
4307f
9
LTC4307
APPLICATIONS INFORMATION
Live Insertion and Capacitance Buffering Application
In most applications the LTC4307 will be used with a
staggered connector where V and GND will be long
CC
Figures 4 and 5 illustrate applications of the LTC4307 that
take advantage of the LTC4307’s Hot SwapTM , capacitance
buffering and precharge features. If the I/O cards were
plugged directly into the backplane without the LTC4307
buffer, all of the backplane and card capacitances would
add directly together, making rise-time and fall-time re-
quirements difficult to meet. Placing an LTC4307 on the
edge of each card, however, isolates the card capacitance
from the backplane. For a given I/O card, the LTC4307
drives the capacitance of everything on the card and the
backplanemustdriveonlythecapacitanceoftheLTC4307,
which is less than 10pF.
pins. SDA and SCL are medium length pins to ensure that
the V and GND pins make contact first. This will allow
CC
the precharge circuitry to be activated on SDA and SCL
before they make contact. ENABLE is a short pin that is
pulled down when not connected. This is to ensure that
the connection between the backplane and the card’s data
and clock busses is not is not enabled until the transients
associated with live insertion have settled.
Figure 4 shows the LTC4307 in an application with a stag-
gered connector. The LTC4307 receives its V voltage
CC
from one of the long “early power” pins. Establishing
early power V ensures that the 1V precharge voltage is
Hot Swap is a trademark of Linear Technology Corporation.
CC
present at SDAIN and SCLIN before they make contact.
BACKPLANE
CARD
BACKPLANE
CONNECTOR CONNECTORS
I/O PERIPHERAL CARD 1
V
CC
C1
0.01μF
R1
R2
R3
R5
R6
10k 10k 10k
10k 10k
V
CC
SDAIN
SCLIN
ENABLE
READY
SDA
SCL
ENA1
READY
SDAOUT
SCLOUT
CARD1_SDA
CARD1_SCL
LTC4307
GND
R4
10k
•
•
•
I/O PERIPHERAL CARD N
C2
0.01μF
R8
R9
10k 10k
V
CC
SDAIN
SCLIN
ENABLE
READY
SDAOUT
SCLOUT
CARDn_SDA
CARDn_SCL
LTC4307
GND
ENAn
R7
10k
4307 F04
Figure 4. The LTC4307 in an Application with a Staggered Connector
4307f
10
LTC4307
APPLICATIONS INFORMATION
The ENABLE pin is driven using a short pin. This is to
ensurethataconnectionisnotenableduntilthetransients
associated with live insertion have settled.
a valid logic-low voltage with respect to the ground at one
endofthesystemmayviolatetheallowedV specification
OL
withrespecttothegroundattheotherend. Inaddition, the
connection circuitry offset voltages of the back-to-back
LTC4307s add together, directly contributing to the same
problem.
Figure 5 shows the LTC4307 in an application where all
of the pins have the same length. In this application a
resistor is used to hold the ENABLE pin low during live
insertion, until the backplane control circuitry can enable
the device.
Figure7furtherillustratesarepeaterapplication.Thiscircuit
couldbeusedinanAdvancedTCAsystem.InAdvancedTCA
applications, the bus pull-up resistance on the backplane
is quite small. Since there is no effect on the offset due
to the pull-up impedance, multiple LTC4307 buffers can
be used in a single system. This allows the user to divide
the line and device capacitances into more sections with
buffering and meet rise and fall times.
Repeater/Bus ꢂxtender Applications
Users who wish to connect two 2-wire systems separated
byadistancecandosobyconnectingtwoLTC4307sback-
2
to-back, as shown in Figure 6. The I C specification allows
for 400pF maximum bus capacitance, severely limiting
the length of the bus. The SMBus specification places no
restrictiononbuscapacitance,butthelimitedimpedances
ofdevicesconnectedtothebusrequiresystemstoremain
small if rise time and fall time specifications are to be met.
In this situation, the differential ground voltage between
the two systems may limit the allowed distance, because
The LTC4307 disconnects when both bus I/Os are above
0.48V and rising. In systems with large ground bounce,
if many devices are cascaded, the 0.48V threshold can be
exceeded and the transients associated with the ground
bouncecanappeartobearisingedge.Underthiscondition,
the LTC4307 with inputs above 0.48V may disconnect.
BACKPLANE
CARD
BACKPLANE
CONNECTOR CONNECTORS
I/O PERIPHERAL CARD 1
V
CC
C1
0.01μF
R1
R2
R3
R5
R6
10k 10k 10k
10k 10k
V
CC
SDAIN
SCLIN
ENABLE
READY
CARD1_SDA
CARD1_SCL
SDA
SCL
ENA1
READY
SDAOUT
SCLOUT
LTC4307
GND
R4
10k
•
•
•
I/O PERIPHERAL CARD N
C2
0.01μF
R8
R9
10k 10k
V
CC
SDAIN
SCLIN
ENABLE
READY
CARDn_SDA
CARDn_SCL
SDAOUT
SCLOUT
LTC4307
GND
ENAn
R7
10k
4307 F05
Figure ±. The LTC4307 in an Application Where All the Pins ꢀave the Same Length
4307f
11
LTC4307
APPLICATIONS INFORMATION
Systems with Supply Voltage Droop
millivolts or more. This situation is modeled by a series
resistor in the V line, as shown in Figure 8. For proper
CC
In large 2-wire systems, the V voltages seen by devices
CC
operation, make sure that the V
is ≥ 2.3V.
CC(LTC4307)
at various points in the system can differ by a few hundred
3.3V
C1
0.01μF
C2
0.01μF
R1
R2
R4
R5
R7
R8
R3
10k
R6
10k
10k 10k
10k 10k
10k 10k
V
CC
V
CC
LTC4307
ENABLE
LTC4307
ENABLE
READY
SDAIN
SCLIN
READY
SDAIN
SCLIN
SDA1
SCL1
SDA2
SCL2
SDAOUT
SCLOUT
SDAOUT
SCLOUT
GND
GND
4307 F06
Figure 6. The LTC4307 in a Repeater/Bus ꢂxtender Application Where Two 2-Wire Systems are Separated by a Distance
V
CC
C1
0.01 F
C2
0.01 F
C3
0.01 F
R1
R2
R4
R5
R7
R8
R10 R11
2.7k 2.7k
R3
10k
R6
10k
R9
10k
2.7k 2.7k
2.7k 2.7k
2.7k 2.7k
V
V
CC
V
CC
CC
LTC4307
ENABLE
LTC4307
ENABLE
LTC4307
ENABLE
READY
SDAIN
SCLIN
READY
SDAIN
SCLIN
READY
SDAIN
SCLIN
SDA1
SCL1
SDAOUT
SCLOUT
SDA2
SCL2
SDAOUT
SCLOUT
GND
SDAOUT
SCLOUT
GND
GND
4307 F07
Figure 7. The LTC4307 in a Repeater Application. The LTC4307’s Low Offset Allows Cascading of ꢁultiple Devices
R
DROOP
V
CC(LTC4307)
V
CC(BUS)
C1
0.01μF
R1
R2
R4
R5
R3
10k
10k 10k
10k 10k
V
CC
LTC4307
ENABLE
READY
SDA1
SCL1
READY
SDAIN
SCLIN
SDA2
SCL2
SDAOUT
SCLOUT
GND
4307 F08
Figure 8. System with Voltage Droop
4307f
12
LTC4307
TYPICAL APPLICATIONS
ꢀigh VIL Application
5V
C1
0.01μF
R5
10k
R6
10k
R2
1.8k
R1
1.8k
V
CC
R3
200Ω
ENABLE
SCLIN
SCLOUT
SCL
SDA
TEMPERATURE
SENSOR
R4
200Ω
LTC4307
SDAIN SDAOUT
5V
R7
10k
READY
GND
READY
4307 TA02
Simplified ATCA IPꢁB Application
ATCA BOARD
SHELF MANAGER
–48V
–48V
–48V
DC/DC
DC/DC
3.3V
3.3V
C2
0.01μF
C1
0.01μF
R5
10k
R6
10k
R1
10k
R2
10k
R3
R4
2.7k 2.7k
V
V
V
V
CC
CC
CC
CC
ENABLE
SDAIN
SCLIN
ENABLE
SDAOUT
SDAOUT
LTC4307
SCLOUT
SDAIN
SCLIN
ShMC
IPMC
LTC4307
SCLOUT
IPM
BUS
4307 TA03
(1 OF 2)
4307f
13
LTC4307
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
0.38 0.10
TYP
5
8
0.675 0.05
3.5 0.05
2.15 0.05 (2 SIDES)
1.65 0.05
3.00 0.10
(4 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
(DD8) DFN 1203
4
1
0.25 0.05
0.75 0.05
0.200 REF
0.25 0.05
0.50 BSC
0.50
BSC
2.38 0.05
(2 SIDES)
2.38 0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
4307f
14
LTC4307
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
3.00 0.102
(.118 .004)
(NOTE 3)
0.52
(.0205)
REF
8
7 6 5
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .006)
DETAIL “A”
0.254
0.889 0.127
(.035 .005)
(.010)
0° – 6° TYP
GAUGE PLANE
5.23
1
2
3
4
3.20 – 3.45
(.206)
0.53 0.152
(.021 .006)
(.126 – .136)
MIN
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
0.65
(.0256)
BSC
0.42 0.038
(.0165 .0015)
TYP
SEATING
PLANE
0.22 – 0.38
0.1016 0.0508
RECOMMENDED SOLDER PAD LAYOUT
(.009 – .015)
(.004 .002)
0.65
(.0256)
BSC
TYP
MSOP (MS8) 0307 REV F
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
4307f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC4307
TYPICAL APPLICATION
The LTC4307 in a Repeater Application. The LTC4307’s Low Offset Allows Cascading of ꢁultiple Devices
V
CC
C1
0.01 F
C2
0.01 F
C3
0.01 F
R1
R2
R4
R5
R7
R8
R10 R11
2.7k 2.7k
R3
10k
R6
10k
R9
10k
2.7k 2.7k
2.7k 2.7k
2.7k 2.7k
V
V
CC
V
CC
CC
LTC4307
ENABLE
LTC4307
ENABLE
LTC4307
ENABLE
READY
SDAIN
SCLIN
READY
SDAIN
SCLIN
READY
SDAIN
SCLIN
SDA1
SCL1
SDAOUT
SCLOUT
SDA2
SCL2
SDAOUT
SCLOUT
GND
SDAOUT
SCLOUT
GND
GND
4307 F07
RELATED PARTS
PART NUꢁBꢂR
DꢂSCRIPTION
COꢁꢁꢂNTS
LTC1380/LTC1393
Single-Ended 8-Channel/Differential 4-Channel Analog Low R : 35Ω Single Ended/70Ω Differential, Expandable to 32 Single
ON
MUX with SMBus Interface
or 16 Differential Channels
LTC1427-50
Micropower, 10-Bit Current Output DAC with SMBus
Interface
Precision 50μA 2.5ꢀ Tolerance Over Temperature, Four Selectable
SMBus Addresses, DAC Powers Up at Zero or Midscale
LTC1623
Dual High Side Switch Controller with SMBus Interface Eight Selectable Addresses/16-Channel Capability
LTC1663
SMBus Interface 10-Bit Rail-to-Rail Micropower DAC
SMBus Accelerator
DNL < 0.75LSB Max, 5-Lead SOT-23 Package
2
LTC1694/LTC1694-1
Improved SMBus/I C Rise Time, Ensures Data Integrity with Multiple
2
SMBus/I C Devices
2
LTC1695
LT1786F
LTC1840
SMBus/I C Fan Speed Controller in ThinSOTTM Package 0.75Ω PMOS 180mA Regulator, 6-Bit DAC
SMBus Controlled CCFL Switching Regulator
1.25A, 200kHz Floating or Grounded Lamp Configurations
2
Dual I C Fan Speed Controller
Two 100μA 8-Bit DACs, Two Tach Inputs, Four GPIO
LTC4300A-1/
LTC4300A-2/
LTC4300A-3
Hot Swappable 2-Wire Bus Buffers
LTC4300A-1: Bus Buffer with READY, ACC and ENABLE
LTC4300A-2: Dual Supply Bus Buffer with READY and ACC
LTC4300A-3: Dual Supply Bus Buffer with READY and ENABLE
LTC4301
Supply Independent Hot Swappable 2-Wire Bus Buffer Supply Independent
LTC4301L
Hot Swappable 2-Wire Bus Buffer with Low Voltage
Level Translation
Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN
LTC4302-1/LTC4302-2 Addressable 2-Wire Bus Buffer
Address Expansion, GPIO, Software Controlled
2
LTC4303/LTC4304
Hot Swappable 2-Wire Bus Buffers with Stuck Bus
Recovery
Provides Automatic Clocking to Free Stuck I C Busses
LTC4305/LTC4306
2-/4-Channel, 2-Wire Bus Multiplexers with
Capacitance Buffering
2/4 Selectable Downstream Busses, Stuck Bus Disconnect, Rise Time
Accelerators, Fault Reporting, 10kV HBM ESD Tolerance
ThinSOT is a trademark of Linear Technology Corporation
4307f
LT 0507 • PRINTED IN USA
16 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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