LTC4307IMS8-1#TRPBF [Linear]

LTC4307-1 - High Definition Multimedia Interface (HDMI) Level-Shifting 2-Wire Bus Buffer; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C;


型号：	LTC4307IMS8-1#TRPBF
厂家：	Linear
描述：	LTC4307-1 - High Definition Multimedia Interface (HDMI) Level-Shifting 2-Wire Bus Buffer; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C 驱动光电二极管接口集成电路
文件：	总12页 (文件大小：164K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC4307-1

High Deﬁnition Multimedia

Interface (HDMI) Level-

Shifting 2-Wire Bus Buffer

DESCRIPTIO

FEATURES

■

Bidirectional Buffer for Display Data Channel (DDC)

The LTC4307-1 is a 2-wire bus buffer that provides ca-

pacitance buffering between input and output. The HDMI

speciﬁcation requires that devices have less than 50pF of

inputcapacitanceontheirDDCbuslines.TheLTC4307-1’s

capacitance buffering feature, in conjunction with its

sub-10pF data and clock input capacitance, allows HDMI

components to easily meet the 50pF requirement and

tolerate high capacitance on the internal bus.

■

Compliant with HDMI Speciﬁcation Version 1.3

DDC Capacitance Requirement

■

Level Translation Between 3.3V and 5V

■

5ꢀV Human Body Model ꢁSD ꢂrotection

■

60mV Buffer Offset Independent of Load

■

Compatible with Non-Compliant V I C Devices

■

Isolates Input SDA and SCL Line from Output

Compatible with I C , I C Fast Mode and SMBus

READY Open-Drain Output

The LTC4307-1 also provides level-shifting between 3.3V

and5VsystemstoallowlowervoltageHDMItransmitters,

receivers and EEPROM to interface to the 5V DDC bus.

READY is an open-drain digital output ﬂag that indicates

whether or not the input and output busses are connected

andcaninterfacetotheHDMIhotplugdetect(HPD)signal.

When driven high, the ENABLE digital input allows the

LTC4307-1 to connect after a stop bit or bus idle. Driving

ENABLE low breaks the connection between the input and

output busses.

High Impedance SDA, SCL Pins for V = 0V

Small 8-Lead (3mm × 3mm) DFN and 8-Lead MSOP

Packages

APPLICATIO S

■

HDMI

■

3.3V/5V Level Translation

■

Capacitance Buffer/Bus Extender

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 7032051, 6356140, 6650174

TYPICAL APPLICATIO

Rising ꢁdge from Asserted Low

DVD PLAYER (SOURCE)

TV (SINK)

1000

3.3V

0.1μF

800

EEPROM

1.8k 1.8k

10k

μC

10k

LTC4307-1

600

HDMI

CABLE

LOW

OFFSET

HDMI TX

<50pF

SDAOUT

SDAIN

SCLIN

HDMI RX

SDAOUT

SDAIN

400

SCLOUT

ENABLE

GND

DDC GROUND

200

100

200

300

100ns/DIV

400

500

43071 TA01b

600

43071 TA01a

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LTC4307-1

W W U W

ABSOLUTE AXI U RATI GS

(Notes 1, 6)

to GND ................................................. –0.3V to 6V

Storage Temperature Range

SDAIN, SCLIN, SDAOUT, SCLOUT,

DFN....................................................–65°C to 125°C

MSOP ................................................–65°C to 150°C

Lead Temperature (Soldering, 10 sec)

READY, ENABLE.......................................... –0.3V to 6V

Maximum Sink Current (SDAIN, SCLIN, SDAOUT,

SCLOUT, READY).............................................. 50mA

Operating Temperature Range

MSOP ............................................................... 300°C

LTC4307C ................................................ 0°C to 70°C

LTC4307I .............................................–40°C to 85°C

PIN CONFIGURATION

TOP VIEW

ENABLE

SCLOUT

SCLIN

GND

ENABLE

SCLOUT

SCLIN

GND

8 V

7 SDAOUT

6 SDAIN

SDAOUT

SDAIN

READY

5 READY

MS8 PACKAGE

8-LEAD PLASTIC MSOP

= 125°C, θ = 200°C/W

DD PACKAGE

8-LEAD (3mm × 3mm) PLASTIC DFN

JMAX

= 125°C, θ = 43°C/W

JMAX

EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LꢁAD FRꢁꢁ FINISH

LTC4307CDD-1#PBF

LTC4307IDD-1#PBF

LTC4307CMS8-1#PBF

LTC4307IMS8-1#PBF

TAꢂꢁ AND RꢁꢁL

ꢂART MARKING*

LDBP

ꢂACKAGꢁ DꢁSCRIꢂTION

TꢁMꢂꢁRATURꢁ RANGꢁ

0°C to 70°C

LTC4307CDD-1#TRPBF

LTC4307IDD-1#TRPBF

8-Lead (3mm × 3mm) Plastic DFN

8-Lead Plastic MSOP

LDBP

–40°C to 85°C

0°C to 70°C

LTC4307CMS8-1#TRPBF LTDBN

LTC4307IMS8-1#TRPBF LTDBN

8-Lead Plastic MSOP

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS ^The● denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 3.3V, unless otherwise noted.

SYMBOL

ꢂARAMꢁTꢁR

CONDITIONS

MIN

TYꢂ

MAX

UNITS

ꢂower Supply

●

Positive Supply Voltage

Supply Current

2.3

5.5

μA

μs

= 5.5V, V

= V = 0V (Note 5)

SDAOUT

SCLOUT

Shutdown Supply Current

Bus Idle Time

= 5.5V, ENABLE = GND, SDA, SCL = 5.5V

900

1200

175

IDLE

43071fa

LTC4307-1

ELECTRICAL CHARACTERISTICS ^The● denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 3.3V, unless otherwise noted.

SYMBOL

ꢂARAMꢁTꢁR

CONDITIONS

MIN

TYꢂ

1.4

0.1

MAX

UNITS

ENABLE Threshold

0.8

THR_ENABLE

ENABLE

●

ENABLE Input Current

ENABLE Delay Off-On

ENABLE Delay On-Off

READY Delay Off-On

READY Delay On-Off

READY Output Low Voltage

READY Off Leakage Current

ENABLE from 0V to V

μA

μs

= 3.3V (Figure 1)

PLH_EN

= 3.3V (Note 3) (Figure 1)

PHL_EN

PLH_READY

PHL_READY

●

= 3mA, V = 2.3V

0.4

OL_READY

OFF_READY

PULLUP

= READY = 5.5V

0.1

μA

ꢂropagation Delay

SDA/SCL Propagation Delay High to Low

SDA/SCL Propagation Delay Low to High

SDA/SCL Transition Time High to Low

= 50pF, 2.7k to V on SDA, SCL,

PHL

PLH

FALL

LOAD

= 3.3V (Notes 2, 3) (Figure 1)

= 50pF, 2.7k to V on SDA, SCL,

= 3.3V (Notes 2, 3) (Figure 1)

LOAD

= 100pF, 10k to V on SDA, SCL,

300

100

LOAD

= 3.3V (Notes 3, 4) (Figure 1)

Input-Output Connection

●

Input-Output Offset Voltage

2.7k to V on SDA, SCL, V = 3.3V,

Driven SDA, SCL = 0.2V

SDA, SCL Logic Input Threshold Voltage

Rising Edge

(Note 3)

0.45V

0.55V

0.65V

THR

SDA, SCL Logic Input Threshold Voltage

Hysteresis

HYS

Digital Input Capacitance SDAIN, SDAOUT, (Note 3)

SCLIN, SCLOUT

●

Input Leakage Current

Output Low Voltage

SDA, SCL, Pins

SDA, SCL Pins, I

μA

LEAK

= 4mA,

SINK

0.4

SDAIN/SCLIN = 0.2V, V = 2.7V

●

2.7k to V on SDA, SCL, V = 3.3V,

120

160

600

205

1.2

Driven SDA, SCL = 0.1V

Buffer Input Logic Low Voltage

= 3.3V

ILMAX

Timing Characteristics

I C Maximum Operating Frequency

(Note 3)

400

kHz

μs

I2C,MAX

BUF

Bus Free Time Between Stop and Start

Condition

1.3

Hold Time After (Repeated) Start Condition (Note 3)

100

HD,STA

SU,STA

SU,STO

HD,DATI

SU,DAT

Repeated Start Condition Set-Up Time

Stop Condition Set-Up Time

Data Hold Time Input

(Note 3)

Data Set-Up Time

100

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: Determined by design, not tested in production.

Note 4: Measure points are 0.3 • V and 0.7 • V

Note 5: I test performed with connection circuitry active.

Note 6: All currents into pins are positive; all voltages are referenced to

GND unless otherwise speciﬁed.

Note 2: See “Propagation Delays” in the Operations section for a

discussion of t

capacitance.

and t

as a function of pull-up resistance and bus

PHL

PLH

43071fa

LTC4307-1

TIMING DIAGRAMS

ꢁNABLꢁ, CONNꢁCT, RꢁADY Timing

PLH_READY

PHL_READY

PHL_EN

PLH_EN

ENABLE

CONNECT

READY

4307 F01a

Rising and Falling ꢂropagation Delay and Rise and Fall Times for SDAIN, SDAOUT and SCLIN, SCLOUT

FALL

RISE

FALL

PLH

PHL

RISE

SDAIN/SCLIN

SDAOUT/SCLOUT

4307 F01b

Figure 1. Timing Diagrams

43071fa

LTC4307-1

U W

TYPICAL PERFOR A CE CHARACTERISTICS ^T_A^{= 25°C, V}_CC= 3.3V, unless otherwise indicated.

Input-Output High to Low

ꢂropagation Delay vs Temperature

I_CCvs Temperature

I_SDvs Temperature

100

950

900

850

800

750

700

8.3

8.0

7.7

7.4

= 5.5V

= 3.3V

= 2.3V

= 3.3V

= 2.3V

7.1

6.8

6.5

6.2

5.9

= 2.3V

= C

= 50pF

OUT

= R

= 10k

PULLUPIN

PULLUPOUT

–50

100

–25

–50

–25

100

–25

–50

100

TEMPERATURE (°C)

4307 G03

4307 G02

4307 G01

Input-Output High to Low

ꢂropagation Delay vs C_OUT

Connection Circuitry V_OUT– V_IN

(V_OS

)

130

120

110

100

= 50pF

PULLUPIN

= R

= 10k

PULLUPOUT

= 5.5V

= 3.3V

200

400

600

(pF)

800

1000

(kΩ)

OUT

PULLUP

4307 G04

4307 G05

43071fa

LTC4307-1

PI FU CTIO S

ꢁNABLꢁ (ꢂin 1): Connection Enable Input. This is a 1.4V

digital threshold input pin. For normal operation pull or tie

ENABLE high. Driving ENABLE below 0.8V isolates SDAIN

from SDAOUT, SCLIN from SCLOUT and asserts READY

low. A rising edge on ENABLE after a fault has occurred

forces a connection between SDAIN, SDAOUT and SCLIN,

pulls low when ENABLE is low, or when the start-up and

connection sequence described in the Operation section

has not been completed. READY goes high when ENABLE

is high and a connection is made. READY can be used to

control the HDMI HPD signal. Connect a pull-up resistor,

typically 10k, from this pin to V to provide the pull-up.

SCLOUT. Connect to V if unused.

This pin can be ﬂoated if unused.

SCLOUT (ꢂin 2): Serial Clock Output. Connect this pin to

the clock line of a DDC bus. A pull-up resistor should be

connected between this pin and a supply voltage greater

SDAIN (ꢂin 6): Serial Data Input. Connect this pin to the

data line of a DDC bus. A pull-up resistor should be con-

nected between this pin and a supply voltage greater than

than or equal to the V voltage.

or equal to the V voltage.

SCLIN (ꢂin 3): Serial Clock Input. Connect this pin to

the clock line of a DDC bus. A pull-up resistor should be

connected between this pin and a supply voltage greater

SDAOUT (ꢂin 7): Serial Data Output. Connect this pin to

the data line of a DDC bus. A pull-up resistor should be

connected between this pin and a supply voltage greater

than or equal to the V voltage.

GND (ꢂin 4): Device Ground. Connect this pin to a ground

plane for best results.

(ꢂin8):SupplyVoltageInput.Placeabypasscapacitor

of at least 0.01μF close to V for best results.

RꢁADY (ꢂin 5): Connection READY Status Output. The

READYpinisanopen-drainN-channelMOSFEToutputthat

ꢁxposed ꢂad (ꢂin 9, DFN ꢂacꢀage Only): Exposed Pad

may be left open or connected to device ground.

43071fa

LTC4307-1

BLOCK DIAGRA

Low Offset Level-Shifting 2-Wire Bus Buffer

CONNECT

SDAIN

SDAOUT

SLEW RATE

DETECTOR

SLEW RATE

DETECTOR

CONNECT

SCLIN

SCLOUT

SLEW RATE

DETECTOR

SLEW RATE

DETECTOR

–

CONNECT

0.55V

–

LOGIC

READY

CONNECT

ENABLE

–

1.4V

GND

95μs

DELAY

CONNECT

UVLO

43071 BD

43071fa

LTC4307-1

OPERATION

Start-Up

Input to Output Offset Voltage

When a logic low voltage, V

LTC4307-1’s data or clock pins, the LTC4307-1 regulates

the voltage on the opposite data or clock pins to a slightly

higher voltage, typically 60mV above V

When the LTC4307-1 ﬁrst receives power on its V pin

, is driven on any of the

LOW1

during power-up, it starts in an undervoltage lockout

(UVLO) state, ignoring any activity on the SDA or SCL

pins until V rises above 2V (typ). This is to ensure that

. This offset is

LOW1

the LTC4307-1 does not try to function until it has enough

practically independent of pull-up current (see the Typical

Performance curves).

voltage to do so.

Once the LTC4307-1 comes out of UVLO, it monitors both

2-wire busses for either a stop bit or bus idle condition to

indicate the completion of data transactions. When both

sides are idle or one side has a stop bit condition while the

otherisidle,theinput-to-outputconnectioncircuitryisacti-

vated, joining SDAIN to SDAOUT and SCLIN to SCLOUT.

ꢂropagation Delays

During a rising edge, the rise time on each side is de-

termined by the bus pull-up resistor and the equivalent

capacitance on the line. If the pull-up resistors are the

same, a difference in rise time occurs which is directly

proportional to the difference in capacitance between

the two sides. Users must account for differences in the

RC time constants between the two 2-wire busses and

ensure that all system timing speciﬁcations are met on

both busses.

Connection Circuitry

Oncetheconnectioncircuitryisactivated,thefunctionality

of the SDAIN and SDAOUT pins is identical. A low forced

on either pin at any time results in both pin voltages being

low. The LTC4307-1 is tolerant of I C bus DC logic low

There is a ﬁnite propagation delay through the connection

circuitry for falling waveforms. Figure 2 shows the falling

edge waveforms for V = 5.5V, a 10k pull-up resistor on

voltages up to the 0.3V V I C speciﬁcation.

CC IL

When the LTC4307-1 senses a rising edge on the bus,

it deactivates its pull-down devices for bus voltages as

low as 0.48V. Care must be taken to ensure that devices

participating in clock stretching or arbitration force logic

low voltages below 0.48V at the LTC4307-1 inputs.

eachside,150pFparasiticcapacitanceontheinputbusand

50pF on the output pins. An external N-channel MOSFET

device pulls down the voltage on the side with 150pF

capacitance; the LTC4307-1 pulls down the voltage on the

opposite side with a delay of 80ns. This delay is always

positive and is a function of supply voltage, temperature

and the pull-up resistors and equivalent bus capacitances

onbothsidesofthebus. TheTypicalPerformanceCharac-

teristics section shows propagation delay as a function of

temperatureandvoltagefor10kpull-upresistorsand50pF

equivalent capacitance on both sides of the part. Also, the

SDAIN and SDAOUT enter a logic high state only when

all devices on both SDAIN and SDAOUT release high.

The same is true for SCLIN and SCLOUT. This important

feature ensures that clock stretching, clock synchroniza-

tion, arbitration and the acknowledge protocol always

work, regardless of how the devices in the system are

tied to the LTC4307-1.

vsC curveforV =5.5Vshowsthatincreasingthe

PHL

OUT CC

Another key feature of the connection circuitry is that it

provides bidirectional buffering, keeping the capacitances

of the two 2-wire busses isolated from each other. Plac-

ing an LTC4307-1 close to an HDMI port inside an HDMI

transmitter or receiver allows the HDMI device to pass

the capacitance compliance speciﬁcation. Because of this

isolation,thewaveformsonSDAINandSCLINlookslightly

different than the corresponding waveforms on SDAOUT

and SCLOUT as described here.

INPUT SIDE

OUTPUT SIDE

50pF

150pF

1V/DIV

43071 F02

200ns/DIV

Figure 2. Input-Output Falling ꢁdge Waveforms

43071fa

LTC4307-1

OPERATION

capacitance from 50pF to 150pF results in a t

increase

ꢁNABLꢁ

PHL

from 81ns to 91ns. Larger output capacitances translate

to longer delays (up to 125ns). Users must quantify the

difference in propagation times for a rising edge versus

a falling edge in their systems and adjust setup and hold

times accordingly.

When the ENABLE pin is driven below 0.8V with respect to

the LTC4307-1’s ground, the input 2-wire bus is discon-

nected from the output 2-wire bus and the READY pin is

internally pulled low. When the pin is driven above 2V,

the part waits for data transactions on both 2-wire bus-

ses to be complete (as described in the Start-Up section)

before connecting the two sides. At this time the internal

pull-down on READY releases.

RꢁADY Digital Output

This pin provides a digital ﬂag which is low when either

ENABLE is low or the start-up sequence described earlier

in this section has not been completed. READY goes high

when ENABLE is high and the input and output 2-wire

busses are connected. The pin is driven by an open-drain

pull-down capable of sinking 3mA while holding 0.4V on

LTC4307 and LTC4307-1 Feature Differences

The LTC4307-1 HDMI level-shifting 2-wire bus buffer is

speciﬁcally intended for HDMI applications. Features in

the general purpose LTC4307 device that are not required

in HDMI systems have been removed. In addition, level-

shifting functionality has been added to the LTC4307-1

to allow 3.3V HDMI devices to interface safely to the 5V

HDMI DDC bus. See Table 1 for a list of the differences

between the LTC4307 and LTC4307 -1.

the pin. Connect a resistor to V to provide the pull-up.

READY can be used to control the HDMI hot plug detect

(HPD) signal to prevent the possibility of erroneous at-

tempts by the source to contact the sink before the sink

is ready to communicate.

Table 1. Differences Between the LTC4307 and the LTC4307-1

SꢂꢁCIFICATION

LTC4307

LTC4307-1

COMMꢁNTS ON LTC4307-1

Pre-charge

Yes

HDMI DDC Lines are Not Hot Swapped

Yes,

Provides Communication Between 3.3V and 5V DDC Busses,

Level Shifting

2.2V to 5.5V Protects 3.3V Devices from 5V Supply

Stuck Bus Disconnect and Recovery

Rise Time Accelerators

Yes

Stuck Busses, Not an Issue in HDMI Systems

Complies with HDMI Speciﬁcation Version 1.3 DDC Capacitance

Requirement

APPLICATIONS INFORMATION

Figure 3 shows the LTC4307-1 in a capacitance buffering

application. Due to the LTC4307-1’s capacitance buffering

feature and sub-10pF input capacitance, this application

circuit passes the HDMI 50pF maximum DDC capacitance

speciﬁcation easily when the LTC4307-1 is located right at

the HDMI connector interface as shown. The capacitance

of the internal bus connected to the SDAIN and SCLIN

pins may be much larger than 50pF, but because of the

LTC4307-1’s capacitance buffering, the internal bus ca-

pacitance is isolated from the HDMI connector.

In HDMI, the sink device pulls the hot plug detect HPD

signal high to tell the source that it is ready to accept

commandsthroughtheDDC.Thissignalcanbecontrolled

through the READY pin of the LTC4307-1 to prevent the

possibility of erroneous attempts by the source to contact

the sink before the sink is ready to return its extended

display identiﬁcation data (EDID). The READY pin only

goes high after 5V is applied and the LTC4307-1 ENABLE

pin is pulled high by the HDMI receiver IC, a controller in

the sink, or the 5V line itself.

43071fa

LTC4307-1

APPLICATIONS INFORMATION

Figure 4 shows the LTC4307-1 being used for capacitance

buffering and 5V to 3.3V level shifting. In this application,

the EEPROM is powered by a backup 3.3V supply that is

available when the component is turned off. The EDID in

the EEPROM should be available for reading even when

a component’s power is off.

Although the applications shown in this section are for

HDMI receive channels, the LTC4307-1 can also be used

in HDMI transmit channels with equal success as shown

in the Typical Application on the last page of this data

sheet.

EEPROM

SCL SDA GND

0.1μF

1.8k

3.3V

100k

1.8k

47k

LTC4307-1

READY

10k 10k

R10

10k 10k

SDA

SCL

HPD

SDAOUT SDAIN

SCLOUT SCLIN

HDMI

TX IC

HDMI CABLE

HDMI

RX IC

ENABLE

GND

DDC

100k

DDC/CEC

GROUND

HDMI SOURCE

(DVD PLAYER)

HDMI SINK

(DIGITAL TV)

43071 F03

Figure 3. The LTC4307-1 in HDMI Capacitance Buffering Application

SWITCHED

3.3V

BACKUP 3.3V

EEPROM

SCL SDA

HDMI

RX IC

47k

0.1μF R5

1.8k 1.8k

LTC4307-1

READY

100k 10k 10k

SDA

SCL

HDMI

TX IC

SDAIN SDAOUT

SCLIN SCLOUT

HDMI CABLE

ENABLE

GND

DDC

DDC/CEC

GROUND

μC

HDMI SOURCE

(DVD PLAYER)

HDMI REPEATER

(DIGITAL RECEIVER)

43071 F04

Figure 4. The LTC4307-1 in a Level Shifting and Capacitance Buffering HDMI Application with Bacꢀup 3.3V

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LTC4307-1

PACKAGE DESCRIPTION

DD Package

8-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698)

R = 0.115

0.38 ± 0.10

TYP

0.675 ±0.05

3.5 ±0.05

2.15 ±0.05 (2 SIDES)

1.65 ±0.05

3.00 ±0.10

(4 SIDES)

1.65 ± 0.10

(2 SIDES)

PIN 1

TOP MARK

(NOTE 6)

PACKAGE

OUTLINE

(DD8) DFN 1203

0.25 ± 0.05

0.75 ±0.05

0.200 REF

0.25 ± 0.05

0.50 BSC

0.50

BSC

2.38 ±0.05

(2 SIDES)

2.38 ±0.10

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660 Rev F)

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.52

(.0205)

REF

7 6

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

4.90 ± 0.152

(.193 ± .006)

DETAIL “A”

0° – 6° TYP

0.889 ± 0.127

(.035 ± .005)

0.254

(.010)

GAUGE PLANE

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.53 ± 0.152

(.021 ± .006)

1.10

(.043)

MAX

0.86

(.034)

REF

DETAIL “A”

0.18

(.007)

0.65

(.0256)

BSC

0.42 ± 0.038

(.0165 ± .0015)

SEATING

PLANE

TYP

0.22 – 0.38

0.1016 ± 0.0508

RECOMMENDED SOLDER PAD LAYOUT

(.009 – .015)

(.004 ± .002)

0.65

(.0256)

BSC

TYP

MSOP (MS8) 0307 REV F

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

43071fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC4307-1

TYPICAL APPLICATION

HDMI Application with LTC4307-1’s ꢂroviding Capacitance Buffering

On Both the Transmit and Receive Channels

DVD PLAYER (SOURCE)

TV (SINK)

3.3V

EEPROM

0.1μF

10k

10k 1.8k 1.8k

LTC4307-1

READY

SDAOUT

SCLOUT

READY

SDAIN

SCLIN

HDMI

CABLE

<50pF

SDAIN

SCLIN

SDAOUT

SCLOUT

HDMI RX

HDMI TX

ENABLE

μC

GND

DDC GROUND

43071 TA02

RELATED PARTS

ꢂART NUMBꢁR

DꢁSCRIꢂTION

COMMꢁNTS

LTC1380/LTC1393

Single-Ended 8-Channel/Differential 4-Channel Analog Low R : 35Ω Single Ended/70Ω Differential, Expandable to 32 Single

MUX with SMBus Interface

or 16 Differential Channels

LTC1427-50

Micropower, 10-Bit Current Output DAC with SMBus

Interface

Precision 50μA 2.5ꢀ Tolerance Over Temperature, Four Selectable

SMBus Addresses, DAC Powers Up at Zero or Midscale

LTC1623

Dual High Side Switch Controller with SMBus Interface Eight Selectable Addresses/16-Channel Capability

LTC1663

SMBus Interface 10-Bit Rail-to-Rail Micropower DAC

SMBus Accelerator

DNL < 0.75LSB Max, 5-Lead SOT-23 Package

LTC1694/LTC1694-1

Improved SMBus/I C Rise Time, Ensures Data Integrity with Multiple

SMBus/I C Devices

LTC1695

LT1786F

LTC1840

SMBus/I C Fan Speed Controller in ThinSOT^TMPackage 0.75Ω PMOS 180mA Regulator, 6-Bit DAC

SMBus Controlled CCFL Switching Regulator

1.25A, 200kHz Floating or Grounded Lamp Conﬁgurations

Dual I C Fan Speed Controller

Two 100μA 8-Bit DACs, Two Tach Inputs, Four GPIO

LTC4300A-1/

LTC4300A-2/

LTC4300A-3

Hot Swappable 2-Wire Bus Buffers

LTC4300A-1: Bus Buffer with READY, ACC and ENABLE

LTC4300A-2: Dual Supply Bus Buffer with READY and ACC

LTC4300A-3: Dual Supply Bus Buffer with READY and ENABLE

LTC4301

Supply Independent Hot Swappable 2-Wire Bus Buffer Supply Independent

LTC4301L

Hot Swappable 2-Wire Bus Buffer with Low Voltage

Level Translation

Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN

LTC4302-1/LTC4302-2 Addressable 2-Wire Bus Buffer

Address Expansion, GPIO, Software Controlled

LTC4303/LTC4304

LTC4305/LTC4306

LTC4307

Hot Swappable 2-Wire Bus Buffers with Stuck Bus

Provides Automatic Clocking to Free Stuck I C Busses

Recovery

2-/4-Channel, 2-Wire Bus Multiplexers with

Capacitance Buffering

2/4 Selectable Downstream Busses, Stuck Bus Disconnect, Rise Time

Accelerators, Fault Reporting, 10kV HBM ESD Tolerance

Low Offset Hot-Swappable 2-Wire Bus Buffer with

Stuck Bus Recovery

60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery

ThinSOT is a trademark of Linear Technology Corporation

43071fa

LT 0208 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

LTC4307IMS8-1#TRPBF [Linear]

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