LTC4308_技术文档

LTC4308

Low Voltage, Level Shifting

Hot Swappable 2-Wire Bus

Buffer with Stuck Bus Recovery

FEATURES

DESCRIPTION

The LTC^®4308 hot swappable, 2-wire bus buffer allows

I/O card insertion into a live backplane without corrup-

tion of the data and clock busses. The LTC4308 provides

bidirectional buffering, keeping the backplane and card

capacitances isolated. Negative offset from output to

input allows communication between output bus devices

n

Optimized for Low Voltage Systems Down to 0.9V

n

Bidirectional Buffer with Stuck Bus Recovery

n

–200mV Offset In-Out/+300mV Offset Out-In

n

30ms Stuck Bus Timeout

2

n

Compatible with Non-Compliant V I C Devices

OL

n

Prevents SDA and SCL Corruption During Live

Board Insertion and Removal from Backplane

with high V and devices on the low voltage input side,

OL

n

±±kV ꢀuman Body ꢁodel ꢂꢀBꢁM ꢃSD Protection

where bus supplies can be as low as 0.9V. If SDAOUT or

SCLOUT are low for 30ms, the LTC4308 will automati-

cally break the Input-Output connection. At this time the

LTC4308 automatically generates up to 16 clock pulses

on SCLOUT in an attempt to free the bus. A connection

will resume if the stuck bus is cleared.

n

Isolates Input SDA and SCL Lines from Output

2

n

Compatible with I C™, I C Fast Mode and SMBus

READY Open-Drain Output

1V Precharge on SDAOUT and SCLOUT Lines

Small 8-Lead (3mm × 3mm × 0.75mm) DFN and

8-Lead MSOP Packages

During insertion, the SDAOUT and SCLOUT lines are pre-

charged to 1V to minimize bus disturbances. When driven

high,theENABLEinputallowstheLTC4308toconnectafter

astopbitorbusidlecondition.DrivingENABLElowbreaks

the connection between SDAIN and SDAOUT, SCLIN and

SCLOUT. READY is an open-drain output which indicates

that the backplane and card sides are connected.

APPLICATIONS

n

Live Board Insertion

n

Servers

n

Capacitance Buffer/Bus Extender

RAID Systems

ATCA

n

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap

is a trademark of Linear Technology Corporation. All other trademarks are the property of their

respective owners. Protected by U.S. Patents including 7032051, 6650174, 6356140.

n

TYPICAL APPLICATION

The LTC4308 in a 1.2V

ꢁicrocontroller Application

1.2V to 5V Level Shifting

SDAOUT

5V

1.2V

0.01μF

2V/DIV

CH1

2.7k 2.7k

10k

2.7k 2.7k

V

CC

LTC4308

SCLIN SCLOUT

SDAIN

CARD_SCL

MICRO-

CONTROLLER

0.5V/DIV

CH2

SDAIN SDAOUT

ENABLE

CARD_SDA

4308 TA01a

READY

GND

READY

1μs/DIV

4308 TA01b

4308f

1

LTC4308

ꢂNotes 1, 7M

ABSOLUTE MAXIMUM RATINGS

V

to GND ................................................. –0.3V to 6V

Storage Temperature Range

CC

SDAIN, SCLIN, SDAOUT, SCLOUT,

DFN....................................................–65°C to 125°C

MSOP ................................................–65°C to 150°C

Lead Temperature (Soldering, 10 sec)

READY, ENABLE.......................................... –0.3V to 6V

Maximum Sink Current (SDAIN, SCLIN, SDAOUT,

SCLOUT, READY).............................................. 50mA

Operating Temperature Range

MSOP ............................................................... 300°C

LTC4308C ................................................ 0°C to 70°C

LTC4308I..............................................–40°C to 85°C

PIN CONFIGURATION

TOP VIEW

ENABLE

SCLOUT

SCLIN

GND

1

2

3

4

8

7

6

5

V

CC

ENABLE

SCLOUT

SCLIN

GND

1

2

3

4

8 V

CC

7 SDAOUT

6 SDAIN

SDAOUT

SDAIN

9

5 READY

READY

MS8 PACKAGE

8-LEAD PLASTIC MSOP

DD PACKAGE

8-LEAD (3mm × 3mm) PLASTIC DFN

T

= 125°C, θ = 200°C/W

JA

JMAX

T

JMAX

= 125°C, θ = 43°C/W

JA

EXPOSED PAD (PIN 9) CONNECTION TO GROUND IS OPTIONAL

ORDER INFORMATION

LꢃAD FRꢃꢃ FINISꢀ

LTC4308CDD#PBF

LTC4308IDD#PBF

LTC4308CMS8#PBF

LTC4308IMS8#PBF

TAPꢃ AND RꢃꢃL

PART ꢁARKING*

LBTT

PACKAGꢃ DꢃSCRIPTION

TꢃꢁPꢃRATURꢃ RANGꢃ

0°C to 70°C

LTC4308CDD#TRPBF

LTC4308IDD#TRPBF

LTC4308CMS8#TRPBF

LTC4308IMS8#TRPBF

8-Lead (3mm × 3mm) Plastic DFN

8-Lead Plastic MSOP

LBTT

–40°C to 85°C

0°C to 70°C

LTBTS

8-Lead Plastic MSOP

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *Temperature grades are identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

The ^ldenotes the speciﬁcations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 3.3V, unless otherwise noted.

SYꢁBOL

PARAꢁꢃTꢃR

CONDITIONS

ꢁIN

TYP

ꢁAX UNITS

Power Supply

l

V

Positive Supply Voltage

Supply Current

2.3

5.5

11

V

mA

μA

CC

I

V

= 5.5V, V

= V = 0V (Note 6)

SDAOUT

7

900

1

CC

SD

CC

SCLOUT

I

Shutdown Supply Current

Precharge Voltage

= 5.5V, ENABLE = 0V

1400

1.2

CC

V

SDAOUT, SCLOUT Open

0.8

V

PRE

4308f

2

LTC4308

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 3.3V, unless otherwise noted.

SYꢁBOL

PARAꢁꢃTꢃR

CONDITIONS

ꢁIN

55

TYP

95

ꢁAX UNITS

l

t

Bus Idle Time

175

μs

V

IDLE

V

ENABLE Threshold Voltage

ENABLE Threshold Voltage Hysteresis

ENABLE Input Current

ENABLE Delay Off-On

ENABLE Delay On-Off

READY Delay Off-On

ENABLE Rising Edge

(Note 3)

0.45

0.6

35

0.75

THR_EN

V

mV

μA

μs

ns

V

THR_EN(HYST)

l

I

t

ENABLE from 0V to V

(Figure 1)

0.1

95

5

ENABLE

CC

PLH_EN

(Note 3), (Figure 1)

10

PHL_EN

10

PLH_READY

PHL_READY

READY Delay On-Off

10

l

V

READY Output Low Voltage

READY Off Leakage Current

I

= 3mA, V = 2.3V

0.4

5

OL_READY

OFF_READY

READY

CC

I

V

CC

= READY = 5.5V

0.1

μA

Prop Delay and Rise-Time Accelerators

t

I

SDA/SCL Propagation Delay High to Low

SDA/SCL Propagation Delay Low to High

SDA/SCL Transition Time Low to High

SDA/SCL Transition Time High to Low

Transient Boosted Pull-Up Current

C

= 50pF, 2.7k to V on SDA, SCL,

70

10

30

8

ns

PHL

LOAD

CC

(Notes 2, 3), (Figure 1)

C

LOAD

= 50pF, 2.7k to V on SDA, SCL,

CC

PLH

(Notes 2, 3), (Figure 1)

C

LOAD

= 100pF, 10k to V on SDA, SCL,

300

ns

RISE

CC

(Notes 3, 4), (Figure 1)

C

LOAD

= 100pF, 10k to V on SDA, SCL,

ns

FALL

CC

(Notes 3, 4), (Figure 1)

Positive Transition > 0.8V/μs on SDAOUT,

SCLOUT (Note 5)

5

mA

PULLUPAC

Input-Output Connection

l

V

OS

Input to Output Offset Voltage (OUT – IN)

2.7k to V on SDAOUT, SCLOUT,

250

300

350

380

450

mV

CC

SDAIN = SCLIN = 0.2V

2.7k to V on SDAOUT, SCLOUT,

CC

SDAIN = SCLIN = 0.4V, V = 5.5V

CC

Output to Input Offset Voltage (IN – OUT)

2.7k to V on SDAIN, SCLIN,

–150

–200

–250

–300

–350

CC

SDAOUT = SCLOUT = 0.4V

2.7k to V on SDAIN, SCLIN,

CC

SDAOUT = SCLOUT = 0.4V, V = 5.5V

CC

V

SDAOUT, SCLOUT Logic Input Threshold Voltage

SDAIN, SCLIN Logic Input Threshold Voltage

V

≥ 2.9V

< 2.9V

1.4

1.1

1.65

1.35

1.9

1.6

V

THR

CC

SDAIN, SCLIN Rising Edge, V = 2.3V, 5.5V

0.45

0.6

50

0.75

V

CC

V

SDAOUT, SCLOUT Logic Input Threshold Voltage (Note 3)

Hysteresis

mV

THR(HYST)

SDAIN, SCLIN Logic Input Threshold Voltage

Hysteresis

(Note 3)

35

mV

pF

C

Digital Input Capacitance SDAIN, SDAOUT,

SCLIN, SCLOUT

(Note 3)

10

IN

l

I

Input Leakage Current

Output Low Voltage

SDA, SCL Pins

5

μA

LEAK

V

SDAOUT, SCLOUT Pins, I

SDAIN = SCLIN = 0V, V = 2.7V

= 4mA,

SINK

CC

0

400

mV

OL

l

2.7k to V on SDAOUT, SCLOUT,

250

300

380

1.2

mV

CC

SDAIN = SCLIN = 0V

V

ILMAX

Buffer Input Logic Low Voltage

SDAOUT, SCLOUT Pins

V

4308f

3

LTC4308

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 3.3V, unless otherwise noted.

SYꢁBOL

Bus Stuck Low Timeout

Bus Stuck Low Timer

PARAꢁꢃTꢃR

CONDITIONS

ꢁIN

25

TYP

30

ꢁAX UNITS

l

t

SDAOUT = SCLOUT = 0V

35

ms

TIMEOUT

Timing Characteristics

2

f

t

I C Maximum Operating Frequency

(Note 3)

400

600

kHz

μs

ns

I2C,MAX

BUF

Bus Free Time Between Stop and Start Condition (Note 3)

1.3

100

0

Hold Time After (Repeated) Start Condition

Repeated Start Condition Set-Up Time

Stop Condition Set-Up Time

Data Hold Time Input

(Note 3)

HD,STA

SU,STA

SU,STO

HD,DATI

SU,DAT

0

Data Set-Up Time

100

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: Determined by design, not tested in production.

Note 4: Measure points are 0.3 • V and 0.7 • V

.

CC

Note 5: I

varies with temperature and V voltage as shown in the

PULLUPAC

CC

Typical Performance Characteristics section.

Note 2: See “Propagation Delays” in the Operations section for a

Note ±: I test performed with connection circuitry active.

CC

discussion of t

capacitance.

and t

as a function of pull-up resistance and bus

PHL

PLH

Note 7: All currents into pins are positive; all voltages are referenced to

GND unless otherwise speciﬁed.

TIMING DIAGRAMS

ꢃNABLꢃ, CONNꢃCT, RꢃADY Timing

t

PLH_READY

PLH_EN

PHL_READY

t

PHL_EN

t

ENABLE

CONNECT

READY

4308 TD01

Rising and Falling Propagation Delays and Rise and Fall Times for SDAIN, SDAOUT and SCLIN, SCLOUT

t

FALL

RISE

t

FALL

PLH

PHL

RISE

SDAIN/SCLIN

SDAOUT/SCLOUT

4308 TD02

Figure 1. Timing Diagrams

4308f

4

LTC4308

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_CC= 3.3V, unless otherwise indicated.

I_CCꢃnabled Current

vs Temperature

I_SDDisabled Current

vs Temperature

8.0

7.5

7.0

6.5

1000

950

900

850

800

750

700

650

600

V

CC

= 5.5V

V

= 3.3V

= 2.3V

CC

6.0

5.5

V

CC

5.0

4.5

4.0

–25

0

50

–50

75

100

25

–50

–25

25

50

75

100

0

TEMPERATURE (°C)

4308 G01

4308 G02

Input-Output ꢀigh to Low

Propagation Delay

vs Temperature

Boost Pull-Up Current

vs Temperature

140

120

100

80

24

20

16

12

8

C

= C

PULLUPIN

= 50pF

OUT

IN

C

IN

= 50pF, C

= 1nF

OUT

R

= R

= 2.7k

PULLUPOUT

R

= R

= 2.7k

PULLUPOUT

PULLUPIN

V

CC

= 5.5V

V

CC

= 5.5V

V

= 3.3V

= 2.3V

75

CC

V

= 2.3V

= 3.3V

CC

60

4

V

CC

40

–50

0

–25

25

50

75

100

0

–50

0

25

50

100

–25

TEMPERATURE (°C)

4308 G03

4308 G04

Input-Output ꢀigh to Low

Propagation Delay vs Output

Capacitance

Input-Output Offset Voltage

vs Pull-Up Resistance

Output-Input Offset Voltage

vs Pull-Up Resistance

140

125

110

95

–196

–198

–200

–202

–204

–206

304

302

300

298

296

294

C

R

= 50pF

PULLUPIN

PULLUPOUT

IN

= 2.7k

V

= 5.5V

= 2.3V

= 3.3V

CC

80

V

CC

65

V

= 1.8V

PULLUPIN

= V

PULLUPOUT

CC

50

0

400

600

800

1000

200

0

4

6

8

10

0

2

4

6

8

10

2

OUTPUT CAPACITANCE (pF)

INPUT BUS PULL-UP RESISTANCE (k)

OUTPUT BUS PULL-UP RESISTANCE (k)

4308 G05

4308 G06

4308 G07

4308f

5

LTC4308

PIN FUNCTIONS

ꢃNABLꢃꢂPin1M:ConnectionEnableInput. This0.6Vnomi-

nal threshold input pin enables or disables the LTC4308.

Fornormaloperation,pullorconnectENABLEhigh.Driving

ENABLE below the 0.45V threshold isolates SDAIN from

SDAOUT, SCLIN from SCLOUT, asserts READY low, and

prohibits automatic clock and stop bit generation during a

fault condition. A rising edge on ENABLE after a fault has

occurred forces a connection between SDAIN, SDAOUT

RꢃADY ꢂPin 5M: Connection Ready Status Output. This

open-drain N-channel MOSFET pin pulls low when

ENABLEislow,whenthestartupandconnectionsequence

describedintheOperationsectionhasnotbeencompleted,

or when the LTC4308 disconnects the input and output

pins due to a bus stuck low condition. READY goes high

whenENABLEishighandconnectionismadebetweenthe

input and output pins. Connect a pull-up resistor, typically

10k, from this pin to the bus pull-up supply. This pin can

be left open if unused.

and SCLIN, SCLOUT. Connect to V if unused.

CC

SCLOUT ꢂPin 2M: Serial Clock Output. Connect this pin to a

SCLbussegmentwherebusstucklowrecoveryisdesired.

A pull-up resistor should be connected between this pin

SDAINꢂPin±M:SerialDataInput. ConnectthispintoaSDA

bus segment where isolation from bus stuck low issues is

desired. A pull-up resistor should be connected between

this pin and a bus pull-up supply greater than 0.9V.

and a bus pull-up supply greater than or equal to V .

CC

SCLINꢂPin3M:SerialClockInput.ConnectthispintoaSCL

bus segment where isolation from bus stuck low issues is

desired. A pull-up resistor should be connected between

this pin and a bus pull-up supply greater than 0.9V.

SDAOUT ꢂPin 7M: Serial Data Output. Connect this pin to a

SDAbussegmentwherebusstucklowrecoveryisdesired.

A pull-up resistor should be connected between this pin

and a bus pull-up supply greater than or equal to V .

CC

GND ꢂPin 4M: Device Ground. Connect this pin to a ground

plane for best results.

V

ꢂPin8M:SupplyVoltageInput.Placeabypasscapacitor

CC

of at least 0.01μF close to V for best results.

CC

ꢃxposed Pad ꢂPin 9, DFN Package OnlyM: Exposed Pad

may be left open or connected to device ground.

4308f

6

LTC4308

BLOCK DIAGRAM

Low Voltage Level Shifting 2-Wire Bus Buffer with Stuck Bus Recovery

8mA

V

8

7

CC

CONNECT

I

BOOSTSDA

SDAIN

SDAOUT

100k

6

SLEW RATE

DETECTOR

CONNECT

PRECHARGE

PC_CONNECT

CONNECT

100k

8mA

I

BOOSTSCL

SCLIN

SCLOUT

3

2

SLEW RATE

DETECTOR

+

–

CONNECT

1.65V/1.6V

1.35V/1.3V

30ms

TIMER

+

–

+

–

0.6V

1.65V/1.6V

1.35V/1.3V

I

BOOSTSCL

I

BOOSTSDA

+

–

LOGIC

READY

5

CONNECT

PC_CONNECT

ENABLE

+

–

1

GND

95μs

DELAY

CONNECT

4

UVLO

4308 BD

4308f

7

LTC4308

OPERATION

Start-Up

0.3 • V , while the SCLIN and SDAIN busses are tolerant

CC

of bus logic low voltages up to 0.6V. A high occurs when

all devices on the input and output pins release high.

When the LTC4308 ﬁrst receives power on its V pin,

CC

either during power-up or live insertion, it starts in an

under voltage lockout (UVLO) state, ignoring any activity

When the LTC4308 senses a rising edge on either of the

output busses, with a slew rate greater than 0.8V/μs, the

internal pull-down device for the respective bus is deacti-

vated at bus voltages as low as 0.48V. This methodology

maximizes the effectiveness of the rise time accelerator

circuitry and maintains compatibility with other devices

in the LTC4300 bus buffer family. Care must be taken to

ensure devices participating in clock stretching or arbitra-

tion is capable of forcing logic low voltages below 0.48V

at the LTC4308’s SCLOUT and SDAOUT pins.

on the SDA or SCL pins until V rises above 2V (typical).

CC

This ensures the LTC4308 does not try to function until

enough supply voltage is present.

During this time, the 1V precharge circuitry is actively

forcing1Vthrough100knominalresistorstotheSDAOUT

and SCLOUT pins. Because SDAOUT and SCLOUT pins

may be plugged into a live backplane, where the voltage

on the backplane SDA and SCL busses can be anywhere

between 0V and V , precharging SCLOUT and SDAOUT

CC

2

to 1V minimizes the worst-case voltage differential these

pinswillseeatthemomentofcontact,thereforeminimizing

the amount of disturbance caused by the I/O card.

These important features ensure the I C speciﬁcation

protocols such as clock stretching, clock synchroniza-

tion, arbitration, and acknowledge function seamlessly

in all cases as speciﬁed, regardless of how the devices in

the system are connected to the LTC4308.

Once the LTC4308 exits from UVLO, it monitors both the

input and output pins for either a stop bit or a bus idle

condition to indicate the completion of data transactions.

Whenbothsidesareidleoronesidehasastopbitwhilethe

other is idle, the connection circuitry is activated, joining

the SDA and SCL pins on the input bus with those on the

output bus. Because SDAIN and SCLIN are monitored for

a stop bit or bus idle as a condition for connection, they

may also be used for Hot-Swapping, but note that these

pins are not precharged.

Another key feature provided by the connection circuitry

is input and output bus capacitance isolation through

bidirectional buffering. Because of this isolation, the

waveforms on the input busses look slightly different than

the corresponding output bus waveforms, as described

in the next two sections.

Offset Voltages

WhenalogiclowisdrivenonSDAINorSCLIN,theLTC4308

regulates SDAOUT or SCLOUT, respectively, to a higher

voltage, typically 300mV above the driven low voltage.

When a logic low is driven on SCLOUT or SDAOUT, the

LTC4308regulatesSCLINorSDAIN,respectively,toavolt-

age that is typically 200mV below the driven low voltage.

These offsets are nearly independent of pull-up current

(see Typical Performance Characteristics).

Connection Circuitry

Oncetheconnectioncircuitryisactivated,thefunctionality

of the input and output bus of the respective SDA or SCL

pins is identical. A low forced on either output or input pin

at any time results in both pin voltages forced low. The

LTC4308 SCLOUT and SDAOUT busses are tolerant of I C

bus DC logic low voltages up to the V speciﬁcation of

2

IL

4308f

8

LTC4308

OPERATION

C

V

= 50pF

PULLUP(OUT)

C

V

= 50pF

OUT

PULLUP(OUT)

OUT

= V = 3.3V

CC

= V = 3.3V

CC

C

V

= 150pF

IN

PULLUP(IN)

C

V

= 150pF

IN

PULLUP(IN)

= 1.8V

200ns/DIV

4308 F02

4308 F03

Figure 2. Input-Output Rising ꢃdge Waveforms

Figure 3. Input-Output Falling ꢃdge Waveforms

Propagation Delays

outputcapacitancestranslatetolongerdelays.Usersmust

quantify the difference in propagation times for a rising

edge versus a falling edge in their systems and adjust

setup and hold times accordingly.

During a rising edge, the rise time on each side is inﬂu-

enced by rise time acceleration, bus pull-up resistor, and

theequivalentcapacitanceontheline.Ifthepull-upresis-

torsarethesame,adifferenceinrisetimeoccurswhichis

directly proportional to the difference in capacitance and

the presence of rise time acceleration between the two

Bus Stuck Low Timeout

SDAOUT and SCLOUT are each connected to an internal

timer. When SDAOUT or SCLOUT is low, its respective

timer is started. Each timer is only reset when its pin goes

high. If the bus stuck low does not go high within 30ms

(typical), the connection circuitry is disabled, breaking

the connection between the respective input and output

pins. In addition, after at least 40μs, up to 16 clock pulses

at 8.5kHz (typical) are generated on the SCLOUT pin by

the LTC4308 in an attempt to free the stuck low bus. The

clock pulses are halted if the bus recovers to a logic high

condition before the completion of the full 16 pulses. A

stop bit is always generated on the SCLOUT and SDAOUT

pins to reset all devices on the bus.

sides. This effect is displayed in Figure 2 for V = 3.3V

CC

and a 2.7k pull-up resistor on the input (V

1.8V, C = 150pF) and output (V

=

OUT

PULLUP(IN)

= 3.3V, C

IN

PULLUP(OUT)

= 50pF). Since the output pin has rise time acceleration

and less capacitance than the input, it rises faster and

the effective propagation delay is negative.

There is a ﬁnite propagation delay through the connec-

tion circuitry for falling waveforms. Figure 3 shows the

falling edge waveforms for the same pull-up resistors and

equivalent capacitance conditions as used in Figure 2.

An external N-channel MOSFET device pulls down the

voltage on the side with 150pF capacitance; the LTC4308

pulls down the voltage on the opposite side with a delay

of 70ns. This delay is always positive and is a function of

supply voltage, temperature and the pull-up resistors and

equivalent bus capacitances on both sides of the bus.

If the stuck low SDAOUT or SCLOUT does not recover to

a logic high condition after the automatic clocking and

stop bit generation, the LTC4308 remains disconnected.

Should the bus free, the LTC4308 will reconnect the input

and output busses if a stop bit or bus idle condition is

detected,asspeciﬁedintheStartUpsection.Alternatively,

a rising edge on ENABLE forces the connection circuitry to

reconnect the input and output busses and reset the 30ms

timer if the bus remains in a stuck bus low condition.

The Typical Performance Characteristics section shows

propagationdelayasafunctionoftemperatureandvoltage

for 2.7k pull-up resistors and 50pF equivalent capacitance

on both sides of the part. Also, the Propagation Delay as

a function of Output Capacitance curve shows that larger

4308f

9

LTC4308

OPERATION

When powering up into a bus stuck low condition, the

connection circuitry connecting the SDA and SCL pins are

not activated. 30ms after UVLO, automatic clocking and

stop bit generation takes place as described above.

Rise Time Accelerators

Once connection has been established, rise time accelera-

tor circuits on SDAOUT and SCLOUT are enabled. During

positive bus transitions of at least 0.8V/μs, the rise time

accelerators provide strong, slew-limited pull-up currents

to force the bus voltage to rise at a rate of 100V/μs.

RꢃADY Digital Output

This pin provides a digital ﬂag which is low when either

ENABLE is low, the start-up sequence described earlier

in this section has not been completed, or the LTC4308

has disconnected the input and output busses due to a

bus stuck low condition. READY goes high when ENABLE

is high and start-up is complete. The pin is driven by an

open-drainpull-downdevicecapableofsinking3mAwhile

holding 0.4V on the pin. Connect a resistor to the bus

pull-up supply to provide the pull-up.

The rise time accelerators signiﬁcantly improve reli-

2

ability and performance in I C systems in several ways.

First, due to the accelerator’s signiﬁcantly lower pull-up

impedance, as compared to the bus pull-up resistance,

the system is less susceptible to noise on rising edges,

providing smooth, controlled transitions for both small

and large systems. Second, the accelerators allow users

to choose larger bus pull-up resistors, reducing power

consumption and improving logic low noise margins or

to design with bus capacitances beyond those speciﬁed

ꢃNABLꢃ

2

in the I C speciﬁcations.

When the ENABLE pin is driven below 0.45V with respect

to the LTC4308’s ground, the input pin is disconnected

from the output pin and the READY pin is pulled low.

When the pin is driven above 0.75V, the part waits for

data transactions on both the input and output pins to be

complete (as described in the Start-Up section) before

connectingthetwopins.Atthistimetheinternalpull-down

on READY releases.

For these reasons, it is strongly recommended that users

choose bus pull-up resistors that guarantee the output

busses will rise on their own at a rate of at least 0.8 V/μs to

ensure activation of the accelerators. See the Applications

Information section for selecting pull-up resistor sizes.

It is important to connect SDAOUT and SCLOUT pins to

a bus whose pull-up supply is equal to or greater than

the LTC4308’s supply to ensure the accelerators do not

source current through the pull up resistors into the pull-

up supply.

A rising edge on ENABLE after a bus stuck low condition

hasoccurredforcesaconnectionbetweenSDAIN,SDAOUT,

and SCLIN, SCLOUT even if the bus stuck low condition

has not been cleared. At this time the 30ms timer is reset,

but not disabled.

The rise time accelerators are internally disabled until the

sequence of events described in the start-up section has

been completed, as well as during automatic clocking and

stop bit generation for a bus stuck low recovery event.

4308f

10

LTC4308

APPLICATIONS INFORMATION

Resistor Pull-Up Value Selection

requirements difﬁcult to meet. Placing an LTC4308 on the

edge of each card isolates the card capacitance from the

backplane. For a given I/O card, the LTC4308 drives the

capacitance of everything on the card and the backplane

must drive only the capacitance of the LTC4308, which

is less than 10pF.

ToguaranteetheSDAOUTandSCLOUTrisetimeaccelera-

tors are activated during a rising edge, the bus must rise

on its own with a positive slew rate of at least 0.8V/μs. To

achieve this, choose a maximum resistor value R

using the formula:

PULLUP

Figure 4 shows the LTC4308 used in the typical staggered

(V_BUS(MIN)− 0.8V)•1250ns / V

R_PULLUP

WhereR

≤

connectorapplication, whereV andGNDarethelongest

CC

C_BUS

“early power” pins. The “early power” pins ensure the

LTC4308 is initially powered and forcing the 1V precharge

voltage on the medium length SDA and SCL output pins

before they contact with the backplane busses. Coupled

withENABLEastheshortestpin,passivelypulledtoground

by a resistor, the staggered approach provides additional

time for transients associated with live insertion to settle

before the LTC4308 can be enabled.

isthepull-upresistorvalueinkΩ,V

PULLUP

BUS(MIN)

is the minimum bus pull-up supply voltage and C

the equivalent bus capacitance in pF.

is

BUS

To estimate the value of C , use a general rule of 20pF

BUS

of capacitance per device on the bus (10pF for the device

and 10pF for interconnect).

In addition, R

must be strong enough to overcome

PULLUP

Figure 5 shows the LTC4308 in an application where all

of the pins have the same length. In this application, a

resistor is used to hold the ENABLE pin low during live

insertion, until the backplane control circuitry can enable

the device.

the precharge voltage and provide logic highs on SDAOUT

and SCLOUT for the start-up and connection circuitry to

connect the backplane to the card. To meet this require-

ment, always choose

V

_BUS(MIN)− V_THR(MAX)

R_PULLUP≤75k

Level Shifting Applications

V_THR(MAX)−1V

Systems requiring different supply voltages for the

backplane side and the card side can use the LTC4308

for bidirectional level shifting, as shown in Figures 4, 5,

and 7. The LTC4308 can level shift between bus pull-up

supplies as low as 0.9V to as high as 5.5V. Level shifting

allows newer designs that require lower voltage supplies,

such as EEPROMs and microcontrollers, the capability to

interface with legacy backplanes which may be operating

at higher supply voltages.

where V

is the maximum speciﬁed Logic Input

THR(MAX)

Threshold Voltage, V

.

THR

Further, on SDAIN and SCLIN and for heavily loaded

systems on SDAOUT and SCLOUT, where the selected

R

value causes the bus to rise at a rate slower than

PULLUP

0.8V/μs, users must also guarantee

V

_BUS(MIN)− V_THR(MAX)

R_PULLUP

≤

100μA

The LTC4308’s negative offset voltage from output to

input allow level shifting applications with high SDAOUT

Live Insertion and Capacitance Buffering Application

and SCLOUT V to effectively translate to the low voltage

OL

Figure 4 and 5 illustrate applications of the LTC4308 that

take advantage of the LTC4308’s Hot Swap™, capacitance

buffering and output pin precharge features. If the I/O

cardswerepluggeddirectlyintothebackplanewithoutthe

LTC4308buffer, allofthebackplaneandcardcapacitances

would add directly together, making rise time and fall time

SDAIN and SCLIN busses. Figure 7 shows an application

where 200Ω resistors, used to provide additional ESD

protection for the Temperature Sensor’s internal low

impedance pull-down device, generate high V on the

OL

SDAOUT and SCLOUT busses.

4308f

11

LTC4308

APPLICATIONS INFORMATION

Systems with Supply Voltage Droop

LTC4308 and LTC4301L Feature Comparison

In large 2-wire systems, the V voltages seen by devices

Although both, the LTC4308 and LTC4301L are func-

tionally similar Hot Swappable Bus Buffers designed for

Low Voltage Level Translation in 2-wire bus systems, the

LTC4308providesgreaterfeatures.Thesefeaturesinclude

automatic bus stuck low detection and recovery; rise time

acceleratorsontheoutputbusses,and–200mVIn-Outand

300mV Out-In offset voltages that are nearly independent

of pull-up resistors. These and other differences are listed

in Table 1 and must be accounted for if using the LTC4308

in LTC4301L applications.

CC

at various points in the system can differ by a few hundred

millivolts or more. This situation is modeled by a series

resistor in the V line, as shown in Figure 6. For proper

CC

operation, make sure that the V

is ≥ 2.3V.

CC(LTC4308)

Table 1: Differences Between LTC4301l and LTC4308

SPꢃCIFICATION LTC4301L LTC4308 COꢁꢁꢃNTS

Lower supply voltage allows greater compatibility with low voltage systems.

–200mV/300mV Negative output-to-input offset voltage provide better noise margin on low voltage bus.

V

2.7V

100mV

N/A

2.3V

CC(MIN)

OS(TYP)

I

t

8mA

Output bus rise time accelerators aid heavily loaded busses to meet rise time speciﬁcations.

PULLUPAC(TYP)

TIMEOUT

N/A

30ms

Stuck Bus Recovery automatically isolates the input bus from the output bus and attempts to recover

the output bus.

READY

–

READY functions identically. In addition, the LTC4308 will pull READY low to indicate when

disconnection has occurred.

CS/ENABLE

Active Low Active High

When replacing an LTC4301L with an LTC4308, invert the CS signal.

4308f

12

LTC4308

APPLICATIONS INFORMATION

BACKPLANE CARD

CONNECTOR CONNECTORS

MIXED VOLTAGE BACKPLANE

LOW VOLTAGE PERIPHERAL I/O CARD 1

3.3V

1V

C1

0.01μF

C2

0.01μF

R4

2.7k

R5

2.7k

R1

10k

R2

10k

R3

10k

V

CC

SDAOUT

SCLOUT

READY

SDA

SCL

READY

ENA1

SDAIN

SCLIN

CARD1_SDA

CARD1_SCL

LTC4308

GND

ENABLE

R6

10k

•

LOW VOLTAGE PERIPHERAL I/O CARD N

1V

C3

0.01μF

C4

0.01μF

R7

2.7k

R8

2.7k

V

CC

SDAOUT

SCLOUT

READY

SDAIN

SCLIN

CARDn_SDA

CARDn_SCL

LTC4308

GND

ENABLE

ENAn

R9

10k

4308 F03

Figure 4. The LTC4308 in an Application with Staggered Connectors.

BACKPLANE CARD

CONNECTOR CONNECTORS

MIXED VOLTAGE BACKPLANE

LOW VOLTAGE PERIPHERAL I/O CARD 1

3.3V

1V

C1

0.01μF

C2

0.01μF

R4

2.7k

R5

2.7k

R1

10k

R2

10k

R3

10k

V

CC

SDAOUT

SCLOUT

READY

SDA

SCL

READY

ENA1

SDAIN

SCLIN

CARD1_SDA

CARD1_SCL

LTC4308

GND

ENABLE

R6

10k

•

LOW VOLTAGE PERIPHERAL I/O CARD N

1V

C3

0.01μF

C4

0.01μF

R7

2.7k

R8

2.7k

V

CC

SDAOUT

SCLOUT

READY

SDAIN

SCLIN

CARDn_SDA

CARDn_SCL

LTC4308

GND

ENABLE

ENAn

R9

10k

4308 F04

Figure 5. The LTC4308 in an Application Where All the Pins ꢀave the Same Length.

4308f

13

LTC4308

TYPICAL APPLICATIONS

V

R

CC(LTC4308)

DROOP

V

CC

V

(BUS)

C1

0.01μF

R1

R2

R4

R5

R3

10k

10k 10k

V

CC

LTC4308

ENABLE

SDA1

SCL1

SDA2

SCL2

SDAOUT

SCLOUT

SDAIN

SCLIN

READY

GND

4308 TA02

Figure ±. System with Voltage Droop

1.2V

5V

0.01μF

V

CC

1.8k 1.8k

10k

LTC4308

ENABLE

200Ω*

SCLOUT

SCLIN

SCL

SDA

TEMPERATURE

SENSOR

SDAOUT SDAIN

5V

10k

READY

GND

READY

4308 TA03

*200Ω ARE ADDITIONAL ESD

PROTECTION RESISTORS

Figure 7. ꢀigh V_OLApplication

4308f

14

LTC4308

PACKAGE DESCRIPTION

DD Package

8-Lead Plastic DFN ꢂ3mm × 3mmM

(Reference LTC DWG # 05-08-1698)

R = 0.115

0.38 ± 0.10

TYP

5

8

0.675 ±0.05

3.5 ±0.05

2.15 ±0.05 (2 SIDES)

1.65 ±0.05

3.00 ±0.10

(4 SIDES)

1.65 ± 0.10

(2 SIDES)

PIN 1

TOP MARK

(NOTE 6)

PACKAGE

OUTLINE

(DD8) DFN 1203

4

1

0.25 ± 0.05

0.75 ±0.05

0.200 REF

0.25 ± 0.05

0.50 BSC

0.50

BSC

2.38 ±0.10

(2 SIDES)

2.38 ±0.05

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

ꢁS8 Package

8-Lead Plastic ꢁSOP

(Reference LTC DWG # 05-08-1660)

0.889 ± 0.127

(.035 ± .005)

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.52

(.0205)

REF

0.65

(.0256)

BSC

0.42 ± 0.038

(.0165 ± .0015)

8

7 6

5

TYP

RECOMMENDED SOLDER PAD LAYOUT

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

4.90 ± 0.152

(.193 ± .006)

DETAIL “A”

0.254

(.010)

0° – 6° TYP

GAUGE PLANE

1

2

3

4

0.53 ± 0.152

(.021 ± .006)

1.10

(.043)

MAX

0.86

(.034)

REF

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.22 – 0.38

(.009 – .015)

TYP

0.127 ± 0.076

(.005 ± .003)

0.65

(.0256)

BSC

MSOP (MS8) 0204

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

4308f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LTC4308

TYPICAL APPLICATION

The LTC4308 in a Level Shifting Application.

2.5V

1.8V

0.01μF

2.7k 2.7k

V

CC

LTC4308

SCLIN SCLOUT

MICRO-

CONTROLLER

SCL

SDA

SDAIN SDAOUT

ENABLE

3.3V

10k

READY

GND

READY

4308 TA04

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DꢃSCRIPTION

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Provides Automatic Clocking to Free Stuck I C Busses

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2/4 Selectable Downstream Busses, Stuck Bus Disconnect, Rise Time

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Time Accelerators, 5kV HBM ESD Tolerance

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High Deﬁnition Multimedia Interface (HDMI) Level

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ThinSOT is a trademark of Linear Technology Corporation

4308f

LT 0408 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

16

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC4308
厂家：	Linear
描述：	Low Voltage, Level Shifting Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery 低电压，电平转换热插拔2线总线缓冲器，具有阻塞总线恢复
文件：	总16页 (文件大小：170K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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