LTC4309IDE#TRPBF [Linear]
LTC4309 - Level Shifting Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C;型号: | LTC4309IDE#TRPBF |
厂家: | Linear |
描述: | LTC4309 - Level Shifting Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C |
文件: | 总16页 (文件大小:200K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC4309
Level Shifting Low Offset Hot
Swappable 2-Wire Bus Buffer
with Stuck Bus Recovery
DESCRIPTION
FEATURES
The LTC®4309 hot swappable 2-wire bus buffer allows
I/O card insertion into a live backplane without corrup-
tion of the data and clock busses. The LTC4309 provides
bidirectional buffering, keeping the backplane and card
n
Bidirectional Buffer Increases Fanout
n
60mV Buffer Offset Independent of Load
n
Optional Disconnect when Bus is Stuck Low
n
Prevents SDA and SCL Corruption During Live
Board Insertion and Removal from Backplane
capacitances isolated. Low offset and high V tolerance
OL
n
Level Shift 2.5V, 3.3V and 5V Busses
allows cascading of multiple devices on the clock and data
busses. If SDAOUT or SCLOUT are low for 30ms, FAULT
willpulllowindicatingastuckbuslowcondition.IfDISCEN
is tied high, the LTC4309 will automatically break the bus
connection and generate up to 16 clock pulses and a stop
bit in an attempt to free the bus. A connection will resume
if the stuck bus is cleared. If DISCEN is connected to GND,
the busses will remain connected with no clock or stop
bit generation. ACC input enables rise-time accelerators
for high capacitively loaded busses.
2
n
Compatible with Non-Compliant V I C Devices
OL
n
n
n
n
n
n
n
n
n
6kV ꢀuman Bodꢁ ꢂodel ꢃSD Ruggedness
Isolates Input SDA and SCL Lines from Output
2
2
Compatible with I C™, I C Fast-Mode and SMBus
READY Open Drain Output
FAULT Open Drain Output
1V Precharge on All SDA and SCL Lines
Optional Rise Time Accelerators
High Impedance SDA, SCL Pins for V = 0
Available in Small 12-Pin DFN (4mm x 3mm) and
16-Lead SSOP Packages
CC
During insertion, the SDA and SCL lines are precharged to
1V to minimize bus disturbances. When driven high, the
ENABLE input allows the LTC4309 to connect after a stop
bit or bus idle. Driving ENABLE low breaks the connection
between SDAIN and SDAOUT, SCLIN and SCLOUT. READY
is an open drain output which indicates that the backplane
and card sides are connected.
APPLICATIONS
n
Live Board Insertion
n
Servers
n
Capacitance Buffer/Bus Extender
RAID Systems
ATCA
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents including
6356140, 6650174, 7032051.
n
n
TYPICAL APPLICATION
3.3V
Rising ꢃdge from Asserted Low
5V
0.01μF
1000
10k 10k
0.01μF
V
CC
V
CC
V
V
CC2
ENABLE
LTC4309
SCLIN SCLOUT
CC2
ENABLE
LTC4309
SCLIN SCLOUT
800
600
400
EN
ACC
ACC
2.7k 2.7k
100k
10k
10k
SCL2
LOW
OFFSET
SDAOUT
SDAIN
SCL1
SDA1
SDA2
SDAIN SDAOUT
SDAIN SDAOUT
3.3V
10k
5V
200
0
3.3V
5V
10k
DISCEN
READY
DISCEN
READY
10k
10k
0
200
300
400
500
600
100
100ns/DIV
FAULT
FAULT
FAULT
FAULT
4309 G01
GND
GND
BACKPLANE
CONNECTOR
CARD
CONNECTOR
4309 TA01
4309fa
1
LTC4309
ABSOLUTE MAXIMUM RATINGS
(Note 1, 6)
V , V
to GND............................................–0.3 to 6V
Operating Temperature
CC CC2
SDAIN, SCLIN, SDAOUT, SCLOUT, READY,
LTC4309C ................................................ 0°C to 70°C
LTC4309I.............................................. –40°C to 85°C
Storage Temperature Range (DE)........... –65°C to 125°C
Storage Temperature Range (GN).......... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
ENABLE, FAULT, ACC, DISCEN .......................–0.3 to 6V
Maximum Sink Current (SDA, SCL, FAULT, READY)
I
......................................................................50mA
SINK
GN Package ...................................................... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
ENABLE
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
ENABLE
DISCEN
SCLOUT
SCLIN
ACC
1
2
3
4
5
6
12
11
V
V
CC
NC
V
CC2
DISCEN
SCLOUT
SCLIN
ACC
CC2
10 SDAOUT
SDAOUT
SDAIN
FAULT
NC
13
9
8
7
SDAIN
FAULT
READY
GND
NC
GND
READY
DE12 PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
T
= 125°C, θ = 43°C/W
JA
JMAX
EXPOSED PAD (PIN 13) PCB CONNECTION TO GND IS OPTIONAL
T
= 150°C, θ = 110°C/W
JA
JMAX
ORDER INFORMATION
LꢃAD FRꢃꢃ FINISꢀ
LTC4309CDE#PBF
LTC4309IDE#PBF
LTC4309CGN#PBF
LTC4309IGN#PBF
TAPꢃ AND RꢃꢃL
PART ꢂARKING*
4309
PACKAGꢃ DꢃSCRIPTION
TꢃꢂPꢃRATURꢃ RANGꢃ
0°C to 70°C
LTC4309CDE#TRPBF
LTC4309IDE#TRPBF
LTC4309CGN#TRPBF
LTC4309IGN#TRPBF
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
16-Lead Plastic SSOP
4309
–40°C to 85°C
0°C to 70°C
4309
4309I
16-Lead Plastic SSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4309fa
2
LTC4309
ELECTRICAL CHARACTERISTICS The l denotes the specifications which applꢁ over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, VCC2 = 3.3V, unless otherwise noted.
SYꢂBOL
PARAꢂꢃTꢃR
CONDITIONS
ꢂIN TYP ꢂAX UNITS
l
l
l
l
l
l
V
V
Positive Supply Voltage
2.3
1.8
5.5
5.5
11
V
V
CC
Input Side Accelerator Supply Voltage
CC2
I
I
I
I
V
V
V
V
Input Supply Current Enabled
Input Supply Current Disabled
V
CC
V
CC
V
CC
V
CC
= V
= V
= V
= V
= 5.5V, V
= V = 0V (Note 2)
SCLIN
7
mA
μA
μA
μA
CC
CC
CC2
CC2
CC2
CC2
SDAIN
= 5.5V, SDA = SCL = 5.5V, ENABLE = OV
= 5.5V, V = V = 0V (Note 2)
900 1400
190 250
140 180
SD
CC
Input Supply Current Enabled
Input Supply Current Disabled
CC2
SD2
CC2
CC2
SDAIN
SCLIN
= 5.5V, SDA = SCL = 5.5V, ENABLE = OV
Propagation Delaꢁ and Rise Time Accelerators
t
t
t
SDA/SCL Propagation Delay High to Low
SDA/SCL Propagation Delay Low to High
SDA/SCL Rise Time
C
C
C
= 50pF, 2.7k to V on SDA, SCL, (Note 3, 4), (Figure 1)
85
ns
ns
ns
PHL
PLH
RISE
LOAD
LOAD
LOAD
CC
= 50pF, 2.7k to V on SDA, SCL, (Note 3, 4), (Figure 1)
10
CC
= 100pF, 10k to V on SDA, SCL, V = 5V V = 5V,
CC2
30 300
CC
CC
(Note 3, 5), (Figure 1)
= 100pF, 10k to V on SDA, SCL, V = 5V (Note 3, 5),
t
I
SDA/SCL Fall Time
C
30 300
8
ns
FALL
LOAD
CC
CC
(Figure 1)
Transient Boosted Pull-up Current
Positive Transition > 0.8V/μS on SDA, SCL, V = 3.3V (Note 7)
5
mA
PULLUPAC
CC
Start-Up Circuitrꢁ
l
l
l
V
Precharge Voltage
SDA, SCL Open
0.8 1.0 1.2
55 95 175
V
μs
V
PRE
t
Bus Idle Time
IDLE
V
ENABLE Threshold Voltage
ENABLE Threshold Voltage Hysteresis
ACC, DISCEN Threshold Voltage
ENABLE, ACC, DISCEN Input Currents
ENABLE Delay Off-On
ENABLE Rising Edge
(Note 3)
0.8 1.4
2
THR_EN
V
100
mV
V
THR_EN(HYST)
V
0.5 0.7
1
THR_CTRL
l
I
t
t
t
t
ENABLE, ACC, DISCEN from 0 to V
(Figure 1)
0.1
95
10
10
10
5
μA
μs
ns
ns
ns
V
CTRL
CC
PLH_EN
ENABLE Delay On-Off
(Note 3), (Figure 1)
(Note 3), (Figure 1)
(Note 3), (Figure 1)
PHL_EN
READY Delay On-Off
PLH_READY
PHL_READY
READY Delay Off-On
l
l
V
READY Output Low Voltage
READY Off Leakage Current
I
= 3mA, V = 2.3V
0.4
5
OL_READY
OFF_READY
READY
CC
I
V
CC
= READY = 5.5V
0.1
μA
Timing Characteristics
2
f
I C Maximum Operating Frequency
(Note 3)
(Note 3)
400 600
kHz
μs
I2C, MAX
BUF
t
Bus Free Time Between Stop and Start
Condition
1.3
t
Hold Time After (Repeated)
Start Condition
(Note 3)
100
ns
HD, STA
t
t
t
t
Repeated Start Condition Set-Up Time
Stop Condition Set-Up Time
Data Hold Time Input
(Note 3)
(Note 3)
(Note 3)
(Note 3)
0
0
ns
ns
ns
ns
SU, STA
SU, STO
HD, DATI
SU, DAT
0
Data Set-Up Time
100
Input-Output Connection
l
V
OS
Input-Output Offset Voltage
2.7k to V on SDA, SCL, Driven SDA, SCL = 0.2V
20
60 100
mV
CC2
V
THR
SDA, SCL Logic Input Threshold Voltage
V
CC
V
CC
≥ 2.9V
< 2.9V
1.4 1.65 1.9
1.1 1.35 1.6
V
V
4309fa
3
LTC4309
The l denotes the specifications which applꢁ over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, VCC2 = 3.3V, unless otherwise noted.
SYꢂBOL
PARAꢂꢃTꢃR
CONDITIONS
ꢂIN TYP ꢂAX UNITS
V
SDA, SCL Logic Input Threshold Voltage (Note 3)
Hysteresis
50
mV
THR(HYST)
C
IN
Digital Input Capacitance SDAIN,
SDAOUT, SCLIN, SCLOUT
(Note 3)
10
pF
l
l
I
Input Leakage Current
SDA, SCL, ACC, DISCEN Pins
5
μA
V
LEAK
V
Output Low Voltage
SDA, SCL Pins, I
= 4mA, Driven SDA/SCL = 0.2V, V =
CC
0
0.4
OL
SINK
V
= 2.7V
CC2
l
l
2.7k to V on SDA, SCL, Driven SDA/SCL = 0.1V,
CC
120 170 205
1.2
mV
V
CC
V
= V
= 3.3V
CC2
V
Buffer Input Logic Low Voltage
ILMAX
Bus Stuck Low Timeout
l
l
l
t
Bus Stuck Low Timer
SDAOUT, SCLOUT = OV
I = 3mA
FAULT
25
30
35
0.4
5
ms
V
TIMEOUT
V
FAULT Output Low Voltage
FAULT Off Leakage Current
OL_FAULT
OFF_FAULT
I
0.1
μA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Test performed with connection circuity active.
Note 3: Determined by design, not subject to test.
setup and hold times must be adjusted accordingly. Please see the
Operation Section of the datasheet.
Note 5: Measure points are 0.3 • V and 0.7 • V
.
CC
CC
Note 6: All currents into pins are positive, all voltages are referenced to
GND, unless otherwise specified.
Note 7: I
varies with temperature and V voltage as shown in the
PULLUPAC
CC
Note 4: For larger equivalent bus capacitance, the skew increases, and
Typical Performance Characteristics section.
TIMING DIAGRAMS
ꢃNABLꢃ and RꢃADY Timing
t
t
PLH_READY
PLH_EN
PHL_READY
t
PHL_EN
t
ENABLE
CONNECT
READY
4309 TD01
SDA/SCL Propagation Delaꢁs, Rise and Fall Times
t
t
FALL
RISE
t
t
t
t
FALL
PLH
PHL
RISE
SDAIN/SCLIN
SDAOUT/SCLOUT
4309 TD02
Figure 1. Timing Diagrams
4309fa
4
LTC4309
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = 3.3V, VCC2 = 3.3V unless
otherwise noted.
ICC ꢃnabled Current vs
Temperature
ICC Disabled Current vs
Temperature
ICC2 ꢃnabled Current vs
Temperature
8
7.5
7
20
16
12
8
220
200
180
160
140
120
100
V
CC
V
CC
V
CC
= 5.5V
= 3.3V
V
V
= 5.5V
= 3.3V
V
= 5.5V
CC
CC
CC
6.5
6
V
= 3.3V
= 2.3V
CC
CC
V
= 2.3V
0
4
5.5
5
0
–25
0
50
–50
75
100
25
–50
–25
25
50
75
100
–50
–25
25
50
75
100
0
TEMPERATURE (oC)
TEMPERATURE (°C)
TEMPERATURE (oC)
4309 G02
4309 G04
4309 G03
ICC2 Disabled Current vs
Temperature
Input-Output ꢀigh to Low
Propagation Delaꢁ vs Temperature
Boost Pull-Up Current vs
Temperature
30
25
20
15
10
5
140
130
120
110
100
90
160
140
130
120
110
100
90
C
C
= 50pF
= 1nF
PULLUPIN
IN
OUT
R
C
= C
PULLUPIN
= 50pF
= R
IN
OUT
V
= 5.5V
R
= 2.7kΩ
CC
PULLUPOUT
= R
PULLUPOUT
= 2.7kΩ
V
= 5.5V
CC
V
= 5.5V
= 3.3V
CC
V
= 3.3V
= 2.3V
CC
CC
V
V
= 2.3V
CC
CC
CC
80
V
70
V
= 3.3V
V
= 2.3V
75
CC
0
60
–50
–25
0
25
50
100
–50
0
25
50
75
100
–50
–25
0
25
50
75
100
–25
TEMPERATURE (oC)
TEMPERATURE (°C)
TEMPERATURE (°C)
4309 G07
4309 G05
4309 G06
Offset Voltage vs Pull-Up
Resistance
Input-Output ꢀigh to Low Propagation
Delaꢁ vs Output Capacitance
160
150
140
130
120
110
100
90
70
66
62
58
54
50
V
= 5.5V
CC
V
= 2.3V
= 3.3V
CC
C
R
R
= 50pF
PULLUPIN
PULLUPOUT
IN
V
C
= 0.1V
C
PULLUPIN
OL
IN = OUT
R
= 2.7k7
V
CC
= 50pF
80
= 2.7k7
= 2.7kΩ
70
0
200
400
600
800
1000
0
4
6
8
10
2
OUTPUT CAPACITANCE (pF)
PULL-UP RESISTANCE (kΩ)
4309 G08
4309 G09
4309fa
5
LTC4309
PIN FUNCTIONS
(Dꢃ12/GN16)
ꢃNABLꢃ(Pin1/Pin1):ConnectionEnableInput. This1.4V
digitalthresholdinputpinenablesordisablestheLTC4309.
FornormaloperationpullorconnectENABLEhigh. Driving
ENABLE below the 0.8V threshold isolates SDAIN from
SDAOUT, SCLIN from SCLOUT, asserts READY low, and
prohibitsautomaticclockandstopbitgenerationduringa
fault condition. A rising edge on ENABLE after a fault has
occurred forces a connection between SDAIN, SDAOUT
RꢃADY (Pin 7/Pin 9): Connection Ready Status Output.
This open-drain N-channel MOSFET pin pulls low when
ENABLEislow,whenthestart-upandconnectionsequence
describedintheOperationsectionhasnotbeencompleted,
or when the LTC4309 disconnects the input and output
pins due to a bus stuck low condition. READY goes high
whenENABLEishighandconnectionismadebetweenthe
input and output pins. Connect a pull-up resistor, typically
10k, from this pin to the bus pull-up supply. This pin can
be left open if unused.
and SCLIN, SCLOUT. Connect to V if unused.
CC
DISCꢃN (Pin 2/Pin 3 ): Bus Stuck Low Disconnect Enable
Input. This pin, when high, allows the stuck low bus
timeoutcircuitrytodisconnectthebusinafaultcondition.
When connected to GND, this pin disables the circuitry
that disconnects the bus under a fault condition; however,
the FAULT pin will still go low.
FAULT (Pin8/Pin11):BusStuckLowTimeoutOutput.This
opendrainN-channelMOSFEToutputpullslowafter30ms
when there is a bus stuck low condition on the output pins
oftheLTC4309.InnormaloperationFAULT ishigh.Connect
a pull-up resistor, typically 10k, from this pin to the bus
pull-up supply. This pin can be left open if unused.
SCLOUT (Pin 3/Pin 4): Serial Clock Output. Connect this
pintoaSCLbussegmentwherebusstucklowrecoveryis
desired. If the output rise time accelerators are enabled, a
pull-upresistorshouldbeconnectedbetweenthispinand
SDAIN (Pin 9/Pin 12): Serial Clock Input. Connect this
pin to a SDA bus segment where isolation from bus stuck
low issues is desired. If the input accelerator is enabled, a
pull-up resistor should be connected between this pin and
a bus supply greater than or equal to V . Bus supplies
CC
can be lower than V if the output rise time accelerators
CC
a bus supply greater than or equal to V . Bus supplies
CC2
are disabled. See Application Information section for
can be lower than V
if the input rise time accelerators
are disabled. See Application Information section for
CC2
detailed bus pull-up supply options.
detailed bus pull-up supply options.
SCLIN (Pin 4/Pin 5): Serial Clock Input. Connect this pin
to a SCL bus segment where isolation from bus stuck
low issues is desired. If the input rise time accelerator is
enabled, a pull-up resistor should be connected between
SDAOUT(Pin10/Pin13):SerialClockOutput. Connectthis
pin to a SCL bus segment where bus stuck low recovery is
desired. If the output rise time accelerators are enabled, a
pull-up resistor should be connected between this pin and
this pin and a bus supply greater than or equal to V
.
CC2
Bus supplies can be lower than V if the input rise time
CC2
a bus supply greater than or equal to V . Bus supplies
CC
accelerators are disabled. See Application Information
section for detailed bus pull-up supply options.
can be lower than V if the output rise time accelerators
CC
are disabled. See Application Information section for
detailed bus pull-up supply options.
ACC (Pin 5/Pin 6): Rise Time Accelerator Control Input.
Thisnominal0.7Vthresholdinputpinenablesanddisables
allrisetimeacceleratorsontheSDAandSCLpins.Connect
ACC to GND to enable all four rise time accelerators or
V
(Pin 11/Pin 14): Supply Voltage Input for SDAIN and
CC2
SCLIN Rise Time Accelerator Circuitry. V
supplies the
CC2
rise time accelerator circuitry on the input side. Bypass
this pin to GND with a capacitor of at least 0.01μF and
connectACCtoV todisableallfourrisetimeaccelerators.
CC
Connect ACC to V
to GND to enable the accelerators
CC2
place close to V for best results. If V
is connected
CC2
CC2
on SDAOUT and SCLOUT only.
to GND, the input side rise time accelerator circuitry is
disabled, regardless of ACC.
GND (Pin 6/Pin 8): Device Ground. Connect this pin to a
ground plane for best results.
4309fa
6
LTC4309
PIN FUNCTIONS
(Dꢃ12/GN16)
V
(Pin 12/Pin 16): Supply Voltage Input. Bypass this
ꢃXPOSꢃDPAD(Pin13Dꢃ12PackageOnlꢁ):ExposedPad
may be left open or connected to device ground.
CC
pin to GND with a capacitor of at least 0.01μF and place
close to V for best results.
CC
BLOCK DIAGRAM
V
CC2
V
CC
V
CC2
V
CC
8mA
8mA
CONNECT
I
I
BOOSTSDA
BOOSTSDA
SDAIN
SDAOUT
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
100k
100k
PRECHARGE
V
V
CC2
CC
PC
CONNECT
PC
CONNECT
8mA
8mA
100k
100k
CONNECT
I
I
BOOSTSCL
BOOSTSCL
SCLIN
SCLOUT
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
+
–
1.65V/1.6V
1.35V/1.3V
ACC
30ms
TIMER
+
–
1.65V/1.6V
1.35V/1.3V
FAULT
DISCEN
I
I
BOOSTSCL
BOOSTSDA
+
–
LOGIC
1.65V/1.6V
1.35V/1.3V
CONNECT
READY
GND
+
–
PC CONNECT
1.65V/1.6V
1.35V/1.3V
ENABLE
+
–
CONNECT
1.4V/1.3V
95μs
DELAY
4309 BD
UVLO
4309fa
7
LTC4309
OPERATION
Start-Up
All four rise time accelerators can be disabled by connect-
ing ACC to V . To activate the rise time accelerators on
CC
When the LTC4309 first receives power on its V pin,
CC
only SDAOUT and SCLOUT, connect both ACC and V
CC2
eitherduringpoweruporliveinsertion,itstartsinanunder
to ground. The rise time accelerators are also internally
disabled until the sequence of events described in the
start-up section have been completed, as well as during
automatic clocking and stop bit generation for a bus stuck
low recovery event.
voltage lockout (UVLO) state, ignoring any activity on the
SDA or SCL pins until V rises above 2V. This ensures
CC
the LTC4309 does not try to function until enough supply
voltage is present.
During this time, the 1V precharge circuitry is actively
forcing 1V through 100k nominal resistors to the SDA
and SCL pins. Because the I/O card is being plugged
into a live backplane, the voltage on the backplane SDA
Connection Circuitrꢁ
Oncetheconnectioncircuitryisactivated,thefunctionality
of the input and output bus of the respective SDA or SCL
pins are identical. A low forced on either output or input
pin at any time results in both pin voltages forced low.
and SCL busses may be anywhere between 0V and V .
CC
Precharging the SCL and SDA pins to 1V minimizes the
worst-case voltage differential these pins will see at the
moment of contact, therefore minimizing the amount of
disturbance caused by the I/O card.
2
The LTC4309 is tolerant of I C bus DC logic low voltages
up to the V specification of 0.3 • V .
IL
CC
When the LTC4309 senses a rising edge on the bus, with
a slew rate greater than 0.8V/μs, the internal pull-down
device for the respective bus is deactivated at bus volt-
ages as low as 0.48V. This methodology maximizes the
effectiveness of the rise time accelerator circuitry and
maintains compatibility with other devices in the LTC4300
bus buffer family. Care must be taken to ensure devices
participating in clock stretching or arbitration are capable
of forcing logic low voltages below 0.48V at the LTC4309’s
SDA and SCL pins.
Once the LTC4309 exits from UVLO, it monitors both the
input and output pins for either a stop bit or a bus idle
condition to indicate the completion of data transactions.
When both sides are idle or one side has a stop bit while
the other is idle, the connection circuitry is activated,
joining the SDA and SCL busses on the input side with
those on the output side.
Rise Time Accelerators
OnceconnectionhasbeenestablishedifACCisconnected
togroundandV ispoweredfromasupplyvoltagegreater
A high occurs when all devices on the input and output
pins release high. These important features ensures the
CC2
than or equal to 1.8V, the rise time accelerator circuits on
allfourSDAandSCLpinsareenabled. Duringpositivebus
transitions of at least 0.8V/μs, the rise time accelerators
provide strong, slew-limited pull-up currents to force the
bus voltage to rise at a rate of 100V/μs. Enabling the rise
time accelerators allows users to choose larger bus pull-
up resistors, reducing power consumption and improving
logic low noise margins, or design with bus capacitances
2
I C specification protocols such as clock stretching, clock
synchronization, arbitration, and acknowledge function
seamlessly in all cases as specified, regardless of how the
devices in the system are connected to the LTC4309.
Another key feature provided by the connection circuitry
is input and output bus capacitance isolation through
bidirectional buffering. Because of this isolation, the
waveforms on the input busses look slightly different than
the corresponding output bus waveforms, as described
below.
2
beyond those specified in the I C specifications.
To ensure the rise time accelerators are properly activated
when the rise time accelerators are enabled, users should
choose bus pull-up resistors that guarantee the bus will
rise on its own at a rate of at least 0.8V/μs. See the Ap-
plication Information section for determining the correct
pull-up resistor size.
Input to Output Offset Voltage
When a logic low voltage is driven on any of the LTC4309’s
data or clock pins, the LTC4309 regulates the voltage on
the other side of the device to a slightly higher voltage,
4309fa
8
LTC4309
OPERATION
OUTPUT SIDE
50pF
INPUT SIDE
150pF
1V/DIV
INPUT SIDE
150pF
OUTPUT SIDE
50pF
1V/DIV
1V/DIV
1V/DIV
4307 F01
4307 F02
200ns/DIV
200ns/DIV
Figure 2. Input-Output Rising ꢃdge Waveforms
Figure 3. Input-Output Falling ꢃdge Waveforms
Bus Stuck Low Timeout
typically60mV. Thisoffsetisnearlyindependentofpull-up
current. (See Typical Performance curves.)
When SDAOUT or SCLOUT is low, an internal timer is
started. The timer is only reset by the respective pin
going high. If the bus stuck low does not go high within
30ms (typical), the FAULT pin pulls low indicating a bus
Propagation Delaꢁs
During a rising edge, the rise time on each side is de-
termined by the bus pull-up resistor and the equivalent
capacitance on the line. If the pull-up resistors are the
same, a difference in rise time occurs which is directly
proportional to the difference in capacitance between the
stuck low condition. If DISCEN is connected to V , the
CC
connection circuitry is disabled, breaking the connection
between the respective input and output pins. In addition,
after at least 40μs, up to 16 clock pulses at 8.5kHz (typi-
cal) is generated on the SCLOUT pin by the LTC4309 in an
attempt to free the stuck low bus. Once the clock pulses
have completed, a stop bit is generated on the SCLOUT
and SDAOUT pins to reset all devices on the bus.
two sides. This effect is displayed in Figure 2 for V and
CC
V
= 5.5V and a 10k pull-up resistor on each side (50pF
CC2
on one side and 150pF on the other). Since the output side
has less capacitance than the input, it rises faster and the
effective propagation delay is negative.
If the stuck low SDAOUT or SCLOUT recovers to a logic
high, the FAULT flag clears, and the LTC4309 waits for
either a stop bit or a bus idle condition to activate the
connection circuitry to reconnect the input and output
busses.
There is a finite propagation delay through the connec-
tion circuitry for falling waveforms. Figure 3 shows the
falling edge waveforms for the same pull-up resistors and
equivalent capacitance conditions as used in Figure 2. An
externalN-channelMOSFETdevicepullsdownthevoltage
on the side with 150pF capacitance; LTC4309 pulls down
the voltage on the opposite side, with a delay of 85ns. This
delayisalwayspositiveandisafunctionofsupplyvoltage,
temperature and the pull-up resistors and equivalent bus
capacitances on both sides of the bus.
If DISCEN is connected to GND, the FAULT pin will pull
low, but the connection circuitry will not be disabled,
leaving the input and output busses connected. Also, no
clock or stop bit is generated.
When powering up into a bus stuck low condition, the
connection circuitry connecting the SDA and SCL busses
ontheI/Ocardwiththoseonthebackplaneisnotactivated.
30msafterUVLO, theFAULTpinpullslowindicatingabus
stuck low condition and automatic clocking and stop bit
generation takes place as described above.
The Typical Performance Characteristics section shows
PropagationDelayasafunctionoftemperatureandvoltage
for 2.7k pull-up resistors and 50pF equivalent capacitance
on both sides of the part. Also, the Propagation Delay as
a function of Output Capacitance curve shows that larger
outputcapacitancestranslatetolongerdelays.Usersmust
quantify the difference in propagation times for a rising
edge versus a falling edge in their systems and adjust
setup and hold times accordingly.
RꢃADY Digital Output
This pin provides a digital flag which is low when either
ENABLE is low, the start-up sequence described earlier
in this section has not been completed, or the LTC4309
4309fa
9
LTC4309
OPERATION
has disconnected the input and output busses due to a
bus stuck low condition. READY goes high when ENABLE
is high and start-up is complete. The pin is driven by an
open drain pull-down device capable of sinking 3mA
while holding 0.4V on the pin. Connect a resistor to the
bus pull-up supply to provide the pull-up.
ꢃNABLꢃ
When the ENABLE pin is driven below 0.8V with respect
to the LTC4309’s ground, the input pin is disconnected
from the output pin and the READY pin is internally pulled
low. When the pin is driven above 2V, the part waits for
data transactions on both the input and output pins to be
complete (as described in the Start-Up section) before
connecting the two sides. At this time the internal pull-
down on READY releases.
FAULT Digital Output
This pin provides a digital flag which is low when SDA
or SCL is low for 30ms (typical). The pin is driven by an
open drain pull-down capable of sinking 3mA while hold-
ing 0.4V on the pin. Connect a resistor from FAULT to the
bus pull-up supply to provide the pull-up.
ArisingedgeonENABLEafterafaulthasoccurredforcesa
connectionbetweenSDAIN,SDAOUTandSCLIN,SCLOUT,
even if the bus stuck low conditions has not been cleared.
At this time, the 30ms timer is reset, but not disabled.
APPLICATIONS INFORMATION
Live Insertion and Capacitance Buffering Application
resistor is used to hold the ENABLE pin low during live
insertion, until the backplane control circuitry can enable
the device.
Figures 4 and 5 illustrate applications of the LTC4309 that
take advantage of the LTC4309’s Hot SwapTM, capacitance
buffering and precharge features. If the I/O cards were
plugged directly into the backplane without the LTC4309
buffer, all of the backplane and card capacitances would
add directly together, making rise time and fall time re-
quirements difficult to meet. Placing an LTC4309 on the
edge of each card, however, isolates the card capacitance
from the backplane. For a given I/O card, the LTC4309
drives the capacitance of everything on the card and the
backplanemustdriveonlythecapacitanceoftheLTC4309,
which is less than 10pF.
Repeater/Bus ꢃxtender Applications
Users who wish to connect two 2-wire systems separated
byadistancecandosobyconnectingtwoLTC4309sback-
2
to-back, as shown in Figure 6. The I C specification allows
for 400pF maximum bus capacitance, severely limiting
the length of the bus. The SMBus specification places no
restrictiononbuscapacitance,butthelimitedimpedances
ofdevicesconnectedtothebusrequiresystemstoremain
small if rise time and fall time specifications are to be met.
In this situation, the differential ground voltage between
the two systems may limit the allowed distance, because
a valid logic low voltage with respect to the ground at one
Figure 4 shows the LTC4309 used in the typical staggered
connectorapplication,whereV andGNDarethelongest
CC
“early power” pins. The “early power” pins ensure the
LTC4309 is initially powered and forcing a 1V precharge
voltage on the medium length SDA and SCL pins before
they contact to the backplane busses. Coupled with
ENABLE as the shortest pin, passively pulled to ground
by a resistor, the staggered approach provides additional
time for transients associated with live insertion to settle
before the LTC4309 can be enabled.
endofthesystemmayviolatetheallowedV specification
OL
with respect to the ground at the other end. In addition,
the connection circuitry offset voltages of the back-to-
back LTC4309s add together, directly contributing to the
same problem.
Figure 7 further illustrates a repeater application. In
AdvancedTCAapplications, thebuspull-upresistancecan
be quite small. Since there is no effect on the offset due
Figure 5 shows the LTC4309 in an application where all
of the pins have the same length. In this application, a
Hot Swap is a trademark of Linear Technology Corporation.
4309fa
10
LTC4309
APPLICATIONS INFORMATION
to the pull-up impedance, multiple LTC4309 buffers can
be used in a single system. This allows the user to divide
the line and device capacitances into more sections with
buffering and meet rise and fall times.
If the rise time accelerators are enabled, the bus pull-up
supply can be greater than or equal to V for the output
CC
busses and accordingly, the input pull-up supply can
be greater than or equal to V
for the input busses.
CC2
This ensures the LTC4309’s rise time accelerators do
not source current through the pull-up resistors into the
pull-up supply. If the rise time accelerator circuitries are
disabled, the bus pull-up supply can be as low as 2V for
The LTC4309 disconnects when both bus I/O’s are above
0.48V and rising. In systems with large ground bounce,
if many devices are cascaded, the 0.48V threshold can be
exceeded, and the transients associated with the ground
bouncecanappeartobearisingedge.Underthiscondition,
the LTC4309 with inputs above 0.48V may disconnect.
V
≥ 2.9V and for V < 2.9V, the bus pull-up supply can
CC
CC
be as low as 1.7V. The bound on the lower supply limit
exists to ensure the bus signal range exceeds the logic
Level Shifting Applications
input threshold voltage, V
.
THR
Systems requiring different supply voltages for the
backplane side and the card side can use the LTC4309
for bidirectional level shifting, as shown in Figure 6. The
LTC4309 can level shift between bus pull-up supplies as
low as 1.7V, with the accelerators disabled, to as high as
5.5V. Level shifting allows newer designs that require low
voltagesupplies,suchasEEPROMsandmicrocontrollers,
the capability to interface with legacy backplanes which
may be operating at higher supply voltages.
Resistor Pull-Up Value Selection
Toguaranteetherisetimeacceleratorsareactivatedduring
a rising edge, the bus must rise on its own with a positive
slew rate of at least 0.8V/μs. To achieve this, choose a
maximum resistor value R
using the formula:
PULLUP
ns
V
(VBUS(MIN) – 0.8V)•1250
RPULLUP ꢀ
CBUS
Sꢁstems with Supplꢁ Voltage Droop
Where R
is the pull-up resistor value in kilo ohms,
PULLUP
V
C
is the minimum bus pull-up supply voltage and
BUS(MIN)
Inlarge2-wiresystems,thesupplyvoltagesseenbydevices
at various points in the system can differ by a few hundred
millivolts or more. For proper operation, make sure that
is the equivalent bus capacitance in pico-Farads
BUS
(pF).
the V
is ≥ 1.8V, and V
≥ 2.3V.
To estimate the value of C , use a general rule of 20pF
CC2(LTC4309)
CC(LTC4309)
BUS
of capacitance per device on the bus (10pF for the device
Additional Pull-Up Supplꢁ Options
and 10pF for interconnect).
In typical applications, a pull-up resistor connected from
In addition, R
must be strong enough to overcome
PULLUP
the LTC4309’s bus output pins to V and bus input pins
theprechargevoltageandprovidelogichighsonSDAOUT
and SCLOUT for the start-up and connection circuitry to
connect the backplane to the card. Regardless of the bus
capacitance, always choose
CC
to V or V , if V is grounded, is sufficient. However,
CC2
CC
CC2
foruniqueapplications,additionalflexibilityisavailablefor
bus pull-up supplies other than V or V . One example
CC
CC2
is shown in Figure 8. The expanded bus pull-up range is
VBUS(MAX) – VTHR
dependent on the user configuration of the rise time ac-
RPULLUP ꢀ
celerators and the supply voltage, V .
100μA
CC
4309fa
11
LTC4309
APPLICATIONS INFORMATION
BACKPLANE
CONNECTOR
CARD
CONNECTORS
BACKPLANE
I/O PERIPHERAL CARD 1
V
CC
C1
0.01μF
C2
0.01μF
R5
10k
R6
10k
V
CC2
V
R1
10k
R2
10k
R3
10k
R4
10k
CC
V
DISCEN
CC2
SDAIN
SDAOUT
SCLOUT
ACC
SDA
SCL
CARD 1_SDA
CARD 1_SCL
LTC4309
SCLIN
FAULT
FAULT
READY
ENA1
READY
ENABLE
GND
R7
10k
I/O PERIPHERAL CARD N
C3
0.01μF
C4
0.01μF
R8
10k
R9
10k
V
CC
DISCEN
SDAOUT
SCLOUT
ACC
V
CC2
CARD N_SDA
CARD N_SCL
SDAIN
SCLIN
FAULT
LTC4309
READY
ENABLE
ENAN
GND
R10
10k
4309 F01
Figure 4. The LTC4309 in an Application with a Staggered Connector.
4309fa
12
LTC4309
APPLICATIONS INFORMATION
BACKPLANE
CONNECTOR
CARD
CONNECTORS
BACKPLANE
I/O PERIPHERAL CARD 1
V
CC
C1
0.01μF
C2
0.01μF
R5
10k
R6
10k
V
CC2
V
R1
10k
R2
10k
R3
10k
R4
10k
CC
V
DISCEN
CC2
SDAIN
SDAOUT
SCLOUT
ACC
SDA
SCL
CARD 1_SDA
CARD 1_SCL
LTC4309
SCLIN
FAULT
FAULT
READY
ENA1
READY
ENABLE
GND
R7
10k
I/O PERIPHERAL CARD N
C3
0.01μF
C4
0.01μF
R8
10k
R9
10k
V
CC
DISCEN
SDAOUT
SCLOUT
ACC
V
CC2
CARD N_SDA
CARD N_SCL
SDAIN
SCLIN
FAULT
LTC4309
READY
ENABLE
ENAN
GND
R10
10k
4309 F01
Figure 5. The LTC4309 in an Application Where All the Pins ꢀave the Same Length.
2.5V
3.3V
R1
5V
C1
0.01μF
C2
C3
C4
0.01μF
R2
R3
R4
R7
R8
R9
R10
0.01μF
0.01μF
10k 10k
10k 10k
10k 10k
10k 10k
R5
2.7k
R6
2.7k
V
V
V
V
CC
CC
CC2
CC2
DISCEN
ENABLE
READY
FAULT
DISCEN
ENABLE
READY
FAULT
LTC4309
LTC4309
SDA1
SCL1
SDA2
SCL2
SDAOUT
SDAIN
SDAIN
SDAOUT
SCLOUT
SCLIN
GND
SCLIN
GND
SCLOUT
ACC
ACC
4309 F04
Figure 6. The LTC4309 in a Level Shifting Repeater/Bus ꢃxtender Application.
4309fa
13
LTC4309
APPLICATIONS INFORMATION
V
V
CC
CC
C1
0.01MF
C2
0.01MF
C3
0.01MF
C4
0.01MF
C5
0.01MF
C6
0.01MF
R1
R2
R3
R4
R7
R8
R9
R10 R11 R12
10k
R13 R14
2.7k 2.7k
2.7k 2.7k
10k 10k
10k 10k
2.7k 2.7k 10k
R5
2.7k
R6
2.7k
V
V
V
V
V V
CC CC2
CC CC2
CC2 CC
DISCEN
ENABLE
READY
FAULT
DISCEN
DISCEN
ENABLE
READY
FAULT
ENABLE
READY
FAULT
LTC4309
LTC4309
LTC4309
SDA1
SDA2
SDAOUT SDAIN
SDAIN SDAOUT
SDAOUT SDAIN
SCLOUT SCLIN
SCLIN SCLOUT
SCLOUT SCLIN
SCL1
SCL2
ACC GND
GND ACC
ACC GND
4309 F05
Figure 7. The LTC4309 in a Repeater Application. The LTC4309’s Low Offset Allows Cascading of ꢂultiple Devices.
2.5V
3.3V
5V
C2
0.01μF
R3
R4
R5
R6
10k 10k
10k 10k
R1
2.7k
R2
2.7k
V
CC2
V
CC
DISCEN
ENABLE
READY
FAULT
LTC4309
SDA1
SCL1
SDA2
SCL2
SDAIN
SDAOUT
SCLIN
GND
SCLOUT
ACC
4309 F06
Figure 8. The LTC4309 in a level shifting application where the bus supplies are different from VCC
.
4309fa
14
LTC4309
PACKAGE DESCRIPTION
Dꢃ/Uꢃ Package
12-Lead Plastic DFN (4mm x 3mm)
(Reference LTC DWG # 05-08-1695)
0.70 p0.05
3.60 p0.05
2.20 p0.05 (2 SIDES)
1.70 p0.05
PACKAGE OUTLINE
0.25 p 0.05
0.50
BSC
3.30 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.40 p 0.10
4.00 p0.10
(2 SIDES)
R = 0.115
TYP
7
12
R = 0.05
TYP
3.00 p0.10 1.70 p 0.05
(2 SIDES)
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
CHAMFER
(UE12/DE12) DFN 0905 REV
C
6
0.25 p 0.05
1
0.75 p0.05
0.200 REF
0.50
BSC
3.30 p0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 p.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 p.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 p .004
(0.38 p 0.10)
s 45o
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0o – 8o TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
4309fa
InformationfurnishedbyLinearTechnologyCorporationisbelievedtobeaccurateandreliable.However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC4309
TYPICAL APPLICATION
5V to 3.3V Level Translator
3.3V
5V
C1
0.01MF
C2
0.01MF
R3
R4
R5
R6
10k 10k
10k 10k
R1
10k
R2
10k
V
V
CC
CC2
DISCEN
ENABLE
READY
FAULT
LTC4309
SDA1
SCL1
SDA2
SCL2
SDAIN
SDAOUT
SCLIN
GND
SCLOUT
ACC
4309 F07
RELATED PARTS
PART NUꢂBꢃR
DꢃSCRIPTION
COꢂꢂꢃNTS
LTC1380/LTC1393
Single-Ended 8-Channel/Differential 4-Channel Analog
MUX with SMBus Interface
Low R : 35Ω Single Ended/70Ω Differential, Expandable to 32
ON
Single or 16 Differential Channels
LTC1427-50
Micropower, 10-Bit Current Output DAC with SMBus
Interface
Precision 50uA+/–2.5% Tolerance Over Temperature, 4 Selectable
SMBus Addresses, DAC Powers up at Zero or Midscale
LTC1623
Dual High Side Switch Controller with SMBus Interface
SMBus Interface 10-Bit Rail to Rail Micropower DAC
SMBus Accelerator
8 Selectable Addresses/16 Channel Capability
DNL < 0.75 LSB Max, 5-Lead SOT-23 Package
LTC1663
2
LTC1694/LTC1694-1
Improved SMBus/I C Rise-Time, Ensures Data Integrity with Multiple
2
SMBus/I C Devices
2
LTC1695
LT1786F
LTC1840
SMBus/I C Fan Speed Controller in ThinSOT™
0.75Ω PMOS 180mA Regulator, 6-Bit DAC
SMBus Controlled CCFL Switching Regulator
1.25A, 200kHz, Floating or Grounded Lamp Configurations
Two 100μA 8-Bit DACs, Two Tach Inputs, Four GPIO
2
Dual I C Fan Speed Controller
LTC4300A-1/
LTC4300A-2/
LTC4300A-3
Hot Swappable 2-Wire Bus Buffers
–1: Bus Buffer with READY, ACC and ENABLE
–2: Dual Supply Bus Buffer with READY and ACC
–3: Dual Supply Bus Buffer with READY and ENABLE
LTC4301
Supply Independent Hot Swappable 2-Wire Bus Buffer
Supply Independent
LTC4301L
Hot Swappable 2-Wire Bus Buffer with Low Voltage Level Allows Bus Pull-Up Voltages as Low as 1V on SDA and SCL
IN
IN
Translation
LTC4302-1/
LTC4302-2
Addressable 2-Wire Bus Buffer
Address Expansion, GPIO, Software Controlled
2
LTC4303
LTC4304
Hot Swappable 2-Wire Bus Buffer with Stuck Bus
Recovery
Provides Automatic Clocking to Free Stuck I C Busses
LTC4305
LTC4306
2 or 4-Channel, 2 Wire Bus Multiplexers with Capacitance 2 or 4 Selectable Downstream Busses, Stuck Bus Disconnect, Rise
Buffering
Time Accelerators, Fault Reporting, 10kV HBM ESD Tolerance
LTC4307
Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck
Bus Recovery
60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery, Rise
Time Accelerators, 5kV HBM ESD Tolerance
LTC4307-1
High Definition Multimedia Interface (HDMI) Level Shifting 60mV Buffer Offset, 3.3V to 5V Level Shifting,
2-Wire Bus Buffer 5kV HBM ESD Tolerance
ThinSOT is a trademark of Linear Technology Corporation
4309fa
LT 0108 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
© LINEAR TECHNOLOGY CORPORATION 2006
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号:
LTC4309IDE-PBF
Level Shifting Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery
Linear
LTC4309IDE-TRPBF
Level Shifting Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery
Linear
LTC4309IGN-PBF
Level Shifting Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery
Linear
LTC4309IGN-TRPBF
Level Shifting Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery
Linear
©2020 ICPDF网 联系我们和版权申明