LTC4312CDE#PBF [Linear]
LTC4312 - Pin-Selectable, 2-Channel, 2-Wire Multiplexer with Bus Buffers; Package: DFN; Pins: 14; Temperature Range: 0°C to 70°C;
| 型号： | LTC4312CDE#PBF |
| 厂家： | 
Linear |
| 描述： | LTC4312 - Pin-Selectable, 2-Channel, 2-Wire Multiplexer with Bus Buffers; Package: DFN; Pins: 14; Temperature Range: 0°C to 70°C 光电二极管 |
| 文件： | 总20页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4312
Pin-Selectable, 2-Channel,
2-Wire Multiplexer
with Bus Buffers
FEATURES
DESCRIPTION
n
1:2 Multiplexer/Switch for 2-Wire Bus
The LTC®4312 is a hot-swappable 2-channel 2-wire bus
multiplexer that allows one upstream bus to connect to
any combination of downstream busses or channels.
An individual enable pin controls each connection. The
LTC4312 provides bidirectional buffering, keeping the up-
streambuscapacitanceisolatedfromthedownstreambus
n
Bidirectional Buffer for SDA and SCL Lines
n
High Noise Margin with V = 0.3•V
IL
CC
n
n
ENABLE Pins Connect SDA and SCL Lines
Selectable Rise Time Accelerator Current and
Activation Voltage
Level Shift 1.5V, 1.8V, 2.5V, 3.3V and 5V Busses
Prevents SDA and SCL Corruption During Live Board
Insertion and Removal from Backplane
Stuck Bus Disconnect and Recovery
Compatible with I C, I C Fast Mode and SMBus
4kV Human Body Model (HBM) ESD Ruggedness
14-Lead 4mm × 3mm DFN and 16-Lead MSOP
Packages
n
n
capacitances. The high noise margin allows the LTC4312
2
to be interoperable with I C devices that drive a high V
OL
(> 0.4V). The LTC4312 supports level translation between
1.5V, 1.8V, 2.5V, 3.3V and 5V busses. The hot-swappable
nature of the LTC4312 allows I/O card insertion into, and
removal from, a live backplane without corruption of the
data and clock busses.
n
n
n
n
2
2
If both data and clock are not simultaneously high at
least once in 45ms and DISCEN is high, a FAULT signal is
generated indicating a stuck bus low condition, the input
is disconnected from each enabled output channel and up
to 16 clocks are generated on the enabled downstream
busses. A three state ACC pin enables input and output
side rise time accelerators of varying strengths and sets
APPLICATIONS
n
Telecommunications Systems Including ATCA
n
Address Expansion
n
Level Translator
Capacitance Buffers/Bus Extender
Live Board Insertion
PMBus
n
the V
voltage.
IL,RISING
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents, including
6356140, 6650174, 7032051, 7478286.
n
TYPICAL APPLICATION
3.3V
3.3V
Rising Edge from Asserted Low
with Level Translation
0.01μF
0.01μF
V
CC
V
CC2
10k
10k
10k
10k
6V
C
C
+ C
= 100pF
SCLOUT2
SCLOUT1
SCLIN
= 50pF
SCLIN
SDAIN
SCLIN
SCLOUT2
5V
SDAIN
ENABLE1
ENABLE2
ENABLE1
ENABLE2
SCLOUT1
SDAOUT1
SCLOUT1
SDAOUT1
SCLOUT1
SCLIN
3.3V
5V
3.3V
LTC4312
10k
10k
10k
ACC
SCLOUT2
SDAOUT2
SCLOUT2
SDAOUT2
DISCEN
FAULT
0V
FAULT
GND
200ns/DIV
4312 TA01b
4314 TA01a
4312f
1
LTC4312
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage
Output DC Sink Currents
FAULT.................................................................50mA
Operating Ambient Temperature Range
V , V ................................................. –0.3V to 6V
CC CC2
Input Voltages
ACC, DISCEN, ENABLE1-2....................... –0.3V to 6V
Input/Output Voltages
LTC4312C ................................................ 0°C to 70°C
LTC4312I..............................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
SDAIN, SCLIN, SCLOUT1-2,
SDAOUT1-2, FAULT ................................. –0.3V to 6V
MSOP .............................................................. 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
V
1
2
3
4
5
6
7
14 DISCEN
CC
DISCEN 1
16 ACC
15 GND
14 NC
13
12
11
SCLOUT1
SDAOUT1
SDAIN
ACC
V
2
CC
GND
SCLOUT1 3
SDAOUT1 4
SDAIN 5
SCLIN 6
SCLOUT2 7
SDAOUT2 8
13 NC
15
V
CC2
12 V
CC2
SCLIN
10 FAULT
11 FAULT
10 ENABLE1
SCLOUT2
SDAOUT2
9
8
ENABLE1
ENABLE2
9
ENABLE2
MS PACKAGE
16-LEAD PLASTIC MSOP
DE14 PACKAGE
14-LEAD (4mm = 3mm) PLASTIC DFN
T
= 150°C, θ = 120°C/W, θ = 21°C/W
JA JC
JMAX
T
= 125°C, θ = 43°C/W, θ = 5°C/W
JA JC
JMAX
EXPOSED PAD (PIN #15) PCB CONNECTION TO GND IS OPTIONAL
ORDER INFORMATION
LEAD FREE FINISH
LTC4312IDE#PBF
LTC4312IMS#PBF
LTC4312CDE#PBF
LTC4312CMS#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
LTC4312IDE#TRPBF
LTC4312IMS#TRPBF
LTC4312CDE#TRPBF
LTC4312CMS#TRPBF
4312
4312
4312
4312
14-Lead (4mm × 3mm) DFN
16-Lead Plastic MSOP
14-Lead (4mm × 3mm) DFN
16-Lead Plastic MSOP
0°C to 70°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4312f
2
LTC4312
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = VCC2 = 3.3V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply/Start-Up
l
l
l
V
V
V
Input Supply Range
2.9
5.5
5.5
5.5
V
V
V
CC
2-Wire Bus Supply Voltage
2.25
2.25
DD, BUS
CC2
Output Side Accelerator Supply
Range
l
l
l
l
l
I
I
I
t
Input Supply Current
Input Supply Current
One or Both V
= V = V = 5.5V (Note 3)
6.0
1.6
0.35
60
7.3
2.2
0.5
110
2.3
200
9
mA
mA
mA
μs
CC
ENABLE1-2
CC
CC2
V
= 0V; V = V = 5.5V (Note 3)
3.5
0.6
200
2.6
CC(DISABLED)
CC2
ENABLE1-2
CC
CC2
V
CC2
Supply Current
One or Both V
= V = V = 5.5V (Note 3)
ENABLE1-2 CC CC2
UVLO Delay
UVLO
V
UVLO Threshold
V
TH_UVLO
V
UVLO Threshold Hysteresis
Voltage
mV
CC_UVLO(HYST)
Buffers
l
l
l
l
l
l
l
l
l
l
l
l
V
V
V
V
Buffer Offset Voltage
Buffer Offset Voltage
Buffer Offset Voltage
Buffer Offset Voltage
I
I
I
I
I
I
I
I
= 4mA, Driven V = 50mV
SDAIN,SCLIN
130
15
90
15
50
15
35
15
220
60
280
120
260
110
195
110
170
100
mV
mV
mV
mV
mV
mV
mV
mV
V
OS1(SAT)
OS2(SAT)
OS
OL
OL
OL
OL
OL
OL
OL
OL
= 500μA, Driven V
= 50mV
SDAIN,SCLIN
= 4mA, Driven V
= 50mV
190
55
SDAOUT,SCLOUT
= 500μA, Driven V
= 50mV
SDAOUT,SCLOUT
= 4mA, Driven V
= 200mV
130
55
SDAIN,SCLIN
= 500μA, Driven V
= 200mV
SDAIN,SCLIN
= 4mA, Driven V
= 200mV
95
OS2
SDAOUT,SCLOUT
= 500μA, Driven V
= 200mV
50
SDAOUT,SCLOUT
V
V
Buffer Input Logic Low Voltage
Buffer Input Logic Low Voltage
SDA, SCL Pins (Notes 4, 5)
0.3•V
0.33•V
0.6
0.36•V
0.7
IL,FALLING
MIN
MIN
MIN
MIN
SDA, SCL Pins; ACC Grounded
0.5
0.3•V
V
IL,RISING
SDA, SCL Pins; ACC Open or High (Notes 4, 5)
0.33•V
0.36•V
10
V
MIN
MIN
I
Input Leakage Current
Input Capacitance
SDA, SCL Pins; V , V = 0V, 5.5V
μA
pF
LEAK
CC CC2
C
SDA, SCL Pins (Note 6)
<20
IN
Rise Time Accelerators
dV/dt (RTA) Minimum Slew Rate Requirement SDA, SCL Pins; V = V
l
l
l
l
l
l
= 5V
0.1
0.7
0.2
0.8
0.4
0.9
V/μs
V
CC
CC2
CC2
V
Rise Time Accelerator DC
Threshold Voltage
SDA, SCL Pins; V = V
= 5V, ACC Grounded
RTA(TH)
CC
ACC Open or High, V = V
= 5V (Note 4)
0.36•V
100
0.4•V
0.44•V
MIN
V
CC
CC2
MIN
MIN
ΔV
ACC
Buffers Off to Accelerator On
Voltage
SDA, SCL Pins; V = V = 5V, ACC Grounded
CC2
200
mV
mV
mA
CC
ACC Open, V = V
= 5V (Note 4)
0.05•V
20
0.07•V
35
CC
CC2
MIN
MIN
I
Rise Time Accelerator Pull-Up
Current
SDA, SCL Pins; V = V
= 5V, ACC Grounded
45
4
RTA
CC
CC2
(Note 7)
l
l
l
ACC Open, V = V
= 5V (Note 7)
CC2
1.5
0.8
0.8
3
mA
CC
Enable/Control
V
DISCEN Threshold Voltage
1.4
20
2
2
1
V
mV
V
DISCEN(TH)
ΔV
DISCEN Hysteresis Voltage
ENABLE1-2 Threshold Voltage
ENABLE1-2 Hysteresis Voltage
ENABLE1-2 High to Buffer Active
DISCEN(HYST)
V
1.4
20
EN(TH)
ΔV
mV
μs
EN(HYST)
t
0.56
LH_EN
4312f
3
LTC4312
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = VCC2 = 3.3V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
0.1
23
MAX
10
40
5
UNITS
μA
l
l
l
I
I
I
Input Leakage Current
ACC High, Low Input Current
DISCEN = ENABLE1-2 = 5.5V
LEAK
V
= 5V, V
= 5V, 0V
ACC
μA
ACC(IN, HL)
ACC(IN, Z)
CC
CC
Allowable Leakage Current in
Open State
V
= 5V
μA
l
l
I
ACC High Z Input Current
V
V
= 5V
= 5V
5
μA
V
ACC(EN, Z)
CC
V
ACC Input Low Threshold
Voltages
0.2•V
0.3•V
0.8•V
0.4•V
0.9•V
ACC(L, TH)
CC
CC
CC
CC
CC
l
V
ACC Input High Threshold
Voltages
V
CC
= 5V
0.7•V
V
ACC(H,TH)
CC
CC
Stuck Low Timeout Circuitry
l
l
l
t
Bus Stuck Low Timer
SDAOUT or SCLOUT < 0.3•V
35
45
55
0.4
5
ms
V
TIMEOUT
CC
V
FAULT Output Low Voltage
FAULT Leakage Current
I
= 3mA
FAULT(OL)
FAULT
I
0.1
μA
FAULT(OH)
2
I C Interface Timing
2
l
f
t
t
I C Frequency Max
SDA, SCL Fall Delay
SDA, SCL Fall Times
(Note 6)
400
kHz
ns
SCL(MAX)
V
CC
CC
= 3V to 5.5V, C
= 50pF, I
= 50pF, I
= 1mA (Note 6)
= 1mA (Note 6)
60
10
100
PDHL
f
BUS
BUS
BUS
V
= 3V to 5.5V, C
ns
BUS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive and all voltages are referenced to
GND unless otherwise indicated.
Note 5: V is tested for the following (V , V ) combinations:
IL CC CC2
(2.9V, 5.5V), (5.5V, 2.25V), (3.3V, 3.3V) and (5V, 0V).
Note 6: Guaranteed by design and not tested.
Note 7: Measured in a special DC mode with V
= V
+ 1V.
SDA,SCL
RTA(TH)
The transient I
seen during rising edges when ACC is low will depend
RTA
on the bus loading condition and the slew rate of the bus. The LTC4312’s
internal slew rate control circuitry limits the maximum bus rise rate to
Note 3: SDAIN, SCLIN pulled low.
75V/μs by controlling the transient I
.
RTA
Note 4: V
= minimum of V and V
if V
> 2.25V else V = V .
MIN CC
MIN
CC
CC2
CC2
4312f
4
LTC4312
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = 3.3V unless otherwise noted.
ICC Enabled Current
vs Supply Voltage
ICC Disabled (ENABLE1-2 Low)
Current vs Supply Voltage
Multiplexer Switch Resistance
RMUX vs Temperature
8.0
7.5
7.0
6.5
3.0
2.5
2.0
1.5
1.0
10
9
V
= 0V
V
= 0V
I
= 4mA
DS
SDAIN, SCLIN
SDAIN, SCLIN
V
= 3.3V
CC2
8
7
V
= 5V
CC2
6
5
4
2
3
4
5
6
2
3
4
5
6
–50
–25
0
25
50
75
100
V
(V)
V
CC
(V)
TEMPERATURE (°C)
CC
4312 G01
4312 G02
4312 G03
Input to Output Offset Voltage
vs Bus Current for Different Driven
Input Voltage Levels
Buffer High to Low Propagation
Delay vs Output Capacitance
Buffer DC IOL vs Temperature
10
9
350
300
250
200
150
100
50
250
200
150
100
50
V
= V
= 3.3V
CC2
V
= V
BUS
= V = 5V
DD, BUS
V
= V
= V
= 5V
DD, BUS
CC
CC
CC2
CC
CC2
R
= 2.7kΩ
DRIVEN V
= 50mV
SDAIN,SCLIN
8
V
= 0.4V
SDAIN,SCLIN
100mV
7
≥200mV
6
V
= 0.4V
SDAOUT,SCLOUT
5
4
0
0
–50 –25
0
25
50
75 100 125
0
2
4
6
0
500
1000
1500
TEMPERATURE (°C)
I
(mA)
BUS
C
(pF)
BUS
4312 G04
4312 G06
4312 G05
Output to Input Offset Voltage
vs Bus Current for Different
Driven Output Voltage Levels
Rise Time Accelerator Current
vs Temperature
tRISE(30%–70%) vs CBUS
350
300
250
200
150
100
50
16
14
12
10
8
150
125
100
75
V
= V
= V
CC2 DD, BUS
V
= V
= V
= 5V
V
= V
= V
CC2 DD, BUS
CC
SDA,SCL
CC
CC2
DD, BUS
CC
V
ꢀꢁꢀꢂꢃꢄꢀtꢀV
ACC = 0V
DD,BUS
ACC = 0V
= 400pF
BUS
C
BUS
5V
R
= 10k
DRIVEN V
= 50mV
SDAOUT, SCLOUT
5V
3.3V
100mV
50
3.3V
≥200mV
25
0
6
0
0
2
4
6
–50
–25
0
25
50
75
100
0
200
400
C (pF)
BUS
600
800
I
(mA)
TEMPERATURE (°C)
BUS
4312 G07
4312 G08
4312 G09
4312f
5
LTC4312
PIN FUNCTIONS
ACC: Three-State Acceleration and Buffer Mode Selector.
This pin controls the turn on voltage of the rise time ac-
celerators and their current strength on both the input and
output sides. It also controls the turn-off voltage of the
buffers.SeeTable1intheApplicationsInformationsection.
SCLIN: Upstream Serial Bus Clock Input/Output. Connect
this pin to the SCL line on the upstream bus. Connect an
external pull-up resistor or current source between this
pin and the bus supply. Do not leave open.
SCLOUT1-SCLOUT2:DownstreamSerialBusClockInput/
Output Channels 1-2. Connect pins SCLOUT1-SCLOUT2
to the SCL lines on the downstream channels 1-2, respec-
tively. When in use, an external pull-up resistor or current
source is required between the pin and the corresponding
bus supply. Leave open or tie to GND and connect the
corresponding ENABLE pin to GND, if unused.
DISCEN: Disconnect Stuck Bus Enable Input. When this
pin is high, stuck busses are automatically disconnected
and FAULT is pulled low after a timeout period of 45ms.
Up to sixteen clock pulses are subsequently applied to the
stuck output channels. When DISCEN pin is low, stuck
busses are neither disconnected nor clocked but FAULT
is pulled low. Connect to GND if unused.
SDAIN: Upstream Serial Bus Data Input/Output. Connect
this pin to the SDA line on the upstream bus. Connect an
external pull-up resistor or current source between this
pin and the bus supply. Do not leave open.
ENABLE1-ENABLE2: Connection Enable Inputs. These
input pins enable or disable the corresponding output
channel. Driving an ENABLE pin low isolates SDAIN and
SCLIN from the corresponding SDAOUT and SCLOUT.
Only enable and disable a channel when all busses are
idle. During a bus stuck low fault condition, a falling edge
on all ENABLE pins followed by a rising edge on one or
more ENABLE pins forces a connection from SDAIN to
the selected SDAOUT and SCLIN to the selected SCLOUT.
Connect to GND if unused.
SDAOUT1-SDAOUT2: Downstream Serial Bus Data Input/
OutputChannels1-2.ConnectpinsSDAOUT1-SDAOUT2to
the SDA lines on downstream channels 1-2, respectively.
Wheninuse, anexternalpull-upresistororcurrentsource
is required between the pin and the corresponding bus
supply. Leave open or tie to GND and connect the cor-
responding ENABLE pin to GND, if unused.
Exposed Pad (DFN Package Only): Exposed pad may be
left open or connected to device ground.
V : Power Supply Voltage. Power this pin from a sup-
CC
ply between 2.9V and 5.5V. Bypass with at least 0.01μF
FAULT:StuckBusFaultOutput. ThisopendrainN-channel
MOSFET output pulls low if a simultaneous high on the
enabled SCLOUT and SDAOUT channels does not occur in
45ms. In normal operation FAULT is high. Connect a pull
up resistor, typically 10k, from this pin to the bus pull-up
supply. Leave open or tie to GND if unused.
to GND.
V
: Output Side Rise Time Accelerator (RTA) Power
CC2
Supply Voltage. When powering V , use a supply volt-
CC2
age ranging from 2.25V to 5.5V and bypass with at least
0.01μF to GND. If the downstream busses are powered
from multiple supply voltages, power V
from the low-
CC2
GND: Device Ground.
est supply voltage. Output side RTAs are active if V
≥
CC2
2.25V and ACC is low or open. Grounding V
disables
CC2
output side RTAs.
4312f
6
LTC4312
BLOCK DIAGRAM
V
CC
V
CC2
I
RTA
I
RTA
RTA
CO1
CO2
SCLOUT1
SCLOUT2
SCLIN
V
CC2
SLEW RATE
DETECTOR
0.2V/μs
I
CIN
SLEW RATE
DETECTOR
0.2V/μs
V
CC
V
V
CC2
I
RTA
I
I
RTA
MUX
SDAIN
DO1
SDAOUT1
CC2
SLEW RATE
DETECTOR
0.2V/μs
DIN
EN1
SLEW RATE
DETECTOR
0.2V/μs
RTA
+
–
CONNECT
DO2
EN2
SDAOUT2
VCC2
V
V
IL
IL
+
–
+
–
V
V
IL
IL
LOGIC
45ms
TIMER
+
–
GND
110μs
TIMER
UVLO
V
CC
FAULT
ACC
I
/I
BOOST_SCL BOOST_SDA
DISCEN
ENABLE1
ENABLE2
4314 BD
4312f
7
LTC4312
OPERATION
TheBlockDiagramshowsthemajorfunctionalblocksofthe
V
and V
voltages. For V
< 1.8V, V
is the V
MIN CC
CC
CC2
CC2
LTC4312.TheLTC4312isa1:2multiplexerwithcapacitance
voltage. The LTC4312 is designed to sink a minimum
total bus current I of 4mA while holding a V of 0.4V.
2
bufferingforI Csignals.Capacitancebufferingisachieved
OL
OL
by use of back to back buffers on the clock and data chan-
nelswhichisolatetheSDAINandSCLINcapacitancesfrom
the SDAOUT and SCLOUT capacitances respectively. All
SDA and SCL pins are fully bidirectional. The high noise
If multiple output channels are enabled, the bus current of
all enabled channels needs to be summed to get the total
bus current. See the Typical Performance Characteristics
curves for I as a function of temperature.
OL
2
margin allows the LTC4312 to operate with I C devices
A high occurs when all devices on the input and output
sides release high. Once the bus voltages rise above the
that drive a non-compliant high V . Multiplexing is done
OL
usingN-channelMOSFETsthatarecontrolledbydedicated
V
level,whichisdeterminedbythestateoftheACC
IL,RISING
ENABLE pins. When enabled, rise time accelerator pull-up
pin, the buffers are turned off. The rise time accelerators
are turned on at a slightly higher voltage. The rise time
accelerators accelerate the rising edges of the SDA/SCL
currents I
turn on during rising edges to reduce sys-
RTA
tem rise time. In a typical application the input side bus
is pulled up to V and the output side busses are pulled
CC
inputs and selected outputs up to voltages of 0.9•V and
CC
up to V
although these are not requirements. V is
CC2
CC
CC2
0.8•V
respectively, provided that the busses on their
CC2
the primary power supply to the LTC4312. V and V
CC
ownarerisingataminimumrateof0.2V/μsasdetermined
serve as the input and output side rise time accelerator
by the slew rate detectors. ACC is a 3-state input that con-
supplies respectively. Grounding V disables the output
CC2
trols V
, the rise time accelerator turn-on voltage
IL,RISING
side accelerators. The multiplexer N-channel MOSFET
and the rise time accelerator pull-up strength.
gates of the enabled channels are driven to V
is > 1.8V, otherwise they are driven to V .
if V
CC2
CC2
The LTC4312 detects a bus stuck low (fault) condition
when both clock and data busses are not simultaneously
high at least once in 45ms. The voltage monitoring for a
stuck low condition is done on the common internal node
of the clock and data outputs. Hence a stuck low condition
is detected only if it occurs on an enabled output channel.
When a stuck bus occurs, the LTC4312 asserts the FAULT
flag. If DISCEN is tied high, the LTC4312 also disconnects
the input and output sides. After waiting at least 40μs, it
generatesuptosixteen5.5kHzclockpulsesontheenabled
SCLOUT pins and a stop bit to attempt to free the stuck
bus. If the bus recovers high before 16 clocks are issued,
the LTC4312 ceases issuing clocks and generates a stop
bit. If DISCEN is tied low, a stuck bus event only causes
FAULTflagassertion.Disconnectionoftheinputandoutput
sides and clock generation do not occur. Once the stuck
bus recovers and the fault has been cleared, in order for a
connectiontobeestablishedbetweentheinputandoutput
sides, both ENABLE pins need to be driven low followed
by the assertion high of the desired ENABLE pins. When
powering into a stuck low condition, the LTC4312 upon
exiting UVLO will connect the input and output sides for
45ms until a stuck bus timeout event is detected.
CC
When the LTC4312 first receives power on its V pin, it
CC
starts out in an undervoltage lockout mode (UVLO) until
110μsafterV exceeds2.3V. Duringthistime, thebuffers
CC
and rise time accelerators are disabled, the multiplexer
gates are off and the LTC4312 ignores transitions on the
clockanddatapinsindependentofthestateoftheENABLE
pins. V
transitions from a high to a low or vice-versa
CC2
across a 1.8V threshold also cause the LTC4312 to dis-
able the buffers, rise time accelerators and transmission
gates and to ignore the clock and data pins until 110μs
after that transition. Assuming that the LTC4312 is not in
UVLO mode, when one or both ENABLEs are asserted,
the LTC4312 activates the connection circuitry between
the SDAIN/SCLIN inputs and selected output channels.
The input rise time accelerators and the output rise time
accelerators of the selected channels are also enabled at
this time. When a SDA/SCL input pin or output pin on an
enabled output channel is driven below the V
IL,FALLING
level of 0.33•V , the buffers are turned on and the
MIN
logic low level is propagated though the LTC4312 to
the other side. For V
> 1.8V, V
is the lower of the
CC2
MIN
4312f
8
LTC4312
APPLICATIONS INFORMATION
The LTC4312 is a 1:2 pin selectable I C multiplexer that
provides a high noise margin, capacitance buffering and
level translation capability on its clock and data pins. Rise
time accelerators accelerate rising edges to enable opera-
tion at high frequencies with heavy loads. These features
are illustrated in the following subsections.
2
Table 1. ACC Control of the Rise Time Accelerator Current IRTA
and Buffer Turn-Off Voltage VIL,RISING
ACC
Low
I
V
V
IL,RISING
RTA
RTA(TH)
Strong
3mA
0.8V
0.6V
Open
High
0.4•V
0.33•V
0.33•V
MIN
MIN
MIN
None
N/A
Rise Time Accelerators and DC Hold-Off Voltage
The ACC pin has a resistive divider between V and GND
CC
to set its voltage to 0.5•V if left open. In the current
CC
Once the LTC4312 has exited UVLO and a connection has
been established between the SDA and SCL inputs and
outputs, the rise time accelerators on both the input and
output sides of the SDA and SCL busses are activated
source accelerator mode, the LTC4312 provides a 3mA
constant current source pull-up. In the strong mode, the
LTC4312 sources pull-up current to make the bus rise at
75V/μs (typical). The strong mode current is therefore
directly proportional to the bus capacitance. The LTC4312
is capable of sourcing up to 45mA of current in the strong
mode. The effect of the rise time accelerator strength is
shown in the SDA waveforms in Figures 1 and 2 for iden-
tical bus loads for a single enabled output channel. The
rise time accelerator supplies 3mA and 10mA of pull-up
based on the state of the ACC pin and the V
supply
CC2
voltage. During positive bus transitions of at least 0.2V/
μs, the rise time accelerators provide pull-up currents to
reduce rise time. Enabling the rise time accelerators al-
lows users to choose larger bus pull-up resistors, reduc-
ing power consumption and improving logic low noise
margins, to design with bus capacitances outside of the
current(I )respectivelyinthecurrentsourceandstrong
2
RTA
I C specification or to switch at a higher clock frequency.
modes for the bus conditions shown in Figures 1 and 2.
The rise time accelerator turn-on voltage in the strong
mode is also lower as compared to the current source
mode.Foridenticalbusloadingconditions,thebusreturns
high faster in Figure 1 compared to Figure 2 because of
The ACC pin sets the turn-off threshold voltage for the
buffers, the turn-on voltage for the rise time accelerators,
and the rise time accelerator pull-up current strength. The
ACC functionality is shown in Table 1. Set ACC open or
high when a high noise margin is required such as when
both the higher I
and the lower turn-on voltage of the
2
RTA
the LTC4312 is used in a system having I C devices with
rise time accelerator. In each figure, note that the input
and output rising waveforms are nearly coincident due to
the input and output busses having nearly identical bus
current and capacitance.
V
> 0.4V.
OL
C
= C
= 200pF
C = C
= 200pF
= 10kΩ
IN
OUT
= 10kΩ
IN OUT
R
R
BUS
ACC = 0
= V = 5V
BUS
ACC = OPEN
V = V = 5V
CC
V
CC
CC
CC2
SDAOUT1
SDAIN
SDAOUT1
SDAIN
0V
0V
0V
0V
4312 F01
4312 F02
500ns/DIV
500ns/DIV
Figure 1. Bus Rising Edge for the
Strong Accelerator Mode
Figure 2. Bus Rising Edge for the
Current Source Accelerator Mode
4312f
9
LTC4312
APPLICATIONS INFORMATION
If V
is tied low, the output side rise time accelerators
Supply Voltage Considerations in Level Translation
Applications
CC2
are disabled independent of the state of the ACC pin.
ACC tied high disables input and output RTAs. Using a
Care must be taken to ensure that the bus supply voltages
combination of the ACC pin and the V
voltage allows
CC2
ontheinputandoutputsidesaregreaterthan0.9•V and
CC
the user independent control of the input and output side
rise time accelerators. The rise time accelerators are also
0.8•V , respectively, to ensure that the bus is not driven
CC2
above the bus supplies by the rise time accelerators. This
internally disabled during power-up and V transitions,
CC2
is usually accomplished in a level shifting application by
as described in the Operation section, as well as during
automatic clocking and stop bit generation for a bus stuck
low recovery event.
tyingV totheinputbussupplyandV totheminimum
CC
CC2
bus supply on the output side as shown in Figure 3.
IfV isgrounded,themultiplexerpassgatesarepowered
CC2
The rise time accelerators when activated pull the bus up
from V . In this case the minimum output bus supply
CC
to 0.9•V on the input side of the SDA and SCL lines.
CC
of the enabled channels should be greater than or equal
On the output side the SDAOUT and SCLOUT lines are
to V to prevent cross-conduction between the enabled
CC
pulled up by the rise time accelerators to 0.8•V . For
CC2
outputchannels.ThisisshowninFigure4.GroundingV
CC2
V
voltagesapproaching2.3V,accelerationoftheoutput
CC2
as shown in Figure 4 disables the output side rise time
accelerators independent of the state of the ACC pin. The
input rise time accelerators in this configuration continue
to be controlled by the ACC pin and can be enabled inde-
bus may not be seen all the way to 0.8•V
due to the
CC2
threshold voltage of the NFET pass device.
pendently. In Figure 4, ACC is left open to obtain a high V
and a 3mA rise time accelerator current on the input side.
IL
3.3V
3.3V
C1
0.01μF
C2
0.01μF
R1
10k
R2
10k
R4
10k
R5
10k
V
CC
V
CC2
SCLIN
SDAIN
SCLIN
SDAIN
ENABLE1
ENABLE2
ENABLE1
ENABLE2
SCLOUT1
SDAOUT1
SCLOUT1
SDAOUT1
5V
LTC4312
3.3V
R6
10k
R7
10k
R3
10k
ACC
SCLOUT2
SDAOUT2
SCLOUT2
SDAOUT2
DISCEN
FAULT
FAULT
GND
4312 F03
Figure 3. Connection of the LTC4312 in a Level Shift Application. VCC2 Is
Less Than or Equal to the Minimum Bus Supply Voltage on the Output Side
4312f
10
LTC4312
APPLICATIONS INFORMATION
3.3V
3.3V
C1
0.01μF
C2
0.01μF
R1
10k
R2
10k
R4
10k
R5
10k
V
CC
V
CC2
SCLIN
SDAIN
SCLIN
SDAIN
ENABLE1
ENABLE2
ENABLE1
ENABLE2
SCLOUT1
SDAOUT1
SCLOUT1
SDAOUT1
5V
LTC4312
3.3V
R6
10k
R7
10k
ACC
R3
10k
SCLOUT2
SDAOUT2
SCLOUT2
SDAOUT2
DISCEN
FAULT
FAULT
GND
4312 F04
Figure 4. Connection of the LTC4312 in a Level Shift Application. VCC Is Less Than or Equal to the Minimum
Bus Supply Voltages on the Output Side. VCC2 Is Grounded to Disable Output Rise Time Accelerators
Pull-Up Resistor Value Selection
Input to Output Offset Voltage and Propagation Delay
To guarantee that the rise time accelerators are activated
during a rising edge, the bus must rise on its own with
a positive slew rate of at least 0.4V/μs. To achieve this,
The LTC4312 introduces both an offset as well as a
propagation delay for falling edges between the input and
output. When a logic low voltage of ≥200mV is driven
on any of the LTC4312’s data or clock pins, the LTC4312
regulates the voltage on the opposite side to a slightly
higher value. When SCLIN or SDAIN is driven to a logic
low voltage, SCLOUT or SDAOUT is driven to a slightly
higher voltage as directed by equation 3 which uses SDA
as an example:
choose a maximum R
using equation 1:
BUS
V
− VRTA(TH)
(
)
DD,BUS(MIN)
RBUS(Ω)≤
V
µs
(1)
0.4 •CBUS
R
isthebuspull-upresistor,V
theminimum
DD,BUS(MIN)
BUS
V
(V)= V
+ 45mV
bus pull-up supply voltage, V
the voltage at which
SDAOUT
SDAIN
RTA(TH)
the rise time accelerator turns on, which is a function of
ACC,andC theequivalentbuscapacitance.R values
V
DD,BUS
(3)
+(10Ω +R
) •
MUX
BUS
BUS
R
BUS
on each output channel must also be chosen to ensure
thatwhenalltherequiredoutputchannelsareenabled, the
total bus current is ≤4mA. The bus current in each output
channel can be 4mA if only one output channel is enabled
V
is the output bus voltage, R
BUS
the output bus
DD,BUS
pull-upresistanceandR
istheresistanceofthechannel
MUX
transmission gate in the multiplexer shown in the block
diagram. TheoffsetisaffectedbytheV voltageandbus
at any given time. The R
value on the input side must
BUS
CC2
also be chosen to limit the bus current to be ≤4mA. The
bus current for a single bus is determined by equation 2:
current. A higher V
voltage (V if V
is grounded)
CC2
CC
CC2
reduces R
leading to a lower offset. See the Typical
MUX
PerformanceCharacteristicsplotsforthevariationofR
MUX
V
DD,BUS −0.4V
as a function of V
and temperature. When SDAOUT or
(2)
IBUS(A)=
CC2
RBUS
SCLOUT is driven to a logic low voltage ≥ 200mV, SCLIN
4312f
11
LTC4312
APPLICATIONS INFORMATION
or SDAIN is regulated to a logic low voltage as directed
by equation 4 which uses SDA as an example:
Cascading LTC4312 Devices and Other LTC Bus Buffers
Multiple LTC4312s can be cascaded or the LTC4312 may
be cascaded with other LTC bus buffers as required by the
application. This is shown for the data pathway in Figure 5
where an LTC4312 is cascaded with other LTC4312s and
some select LTC bus buffers. The clock path is identical.
When using such cascades, users should be aware of the
VDD,BUS
(4)
VSDAIN(V)= VSDAOUT +45mV+10Ω •
RBUS
The SCLOUT/SDAOUT to SCLIN/SDAIN offset is lower
than the reverse case as the multiplexer transmission gate
does not affect this offset. For driven logic low voltages
<200mV,theaboveequationsdonotapplyasthesaturation
voltage of the open collector output transistor results in a
higher offset. However, the offset is guaranteed to be less
than 400mV for a total bus pull-up current of 4mA under
allconditions.SeetheTypicalPerformanceCharacteristics
curves for the buffer offset voltage as a function of the
driven logic low voltage and bus pull-up current.
additive logic low offset voltages (V ) when determin-
OS
ing system noise margin. If the sum of the offsets (refer
to Equations 3 and 4 and to the data sheets of the cor-
responding bus buffers) plus the worst-case driven logic
low voltage across the cascade exceeds the buffer turn off
voltage,signalswillnotbepropagatedacrossthecascade.
Alsotheminimumrisetimeaccelerator(RTA)turn-onvolt-
age (wherever applicable) of each device in the cascade
should also be greater than the maximum buffer turn-off
voltage of all the devices in the cascade. This condition
is required to prevent contention between one device’s
buffer and another’s RTA. Based on this requirement,
The high-to-low propagation delay arises due to both the
finite response time of the buffers and their finite current
sinkcapability.SeetheTypicalPerformanceCharacteristics
curves for the propagation delay as a function of the bus
capacitance.
3.3V
5V
3.3V
C1
0.01μF
C4
0.01μF
C5
0.01μF
R1
10k
R2
10k
R3
10k
R4
10k
R5
10k
V
V
V
CC
V
CC2
R6
10k
CC
CC2
LTC4312
LTC4312
SDAIN
SDAOUT1
SDAOUT2
SDAIN
SDAOUT1
SDAOUT2
SDAOUT1
SDAOUT2
ACC
ACC
GND
GND
3.3V
3.3V
5V
V
R7
10k
CC
LTC4301
C2
0.01μF
C3
0.01μF
SDAIN
SDAIN
SDAIN
SDAOUT
SDAOUT
SDAOUT3
SDAOUT4
SDAOUT5
GND
V
V
CC
CC2
5V
LTC4312
SDAOUT1
SDAOUT2
SDAIN
V
R8
10k
CC
ACC
LTC4303
GND
GND
5V
V
R9
10k
CC
LTC4307
GND
SDAOUT
4312 F05
Figure 5. Cascading LTC4312s with Other LTC4312s and LTC Bus Buffers. Only the SDA Path Is Shown for Simplicity
4312f
12
LTC4312
APPLICATIONS INFORMATION
the LTC4312 can be cascaded with the LTC4303 and
LTC4307 if the LTC4312’s RTA turn-on voltage is set to be
0.8V (ACC low). The LTC4312 can be cascaded with the
LTC4301 and LTC4301L under all ACC settings as these
devices do not have RTAs. The LTC4312 can be cascaded
with the LTC4302, LTC4304, LTC4305 and LTC4306 if the
LTC4312’s RTAs are set to turn on at 0.8V (ACC low) or
under all ACC settings if the RTAs on the other bus buf-
fers are disabled. Finally, two LTC4312s can be cascaded
if their ACC pins are tied to the same state, HIGH, LOW
or open or if the ACC pin of one LTC4312 is tied high and
the other is left open.
Radial Telecommunications
Figure 6 shows the use of the LTC4312 in a radial telecom-
munications application. Two Shelf Managers are wired to
2
communicate with slave I C devices for redundancy. Each
Shelf Manager can have as many LTC4312s as required
depending on the number of boards in the system and
the desired radial/star configuration. The ENABLE pins of
the LTC4312s inside only one Shelf Manager are asserted
high at any time. For simplicity, in Figure 6 only the SDA
pathway is shown. The SCL pathway is identical.
BACKPLANE
FRU #1
SHMC #1
3.3V
3.3V
3.3V
R1
10k
V
V
CC2
CC
R2
10k
LTC4312 #1
IPMB-A
SDA1
SDAIN
μP
SDAOUT1
SDAOUT2
ENABLE1
ENABLE2
ENABLE1A
ENABLE2A
IPMB-B
SDA1
ACC
GND
3.3V
V
CC
V
CC2
LTC4312 #12
SDAIN
SDAOUT1
SDAOUT2
ENABLE1
ENABLE2
ENABLE23A
ENABLE24A
3.3V
R3
10k
IPMB-A
SDA24
SDA1
ACC
GND
IPMB-B (×24)
SDA24
FRU #24
SHMC #2
(IDENTICAL TO SHMC#1)
IPMB-A (×24)
IPMB-B (×24)
IPMB-B
SDA24
SDA1
SDA24
4312 F06
Figure 6. LTC4312s Configured for a Radially Connected Redundant Telecommunications Shelf Manager Application
in a 12 × 2 Arrangement. The ENABLE Pins on Only One of the Shelf Managers Are High at Any Time. Only the SDA
Path Is Shown for Simplicity
4312f
13
LTC4312
APPLICATIONS INFORMATION
Nested Addressing
and output, asserting FAULT low and generating up to
16 clock pulses at 5.5kHz on the SCLOUT node common
to the two channels. Should the stuck bus release high
during this period, clock pulsing is stopped, a stop bit is
generated and FAULT is cleared. In order for a connec-
tion to be established between the input and output, all
ENABLEs have to be taken low followed by an assertion
of the ENABLEs of the required channels.This process is
illustrated in Figure 8 for the case where only channel 1 is
active and SDAOUT1 starts out stuck low and then recov-
ers. If DISCEN is tied low and a stuck low event occurs,
the FAULT flag is driven low, but the connection between
the input and output is not broken and clock generation
is not done.
The LTC4312 can provide nested addressing when its
ENABLE pins are used as channel select bits. This is
shown in Figure 7 where the master communicates with
slave devices that have the same address by selectively
enabling only one output channel at a time. Since slaves
have the same address care must be taken that the master
never enables both channels at the same time.
Stop Bit Generation and FAULT Clocking
If the output bus sticks low (SCLOUT or SDAOUT stuck
low for at least 45ms) on one of the enabled channels
and DISCEN is high, the LTC4312 attempts to unstick the
bus by first breaking the connection between the input
3.3V
3.3V
C1
0.01μF
C2
0.01μF
R1
10k
R2
10k
R4
10k
R5
10k
V
V
CC2
CC
2
SCLIN
I C
DEVICE
SDAIN
2
ENABLE1
ENABLE2
ENABLE1
ENABLE2
SCLOUT1
SDAOUT1
I C
DEVICE
ADDRESS = 1001 000
5V
LTC4312
3.3V
R6
10k
R7
10k
R3
10k
ACC
SCLOUT2
SDAOUT2
2
I C
DEVICE
DISCEN
FAULT
FAULT
ADDRESS = 1001 000
GND
4312 F07
Figure 7. Nested Addressing
ENABLE1
5V/DIV
DISCONNECT
AT TIMEOUT
CONNECT AT RISING EDGE OF ENABLE1
RECOVERS DRIVEN LOW
SDAIN
5V/DIV
STUCK LOW>45ms
SDAOUT1
5V/DIV
AUTOMATIC CLOCKING
SCLOUT1
5V/DIV
4312 F08
1ms/DIV
Figure 8.Bus Waveforms During a SDAOUT Stuck Low and Recovery Event
4312f
14
LTC4312
APPLICATIONS INFORMATION
Demultiplexer Function
failure. In Figure 9, if the 5V bus supply on channel 1 falls
below 1.4V, channel 1 gets disabled as ENABLE1 is driven
Due to its bi-directional nature, the LTC4312 can be used
as a demultiplexer. This is shown in Figure 9 where two
2
below its digital threshold. Simultaneously, the V of the
channels are used to drive I C data from the master side
BE
NPN pull-down device on ENABLE2 falls below 0.7V and
it turns off. This causes ENABLE2 to be pulled up by R7
which in turn enables channel 2, causing control to be
with redundancy to the slave side. In this application the
SDAOUT/SCLOUT channels serve as the inputs while the
SDAIN/SCLIN channel is the output. Redundancy on the
master side provides protection against power supply
2
transferred to the backup I C master device.
5V
3.3V
R1
10k
R2
10k
C1
0.01μF
R8
10k
R9
10k
R10
10k
V
V
CC
CC2
LTC4312
PRIMARY
SDAOUT1
SCLOUT1
ENABLE1
2
I C
MASTER
SDAIN
SCLIN
SDA
SCL
3.3V
CONTROLLER
CARD
ACC
DISCEN
R3
R4
R5
10k 10k 100k
R7
20k
FAULT
FAULT
BACKUP
SDAOUT2
SCLOUT2
ENABLE2
2
I C
MASTER
GND
CONTROLLER
CARD
4312 F09
BF840
R6
50k
Figure 9. The LTC4312 Configured as a 2:1 Demultiplexer in a System with Redundancy
4312f
15
LTC4312
APPLICATIONS INFORMATION
Hot-Swapping
Figure 10 shows the LTC4312 in a typical hot-swapping
application where the LTC4312 is on the backplane and I/O
cardsplugintothedownstreamchannels.Theoutputsmust
idle high and the corresponding output channel must be
disabled before an I/0 card can be plugged or unplugged
from an output channel. Figure 10 also shows the use of
2
a non-compliant I C device with the LTC4312. The high
noise margin of the LTC4312 supports logic low levels up
to 0.3• V , allowing devices to drive greater than 0.4V
CC
logic low levels on the clock and data lines.
3.3V
3.3V
C1
0.01μF
C2
0.01μF
R1
10k
R2
10k
R4
10k
R5
10k
V
CC
V
CC2
SCLIN
2
I C
DEVICE
= 0.6V
SDAIN
2
V
I C
OL
ENABLE1
ENABLE2
SCLOUT1
SDAOUT1
ENABLE1
ENABLE2
DEVICE
IO CARD
5V
CONNECTOR
LTC4312
3.3V
R6
10k
R7
10k
R3
10k
ACC
2
I C
SCLOUT2
SDAOUT2
DEVICE
DISCEN
IO CARD
FAULT
FAULT
GND
CONNECTOR
4312 F10
Figure 10. SDA, SCL Hot Swap™ and Operation with a Non-Compliant I2C Device
4312f
16
LTC4312
APPLICATIONS INFORMATION
Level Translating to Bus Voltages < 2.25V
in order to meet the V = 0.7•V
requirement and
IH
DD,BUS
not impact the high side noise margin. Users willing to live
with a lower logic high noise margin can level translate
down to 1.5V. An example of voltage level translation from
3.3V to 1.8V is illustrated in Figure 11, where a 3.3V input
voltage level is translated to a 1.8V output voltage level on
The LTC4312 can be used for level translation to bus volt-
ages below 2.25V if certain conditions are met. In order
to perform this level translation, RTAs on the low voltage
side need to be disabled in order to prevent an over drive
of the low voltage bus. If one of the output channels is
pulled up to the low voltage bus supply, the other output
channel needs to be disabled when this channel is active,
in order to prevent cross conduction between the output
channels. Since the buffer turn-on and turn-off voltages
channel 1. Tying V to 3.3V satisfies equation 5. Ground-
CC
ing V
MIN
disables the RTA on the low voltage channel.
CC2
V
defaults to V under these conditions, making the
CC
buffer turn off voltage 0.99V. Channel 2 must be disabled
when channel 1 is enabled. A similar voltage translation
can also be performed going from a 3.3V bus supply on
the output side to a 1.8V bus supply on the input side if
are 0.3•V , the minimum bus supply voltage is deter-
MIN
mined by equation 5:
0.3• VMIN
ACC is tied high to disable the input RTA and if V and
CC
VDD,BUS(MIN)
≥
(5)
V
CC2
are tied to the output side bus supply.
0.7
3.3V
1.8V
C1
0.01μF
C2
0.01μF
R1
10k
R2
10k
R4
10k
R5
10k
V
V
CC2
CC
SCLIN
SDAIN
SCLIN
SDAIN
ENABLE1
ENABLE2
SCLOUT1
SDAOUT1
ENABLE1
ENABLE2
SCLOUT1
SDAOUT1
3.3V
5V
LTC4312
C3
0.01μF
R6
10k
R7
10k
R3
10k
ACC
SCLOUT2
SDAOUT2
DISCEN
FAULT
SCLOUT2
SDAOUT2
GND
4312 F11
Figure 11. Level Shifting Down to 1.8V Using the LTC4312, VCC2 Is Grounded to Disable the Rise Time Accelerator
on the Low Voltage Bus. ENABLE2 Must Be Low Whenever ENABLE1 Is High
4312f
17
LTC4312
PACKAGE DESCRIPTION
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev B)
0.70 ±0.05
3.30 ±0.05
1.70 ± 0.05
3.60 ±0.05
2.20 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
3.00 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
0.40 ± 0.10
4.00 ±0.10
(2 SIDES)
8
14
R = 0.05
TYP
3.30 ±0.10
3.00 ±0.10
(2 SIDES)
1.70 ± 0.10
PIN 1 NOTCH
R = 0.20 OR
PIN 1
TOP MARK
(SEE NOTE 6)
0.35 × 45°
CHAMFER
(DE14) DFN 0806 REV B
7
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.50 BSC
3.00 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
4312f
18
LTC4312
PACKAGE DESCRIPTION
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev Ø)
0.889 p 0.127
(.035 p .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
4.039 p 0.102
(.159 p .004)
(NOTE 3)
0.50
(.0197)
BSC
0.305 p 0.038
(.0120 p .0015)
TYP
0.280 p 0.076
(.011 p .003)
REF
16151413121110
9
RECOMMENDED SOLDER PAD LAYOUT
3.00 p 0.102
(.118 p .004)
(NOTE 4)
DETAIL “A”
0.254
4.90 p 0.152
(.193 p .006)
(.010)
0o – 6o TYP
GAUGE PLANE
0.53 p 0.152
(.021 p .006)
1 2 3 4 5 6 7 8
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 p 0.0508
(.004 p .002)
MSOP (MS16) 1107 REV Ø
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
4312f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC4312
TYPICAL APPLICATION
Level Translating 2.5V, 3.3V and 5V Busses and Operation with a Non-Compliant I2C Device
3.3V
5V
C1
0.01μF
C2
0.01μF
R1
10k
R2
10k
R3
10k
R4
10k
V
V
CC2
CC
SCLIN
SDAIN
SCLOUT1
SDAOUT1
ENABLE1
ENABLE2
SCLOUT1
SDAOUT1
LTC4312
NON-COMPLIANT
2.5V
2
I C DEVICE
V
OL
= 0.6V
3.3V
R5
10k
R6
10k
ACC
SCLOUT2
SDAOUT2
DISCEN
SCLOUT2
SDAOUT2
GND
4312 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC4300A-1/
LTC4300A-2/
LTC4300A-3
Hot-Swappable 2-Wire Bus Buffers
-1: Bus Buffer with READY and ENABLE
-2: Dual Supply Buffer with ACC
-3: Dual Supply Buffer with ENABLE
LTC4302-1/
LTC4302-2
Addressable 2-Wire Bus Buffer
Address Expansion, GPIO, Software Controlled
2
LTC4303
LTC4304
Hot-Swappable 2-Wire Bus Buffer with Stuck Bus
Recovery
Provides Automatic Clocking to Free Stuck I C Busses
LTC4305
LTC4306
2- or 4-Channel, 2-Wire Bus Multiplexers with
Capacitance Buffering
2 or 4 Software Selectable Downstream Busses, Stuck Bus Disconnect, Rise
Time Accelerators, Fault Reporting, 10kV HBM ESD Tolerance
LTC4307
LTC4307-1
LTC4308
LTC4309
Low Offset Hot-Swappable 2-Wire Bus Buffer with
Stuck Bus Recovery
60mV Bus Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time
Accelerators, 5kV HBM ESD Tolerance
High Definition Multimedia Interface (HDMI) Level
Shifting 2-Wire Bus Buffer
60mV Buffer Offset, 3.3V to 5V Level Shifting, 5kV HBM ESD Tolerance
Low Voltage, Level Shifting Hot-Swappable 2-Wire
Bus Buffer with Stuck Bus Recovery
Bus Buffer with ENABLE and READY, Level Translation to 1V Busses,
Output Side Rise Time Accelerators
Low Offset Hot-Swappable 2-Wire Bus Buffer with
Stuck Bus Recovery
60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time
Accelerators, 5kV HBM ESD Tolerance
2
LTC4310-1/
LTC4310-2
Hot-Swappable I C Isolators
-1: 100kHz Bus
-2: 400kHz Bus
2
LTC4311
LTC4314
Low Voltage I C/SMBus Accelerator
Rise Time Acceleration with ENABLE and 8kV HBM ESD Tolerance
Pin-Selectable, 4-Channel, 2-Wire Multiplexer with
Bus Buffer
4 Pin-Selectable Downstream Busses, Stuck Bus Disconnect and Recovery,
Selectable Rise Time Accelerator Current and Activation Voltage, 4kV HBM
ESD Tolerance
LTC4301
Supply Independent Hot Swappable 2-Wire Bus Buffer Bus Buffer with 1V Pre-Charge, CS and READY
LTC4301L
Hot-Swappable 2-Wire Bus Buffer with Low Voltage
Level Translation
Bus Buffer with CS and READY Allowing for Input Bus Voltages of Up to 1V
2
LTC1694-1
SMBus/I C Accelerator
Rise Time Accelerator
4312f
LT 1210 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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