LTC4440ES6#TRMPBF [Linear]
暂无描述;型号: | LTC4440ES6#TRMPBF |
厂家: | Linear |
描述: | 暂无描述 驱动器 栅极 接口集成电路 光电二极管 栅极驱动 |
文件: | 总12页 (文件大小:230K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Final Electrical Specifications
LTC4440
High Speed, High Voltage
High Side Gate Driver
October 2003
U
FEATURES
DESCRIPTION
The LTC®4440 is a high frequency high side N-channel
MOSFET gate driver that is designed to operate in applica-
tions with VIN voltages up to 80V. The LTC4440 can also
withstand and continue to function during 100V VIN tran-
sients. The powerful driver capability reduces switching
losses in MOSFETs with high gate capacitances. The
LTC4440’s pull-up has a peak output current of 2.4A and
its pull-down has an output impedance of 1.5Ω.
■
Wide Operating VIN Range: Up to 80V
■
Rugged Architecture Tolerant of 100V VIN
Transients
Powerful 1.5Ω Driver Pull-Down
■
■
Powerful 2.4A Peak Current Driver Pull-Up
■
7ns Fall Time Driving 1000pF Load
■
10ns Rise Time Driving 1000pF Load
■
Drives Standard Threshold MOSFETs
■
TTL/CMOS Compatible Inputs with Hysteresis
The LTC4440 features supply independent TTL/CMOS
compatible input thresholds with 350mV of hysteresis.
The input logic signal is internally level-shifted to the
bootstrapped supply, which may function at up to 115V
above ground.
■
Input Thresholds are Independent of Supply
■
Undervoltage Lockout
Low Profile (1mm) SOT-23 (ThinSOT)TM or Thermally
■
Enhanced 8-Pin MSOP Packages
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The LTC4440 contains both high side and low side under-
voltage lockout circuits that disable the external MOSFET
when activated.
APPLICATIO S
■
Telecommunications Power Systems
■
Distributed Power Architectures
The LTC4440 is available in the low profile (1mm) SOT-23
or a thermally enhanced 8-lead MSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation.
■
Server Power Supplies
High Density Power Modules
■
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TYPICAL APPLICATIO
Synchronous Phase-Modulated Full-Bridge Converter
V
IN
36V TO 72V
100V PEAK TRANSIENT
(ABS MAX)
LTC4440 Driving a 1000pF
Capacitive Load
V
CC
8V TO 15V
LTC4440
BOOST
INPUT
(INP)
2V/DIV
V
CC
INP
TG
TS
GND
OUTPUT
(TG – TS)
5V/DIV
LTC4440
V
BOOST
TG
V
CC
CC
•
•
LTC3722-1
INP
GND
TS
10ns/DIV
4440 F02
4440 TA01
4440i
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will notinfringe onexisting patent rights.
1
LTC4440
W W U W
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Peak Output Current < 1µs (TG) ............................... 4A
Driver Output TG (with Respect to TS) ..... –0.3V to 15V
Operating Ambient Temperature Range
(Note 2) .............................................. –40°C to 85°C
Junction Temperature (Note 3)............................ 150°C
Storage Ambient Temperature Range ... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Supply Voltage
VCC ....................................................... –0.3V to 15V
BOOST – TS ......................................... –0.3V to 15V
INP Voltage............................................... –0.3V to 15V
BOOST Voltage (Continuous) ................... –0.3V to 95V
BOOST Voltage (100ms) ........................ –0.3V to 115V
TS Voltage (Continuous) ............................. –5V to 80V
TS Voltage (100ms)................................... –5V to 100V
U
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PACKAGE/ORDER INFORMATION
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
INP
GND
1
2
3
4
8 TS
7 TG
6 BOOST
5 NC
9
V
1
6 BOOST
5 TG
CC
LTC4440EMS8E
LTC4440ES6
V
CC
GND 2
INP 3
GND
4 TS
MS8E PACKAGE
MS8E
S6
8-LEAD PLASTIC MSOP
S6 PACKAGE
TJMAX = 150°C, θJA = 40°C/W (NOTE 4)
PART MARKING
PART MARKING
6-LEAD PLASTIC SOT-23
EXPOSED PAD IS GND (PIN 9)
MUST BE SOLDERED TO PCB
TJMAX = 150°C, θJA = 230°C/W
LTF9
LTZY
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = VBOOST = 12V, VTS = GND = 0V, unless otherwise noted.
SYMBOL PARAMETER
Main Supply (V
CONDITIONS
MIN
TYP
MAX
UNITS
)
CC
I
DC Supply Current
Normal Operation
UVLO
VCC
INP = 0V
250
25
400
80
µA
µA
V
IN
< UVLO Threshold – 0.1V
UVLO
Undervoltage Lockout Threshold
V
V
Rising
Falling
●
●
5.7
5.4
6.5
6.2
7.3
7.0
V
V
CC
CC
Hysteresis
300
mV
Bootstrapped Supply (BOOST – TS)
I
DC Supply Current
Normal Operation
UVLO
BOOST
INP = 0V
110
86
180
170
µA
µA
V
– V < UVLO – 0.1V, INP = 0V
TS HS
BOOST
UVLO
Undervoltage Lockout Threshold
V
V
– V Rising
●
●
6.75
6.25
7.4
6.9
7.95
7.60
V
V
HS
BOOST
TS
– V Falling
BOOST
TS
Hysteresis
500
mV
Input Signal (INP)
V
V
V
High Input Threshold
Low Input Threshold
Input Voltage Hysteresis
Input Pin Bias Current
INP Ramping High
INP Ramping Low
●
●
1.3
1.6
2
V
V
V
IH
IL
0.85
1.25
1.6
– V
0.350
±0.01
IH
IL
I
±2
µA
INP
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LTC4440
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = VBOOST = 12V, VTS = GND = 0V, unless otherwise noted.
SYMBOL PARAMETER
Output Gate Driver (TG)
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
High Output Voltage
I
I
= –10mA, V = V
– V
TG
0.7
150
2.4
1.5
V
mV
A
OH
OL
TG
TG
OH
BOOST
Low Output Voltage
= 100mA
●
●
●
220
2.2
I
Peak Pull-Up Current
Output Pull-Down Resistance
1.7
PU
R
Ω
DS
Switching Timing
t
Output Rise Time
10% – 90%, C = 1nF
10
100
ns
ns
r
L
10% – 90%, C = 10nF
L
t
Output Fall Time
10% – 90%, C = 1nF
7
70
ns
ns
f
L
10% – 90%, C = 10nF
L
t
t
Output Low-High Propagation Delay
Output High-Low Propagation Delay
●
●
30
28
65
65
ns
ns
PLH
PHL
Note 3: T is calculated from the ambient temperature T and power
dissipation PD according to the following formula:
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
J
A
T = T + (PD • θ °C/W)
Note 4: Failure to solder the exposed back side of the MS8E package to
the PC board will result in a thermal resistance much higher than 40°C/W.
Note 2: The LTC4440 is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
J
A
JA
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TYPICAL PERFOR A CE CHARACTERISTICS
VCC Supply Quiescent Current
vs Voltage
BOOST – TS Supply Quiescent
Current vs Voltage
Output Low Voltage (VOL
)
vs Supply Voltage
300
250
200
150
100
50
160
155
150
145
500
450
T
= 25°C
T = 25°C
A
I
= 100mA
A
TG
A
INP = 0V
T
= 25°C
400
350
300
INP = V
CC
INP = V
CC
250
200
140
135
130
150
100
50
INP = 0V
0
0
0
5
10
15
0
10
BOOST – TS SUPPLY VOLTAGE (V)
15
8
9
10
11
12
13
14
15
5
V
SUPPLY VOLTAGE (V)
BOOST – TS SUPPLY VOLTAGE (V)
CC
4440 G01
4440 G02
4440 G03
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LTC4440
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TYPICAL PERFOR A CE CHARACTERISTICS
Output High Voltage (VOH
)
Input Thresholds (INP)
vs Supply Voltage
VCC Supply Current
at TTL Input Levels
vs Supply Voltage
2.0
1.8
15
380
360
340
320
300
280
260
240
220
200
T
= 25°C
A
T = 25°C
A
T
A
= 25°C
14
13
V
IH
(INPUT HIGH THRESHOLD)
INP = 2V
I
TG
= –1mA
1.6
1.4
12
11
10
9
I
TG
= –10mA
V
IL
(INPUT LOW THRESHOLD)
I
TG
= –100mA
INP = 0.8V
1.2
1.0
0.8
8
7
7
9
11
13
15
9
10
12
13
14
15
12
SUPPLY VOLTAGE (V)
8
11
8
10
V
CC
14
V
CC
SUPPLY VOLTAGE (V)
BOOST – TS SUPPLY VOLTAGE (V)
4440 G05
4440 G04
4440 G06
VCC Supply Current (VCC = 12V)
vs Temperature
VCC Undervoltage Lockout
Thresholds vs Temperature
2MHz Operation
300
250
6.45
6.40
6.35
6.30
6.25
6.20
6.15
6.10
6.05
INPUT
(INP)
INP = 0V
RISING THRESHOLD
5V/DIV
INP = 12V
200
150
100
50
OUTPUT
(TG)
5V/DIV
FALLING THRESHOLD
V
CC = 12V
250ns/DIV
4440 G07
0
0
30
60
90
120
0
30
60
90
120
–60 –30
–60 –30
TEMPERATURE (°C)
TEMPERATURE (°C)
4440 G08
4440 G09
Boost Supply (BOOST – TS)
Undervoltage Lockout Thresholds
vs Temperature
Boost Supply Current
vs Temperature
Input Threshold vs Temperature
7.6
7.5
7.4
7.3
7.2
7.1
7.0
6.9
6.8
6.7
500
450
400
350
300
250
200
150
100
50
2.0
1.8
INP = 12V
RISING THRESHOLD
V
(V = 12V)
IH CC
V
(V = 15V)
IH CC
V
(V = 8V)
IH CC
1.6
1.4
1.2
1.0
0.8
V
(V = 12V)
IL CC
V (V = 15V)
IL CC
FALLING THRESHOLD
V
(V = 8V)
IL CC
INP = 0V
0
0
30
60
90
120
0
30
60
90
120
–60 –30
–60 –30
0
30
60
90
120
–60 –30
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4440 G10
4440 G12
4440 G11
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LTC4440
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TYPICAL PERFOR A CE CHARACTERISTICS
Input Threshold Hysteresis
vs Temperature
Peak Driver (TG) Pull-Up Current
vs Temperature
500
480
460
440
420
400
380
360
340
320
300
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
BOOST – TS = 15V
V
-V (V = 12V)
IH IL CC
V -V (V = 15V)
IH IL CC
V
-V (V = 8V)
IH IL CC
BOOST – TS = 12V
0
30
60
90
120
0
30
60
90
120
–60 –30
–60 –30
TEMPERATURE (°C)
TEMPERATURE (°C)
4440 G13
4440 G14
Output Driver Pull-Down
Resistance vs Temperature
Propagation Delay vs Temperature
(VCC = BOOST = 12V)
45
40
35
30
25
20
15
10
5
3.0
2.5
t
BOOST – TS = 12V
BOOST – TS = 8V
PLH
2.0
1.5
1.0
0.5
0
t
PHL
BOOST – TS = 15V
0
0
30
60
90
120
–60 –30
0
30
60
90
120
–60 –30
TEMPERATURE (°C)
TEMPERATURE (°C)
4440 G16
4440 G15
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PI FU CTIO S
SOT-23 Package
VCC (Pin 1): Chip Supply. This pin powers the internal low
side circuitry. A low ESR ceramic bypass capacitor should
be tied between this pin and the GND pin (Pin 2).
TG (Pin 5): High Current Gate Driver Output (Top Gate).
This pin swings between TS and BOOST – 0.7V.
BOOST (Pin 6): High Side Bootstrapped Supply. An exter-
nal capacitor should be tied between this pin and TS
(Pin 4). Normally, abootstrapdiodeisconnectedbetween
VCC (Pin 1) and this pin. Voltage swing at this pin is from
VCC – VD to VIN + VCC – VD, where VD is the forward voltage
drop of the bootstrap diode.
GND (Pin 2): Chip Ground.
INP (Pin 3): Input Signal. TTL/CMOS compatible input
referenced to GND (Pin 2).
TS (Pin 4): Top (High Side) Source Connection.
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LTC4440
U
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PI FU CTIO S
Exposed Pad MS8E Package
INP (Pin 1): Input Signal. TTL/CMOS compatible input
BOOST (Pin 6): High Side Bootstrapped Supply. An exter-
nal capacitor should be tied between this pin and TS
(Pin 8). Normally, abootstrapdiodeisconnectedbetween
VCC (Pin 3) and this pin. Voltage swing at this pin is from
referenced to GND (Pin 2).
GND (Pins 2, 4): Chip Ground.
V
CC (Pin 3): Chip Supply. This pin powers the internal low
V
CC – VD to VIN + VCC – VD, where VD is the forward voltage
side circuitry. A low ESR ceramic bypass capacitor should
be tied between this pin and the GND pin (Pin 2).
drop of the bootstrap diode.
TG (Pin 7): High Current Gate Driver Output (Top Gate).
This pin swings between TS and BOOST.
NC (Pin 5): No Connect. No connection required. For
convenience, this pin may be tied to Pin 6 (BOOST) on the
application board.
TS (Pin 8): Top (High Side) Source Connection.
Exposed Pad (Pin 9): Ground. Must be electrically con-
nected to Pins 2, 4.
W
BLOCK DIAGRA
V
IN
UP TO 80V,
TRANSIENT
UP TO 100V
BOOST
HIGH SIDE
UNDERVOLTAGE
LOCKOUT
V
CC
UNDERVOLTAGE
LOCKOUT
TG
TS
8V TO 15V
GND
BOOST
INP
LEVEL SHIFTER
4440 BD
GND
TS
W U
W
TI I G DIAGRA
INPUT RISE/FALL TIME <10ns
V
IH
INPUT (INP)
V
IL
90%
10%
OUTPUT (TG)
t
t
f
r
t
t
PHL
PLH
4440 TD
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LTC4440
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APPLICATIO S I FOR ATIO
V
BOOST
IN
Overview
UP TO 100V
The LTC4440 receives a ground-referenced, low voltage
digital input signal to drive a high side N-channel power
MOSFET whose drain can float up to 100V above ground,
eliminating the need for a transformer between the low
voltage control signal and the high side gate driver. The
LTC4440 normally operates in applications with input
supply voltages (VIN) up to 80V, but is able to withstand
and continue to function during 100V, 100ms transients
on the input supply.
LTC4440
C
Q1
N1
GD
TG
POWER
MOSFET
C
GS
TS
LOAD
INDUCTOR
4440 F03
–
The powerful output driver of the LTC4440 reduces the
switching losses of the power MOSFET, which increase
with transition time. The LTC4440 is capable of driving a
1nF load with 10ns rise and 7ns fall times using a
bootstrapped supply voltage VBOOST–TS of 12V.
V
Figure 3. Capacitance Seen by TG During Switching
The LTC4440’s peak pull-up (Q1) current is 2.4A while the
pull-down (N1) resistance is 1.6Ω. The low impedance of
N1 is required to discharge the power MOSFET’s gate
capacitance during high-to-low signal transitions. When
the power MOSFET’s gate is pulled low (gate shorted to
source through N1) by the LTC4440, its source (TS) is
pulled low by its load (e.g., an inductor or resistor). The
slew rate of the source/gate voltage causes current to flow
back to the MOSFET’s gate through the gate-to-drain
capacitance (CGD). If the MOSFET driver does not have
sufficient sink current capability (low output impedance),
the current through the power MOSFET’s CGD can mo-
mentarily pull the gate high, turning the MOSFET back on.
Input Stage
TheLTC4440employsTTL/CMOScompatibleinputthresh-
oldsthatallowalowvoltagedigitalsignaltodrivestandard
power MOSFETs. The LTC4440 contains an internal volt-
age regulator that biases the input buffer, allowing the
input thresholds (VIH = 1.6V, VIL = 1.25V) to be indepen-
dent of variations in VCC. The 350mV hysteresis between
VIH and VIL eliminates false triggering due to noise during
switching transitions. However, care should be taken to
keep this pin from any noise pickup, especially in high
frequency, high voltage applications. The LTC4440 input
buffer has a high input impedance and draws negligible A similar scenario exists when the LTC4440 is used to
input current, simplifying the drive circuitry required for drive a low side MOSFET. When the low side power
the input.
MOSFET’s gate is pulled low by the LTC4440, its drain
voltage is pulled high by its load (e.g., inductor or resis-
tor). The slew rate of the drain voltage causes current to
flow back to the MOSFET’s gate through its gate-to-drain
capacitance. If the MOSFET driver does not have sufficient
sink current capability (low output impedance), the cur-
rent through the power MOSFET’s CGD can momentarily
pull the gate high, turning the MOSFET back on.
Output Stage
A simplified version of the LTC4440’s output stage is
shown in Figure 3 . The pull-down device is an N-channel
MOSFET (N1) and the pull-up device is an NPN bipolar
junctiontransistor(Q1).Theoutputswingsfromthelower
rail (TS) to within an NPN VBE (~0.7V) of the positive rail
(BOOST). This large voltage swing is important in driving
external power MOSFETs, whose RDS(ON) is inversely
proportional to its gate overdrive voltage (VGS – VTH).
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LTC4440
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APPLICATIO S I FOR ATIO
Rise/Fall Time
TheLTC4440consumesverylittlecurrentduringstandby.
The DC power loss at VCC = 12V and VBOOST–TS = 12V is
only (250µA + 110µA)(12V) = 4.32mW.
Since the power MOSFET generally accounts for the
majority of the power loss in a converter, it is important to
quickly turn it on or off, thereby minimizing the transition
time in its linear region. The LTC4440 can drive a 1nF load
with a 10ns rise time and 7ns fall time.
AC switching losses are made up of the output capacitive
load losses and the transition state losses. The capacitive
load losses are primarily due to the large AC currents
needed to charge and discharge the load capacitance
during switching. Loadlosses fortheoutputdriver driving
a pure capacitive load COUT would be:
The LTC4440’s rise and fall times are determined by the
peak current capabilities of Q1 and N1. The predriver that
drivesQ1andN1usesanonoverlappingtransitionscheme
to minimize cross-conduction currents. N1 is fully turned
off before Q1 is turned on and vice versa.
2
Load Capacitive Power = (COUT)(f)(VBOOST–TS
)
The power MOSFET’s gate capacitance seen by the driver
output varies with its VGS voltage level during switching.
A power MOSFET’s capacitive load power dissipation can
be calculated using its gate charge, QG. The QG value
corresponding to the MOSFET’s VGS value (VCC in this
case) can be readily obtained from the manufacturer’s QG
vs VGS curves:
Power Dissipation
To ensure proper operation and long-term reliability, the
LTC4440mustnotoperatebeyonditsmaximumtempera-
ture rating. Package junction temperature can be calcu-
lated by:
TJ = TA + PD (θJA)
Load Capacitive Power (MOS) = (VBOOST–TS)(QG)(f)
where:
Transition state power losses are due to both AC currents
required to charge and discharge the driver’s internal
nodal capacitances and cross-conduction currents in the
internal gates.
TJ = Junction Temperature
TA = Ambient Temperature
PD = Power Dissipation
Undervoltage Lockout (UVLO)
θJA = Junction-to-Ambient Thermal Resistance
The LTC4440 contains both low side and high side under-
voltage lockout detectors that monitor VCC and the
bootstrapped supply VBOOST–TS. When VCC falls below
6.2V, theinternalbufferisdisabledandtheoutputpinOUT
is pulled down to TS. When VBOOST – TS falls below 6.9V,
OUT is pulled down to TS. When both supplies are under-
voltage, OUT is pulled low to TS and the chip enters a low
current mode, drawing approximately 25µA from VCC and
86µA from BOOST.
Power dissipation consists of standby and switching
power losses:
PD = PSTDBY + PAC
where:
PSTDBY = Standby Power Losses
PAC = AC Switching Losses
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LTC4440
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APPLICATIO S I FOR ATIO
Bypassing and Grounding
C. Plan the power/ground routing carefully. Know where
the large load switching current is coming from and
going to. Maintain separate ground return paths for the
input pin and the output power stage.
The LTC4440 requires proper bypassing on the VCC and
VBOOST–TS suppliesduetoitshighspeedswitching(nano-
seconds) and large AC currents (Amperes). Careless
component placement and PCB trace routing may cause
excessive ringing and under/overshoot.
D. Keepthecoppertracebetweenthedriveroutputpinand
the load short and wide.
To obtain the optimum performance from the LTC4440:
E. When using the MS8E package, be sure to solder the
exposed pad on the back side of the LTC4440 package
to the board. Correctly soldered to a 2500mm2 double-
sided 1oz copper board, the LTC4440 has a thermal
resistance of approximately 40°C/W. Failure to make
good thermal contact between the exposed back side
and the copper board will result in thermal resistances
far greater than 40°C/W.
A. Mount the bypass capacitors as close as possible
between the VCC and GND pins and the BOOST and TS
pins. The leads should be shortened as much as pos-
sible to reduce lead inductance.
B. Use a low inductance, low impedance ground plane to
reduce any ground drop and stray capacitance. Re-
member that the LTC4440 switches >2A peak currents
and any significant ground drop will degrade signal
integrity.
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LTC4440
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TYPICAL APPLICATIO
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LTC4440
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PACKAGE DESCRIPTION
MS8E Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1662)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
2.794 ± 0.102
(.110 ± .004)
0.52
(.0205)
REF
2.06 ± 0.102
(.081 ± .004)
1
8
7 6
5
1.83 ± 0.102
(.072 ± .004)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
2.083 ± 0.102
(.082 ± .004)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
0.65
(.0256)
BSC
0.42 ± 0.038
(.0165 ± .0015)
TYP
GAUGE
PLANE
1
2
3
4
8
0.53 ± 0.152
(.021 ± .006)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.10
(.043)
MAX
0.86
(.034)
REF
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.18
(.007)
SEATING
PLANE
NOTE:
0.22 – 0.38
(.009 – .015)
TYP
0.127 ± 0.076
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
(.005 ± .003)
0.65
(.0256)
BSC
MSOP (MS8E) 0603
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
S6 Package
6-Lead Plastic SOT-23
(Reference LTC DWG # 05-08-1636)
2.90 BSC
(NOTE 4)
0.62
MAX
0.95
REF
1.22 REF
1.50 – 1.75
(NOTE 4)
2.80 BSC
1.4 MIN
3.85 MAX 2.62 REF
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4440i
11
LTC4440
U
TYPICAL APPLICATIO
LTC3723-2/LTC4440 240W 42V-56V Input 94.5% Efficient Unregulated 12V Half-Bridge Converter
L5
0.56µH
V
IN
2
7
9
+V
IN
•
•
•
L6 0.22µH
1µF
100V
1µF
100V
48V
–V
+V
OUT
11V
1µF
1µF
D23
IN
100V
100V
11
4
3
T2
1
10Ω
1W
+
C32
180µF
16V
500pF
100V
70(980µH):1
•
V
CC
LTC4440ES6
BOOST
1
8
+
CS
•
•
6
1µF
100V
1µF
100V
Si7370DP
×2
Si7370DP
×2
3
5
Si7852DP
C30
2.2nF
250V
7
A
IN
TG
TS
3
5
×2
1µF
GND
2
0.22µF
4
–V
OUT
1
D8
D9
12V
L4
1mH
C14
B
•
D12
T1
Si7852DP
×2
+
D14
5T:4T(75µH):
Q17
OUT
Q18
4T:2T:2T
68µF
6
–V
T3
1.5mH 1:0.5:0.5
5
7
•
3
OUT1
LTC1693-1
OUT2
BAT54
BAT54
1
•
4.7k
100Ω
1/4W
MMBT3904
1k
6
3
1
4
6
8
2
+V
IN2
IN1
V
OUT
CC2
0.1µF
V
V
IN
22Ω
220pF
CC1
12V
15k
11V
•
4
5
GND2
GND1
MMBT3904
330pF
8
MMBZ5240B
10V
A
1µF
120Ω
1µF
6
4
2
3
–V
OUT
1/4W
5
DRVA DRVB
SDRB
SDRA
V
CC
11
1µF, 100V: TDK C4532X7R2A105M
C14: AVX TPSE686M020R0150
C30: MuRata DE2E3KH222MB3B
C32: SANYO 16SP180M
D8, D9, D26, D27: MMBD914
D12, D14, D23: BAS21
L4: COILCRAFT DO1608C-105
L5: COILCRAFT DO1813P-561HC
L6: SUMIDA CDEP105-0R2NC-50
Q17, Q18: ZETEX FMMT718
T1: PULSE PA0901-005
215k
COMP
LTC3723-2
+
CS
15
UVLO
B
DPRG
12
V
RAMP CT SPRG GND CS
SS FB
14 13
REF
1
0.22µF
1k
9
8
16
7
10
1µF
D26
D27
1nF
62k
12V
MMBZ5242B
150pF
30.1k
2N7002
10k
4.7k
7.5Ω
7.5Ω
4440 TA04
0.47µF
470pF
0.47µF
330pF
T2: PULSE P8207
T3: PULSE PA0297
RELATED PARTS
PART NUMBER
LTC1154
DESCRIPTION
High Side Micropower MOSFET Drivers
COMMENTS
Internal Charge Pump, 4.5V to 48V Supply Range, t = 80µs, t = 28µs
ON
OFF
LTC1155
Dual Micropower High/Low Side Drivers with
Internal Charge Pump
4.5V to 18V Supply Range
LT®1161
LTC1163
LT1339
Quad Protected High Side MOSFET Driver
Triple 1.8V to 6V High Side MOSFET Driver
High Power Synchronous DC/DC Controller
Isolated RS485 Transceiver
8V to 48V Supply Range, t = 200µs, t = 28µs
ON
OFF
1.8V to 6V Supply Range, t = 95µs, t = 45µs
ON
OFF
Current Mode Operation Up to 60V, Dual N-Channel Synchronous Drive
2500V of Isolation Between Line Transceiver and Logic Level Interface
LTC1535
RMS
LTC1693 Family High Speed Dual MOSFET Drivers
LT3010/LT3010-5 50mA, 3V to 80V Low Dropout Micropower Regulators
1.5A Peak Output Current, 4.5V ≤ V ≤ 13.2V
IN
Low Quiescent Current (30µA), Stable with Small (1µF) Ceramic Capacitor
LT3430
High Voltage, 3A, 200kHz Step-Down Switching Regulator Input Voltages Up to 60V, Internal 0.1Ω Power Switch, Current Mode
Architecture, 16-Pin Exposed Pad TSSOP Package
LTC3722-1/
LTC3722-2
Synchronous Dual Mode Phase Modulated Full-Bridge
Controllers
Adaptive Zero Voltage Switching, High Output Power Levels
(Up to Kilowatts)
LT3781/LTC1698 36V to 72V Input Isolated DC/DC Converter Chip Set
Synchronous Rectification; Overcurrent, Overvoltage, UVLO Protection;
Power Good Output Signal; Voltage Margining; Compact Solution
4440i
LT/TP 1003 1K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
LINEAR TECHNOLOGY CORPORATION 2003
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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