LTC4440ES6-5#TR [Linear]

LTC4440-5 - High Speed, High Voltage, High Side Gate Driver; Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C;


型号：	LTC4440ES6-5#TR
厂家：	Linear
描述：	LTC4440-5 - High Speed, High Voltage, High Side Gate Driver; Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C 驱动器栅极栅极驱动
文件：	总12页 (文件大小：260K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC4440-5

High Speed, High Voltage,

High Side Gate Driver

FEATURES

DESCRIPTIO

The LTC^®4440-5 is a high frequency high side N-channel

MOSFET gate driver that is designed to operate in applica-

tions with V_INvoltages up to 60V. The LTC4440-5 can also

withstand and continue to function during 80V V_INtran-

sients. The powerful driver capability reduces switching

losses in MOSFETs with high gate capacitances. The

LTC4440-5’spull-uphasapeakoutputcurrentof1.1Aand

its pull-down has an output impedance of 1.85Ω.

■

Wide Operating V_INRange: Up to 60V

■

Rugged Architecture Tolerant of 80V V_INTransients

■

Powerful 1.85Ω Driver Pull-Down (with 6V Supply)

■

Powerful 1.1A Peak Current Driver Pull-Up

(with 6V Supply)

■

7ns Fall Time Driving 1000pF Load

■

10ns Rise Time Driving 1000pF Load

■

Drives Standard Threshold MOSFETs

■

TTL/CMOS Compatible Inputs with Hysteresis

The LTC4440-5 features supply independent TTL/CMOS

compatible input thresholds with 350mV of hysteresis.

The input logic signal is internally level-shifted to the

bootstrapped supply, which may function at up to 95V

above ground.

■

Input Thresholds are Independent of Supply

■

Undervoltage Lockout

Low Profile (1mm) SOT-23 (ThinSOT^TM) and

■

^{Thermally Enhan}U^{ced 8-Pin MSOP Packages}

APPLICATIO S

The LTC4440-5 is optimized for driving (5V) logic level

FETs and contains an undervoltage lockout circuit that

disables the external MOSFET when activated.

■

Telecommunications Power Systems

■

Distributed Power Architectures

■

The LTC4440-5 is available in the low profile (1mm)

SOT-23 or a thermally enhanced 8-lead MSOP package.

Server Power Supplies

■

High Density Power Modules

■

General Purpose Low-Side Driver

PARAMETER

LTC4440-5

60V

LTC4440

80V

, LTC and LT are registered trademarks of Linear Technology Corporation. ThinSOT is a

trademark of Linear Technology Corporation. All other trademarks are the property of their

respective owners. Protected by U.S. Patents including 6677210.

Max Operating TS

Absolute Max TS

80V

100V

MOSFET Gate Drive

4V to 15V

3.2V

8V to 15V

6.3V

–

3.04V

6.0V

TYPICAL APPLICATIO

Synchronous Phase-Modulated Full-Bridge Converter

LTC4440-5 Driving a 1000pF Capacitive Load

36V TO 60V

4V TO 15V

LTC4440-5

TG-TS

2V/DIV

BOOST

INP

GND

INP

2V/DIV

LTC4440-5

BOOST

•

LTC3722-1

INP

4440-5 TA02

50ns/DIV

GND

= BOOST-TS = 5V

4440 TA01

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LTC4440-5

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ABSOLUTE MAXIMUM RATINGS

(Note 1)

TS Voltage (100ms)..................................... –5V to 80V

Peak Output Current < 1µs (TG) ............................... 4A

Operating Ambient Temperature Range

(Note 2) .............................................. –40°C to 85°C

Junction Temperature (Note 3)............................ 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

Supply Voltage

V_CC....................................................... –0.3V to 15V

BOOST – TS ......................................... –0.3V to 15V

INP Voltage............................................... –0.3V to 15V

BOOST Voltage (Continuous) ................... –0.3V to 85V

BOOST Voltage (100ms) .......................... –0.3V to 95V

TS Voltage (Continuous) ............................. –5V to 70V

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PACKAGE/ORDER INFORMATION

TOP VIEW

INP

GND

8 TS

7 TG

6 BOOST

5 NC

6 BOOST

5 TG

GND 2

INP 3

GND

4 TS

MS8E PACKAGE

8-LEAD PLASTIC MSOP

S6 PACKAGE

6-LEAD PLASTIC SOT-23

T_JMAX= 125°C, θ_JA= 40°C/W (NOTE 4)

EXPOSED PAD IS GND (PIN 9), MUST BE SOLDERED TO PCB

T_JMAX= 125°C, θ_JA= 230°C/W

MS8E PART MARKING

LTBRG

S6 PART MARKING

LTBRF

ORDER PART NUMBER

LTC4440ES6-5

LTC4440EMS8E-5

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The

●

denotes specifications which apply over the full operating

= 6V, V = GND = 0V, unless otherwise noted.

temperature range, otherwise specifications are at T = 25°C. V = V

BOOST

SYMBOL PARAMETER

Main Supply (V

CONDITIONS

MIN

TYP

MAX

UNITS

)

DC Supply Current

Normal Operation

UVLO

VCC

INP = 0V

200

325

µA

< UVLO Threshold (Falling) – 0.1V

UVLO

Undervoltage Lockout Threshold

Rising

Falling

●

2.75

2.60

3.20

3.04

160

3.65

3.50

Hysteresis

Bootstrapped Supply (BOOST – TS)

DC Supply Current

Normal Operation

BOOST

INP = 0V

INP = 6V

310

µA

450

Input Signal (INP)

High Input Threshold

Low Input Threshold

Input Voltage Hysteresis

Input Pin Bias Current

INP Ramping High

INP Ramping Low

●

1.2

0.8

1.6

1.25

1.6

– V

0.350

±0.01

±2

µA

INP

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LTC4440-5

ELECTRICAL CHARACTERISTICS

The

●

denotes specifications which apply over the full operating

= 6V, V = GND = 0V, unless otherwise noted.

temperature range, otherwise specifications are at T = 25°C. V = V

BOOST

SYMBOL PARAMETER

Output Gate Driver (TG)

CONDITIONS

MIN

TYP

MAX

UNITS

High Output Voltage

= –10mA, V = V

– V

0.7

185

1.1

BOOST

Low Output Voltage

= 100mA

●

275

Peak Pull-Up Current

Output Pull-Down Resistance

0.75

1.85

2.75

Ω

Switching Timing

Output Rise Time

10% – 90%, C = 1nF

100

10% – 90%, C = 10nF

Output Fall Time

10% – 90%, C = 1nF

10% – 90%, C = 10nF

Output Low-High Propagation Delay

Output High-Low Propagation Delay

●

PLH

PHL

Note 3: T is calculated from the ambient temperature T and power

dissipation PD according to the following formula:

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

T = T + (PD • θ °C/W)

Note 4: Failure to solder the exposed back side of the MS8E package to

the PC board will result in a thermal resistance much higher than 40°C/W.

Note 2: The LTC4440-5 is guaranteed to meet performance specifications

from 0°C to 85°C. Specifications over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls.

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TYPICAL PERFOR A CE CHARACTERISTICS

Supply Quiescent Current

BOOST-TS Supply Quiescent

Current vs Voltage

Output Low Voltage (V

)

vs Voltage

vs Supply Voltage

350

300

250

200

150

100

300

250

200

150

100

400

350

300

250

INP = V

INP = GND

INP = V

200

150

100

SUPPLY VOLTAGE (V)

10 11 12 13 14 15

BOOST-TS SUPPLY VOLTAGE (V)

4440-5 G01

4440-5 G03

4440-5 G02

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LTC4440-5

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TYPICAL PERFOR A CE CHARACTERISTICS

Output High Voltage (V

vs Supply Voltage

)

Input (INP) Thresholds

vs Supply Voltage

2MHz Operation

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

INPUT

(INP)

5V/DIV

= 1mA

= 10mA

= 100mA

OUTPUT

(TG)

5V/DIV

4440-5 G07

250ns/DIV

= BOOST-TS = 12V

11 12 13 14 15

10 11 12 13 14 15

BOOST-TS SUPPLY VOLTAGE (V)

SUPPLY VOLTAGE (V)

4440-5 G04

4440-5 G05

BOOST-TS Quiescent Current

vs Temperature

Supply Current

Undervoltage Lockout

vs Temperature

Thresholds vs Temperature

3.5

3.4

3.3

3.2

3.1

3.0

2.9

2.8

2.7

2.6

2.5

250

200

400

350

300

250

200

150

100

INP = GND

RISING

INP = V

150

FALLING

100

–55 –35 –15

25 45 65 85 105 125

25 45

–55 –35 –15

25 45 65

105 125

–55 –35 –15

65 85 105 125

TEMPERATURE (°C)

4440-5 G08

4440-5 G09

4440-5 G10

Input (INP) Threshold

vs Temperature

Input Threshold Hysteresis

vs Temperature

Peak Driver (TG) Pull-Up Current

vs Temperature

3.5

3.0

2.5

2.0

1.5

1.0

0.5

2.0

1.8

380

370

360

350

340

330

320

310

300

BOOST-TS = 15V

BOOST-TS = 12V

1.6

1.4

1.2

BOOST-TS = 6V

BOOST-TS = 4V

1.0

0.8

–55 –35 –15

25 45 65 85 105 125

25 45

–55 –35 –15

65 85 105 125

–55 –35 –15

25 45 65 85 105 125

TEMPERATURE (°C)

4440-5 G13

4440-5 G12

4440-5 G11

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LTC4440-5

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TYPICAL PERFOR A CE CHARACTERISTICS

Output Driver Pull-Down

Resistance vs Temperature

Propagation Delay vs Temperature

3.0

2.5

= BOOST = 6V

BOOST-TS = 4V

BOOST-TS = 6V

2.0

PLH

1.5

1.0

BOOST-TS = 15V

BOOST-TS = 12V

PHL

0.5

–55 –35 –15

25 45 65 85 105 125

–55 –35 –15

25 45 65 85 105 125

TEMPERATURE (°C)

4440-5 G14

4440-5 G15

Driving a 3300pF Capacitive Load

TG-TS

5V/DIV

TG-TS

2V/DIV

INP

2V/DIV

INP

2V/DIV

4440-5 G17

4440-5 G16

50ns/DIV

= BOOST-TS = 12V

50ns/DIV

= BOOST-TS = 5V

PI FU CTIO S

SOT-23 Package

V_CC(Pin 1): Chip Supply. This pin powers the internal low

side circuitry. A low ESR ceramic bypass capacitor should

be tied between this pin and the GND pin (Pin 2).

TG (Pin 5): High Current Gate Driver Output (Top Gate).

This pin swings between TS and BOOST.

BOOST (Pin 6): High Side Bootstrapped Supply. An exter-

nal capacitor should be tied between this pin and TS

(Pin 4). Normally, abootstrapdiodeisconnectedbetween

V_CC(Pin 1) and this pin. Voltage swing at this pin is from

V_CC– V_Dto V_IN+ V_CC– V_D, where V_Dis the forward voltage

drop of the bootstrap diode.

GND (Pin 2): Chip Ground.

INP (Pin 3): Input Signal. TTL/CMOS compatible input

referenced to GND (Pin 2).

TS (Pin 4): Top (High Side) source connection or GND if

used in ground referenced applications.

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LTC4440-5

PI FU CTIO S

Exposed Pad MS8E Package

INP (Pin 1): Input Signal. TTL/CMOS compatible input

BOOST (Pin 6): High Side Bootstrapped Supply. An exter-

nal capacitor should be tied between this pin and TS

(Pin 8). Normally, abootstrapdiodeisconnectedbetween

referenced to GND (Pin 2).

GND (Pins 2, 4): Chip Ground.

_CC(Pin 3) and this pin. Voltage swing at this pin is from

_CC– V_Dto V_IN+ V_CC– V_D, where V_Dis the forward voltage

_CC(Pin 3): Chip Supply. This pin powers the internal low

side circuitry. A low ESR ceramic bypass capacitor should

be tied between this pin and the GND pin (Pin 2).

drop of the bootstrap diode.

TG (Pin 7): High Current Gate Driver Output (Top Gate).

This pin swings between TS and BOOST.

NC (Pin 5): No Connect. No connection required. For

convenience, this pin may be tied to Pin 6 (BOOST) on the

application board.

TS (Pin 8): Top (High Side) source connection or GND if

used in ground referenced applications.

Exposed Pad (Pin 9): Ground. Must be electrically con-

nected to Pins 2 and 4 and soldered to PCB ground for

optimum thermal performance.

BLOCK DIAGRA

UP TO 60V,

TRANSIENT

UP TO 80V

BOOST

UNDERVOLTAGE

LOCKOUT

4V TO 15V

GND

BOOST

INP

LEVEL SHIFTER

44405 BD

GND

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TI I G DIAGRA

INPUT RISE/FALL TIME <10ns

INPUT (INP)

90%

10%

OUTPUT (TG)

PHL

PLH

4440 TD

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LTC4440-5

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APPLICATIO S I FOR ATIO

BOOST

Overview

UP TO 100V

TheLTC4440-5receivesaground-referenced,lowvoltage

digital input signal to drive a high side N-channel power

MOSFET whose drain can float up to 80V above ground,

eliminating the need for a transformer between the low

voltage control signal and the high side gate driver. The

LTC4440-5 normally operates in applications with input

supply voltages (V_IN) up to 60V, but is able to withstand

and continue to function during 80V, 100ms transients on

the input supply.

LTC4440-5

POWER

MOSFET

LOAD

INDUCTOR

4440 F01

–

Figure 1. Capacitance Seen by TG During Switching

discharge the power MOSFET’s gate capacitance during

high-to-lowsignaltransitions.WhenthepowerMOSFET’s

gate is pulled low (gate shorted to source through N1) by

the LTC4440-5, its source (TS) is pulled low by its load

(e.g., an inductor or resistor). The slew rate of the source/

gate voltage causes current to flow back to the MOSFET’s

gate through the gate-to-drain capacitance (C_GD). If the

MOSFET driver does not have sufficient sink current

capability (low output impedance), the current through

the power MOSFET’s C_GDcan momentarily pull the gate

high, turning the MOSFET back on.

The powerful output driver of the LTC4440-5 reduces the

switching losses of the power MOSFET, which increase

with transition time. The LTC4440-5 is capable of driving

a 1nF load with 10ns rise and 7ns fall times using a

bootstrapped supply voltage V_BOOST–TSof 6V.

Input Stage

TheLTC4440-5employsTTL/CMOScompatibleinputlogic

level or thresholds that allow a low voltage digital signal to

drive standard threshold power MOSFETs. The LTC4440-

5containsaninternalvoltageregulatorthatbiasestheinput

buffer, allowing the input thresholds (V_IH= 1.6V, V_IL=

1.25V)toberelativelyindependentofvariationsinV_CC.The

350mV hysteresis between V_IHand V_ILeliminates false

triggering due to noise during switching transitions. How-

ever, care should be taken to keep this pin from any noise

pickup, especially in high frequency, high voltage applica-

tions. The LTC4440-5 input buffer has a high input imped-

ance and draws negligible input current, simplifying the

drive circuitry required for the input.

A similar scenario exists when the LTC4440-5 is used to

drive a low side MOSFET. When the low side power

MOSFET’s gate is pulled low by the LTC4440-5, its drain

voltage is pulled high by its load (e.g., inductor or resis-

tor). The slew rate of the drain voltage causes current to

flow back to the MOSFET’s gate through its gate-to-drain

capacitance. If the MOSFET driver does not have sufficient

sink current capability (low output impedance), the cur-

rent through the power MOSFET’s C_GDcan momentarily

pull the gate high, turning the MOSFET back on.

Output Stage

Rise/Fall Time

A simplified version of the LTC4440-5’s output stage is

shown in Figure 1 . The pull-down device is an N-channel

MOSFET (N1) and the pull-up device is an NPN bipolar

junctiontransistor(Q1).Theoutputswingsfromthelower

rail (TS) to within an NPN V_BE(~0.7V) of the positive rail

(BOOST). This large voltage swing is important in driving

external power MOSFETs, whose R_DS(ON)is inversely

proportional to its gate overdrive voltage (V_GS– V_TH).

Since the power MOSFET generally accounts for the

majority of the power loss in a converter, it is important to

quickly turn it on or off, thereby minimizing the transition

time in its linear region. The LTC4440-5 can drive a 1nF

load with a 10ns rise time and 7ns fall time.

The LTC4440-5’s rise and fall times are determined by the

peak current capabilities of Q1 and N1. The predriver that

drivesQ1andN1usesanonoverlappingtransitionscheme

to minimize cross-conduction currents. N1 is fully turned

The LTC4440-5’s peak pull-up (Q1) current is 1.1A while

the pull-down (N1) resistance is 1.85Ω, with a BOOST-TS

supply of 6V. The low impedance of N1 is required to

off before Q1 is turned on and vice versa.

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LTC4440-5

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APPLICATIO S I FOR ATIO

Power Dissipation

nodal capacitances and cross-conduction currents in the

internal gates.

To ensure proper operation and long-term reliability, the

LTC4440-5 must not operate beyond its maximum tem-

perature rating. Package junction temperature can be

calculated by:

Undervoltage Lockout (UVLO)

TheLTC4440-5containsanundervoltagelockoutdetector

that monitors V_CC. When V_CCfalls below 3.04V, the

internal buffer is disabled and the output pin TG is pulled

down to TS.

T_J= T_A+ PD (θ_JA)

where:

T_J= Junction Temperature

T_A= Ambient Temperature

PD = Power Dissipation

Bypassing and Grounding

The LTC4440-5 requires proper bypassing on the V_CCand

_BOOST–TSsuppliesduetoitshighspeedswitching(nano-

_JA= Junction-to-Ambient Thermal Resistance

seconds) and large AC currents (Amperes). Careless

component placement and PCB trace routing may cause

excessive ringing and under/overshoot.

Power dissipation consists of standby and switching

power losses:

PD = P_STDBY+ P_AC

where:

To obtain the optimum performance from the LTC4440-5:

A. Mount the bypass capacitors as close as possible

between the V_CCand GND pins and the BOOST and TS

pins. The leads should be shortened as much as pos-

sible to reduce lead inductance.

P_STDBY= Standby Power Losses

P_AC= AC Switching Losses

The LTC4440-5 consumes very little current during

B. Use a low inductance, low impedance ground plane to

reduceanygrounddropandstraycapacitance.Remem-

berthattheLTC4440-5switches>2Apeakcurrentsand

anysignificantgrounddropwilldegradesignalintegrity.

standby. The DC power loss at V_CC= 6V and V_BOOST–TS

6V is only (250µA)(5V) = 1.2mW with INP = 0V.

AC switching losses are made up of the output capacitive

load losses and the transition state losses. The capacitive

load losses are primarily due to the large AC currents

needed to charge and discharge the load capacitance

duringswitching. Loadlossesfortheoutputdriverdriving

a pure capacitive load C_OUTwould be:

C. Plan the power/ground routing carefully. Know where

the large load switching current is coming from and

going to. Maintain separate ground return paths for the

input pin and the output power stage.

D. Keepthecoppertracebetweenthedriveroutputpinand

the load short and wide.

Load Capacitive Power = (C_OUT)(f)(V_BOOST–TS

)

The power MOSFET’s gate capacitance seen by the driver

output varies with its V_GSvoltage level during switching.

A power MOSFET’s capacitive load power dissipation can

be calculated using its gate charge, Q_G. The Q_Gvalue

corresponding to the MOSFET’s V_GSvalue (V_CCin this

case) can be readily obtained from the manufacturer’s Q_G

vs V_GScurves:

E. When using the MS8E package, be sure to solder the

exposed pad on the back side of the LTC4440-5 pack-

age to the board. Correctly soldered to a 2500mm²

double-sided 1oz copper board, the LTC4440-5 has a

thermal resistance of approximately 40°C/W. Failure to

make good thermal contact between the exposed back

side and the copper board will result in thermal resis-

tances far greater than 40°C/W.

Load Capacitive Power (MOS) = (V_BOOST–TS)(Q_G)(f)

Transition state power losses are due to both AC currents

required to charge and discharge the driver’s internal

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LTC4440-5

TYPICAL APPLICATIO S

•

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LTC4440-5

TYPICAL APPLICATIO S

•

E F F I C I E N C Y ( % )

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LTC4440-5

PACKAGE DESCRIPTION

MS8E Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1662)

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.889 ± 0.127

(.035 ± .005)

2.794 ± 0.102

(.110 ± .004)

0.52

(.0205)

REF

2.06 ± 0.102

(.081 ± .004)

1.83 ± 0.102

(.072 ± .004)

7 6

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

2.083 ± 0.102

(.082 ± .004)

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

4.90 ± 0.152

(.193 ± .006)

DETAIL “A”

0.254

(.010)

0° – 6° TYP

0.65

(.0256)

BSC

0.42 ± 0.038

(.0165 ± .0015)

TYP

GAUGE

PLANE

0.53 ± 0.152

(.021 ± .006)

BOTTOM VIEW OF

EXPOSED PAD OPTION

1.10

(.043)

MAX

0.86

(.034)

REF

RECOMMENDED SOLDER PAD LAYOUT

DETAIL “A”

0.18

(.007)

SEATING

PLANE

NOTE:

0.22 – 0.38

(.009 – .015)

TYP

0.127 ± 0.076

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

(.005 ± .003)

0.65

(.0256)

BSC

MSOP (MS8E) 0603

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

S6 Package

6-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1636)

0.62

MAX

0.95

REF

2.90 BSC

(NOTE 4)

1.22 REF

1.50 – 1.75

(NOTE 4)

2.80 BSC

1.4 MIN

3.85 MAX 2.62 REF

PIN ONE ID

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

0.30 – 0.45

6 PLCS (NOTE 3)

0.95 BSC

0.80 – 0.90

0.20 BSC

DATUM ‘A’

0.01 – 0.10

1.00 MAX

0.30 – 0.50 REF

1.90 BSC

0.09 – 0.20

(NOTE 3)

S6 TSOT-23 0302 REV B

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

44405fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

LTC4440-5

TYPICAL APPLICATIO

240W 42V-56V to Unregulated 12V Half-Bridge Converter

0.56µH

48V

–V

1µF

100V

1µF

OUT

L2 0.22µH

1µF

100V

11V

100V

OUT

1500pF

100V

20Ω 1W

70(980µH):1

180µF

16V

INP BOOST

LTC4440-5ES6

1µF

100V

1µF

100V

1µF

Si7370DP

×2

Si7852DP

×2

GND TS

–V

OUT

0.22µF

2.2nF

250V

–V

OUT

12V

4.7k

1/4W

4.7k

1/4W

1mH

68µF

5:4:4:2:2

Si7852DP

×2

10k 3k

12V

MMBT3904

11V

12 14 15

–

33.2k

100Ω

MMBT3904

CSF

CSF MF MF2 CSE

CSE ME ME2 V

OUT

1(1.5mH):0.5

15k

1/4W

120Ω

LTC3901EGN

DRVA DRVB

SYNC

SDRB

0.1µF

100Ω

GND PGND GND2 PGND2

10 13

TIMER

22Ω

1µF

LTC3723EGN-2

215k

SDRA

10V

MMBZ5240B

220pF

UVLO

DPRG

COMP

330pF

0.22µF

REF

RAMP

SPRG GND CS SS FB

4440 TA04

–V

OUT

1µF, 100V TDK C4532X7R2A105M L1: COILCRAFT DO1813P-561HC

1µF

10 14 13

100pF

C1: MURATA DE2E3KH222MB3B

C2: SANYO 16SP180M

C3: AVX TPSE686M020R0150

D1-D3: BAS21

L2: SUMIDA CDEP105-0R2NC-50

L3: COILCRAFT DO1608C-105

T1: PULSE PA0801.005

T2: PULSE P8207

62k

1µF

150pF

10k

2N7002

4.7k

30.1k

0.47µF

330pF

0.47µF

470pF

7.5Ω 7.5Ω

D4, D5: MMBD914

T3: PULSE PA0785

12V

MMBZ5242B

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PolyPhase is a registered trademark of Linear Technology Corporation.

44405fa

LT 1205 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

LTC4440ES6-5#TR [Linear]

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