LTC6240HVHS5#TRM [Linear]
IC OP-AMP, 450 uV OFFSET-MAX, 12 MHz BAND WIDTH, PDSO5, PLASTIC, MO-193, TSOT-23, 5 PIN, Operational Amplifier;
| 型号： | LTC6240HVHS5#TRM |
| 厂家： | 
Linear |
| 描述： | IC OP-AMP, 450 uV OFFSET-MAX, 12 MHz BAND WIDTH, PDSO5, PLASTIC, MO-193, TSOT-23, 5 PIN, Operational Amplifier 运算放大器 放大器电路 |
| 文件： | 总28页 (文件大小：515K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6240/LTC6241/LTC6242
Single/Dual/Quad 18MHz,
Low Noise, Rail-to-Rail Output,
CMOS Op Amps
U
DESCRIPTIO
FEATURES
The LTC®6240/6241/LTC6242 are single, dual and quad
low noise, low offset, rail-to-rail output, unity gain stable
CMOSopampsthatfeature1pAofinputbiascurrent.Input
bias current is guaranteed to be 1pA max on the single
■
0.1Hz to 10Hz Noise: 550nV
P-P
■
Input Bias Current:
0.2pA (Typ at 25°C)
1pA Max (LT6240)
■
Low Offset Voltage: 125µV Max
LTC6240. The0.1Hzto10Hznoiseofonly550nV , along
P-P
■
■
■
■
Low Offset Drift: 2.5µV/°C Max
with an offset of just 125µV are significant improvements
over traditional CMOS op amps. Additionally, noise is
guaranteed to be less than 10nV/√Hz at 1kHz. An 18MHz
gain bandwidth, and 10V/µs slew rate, along with the wide
supplyrangeandlowinputcapacitance,makethemperfect
for use as fast signal processing amplifiers.
Gain Bandwidth Product: 18MHz
Output Swings Rail-to-Rail
Supply Operation:
2.8V to 6V LTC6240/LTC6241/LTC6242
2.8V to 5.5V LTC6240HV/LTC6241HV/LTC6242HV
Low Input Capacitance
H Grade Temperature Range: –40°C to 125°C
Single LTC6240 in 5-Pin SOT-23 Package and
8-Pin SO for PCB Guard Ring
Dual LTC6241 in 8-Pin SO and Tiny DFN Packages
Quad LTC6242 in 16-Pin SSOP and 5mm × 3mm
DFN Packages
■
■
■
These op amps have an output stage that swings within
30mV of either supply rail to maximize the signal dynamic
rangeinlowsupplyapplications.Theinputcommonmode
range extends to the negative supply. They are fully speci-
fiedon3Vand5V, andanHVversionguaranteesoperation
on supplies up to 5V.
■
■
U
The LTC6240 is available in the 8-pin SO and the 5-pin
SOT-23 packages. The LTC6241 is available in the 8-pin
SO, and for compact designs it is packaged in a tiny dual
fine pitch leadless (DFN) package. The LTC6242 is avail-
able in the 16-Pin SSOP as well as the 5mm × 3mm DFN
package.
APPLICATIO S
■
Photo Diode Amplifiers
■
Charge Coupled Amplifiers
■
Low Noise Signal Processing
Medical Instrumentation
High Impedance Transducer Amplifier
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
U
TYPICAL APPLICATIO
Low Noise Single-Ended Input to Differential Output Amplifier
Noise Voltage vs Frequency
60
C3
10pF
T
V
V
= 25°C
A
S
=
2.5V
= 0V
50
40
30
20
10
0
CM
C4
10pF
R4
4.99k
C1
10pF
+2.5V
1/2
R1
200k
R3
4.99k
V
–
IN
+
–
V
V
OUT
OUT
LTC6241
+
–
–2.5V
1/2
LTC6241
+
R2
200k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
6241 TA01b
C2
10pF
6241 TA01a
624012fc
1
LTC6240/LTC6241/LTC6242
W W U W
(Note 1)
ABSOLUTE AXI U RATI GS
Total Supply Voltage (V to V )
+
–
Specified Temperature Range (Note 3)
LTC6240/LTC6241/LTC6242 ...................................7V
LTC6240HV/LTC6241HV/LTC6242HV ...................12V
Input Voltage.......................... (V + 0.3V) to (V – 0.3V)
Input Current........................................................ 10mA
Output Short Circuit Duration (Note 2) ............ Indefinite
Operating Temperature Range
LTC6240C/LTC6241C/LTC6242C.............. 0°C to 70°C
LTC6240I/LTC6241I/LTC6242I............. –40°C to 85°C
LTC6240H/LTC6241H/LTC6242H....... –40°C to 125°C
Junction Temperature ........................................... 150°C
DHC, DD Package ............................................. 125°C
Storage Temperature Range....................–65ºC to 150°C
DHC, DD Package ...............................–65ºC to 125°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
+
–
LTC6240C/LTC6241C/LTC6242C.......... –40°C to 85°C
LTC6240I/LTC6241I/LTC6242I............. –40°C to 85°C
LTC6240H/LTC6241H/LTC6242H....... –40°C to 125°C
U
W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER S5 PART MARKING*
LTC6240CS5
LTC6240HVCS5
LTC6240IS5
LTC6240HVIS5
LTC6240HS5
LTC6240HVHS5
LTCRR
LTCRS
LTCRR
LTCRS
LTCRR
LTCRS
TOP VIEW
TOP VIEW
NC
–IN
+IN
1
2
3
4
8
7
6
5
NC
+
–
+
OUT 1
–
5 V
+
V
V
2
OUT
NC
+IN 3
4 –IN
–
ORDER PART NUMBER S8 PART MARKING
V
S5 PACKAGE
5-LEAD PLASTIC TSOT-23
S8 PACKAGE
8-LEAD PLASTIC SO
LTC6240CS8
LTC6240HVCS8
LTC6240IS8
6240
6240HV
6240I
T
= 150°C, θ = 250°C/W
JMAX
JA
T
= 150°C, θ = 190°C/W
JMAX
JA
LTC6240HVIS8
LTC6240HS8
LTC6240HVHS8
240HVI
6240H
240HVH
ORDER PART NUMBER DD PART MARKING*
LTC6241CDD
LTC6241HVCDD
LTC6241IDD
LBPD
LBRR
LBPD
LBRR
TOP VIEW
TOP VIEW
+
OUT A
1
2
3
4
8
7
6
5
V
+
OUT A
–IN A
+IN A
1
2
3
4
8
7
6
5
V
–IN A
OUT B
–IN B
+IN B
LTC6241HVIDD
A
OUT B
–IN B
+IN B
A
+IN A
B
ORDER PART NUMBER S8 PART MARKING
–
V
B
–
V
LTC6241CS8
LTC6241HVCS8
LTC6241IS8
LTC6241HVIS8
LTC6241HS8
LTC6241HVHS8
6241
6241HV
6241I
241HVI
6241H
241HVH
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
= 125°C, θ = 43°C/W
S8 PACKAGE
8-LEAD PLASTIC SO
= 150°C, θ = 190°C/W
T
JMAX
JA
T
JMAX
JA
–
UNDERSIDE METAL CONNECTED TO V
(PCB CONNECTION OPTIONAL)
624012fc
2
LTC6240/LTC6241/LTC6242
U
W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER DHC PART MARKING*
TOP VIEW
TOP VIEW
LTC6242CDHC
LTC6242HVCDHC
LTC6242IDHC
6242
OUT A
–IN A
+IN A
1
2
3
4
5
6
7
8
16 OUT D
15 –IN D
OUT A
–IN A
+IN A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUT D
–IN D
+IN D
6242HV
6242
A
B
D
C
A
B
D
C
14 +IN D
–
+
V
13 V
LTC6242HVIDHC
6242HV
+
–
17
V
V
+IN B
–IN B
OUT B
NC
12 +IN C
11 –IN C
10 OUT C
+IN B
–IN B
OUT B
NC
+IN C
–IN C
OUT C
NC
ORDER PART NUMBER GN PART MARKING
LTC6242CGN
LTC6242HVCGN
LTC6242IGN
LTC6242HVIGN
LTC6242HGN
LTC6242HVHGN
6242
6242HV
6242I
242HVI
6242H
242HVH
9
NC
DHC16 PACKAGE
16-LEAD (5mm × 3mm) PLASTIC DFN
= 125°C, θ = 43°C/W
GN PACKAGE
16-LEAD PLASTIC SSOP
= 150°C, θ = 135°C/W
T
JMAX
JA
–
T
JMAX
JA
UNDERSIDE METAL CONNECTED TO V
(PCB CONNECTION OPTIONAL)
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
U
AVAILABLE OPTIO S
PART NUMBER
LTC6240CS5
AMPS/PACKAGE
SPECIFIED TEMP RANGE
0°C to 70°C
SPECIFIED SUPPLY VOLTAGE
3V, 5V
PACKAGE
SOT-23
SO-8
SOT-23
SO-8
SOT-23
SO-8
SOT-23
SO-8
SOT-23
SO-8
SOT-23
SO-8
SO-8
DD
PART MARKING
LTCRR
6240
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
LTC6240CS8
0°C to 70°C
3V, 5V
LTC6240HVCS5
LTC6240HVCS8
LTC6240IS5
0°C to 70°C
3V, 5V, 5V
3V, 5V, 5V
3V, 5V
LTCRS
6240HV
LTCRR
6240I
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
0°C to 70°C
LTC6240IS8
3V, 5V
LTC6240HVIS5
LTC6240HVIS8
LTC6240HS5
LTC6240HS8
LTC6240HVHS5
LTC6240HVHS8
LTC6241CS8
3V, 5V, 5V
3V, 5V, 5V
3V, 5V
LTCRS
240HVI
LTCRR
6240H
LTCRS
240HVH
6241
3V, 5V
3V, 5V, 5V
3V, 5V, 5V
3V, 5V
LTC6241CDD
LTC6241HVCS8
LTC6241HVCDD
LTC6241IS8
0°C to 70°C
3V, 5V
LBPD
0°C to 70°C
3V, 5V, 5V
3V, 5V, 5V
3V, 5V
SO-8
DD
6241HV
LBRR
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
SO-8
DD
6241I
LTC6241IDD
3V, 5V
LBPD
LTC6241HVIS8
LTC6241HVIDD
LTC6241HS8
LTC6241HVHS8
3V, 5V, 5V
3V, 5V, 5V
3V, 5V
SO-8
DD
241HVI
LBRR
SO-8
SO-8
6241H
241HVH
3V, 5V, 5V
624012fc
3
LTC6240/LTC6241/LTC6242
U
AVAILABLE OPTIO S
PART NUMBER
AMPS/PACKAGE
SPECIFIED TEMP RANGE
0°C to 70°C
SPECIFIED SUPPLY VOLTAGE
3V, 5V
PACKAGE
GN
PART MARKING
6242
LTC6242CGN
4
4
4
4
4
4
4
4
4
4
LTC6242CDHC
LTC6242HVCGN
LTC6242HVCDHC
LTC6242IGN
0°C to 70°C
3V, 5V
DHC
GN
6242
0°C to 70°C
3V, 5V, 5V
3V, 5V, 5V
3V, 5V
6242HV
6242HV
6242I
0°C to 70°C
DHC
GN
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
LTC6242IDHC
LTC6242HVIGN
LTC6242HVIDHC
LTC6242HGN
3V, 5V
DHC
GN
6242
3V, 5V, 5V
3V, 5V, 5V
3V, 5V
242HVI
6242HV
6242H
DHC
GN
LTC6242HVHGN
3V, 5V, 5V
GN
242HVH
ELECTRICAL CHARACTERISTICS (LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I,
LTC6242HVC/I) The ● denotes the specifications which apply over the specified temperature range, otherwise specifications are at
TA = 25°C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
OS
Input Offset Voltage (Note 4)
LTC6241 S8
0°C to 70°C
–40°C to 85°C
40
125
250
300
µV
µV
µV
●
●
LTC6242 GN
0°C to 70°C
–40°C to 85°C
50
50
150
275
300
µV
µV
µV
●
●
LTC6240
0°C to 70°C
–40°C to 85°C
175
300
350
µV
µV
µV
●
●
LTC6241 DD, LTC6242 DHC
0°C to 70°C
100
40
550
650
725
µV
µV
µV
●
●
–40°C to 85°C
V
Match Channel-to-Channel (Note 5) LTC6241 S8
160
300
375
µV
µV
µV
OS
●
●
0°C to 70°C
–40°C to 85°C
LTC6242 GN
0°C to 70°C
–40°C to 85°C
50
185
325
400
µV
µV
µV
●
●
LTC6241 DD, LTC6242 DHC
0°C to 70°C
–40°C to 85°C
150
650
700
750
µV
µV
µV
●
●
●
●
●
●
●
TC V
Input Offset Voltage Drift (Note 6)
Input Bias Current (Notes 4, 7)
0.7
0.2
2.5
µV/°C
OS
I
LTC6241, LTC6242
LTC6240
pA
pA
B
75
0.2
0.2
0.2
550
1
75
pA
pA
I
OS
Input Offset Current (Notes 4, 7)
Input Noise Voltage
LTC6241, LTC6242
LTC6240
pA
pA
75
1
75
pA
pA
0.1Hz to 10Hz
nV
P-P
624012fc
4
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS (LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I,
LTC6242HVC/I) The ● denotes the specifications which apply over the specified temperature range, otherwise specifications are at
TA = 25°C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
7
MAX
UNITS
nV/√Hz
fA/√Hz
Ω
e
n
Input Noise Voltage Density
Input Noise Current Density (Note 8)
Input Resistance
f = 1kHz
10
i
n
0.56
12
R
IN
Common Mode
f = 100kHz
10
C
IN
Input Capacitance
Differential Mode
Common Mode
3.5
3
pF
pF
●
●
V
Input Voltage Range
Guaranteed by CMRR
0
3.5
V
CM
CMRR
Common Mode Rejection
0V ≤ V ≤ 3.5V
80
105
95
dB
CM
CMRR Match
Channel-to-Channel (Note 5)
●
76
dB
A
VOL
Large Signal Voltage Gain
V = 1V to 4V
O
R = 10k to V /2
425
300
200
1600
V/mV
V/mV
V/mV
L
S
●
●
0°C to 70°C
–40°C to 85°C
V = 1.5V to 3.5V
O
R = 1k to V /2
90
60
50
215
V/mV
V/mV
V/mV
L
S
●
●
0°C to 70°C
–40°C to 85°C
●
●
●
V
V
Output Voltage Swing Low (Note 9)
Output Voltage Swing High (Note 9)
Power Supply Rejection
No Load
SINK
SINK
7
30
75
mV
mV
mV
OL
I
I
= 1mA
= 5mA
40
190
325
●
●
●
No Load
SOURCE
SOURCE
11
45
190
30
75
325
mV
mV
mV
OH
I
I
= 1mA
= 5mA
●
PSRR
V = 2.8V to 6V, V = 0.2V
S
80
104
100
dB
CM
PSRR Match
Channel-to-Channel (Note 5)
●
●
●
74
2.8
15
dB
V
Minimum Supply Voltage (Note 10)
Short-Circuit Current
I
I
30
mA
SC
S
Supply Current per Amplifier
LTC6241, LTC6242
0°C to 70°C
–40°C to 85°C
1.8
2.2
2.3
2.4
mA
mA
mA
●
●
LTC6240
0°C to 70°C
–40°C to 85°C
2
2.4
2.5
2.6
mA
mA
mA
●
●
●
●
●
GBW
SR
Gain Bandwidth Product
Slew Rate (Note 11)
Frequency = 20kHz, R = 1kΩ
13
5
18
10
MHz
V/µs
MHz
ns
L
A = –2, R = 1kΩ
V
L
FPBW
Full Power Bandwidth (Note 12)
Settling Time
V
OUT
= 3V , R = 1kΩ
0.53
1.06
1100
P-P
L
t
s
V = 2V, A = –1, R = 1kΩ, 0.1%
STEP V L
624012fc
5
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS (LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I,
LTC6242HVC/I) The ● denotes the specifications which apply over the specified temperature range, otherwise specifications are at
TA = 25°C. VS = 3V, 0V, VCM = 1.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
OS
Input Offset Voltage (Note 4)
LTC6241 S8
0°C to 70°C
–40°C to 85°C
40
175
275
325
µV
µV
µV
●
●
LTC6242 GN
0°C to 70°C
–40°C to 85°C
LTC6240
0°C to 70°C
–40°C to 85°C
60
50
200
275
325
200
325
375
µV
µV
µV
µV
µV
µV
●
●
●
●
LTC6241 DD, LTC6242 DHC
0°C to 70°C
100
40
550
650
725
200
325
400
µV
µV
µV
µV
µV
µV
●
●
–40°C to 85°C
V
OS
Match Channel-to-Channel (Note 5) LTC6241 S8
●
●
0°C to 70°C
–40°C to 85°C
LTC6242 GN
0°C to 70°C
–40°C to 85°C
60
225
325
400
µV
µV
µV
●
●
LTC6241 DD, LTC6242 DHC
0°C to 70°C
–40°C to 85°C
150
650
700
750
µV
µV
µV
●
●
●
●
●
●
TC V
Input Offset Voltage Drift (Note 6)
Input Bias Current (Notes 4, 7)
0.7
0.2
2.5
µV/°C
OS
I
B
LTC6241, LTC6242
LTC6240
pA
pA
pA
pA
pA
pA
pA
pA
75
1
75
0.2
0.2
0.2
I
OS
Input Offset Current (Notes 4, 7)
LTC6241, LTC6242
LTC6240
75
1
75
●
●
●
V
CM
Input Voltage Range
Common Mode Rejection
CMRR Match
Channel-to-Channel (Note 5)
Guaranteed by CMRR
0
78
1.5
V
dB
CMRR
0V ≤ V ≤ 1.5V
100
95
CM
●
76
dB
A
Large Signal Voltage Gain
V = 1V to 2V
O
VOL
R = 10k to V /2
140
100
75
600
V/mV
V/mV
V/mV
mV
mV
mV
mV
dB
L
S
●
●
0°C to 70°C
–40°C to 85°C
No Load
●
●
V
V
Output Voltage Swing Low (Note 9)
Output Voltage Swing High (Note 9)
Power Supply Rejection
PSRR Match
Channel-to-Channel (Note 5)
Minimum Supply Voltage (Note 10)
Short-Circuit Current
Supply Current per Amplifier
3
65
4
70
104
100
30
OL
I
= 1mA
110
SINK
●
●
No Load
= 1mA
30
120
OH
I
SOURCE
●
PSRR
V = 2.8V to 6V, V = 0.2V
S
80
CM
●
●
●
74
2.8
3
dB
V
mA
mA
mA
mA
I
I
6
1.4
SC
LTC6241, LTC6242
0°C to 70°C
–40°C to 85°C
1.7
1.8
1.9
S
●
●
LTC6240
1.5
17
1.9
2
2.1
mA
mA
mA
●
●
0°C to 70°C
–40°C to 85°C
●
GBW
Gain Bandwidth Product
Frequency = 20kHz, R = 1kΩ
12
MHz
L
624012fc
6
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS (LTC6240HVC/I, LTC6241HVC/I, LTC6242HVC/I) The ● denotes the
specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C. VS = 5V, 0V, VCM = 0V
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
OS
Input Offset Voltage (Note 4)
LTC6241 S8
0°C to 70°C
–40°C to 85°C
50
175
275
325
µV
µV
µV
●
●
LTC6242 GN
0°C to 70°C
–40°C to 85°C
LTC6240
0°C to 70°C
–40°C to 85°C
60
60
200
275
325
250
350
400
µV
µV
µV
µV
µV
µV
●
●
●
●
LTC6241 DD, LTC6242 DHC
0°C to 70°C
100
50
550
650
725
200
325
400
µV
µV
µV
µV
µV
µV
●
●
–40°C to 85°C
V
Match Channel-to-Channel (Note 5) LTC6241 S8
OS
●
●
0°C to 70°C
–40°C to 85°C
LTC6242 GN
0°C to 70°C
–40°C to 85°C
60
225
325
400
µV
µV
µV
●
●
LTC6241 DD, LTC6242 DHC
0°C to 70°C
–40°C to 85°C
150
650
700
750
µV
µV
µV
●
●
●
●
●
●
●
TC V
Input Offset Voltage Drift (Note 6)
Input Bias Current (Notes 4, 7)
0.7
0.5
2.5
µV/°C
OS
I
LTC6241, LTC6242
LTC6240
pA
pA
pA
pA
pA
pA
pA
pA
B
75
1
75
0.5
0.2
0.2
I
OS
Input Offset Current (Notes 4, 7)
LTC6241, LTC6242
LTC6240
75
1
75
Input Noise Voltage
0.1Hz to 10Hz
f = 1kHz
550
7
nV
P-P
e
n
Input Noise Voltage Density
Input Noise Current Density (Note 8)
Input Resistance
Input Capacitance
Differential Mode
Common Mode
10
nV/√Hz
fA/√Hz
Ω
i
0.56
n
12
R
Common Mode
f = 100kHz
10
IN
C
IN
3.5
3
pF
pF
●
●
V
Input Voltage Range
Common Mode Rejection
CMRR Match
Channel-to-Channel (Note 5)
Guaranteed by CMRR
–5
83
3.5
V
dB
CM
CMRR
–5V ≤ V ≤ 3.5V
105
95
CM
76
dB
●
A
VOL
Large Signal Voltage Gain
V = –3.5V to 3.5V
O
R = 10k
775
600
500
2700
V/mV
V/mV
V/mV
L
●
●
0°C to 70°C
–40°C to 85°C
R = 1k
150
90
75
360
V/mV
V/mV
V/mV
L
●
●
0°C to 70°C
–40°C to 85°C
●
●
●
V
OL
Output Voltage Swing Low (Note 9)
No Load
15
45
360
30
75
550
mV
mV
mV
I
I
= 1mA
SINK
= 10mA
SINK
624012fc
7
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS (LTC6240HVC/I, LTC6241HVC/I, LTC6242HVC/I) The ● denotes the
specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C. VS = 5V, 0V, VCM = 0V
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
●
●
V
OH
Output Voltage Swing High (Note 9)
No Load
15
45
360
30
75
550
mV
mV
mV
I
I
= 1mA
SOURCE
= 10mA
SOURCE
●
PSRR
Power Supply Rejection
PSRR Match
Channel-to-Channel (Note 5)
Minimum Supply Voltage (Note 10)
Short-Circuit Current
Supply Current per Amplifier
V = 2.8V to 11V, V = 0.2V
85
110
106
dB
S
CM
●
●
●
82
2.8
15
dB
V
mA
mA
mA
mA
I
I
35
2.5
SC
S
LTC6241, LTC6242
0°C to 70°C
–40°C to 85°C
3.2
3.3
3.7
●
●
LTC6240
0°C to 70°C
–40°C to 85°C
2.7
3.3
3.4
3.8
mA
mA
mA
●
●
●
●
●
GBW
SR
FPBW
Gain Bandwidth Product
Slew Rate (Note 11)
Full Power Bandwidth (Note 12)
Settling Time
Frequency = 20kHz, R = 1kΩ
13
5.5
0.58
18
10
1.06
900
MHz
V/µs
MHz
ns
L
A = –2, R = 1kΩ
V
L
V
= 3V , R = 1kΩ
OUT
P-P
L
t
s
V = 2V, A = –1, R = 1kΩ, 0.1%
STEP V L
(LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH) The ● denotes the specifications which apply from –40°C
to 125°C, otherwise specifications are at TA = 25°C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage (Note 4)
LTC6241 S8
40
125
400
µV
µV
OS
●
●
●
●
LTC6242 GN
LTC6240
50
50
40
50
150
400
µV
µV
175
450
µV
µV
V
OS
Match Channel-to-Channel (Note 5) LTC6241 S8
160
400
µV
µV
LTC6242 GN
185
400
µV
µV
●
●
TC V
Input Offset Voltage Drift (Note 6)
Input Bias Current (Notes 4, 7)
0.7
0.2
2.5
µV/°C
OS
I
B
LTC6241, LTC6242
LTC6240
pA
nA
●
●
●
1.5
0.2
0.2
0.2
1
2.5
pA
nA
I
Input Offset Current (Notes 4, 7)
LTC6241, LTC6242
LTC6240
pA
pA
OS
150
1
750
pA
pA
●
●
●
V
Input Voltage Range
Guaranteed by CMRR
0
3.5
V
CM
CMRR
Common Mode Rejection
0V ≤ V ≤ 3.5V
78
dB
CM
CMRR Match
●
●
●
Channel-to-Channel (Note 5)
74
dB
A
VOL
Large Signal Voltage Gain
V = 1V to 4V
O
R = 10k to V /2
425
200
1600
215
V/mV
V/mV
L
S
V = 1.5V to 3.5V
O
R = 1k to V /2
90
40
V/mV
V/mV
L
S
624012fc
8
LTC6240/LTC6241/LTC6242
(LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH)
ELECTRICAL CHARACTERISTICS
unless otherwise noted.
The ● denotes the specifications which apply from –40°C to 125°C, otherwise specifications are at TA = 25°C. VS = 5V, 0V, VCM = 2.5V
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
●
●
V
V
Output Voltage Swing Low (Note 9)
No Load
SINK
SINK
30
85
mV
mV
mV
OL
I
I
= 1mA
= 5mA
325
●
●
●
Output Voltage Swing High (Note 9)
No Load
SOURCE
SOURCE
30
85
325
mV
mV
mV
OH
I
I
= 1mA
= 5mA
●
PSRR
Power Supply Rejection
V = 2.8V to 6V, V = 0.2V
78
dB
S
CM
PSRR Match
●
●
●
Channel-to-Channel (Note 5)
74
2.8
15
dB
V
Minimum Supply Voltage (Note 10)
Short-Circuit Current
I
I
mA
SC
Supply Current per Amplifier
LTC6241, LTC6242
LTC6240
1.8
2
2.2
2.4
mA
mA
S
●
2.4
2.8
mA
mA
●
●
●
●
GBW
SR
Gain Bandwidth Product
Slew Rate (Note 11)
Frequency = 20kHz, R = 1kΩ
12
4.5
MHz
V/µs
MHz
L
A = –2, R = 1kΩ
V
L
FPBW
Full Power Bandwidth (Note 12)
V
= 3V , R = 1kΩ
0.48
OUT
P-P
L
(LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH) The ● denotes the specifications which apply from –40°C
to 125°C, otherwise specifications are at TA = 25°C. VS = 3V, 0V, VCM = 1.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage (Note 4)
LTC6241 S8
40
175
400
µV
µV
OS
●
●
●
●
LTC6242 GN
LTC6240
60
50
40
60
200
400
µV
µV
200
450
µV
µV
V
Match Channel-to-Channel (Note 5) LTC6241 S8
200
400
µV
µV
OS
LTC6242 GN
225
400
µV
µV
●
●
TC V
Input Offset Voltage Drift (Note 6)
Input Bias Current (Notes 4, 7)
0.7
0.2
2.5
µV/°C
OS
I
LTC6241, LTC6242
LTC6240
pA
nA
B
●
●
●
1.5
0.2
0.2
0.2
1
2.5
pA
nA
I
OS
Input Offset Current (Notes 4, 7)
LTC6241, LTC6242
LTC6240
pA
pA
150
1
750
pA
pA
●
●
●
V
CM
Input Voltage Range
Guaranteed by CMRR
0
1.5
V
CMRR
Common Mode Rejection
0V ≤ V ≤ 1.5V
75
dB
CM
CMRR Match
●
●
Channel-to-Channel (Note 5)
74
dB
A
VOL
Large Signal Voltage Gain
V = 1V to 2V
O
R = 10k to V /2
140
65
600
V/mV
V/mV
L
S
624012fc
9
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS (LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH)
The ● denotes the specifications which apply from –40°C to 125°C, otherwise specifications are at TA = 25°C. VS = 3V, 0V, VCM = 1.5V
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
●
V
Output Voltage Swing Low (Note 9)
No Load
SINK
30
mV
mV
OL
OH
I
= 1mA
130
●
●
V
Output Voltage Swing High (Note 9)
No Load
= 1mA
30
130
mV
mV
I
SOURCE
●
PSRR
Power Supply Rejection
V = 2.8V to 6V, V = 0.2V
78
dB
S
CM
PSRR Match Channel-to-Channel
(Note 5)
●
●
●
74
2.8
2.5
dB
V
Minimum Supply Voltage (Note 10)
Short-Circuit Current
I
I
mA
SC
S
Supply Current per Amplifier
LTC6241, LTC6242
LTC6240
1.4
1.5
1.7
1.9
mA
mA
●
1.9
2.1
mA
mA
●
●
GBW
Gain Bandwidth Product
Frequency = 20kHz, R = 1kΩ
10
MHz
L
(LTC6240HVH/LTC6241HVH/LTC6242HVH) The ● denotes the specifications which apply from –40°C to 125°C, otherwise specifications
are at TA = 25°C. VS = 5V, VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage (Note 4)
LTC6241 S8
50
175
400
µV
µV
OS
●
●
●
●
LTC6242 GN
LTC6240
60
60
50
60
200
400
µV
µV
250
450
µV
µV
V
Match Channel-to-Channel (Note 5) LTC6241 S8
200
400
µV
µV
OS
LTC6242 GN
225
400
µV
µV
●
●
TC V
Input Offset Voltage Drift (Note 6)
Input Bias Current (Notes 4, 7)
0.7
0.5
2.5
µV/°C
OS
I
LTC6241, LTC6242
LTC6240
pA
nA
B
●
●
●
1.5
0.5
0.2
0.2
1
2.5
pA
nA
I
Input Offset Current (Notes 4, 7)
LTC6241, LTC6242
LTC6240
pA
pA
OS
150
1
750
pA
pA
●
●
●
V
Input Voltage Range
Guaranteed by CMRR
–5
80
3.5
V
CM
CMRR
Common Mode Rejection
–5V ≤ V ≤ 3.5V
dB
CM
CMRR Match
Channel-to-Channel (Note 5)
●
76
dB
A
VOL
Large Signal Voltage Gain
V = –3.5V to 3.5V
O
L
R = 10k
775
350
2700
360
V/mV
V/mV
●
●
R = 1k
L
150
60
V/mV
V/mV
624012fc
10
LTC6240/LTC6241/LTC6242
(LTC6240HVH/LTC6241HVH/LTC6242HVH) The ● denotes the specifications
ELECTRICAL CHARACTERISTICS
which apply from –40°C to 125°C, otherwise specifications are at TA = 25°C. VS = 5V, VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
●
●
V
V
Output Voltage Swing Low (Note 9)
No Load
30
85
mV
mV
mV
OL
I
I
= 1mA
SINK
SINK
= 10mA
600
●
●
●
Output Voltage Swing High (Note 9)
Power Supply Rejection
No Load
30
85
600
mV
mV
mV
OH
I
I
= 1mA
SOURCE
SOURCE
= 10mA
●
PSRR
V = 2.8V to 11V, V = 0.2V
S
83
dB
CM
PSRR Match
●
●
●
Channel-to-Channel (Note 5)
82
2.8
15
dB
V
Minimum Supply Voltage (Note 10)
Short-Circuit Current
I
I
mA
SC
Supply Current per Amplifier
LTC6241, LTC6242
LTC6240
2.5
2.7
3.2
3.7
mA
mA
S
●
3.3
3.8
mA
mA
●
●
●
●
GBW
SR
Gain Bandwidth Product
Slew Rate (Note 11)
Frequency = 20kHz, R = 1kΩ
12
5
MHz
V/µs
MHz
L
A = –2, R = 1kΩ
V
L
FPBW
Full Power Bandwidth (Note 12)
V
= 3V , R = 1kΩ
0.53
OUT
P-P
L
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
and PSRR are measured in µV/V on the matched amplifiers. The difference
is calculated between the matching sides in µV/V. The result is converted
to dB.
Note 6: This parameter is not 100% tested.
Note 2: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 7: Bias current at T = 25°C is 100% tested and guaranteed for the
A
LTC6240 in the S8 package. The LTC6240S5, LTC6241 and LTC6242 are
expected to achieve the same performance as the LTC6240S8. All parts are
guaranteed to meet specifications over temperature.
1/2
Note 3: The LTC6240C/LTC6240HVC/LTC6241C/LTC6241HVC, LTC6242C/
LTC6242HVC are guaranteed to meet specified performance from 0°C to
70°C. They are designed, characterized and expected to meet specified
performance from –40°C to 85°C, but are not tested or QA sampled at
these temperatures. The LTC6240I/LTC6240HVI, LTC6241I/LTC6241HVI,
LTC6242I/LTC6242HVI are guaranteed to meet specified performance
from –40°C to 85°C. All versions of the LTC6240H/LTC6241H/LTC6242H
are guaranteed to meet specified performance
Note 8: Current noise is calculated from the formula: i = (2qI )
n
B
–19
where q = 1.6 × 10 coulomb. The noise of source resistors up to
50GΩ dominates the contribution of current noise. See also Typical
Characteristics curve Noise Current vs Frequency.
Note 9: Output voltage swings are measured between the output and
power supply rails.
Note 10: Minimum supply voltage is guaranteed by the power supply
rejection ratio test.
from –40°C to 125°C.
Note 4: ESD (Electrostatic Discharge) sensitive device. ESD protection
devices are used extensively internal to the LTC6240/LTC6241/LTC6242;
however, high electrostatic discharge can damage or degrade the device.
Use proper ESD handling precautions.
Note 5: Matching parameters are the difference between the two amplifiers
A and D and between B and C of the LTC6242; between the two amplifiers
of the LTC6241. CMRR and PSRR match are defined as follows: CMRR
Note 11: Slew rate is measured in a gain of –2 with R = 1k and R =
F
G
500Ω. On the LTC6240/LTC6241/LTC6242, V = 2.5V, V is 1V and
S
IN
V
slew rate is measured between –1V and +1V. On the LTC6240HV/
OUT
LTC6241HV/LTC6242HV, V is 2V and V
slew rate is measured
IN
OUT
between –2V and +2V.
Note 12: Full-power bandwidth is calculated from the slew rate:
FPBW = SR/πV
.
P-P
624012fc
11
LTC6240/LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
V
OS Temperature Coefficient
VOS Distribution LTC6241
VOS Distribution LTC6241
Distribution LTC6241
120
100
80
60
40
20
0
90
80
70
60
50
40
30
20
10
16
14
12
10
8
V
= 2.5V
V
=
2.5V
V = 2.5V
S
S
S
DD PACKAGE
SO-8 PACKAGE
2 LOTS
–55°C TO 125°C
6
4
2
0
0
–350 –250 –150 –50 50 150 250 350
–70 –50 –30 –10 10
30
50
70
–1.0 –0.6 –0.2 0.2 0.6 1.0 1.4 1.8
INPUT OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE (µV)
DISTRIBUTION (µV/°C)
6241 G02
6241 G01
6241 G03
VOS Temperature Coefficient
Distribution LTC6240
VOS Distribution LTC6240
Supply Current vs Supply Voltage
35
30
25
20
15
10
5
18
16
14
12
10
8
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
S
=
2.5V
V
V
= 5V, 0
= 2.5V
S
CM
2 LOTS
T
= 25°C
A
–40°C TO 125°C
SO-8 AND SOT23
PACKAGES
T
= –55°C
A
T
= 125°C
A
6
4
2
0
0
8
12
0
2
4
6
10
–110 –90 –70 –50 –30 –10 10 30 50 70
–0.6 –0.2 0.2
0.6
1.0
1.4
1.8
TOTAL SUPPLY VOLTAGE (V)
INPUT OFFSET VOLTAGE (µV)
DISTRIBUTION (µV/°C)
6241 G43
6241 G44
6241 G04
Offset Voltage vs Input Common
Mode Voltage
Input Bias Current vs Common
Mode Voltage
Input Bias Current vs
Common Mode Voltage
700
300
250
200
150
100
50
1000
100
10
V
= 5V, 0V
V
= 5V, 0V
V
= 5V, 0V
S
S
S
600
500
400
300
200
100
0
T
= 125°C
A
T
= 125°C
= 25°C
A
T
= 25°C
A
T
T
= 125°C
A
A
0
–50
–100
–150
–200
–250
–300
T
= –55°C
T
= 85°C
A
A
–100
–200
–300
–400
1
T
= 85°C
A
T
= 25°C
A
0.1
–0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
–0.8 –0.6 –0.4 –0.2
0
0.2 0.4 0.6 0.8 1.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
COMMON MODE VOLTAGE (V)
COMMON MODE VOLTAGE (V)
INPUT COMMON MODE VOLTAGE (V)
6241 G07
6241 G06
6241 G05
624012fc
12
LTC6240/LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Output Saturation Voltage vs
Load Current (Output Low)
Output Saturation Voltage vs
Load Current (Output High)
Input Bias Current vs Temperature
10
1
10
1
1000
100
10
V
= 5V, 0V
V = 5V, 0V
S
V
= V /2
S
S
CM
T
= 25°C
A
T
= 25°C
A
V
= 10V
S
T
= 125°C
A
T
= 125°C
A
V
= 5V
S
0.1
T
= –55°C
A
T
= –55°C
A
0.1
1
0.01
0.001
0.1
0.01
25 35 45 55 65 75 85 95 105 115 125
0.1
1
10
100
0.1
1
10
100
TEMPERATURE (°C)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
6241 G08
6241 G09
6241 G10
Gain Bandwidth and Phase
Margin vs Supply Voltage
Gain Bandwidth and Phase
Margin vs Temperature
Open Loop Gain vs Frequency
70
70
60
50
40
30
80
70
60
50
40
30
20
10
0
120
T
= 25°C
= 5pF
= 1k
C
= 5pF
= 1k
C
R
V
= 5pF
L
A
L
L
L
L
PHASE
C
V
=
5V
= 1k
100
80
R
S
L
60
50
40
R
= V /2
CM
S
PHASE MARGIN
60
PHASE MARGIN
V
= 5V
S
V
=
1.5V
GAIN
40
S
V
=
1.5V
5V
S
40
30
20
10
0
20
30
20
10
0
0
V
=
S
V
=
5V
–20
–40
–60
–80
S
GAIN BANDWIDTH
V =
1.5V
S
GAIN BANDWIDTH
V
=
1.5V
S
–10
–20
0
2
4
6
8
10
12
–55 –35 –15
5
25 45 65 85 105 125
10k
100k
1M
FREQUENCY (Hz)
10M
100M
TOTAL SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
6241 G14
6241 G12
6241 G13
Common Mode Rejection Ratio vs
Frequency
Slew Rate vs Temperature
Output Impedance vs Frequency
20
18
16
14
12
10
8
10k
100
90
80
70
60
50
40
30
20
10
0
T
= 25°C
= 2.5V
T
= 25°C
= 2.5V
A
= –2
A
S
A
S
V
F
V
V
R
= 1k, R = 500Ω
G
CONDITIONS: SEE NOTE 12
1k
100
10
V
=
S
5V FALLING
5V RISING
S
A
= 10
V
A
= 2
V
V
=
=
2.5V FALLING
2.5V RISING
S
V
=
1
A
= 1
V
V
S
0.10
0.01
6
4
–10
–55 –35 –15
5
25 45 65 85 105 125
10k
100k
1M
10M
100M
10k
100k
1M
10M
TEMPERATURE (°C)
FREQUENCY (Hz)
FREQUENCY (Hz)
6241 G15
6241 G17
6241 G16
624012fc
13
LTC6240/LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Power Supply Rejection Ratio vs
Frequency
Input Capacitance vs Frequency
Channel Separation vs Frequency
0
–10
90
80
70
60
50
40
30
20
10
0
16
14
12
10
8
T
= 25°C
T
V
A
= 25°C
V
= 1.5V
A
S
A
S
V
S
V
= 2.5V
=
2.5V
= 1
–20
–30
C
CM
–40
–50
POSITIVE SUPPLY
–60
–70
6
–80
–90
4
NEGATIVE SUPPLY
–100
–110
–120
2
0
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
6241 G19
6241 G18
6241 G20
Output Short Circuit Current vs
Power Supply Voltage
Minimum Supply Voltage
Open Loop Gain
50
40
100
80
120
100
80
60
40
20
0
T
= 25°C
= 3V, 0V
V
= V /2
S
A
S
CM
V
T
= –55°C
A
SINKING
30
60
T
T
= 125°C
A
A
20
40
T
A
= 25°C
A
10
20
R
= 100k
L
T
= 25°C
0
0
A
–10
–20
–30
–40
–50
–20
–40
–60
–80
–100
R
= 10k
L
T
= –55°C
= 125°C
T
= 125°C
A
SOURCING
T
= –55°C
A
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
1
2
3
4
5
6
7
8
9
10
0
0.5
1.0
1.5
2.0
2.5
3.0
POWER SUPPLY VOLTAGE ( V)
TOTAL SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
6241 G22
6241 G21
6241 G23
Open Loop Gain
Open Loop Gain
Offset Voltage vs Output Current
120
100
80
100
80
500
400
T
= 25°C
= 5V, 0V
T
= 25°C
= 5V
V = 5V
S
A
S
A
S
V
V
300
T
= 125°C
A
60
200
40
T
= 25°C
100
A
60
R
= 10k
= 1k
L
R
= 10k
= 1k
L
20
0
40
T
= –55°C
A
–100
–200
–300
–400
–500
R
L
0
R
L
20
–20
–40
–60
0
–20
0
1
2
3
4
5
–5 –4 –3 –2 –1
0
1
2
3
4
5
–50 –40 –30 –20 –10
0
10 20 30 40 50
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
6241 G24
6241 G25
6241 G26
624012fc
14
LTC6240/LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Warm-Up Drift vs Time
Noise Voltage vs Frequency
0.1Hz to 10Hz Voltage Noise
25
20
15
10
5
60
50
40
30
20
10
0
T
= 25°C
T
A
= 25°C
2.5V
= 0V
V
= 5V, 0V
A
S
V
V
=
S
CM
V
S
=
5V
S
V
=
2.5V
V
=
1.5V
0
S
–5
1
10
100
1k
10k
100k
0
5
10 15 20 25 30 35 40 45 50 55 60
FREQUENCY (Hz)
TIME AFTER POWER UP (s)
TIME (1s/DIV)
6241 G27
6241 G28
6241 G11
Series Output Resistance and
Overshoot vs Capacitive Load
Minimum Output Series
Resistance vs Capacitive Load
Noise Current vs Frequency
60
50
40
30
20
10
0
1000
100
10
1000
100
10
75pF
T
V
V
= 25°C
V
=
2.5V
A
S
S
=
2.5V
= 0V
<30% OVERSHOOT
CM
1k
1k
R
–
+
S
C
L
R
= 10Ω
S
R
= 50Ω
S
1
1
V
A
=
= –1
2.5V
S
V
0.1
0.1
10
100
CAPACITIVE LOAD (pF)
1000
100
1k
10k
100k
10µF
10pF 100pF 1000pF 0.01µF 0.1µF 1µF
FREQUENCY (Hz)
CAPACITIVE LOAD
6241 G42
6241 G29
6241 G45
Settling Time vs Output Step
(Non-Inverting)
Settling Time vs Output Step
(Inverting)
Series Output Resistance and
Overshoot vs Capacitive Load
60
50
40
30
20
10
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
2.5
2.0
1.5
1.0
0.5
0
75pF
T
V
A
= 25°C
T
V
A
= 25°C
A
A
S
V
=
5V
=
5V
S
V
1k
= 1
= –1
1k
V
–
+
–
+
500Ω
OUT
V
IN
1k
R
–
+
S
V
V
OUT 1k
IN
1k
C
L
1mV
1mV
1mV
R
= 10Ω
S
10mV
R
= 50Ω
S
1mV
10mV
–4 –3 –2 –1
10mV
10mV
3
V
A
=
= –2
2.5V
S
V
10
100
CAPACITIVE LOAD (pF)
1000
0
1
2
4
–4 –3 –2 –1
0
1
2
3
4
OUTPUT STEP (V)
OUTPUT STEP (V)
6241 G31
6241 G32
6241 G30
624012fc
15
LTC6240/LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Undistorted Output
Signal vs Frequency
Distortion vs Frequency
Distortion vs Frequency
10
9
8
7
6
5
4
3
2
1
–30
–40
–50
–60
–70
–80
–90
–100
–30
–40
–50
–60
–70
–80
–90
–100
V
A
V
=
2.5V
V
A
V
=
5V
S
V
S
V
= 1
= 1
= 2V
= 2V
OUT
P-P
OUT
P-P
A
= –1
V
A
= +2
V
R
= 1k, 2ND
L
R
= 1k, 2ND
L
R
= 1k, 3RD
L
R
= 1k, 3RD
L
T
= 25°C
A
S
V
=
5V
HD , HD < –40dBc
2
3
10k
100k
1M
10M
10k
100k
1M
10M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
6241 G33
6241 G34
6241 G35
Distortion vs Frequency
Distortion vs Frequency
Small Signal Response
–30
–40
–50
–60
–70
–80
–90
–100
–30
–40
–50
–60
–70
–80
–90
–100
V
A
V
=
5V
V
A
V
=
2.5V
= 2V
S
V
S
V
= 2
= 2
= 2V
OUT
P-P
OUT
P-P
0V
R
= 1k, 2ND
L
R
= 1k, 2ND
L
R
= 1k, 3RD
L
R
= 1k, 3RD
1M
L
6241 G38
V
A
=
2.5V
S
V
= 1
R
= ∞
L
10k
100k
1M
10M
10k
100k
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
6241 G37
6241 G36
Large Signal Response
Large Signal Response
Output Overdrive Recovery
0V
V
IN
0V
0V
(1V/DIV)
0V
V
OUT
(2V/DIV)
6241 G39
6241 G40
6241 G41
V
A
=
5V
V
A
= 2.5V
= –1
= 1k
V
A
=
2.5V
500ns/DIV
S
V
L
S
V
L
S
V
L
= 1
= 3
R
= ∞
R
R
= ∞
624012fc
16
LTC6240/LTC6241/LTC6242
U
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APPLICATIO S I FOR ATIO
The amplifier input bias current is the leakage current of
these ESD diodes. This leakage is a function of the tem-
perature and common mode voltage of the amplifier, as
shown in the Typical Performance Curves.
Amplifier Characteristics
Figure 1 is a simplified schematic of the amplifier, which
has a pair of low noise input transistors M1 and M2. A
simple folded cascode Q1, Q2 and R1, R2 allow the input
stage to swing to the negative rail, while performing level
shift to the Differential Drive Generator. Low offset voltage
is accomplished by laser trimming the input stage.
Noise
The LTC6240/LTC6241/LTC6242 exhibit exceptionally
low 1/f noise in the 0.1Hz to 10Hz region. This 550nV
P-P
Capacitor C1 reduces the unity cross frequency and im-
proves the frequency stability without degrading the gain
bandwidth of the amplifier. Capacitor Cm sets the overall
amplifier gain bandwidth. The differential drive generator
supplies signals to transistors M3 and M4 that swing the
output from rail-to-rail.
noise allows these op amps to be used in a wide variety
of high impedance low frequency applications, where
Zero-Drift amplifiers might be inappropriate due to their
charge injection.
Inthefrequencyregionabove1kHztheLTC6240/LTC6241/
LTC6242 also show good noise voltage performance. In
this frequency region, noise can easily be dominated by
the total source resistance of the particular application.
Specifically, these amplifiers exhibit the noise of a 3.1kΩ
resistor, meaning it is desirable to keep the source and
The photo of Figure 2 shows the output response to an
input overdrive with the amplifier connected as a voltage
follower. If the negative going input signal is less than
–
a diode drop below V , no phase inversion occurs. For
–
input signals greater than a diode drop below V , limit the
feedbackresistanceatorbelowthisvalue,i.e.R +R ||R
S
G
FB
current to 3mA with a series resistor R to avoid phase
S
≤ 3.1kΩ. Above this total source impedance, the noise
inversion.
voltage is not dominated by the amplifier.
Noise current can be estimated from the expression i =
ESD
n
–19
√2qI , where q = 1.6 • 10 coulombs. Equating √4kTRΔf
B
TheLTC6240/LTC6241/LTC6242havereverse-biasedESD
protection diodes on all input and outputs as shown in
Figure 1. If these pins are forced beyond either supply,
unlimited current will flow through these diodes. If the
current is transient and limited to one hundred milliamps
or less, no damage to the device will occur.
andR√2qI Δfshowsthatforsourceresistorsbelow50GΩ
B
the amplifier noise is dominated by the source resistance.
See the Typical Characteristics curve Noise Current vs
Frequency.
V
=
DD
+2.5V
+
V
I
TAIL
M3
CM
–
V
+
V
+
V
DESD1
+
DESD2
DESD4
DESD5
V
=
SS
–2.5V
DIFFERENTIAL
DRIVE
GENERATOR
V
O
V
M1
M2
IN
–
V
IN
DESD6
C1
V
OUT
AND V OF FOLLOWER WITH LARGE INPUT OVERDRIVE
IN
–
–
V
DESD3
V
Q1
Q2
BIAS
M4
+2.5V
–
V
+
V
R
S
+
V
OUT
LTC6240
V
IN
R1
R2
–
–
V
6241 F01
–2.5V
6241 F02
Figure 1. Simplified Schematic
Figure 2. Unity Gain Follower Test Circuit
624012fc
17
LTC6240/LTC6241/LTC6242
U
W U U
APPLICATIO S I FOR ATIO
Proprietary design techniques are used to obtain simulta-
neous low 1/f noise and low input capacitance. Low input
capacitance is important when the amplifier is used with
high value source and feedback resistors. High frequency
Half the Noise
The circuit shown in Figure 3 can be used to achieve even
lower noise voltage. By paralleling 4 amplifiers the noise
voltage can be lowered by √4, or half as much noise. The
√ comes about from an RMS summing of uncorrelated
noise sources. This circuit maintains extremely high input
resistance, and has a 250Ω output resistance. For lower
output resistance, a buffer amplifier can be added without
influencing the noise.
noise from the amplifier tail current source, I
in Fig-
TAIL
ure 1, couples through the input capacitance and appears
across these large source and feedback resistors. As an
example, the photodiode amplifier of Figure 15 on the last
page of this data sheet shows the noise results from the
LTC6241 and the results of a competitive CMOS amplifier.
The LTC6241 output is the ideal noise of a 1MΩ resistor
at room temperature, 130nV√Hz.
Stability
The good noise performance of these op amps can be at-
tributedtolargeinputdevicesinthedifferentialpair.Above
several hundred kilohertz, the input capacitance rises and
can cause amplifier stability problems if left unchecked.
+2.5
+
1k
1/4
LTC6242
When the feedback around the op amp is resistive (R ), a
–
F
pole will be created with R , the source resistance, source
F
–2.5
capacitance (R , C ), and the amplifier input capacitance.
S
S
1k
In low gain configurations and with R and R in even
10Ω
F
S
the kilohm range (Figure 4), this pole can create excess
phase shift and possibly oscillation. A small capacitor C
F
+
in parallel with R eliminates this problem.
1k
F
1/4
LTC6242
–
Low Noise Single-Ended Input to Differential Output
Amplifier
V
V
O
IN
1k
The circuit on the first page of the data sheet is a low noise
single-ended input to differential output amplifier, with a
200k input impedance. The very low input bias current
of the LTC6241 allows for these large input and feedback
resistors. The 200k resistors, R1 and R2, along with C1
and C2 set the –3dB bandwidth to 80kHz. Capacitor C3 is
used to cancel effects of input capacitance, while C4 adds
10Ω
10Ω
10Ω
+
1k
1/4
LTC6242
–
1k
C
F
R
F
+
1k
1/4
LTC6242
–
+
C
–
IN
OUTPUT
R
C
S
S
6241 F04
1k
Figure 4. Compensating Input Capacitance
6241 F03
Figure 3. Parallel Amplifier Lowers Noise by 2x
624012fc
18
LTC6240/LTC6241/LTC6242
U
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APPLICATIO S I FOR ATIO
source equal to the input voltage prevents such leakage
problems. The guard ring should extend as far as neces-
sary to shield the high impedance signal from any and
all leakage paths. Figure 6 shows the use of a guard ring
on the LTC6241 in a unity gain configuration. In this case
the guard ring is connected to the output and is shielding
phase lead to compensate the phase lag of the second
amplifier. The op amp’s good input offset voltage match
andlowinputbiascurrentmeansthatthetypicaldifferential
output offset voltage is less than 40µV. A noise spectrum
plot of the differential output is shown in Figure 5.
–
140
the high impedance non-inverting input from V . Figure 7
V
T
=
2.5V
S
A
= 25°C
shows the inverting gain configuration.
120
100
80
60
40
20
0
–3dB BW = 80kHz
A Digitally Programmable AC Difference Amplifier
The LTC6241 configured as a difference amplifier, can
be combined with a programmable gain amplifier (PGA)
to obtain a low noise high speed programmable differ-
ence amplifier. Figure 8 shows the LTC6241 based as a
single-supply AC amplifier. One LTC6241 op amp is used
at the circuit’s input as a standard four resistor difference
0
10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)
6241 F05
LTC6241 S8
+
OUT
Figure 5. Differential Output Noise
NO SOLDER MASK
NO LEAKAGE
CURRENT
OVER THE GUARD RING
–
+
IN
IN
Achieving Low Input Bias Current
R
The DD package is leadless and makes contact to the PCB
beneath the package. Solder flux used during the attach-
ment of the part to the PCB can create leakage current
paths and can degrade the input bias current performance
ofthepart. Allinputsaresusceptiblebecausethebackside
LEAKAGE
CURRENT
–
GUARD
RING
V
LTC6241 F06
–
paddle is connected to V internally. As the input voltage
–
changes or if V changes, a leakage path can be formed
Figure 6. Sample Layout. Unity Gain Configuration, Using Guard
Ring to Shield High Impedance Input from Board Leakage
and alter the observed input bias current. For lowest bias
current,usetheLTC6240/LTC6241intheSO-8andprovide
a guard ring around the inputs that are tied to a potential
near the input voltage.
LTC6241 S8
+
OUT
R
Layout Considerations and a PCB Guard Ring
R
–
InhighsourceimpedanceapplicationssuchaspHprobes,
photodiodes, strain gauges, et cetera, the low input bias
current of these parts requires a clean board layout to
minimize additional leakage current into a high imped-
ance signal node. A mere 100GΩ of PC board resistance
between a 5V supply trace and an input trace adds 50pA
of leakage current, far greater then the input bias cur-
rent of the operational amplifier. A guard ring around the
high-impedance input traces driven by a low-impedance
IN
V
IN
+
IN
GND
–
V
LTC6241 F07
Figure 7. Sample Layout. Inverting Gain Configuration, Using
Guard Ring to Shield High Impedance Input from Board Leakage
624012fc
19
LTC6240/LTC6241/LTC6242
U
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APPLICATIO S I FOR ATIO
+
R3
contribute any significant error to the LT6650 reference
voltage. The LT6650 V voltage has a maximum error
V
G2 G1 G0
0.1µF
REF
C1
8
7
6
5
R1
of 2% with 1% resistors. The upper –3dB frequency of
the amplifier is set by resistor R3 and capacitor C1 and
is limited by the bandwidth of the PGA when operated at
a gain of 64. Capacitor C2 is equal to C1 and is added to
maintain good common mode rejection at high frequency.
The lower –3dB frequency is set by the integrator resistor
R7, capacitor C3, and the gain setting of the LTC6910-2
PGA. This lower –3dB zero frequency is multiplied by the
PGA gain. The rail-to-rail output of the LTC6910-2 PGA
allows for a maximum output peak-to-peak voltage equal
V1
LTC6910-2
OUT AGND IN
–
V
4
+
1
2
3
1/2
LTC6241
V
OUT
–
100Ω
R7
R2
C2
R4
C3
V2
+
V
R1 = R2 = R3 = R4
0.1µF
R5
–
+
1/2
LTC6241
1000pF
to twice the V voltage. At the maximum gain setting of
REF
R6
20k
64, the maximum peak-to-peak difference between inputs
1
5
4
LT6650
V1 and V2 is equal to twice V divided by 64.
V
REF
REF
2
1µF
1µF
Example Design: Design a programmable gain AC differ-
enceamplifier,withabandwidthofatleast10Hzto100kHz,
an input impedance equal to or greater than 100kΩ, and
an output DC reference equal to 1V.
1k
3
+
V
DIGITAL INPUTS GAIN
G2 G1 GO
V
V
= (V1 – V2) GAIN + V
REF
OUT
a. Select input resistors R1, R2, R3 and R4 equal to
100k.
R5
R6
⎛
⎞
⎠
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
= 0.4•
+ 1
⎟
REF
⎜
⎝
–1
–2
R5 =10k • 5• V – 2 R6 = 20k
(
)
REF
–4
b. If the upper –3dB frequency is 100kHz then C1 = 1/(2π
• R2 • f3dB) = 1/(6.28 • 100kΩ • 100kHz) = 15pF (to
the nearest 5% value) and C2 = C1 = 15pF.
–3d BANDWIDTH =
1
f
– f
LOW
(
)
HIGH
–8
–16
–32
–64
GAIN
f
=
f
=
HIGH
LOW
2• π •R3•C1
2 • π •R7 •C3
6241 F08
c. Select R7 equal to one 1M and set the lower –3dB
frequency to 10Hz at the highest PGA gain of 64, then
C3 = Gain/(2π • R7 • f3dB) = 64/(6.28 • 100kΩ • 10Hz)
= 1uF. Lower gains settings will give a lower f3dB.
Figure 8. Wideband Difference Amplifier with High
Input Impedance and Digitally Programmable Gain
amplifier. The low bias current and current noise of the
LTC6241allowtheuseofhighvaluedinputresistors, 100k
or greater. Resistors R1, R2, R3 and R4 are equal and the
gain of the difference amplifier is one. An LTC6910-2 PGA
amplifies the difference amplifier output with inverting
gains of –1, –2, –4, –8, –16, –32 and –64. The second
LTC6241 op amp is used as an integrator to set the DC
d. Calculate the value of R5 to set the LT6650 reference
equal to 1V;
V
= 0.4(R5/R6 + 1), so R5 = R6(2.5V
– 1). For
REF
REF
R6 = 20kΩ, R5 = 30kΩ
With V = 1V the maximum input difference voltage
REF
output voltage equal to the LT6650 reference voltage V
.
REF
is equal to 2V/64 = 31.2mV.
The integrator drives the PGA analog ground to provide
a feedback loop, in addition to blocking any DC voltage
through the PGA. The reference voltage of the LT6650
40nVpp Noise, 0.05µV/°C Drift, Chopped FET
Amplifier
+
can be set to a voltage from 400mV to V – 350mV with
Figure9’scircuitcombinesthe 5Vrail-to-railperformance
oftheLTC6241HVwithapairofextremelylownoiseJFETs
configured in a chopper based carrier modulation scheme
resistors R5 and R6. If R6 is 20k or less, the error due
to the LT6650 op amp bias current is negligible. The low
voltage offset and drift of the LTC6241 integrator will not
624012fc
20
LTC6240/LTC6241/LTC6242
U
W U U
APPLICATIO S I FOR ATIO
to achieve an extraordinarily low noise and low DC drift.
The performance of this circuit is suited for the demand-
ing transducer signal conditioning situations such as high
resolution scales and magnetic search coils.
with the input chopper, proper amplitude and polarity
information is presented to A2, the DC output amplifier.
This stage integrates the square wave into a DC voltage,
providing the output. The output is divided down (R2 and
R1) and fed back to the input chopper where it serves as
a zero signal reference. Gain, in this case 1000, is set by
the R1-R2 ratio. Because A1 is AC coupled, its DC offset
and drift do not affect the overall circuit offset, resulting
in the extremely low offset and drift noted. The JFETs
have an input RC damper that minimizes offset voltage
contribution due to parasitic switch behavior, resulting in
the 1µV offset specification.
The LTC1799’s output is divided down to form a 2-phase
925Hz square wave clock. This frequency, harmonically
unrelatedto60Hz,providesexcellentimmunitytoharmonic
beating or mixing effects which could cause instabilities.
S1 and S2 receive complementary drive, causing A1 to
see a chopped version of the input voltage. A1’s square
wave output is synchronously demodulated by S3 and
S4. Because these switches are synchronously driven
5V
–5V
+
–
TO LTC201 V PIN
TO LTC201 V PIN
1µF
1µF
+
5V
5V
18.5kHz
+
V
74C90 ÷ 10
74C74 ÷ 2
DIV
OUT
5V
LTC1799
R
SET
Q
Q
925Hz
54.2k*
TO
Ø1
TO
Ø2
5V
Ø1
POINTS POINTS
8
898Ω**
898Ω**
30.1Ω
6
7
INPUT
Ø2
S1
S2
0.01µF
1µF
1
–
LSK389
1µF
11
10
A1
3
2
9
LTC6241HV
S3
S4
240k
499Ω**
–5V
Ø2
–
+
10M
10k
A2
OUTPUT
LTC6241HV
14
15
16
Ø1
+
R2
10k
1µF
* = 0.1% METAL FILM RESISTOR
** = 1% METAL FILM RESISTOR
NOISE = 40nV 0.1Hz TO 10Hz
P-P
R1
OFFSET = 1µV
DRIFT = 0.05µV/°C
R2
10Ω
= LTC201 QUAD
=
+1
GAIN
10
= LSK389
= LINEAR INTEGRATED SYSTEMS
FREMONT, CA
9
OPEN-LOOP GAIN = 10
= 500pA
I
6241 F09
BIAS
Figure 9. Ultra Low Noise Chopper Amplifier
624012fc
21
LTC6240/LTC6241/LTC6242
U
W U U
APPLICATIO S I FOR ATIO
Thenoisemeasuredovera50secondinterval,inFigure10,
is 40nV in a 0.1Hz to 10Hz bandwidth.This low noise is at-
tributed to the input JFET’s die size and current density.
by the sensor is forced across the feedback capacitor
by the op amp action. Because the feedback capacitor
is 100 times smaller than the sensor, it will be forced to
100 times what would have been the sensor’s open circuit
voltage. So the circuit gain is 100. The benefit of this ap-
proach is that the signal gain of the circuit is independent
of any cable capacitance introduced between the sensor
and the amplifier. Hence this circuit is favored for remote
accelerometerswherethecablelengthmayvary.Difficulties
with the circuit are inaccuracy of the gain setting with the
small capacitor, and low frequency cutoff due to the bias
resistor working into the small feedback capacitor.
VERT = 20nV/DIV
HORIZ = 5s/DIV
6241 F10
Figure 12 shows a non-inverting amplifier approach. This
approach has many advantages. First of all, the gain is set
accurately with resistors rather than with a small capaci-
tor. Second, the low frequency cutoff is dictated by the
bias resistor working into the large 770pF sensor, rather
than into a small feedback capacitor, for lower frequency
response. Third, the non-inverting topology can be paral-
leled and summed (as shown) for scalable reductions in
voltage noise. The only drawback to this circuit is that the
parasiticcapacitanceattheinputreducesthegainslightly.
This circuit is favored in cases where parasitic input
capacitances such as traces and cables will be relatively
small and invariant.
Figure 10. Noise in a 0.1Hz to 10Hz Bandwidth
Low Noise Shock Sensor Amplifiers
Figures 11 and 12 show the amplifiers realizing two dif-
ferent approaches to amplifying signals from a capacitive
sensor. The sensor in both cases is a 770pF piezoelectric
shocksensoraccelerometer,whichgenerateschargeunder
physical acceleration.
Figure11showstheclassical“chargeamplifier”approach.
TheLTC6240isintheinvertingconfigurationsothesensor
looks into a virtual ground. All of the charge generated
+
V
S
+
1/2
LTC6241HV
SHOCK SENSOR
MURATA-ERIE
PKGS-00LD
770pF
–
+
1k
1k
LTC6240
100Ω
10k
SHOCK SENSOR
MURATA-ERIE
PKGS-00LD
770pF
V
OUT
–
C
V
= 110mV/g
OUT
f
1G
7.7pF
+
BIAS RESISTOR
1/2
VISHAY-TECHNO
CRHV2512AF1007G
(OR EQUIVALENT)
LTC6241HV
MAIN
R
GAIN-SETTING
ELEMENT IS A
CAPACITOR
f
–
V
V
= 110mV/g
CABLE HAS
UNKNOWN C
1G
OUT
=
S
1.4V to 5.5V
–
V
S
BW = 0.2Hz to 10kHz
BIAS RESISTOR
VISHAY-TECHNO
CRHV2512AF1007G
(OR EQUIVALENT)
100Ω
10k
6241 F11
6241 F12
Figure 11. Classical Inverting Charge Amplifier
Figure 12. Low Noise Non-Inverting Shock Sensor Amplifier
624012fc
22
LTC6240/LTC6241/LTC6242
U
W U U
APPLICATIO S I FOR ATIO
1M Transimpedance Amplifier with 43nV/√Hz
Output Noise
By achieving an output swing of 50V before attenuation,
the circuit provides an output swing to 5V after attenu-
ation. The 10M resistor sets the gain of the TIA stage
and has a noise density of 400nV/√Hz. After attenuation,
the effective TIA gain drops to 1M while the noise floor
drops to 40nV/√Hz, which clearly dominates the observed
43nV/√Hz.Notetheadditionalbenefitthattheoffsetvoltage
of the op amp is divided by 10. Worst case output offset
for this circuit is 150µV over temperature.
In a normal 1M transimpedance amplifier, like that shown
onthebackpageofthisdatasheet,theoutputnoisedensity
must be at least 130nV/√Hz at room temperature. This is
trueevenshouldtheopampbeperfectlynoiseless,because
the 1M resistor provides 130nV/√Hz of voltage noise at
room temperature independently of the op amp.
ThecircuitofFigure13providesanoveralltransimpedance
gain of 1MΩ, but it has an output noise density of only
43nV/√Hz,about1/3ofthenormaltransimpedanceampli-
fier. It does this by taking a higher initial transimpedance
gain of 10M and then attenuating by a factor of 10. The
transistor section provides voltage gain and works on a
54V supply voltage to guarantee adequate output swing.
Reference Buffer
Figure 14 shows the LTC6240 being utilized as a buffer
in conjunction with the LT1019 reference. The passive
R-C filter attenuates the reference noise and the LTC6240
provides a low noise buffer, resulting in an output noise
of 8nV/√Hz.
54V
33k
0.3pF
MPSA06
10M
1%
5V
10M GAIN
(10V/µA)
+
3pF
PHOTODIODE
MPSA06
9.09k
LTC6240HV
10k
1%
–
1/4W
–1.5V
V
OUT
1M GAIN
10k
2.4k 43k
–5V
(1V/µA)
1k
1%
100pF
1k
–5V
6241 F13
Figure 13. 1M Transimpedance Amplifier with 43nV/√Hz Output Noise
5V
1M
180nV/√Hz
LT1019-2.5
+
0.2Ω
8nV/√Hz
1µF
LTC6240HV
V
OUT
10µF
CERAMIC
OR FILM
–
–5V
6241 F14
Figure 14. Low Noise Reference Buffer
624012fc
23
LTC6240/LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
0.65 0.05
3.50 0.05
2.20 0.05 (2 SIDES)
1.65 0.05
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
4.40 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
0.40 0.10
5.00 0.10
(2 SIDES)
9
16
R = 0.20
TYP
3.00 0.10 1.65 0.10
(2 SIDES)
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PIN 1
NOTCH
(DHC16) DFN 1103
8
1
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
4.40 0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005
.254 MIN
.150 – .165
.0165 .0015
.0250 BSC
.189 – .196*
(4.801 – 4.978)
RECOMMENDED SOLDER PAD LAYOUT
.009
(0.229)
REF
.015 .004
(0.38 0.10)
16 15 14 13 12 11 10 9
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 0204
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
1
2
3
4
5
6
7
8
3. DRAWING NOT TO SCALE
624012fc
24
LTC6240/LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
0.38 0.10
TYP
5
8
0.675 0.05
3.5 0.05
2.15 0.05 (2 SIDES)
1.65 0.05
3.00 0.10
(4 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
(DD8) DFN 1203
4
1
0.25 0.05
0.75 0.05
0.200 REF
0.25 0.05
0.50 BSC
0.50
BSC
2.38 0.05
(2 SIDES)
2.38 0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
624012fc
25
LTC6240/LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
0.62
MAX
0.95
REF
2.90 BSC
(NOTE 4)
1.22 REF
1.50 – 1.75
(NOTE 4)
2.80 BSC
1.4 MIN
3.85 MAX 2.62 REF
PIN ONE
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
NOTE:
S5 TSOT-23 0302 REV B
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
624012fc
26
LTC6240/LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
.045 .005
NOTE 3
.050 BSC
7
5
8
6
.245
MIN
.160 .005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 .005
TYP
1
3
4
2
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SO8 0303
624012fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC6240/LTC6241/LTC6242
U
TYPICAL APPLICATIO
1MΩ TIA
150kHz 3RD ORDER BUTTERWORTH FILTER
+1.5V
R1
R2
1.69k
R3
2k
C2
+
866Ω
1500pF
1/2
LTC6241
+
1/2
LTC6241
–
C1
1500pF
C3
180pF
R
F
1M
–
SFH213FA
OR EQUIVALENT
(≤4pF)
–1.5V
6241 TA02a
C
F
–1.5V
1pF
Figure 15. Ultralow Noise 1MΩ 150kHz Photodiode Amplifier
LTC6241 Output Noise Spectrum. 1MΩ Resistor Noise
Competition Output Noise Spectrum. Op Amp Noise Dominates;
Performance Compromised
Dominates; Ideal Performance
0V
0V
1kHz
10kHz/DIV
101kHz
1kHz
10kHz/DIV
101kHz
6241 TA02b
6241 TA02c
RELATED PARTS
PART NUMBER
LTC1151
DESCRIPTION
15V Zero-Drift Op Amp
COMMENTS
Dual High Voltage Operation 18V
6nV/√Hz Noise, 15V Operation
2.7 Volt Operation, SOT-23
LT1792
Low Noise Precision JFET Op Amp
Zero-Drift Op Amp
LTC2050
LTC2051/LTC2052
LTC2054/LTC2055
LTC6244
Dual/Quad Zero-Drift Op Amp
Single/Dual Zero-Drift Op Amp
Dual 50MHz Rail-to-Rail Op Amp
Dual/Quad Version of LTC2050 in MS8/GN16 Packages
Micropower Version of the LTC2050/LTC2051 in SOT-23 and DD Packages
100µV V , 1pA I , 40V/µV, Slew Rate
OS(MAX)
BIAS
624012fc
LT 0107 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 2005
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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